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MCZ34701EW/R2 [NXP]

1.5A SWITCHING REGULATOR, 400kHz SWITCHING FREQ-MAX, PDSO32, 0.65 MM PITCH, LEAD FREE, SOIC-32;
MCZ34701EW/R2
型号： MCZ34701EW/R2
厂家： NXP    NXP
描述：

1.5A SWITCHING REGULATOR, 400kHz SWITCHING FREQ-MAX, PDSO32, 0.65 MM PITCH, LEAD FREE, SOIC-32

开关 光电二极管
文件： 总39页 (文件大小：908K)
中文：  中文翻译
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Document Number: MC34701  
Rev 7.0, 8/2007  
Freescale Semiconductor  
Technical Data  
1.5A Switch-Mode Power  
Supply with Linear Regulator  
34701  
The 34701 provides the means to efficiently supply the Freescale  
Power QUICC™ I, II, and other families of Freescale  
microprocessors and DSPs. The 34701 incorporates a high  
performance switching regulator, providing the direct supply for the  
microprocessor’s core, and a low dropout (LDO) linear regulator  
control circuit provides the microprocessor I/O and bus voltage.  
POWER SUPPLY  
The switching regulator is a high-efficiency synchronous buck  
regulator with integrated N-channel power MOSFETs to provide  
protection features and to allow space-efficient, compact design.  
The 34701 incorporates many advanced features; e.g., precisely  
maintained up/down power sequencing, ensuring the proper  
operation and protection of the CPU and power system.  
Features  
EW (Pb-FREE) SUFFIX  
98AARH99137A  
• Operating voltage from 2.8V to 6.0V  
• High-accuracy output voltages  
32-PIN SOICW  
• Fast transient response  
• Switcher output current up to 1.5A  
• Under-voltage lockout and overcurrent protection  
• Enable inputs and programmable watchdog timer  
• Voltage margining via I2C™ bus  
• Reset with programmable power-ON delay  
• Pb-free packaging designated by suffix code EW  
ORDERING INFORMATION  
Temperature  
Package  
Device  
Range (T )  
A
MCZ34701EW/R2  
-40 to 85°C  
32 SOICW  
I2C is a trademark of Philips Corporation.  
2.8 V to 6.0 V Input  
34701  
Other  
Circuits  
VIN2  
VIN1  
VBD  
VBST  
LDRV  
CS  
Adjustable:  
0.8 V to VIN -  
Dropout  
LDO  
LFB  
VDDH (I/Os)  
RT  
ADDR  
MPC8xxx  
SDA  
SCL  
PORESET  
RST  
GND  
Adjustable:  
0.8 V to VIN -  
Dropout  
VBST  
BOOT  
SW  
EN1  
VDDL (Core)  
EN2  
VOUT  
CLKSYN  
PGND  
CLKSEL  
FREQ  
INV  
Optional  
VDDI  
Figure 1. 34701 Simplified Application Diagram  
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,  
as may be required, to permit improvements in the design of its products.  
© Freescale Semiconductor, Inc., 2007. All rights reserved.  
INTERNAL BLOCK DIAGRAM  
INTERNAL BLOCK DIAGRAM  
VIN1  
VIN  
VDDI  
Internal  
VDDI  
Supply  
VDDI  
8.0 V  
VBST  
VBST  
VBST  
Power  
Enable  
-
LDRV  
CS  
V
REF  
+
To Reset  
Control  
VDDI  
Linear  
Regulator  
Control  
VDDI  
VBD  
Q5  
LDO  
Bandgap  
Voltage  
Reference  
Boost  
Control  
V
REF  
I
V
Lim  
REF  
V
REF  
LFB  
VDDI  
LCMP  
Power  
Seq  
VLDO  
EN1  
EN2  
Q4  
Power  
Sequencing  
Power  
Down  
UVLO  
VBST  
VBST  
Voltage Margining  
Watchdog Timer  
Reset  
RST  
VOUT  
Reset  
Control  
BOOT  
Q6  
SysCon  
Current Limit  
VDDI  
POR  
Timer  
VIN2  
(2)  
INV  
LFB  
I2C  
Control  
RT  
Buck  
HS  
Q1  
I2C  
Control  
and  
LS  
Driver  
SysCon  
SoftSt  
Thermal  
Limit  
Buck  
Control  
Logic  
SW  
(2)  
Q2  
ADDR  
I2C  
Interface  
PGND  
(2)  
SDA  
SCL  
To Reset  
Control  
Error  
Amp  
PWM  
Comp  
0.8 V  
Switcher  
Oscillator  
300 kHz  
+
+
-
INV  
-
VOUT  
Ramp  
Gen.  
VOUT  
Power  
Seq  
Q3  
(4)  
GND  
CLKSEL  
CLKSYN  
FREQ  
Figure 2. 34701 Simplified Internal Block Diagram  
34701  
Analog Integrated Circuit Device Data  
2
Freescale Semiconductor  
PIN CONNECTIONS  
PIN CONNECTIONS  
FREQ  
INV  
VOUT  
VIN2  
VIN2  
SW  
1
CLKSYN  
CLKSEL  
RST  
RT  
EN2  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
2
3
4
5
6
EN1  
7
SW  
ADDR  
GND  
GND  
VDD1  
VIN1  
LDRV  
CS  
LDO  
LFB  
LCMP  
8
GND  
GND  
PGND  
PGND  
VBD  
VBST  
BOOT  
SDA  
9
10  
11  
12  
13  
14  
15  
16  
SCL  
Figure 3. Pin Connections  
Table 1. Pin Function Description  
A functional description of each pin can be found in the FUNCTIONAL PIN DESCRIPTION section beginning on page 16.  
Pin  
Pin Name  
Formal Name  
Definition  
1
FREQ  
Oscillator Frequency  
This switcher frequency selection pin can be adjusted by connecting external  
resistor RF to the FREQ pin. The default switching frequency (FREQ pin left open or  
tied to VDDI) is set to 300kHz.  
2
3
INV  
Inverting Input  
Output Voltage  
Buck controller error amplifier inverting input.  
VOUT  
Output voltage of the buck converter. Input pin of the switching regulator power  
sequence control circuit.  
4, 5  
6, 7  
VIN2  
SW  
Input Voltage 2  
Switch  
Buck regulator power input. Drain of the high side power MOSFET.  
Buck regulator switching node. This pin is connected to the inductor.  
Analog ground of the IC, thermal heatsinking.  
8, 9  
GND  
Ground  
24, 25  
10, 11  
12  
PGND  
VBD  
Power Ground  
Boost Drain  
Buck regulator power ground.  
Drain of the internal boost regulator power MOSFET.  
13  
VBST  
Boost Voltage  
Internal boost regulator output voltage. The internal boost regulator provides a 20mA  
output current to supply the drive circuits for the integrated power MOSFETs and the  
external N-channel power MOSFET of the linear regulator. The voltage at the VBST  
pin is 7.75V (nominal).  
14  
15  
16  
17  
18  
19  
BOOT  
SDA  
SCL  
Bootstrap  
Serial Data  
Bootstrap capacitor input.  
I2C bus pin. Serial data.  
Serial Clock  
I2C bus pin. Serial clock.  
LCMP  
LFB  
Linear Compensation  
Linear Feedback  
Linear Regulator  
Linear regulator compensation pin.  
Linear regulator feedback pin.  
LDO  
Input pin of the linear regulator power sequence control circuit.  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
3
PIN CONNECTIONS  
Table 1. Pin Function Description (continued)  
A functional description of each pin can be found in the FUNCTIONAL PIN DESCRIPTION section beginning on page 16.  
Pin  
Pin Name  
Formal Name  
Definition  
20  
CS  
Current Sense  
Current sense pin of the LDO. Over-current protection of the linear regulator external  
power MOSFET. The voltage drop over the LDO current sense resistor RS is sensed  
between the CS and LDO pins. The LDO current limit can be adjusted by selecting  
the proper value of the current sensing resistor RS.  
21  
22  
LDRV  
VIN1  
Linear Drive  
LDO gate drive of the external pass N-channel MOSFET.  
Input Voltage 1  
The input supply pin for the integrated circuit. The internal circuits of the IC are  
supplied through this pin.  
23  
26  
27  
28  
29  
30  
VDDI  
ADDR  
EN1  
EN2  
RT  
Power Supply  
Address  
Internal supply voltage. A ceramic low ESR 1uF 6V X5R or X7R capacitor is  
recommended.  
I2C address selection. This pin can either be left open, tied to VDDI, or grounded  
through a 10kresistor.  
Enable 1  
Enable 1 Input. The combination of the logic state of the Enable 1 and Enable 2  
inputs determines operation mode and type of power sequencing of the IC.  
Enable 2  
Enable 2 Input. The combination of the logic state of the Enable 1 and Enable 2  
inputs determines operation mode and type of power sequencing of the IC.  
Reset Timer  
This pin allows programming of the power-ON reset delay by means of an external  
RC network.  
RST  
Reset Output  
(Active LOW)  
The reset control circuit monitors both the switching regulator and the LDO feedback  
voltages. It is an open drain output and has to be pulled up to some supply voltage  
(e.g., the output of the LDO) by an external resistor.  
31  
32  
CLKSEL  
CLKSYN  
Clock Selection  
This pin sets the CLKSYN pin as either an oscillator output or a synchronization input  
pin. The CLKSEL pin is also used for the I2C address selection.  
Clock Synchronization  
Oscillator output/synchronization input pin.  
34701  
Analog Integrated Circuit Device Data  
4
Freescale Semiconductor  
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
Table 2. Maximum Ratings  
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent  
damage to the device.  
Rating  
Symbol  
Value  
Unit  
ELECTRICAL RATINGS  
Supply Voltage  
V
V
, V  
-0.3 to 7.0  
-1.0 to 7.0  
-0.3 to 8.5  
-0.3 to 8.5  
-0.3 to 9.5  
-0.3 to 7.0  
-0.3 to 7.0  
-0.3 to 7.0  
V
V
V
V
V
V
V
V
V
IN1 IN2  
Switching Node Voltage  
V
SW  
IN(BOOT)  
Buck Regulator Bootstrap Input Voltage (BOOT - SW)  
Boost Regulator Output Voltage  
Boost Regulator Drain Voltage  
RST Drain Voltage  
V
BST  
V
BD  
V
RST  
Enable Pin Voltage at EN1, EN2  
Logic Pin Voltage at SDA, SCL  
V
EN  
V
LOG  
Analog Pin Voltage  
LDO, VOUT, RST  
LDRV, LCMP, CS  
-0.3 to 7.0  
-0.3 to 8.5  
V
OUT  
V
LIN  
Pin Voltage at CLKSEL, ADDR, RT, FREQ, VDDI, CLKSYN, INV, LFB  
-0.3 to 3.6  
V
V
V
LOGIC  
ESD Voltage(1)  
Human Body Model  
Machine Model  
±2000  
±200  
V
ESD  
Notes  
1. ESD1 testing is performed in accordance with the Human Body Model (CZAP=100 pF, RZAP=1500 ), ESD2 testing is performed in  
accordance with the Machine Model (CZAP=200 pF, RZAP=0 ), and the Charge Device Model.  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
5
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
Table 2. Maximum Ratings (continued)  
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent  
damage to the device.  
Rating  
Symbol  
Value  
Unit  
THERMAL RATINGS  
Storage Temperature  
T
-65 to 150  
Note 3  
C  
STG  
Peak Package Reflow Temperature During Reflow(2)  
,
TPPRT  
(3)  
°C  
Maximum Junction Temperature  
T
125  
C  
JMAX  
Thermal Resistance  
R
C/W  
JA  
(5)  
Junction to Ambient (Single Layer)(4)  
,
70  
55  
(5)  
Junction to Ambient (Four Layers)(4)  
,
Thermal Resistance, Junction to Base(6)  
R
18  
C/W  
JB  
Operational Package Temperature (Ambient Temperature)  
Notes  
T
-40 to 85  
°C  
A
2. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may  
cause malfunction or permanent damage to the device.  
3. Freescale’s package reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow  
Temperature and Moisture Sensitivity Levels (MSL),   
Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.  
MC33xxxD enter 33xxx), and review parametrics.  
4. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature,  
ambient temperature, air flow, power dissipation of other components on the board and board thermal resistance.  
5. Per JEDEC JESD51-6 with the board horizontal  
6. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top  
surface of the board near the package.  
34701  
Analog Integrated Circuit Device Data  
6
Freescale Semiconductor  
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. Static Electrical Characteristics  
Characteristics noted under conditions -40°C TA 85C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3V using  
the typical application circuit (see Figure 33), unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
GENERAL  
Operating Voltage Range (VIN1, VIN2)  
Start-up Voltage Threshold (Boost Switching)  
VBST Under-voltage Lockout (VBST rising)  
VBST Under-voltage Lockout Hysteresis  
V
2.8  
–
–
1.6  
–
6.0  
1.8  
6.5  
1.5  
–
V
V
IN  
V
ST  
V
5.5  
0.5  
–
V
BST_UVLO  
BST_UVLO_HYS  
V
–
V
Input DC Supply Current (Normal Operation Mode, Enabled), Unloaded  
Outputs  
I
60  
mA  
IN  
VIN1 Pin Input Supply Current (EN1 = EN2 = 0)  
VIN2 Pin Input Leakage Current (EN1 = EN2 = 0)  
VDDI Internal Supply Voltage  
I
–
–
10  
100  
–
–
–
mA  
A  
V
IN1  
I
IN2  
V
2.9  
–
3.3  
-10  
DDI  
DDI  
VDDI Maximum Output Current (Externally Loaded)  
BUCK CONVERTER  
I
–
mA  
Buck Converter Feedback Voltage(7), (8)  
V
V
INV  
IVOUT = 15mA to 1.5A. Includes Load Regulation Error  
0.784  
–
0.800  
1.0  
–
0.816  
–
Buck Converter Voltage Margining Step Size  
V
%
%
%
%
MVO  
Buck Converter Voltage Margining Highest Positive Value  
Buck Converter Voltage Margining Lowest Negative Value  
V
5.9  
7.9  
MP  
MN  
V
-7.9  
–
-5.9  
Buck Converter Line Regulation(7), (8)  
REG  
LNVO  
VIN1 = VIN2 = 2.8V to 6.0V, IVOUT = 15mA to 1.5A  
-1.0  
-1.0  
–
–
1.0  
1.0  
Buck Converter Load Regulation(7), (8)  
REG  
%
mA  
µA  
LDVO  
VIN1 = VIN2 = 2.8V to 6.0V, IVOUT = 15mA to 1.5A  
VOUT Input Leakage Current  
VOUT = 5.25V  
I
INVOUT  
–
3.5  
–
–
INV Input Leakage Current  
INV = 0.8V  
I
-1.0  
1.0  
ININV  
Notes  
7. Design information only. This parameter is not production tested.  
8. IVOUT refers to load current on output switcher.  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
7
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. Static Electrical Characteristics (continued)  
Characteristics noted under conditions -40°C TA 85C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3V using  
the typical application circuit (see Figure 33), unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
BUCK CONVERTER (CONTINUED)  
High Side Power MOSFET Q1 RDS(ON)(9), (10)  
R
m  
m  
DS(ON)Q1  
DS(ON)Q2  
–
60  
–
ID = 500mA, T = 25°C, VBST = 8.0V  
A
Low Side Power MOSFET Q2 RDS(ON)(9), (10)  
R
–
65  
–
ID = 500mA, T = 25°C, VBST = 8.0V  
A
Buck Converter Peak Current Limit (High Level)  
VOUT Pull-down MOSFET Q3 Current Limit  
I
-4.0  
-2.7  
-1.5  
A
A
LIMH  
I
LIMPQ3  
0.75  
–
2.0  
T
= 25°C, VBST = 8.0V  
A
(10)  
VOUT Pull-down MOSFET Q3 R  
ID = 1.0A, VBST = 8.0V  
R
DS(ON)  
DS(ON)PQ3  
–
150  
–
–
1.9  
190  
–
Thermal Shutdown (VOUT Pull-down MOSFET Q3)(9)  
Thermal Shutdown Hysteresis (9)  
T
170  
10  
°C  
°C  
SD  
T
HYS  
Notes  
9. Design information only. This parameter is not production tested.  
10. ID is the MOSFET drain current.  
34701  
Analog Integrated Circuit Device Data  
8
Freescale Semiconductor  
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. Static Electrical Characteristics (continued)  
Characteristics noted under conditions -40°C TA 85C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3V using  
the typical application circuit (see Figure 33), unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
ERROR AMPLIFIER (BUCK CONVERTER)  
Input Impedance(11)  
R
–
–
–
–
–
500  
150  
80  
–
–
–
–
–
k  
IN  
Output Impedance(11)  
R
OUT  
DC Open Loop Gain(11)  
Gain Bandwidth Product(11)  
Slew Rate(11)  
A
dB  
VOL  
GBW  
35  
MHz  
V/s  
V
200  
v
SR  
Output Voltage – High Level  
V
V
EA_OH  
VIN1 > 3.3V, IOEA = -1.0mA(11), (12)  
–
2.0  
–
Output Voltage – Low Level  
IOEA = -1.0 mA(11), (12)  
V
V
EA_OL  
–
–
0.4  
0.5  
–
–
Oscillator Ramp(11)  
V
SCRAMP  
OSCILLATOR  
CLKSYN Pin (open) Low Level Output Voltage  
IOL = +1.0mA(13)  
V
–
–
0.4  
V
V
OSC_OL  
CLKSYN Pin (open) High Level Output Voltage  
IOH = -1.0mA(14)  
V
VDDI  
OSC_OH  
-0.4V  
–
–
CLKSYN Pin (grounded) Input Voltage Threshold  
CLKSYN Pin Pull-up Resistance  
V
1.2  
60  
–
–
–
2.0  
240  
–
V
k  
V
OSC_IH  
RPU  
Frequency Adjusting Reference Voltage  
BOOST REGULATOR  
V
1.26  
FREQ  
Regulator Output Voltage  
V
V
BST  
IBST = 20mA, VIN1 = VIN2 = 2.8V to 6.0V  
7.3  
–
7.7  
8.3  
Power MOSFET Q5 RDS(ON)(11)  
R
m  
DS(ON)Q5  
CBST  
IBD = 500mA, T = 25°C  
A
650  
1000  
Regulator Recommended Output Capacitor  
–
–
10  
–
–
F  
Regulator Recommended Output Capacitor Maximum ESR  
ESRCBST  
100  
m  
Notes  
11. Design information only. This parameter is not production tested.  
12. IOEA Refers to Error Amplifier Output Current.  
13. IOL Refers to I/O Low Level  
14. IOH Refers to I/O High Level  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
9
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. Static Electrical Characteristics (continued)  
Characteristics noted under conditions -40°C TA 85C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3V using  
the typical application circuit (see Figure 33), unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
LINEAR REGULATOR (LDO)  
LDO Feedback Voltage(16)  
V
V
LFB  
VIN1 = VIN2 = 2.8V to 6.0V, ILDO = 10mA to 1000mA. Includes Load  
Regulation Error  
0.784  
–
0.800  
1.0  
–
0.816  
–
LDO Voltage Margining Step Size  
V
%
%
%
%
MLDO  
LDO Voltage Margining Highest Positive Value  
LDO Voltage Margining Lowest Negative Value  
V
V
5.9  
7.9  
MP  
MN  
-7.9  
–
-5.9  
LDO Line Regulation(16)  
REG  
REG  
V
LNVLDO  
VIN1 = VIN2 = 2.8V to 6.0V, ILDO = 1000mA  
-1.0  
-1.0  
–
–
–
1.0  
1.0  
–
LDO Load Regulation(16)  
ILDO = 10mA to 1000mA  
%
LDVLDO  
LDO Ripple Rejection, Dropout Voltage(16)  
VDO = 1.0V, VRIPPLE = +1.0V p-p  
dB  
LDO_RR  
40  
Sinusoidal, f = 300kHz, ILDO = 500mA(15)  
LDO Maximum Dropout Voltage (VIN - VLDO), using IRL2703(16)  
VLDO = 2.5V, ILDO = 1000mA  
V
mV  
DO  
–
50  
50  
75  
65  
LDO Current Sense Comparator Threshold Voltage (VCS - VLDO)  
LDO Pin Input Current, VLDO = 5.25V  
V
35  
mV  
mA  
A  
CSTH  
I
1.0  
-1.0  
-5.0  
1.9  
–
4.0  
1.0  
-2.0  
LDO  
LFB  
LDO Feedback Input Current (LFB Pin), VLFB = 0.8V  
LDO Drive Output Current (LDRV Pin), VLDRV = 0V  
I
I
I
-3.3  
mA  
A  
LDRV  
CSLK  
CS Pin Input Leakage Current  
VCS = 5.25V  
50  
–
–
200  
2.0  
LDO Pull-down MOSFET Q4 Current Limit  
I
A
LIMQ4  
0.75  
T
= 25°C, VBST = 8.0V (LDO Pin)  
A
LDO Pull-down MOSFET Q4 RDS(ON)  
ID = 1.0A, VBST = 8.0V  
R
DS(ON)Q4  
–
–
–
1.9  
–
LDO Recommended Output Capacitance  
LDO Recommended Output Capacitor ESR  
Thermal Shutdown (LDO Pull-down MOSFET Q4)(15)  
Thermal Shutdown Hysteresis(15)  
C
10  
F  
m  
°C  
LDO  
RLDO  
TSD  
–
5.0  
170  
10  
–
150  
–
190  
–
T
°C  
SDHYS  
Notes  
15. Design information only. This parameter is not production tested.  
16. IDO refers to Load Current on External LDOFET - IRL2703 is the Intersil MOSFET.  
34701  
Analog Integrated Circuit Device Data  
10  
Freescale Semiconductor  
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. Static Electrical Characteristics (continued)  
Characteristics noted under conditions -40°C TA 85C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3V using  
the typical application circuit (see Figure 33), unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
CONTROL AND SUPERVISORY CIRCUITS  
Enable (EN1, EN2) Input Voltage Threshold  
Enable (EN1, EN2) Pull-down Resistance  
RST Low-level Output Voltage, IOL = 5.0mA  
RST Leakage Current, OFF State, Pulled Up to 5.25V  
RST Under-voltage Threshold on VOUT (VOUT/VOUT)(17)  
RST Over-voltage Threshold on VOUT (VOUT/VOUT)(17)  
RST Under-voltage Threshold on VLDO (VLDO/VLDO)(17)  
RST Over-voltage Threshold on VLDO (VLDO/VLDO)(17)  
RST Timer Voltage Threshold  
V
R
1.0  
30  
–
1.5  
55  
–
2.0  
90  
V
k  
V
EN-TH  
EN-PD  
V
0.4  
10  
OL  
ILKG-RST  
–
–
A  
%
V
-14  
0.5  
-12  
4.0  
1.0  
-17  
-1.0  
–
–
-0.5  
14  
OUTITH  
V
–
%
OUTITH  
V
–
-4.0  
12  
%
LDOITH  
V
–
%
LDOITH  
V
1.2  
–
1.5  
-34  
1.0  
100  
47  
V
TH-RT  
RST Timer Source Current (RT pin at 0V)  
RST Timer Leakage Current  
IS-RT  
mA  
A  
mV  
F  
V
I
–
LKG-RT  
RST Timer Saturation Voltage, Reset Timer Current = 300A  
Maximum Recommended Value of the Reset Timer Capacitor  
CLKSEL Threshold Voltage  
V
35  
–
SAT-RT  
C
–
t
V
1.2  
60  
1.2  
60  
150  
–
1.6  
120  
1.6  
120  
170  
10  
2.0  
240  
2.0  
240  
190  
–
THCLKS  
CLKSEL Pull-up Resistance  
R
S
k  
V
PU-CLK  
ADDR Threshold Voltage(17)  
V
THADDR  
PU-ADDR  
ADDR Pull-up Resistance  
R
k  
°C  
°C  
Thermal Shut-down (IC sensor) (17)  
T
LIM  
Thermal Shut-down Hysteresis(17)  
T
LIMHYS  
SDA, SCL PINS I2C BUS (STANDARD)  
Input Threshold Voltage (Pin SCL), Rising Edge(17)  
Input Threshold Voltage (Pin SDA)  
V
1.3  
1.3  
–
–
–
1.7  
1.7  
10  
V
V
LTH  
V
LTH  
SDA, SCL Input Current, Input Voltage = 5.25V (VIN1)  
SDA Low-level Output Voltage, 3.0mA Sink Current  
SDA, SCL Capacitance(17)  
IIN  
1.0  
–
A  
V
V
–
0.4  
10  
OL  
C
–
7.0  
pF  
INPUT  
Notes  
17. Design information only. This parameter is not production tested.  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
11  
ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS  
Characteristics noted under conditions -40°C TA 85C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3V using  
the typical application circuit (see Figures 33), unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
BUCK CONVERTER  
Duty Cycle Range (Normal Operation)(18)  
t
0.0  
–
–
95  
–
%
D
Switching Node SW Rise Time(18)  
VIN = 5.0V, ILOAD = 1.0A  
t
ns  
RISE  
7.0  
Switching Node SW Fall Time(18)  
VIN = 5.0V, ILOAD = 1.0A  
t
ns  
FALL  
–
–
17  
35  
–
–
Maximum Deadtime(18)  
t
ns  
ns  
D
Buck Control Loop Propagation Delay(18)  
t
PD  
VINV < 0.8V to VSW > 90% of High Level or VINV > 0.8V to VSW < 10%  
of Low Level  
–
50  
350  
10  
–
Soft Start Duration (Power Sequencing Disabled, EN1 = 1, EN2 = 1)(18)  
t
200  
7.0  
70  
800  
15  
s  
ms  
ms  
SS  
Fault Condition Timeout(18)  
Retry Timer Cycle(18)  
OSCILLATOR  
t
FAULT  
t
100  
150  
RET  
Oscillator Center Frequency(20)  
f
270  
300  
330  
kHz  
OSC  
RF = 11.3k  
Oscillator Frequency Range  
f
200  
7.0  
–
–
400  
22  
kHz  
k  
OSC  
FREQ  
OSC  
Oscillator Frequency Adjusting Resistor Range  
R
f
Oscillator Frequency Adjustment(19), (20)  
kHz  
RF = 7.0k  
400  
–
–
Oscillator Frequency Adjustment(19), (20)  
f
f
kHz  
OSC  
RF = 22k  
–
–
–
200  
–
Oscillator Default Frequency (Switching Frequency), FREQ Pin Open  
300  
kHz  
%
OSC  
Oscillator Output Signal Duty Cycle (Square Wave, 180° Out-of-Phase with  
the Internal Suitable Oscillator)  
D
OSC  
40  
50  
–
60  
–
Synchronization Pulse Minimum Duration(18)  
t
1.0  
s  
SYNC  
Notes  
18. Design information only. This parameter is not production tested.  
19. see Figure 4 for more details  
20. RF is RFREQ  
34701  
Analog Integrated Circuit Device Data  
12  
Freescale Semiconductor  
ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS (continued)  
Characteristics noted under conditions -40°C TA 85C unless otherwise noted. Input voltages VIN1 = VIN2 = 3.3V using  
the typical application circuit (see Figures 33), unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
BOOST REGULATOR  
Boost Regulator MOSFET Maximum ON Time(21)  
Boost Regulator Control Loop Propagation Delay(21)  
t
–
–
24  
50  
–
–
s  
ns  
ns  
ON  
t
BST_PD  
Boost Switching Node VBD Rise Time(21)  
IBST = 20mA  
t
B_RISE  
–
–
5.0  
3.0  
Boost Switching Node VBD Fall Time(21)  
IBST = 20mA  
t
ns  
B_FALL  
–
LINEAR REGULATOR (LDO)  
Fault Condition Timeout  
t
7.0  
70  
10  
15  
ms  
ms  
FAULT  
Retry Timer Cycle  
t
100  
150  
RET  
RESET MONITOR (RST)  
Monitoring LFB Pin Delay  
Monitoring INV Pin Delay  
SCA, SCL PIN, I2C BUS (STANDARD)  
t
12  
12  
–
–
28  
28  
s  
s  
D_RST_LFB  
t
D_RST_INV  
SCL Clock Frequency(21)  
SCL  
f
–
–
–
100  
–
kHz  
s  
Bus Free Time Between a STOP and a START Condition(21)  
BUF  
t
4.7  
Hold Time (Repeated) START Condition (After this period, the first clock  
pulse is generated.)(21)  
t
s  
HD-STA  
4.0  
4.7  
4.0  
–
–
–
–
–
–
Low Period of the SCL Clock(21)  
High Period of the SCL Clock(21)  
LOW  
t
s  
s  
ns  
t
HIGH  
SDA Fall Time from VIH_MAX to VIL_MIN, Bus Capacitance 10pF to 400pF,  
3.0mA Sink Current(21), (23)  
t
F
–
–
–
–
–
–
–
250  
–
Setup Time for a Repeated START Condition(21)  
SU-STA  
t
4.7  
0.0  
250  
4.0  
–
s  
s  
ns  
s  
pF  
(22)  
Data Hold Time for I2C Bus Devices(21)  
Data Setup Time(21)  
,
HD-DAT  
T
t
t
–
–
SU-DA  
Setup Time for STOP Condition(21)  
SU-STO  
CB  
t
–
Capacitive Load for Each Bus Line(21)  
400  
Notes  
21. Design information only. This parameter is not production tested.  
22. The device provides an internal hold time of at least 300ns for the SDA signal (refer to the VIH_MIN of the SCL signal) to bridge the  
undefined region of the falling edge of SCL.  
23. VIH is high level voltage on I2C bus lines and VIL is low level voltage on I2C bus lines  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
13  
ELECTRICAL CHARACTERISTICS  
TIMING DIAGRAM  
TIMING DIAGRAM  
t
HD-STA  
t
t
SU-STO  
t
HD-STA  
SU-STA  
t
t
SU-DAT  
HD-DAT  
Figure 4. Definition of Time on the I2C Bus  
ELECTRICAL PERFORMANCE CURVES  
300  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
295  
Vin=3.3V, Vout=1.2V  
Vin=3.3V, Vout=1.8V  
Vin=5.0V, Vout=1.2V  
Vin=5.0V, Vout=1.8V  
290  
285  
0
280  
0
0,5  
1
1,5  
-50  
50  
100  
Load Current [A]  
0
Temperature (C°)  
Figure 7. Switcher Efficiency vs. Load Current  
Figure 5. fOSC vs. Temperature  
450  
3.00  
2.80  
2.60  
2.40  
2.20  
2.00  
400  
350  
300  
250  
200  
150  
100  
-50  
0
50  
100  
7
12  
17  
22  
Temperature (°C)  
Rf (k )  
Figure 8. Switcher ILim vs. Temperature  
Figure 6. fOSC vs. Rf  
34701  
Analog Integrated Circuit Device Data  
14  
Freescale Semiconductor  
ELECTRICAL CHARACTERISTICS  
ELECTRICAL PERFORMANCE CURVES  
25  
23  
21  
19  
17  
15  
13  
11  
9
0.83  
0.82  
0.81  
0.80  
0.79  
0.78  
0.77  
7
5
-50  
0
50  
100  
Temperature(C°)
0
100  
200  
300  
RT (k ) with CT = 33 nF  
Figure 10. Timer (ms) vs. RT  
Figure 9. VREF vs. Temperature  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
15  
FUNCTIONAL DESCRIPTION  
INTRODUCTION  
FUNCTIONAL DESCRIPTION  
INTRODUCTION  
The 34701 power supply integrated circuit provides the  
means to efficiently supply the Freescale Power QUICC and  
other families of Freescale microprocessors. It incorporates a  
high performance synchronous buck regulator, supplying the  
microprocessor’s core, and a low dropout (LDO) linear  
regulator providing the microprocessor I/O and bus voltages.  
This device incorporates many advanced features; e.g.,  
precisely maintained up/down power sequencing, ensuring  
the proper operation and protection of the CPU and power  
system. At the same time, it provides high flexibility of  
configuration, allowing the maximum optimization of the  
power supply system.  
FUNCTIONAL PIN DESCRIPTION  
OSCILLATOR FREQUENCY PIN (FREQ)  
BOOTSTRAP PIN (BOOT)  
This switcher frequency selection pin can be adjusted by  
connecting external resistor RF to the FREQ pin. The default  
switching frequency (FREQ pin left open or tied to VDDI) is  
set to 300kHz.  
Bootstrap capacitor input.  
SERIAL DATA PIN (SDA)  
I2C bus pin. Serial data.  
INVERTING INPUT PIN (INV)  
SERIAL CLOCK PIN (SCL)  
Buck Controller Error Amplifier inverting input.  
I2C bus pin. Serial clock.  
OUTPUT VOLTAGE PIN (VOUT)  
Output voltage of the buck converter. Input pin of the  
switching regulator power sequence control circuit.  
LINEAR COMPENSATION PIN (LCMP)  
Linear regulator compensation pin.  
INPUT VOLTAGE 2 PINS (VIN2)  
LINEAR FEEDBACK PIN (LFB)  
Buck regulator power input. Drain of the high side power  
MOSFET.  
Linear regulator feedback pin.  
SWITCH PINS (SW)  
LINEAR REGULATOR PIN (LDO)  
Buck regulator switching node. This pin is connected to the  
inductor.  
Input pin of the linear regulator power sequence control  
circuit.  
GROUND PINS (GND)  
CURRENT SENSE PIN (CS)  
Analog ground of the IC, thermal heatsinking.  
Current sense pin of the LDO. Over-current protection of  
the linear regulator external power MOSFET. The voltage  
drop over the LDO current sense resistor RS is sensed  
between the CS and LDO pins. The LDO current limit can be  
adjusted by selecting the proper value of the current sensing  
resistor RS.  
POWER GROUND PINS (PGND)  
Buck regulator power ground.  
BOOST DRAIN PIN (VBD)  
Drain of the internal boost regulator power MOSFET.  
LINEAR DRIVE PIN (LDRV)  
BOOST VOLTAGE PIN (VBST)  
LDO gate drive of the external pass N-channel MOSFET.  
Internal boost regulator output voltage. The internal boost  
regulator provides a 20mA output current to supply the drive  
circuits for the integrated power MOSFETs and the external  
N-channel power MOSFET of the linear regulator. The  
voltage at the VBST pin is 7.75V nominal.  
INPUT VOLTAGE 1 PIN (VIN1)  
The input supply pin for the integrated circuit. The internal  
circuits of the IC are supplied through this pin.  
34701  
Analog Integrated Circuit Device Data  
16  
Freescale Semiconductor  
FUNCTIONAL DESCRIPTION  
FUNCTIONAL PIN DESCRIPTION  
POWER SUPPLY PIN (VDDI)  
RESET TIMER PIN (RT)  
Internal supply voltage. A ceramic low ESR 1uF 6V X5R or  
X7R capacitor is recommended.  
The Reset Timer power-up delay (RT) pin is used to set  
the delay between the time when the LDO and switcher  
outputs are active and stable and the RST output is released.  
An external resistor and capacitor are used to program the  
timer. The power-up delay can be obtained by using the  
following formula:  
ADDRESS PIN (ADDR)  
The ADDR pin is used to set the address of the device  
when used in an I2C communication. This pin can either be  
tied to VDDI or grounded through a 10kresistor. Refer to  
I2C Bus Operation on page 26 for more information on this  
pin.  
t
D = 10ms + RtCt  
Where Rt is the Reset Timer programming resistor and Ct  
is the Reset Timer programming capacitor, both connected in  
parallel from RT to ground.  
Note Observe the maximum Ct value and expect reduced  
accuracy if Rt is less than 10k.  
ENABLE 1 AND 2 PINS (EN1 AND EN2)  
These two pins permit positive logic control of the Enable  
function and selection of the Power Sequencing mode  
concurrently. Table 5 depicts the EN1 and EN2 function and  
Power Sequencing mode selection.  
RESET OUTPUT PIN (RST)  
The Reset Control circuit monitors both the switching  
regulator and the LDO feedback voltages. It is an open drain  
output and has to be pulled up to some supply voltage (e.g.,  
the output of the LDO) by an external resistor.  
Both EN1 and EN2 pins have internal pull-down resistors  
and both can withstand a short circuit to the supply voltage,  
6.0V.  
The Reset Control circuit supervises both output  
voltages—the linear regulator output VLDO and the switching  
regulator output VOUT. When either of these two regulators  
is out of regulation (high or low), the RST pin is pulled low.  
There is a 20s delay filter preventing erroneous resets.  
During power-up sequencing, RST is held low until the Reset  
Timer times out.  
Table 5. Operating Mode Selection  
EN1  
EN2  
Operating Mode  
Regulators Disabled  
0
0
1
1
0
1
0
1
Standard Power Sequencing  
Inverted Power Sequencing  
CLOCK SELECTION PIN (CLKSEL)  
No Power Sequencing,  
Regulators Enabled  
This pin sets the CLKSYN pin as either an oscillator output  
or a synchronization input pin. The CLKSEL pin is also used  
for the I2C address selection.  
CLOCK SYNCHRONIZATION PIN (CLKSYN)  
Oscillator output/synchronization input pin.  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
17  
FUNCTIONAL DESCRIPTION  
FUNCTIONAL INTERNAL BLOCK DESCRIPTION  
FUNCTIONAL INTERNAL BLOCK DESCRIPTION  
incorporates many advanced features; e.g., precisely  
maintained up/down power sequencing, ensuring the proper  
operation and protection of the CPU and power system.  
INTRODUCTION  
The 34701 incorporates a high performance synchronous  
buck regulator, supplying the microprocessor’s core, and a  
low dropout (LDO) linear regulator providing the  
microprocessor I/O and bus voltages. This device  
Power Sequencing  
Voltage Margining  
Watchdog Timer  
UVLO  
Boost Regulator  
Reset Control  
POR Timer  
Buck Control Logic  
I2C Interface  
VDDI  
Internal  
Supply  
Bandgap  
Buck HS and  
LS Driver  
Voltage  
Reference  
Linear Regulator  
Control  
Switcher  
Oscillator  
300kHz  
Thermal Shutdown  
ILIM  
Figure 11. 34701 Functional Internal Block Diagram  
When the inductor current falls below the valley current limit  
BOOST REGULATOR  
value (nominally 600mA), the low side switch is turned on  
again, starting the next switching cycle. After the boost  
regulator output capacitor reaches approximately 6.0 volts,  
the peak and valley current limit levels are proportionally  
scaled down to approximately one fifth of their original values.  
When the boost regulator reaches its regulation limit (7.75V  
typical), the low side switch is turned off until the output  
voltage falls below the regulation limit again.  
A boost regulator provides a high-voltage necessary to  
properly drive the buck regulator power MOSFETs,  
especially during the low input voltage condition. The LDO  
regulator external N-channel MOSFET gate is also powered  
from the boost regulator. In order to properly enhance the  
high side MOSFETs when only a +3.3V supply rail powers  
the integrated circuit, the boost regulator provides an output  
voltage of 7.75V nominal value.  
The higher current limit values in the beginning of the  
boost regulator start-up sequence allow fast power up of the  
whole IC, while the normal operation with reduced current  
limit greatly reduces the switching noise and therefore  
improves the overall EMC performance. See Figure 12 for  
the boost regulator output voltage and inductor current  
waveforms (picture not to scale).  
The 34701 boost regulator uses a simple hysteretic  
current control technique, which allows fast power-up and  
does not require any compensation. When the boost  
regulator main power switch (low side) is turned on, the  
current in the inductor starts to ramp up. After the inductor  
current reaches the upper current limit (nominally set at  
1.0A), the low-side switch is turned off and the current  
charges the output capacitor through the internal rectifier.  
34701  
Analog Integrated Circuit Device Data  
18  
Freescale Semiconductor  
FUNCTIONAL DESCRIPTION  
FUNCTIONAL INTERNAL BLOCK DESCRIPTION  
Fault Timer  
= 10 ms  
Booster Output Voltage  
7.75V  
t
t
= 10 ms  
FAULT  
FAU LT  
I
Current Limit  
I
pk  
pk  
6.0 V  
0.5 I  
0.5 I  
pk  
pk  
Retry Timer  
= 100 ms  
t
Ret  
0 A  
0 V  
Figure 13. Switching Regulator Current Limit  
(Not To Scale)  
I
= 1 A typ.  
pk  
To avoid destruction of the supplied circuits, the switching  
regulator has a current limit with retry capability. When an  
over-current condition occurs and the switch current reaches  
the peak current limit value, the main (high side) switch is  
turned off until the inductor current decays to the valley value,  
which is one half of the peak current limit. If an over-current  
condition exists for 10ms, the buck regulator control circuit  
shuts the switcher OFF and the switcher retry timer starts to  
time out. When the timer expires after 100ms, the switcher  
engages the start-up sequence and runs for 10ms,  
Booster Inductor Current  
0.6 A typ.  
0.2 A typ.  
0.1 A typ.  
repeatedly checking for the over-current condition. Figure 13  
describes the switching regulator over-current condition and  
current limit. During the current limited operation (e.g., in  
case of short-circuit on the switching regulator output), the  
switching regulator operation is not synchronized to the  
oscillator frequency. Figure 14 (respectively Figure 15)  
depicts the current limit with a retry capability feature of the  
switcher (respectively LDO).  
Figure 12. Boost Regulator Startup (Not To Scale)  
SWITCHING REGULATOR  
The switching regulator is a high frequency (300kHz  
default, adjustable in the range from 200kHz to 400kHz),  
synchronous buck converter driving integrated high side and  
low side N-channel power MOSFETs. The switching  
regulator output voltage is adjustable by means of an external  
resistor divider to provide the required output voltage within  
±2.0% accuracy, and is intended to directly power the core of  
the microprocessor. The buck controller uses a PWM voltage  
mode control topology with feed-forward to achieve excellent  
line and load regulation.  
The 34702 integrated boost regulator provides a 7.75V rail  
which is used to properly bias the switcher’s MOSFET. In  
addition, the boost structure has a very low start-up voltage  
(Typically 1.6V), hence ensuring very low input voltage  
functionality. A typical bootstrap technique is used to provide  
voltage necessary to properly enhance the high side  
MOSFET gate. When the regulator is supplied only from low  
input voltage (e.g., single +3.3V supply rail), the bootstrap  
capacitor is charged from the internal boost regulator output  
VBST through an external diode. This arrangement allows  
the 34701 to operate from very low input voltage and also  
comply with the power sequencing requirements of the  
supplied microcontroller.  
Figure 14. Switching Converter Over-current Protection  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
19  
FUNCTIONAL DESCRIPTION  
FUNCTIONAL INTERNAL BLOCK DESCRIPTION  
100ms, the LDO tries to power-up again for 10ms, repeatedly  
checking for the over-current condition. The current limit of  
the LDO can be set by using the following formula:  
ILIM = 50mV/RS  
Where RS is the LDO current sense resistor, connected  
between the CS pin and the LDO pin output (see Figure 33  
on page 34), and 50mV is the typical value of the LDO current  
sense comparator threshold voltage.  
When no current sense resistor is used, it is still possible  
to detect the over-current condition by tying the current sense  
pin CS to the VBST voltage. In this case, the over-current  
condition is sensed by saturation of the linear regulator driver  
buffer.  
The output voltage of the LDO can be adjusted by means  
of an external resistor divider connected to the feedback  
control pin LFB. The linear regulator output voltage can be  
adjusted in the range of 0.8V to VIN - LDO dropout voltage.  
Power-up, power-down, and fault management are  
coordinated with the switching regulator.  
Figure 15. LDO Converter Over-current Protection  
The output voltage VOUT can be adjusted by means of an  
external resistor divider connected to the feedback control  
pin INV. The switching regulator output voltage can be  
adjusted in the range of 0.8V to VIN - buck dropout voltage.  
Power-up, power-down, and fault management are  
coordinated with the linear regulator.  
POWER SEQUENCING VOLTAGE MARGINING  
WATCHDOG TIMER  
A watchdog function is available via I2C bus  
communication. It is possible to select either window  
watchdog or timeout watchdog operation, as illustrated in  
Figure 16.  
SWITCHER OSCILLATOR  
Watchdog timeout starts when the watchdog function is  
activated via I2C bus sending a watchdog programming  
command byte, thus determining watchdog operation  
(window or timeout) and period duration (refer to Table 8,  
page 27). If the watchdog is cleared by receiving a new  
watchdog programming command through the I2C bus, the  
watchdog timer is reset and the new timeout period begins. If  
the watchdog time expires, the RST will become active  
(LOW) for a time determined by the RC components of the  
RT timer plus 10ms. After a watchdog timeout, the function is  
no longer active.  
A 300kHz (default) oscillator sets the switching frequency  
of the buck regulator. The frequency of the oscillator can be  
adjusted between 200kHz and 400kHz by an optional  
external resistor RF connected from the FREQ pin of the  
integrated circuit to ground. See Figure 6 on page 14 for  
frequency resistor selection.  
The CLKSYN pin can be configured as either an oscillator  
output when the CLKSEL pin is left open or as a  
synchronization input when the CLKSEL pin is grounded.  
The oscillator output signal is a square wave logic signal with  
50% duty cycle, 180 degrees out-of-phase with the internal  
clock signal. This allows opposite phase synchronization of  
two 34702 devices.  
Watchdog Closed  
Window Open  
for Watchdog Clear  
No Watchdog Clear Allowed  
When the CLKSYN pin is used as a synchronization input  
(CLKSEL pin grounded), the external resistor RF chosen  
from the chart in Figure 6 should be used to synchronize the  
internal slope compensation ramp to the external clock.  
Operation is only recommended between 200kHz and  
400kHz. The supplied synchronization signal does not need  
to be 50% duty cycle. Minimum pulse width is 1.0µs.  
50% of Watchdog Period  
Watchdog Period  
Timing Selected via 12C Bus – See Table 4  
Window Watchdog  
Window Open for Watchdog Clear  
LOW DROPOUT LINEAR REGULATOR (LDO)  
The adjustable low dropout linear regulator (LDO) is  
capable of supplying a 1.0A output current. It has a current  
limit with retry capability. When the voltage measured across  
the current sense resistor reaches the 50mV threshold, the  
control circuit limits the current for 10ms. If the over-current  
condition still exists, the linear regulator is turned off and the  
retry timer starts to time out. When the timer expires after  
Watchdog Period  
Timing Selected via I2C Bus – See Table 4  
Time-Out Watchdog  
Figure 16. Watchdog Operation  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
20  
FUNCTIONAL DESCRIPTION  
FUNCTIONAL INTERNAL BLOCK DESCRIPTION  
When the window watchdog function is selected, the timer  
cannot be cleared during the closed window time, which is  
50% of the total watchdog period. When the watchdog is  
cleared, the timer is reset and starts a new tim-out period. If  
the watchdog is not cleared during the open window time, the  
RST will become active (LOW) for a time determined by the  
RC components of the RT timer plus 10ms.  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
21  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
THERMAL SHUTDOWN  
POWER SEQUENCING MODES  
To increase the overall safety of the system designed with  
the 34701, an internal thermal shutdown function has been  
incorporated into the switching regulator circuit. The 34701  
senses the temperature of the buck regulator main switching  
MOSFET (high side MOSFET M1; see Figure 2 on page 2),  
the low side (synchronous MOSFET M2), and control circuit.  
If the temperature of any of the monitored components  
exceeds the limit of safe operation (Thermal Shutdown), the  
switching regulator and the LDO shut down. After the  
temperature falls below the value given by the thermal  
shutdown hysteresis window, the switcher tries again to  
operate.  
The power sequencing of the two outputs of this power  
supply IC is in compliance with the Freescale Power QUICC  
and other 32-bit microprocessor requirements. When the  
input voltage is applied, the switcher and linear regulator  
outputs follow the supply rail voltage during power-up and  
power-down in the limits given by the microcontroller power  
sequencing specification, illustrated in Figures 17 through  
19. There are two possible power sequencing modes,  
Standard and Inverted, as explained in more detail below.  
The third mode of operation is Power Sequencing Disabled.  
3.3 V Input  
2.5 V  
Other  
Circuits  
The VOUT pull-down MOSFET M3 has an independent  
thermal shutdown control. If the M3 temperature exceeds the  
thermal shutdown, the M3 is turned off without affecting the  
switcher operation.  
34701  
VIN2  
VIN1  
VBD  
VBST  
LDRV  
CS  
3.3 V  
The LDO pull-down MOSFET M4 has an independent  
thermal shutdown control. If the M4 temperature exceeds the  
thermal shutdown, the M4 will be turned off without affecting  
the LDO operation.  
LDO  
LFB  
VDDL (Core)  
RT  
ADDR  
MCU  
SDA  
SCL  
RST  
GND  
VBST  
BOOT  
SW  
SOFT START  
1.5 V  
EN1  
EN2  
VDDH (I/Os)  
A switching regulator soft start feature is incorporated in  
the 34701. The soft start is active each time the IC is enabled,  
VIN is reapplied, or after a fault retry. Other transient events  
do not activate the soft start.  
VOUT  
CLKSYN  
CLKSEL  
FREQ  
PGND  
INV  
Optional  
VDDI  
VOLTAGE MARGINING  
The 34701 includes a voltage margining feature accessed  
3.3 V Input Supply (I/O Voltage)  
through the I2C bus. Voltage margining allows for  
V = 2.1 V  
Max. Lead  
independent adjustment of the switcher VOUT voltage and  
the linear output VLDO. Each can be adjusted up and down  
in 1.0% steps to a range of ±7.0%. This feature allows for  
worst case system validation; i.e., determining the design  
margin. Margining details are described in the section entitled  
I2C Bus Operation, beginning on page 26 of this datasheet.  
1.8V Start-Up  
Slope  
1.0 V/ms  
1.5 V Core Voltage  
V = 2.1 V  
Max. Lead  
V = 0.4 V  
Max. Lag  
Figure 17. Standard Power-up/Down Sequence  
in +3.3V Supply System  
34701  
Analog Integrated Circuit Device Data  
22  
Freescale Semiconductor  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
5.0 V Input  
5.0 V Input  
34701  
34701  
VIN2  
VIN1  
VIN2  
VIN1  
VBD  
VBST  
LDRV  
CS  
VBD  
VBST  
LDRV  
CS  
3.3 V  
1.5 V  
LDO  
LFB  
VDDL (Core)  
VDDH (I/Os)  
LDO  
LFB  
RT  
RT  
ADDR  
ADDR  
MCU  
SDA  
SCL  
MCU  
SDA  
SCL  
RST  
RST  
GND  
EN1  
GND  
VBST  
BOOT  
SW  
VBST  
BOOT  
SW  
5.0 V  
EN1  
EN2  
1.5 V  
3.3 V  
VDDL (Core)  
VDDH (I/Os)  
EN2  
5.0 V  
VOUT  
VOUT  
CLKSYN  
CLKSYN  
CLKSEL  
FREQ  
PGND  
CLKSEL  
FREQ  
PGND  
INV  
INV  
Optional  
Optional  
VDDI  
VDDI  
5.0 V Input Supply  
V = 2.1 V  
Max. Lead  
V = 2.1 V  
3.3 V I/O Voltage (VOUT)  
5.0 V Input Supply  
V = 2.1 V  
Max. Lead  
Max. Lead  
1.8V Start-Up  
V = 2.1 V  
(VLDO)  
1.5 V Core Voltage  
3.3 V I/O Voltage (VLDO)  
Max. Lead  
1.8V Start-Up  
1.5 V Core Voltage  
(VOUT)  
V = 0.4 V  
V = 0.4 V  
Max. Lag  
Max. Lag  
V = 0.4 V  
V = 0.4 V  
Max. Lag  
Max. Lag  
Figure 19. Inverted Power-up/Down Sequence in +5.0V  
Supply System  
Figure 18. Standard Power-up/Down Sequence  
in +5.0V Supply System  
ASSUMED REQUIREMENTS  
1. I/O supply voltage not to exceed core voltage by more  
than 2.0V.  
STANDARD POWER SEQUENCING  
When the power supply IC operates in the Standard Power  
Sequencing Mode, the switcher output provides the core  
voltage for the microprocessor. This situation and operating  
conditions are illustrated in Figures 17 and 18. Table 5,  
page 17, shows the Power Sequencing Mode selection.  
2. Core supply voltage not to exceed I/O voltage by more  
than 0.4V.  
Methods of Control  
The 34701 has several methods of monitoring and  
controlling the regulator output voltages, as described in the  
paragraphs below. Power sequencing control is also  
achieved through the intrinsic operation of the regulators.  
The EN1 and EN2 pins can be used to select the proper  
Power Sequencing Mode required by the powered system or  
to disable the power sequencing (refer to Table 5).  
INVERTED POWER SEQUENCING  
When the power supply IC is operating in the Inverted  
Power Sequencing Mode, the linear regulator (LDO) output  
provides the core voltage for the microprocessor, as  
illustrated in Figure 19. Table 5 shows the Power  
Sequencing Mode selection.  
Intrinsic Operation  
For both the LDO and switcher, whenever the output  
voltage is below the regulation point, the LDO external Pass  
MOSFET is on, or the buck high side MOSFET is on at a duty  
cycle controlled by the switcher. Because these devices are  
MOSFETs, current can flow in either direction, balancing the  
voltages via the common supply pin. The ability to maintain  
the MOSFETs on is dependent on the available gate voltage,  
and thus the size of the boost regulator storage capacitor.  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
23  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
Standard Power Sequencing Control  
VOUT output voltage is less than 1.8V above the LDO  
output voltage.  
Comparators monitor voltage differences between the  
LDO (LDO pin) and the switcher (VOUT pin) outputs as  
follows:  
4. VOUT < LDO + 2.0V, cancel (2)  
5. VOUT < LDO - 0.2V, turn off LDO. The LDO can be  
forced off. This occurs whenever the VOUT is less than  
VLDO - 0.2V.  
1. LDO > VOUT + 1.9V, turn off LDO. The LDO can be  
forced off. This occurs whenever the LDO output  
voltage exceeds the switcher output voltage by more  
than 1.9V.  
6. VOUT < LDO - 0.3V, turn on the 1.5LDO sink  
MOSFET. This occurs when the LDO output voltage  
exceeds the VOUT output by more than 300mV.  
2. LDO > VOUT + 2.0V, shunt LDO to ground. If turning  
off the LDO is insufficient and the LDO output voltage  
exceeds the switcher output voltage by more than  
2.0V, a 1.5shunt MOSFET is turned on that  
7. VOUT < LDO - 0.2V, cancel (6).  
8. VOUT < LDO - 0.1V, cancel (5). Normal operation  
resumes when VOUT > LDO - 0.1V.  
discharges the LDO load capacitor to ground. The  
shunt MOSFET is used for switcher output shorts to  
ground and for power down in case of VIN1 VIN2  
with the switcher output falling faster than the LDO.  
STANDARD OPERATING MODE  
Single 3.3V Supply, VIN = VIN1 = VIN2 = 3.3V  
3. LDO < VOUT + 1.9V cancel (2).  
The 3.3V supplies the microprocessor I/O voltage, the  
switcher supplies core voltage (e.g., 1.5V nominal), and the  
LDO operates independently (see Figure 17, page 22).  
Power sequencing depends only on the normal switcher  
intrinsic operation to control the buck high side MOSFET.  
4. LDO < VOUT + 1.8V, cancel (1) above, re-enable LDO.  
Normal operation resumes when the LDO output  
voltage is less than 1.8V above the switcher output  
voltage.  
5. LDO < VOUT - 0.1V, turn off switcher. The switcher  
can be forced off. This occurs whenever the LDO is  
less than VOUT - 0.1V.  
Power-up  
When VIN is rising, initially VOUT is below the regulation  
point and the Buck High-Side MOSFET is on. In order not to  
exceed the 2.1 V differential requirement between the I/O  
(VIN) and the core (VOUT), the switcher must start up at  
2.1 V or less and be able to maintain the 2.1 V or less  
differential. The maximum slew rate for VIN is 1.0 V/ms.  
6. LDO < VOUT - 0.3V, turn on Sync (LS) MOSFET and  
1.5VOUT sink MOSFET. The buck high side  
MOSFET is forced off and the sync MOSFET is forced  
on. This occurs when the switcher output voltage  
exceeds the LDO output by more than 300mV.  
7. LDO > VOUT - 0.3V, cancel (6).  
Power-Down  
8. LDO > VOUT - 0.1V, cancel (5). Normal operation  
resumes when LDO < VOUT - 0.1V.  
When VIN is falling, VOUT falls below the regulation point;  
therefore, the buck high side MOSFET is on. In the case  
where VOUT is falling faster than VIN, the buck high side  
MOSFET attempts to maintain VOUT. In the case where VIN  
is falling faster than VOUT, the buck high side MOSFET is  
also on, and the VOUT load capacitor is discharged through  
the buck high side MOSFET to VIN. Thus, provided VIN does  
not fall too fast, the core voltage (VOUT) does not exceed the  
I/O voltage (VIN) by more than a maximum of 0.4V.  
Inverted Power Sequencing Control  
Comparators monitor voltage differences between the  
switcher (VOUT pin) and LDO (LDO pin) outputs as follows:  
1. VOUT > LDO + 1.8V, turn off VOUT . The switcher  
VOUT can be forced off. This occurs whenever the  
VOUT output voltage exceeds the LDO output voltage  
by more than 1.8V.  
2. VOUT > LDO + 2.0V, shunt VOUT to ground. If turning  
off the switcher VOUT is insufficient and the VOUT  
output voltage exceeds the LDO output voltage by  
more than 2.0V, a 1.5shunt MOSFET and the  
switcher synchronous MOSFET are turned on to  
discharge the VOUT load capacitor to ground. The  
shunt MOSFET and synchronous MOSFET are used  
for LDO output shorts to ground and for power down in  
case of VIN1 VIN2 with LDO output falling faster than  
the VOUT.  
Shorted Load  
1. VOUT shorted to ground. This causes the I/O voltage  
to exceed the core voltage by more than 2.1V. No load  
protection.  
2. VIN shorted to ground. Until the switcher load  
capacitance is discharged, the core voltage exceeds  
the I/O voltage by more than 0.4V. By the intrinsic  
operation of the switcher, the load capacitor is  
discharged rapidly through the buck high side  
MOSFET to VIN.  
3. VOUT < LDO + 1.8V, cancel (1) and (2) above, re-  
enable VOUT. Normal operation resumes when the  
3. VOUT shorted to supply. No load protection. 34701 is  
protected by current limit and thermal shutdown.  
34701  
Analog Integrated Circuit Device Data  
24  
Freescale Semiconductor  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
Single 5.0V Supply, VIN1 = VIN2, or Dual Supply VIN1   
VIN2  
depends only on the normal LDO intrinsic operation to control  
the Pass MOSFET.  
The LDO supplies the microprocessor I/O voltage. The  
switcher supplies the core (e.g., 1.5V nominal) (see  
Figure 18, page 23).  
Power-up  
When VIN is rising, initially LDO is below the regulation  
point and the Pass MOSFET is on. In order not to exceed the  
2.1V differential requirement between the I/O (VIN) and the  
core (LDO), the LDO must start up at 2.1V or less and be able  
to maintain the 2.1V or less differential. The maximum slew  
rate for VIN is 1.0V/ms.  
Power-up  
This condition depends upon the regulator current limit,  
load current and capacitance, and the relative rise times of  
the VIN1 and VIN2 supplies. There are two cases:  
1. LDO rises faster than VOUT. The LDO uses control  
methods (1) and (2) described in the section Methods  
of Control on page 23.  
Power-down  
When VIN is falling, LDO falls below the regulation point;  
therefore, the Pass MOSFET is on. In the case where LDO is  
falling faster than VIN, the pass MOSFET attempts to  
maintain LDO. In the case where VIN is falling faster than  
LDO, the pass MOSFET is also on, and the LDO load  
capacitor is discharged through the pass MOSFET to VIN.  
Thus, provided VIN does not fall too fast, the core voltage  
(LDO) does not exceed the I/O voltage (VIN) by more than  
maximum of 0.4V.  
2. VOUT rises faster than LDO. The switcher uses control  
methods (5) and (6) described in the section Methods  
of Control on page 23.  
Power-down  
This condition depends upon the regulator load current  
and capacitance and the relative fall times of the VIN1 and  
VIN2 supplies. There are two cases:  
Shorted Load  
1. VOUT falls faster than LDO. The LDO uses control  
methods (1) and (2) described in the section Methods  
of Control on page 23.  
1. LDO shorted to ground. This will cause the I/O voltage  
to exceed the core voltage by more than 2.1V. No load  
protection.  
In the case VIN1 = VIN2, the intrinsic operation turns  
on both the buck high side MOSFET and the LDO  
external Pass MOSFET, and discharges the LDO load  
capacitor into the VIN supply.  
2. VIN shorted to ground. Until the LDO load capacitance  
is discharged, the core voltage exceeds the I/O voltage  
by more than 0.4V. By the intrinsic operation of the  
LDO, the load capacitor is discharged rapidly through  
the Pass MOSFET to VIN.  
2. LDO falls faster than VOUT. The switcher uses control  
methods (5) and (6) described in the section Methods  
of Control on page 23.  
3. LDO shorted to supply. No load protection.  
Single 5.0V Supply, VIN1 = VIN2, or Dual Supply VIN1   
VIN2  
Shorted Load  
1. VOUT shorted to ground. The LDO uses method (1)  
and (2) described in the section Methods of Control on  
page 23.  
The switcher VOUT supplies the microprocessor I/O  
voltage. The LDO supplies the core (e.g., 1.5V nominal) (see  
Figure 19, page 23).  
2. LDO shorted to ground. The switcher uses control  
methods (5) and (6) described in the section Methods  
of Control on page 23.  
Power-up  
This condition depends upon the regulator current limit,  
load current and capacitance, and the relative rise times of  
the VIN1 and VIN2 supplies. There are two cases:  
3. VIN1 shorted to ground. Device is not working.  
4. VIN2 shorted to ground with VIN1 and VIN2 different.  
This is equivalent to the switcher output shorted to  
ground.  
1. VOUT rises faster than LDO. The switcher VOUT uses  
control methods (1) and (2) described in the section  
Methods of Control on page 23.  
5. VOUT shorted to supply. No load protection. 34701 is  
protected by current limit and thermal shutdown.  
2. LDO rises faster than VOUT. The LDO uses control  
methods (5) and (6) described in the section Methods  
of Control on page 23.  
6. LDO shorted to supply. No load protection. 34701 is  
protected by current limit and thermal shutdown.  
INVERTED OPERATING MODE  
Power-down  
This condition depends upon the regulator load current  
and capacitance and the relative fall times of the VIN1 and  
VIN2 supplies. There are two cases:  
Single 3.3V Supply, VIN = VIN1 = VIN2 = 3.3V  
The 3.3V supplies the microprocessor I/O voltage, the  
LDO supplies core voltage (e.g., 1.5V nominal), and the  
switcher VOUT operates independently. Power sequencing  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
25  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
1. LDO falls faster than VOUT . The VOUT uses control  
methods (4) and (5) described in the section Methods  
of Control on page 23.  
Shorted Load  
1. LDO shorted to ground. The VOUT uses methods (1)  
and (2) described in the section Methods of Control on  
page 23.  
In the case VIN1 = VIN2, the intrinsic operation turns  
on both the buck high side MOSFET and the LDO  
external Pass MOSFET, and discharges the VOUT  
load capacitor into the VIN supply.  
2. VOUT shorted to ground. The LDO uses control  
methods (5) and (6) described in the section Methods  
of Control on page 23.  
2. VOUT falls faster than LDO. The LDO uses control  
methods (5) and (6) described in the section Methods  
of Control on page 23.  
3. VIN1 shorted to ground. Device is not working.  
4. VIN2 shorted to ground. This is equivalent to the  
switcher VOUT output shorted to ground.  
5. LDO shorted to supply. No load protection. 34701 is  
protected by current limit and thermal shutdown.  
6. VOUT shorted to supply. No load protection. 34701 is  
protected by current limit and thermal shutdown.  
LOGIC COMMANDS AND REGISTERS  
2
assure its unique address. Figure 21 illustrates the flexible  
addressing feature for a 7-bit address. Table 6 provides the  
definition of the selectable portion of the device address.  
I C BUS OPERATION  
The 34701 device is compatible with the I2C interface  
standard. SDA and SCL pins are the Serial Data and Serial  
Clock pins of the I2C bus.  
When the ADDR pin is used and put to low level, pull the  
ADDR pin to ground through a 10kresistor.  
2
I C COMMAND AND DATA FORMATS  
MSB  
6
LSB  
Bits  
3
Communication Start  
5
1
4
1
2
1
0
Communication starts with a START condition, followed by  
the slave device unique address. The Read/Write (R/W) bit  
defines whether the data should be read from or written to the  
device (the 34701 operates only as a slave device; therefore,  
the R/W bit should always be set to 0). The 34701 responds  
by sending the Acknowledge bit (Ack) to the master device.  
Figure 20 illustrates the beginning of an I2C communication  
for a 7-bit slave address.  
1
0
1 A1 A0  
Fixed Address Selectable  
Address  
Figure 21. Address Bit Definition for 7-Bit Address  
Table 6. Definition of Selectable Portion of Device  
Address  
CLKSEL Pin  
Low  
ADDR Pin  
Low  
A1  
0
A0  
0
Ack  
S
7-Bit Address  
R/W  
Low  
High (Open)  
Low  
0
1
Figure 20. Communication Start Using 7-Bit Address  
Slave Address Definition  
High (Open)  
High (Open)  
1
0
High (Open)  
1
1
34701 has the two least significant address bits (LSB)  
defined by the state of the CLKSEL pin (A1) and the ADDR  
pin (A0).  
Writing Data Into the Slave Device  
After the address acknowledgment by the slave, DATA  
can be written into the slave registers. The R/W bit must be  
set to 0 to allow DATA to be written into the 34702. Figure 22  
shows the data write sequence. Actions performed by the  
slave device are grayed.   
Note The state of the CLKSEL pin also defines the  
configuration of the oscillator synchronization CLKSYN pin.  
Leaving the CLKSEL pin open or pulling it high defines the  
CLKSYN pin as an oscillator output. When the CLKSEL pin  
is pulled low, the CLKSYN pin is configured as a  
synchronization input for the external clock signal.  
S
7-Bit Address  
0
Ack  
DATA  
Ack  
This feature allows up to four 34701 ICs to communicate  
in the same I2C bus, all of them sharing the same high order  
address bits. A different combination of the two LSB address  
bits A1 and A0 can be assigned to each individual part to  
(Write)  
Figure 22. Data Transfer for Write Operations  
34701  
Analog Integrated Circuit Device Data  
26  
Freescale Semiconductor  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
DATA Definition  
Table 8. Command Byte Definitions  
The DATA field in the single Data Transfer contains one or  
several Command Bytes. The Command Byte identifies the  
kind of operation required by the master to be performed and  
has two fields, as illustrated in Figure 23:  
Watchdog  
Programming  
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
1st Command  
WD OFF  
(As a 2nd  
Command Byte)  
(24)  
1. Address field  
2. Value field  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
WD 1280ms  
Wind. OFF  
WD 320ms  
Wind. OFF  
The address field is selected from the list in Table 7.  
WD 80ms  
Wind. OFF  
MSB  
7
LSB  
Bits  
6
5
4
3
2
1
0
WD 20ms  
Wind. OFF  
D6 D5 D4 D3 D2 D1 D0  
D7  
WD 1280ms  
Wind. ON  
Address Field  
Value Field  
Figure 23. Command Byte  
WD 320ms  
Wind. ON  
Table 7. Address Field Definitions  
WD 80ms  
Wind. ON  
Address Field  
Operation  
Write  
WD 20ms  
Wind. ON  
001  
011  
Voltage Margining  
Watchdog  
W
W
Notes  
24. The Watchdog timer is turned ON automatically after  
receiving any other valid command byte changing watchdog  
time.  
Refer to Table 8, page 27, which summarizes the value  
field definitions for the entire set of operation options.  
Table 8. Command Byte Definitions  
Security in Writing Commands  
To improve the security level, a so-called first command is  
defined to initiate each write communications. The first  
command identifies the operation, which is executed by the  
following command byte.  
Operation  
Address  
Value  
Action  
Voltage Margining  
0
0
0
0
1
1
0
x
0
0
0
0
0
0
0
0
1st Command  
(As a 2nd  
Command Byte)  
Output  
Nominal  
A first command has the address field equal to the related  
operation one, followed by a null value field (all zeros).  
Table 9 summarizes first command definitions. The master  
sends the first command before the command byte for the  
intended operation.  
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
x
x
x
x
x
x
0
0
0
0
0
0
0
0
0
1
1
1
0
1
1
0
0
1
1
0
1
0
1
0
+ 1.0%  
+ 2.0%  
+ 3.0%  
+ 4.0%  
+ 5.0%  
+ 6.0%  
Table 9. First Command Definitions  
LDO Output: x=0  
First Command  
001 00000  
Operation  
Switcher Output  
x=1  
Voltage Margining  
011 00000  
Watchdog Programming  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
x
x
x
x
x
x
x
x
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
+ 7.0%  
- 1.0%  
- 2.0%  
- 3.0%  
- 4.0%  
- 5.0%  
- 6.0%  
- 7.0%  
VOLTAGE MARGINING OPERATION  
After starting the communication in Writing mode, the  
master sends the first command followed by the specific  
command byte to set the required voltage margining for either  
the LDO or the switcher (see Figure 24). To achieve a  
simultaneous set for both LDO and switcher, two specific  
commands must be issued in sequence after the first  
command, one for each supply.  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
27  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
address acknowledge sent by 34702. I2C bus protocol  
defines this circumstance as a master-transmitter and slave-  
receiver configuration.  
0
0
1
0 0  
0
0
0
0 0 1 x x x x x  
Ack  
Figure 27 illustrates a communication beginning with the  
slave address, the first command for voltage margining, and  
a third byte containing the address field 001 and the value  
field 00101 corresponding with the LDO fifth setting (LDO  
output voltage = +5% above its nominal value). If a  
simultaneous setting for switcher is needed, a fourth byte  
should be included before the STOP condition (P); for  
instance, 001 11100 to set the switcher in its twelfth setting  
(switcher output voltage = -5% below its nominal value) - see  
Figure 28.  
First Byte for Voltage Margining  
Command Byte  
Figure 24. Voltage Margining Programming  
(One Supply Only)  
Note: x bits, which set the voltage margining value are  
defined in Table 8.  
WATCHDOG PROGRAMMING OPERATION  
For watchdog operation control, the master periodically  
sends a watchdog first command followed by a command  
byte selecting, or confirming, the watchdog period according  
to the options listed in Table 8. See Figure 25 for the  
watchdog timer programming command example.  
The example of data transfer setting the watchdog timer is  
shown in the Figure 26.  
The internal watchdog timer is turned ON by receiving a  
valid watchdog programming command (after receiving the  
watchdog programming first command), and it is cleared  
each time the next watchdog programming command is  
written into the device, provided it arrives during the window  
open time. Thus, the watchdog programming command  
clears the timer and sets the new timing conditions at the  
same time. The watchdog programming first command  
01100000 sent twice shuts the timer OFF, and the watchdog  
function is disabled. Any other valid watchdog command  
turns the timer ON again.  
A2 A1  
S
A6 A5 A4 A3  
A0 0 Ack  
Write  
START  
Slave Address  
0
1
1
0
0
0
0 Ack  
0
First Command for Watchdog Programming  
0
1
1
0
1
0
0
1 Ack  
P
STOP  
Address Field Value Field:  
Time-out WD = 320 ms  
(Window OFF)  
0
1
1
0 0  
0
0
0
0 1 1 x x x x x  
Ack  
Figure 26. Data Transfer Example - Watch Dog Timer  
Setting.  
First Byte for Watchdog Programming Command Byte  
Figure 25. Watchdog Timer Programming  
A2 A1  
S
A6 A5 A4 A3  
A0 0 Ack  
Write  
Note: x bits, which set the watchdog timer value are  
defined in Table 8, page 27.  
START  
Slave Address  
Communication Stop  
0
0
1
0
0
0
0 Ack  
0
Only the master can terminate the data transfer by issuing  
a STOP condition. The slave waits for this condition to  
resume its initial state waiting for the next START condition  
(see Figure 26).  
First Command for Voltage Margining  
0
0
1
0
0
1
0
1 Ack  
P
STOP  
Address Field Value Field = LDO  
5th Setting  
COMPLETE DATA TRANSFER EXAMPLES  
The master device controlling the I2C bus always starts  
addressing a 34701 slave IC in writing mode (R/W = 0) to  
enable it to write a command byte just after receiving the  
Figure 27. Data Transfer Example - LDO Voltage  
Margining  
34701  
Analog Integrated Circuit Device Data  
28  
Freescale Semiconductor  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
A2 A1  
S
A6 A5 A4 A3  
A0 0 Ack  
Write  
START  
Slave Address  
0
0
1
0
0
0
0 Ack  
0
First Command for Voltage Margining  
0
0
1
0
0
1
0
1 Ack  
Address Field Value Field: LDO  
LDO = Nom. + 5%  
V
0
0
1
1
1
1
0
0 Ack  
P
STOP  
Address Field Value Field: Switcher  
OUT = Nom. - 5%  
V
Figure 28. Data Transfer Example - LDO and Switcher  
Voltage Margining  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
29  
TYPICAL APPLICATIONS  
TYPICAL APPLICATIONS  
load regulation. The control circuit block diagram is shown in  
Figure 29.  
BUCK REGULATOR CONTROL CIRCUIT  
The 34701 buck regulator utilizes a PWM Voltage Mode  
topology with feed-forward to achieve an excellent line and  
L
Figure 29. Buck Regulator Control Circuit  
The integrated 40pF capacitor CF charged through the  
external resistor R4 provides the feed-forward ramp  
waveform, the amplitude of which is proportional to the input  
voltage, thus providing the feed-forward function.  
1
------------------------------------------  
=
fzc  
2C2R1 + R3  
The Feed-Forward implemented by resistor R4 and  
integrated capacitor CF creates a pole in the overall loop  
transfer function, the frequency of which can be calculated  
from the following formula.  
Figure 30 shows the Bode plot of the 34701 buck regulator  
control loop gain and phase versus frequency.  
The first double pole on the Bode plot is created by the  
buck regulator output L-C filter, and its frequency can be  
calculated as:  
VIN  
--------------------------------------------------------------- ----------------------  
1
fpFF  
=
VIN – VRef  
2R4CF  
1
1
------- -------------------------------  
+ Vm1  
----------------------  
fLC  
=
fsw  
R4CF  
2COL  
Where VRef is the buck regulator reference voltage  
(VRef = 0.8V typ.) at the INV pin,  
Where CO is the value of the buck output capacitor and L  
is the inductance value of the output filter inductor L.  
VIN is the buck regulator input voltage,  
Vm1 is the ramp generated by the internal ramp  
generator (Vm1 = 0.5V typ.).  
The frequency of the compensating zero can be calculated  
as follows.  
34701  
Analog Integrated Circuit Device Data  
30  
Freescale Semiconductor  
TYPICAL APPLICATIONS  
.
1
----------------------------------------------------------------------------------------  
R2 = VRef  
Gain  
[dB]  
VO + IO RL– VRef  
VO – VRef  
------------------------------------------------------- -------------------------  
+
20  
f
R4  
R1  
LC  
f
z(c)  
Where VRef is the buck regulator reference voltage   
(VRef = 0.8V typ.) at the INV pin,  
f
BW  
0
VO is the selected output voltage,  
f
f
z(ESR) p(FF)  
IO is the output load current,  
RL is the DC resistance of the inductor L.  
f
p(c)  
-20  
It is apparent that the buck regulator output voltage is  
affected by the voltage drop caused by the inductor serial  
resistance and the regulator output current. In those  
applications which do not require precise output voltage,  
setting the formula for calculating selected output voltage can  
be simplified as follows:  
-40  
-180  
Phase  
[Deg.]  
1
----------------------------------------------------------------  
R2 = VRef  
R1 + R4  
--------------------------  
VO – VRef   
R1 R4  
-2 70  
Linear Regulator Output Voltage  
The output voltage of the linear regulator (LDO) can be set  
by a simple resistor divider according to the following formula:  
RU  
-------  
VLDO = VRef 1 +  
RL  
-3 60  
1.0  
10  
100  
1000  
10000  
Frequency [kHz]  
Where VRef is the linear regulator reference voltage   
(VRef = 0.8V typ.) at the LFB pin,  
Figure 30. Buck Control Loop Bode Plot  
The frequency of the zero created by the ESR of the output  
VLDO is the LDO selected output voltage,  
RU is the “upper” resistor of the LDO resistor divider,  
RL is the “lower” resistor of the LDO resistor divider.  
capacitor CO is calculated as:  
Figure 31 describes the 34701 linear regulator circuit with  
the resistor divider RU, RL setting the output voltage VLDO.  
1
----------------------------  
fzESR  
=
2COESR  
Where CO is the value of the buck regulator output  
capacitor, and ESR is the equivalent series resistance of the  
output capacitor.  
2.8 V to 6.0 V Input  
MC34701  
VIN1  
The frequency of the compensating network pole can be  
calculated as follows:  
LDRV  
CS  
1
------------------------------------------  
2C2  
fpc  
=
V
R
LDO  
S
R1R3  
--------------------------  
LDO  
LFB  
R1 + R3  
R
U
C
LDO  
The well designed and compensated buck regulator  
should yield at least 45 deg. phase margin m of its overall  
loop as depicted in the Figure 30, page 31.  
R
L
LCMP  
LDO  
Compensation  
Selecting Buck Regulator Output Voltage  
The 34701 buck regulator output voltage can be set by  
selecting the right value of the resistors R1, R2 and R4, and  
can be determined from the following formula (see Figure 29,  
page 30 for the component references):  
Figure 31. 34701Linear Regulator Circuit  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
31  
TYPICAL APPLICATIONS  
NOTE: Freescale does not assume liability, endorse, or warrant  
components from external manufacturers referenced in figures  
or tables. Although Freescale offers component  
recommendations, it is the customer’s responsibility to validate  
their application.  
Linear Regulator Current Limit  
As described in the Linear Regulator Functional  
Description section, the current limit of the linear regulator  
can be adjusted by means of an external current sense  
resistor RS. The voltage drop caused by the regulator output  
current flowing through the current sense resistor RS is  
sensed between the LDO and the CS pins. When the sensed  
voltage exceeds 50mV (typical), the current limit timer starts  
to time out while the control circuit limits the output current. If  
the over-current condition lasts for more than 10ms, the linear  
regulator is shut off and turned on again after 100ms. This  
type of operation provides equivalent protection to the analog  
“current foldback” operation.  
*When mounted to an FR4 using 0.5 sq.in. drain pad size  
The maximum power dissipation is limited by the  
maximum operating junction temperature TJmax. The  
allowed power dissipation in the given application can be  
calculated from the following expression:  
T
Jmax – TA  
-----------------------------------------------------------  
PDQmax  
R
thJC + RthCB + RthBA  
It is important to keep in mind that the amount of capacitive  
load which can be supplied by the by the linear regulator is  
limited by the setting of the LDO current limit. During the  
power-up period, the linear regulator operates in the current  
limit, supplying the current into the load of the LDO, which  
includes all the capacitors connected to the regulator output.  
If the total amount load is so large that the regulator could not  
reach its regulation voltage in 10ms during the power-up, it  
turns off and tries to power up again after 100ms. This  
situation may lead to the power-up oscillations.  
Where PD(Q)max is the power MOSFET maximum  
allowed dissipation,  
TJmax is the power MOSFET maximum operating  
junction temperature,  
TA is the ambient temperature,  
RthJC is the power MOSFET thermal resistance  
junction-to-case,  
RthCB is the thermal resistance case-to-board,  
RthBA is the thermal resistance board-to-ambient of  
the PC board.  
Linear Regulator External MOSFET  
PCB Layout Considerations  
The linear regulator uses an external N-channel power  
MOSFET to provide a pass element for the power path. The  
selection of the proper type of the external power MOSFET is  
critical for optimum performance and safe operation of the  
linear regulator.  
As with any power application, the proper PCB layout  
plays a critical role in the overall power regulator  
performance. While good careful printed circuit board layout  
significantly improves regulation parameters and  
electromagnetic compatibility (EMC) performance of the  
switching regulator, poor layout practices can lead not only to  
significant degradation of regulation and EMC parameters,  
but even to total dysfunction of the whole regulator IC.  
The power MOSFET’s threshold voltage, RDS(on), gate  
charge, capacitances and transconductance are important  
parameters for the stable operation of the linear regulator  
while the package of the power MOSFET determines the  
maximum power dissipation, and hence the maximum output  
current for the required input-to-output voltage drop. The  
power dissipation of the external MOSFET can be calculated  
from the simple formula:  
Extreme care should be taken when laying out the ground  
of the regulator circuit. In order to avoid any inductive or  
capacitive coupling of the switching regulator noise into the  
sensitive analog control circuits, the noisy power ground and  
the clean quiet signal ground should be well separated on the  
printed circuit board, and connected only at one connection  
point. The power routing should be made by heavy traces or  
areas of copper. The power path and its return should be  
placed, if possible, atop each other on the different layers or  
opposite sides of the PC board. The switching regulator input  
and output capacitors should be physically placed very close  
to the power pins (VIN2, SW, PGND) of the 34701 switching  
regulator; and their ground pins, together with the 34701  
power ground pins (PGND), should be connected by a single  
island of the power ground copper to create the “single-point”  
grounding. Figure 32 illustrates the 34701 switching regulator  
grounding concept. The bootstrap capacitor Cb should be  
tightly connected to the integrated circuit as well.  
PDQ= ILDO  VIN – VLDO  
Where PD(Q) is the power MOSFET power dissipation  
VIN is the LDO input voltage,  
VLDO is the LDO output voltage,  
ILDO is the LDO output load current.  
Table 10 shows the recommended power MOSFET types  
for the 34701 linear regulator, their typical power dissipation,  
and thermal resistance junction-to-case.  
Table 10. Recommended Power MOSFETs  
Part No.  
Package  
Typ. PD  
RthJ-C  
IRL2703S  
D2PAK  
DPAK  
2.0W  
3.3°C/W  
MTD20N03HDL  
1.75W*  
1.67°C/W  
34701  
Analog Integrated Circuit Device Data  
32  
Freescale Semiconductor  
TYPICAL APPLICATIONS  
The same guidelines as those for the layout of the main  
switching buck regulator should be applied to the layout of the  
low power auxiliary boost regulator and to some extent, the  
power path of the linear regulator.  
Vin = 5.0 V  
VBST  
BOOT  
Cb  
VIN2  
SW  
To L oad  
Vout = 1.5 V  
INV  
Vout Return  
PGND  
GND  
Power  
Ground  
Signal  
Ground  
Figure 32. 34701 Buck Regulator Layout  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
33  
TYPICAL APPLICATIONS  
VIN1  
VIN  
+3.3V  
Supply  
Voltage  
VDDI  
VDDI  
Internal  
Supply  
CIN  
10uF  
1.0 uF  
VDDI  
VBST  
VBD  
8.0V  
VBST  
VBST  
Power  
Enable  
7.75V  
CBST  
10uF  
LDRV  
-
QLDO  
+
Vref  
CS  
10uH  
LBST  
VDDI  
Vref  
VDDI  
RS  
0.022 R  
Linear  
Regulator  
Control  
VLDO=3.3V  
@1.0A  
LDO  
Q5  
Boost  
Control  
Bandgap  
Voltage  
Reference  
Vref  
Vref  
I-lim  
4.7k  
1.5k  
LFB  
+3.3V  
CLDO  
5 x 2.2 uF  
VDDI  
or  
EN1  
EN2  
VLDO  
LCMP  
100pF  
1.5k  
Pow. Seq.  
VLDO  
Q4  
Power  
Power  
Down  
6.8nF  
Sequencing  
Voltage Margining  
W-dog Timer  
5.1k  
VBST  
UVLO  
VBST  
RST  
RST  
to MCU  
Reset  
Reset  
Control  
VOUT  
BOOT  
VBST  
Q6  
Current  
Limit  
SysCon  
INV  
POR  
Timer  
VIN2  
(2)  
RT  
I2C  
Control  
+3.3V  
Supply  
Voltage  
VDDI  
LFB  
Buck  
HS  
&
LS  
Driver  
CIN  
Rt  
100k  
Ct  
Q1  
Q2  
2 x 22 uF  
I2C  
Control  
100nF  
SysCon  
SoftSt  
DB  
0.1uF  
L1  
CB  
VOUT=1.8V  
Thermal  
Limit  
Buck  
Control  
Logic  
SW  
(2)  
4.7 uH  
+
ADDR  
SDA  
CO  
100 uF  
Rpd  
I2C  
PGND  
(2)  
300k  
10k  
Interface  
Error  
Amp.  
PWM  
To Reset  
Control  
0.8V  
+
Switcher  
Comp.  
SCL  
Oscillator  
300kHz  
+
-
INV  
39k  
-
VOUT  
Q3  
Ramp  
Gen.  
Rb  
27k  
300  
VOUT  
470pF  
Pow.  
Seq.  
FREQ  
RF  
(4)  
GND  
CLKSYN  
CLKSEL  
(Optional)  
Figure 33. Simplified Block Diagram and Basic Application  
34701  
Analog Integrated Circuit Device Data  
34  
Freescale Semiconductor  
TYPICAL APPLICATIONS  
D
D
D
D
G N  
G N  
G N  
G N  
2 5  
2 4  
9
8
O B O T  
1
Figure 34. 34701 Typical Application Circuit  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
35  
PACKAGE DIMENSIONS  
PACKAGE DIMENSIONS  
Important: For the most current package revision, visit www.freescale.com and perform a “keyword” search for the “98A”  
number.  
EW SUFFIX  
32-PIN  
98AARH99137A  
REVISION B  
34701  
Analog Integrated Circuit Device Data  
36  
Freescale Semiconductor  
PACKAGE DIMENSIONS  
EW SUFFIX  
32-PIN  
98AARH99137A  
REVISION B  
34701  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
37  
REVISION HISTORY  
REVISION HISTORY  
REVISION  
5.0  
DATE  
2/2006  
2/2007  
DESCRIPTION OF CHANGES  
•
Changed Document Order No.  
•
•
•
•
Updated to the current Freescale form and style.  
Changed the status from Advance Information to Final.  
Added Peak Package Reflow Temperature During Reflow(2)  
Added Notes (2) and (3)  
6.0  
(3)  
,
•
•
Added MCZ34701EW/R2 to the ordering information  
Updated the 98ARH99137A package drawing to Rev. B  
8/2007  
7.0  
34701  
Analog Integrated Circuit Device Data  
38  
Freescale Semiconductor  
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MC34701  
Rev 7.0  
8/2007  

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