MF1S5035DUH/L,005_技术文档

MF1S503x

MIFARE Classic 1K - Mainstream contactless smart card IC

for fast and easy solution development

Rev. 3.1 — 21 February 2011

194031

Product data sheet

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1. General description

NXP Semiconductors has developed the MIFARE MF1S503x to be used in a contactless

smart card according to ISO/IEC 14443 Type A.

The MIFARE MF1S503x IC is used in applications like public transport ticketing and can

also be used for various other applications.

1.1 Anti-collision

An intelligent anti-collision function allows to operate more than one card in the field

simultaneously. The anticollision algorithm selects each card individually and ensures that

the execution of a transaction with a selected card is performed correctly without

interference from another card in the field.

energy

MIFARE

CARD PCD

data

001aam199

Fig 1. MIFARE card reader

1.2 Simple integration and user convenience

The MF1S503x is designed for simple integration and user convenience which allows

complete ticketing transactions to be handled in less than 100 ms.

1.3 Security

• Manufacturer programmed 4 byte Non-Unique IDentifier (NUID) for each device

• Mutual three pass authentication (ISO/IEC DIS 9798-2)

• Individual set of two keys per sector to support multi-application with key hierarchy

1.4 Delivery options

• Die on wafer, bumped die on wafer

• MOA2, MOA4, MOA8 and MOB6 contactless module

MF1S503x

NXP Semiconductors

MIFARE Classic 1K - Mainstream contactless smart card IC

2. Features and benefits

Contactless transmission of data and

Operating distance up to 100 mm

depending on antenna geometry and

reader configuration

supply energy

Operating frequency of 13.56 MHz

Data transfer of 106 kbit/s

Anti-collision

Data integrity of 16-bit CRC, parity, bit

coding, bit counting

Typical ticketing transaction time of less

than 100 ms (including backup

management)

2.1 EEPROM

1 kB, organized in 16 sectors of 4 blocks User definable access conditions for

(one block consists of 16 byte)

each memory block

Data retention time of 10 years

Write endurance 100.000 cycles

3. Applications

Public transportation

Electronic toll collection

School and campus cards

Internet cafés

Access management

Car parking

Employee cards

Loyalty

4. Quick reference data

Table 1.

Quick reference data

Symbol

Parameter

Conditions

Min

14.4

-

Typ

Max

17.4

-

Unit

pF

[1]

C_i

f_i

input capacitance

input frequency

16.1

13.56

MHz

EEPROM characteristics

t_ret

retention time

T_amb= 22 °C

10

-

year

N_endu(W)

write endurance

100000

200000

cycle

[1] LCR meter, T_amb= 22 °C, f_i= 13.56 MHz, 2 V RMS.

MF1S503x

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Product data sheet

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Rev. 3.1 — 21 February 2011

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MF1S503x

NXP Semiconductors

MIFARE Classic 1K - Mainstream contactless smart card IC

5. Ordering information

Table 2.

Ordering information

Type number

Package

Commercial Name

Name

Description

8 inch wafer, 120 μm thickness, laser diced, on film frame

Version

MF1S5035DUD/L FFC Bump

-

not

carrier, electronic fail die marking according to SECSII format), applicable

Au bumps

MF1S5035DUH/L FFC

-

8 inch wafer, 120 μm thickness, laser diced, on film frame

carrier, electronic fail die marking according to SECSII format) applicable

not

MF1S5037DUG

MF1S5037DUA

FFC Bump

FFC

8 inch wafer, 150 μm thickness, on film frame carrier, electronic not

fail die marking according to SECSII format), Au bumps

applicable

8 inch wafer, 150 μm thickness, on film frame carrier, electronic not

fail die marking according to SECSII format)

applicable

MF1S5030DA3

MF1S5030DA4

MF1S5030DA6

MF1S5030DA8

MOA2

MOA4

MOB6

MOA8

PLLMC

plastic leadless module carrier package; 35 mm wide tape

SOT500-1

SOT500-2

SOT500-3

SOT500-4

6. Block diagram

UART

ISO/IEC 14443A

TYPE A

RF

INTERFACE

CRYPTO1

POWER ON

RESET

RNG

CRC

VOLTAGE

REGULATOR

CLOCK

INPUT FILTER

RESET

GENERATOR

LOGIC UNIT

EEPROM

001aan006

Fig 2. Block diagram of MF1S503x

MF1S503x

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Product data sheet

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MIFARE Classic 1K - Mainstream contactless smart card IC

7. Pinning information

7.1 Pinning

The pinning for the MF1S503xDAx is shown as an example in Figure 3 for the MOA4

contactless module. For the contactless modules MOA2, MOB6 and MOA8, the pinning is

analogous and not explicitly shown.

LA

top view

LB

001aan002

Fig 3. Pin configuration for SOT500-2 (MOA4)

Table 3.

Pin allocation table

Symbol

LA

Description

LA

Antenna coil connection LA

Antenna coil connection LB

LB

MF1S503x

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MIFARE Classic 1K - Mainstream contactless smart card IC

8. Functional description

8.1 Block description

The MF1S503x chip consists of a 1 kB EEPROM, RF interface and Digital Control Unit.

Energy and data are transferred via an antenna consisting of a coil with a small number of

turns which is directly connected to the MF1S503x. No further external components are

necessary. Refer to the document Ref. 1 for details on antenna design.

• RF interface:

– Modulator/demodulator

– Rectifier

– Clock regenerator

– Power-On Reset (POR)

– Voltage regulator

• Anti-collision: Multiple cards in the field may be selected and managed in sequence

• Authentication: Preceding any memory operation the authentication procedure

ensures that access to a block is only possible via the two keys specified for each

block

• Control and Arithmetic Logic Unit: Values are stored in a special redundant format and

can be incremented and decremented

• EEPROM interface

• Crypto unit: The CRYPTO1 stream cipher of the MF1S503x is used for authentication

and encryption of data exchange.

• EEPROM: 1 kB is organized in 16 sectors with 4 blocks each. A block contains

16 bytes. The last block of each sector is called “trailer”, which contains two secret

keys and programmable access conditions for each block in this sector.

8.2 Communication principle

The commands are initiated by the reader and controlled by the Digital Control Unit of the

MF1S503x. The command response is depending on the state of the IC and for memory

operations also on the access conditions valid for the corresponding sector.

8.2.1 Request standard/all

After Power-On Reset (POR) the card answers to a request REQA or wakeup WUPA

command with the answer to request code (see Section 9.4, ATQA according to

ISO/IEC 14443A).

8.2.2 Anti-collision loop

In the anti-collision loop the identifier of a card is read. If there are several cards in the

operating field of the reader, they can be distinguished by their identifier and one can be

selected (select card) for further transactions. The unselected cards return to the idle state

and wait for a new request command.

Remark: The identifier retrieved from the card is not defined to be unique. For further

information regarding handling of non-unique identifiers see Ref. 11.

MF1S503x

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MIFARE Classic 1K - Mainstream contactless smart card IC

8.2.3 Select card

With the select card command the reader selects one individual card for authentication

and memory related operations. The card returns the Select Acknowledge (SAK) code

which determines the type of the selected card, see Section 9.4. For further details refer to

the document Ref. 7.

8.2.4 Three pass authentication

After selection of a card the reader specifies the memory location of the following memory

access and uses the corresponding key for the three pass authentication procedure. After

a successful authentication all memory operations are encrypted.

Transaction Sequence

Typical Transaction Time

POR

REQUEST STANDARD

REQUEST ALL

Identification and Selection

Procedure

ANTICOLLISION LOOP

GET IDENTIFIER

~2.5 ms without collision

+~1 ms for each collision

SELECT CARD

Authentication

Procedure

3 PASS AUTHENTICATION

ON SPECIFIC SECTOR

~2 ms

Memory

Operations

READ

BLOCK

WRITE

BLOCK

DECRE-

MENT

INCRE-

MENT

RE-

STORE

HALT

~2.5 ms read block

~6.0 ms write block

~2.5 ms de-/increment

~4.5 ms transfer

TRANSFER

001aan017

Fig 4. Three pass authentication

MF1S503x

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MF1S503x

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MIFARE Classic 1K - Mainstream contactless smart card IC

8.2.5 Memory operations

After authentication any of the following operations may be performed:

• Read block

• Write block

• Decrement: Decrements the contents of a block and stores the result in an internal

data-register

• Increment: Increments the contents of a block and stores the result in an internal

data-register

• Restore: Moves the contents of a block into an internal data-register

• Transfer: Writes the contents of the temporary internal data-register to a value block

8.3 Data integrity

Following mechanisms are implemented in the contactless communication link between

reader and card to ensure very reliable data transmission:

• 16 bits CRC per block

• Parity bits for each byte

• Bit count checking

• Bit coding to distinguish between “1”, “0” and “no information”

• Channel monitoring (protocol sequence and bit stream analysis)

8.4 Three pass authentication sequence

1. The reader specifies the sector to be accessed and chooses key A or B.

2. The card reads the secret key and the access conditions from the sector trailer. Then

the card sends a random number as the challenge to the reader (pass one).

3. The reader calculates the response using the secret key and additional input. The

response, together with a random challenge from the reader, is then transmitted to the

card (pass two).

4. The card verifies the response of the reader by comparing it with its own challenge

and then it calculates the response to the challenge and transmits it (pass three).

5. The reader verifies the response of the card by comparing it to its own challenge.

After transmission of the first random challenge the communication between card and

reader is encrypted.

MF1S503x

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Product data sheet

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MIFARE Classic 1K - Mainstream contactless smart card IC

8.5 RF interface

The RF-interface is according to the standard for contactless smart cards

ISO/IEC 14443 A.

For operation, the carrier field from the reader always needs to be present (with short

pauses when transmitting), as it is used for the power supply of the card.

For both directions of data communication there is only one start bit at the beginning of

each frame. Each byte is transmitted with a parity bit (odd parity) at the end. The LSB of

the byte with the lowest address of the selected block is transmitted first. The maximum

frame length is 163 bits (16 data bytes + 2 CRC bytes = 16 × 9 + 2 × 9 + 1 start bit).

8.6 Memory organization

The 1024 × 8 bit EEPROM memory is organized in 16 sectors of 4 blocks. One block

contains 16 bytes.

Byte Number within a Block

Sector

15

Block

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

Key B

Description

Sector Trailer 15

Data

3

2

1

0

3

2

1

0

Key A

Access Bits

Data

14

Key A

Access Bits

Key B

Sector Trailer 14

Data

:

1

3

2

1

0

3

2

1

0

Key A

Access Bits

Key B

Sector Trailer 1

Data

0

Access Bits

Sector Trailer 0

Data

Manufacturer Data

Manufacturer Block

001aan011

Fig 5. Memory organization

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MIFARE Classic 1K - Mainstream contactless smart card IC

8.6.1 Manufacturer block

This is the first data block (block 0) of the first sector (sector 0). It contains the IC

manufacturer data. This block is programmed and write protected in the production test.

Block 0/Sector 0

Byte

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

NUID

Manufacturer Data

001aan010

Fig 6. Manufacturer block

8.6.2 Data blocks

All sectors contain 3 blocks of 16 bytes for storing data (Sector 0 contains only two data

blocks and the read-only manufacturer block).

The data blocks can be configured by the access bits as

• read/write blocks

• value blocks

Value blocks can be used for e.g. electronic purse applications, where additional

commands like increment and decrement for direct control of the stored value are

provided.

A successful authentication has to be performed to allow any memory operation.

Remark: The default content of the data blocks at delivery is not defined.

8.6.2.1 Value blocks

The value blocks allow performing electronic purse functions (valid commands: read,

write, increment, decrement, restore, transfer). Value blocks have a fixed data format

which permits error detection and correction and a backup management.

A value block can only be generated through a write operation in the value block format:

• Value: Signifies a signed 4-byte value. The lowest significant byte of a value is stored

in the lowest address byte. Negative values are stored in standard 2´s complement

format. For reasons of data integrity and security, a value is stored three times, twice

non-inverted and once inverted.

• Adr: Signifies a 1-byte address, which can be used to save the storage address of a

block, when implementing a powerful backup management. The address byte is

stored four times, twice inverted and non-inverted. During increment, decrement,

restore and transfer operations the address remains unchanged. It can only be

altered via a write command.

Byte Number

Description

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

value

adr adr adr adr

001aan018

Fig 7. Value blocks

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MIFARE Classic 1K - Mainstream contactless smart card IC

8.6.3 Sector trailer (block 3)

The sector trailer is the last block (block 3) in one sector. Each sector has a sector trailer

containing the

• secret keys A and B (optional), which return logical “0”s when read and

• the access conditions for the blocks of that sector, which are stored in bytes 6...9. The

access bits also specify the type (data or value) of the data blocks.

If key B is not needed, the last 6 bytes of the sector trailer can be used as data bytes. The

access bits for the sector trailer have to be configured accordingly, see Section 8.7.2.

Byte 9 of the sector trailer is available for user data. For this byte the same access rights

as for byte 6, 7 and 8 apply.

When the sector trailer is read, the key bytes are blanked out by returning logical zeros. If

Key B is configured to be readable, the data stored in bytes 10 to 15 is returned, see

Section 8.7.2.

All keys are set to FFFFFFFFFFFFh at chip delivery.

Byte Number

Description

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

Key A

Access Bits

Key B (optional)

001aan013

Fig 8. Sector trailer

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8.7 Memory access

Before any memory operation can be carried out, the card has to be selected and

authenticated as described in Section 8.2. The possible memory operations for an

addressed block depend on the key used and the access conditions stored in the

associated sector trailer.

Table 4.

Operation

Read

Memory operations

Description

Valid for Block Type

reads one memory block

read/write, value and sector trailer

value

Write

writes one memory block

Increment

increments the contents of a block and

stores the result in the internal data

register

Decrement

decrements the contents of a block and value

stores the result in the internal data

register

Transfer

Restore

writes the contents of the internal data

register to a block

value

reads the contents of a block into the

internal data register

value

8.7.1 Access conditions

The access conditions for every data block and sector trailer are defined by 3 bits, which

are stored non-inverted and inverted in the sector trailer of the specified sector.

The access bits control the rights of memory access using the secret keys A and B. The

access conditions may be altered, provided one knows the relevant key and the current

access condition allows this operation.

Remark: With each memory access the internal logic verifies the format of the access

conditions. If it detects a format violation the whole sector is irreversibly blocked.

Remark: In the following description the access bits are mentioned in the non-inverted

mode only.

The internal logic of the MF1S503x ensures that the commands are executed only after a

successful authentication.

Table 5.

Access conditions

Access Bits

C1₃C2₃C3₃

C1₂C2₂C3₂

Valid Commands

Block Description

read, write

→

3

2

sector trailer

data block

read, write, increment, decrement,

transfer, restore

C1₁C2₁C3₁

C1₀C2₀C3₀

read, write, increment, decrement,

transfer, restore

→

1

0

data block

read, write, increment, decrement,

transfer, restore

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Byte Number

Description

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15

Key B (optional)

Key A

Access Bits

Bit

7

6

5

4

3

2

1

0

Byte 6

Byte 7

Byte 8

Byte 9

C2

2

C1

2

C3

2

C2

C1

3

1

0

3

2

1

0

C1

C3

C1

C3

C1

C3

C2

C3

C2

C3

C2

C3

C2

user data

001aan003

Fig 9. Access conditions

8.7.2 Access conditions for the sector trailer

Depending on the access bits for the sector trailer (block 3) the read/write access to the

keys and the access bits is specified as ‘never’, ‘key A’, ‘key B’ or key A|B’ (key A or

key B).

On chip delivery the access conditions for the sector trailers and key A are predefined as

transport configuration. Since key B may be read in the transport configuration, new cards

must be authenticated with key A. Since the access bits themselves can also be blocked,

special care has to be taken during personalization of cards.

Table 6.

Access bits Access condition for

KEYA Access bits

C1 C2 C3 read

Access conditions for the sector trailer

Remark

KEYB

write

read

write

read

write

0

1

0

1

0

1

0

1

never

key A

never

key B

never

key A

never key A

key A Key B may be read^[1]

never Key B may be read^[1]

key A|B never never

key B

never

key A

key A key A

key A Key B may be read,

transport configuration^[1]

0

1

0

1

never

key B

never

key A|B key B never

key A|B never never

key B

never

[1] for this access condition key B is readable and may be used for data

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8.7.3 Access conditions for data blocks

Depending on the access bits for data blocks (blocks 0...2) the read/write access is

specified as ‘never’, ‘key A’, ‘key B’ or ‘key A|B’ (key A or key B). The setting of the

relevant access bits defines the application and the corresponding applicable commands.

• Read/write block: the operations read and write are allowed.

• Value block: Allows the additional value operations increment, decrement, transfer

and restore. With access condition ‘001’ only read and decrement are possible which

reflects a non-rechargeable card. For access condition ‘110’ recharging is possible by

using key B.

• Manufacturer block: the read-only condition is not affected by the access bits setting!

• Key management: in transport configuration key A must be used for authentication

Table 7.

Access bits

C1 C2 C3 read

Access conditions for data blocks

Access condition for

Application

write

increment

key A|B1

decrement,

transfer,

restore

0

key A|B^[1]

key A|B1

transport

configuration

0

1

0

1

0

1

0

1

0

1

0

1

key A|B^[1]

key B^[1]

never

key B¹

never

key B¹

never

key B¹

never

read/write block

value block

never

key A|B¹

never

value block

read/write block

key B^[1]

never

[1] if Key B may be read in the corresponding Sector Trailer it cannot serve for authentication (all grey marked

lines in previous table). As a consequences, if the reader authenticates any block of a sector which uses

the grey marked access conditions and using key B, the card will refuse any subsequent memory access

after authentication.

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9. Command overview

The MIFARE Classic card activation follows the ISO/IEC 14443-3 type A. After the

MIFARE Classic card has been selected, it can either be deactivated using the

ISO/IEC 14443 Halt command, or the MIFARE Classic commands can be performed. For

more details about the card activation refer to Ref. 9.

9.1 MIFARE Classic command overview

All MIFARE Classic commands use the MIFARE Crypto1 and require an authentication.

All available commands for the MIFARE Classic are shown in Table 8.

Table 8.

Command overview

Command

ISO/IEC 14443

Command code

(hexadecimal)

Request

Wake-up

REQA

26h (7 bit)

52h (7 bit)

93h 20h

93h 70h

50h 00h

60h

WUPA

Anti-collision CL1

Select CL1

Anti-collision CL1

Select CL1

Halt

Authentication with Key A

Authentication with Key B

MIFARE Read

-

61h

30h

MIFARE Write

A0h

MIFARE Decrement

MIFARE Increment

MIFARE Restore

MIFARE Transfer

C0h

C1h

C2h

B0h

All the commands use the coding and framing as described in Ref. 8 and Ref. 9 if not

otherwise specified.

9.2 Timings

The timing shown in this document are not to scale and values are rounded to 1 μs.

All the given times refer to the data frames including start of communication and end of

communication, but do not include the encoding (like the Miller pulses).

Consequently a data frame sent by the PCD contains the start of communication (1 “start

bit”) and the end of communication (one logic 0 + 1 bit length of unmodulated carrier).

A data frame sent by the PICC contains the start of communication (1 “start bit”) and the

end of communication (1 bit length of no subcarrier).

All timing can be measured according to ISO/IEC 14443-3 frame specification as shown

for the Frame Delay Time in Figure 10. For more details refer to Ref. 8 and Ref. 9.

The frame delay time from PICC to PCD must be at least 87 μs.

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last data bit transmitted by the PCD

FDT = (n* 128 + 84)/fc

first modulation of the PICC

128/fc

logic ''1''

256/fc

end of communication (E)

128/fc

start of

communication (S)

FDT = (n* 128 + 20)/fc

128/fc

logic ''0''

256/fc

128/fc

start of

end of communication (E)

communication (S)

T

, T

ACK NAK

001aan008

Fig 10. Frame Delay Time (from PCD to PICC) and T_ACKand T_NAK

Remark: Due to the coding of commands, the measured timings usually exclude (a part

of) the end of communication. This needs to be considered, when comparing the specified

with the measured times.

9.3 MIFARE Classic ACK and NAK

The MIFARE Classic uses a 4 bit ACK/NAK as shown in Table 9.

Table 9.

MIFARE ACK and NAK

Code (4-bit)

Ah

ACK/NAK

Acknowledge (ACK)

NAK

0h to 9h, Bh to Fh

9.4 ATQA and SAK responses

For details on the type identification procedure please refer to Ref. 7.

The MF1S503x answers to a REQA or WUPA command with the ATQA value shown in

Table 10 and to a Select CL1 command with the SAK value shown in Table 11.

Table 10. ATQA response of the MF1S503x

Bit Number

Response

Hex Value

16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

ATQA

00 04h

0

1

0

Table 11. SAK response of the MF1S503x

Bit Number

Response

Hex Value

8

7

6

5

4

3

2

1

SAK

08h

0

1

0

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10. MIFARE Classic commands

10.1 MIFARE Authentication

The MIFARE authentication is a 3-pass mutual authentication which needs two pairs of

command-response. These two parts, MIFARE authentication part 1 and part 2 are shown

in Figure 11, Figure 12 and Table 12.

Table 13 shows the required timing.

PCD

Auth

Addr

CRC

Token RB

PICC ,,ACK''

T

ACK

368 μs

359 μs

PICC ,,NAK''

NAK

59 μs

T

TimeOut

Time out

001aan004

Fig 11. MIFARE Authentication part 1

PCD

Token AB

Token BA

PICC ,,ACK''

T

ACK

708 μs

359 μs

PICC ,,NAK''

NAK

T

NAK

59 μs

T

TimeOut

Time out

001aan005

Fig 12. MIFARE Authentication part 2

Table 12. MIFARE authentication command

Name

Code

Description

Length

1 byte

Auth (with Key A) 60h

Auth (with Key B) 61h

Authentication with Key A

Authentication with Key B

Addr

-

MIFARE Block address (00h to 3Fh) 1 byte

CRC

-

CRC according to Ref. 9

Challenge 1 (Random Number)

Challenge 2 (encrypted data)

see Section 9.3

2 bytes

4 bytes

8 bytes

4 bytes

4-bit

Token RB

Token AB

Token BA

NAK

-

see Table 9

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Table 13. MIFARE authentication timing

These times exclude the end of communication of the PCD.

T_ACKmin

71 μs

T_ACKmax

T_TimeOut

T_{NAK min}

71 μs

T_{NAK max}

T_TimeOut

1 ms

Authentication part 1

Authentication part 2

71 μs

T_TimeOut

71 μs

1 ms

Remark: The minimum required time between MIFARE Authentication part 1 and part 2 is

the minimum required FDT according to Ref. 9. There is no maximum time specified.

Remark: The MIFARE authentication and encryption requires an MIFARE reader IC (e.g.

the CL RC632). For more details about the authentication command refer to the

corresponding data sheet (e.g. Ref. 10).

10.2 MIFARE Read

The MIFARE Read requires a block address, and returns the 16 bytes of one MIFARE

Classic block. The command structure is shown in Figure 13 and Table 14.

Table 15 shows the required timing.

PCD

Cmd

Addr

CRC

Data

CRC

PICC ,,ACK''

T

ACK

368 μs

1548 μs

PICC ,,NAK''

NAK

59 μs

T

TimeOut

Time out

001aan014

Fig 13. MIFARE Read

Table 14. MIFARE Read command

Name

Cmd

Addr

CRC

Data

NAK

Code

Description

Length

30h

Read one block

1 byte

-

MIFARE Block address (00h to 3Fh) 1 byte

CRC according to Ref. 9 2 bytes

Data content of the addressed block 16 bytes

see Section 9.3 4-bit

-

see Table 9

Table 15. MIFARE Read timing

These times exclude the end of communication of the PCD.

T_ACKmin

T_ACKmax

T_{NAK min}

T_{NAK max}

T_TimeOut

5 ms

Read

71 μs

T_TimeOut

71 μs

T_TimeOut

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10.3 MIFARE Write

The MIFARE Write requires a block address, and writes 16 Bytes of data into the

addressed MIFARE Classic 1K block. It needs two pairs of command-response. These

two parts, MIFARE Write part 1 and part 2 are shown in Figure 14 and Figure 15 and

Table 16.

Table 17 shows the required timing.

PCD

Cmd

Addr

CRC

ACK

PICC ,,ACK''

T

ACK

368 μs

59 μs

PICC ,,NAK''

NAK

59 μs

T

TimeOut

Time out

001aan015

Fig 14. MIFARE Write part 1

PCD

Data

CRC

ACK

PICC ,,ACK''

T

ACK

1558 μs

59 μs

PICC ,,NAK''

NAK

59 μs

T

TimeOut

Time out

001aan016

Fig 15. MIFARE Write part 2

Table 16. MIFARE Write command

Name

Cmd

Addr

Code

A0h

-

Description

Read one block

Length

1 byte

MIFARE Block or Page address (00h 1 byte

to 3Fh)

CRC

Data

NAK

-

CRC according to Ref. 9

Data

2 bytes

16 bytes

4-bit

-

see Table 9

see Section 9.3

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Table 17. MIFARE Write timing

These times exclude the end of communication of the PCD.

T_ACKmin

71 μs

T_ACKmax

T_TimeOut

T_{NAK min}

71 μs

T_{NAK max}

T_TimeOut

5 ms

Write part 1

Write part 2

71 μs

T_TimeOut

71 μs

10 ms

Remark: The minimum required time between MIFARE Write part 1 and part 2 is the

minimum required FDT acc. to Ref. 9. There is no maximum time specified.

10.4 MIFARE Increment, Decrement and Restore

The MIFARE Increment requires a source block address and an operand. It adds the

operand to the value of the addressed block, and stores the result in a volatile memory.

The MIFARE Decrement requires a source block address and an operand. It subtracts the

operand from the value of the addressed block, and stores the result in a volatile memory.

The MIFARE Restore requires a source block address. It copies the value of the

addressed block into a volatile memory.

These two parts of each command are shown in Figure 16 and Figure 17 and Table 18.

Table 19 shows the required timing.

PCD

Cmd

Addr

CRC

ACK

PICC ,,ACK''

T

ACK

NAK

368 μs

59 μs

PICC ,,NAK''

NAK

T

59 μs

T

TimeOut

Time out

001aan015

Fig 16. MIFARE Increment, Decrement, Restore part 1

PCD

Data

CRC

PICC ,,ACK''

538 μs

PICC ,,NAK''

NAK

T

NAK

59 μs

T

TimeOut

Time out

001aan009

(1) Increment, Decrement and Restore part 2 does not acknowledge

Fig 17. MIFARE Increment, Decrement, Restore part 2

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Table 18. MIFARE Increment, Decrement and Restore command

Name

Cmd

Addr

CRC

Data

NAK

Code

Description

Increment

Decrement

Restore

Length

1 byte

C1h

C0h

C2h

-

MIFARE source block address (00h to 3Fh) 1 byte

-

CRC according to Ref. 9

Operand (4 byte signed integer)

see Section 9.3

2 bytes

4 bytes

4-bit

-

see Table 9

Table 19. MIFARE Increment, Decrement and Restore timing

These times exclude the end of communication of the PCD.

T_ACKmin

T_ACKmax

T_{NAK min}

T_{NAK max}

T_TimeOut

Increment,

71 μs

T_TimeOut

71 μs

T_TimeOut

5 ms

Decrement, and

Restore part 1

Increment,

71 μs

T_TimeOut

71 μs

T_TimeOut

5 ms

Decrement, and

Restore part 2

Remark: The minimum required time between MIFARE Increment, Decrement, and

Restore part 1 and part 2 is the minimum required FDT according too Ref. 9. There is no

maximum time specified.

Remark: The MIFARE Increment, Decrement, and Restore commands require a MIFARE

Transfer to store the value into a destination block.

Remark: The MIFARE Increment, Decrement, and Restore command part 2 does not

provide an acknowledgement, so the regular time-out has to be used instead.

10.5 MIFARE Transfer

The MIFARE Transfer requires a destination block address, and writes the value stored in

the volatile memory into one MIFARE Classic block. The command structure is shown in

Figure 18 and Table 20.

Table 21 shows the required timing.

PCD

Cmd

Addr

CRC

ACK

PICC ,,ACK''

T

ACK

368 μs

59 μs

PICC ,,NAK''

NAK

59 μs

T

TimeOut

Time out

001aan015

Fig 18. MIFARE Transfer

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Table 20. MIFARE Transfer command

Name

Cmd

Addr

Code

B0h

-

Description

Length

1 byte

Write value into destination block

MIFARE destination block address

(00h to 3Fh)

CRC

NAK

-

CRC according to Ref. 9

see Section 9.3

2 bytes

4-bit

see Table 9

Table 21. MIFARE Transfer timing

These times exclude the end of communication of the PCD.

T_ACKmin

T_ACKmax

T_{NAK min}

T_{NAK max}

T_TimeOut

Transfer

71 μs

T_TimeOut

71 μs

T_TimeOut

10 ms

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11. Limiting values

Table 22. Limiting values ^[1][2]

In accordance with the Absolute Maximum Rating System (IEC 60134).

Symbol

I_I

Parameter

Min

-

Max

30

Unit

mA

mW

°C

input current

P_tot/pack

T_stg

total power dissipation per package

storage temperature

ambient temperature

electrostatic discharge voltage

-

200

125

70

−55

−25

2

T_amb

°C

[3]

V_ESD

-

kV

[1] Stresses above one or more of the limiting values may cause permanent damage to the device

[2] Exposure to limiting values for extended periods may affect device reliability

[3] MIL Standard 883-C method 3015; Human body model: C = 100 pF, R = 1.5 kΩ

12. Characteristics

Table 23. Characteristics

Symbol

Parameter

Conditions

Min

14.4

-

Typ

Max

17.4

-

Unit

[1]

C_i

f_i

input capacitance

input frequency

16.1

13.56

pF

MHz

EEPROM characteristics

t_ret

retention time

T_amb= 22 °C

10

-

year

N_endu(W)

write endurance

100000

200000

cycle

[1] LCR meter, T_amb= 22 °C, f_i= 13.56 MHz, 2 V RMS.

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13. Wafer specification

For more details on the wafer delivery forms see Ref. 6.

Table 24. Wafer specifications MF1S5035DUx/L

Wafer

diameter

200 mm typical (8 inches)

210 mm

maximum diameter after foil expansion

thickness

120 μm ± 15 μm

not applicable

27720

flatness

Potential Good Dies per Wafer (PGDW)

Wafer backside

material

Si

treatment

ground and stress relieve

R_amax = 0.5 μm

R_tmax = 5 μm

roughness

Chip dimensions

step size

x = 1062 μm

y = 1012 μm

gap between chips^[1]

typical = 27 μm

minimum = 5 μm

Passivation

type

sandwich structure

PSG / nitride

material

thickness

500 nm / 600 nm

[1] the gap between chips may vary due to changing foil expansion

Table 25. Wafer specifications MF1S5037DUx

Wafer

diameter

200 mm typical (8 inches)

thickness

120 μm ± 15 μm

not applicable

25060

flatness

Potential Good Dies per Wafer (PGDW)

Wafer backside

material

Si

treatment

ground and stress relieve

R_amax = 0.5 μm

R_tmax = 5 μm

roughness

Chip dimensions

step size

x = 1100 μm

y = 1030 μm

x = 86,4 μm

y = 66,4 μm

scribe line

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Table 25. Wafer specifications MF1S5037DUx …continued

Passivation

type

sandwich structure

PSG / nitride

material

thickness

500 nm / 600 nm

[1] the gap between chips may vary due to changing foil expansion

Table 26. Bond pad specifications

Bond pads (substrate connected to VSS)

size (metallization)

LA, LB, VSS^[1]= 118 μm × 118 μm

TESTIO^[1]= 103 μm × 118 μm

LA, LB, VSS^[1]= 90 μm × 90 μm

TESTIO^[1]= 75 μm × 90 μm

Al-Cu

size (pad opening)

material

thickness

850 nm

[1] Pads VSS and TESTIO are disconnected when wafer is sawn.

Table 27. Bump specifications

Au bump (substrate connected to VSS)

material

> 99.9 % pure Au

35 to 80 HV 0.005

> 70 MPa

hardness

shear strength

height

18 μm

height uniformity

within a die = ±2 μm

within a wafer = ±3 μm

wafer to wafer = ±4 μm

minimum = ±1.5 μm

LA, LB, VSS^[1]= 104 μm × 104 μm

TESTIO^[1]= 89 μm × 104 μm

±5 μm

flatness

size

size variation

under bump metallization

sputtered TiW

[1] Pads VSS and TESTIO are disconnected when wafer is sawn.

13.1 Fail die identification

Electronic wafer mapping covers the electrical test results and additionally the results of

mechanical/visual inspection.

No ink dots are applied.

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14. Package outline

For more details on the contactless modules MOA2, MOA4, MOA8 and MOB6 please

refer to Ref. 2, Ref. 3, Ref. 4 and Ref. 5.

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PLLMC: plastic leadless module carrier package; 35 mm wide tape

SOT500-2

X

D

A

detail X

0

10

20 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

max.

UNIT

D

For unspecified dimensions see PLLMC-drawing given in the subpackage code.

35.05

34.95

mm

0.33

Note

1. Total package thickness, exclusive punching burr.

REFERENCES

JEDEC

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEITA

03-09-17

06-05-22

SOT500-2

- - -

Fig 19. Package outline SOT500-2

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PLLMC: plastic leadless module carrier package; 35 mm wide tape

SOT500-3

X

D

A

detail X

0

10

20 mm

scale

DIMENSIONS (mm are the original dimensions)

(1)

A

max.

UNIT

D

For unspecified dimensions see PLLMC-drawing given in the subpackage code.

35.05

34.95

mm

0.25

Note

1. Total package thickness, exclusive punching burr.

REFERENCES

JEDEC

OUTLINE

VERSION

EUROPEAN

PROJECTION

ISSUE DATE

IEC

JEITA

07-10-18

SOT500-3

- - -

Fig 20. Package outline SOT500-3

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PLLMC: plastic leadless module carrier package; 35 mm wide tape

SOT500-4

X

D

A

detail X

0

10

20 mm

scale

Dimensions

Unit

(1)

A

D

For unspecified dimensions see PLLMC-drawing given in the subpackage code.

max 0.26 35.05

mm nom

min

35.00

34.95

Note

1. Total package thickness, exclusive punching burr.

sot500-4_po

References

Outline

version

European

projection

Issue date

IEC

- - -

JEDEC

- - -

JEITA

- - -

11-02-18

SOT500-4

Fig 21. Package outline SOT500-4

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15. Bare die outline

x (μm)

y (μm)

(1)

Chip Step

1062

1012

Pad size

LA, LB, VSS

TESTIO

90

75

90

Bump size

LA, LB, VSS

TESTIO

104

89

104

(1)

typ. 27.0

min. 5.0

401.3

166.5

(1)

typ. 27.0

min. 5.0

LA

TESTIO

typ.

1012.0

(1)

799.4

793.7

VSS

LB

196.8

MF1S5035

Y

(2)

149.1

X

861.5

typ. 1062.0

(1)

Note

1. The air gap and thus the step size may vary due to varying foil expansion

2. All dimensions in μm, pad locations measured from outher sealring edge (see detail)

001aan012

Fig 22. Bare die outline and chip orientation MF1S5035

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x (μm)

y (μm)

Chip Step

1100

1030

Pad size

LA, LB, VSS

TESTIO

90

75

90

Bump size

LA, LB, VSS

TESTIO

104

89

104

86.4

401.3

166.5

66.4

LA

TESTIO

1030.0

799.4

793.7

VSS

LB

196.8

MF1S5037

Y

(1)

149.1

X

861.5

1100.0

Note

1. All dimensions in μm, pad locations measured from outher sealring edge (see detail)

001aan001

Fig 23. Bare die outline and chip orientation MF1S5037

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16. Abbreviations

Table 28. Abbreviations and symbols

Acronym Description

ACK

ACKnowledge

ATQA

CRC

EEPROM

FDT

Answer To reQuest, Type A

Cyclic Redundancy Check

Electrically Erasable Programmable Read-Only Memory

Frame Delay Time

FFC

Film Frame Carrier

IC

Integrated Circuit

LCR

L = inductance, Capacitance, Resistance (LCR meter)

Least Significant Bit

LSB

NAK

Not AcKnowledge

NUID

PCD

PICC

POR

REQA

RF

Non-Unique IDentifier

Proximity Coupling Device (Contactless Reader)

Proximity Integrated Circuit Card (Contactless Card)

Power-On Reset

REQuest command, Type A

Radio Frequency

RMS

SAK

Root Mean Square

Select AcKnowledge, type A

SEMI Equipment Communications Standard part 2

Titanium Tungsten

SECS-II

TiW

WUPA

Wake-Up Protocol type A

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17. References

[1] MIFARE (Card) Coil Design Guide — Application note, BU-ID Document

number 0117**¹

[2] Contactless smart card module specification MOA2 — Delivery Type

Description, BU-ID Document number 0287**¹

[3] Contactless smart card module specification MOA4 — Delivery Type

Description, BU-ID Document number 0823**¹

[4] Contactless smart card module specification MOA8 — Delivery Type

Description, BU-ID Document number 1636**¹

[5] Contactless smart card module specification MOB6 — Delivery Type

Description, BU-ID Document number 1309**¹

[6] General specification for 8" wafer on UV-tape; delivery types — Delivery Type

Description, BU-ID Document number 1005**¹

[7] MIFARE Type Identification Procedure — Application note, BU-ID Document

number 0184**¹

[8] ISO/IEC 14443-2 — 2001

[9] ISO/IEC 14443-3 — 2001

[10] CLRC632 Multiple protocol contactless reader IC (MIFARE/ICODE1) — Product

data sheet, BU-ID Document number 0739**¹

[11] MIFARE and handling of UIDs — Application note, BU-ID Document number

1907**¹

1. ** ... document version number

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18. Revision history

Table 29. Revision history

Document ID

MF1S503x v.3.1

Modifications:

MF1S503x v.3.0

Release date

20110221

Data sheet status

Change notice

Supersedes

Product data sheet

-

MF1S503x v.3.0

• Added MOA8 delivery form in Section 5, Section 7 and Section 14

20101202 Product data sheet

-

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19. Legal information

19.1 Data sheet status

Document status^[1][2]

Product status^[3]

Development

Definition

Objective [short] data sheet

This document contains data from the objective specification for product development.

This document contains data from the preliminary specification.

This document contains the product specification.

Preliminary [short] data sheet Qualification

Product [short] data sheet Production

[1]

[2]

[3]

Please consult the most recently issued document before initiating or completing a design.

The term ‘short data sheet’ is explained in section “Definitions”.

The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

malfunction of an NXP Semiconductors product can reasonably be expected

19.2 Definitions

to result in personal injury, death or severe property or environmental

damage. NXP Semiconductors accepts no liability for inclusion and/or use of

NXP Semiconductors products in such equipment or applications and

therefore such inclusion and/or use is at the customer’s own risk.

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modifications or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

specified use without further testing or modification.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

office. In case of any inconsistency or conflict with the short data sheet, the

full data sheet shall prevail.

Customers are responsible for the design and operation of their applications

and products using NXP Semiconductors products, and NXP Semiconductors

accepts no liability for any assistance with applications or customer product

design. It is customer’s sole responsibility to determine whether the NXP

Semiconductors product is suitable and fit for the customer’s applications and

products planned, as well as for the planned application and use of

customer’s third party customer(s). Customers should provide appropriate

design and operating safeguards to minimize the risks associated with their

applications and products.

Product specification — The information and data provided in a Product

data sheet shall define the specification of the product as agreed between

NXP Semiconductors and its customer, unless NXP Semiconductors and

customer have explicitly agreed otherwise in writing. In no event however,

shall an agreement be valid in which the NXP Semiconductors product is

deemed to offer functions and qualities beyond those described in the

Product data sheet.

NXP Semiconductors does not accept any liability related to any default,

damage, costs or problem which is based on any weakness or default in the

customer’s applications or products, or the application or use by customer’s

third party customer(s). Customer is responsible for doing all necessary

testing for the customer’s applications and products using NXP

Semiconductors products in order to avoid a default of the applications and

the products or of the application or use by customer’s third party

customer(s). NXP does not accept any liability in this respect.

19.3 Disclaimers

Limiting values — Stress above one or more limiting values (as defined in

the Absolute Maximum Ratings System of IEC 60134) will cause permanent

damage to the device. Limiting values are stress ratings only and (proper)

operation of the device at these or any other conditions above those given in

the Recommended operating conditions section (if present) or the

Characteristics sections of this document is not warranted. Constant or

repeated exposure to limiting values will permanently and irreversibly affect

the quality and reliability of the device.

Limited warranty and liability — Information in this document is believed to

be accurate and reliable. However, NXP Semiconductors does not give any

representations or warranties, expressed or implied, as to the accuracy or

completeness of such information and shall have no liability for the

consequences of use of such information.

In no event shall NXP Semiconductors be liable for any indirect, incidental,

punitive, special or consequential damages (including - without limitation - lost

profits, lost savings, business interruption, costs related to the removal or

replacement of any products or rework charges) whether or not such

damages are based on tort (including negligence), warranty, breach of

contract or any other legal theory.

Quick reference data — The Quick reference data is an extract of the

product data given in the Limiting values and Characteristics sections of this

document, and as such is not complete, exhaustive or legally binding.

Notwithstanding any damages that customer might incur for any reason

whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards

customer for the products described herein shall be limited in accordance

with the Terms and conditions of commercial sale of NXP Semiconductors.

Terms and conditions of commercial sale — NXP Semiconductors

products are sold subject to the general terms and conditions of commercial

sale, as published at http://www.nxp.com/profile/terms, unless otherwise

agreed in a valid written individual agreement. In case an individual

agreement is concluded only the terms and conditions of the respective

agreement shall apply. NXP Semiconductors hereby expressly objects to

applying the customer’s general terms and conditions with regard to the

purchase of NXP Semiconductors products by customer.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation specifications and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

No offer to sell or license — Nothing in this document may be interpreted or

construed as an offer to sell products that is open for acceptance or the grant,

conveyance or implication of any license under any copyrights, patents or

other industrial or intellectual property rights.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in life support, life-critical or

safety-critical systems or equipment, nor in applications where failure or

MF1S503x

All information provided in this document is subject to legal disclaimers.

Product data sheet

PUBLIC

Rev. 3.1 — 21 February 2011

194031

34 of 37

MF1S503x

NXP Semiconductors

MIFARE Classic 1K - Mainstream contactless smart card IC

Export control — This document as well as the item(s) described herein

may be subject to export control regulations. Export might require a prior

authorization from national authorities.

Bare die — All die are tested on compliance with their related technical

specifications as stated in this data sheet up to the point of wafer sawing and

are handled in accordance with the NXP Semiconductors storage and

transportation conditions. If there are data sheet limits not guaranteed, these

will be separately indicated in the data sheet. There are no post-packing tests

Non-automotive qualified products — Unless this data sheet expressly

states that this specific NXP Semiconductors product is automotive qualified,

the product is not suitable for automotive use. It is neither qualified nor tested

in accordance with automotive testing or application requirements. NXP

Semiconductors accepts no liability for inclusion and/or use of

performed on individual die or wafers.

NXP Semiconductors has no control of third party procedures in the sawing,

handling, packing or assembly of the die. Accordingly, NXP Semiconductors

assumes no liability for device functionality or performance of the die or

systems after third party sawing, handling, packing or assembly of the die. It

is the responsibility of the customer to test and qualify their application in

which the die is used.

non-automotive qualified products in automotive equipment or applications.

In the event that customer uses the product for design-in and use in

automotive applications to automotive specifications and standards, customer

(a) shall use the product without NXP Semiconductors’ warranty of the

product for such automotive applications, use and specifications, and (b)

whenever customer uses the product for automotive applications beyond

NXP Semiconductors’ specifications such use shall be solely at customer’s

own risk, and (c) customer fully indemnifies NXP Semiconductors for any

liability, damages or failed product claims resulting from customer design and

use of the product for automotive applications beyond NXP Semiconductors’

standard warranty and NXP Semiconductors’ product specifications.

All die sales are conditioned upon and subject to the customer entering into a

written die sale agreement with NXP Semiconductors through its legal

department.

19.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

MIFARE — is a trademark of NXP B.V.

20. Contact information

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

MF1S503x

All information provided in this document is subject to legal disclaimers.

Product data sheet

PUBLIC

Rev. 3.1 — 21 February 2011

194031

35 of 37

MF1S503x

NXP Semiconductors

MIFARE Classic 1K - Mainstream contactless smart card IC

21. Tables

Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2

Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3

Table 3. Pin allocation table . . . . . . . . . . . . . . . . . . . . . . .4

Table 4. Memory operations. . . . . . . . . . . . . . . . . . . . . .11

Table 5. Access conditions. . . . . . . . . . . . . . . . . . . . . . .11

Table 6. Access conditions for the sector trailer . . . . . .12

Table 7. Access conditions for data blocks. . . . . . . . . . .13

Table 8. Command overview . . . . . . . . . . . . . . . . . . . . .14

Table 9. MIFARE ACK and NAK . . . . . . . . . . . . . . . . . .15

Table 10. ATQA response of the MF1S503x . . . . . . . . . .15

Table 11. SAK response of the MF1S503x . . . . . . . . . . .15

Table 12. MIFARE authentication command . . . . . . . . . .16

Table 13. MIFARE authentication timing . . . . . . . . . . . . .17

Table 14. MIFARE Read command . . . . . . . . . . . . . . . . .17

Table 15. MIFARE Read timing . . . . . . . . . . . . . . . . . . . .17

Table 16. MIFARE Write command . . . . . . . . . . . . . . . . .18

Table 17. MIFARE Write timing . . . . . . . . . . . . . . . . . . . . 19

Table 18. MIFARE Increment, Decrement and

Restore command . . . . . . . . . . . . . . . . . . . . . . 20

Table 19. MIFARE Increment, Decrement and

Restore timing . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 20. MIFARE Transfer command. . . . . . . . . . . . . . . 21

Table 21. MIFARE Transfer timing. . . . . . . . . . . . . . . . . . 21

Table 22. Limiting values ^[1][2]. . . . . . . . . . . . . . . . . . . . . 22

Table 23. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 24. Wafer specifications MF1S5035DUx/L . . . . . . 23

Table 25. Wafer specifications MF1S5037DUx . . . . . . . 23

Table 26. Bond pad specifications. . . . . . . . . . . . . . . . . . 24

Table 27. Bump specifications. . . . . . . . . . . . . . . . . . . . . 24

Table 28. Abbreviations and symbols . . . . . . . . . . . . . . . 31

Table 29. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 33

22. Figures

Fig 1. MIFARE card reader . . . . . . . . . . . . . . . . . . . . . . .1

Fig 2. Block diagram of MF1S503x . . . . . . . . . . . . . . . . .3

Fig 3. Pin configuration for SOT500-2 (MOA4) . . . . . . . .4

Fig 4. Three pass authentication . . . . . . . . . . . . . . . . . . .6

Fig 5. Memory organization . . . . . . . . . . . . . . . . . . . . . . .8

Fig 6. Manufacturer block . . . . . . . . . . . . . . . . . . . . . . . .9

Fig 7. Value blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9

Fig 8. Sector trailer . . . . . . . . . . . . . . . . . . . . . . . . . . . .10

Fig 9. Access conditions . . . . . . . . . . . . . . . . . . . . . . . .12

Fig 10. Frame Delay Time (from PCD to PICC)

and T_ACKand T_NAK. . . . . . . . . . . . . . . . . . . . . . . .15

Fig 11. MIFARE Authentication part 1 . . . . . . . . . . . . . . .16

Fig 12. MIFARE Authentication part 2 . . . . . . . . . . . . . . .16

Fig 13. MIFARE Read . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Fig 14. MIFARE Write part 1 . . . . . . . . . . . . . . . . . . . . . .18

Fig 15. MIFARE Write part 2 . . . . . . . . . . . . . . . . . . . . . .18

Fig 16. MIFARE Increment, Decrement,

Restore part 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Fig 17. MIFARE Increment, Decrement,

Restore part 2 . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Fig 18. MIFARE Transfer . . . . . . . . . . . . . . . . . . . . . . . . .20

Fig 19. Package outline SOT500-2 . . . . . . . . . . . . . . . . .26

Fig 20. Package outline SOT500-3 . . . . . . . . . . . . . . . . .27

Fig 21. Package outline SOT500-4 . . . . . . . . . . . . . . . . .28

Fig 22. Bare die outline and chip orientation

MF1S5035 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29

Fig 23. Bare die outline and chip orientation

MF1S5037 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30

MF1S503x

All information provided in this document is subject to legal disclaimers.

Product data sheet

PUBLIC

Rev. 3.1 — 21 February 2011

194031

36 of 37

MF1S503x

NXP Semiconductors

MIFARE Classic 1K - Mainstream contactless smart card IC

23. Contents

1

General description. . . . . . . . . . . . . . . . . . . . . . 1

12

13

13.1

14

15

16

17

18

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 22

Wafer specification . . . . . . . . . . . . . . . . . . . . . 23

Fail die identification . . . . . . . . . . . . . . . . . . . 24

Package outline. . . . . . . . . . . . . . . . . . . . . . . . 25

Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 29

Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 31

References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Revision history . . . . . . . . . . . . . . . . . . . . . . . 33

1.1

1.2

1.3

1.4

Anti-collision . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Simple integration and user convenience. . . . . 1

Security. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Delivery options . . . . . . . . . . . . . . . . . . . . . . . . 1

2

2.1

3

Features and benefits . . . . . . . . . . . . . . . . . . . . 2

EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Quick reference data . . . . . . . . . . . . . . . . . . . . . 2

Ordering information. . . . . . . . . . . . . . . . . . . . . 3

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Pinning information. . . . . . . . . . . . . . . . . . . . . . 4

Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4

19

Legal information . . . . . . . . . . . . . . . . . . . . . . 34

Data sheet status . . . . . . . . . . . . . . . . . . . . . . 34

Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 35

5

19.1

19.2

19.3

19.4

6

7

7.1

8

8.1

8.2

8.2.1

8.2.2

8.2.3

8.2.4

8.2.5

8.3

Functional description . . . . . . . . . . . . . . . . . . . 5

Block description . . . . . . . . . . . . . . . . . . . . . . . 5

Communication principle . . . . . . . . . . . . . . . . . 5

Request standard/all. . . . . . . . . . . . . . . . . . . . . 5

Anti-collision loop . . . . . . . . . . . . . . . . . . . . . . . 5

Select card . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Three pass authentication . . . . . . . . . . . . . . . . 6

Memory operations. . . . . . . . . . . . . . . . . . . . . . 7

Data integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Three pass authentication sequence . . . . . . . . 7

RF interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Memory organization . . . . . . . . . . . . . . . . . . . . 8

Manufacturer block. . . . . . . . . . . . . . . . . . . . . . 9

Data blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Value blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Sector trailer (block 3) . . . . . . . . . . . . . . . . . . 10

Memory access . . . . . . . . . . . . . . . . . . . . . . . 11

Access conditions. . . . . . . . . . . . . . . . . . . . . . 11

Access conditions for the sector trailer. . . . . . 12

Access conditions for data blocks. . . . . . . . . . 13

20

21

22

23

Contact information . . . . . . . . . . . . . . . . . . . . 35

Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

8.4

8.5

8.6

8.6.1

8.6.2

8.6.2.1

8.6.3

8.7

8.7.1

8.7.2

8.7.3

9

Command overview. . . . . . . . . . . . . . . . . . . . . 14

MIFARE Classic command overview . . . . . . . 14

Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

MIFARE Classic ACK and NAK . . . . . . . . . . . 15

ATQA and SAK responses . . . . . . . . . . . . . . . 15

9.1

9.2

9.3

9.4

10

MIFARE Classic commands . . . . . . . . . . . . . . 16

MIFARE Authentication . . . . . . . . . . . . . . . . . 16

MIFARE Read. . . . . . . . . . . . . . . . . . . . . . . . . 17

MIFARE Write. . . . . . . . . . . . . . . . . . . . . . . . . 18

MIFARE Increment, Decrement and Restore. 19

MIFARE Transfer . . . . . . . . . . . . . . . . . . . . . . 20

10.1

10.2

10.3

10.4

10.5

11

Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 22

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 21 February 2011

194031


型号：	MF1S5035DUH/L,005
厂家：	NXP
描述：	MF1S503x - MIFARE Classic 1K - Mainstream contactless smart card IC for fast and easy solution development
文件：	总37页 (文件大小：402K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MF1S5035DUH/L,005 [NXP]

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