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MF1S7000XDA4/V1 [NXP]

SPECIALTY CONSUMER CIRCUIT;
MF1S7000XDA4/V1
型号： MF1S7000XDA4/V1
厂家： NXP    NXP
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SPECIALTY CONSUMER CIRCUIT

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MF1S70yyX/V1  
MIFARE Classic EV1 4K - Mainstream contactless smart card  
IC for fast and easy solution development  
Rev. 3.0 — 3 March 2014  
279330  
Product data sheet  
COMPANY PUBLIC  
1. General description  
NXP Semiconductors has developed the MIFARE Classic MF1S70yyX/V1 to be used in a  
contactless smart card according to ISO/IEC 14443 Type A.  
The MIFARE Classic EV1 4K MF1S70yyX/V1 IC is used in applications like public  
transport ticketing and can also be used for various other applications.  
1.1 Anticollision  
An intelligent anticollision function allows to operate more than one card in the field  
simultaneously. The anticollision algorithm selects each card individually and ensures that  
the execution of a transaction with a selected card is performed correctly without  
interference from another card in the field.  
energy  
MIFARE  
CARD PCD  
data  
001aam199  
Fig 1. Contactless MIFARE system  
1.2 Simple integration and user convenience  
The MF1S70yyX/V1 is designed for simple integration and user convenience which allows  
complete ticketing transactions to be handled in less than 100 ms.  
1.3 Security and privacy  
• Manufacturer programmed 7-byte UID or 4-byte NUID identifier for each device  
• Random ID support  
• Mutual three pass authentication (ISO/IEC DIS 9798-2)  
• Individual set of two keys per sector to support multi-application with key hierarchy  
1.4 Delivery options  
• 7-byte UID, 4-byte NUID  
MF1S70yyX/V1  
NXP Semiconductors  
MIFARE Classic EV1 4K - Mainstream contactless smart card IC  
• Bumped die on sawn wafer  
• MOA4 and MOA8 contactless module  
2. Features and benefits  
Contactless transmission of data and  
Operating distance up to 100 mm  
depending on antenna geometry and  
reader configuration  
energy supply  
Operating frequency of 13.56 MHz  
Data integrity of 16-bit CRC, parity, bit  
coding, bit counting  
Data transfer of 106 kbit/s  
Anticollision  
Typical ticketing transaction time of  
< 100 ms (including backup  
management)  
7 Byte UID or 4 Byte NUID  
Random ID support (7 Byte UID version) NXP Originality Check support  
2.1 EEPROM  
4 kB, organized in 32 sectors of 4 blocks User definable access conditions for  
and 8 sectors of 16 blocks (one block  
consists of 16 byte)  
each memory block  
Data retention time of 10 years  
Write endurance 200000 cycles  
3. Applications  
Public transportation  
Electronic toll collection  
School and campus cards  
Internet cafés  
Access management  
Car parking  
Employee cards  
Loyalty  
4. Quick reference data  
Table 1.  
Quick reference data  
Symbol  
Parameter  
Conditions  
Min  
14.9  
-
Typ  
Max  
19.0  
-
Unit  
pF  
[1]  
Ci  
fi  
input capacitance  
input frequency  
16.9  
13.56  
MHz  
EEPROM characteristics  
tret  
retention time  
Tamb = 22 C  
Tamb = 22 C  
10  
-
-
-
year  
Nendu(W)  
write endurance  
100000  
200000  
cycle  
[1] Tamb=22°C, f=13,56Mhz, VLaLb = 1,5 V RMS  
MF1S70yyX_V1  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2014. All rights reserved.  
Product data sheet  
COMPANY PUBLIC  
Rev. 3.0 — 3 March 2014  
279330  
2 of 41  
MF1S70yyX/V1  
NXP Semiconductors  
MIFARE Classic EV1 4K - Mainstream contactless smart card IC  
5. Ordering information  
Table 2.  
Ordering information  
Type number  
Package  
Name  
Description  
Version  
MF1S7001XDUD/V1 FFC Bump 8 inch wafer, 120 m thickness, on film frame carrier, electronic fail die  
-
marking according to SECS-II format), Au bumps, 7-byte UID  
MF1S7001XDUF/V1 FFC Bump 8 inch wafer, 75 m thickness, on film frame carrier, electronic fail die  
-
marking according to SECS-II format), Au bumps, 7-byte UID  
MF1S7000XDA4/V1 MOA4  
MF1S7000XDA8/V1 MOA8  
plastic leadless module carrier package; 35 mm wide tape, 7-byte UID  
plastic leadless module carrier package; 35 mm wide tape, 7-byte UID  
SOT500-2  
SOT500-4  
-
MF1S7031XDUD/V1 FFC Bump 8 inch wafer, 120 m thickness, on film frame carrier, electronic fail die  
marking according to SECS-II format), Au bumps, 4-byte non-unique ID  
MF1S7031XDUF/V1 FFC Bump 8 inch wafer, 75 m thickness, on film frame carrier, electronic fail die  
-
marking according to SECS-II format), Au bumps, 4-byte non-unique ID  
MF1S7030XDA4/V1 MOA4  
MF1S7030XDA8/V1 MOA8  
plastic leadless module carrier package; 35 mm wide tape,  
4-byte non-unique ID  
SOT500-2  
SOT500-4  
plastic leadless module carrier package; 35 mm wide tape,  
4-byte non-unique ID  
6. Block diagram  
UART  
RF  
CRYPTO1  
RNG  
ISO/IEC 14443  
INTERFACE  
TYPE A  
POWER ON  
RESET  
VOLTAGE  
REGULATOR  
CRC  
CLOCK  
INPUT FILTER  
RESET  
LOGIC UNIT  
GENERATOR  
EEPROM  
001aan006  
Fig 2. Block diagram of MF1S70yyX/V1  
7. Pinning information  
7.1 Pinning  
The pinning for the MF1S70yyX/V1DAx is shown as an example in Figure 3 for the MOA4  
contactless module. For the contactless module MOA8, the pinning is analogous and not  
explicitly shown.  
MF1S70yyX_V1  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2014. All rights reserved.  
Product data sheet  
COMPANY PUBLIC  
Rev. 3.0 — 3 March 2014  
279330  
3 of 41  
MF1S70yyX/V1  
NXP Semiconductors  
MIFARE Classic EV1 4K - Mainstream contactless smart card IC  
LA  
top view  
LB  
001aan002  
Fig 3. Pin configuration for SOT500-2 (MOA4)  
Table 3.  
Pin  
Pin allocation table  
Symbol  
LA  
LA  
Antenna coil connection LA  
Antenna coil connection LB  
LB  
LB  
MF1S70yyX_V1  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2014. All rights reserved.  
Product data sheet  
COMPANY PUBLIC  
Rev. 3.0 — 3 March 2014  
279330  
4 of 41  
MF1S70yyX/V1  
NXP Semiconductors  
MIFARE Classic EV1 4K - Mainstream contactless smart card IC  
8. Functional description  
8.1 Block description  
The MF1S70yyX/V1 chip consists of a 4 kB EEPROM, RF interface and Digital Control  
Unit. Energy and data are transferred via an antenna consisting of a coil with a small  
number of turns which is directly connected to the MF1S70yyX/V1. No further external  
components are necessary. Refer to the document Ref. 1 for details on antenna design.  
• RF interface:  
– Modulator/demodulator  
– Rectifier  
– Clock regenerator  
– Power-On Reset (POR)  
– Voltage regulator  
• Anticollision: Multiple cards in the field may be selected and managed in sequence  
• Authentication: Preceding any memory operation the authentication procedure  
ensures that access to a block is only possible via the two keys specified for each  
block  
• Control and Arithmetic Logic Unit: Values are stored in a special redundant format and  
can be incremented and decremented  
• EEPROM interface  
• Crypto unit: The CRYPTO1 stream cipher of the MF1S70yyX/V1 is used for  
authentication and encryption of data exchange.  
• EEPROM: 4 kB is organized in 32 sectors of 4 blocks and 8 sectors of 16 blocks. One  
block contains 16 bytes. The last block of each sector is called “trailer”, which  
contains two secret keys and programmable access conditions for each block in this  
sector.  
8.2 Communication principle  
The commands are initiated by the reader and controlled by the Digital Control Unit of the  
MF1S70yyX/V1. The command response is depending on the state of the IC and for  
memory operations also on the access conditions valid for the corresponding sector.  
8.2.1 Request standard / all  
After Power-On Reset (POR) the card answers to a request REQA or wakeup WUPA  
command with the answer to request code (see Section 9.4, ATQA according to ISO/IEC  
14443A).  
8.2.2 Anticollision loop  
In the anticollision loop the identifier of a card is read. If there are several cards in the  
operating field of the reader, they can be distinguished by their identifier and one can be  
selected (select card) for further transactions. The unselected cards return to the idle state  
and wait for a new request command. If the 7-byte UID is used for anticollision and  
selection, two cascade levels need to be processes as defined in ISO/IEC 14443-3.  
MF1S70yyX_V1  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2014. All rights reserved.  
Product data sheet  
COMPANY PUBLIC  
Rev. 3.0 — 3 March 2014  
279330  
5 of 41  
MF1S70yyX/V1  
NXP Semiconductors  
MIFARE Classic EV1 4K - Mainstream contactless smart card IC  
Remark: For the 4-byte non-unique ID product versions, the identifier retrieved from the  
card is not defined to be unique. For further information regarding handling of non-unique  
identifiers see Ref. 6.  
8.2.3 Select card  
With the select card command the reader selects one individual card for authentication  
and memory related operations. The card returns the Select AcKnowledge (SAK) code  
which determines the type of the selected card, see Section 9.4. For further details refer to  
the document Ref. 2.  
8.2.4 Three pass authentication  
After selection of a card the reader specifies the memory location of the following memory  
access and uses the corresponding key for the three pass authentication procedure. After  
a successful authentication all commands and responses are encrypted.  
Remark: The HLTA command needs to be sent encrypted to the PICC after a successful  
authentication in order to be accepted.  
Transaction Sequence  
Typical Transaction Time  
POR  
Request Standard  
Request All  
Identification and Selection  
Procedure  
Anticollision Loop  
Get Identifier  
~2.5 ms without collision  
+ ~1 ms for 7-byte UID  
+ ~1 ms for each collision  
Select Card  
Authentication Procedure  
~2 ms  
3 Pass Authenticationon  
specific sector  
Memory Operations  
~2.5 ms read block  
~5.5 ms write block  
~2.5 ms de-/increment  
~4.5 ms transfer  
Read  
Block  
Write  
Block  
Decre-  
ment  
Incre-  
ment  
Re-  
store  
Halt  
Transfer  
001aan921  
(1) the command flow diagram does not include the Personalize UID Usage and the  
SET_MOD_TYPE command, for details on those commands please see Section 10.1.1 and  
Section 11  
Fig 4. MIFARE Classic command flow diagram  
MF1S70yyX_V1  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2014. All rights reserved.  
Product data sheet  
COMPANY PUBLIC  
Rev. 3.0 — 3 March 2014  
279330  
6 of 41  
MF1S70yyX/V1  
NXP Semiconductors  
MIFARE Classic EV1 4K - Mainstream contactless smart card IC  
8.2.5 Memory operations  
After authentication any of the following operations may be performed:  
• Read block  
• Write block  
• Decrement: Decrements the contents of a block and stores the result in the internal  
Transfer Buffer  
• Increment: Increments the contents of a block and stores the result in the internal  
Transfer Buffer  
• Restore: Moves the contents of a block into the internal Transfer Buffer  
• Transfer: Writes the contents of the internal Transfer Buffer to a value block  
8.3 Data integrity  
Following mechanisms are implemented in the contactless communication link between  
reader and card to ensure very reliable data transmission:  
• 16 bits CRC per block  
• Parity bits for each byte  
• Bit count checking  
• Bit coding to distinguish between “1”, “0” and “no information”  
• Channel monitoring (protocol sequence and bit stream analysis)  
8.4 Three pass authentication sequence  
1. The reader specifies the sector to be accessed and chooses key A or B.  
2. The card reads the secret key and the access conditions from the sector trailer. Then  
the card sends a number as the challenge to the reader (pass one).  
3. The reader calculates the response using the secret key and additional input. The  
response, together with a random challenge from the reader, is then transmitted to the  
card (pass two).  
4. The card verifies the response of the reader by comparing it with its own challenge  
and then it calculates the response to the challenge and transmits it (pass three).  
5. The reader verifies the response of the card by comparing it to its own challenge.  
After transmission of the first random challenge the communication between card and  
reader is encrypted.  
MF1S70yyX_V1  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2014. All rights reserved.  
Product data sheet  
COMPANY PUBLIC  
Rev. 3.0 — 3 March 2014  
279330  
7 of 41  
MF1S70yyX/V1  
NXP Semiconductors  
MIFARE Classic EV1 4K - Mainstream contactless smart card IC  
8.5 RF interface  
The RF-interface is according to the standard for contactless smart cards  
ISO/IEC 14443A.  
For operation, the carrier field from the reader always needs to be present (with short  
pauses when transmitting), as it is used for the power supply of the card.  
For both directions of data communication there is only one start bit at the beginning of  
each frame. Each byte is transmitted with a parity bit (odd parity) at the end. The LSB of  
the byte with the lowest address of the selected block is transmitted first. The maximum  
frame length is 163 bits (16 data bytes + 2 CRC bytes = 16 9 + 2 9 + 1 start bit).  
8.6 Memory organization  
The 4096 8 bit EEPROM memory is organized in 32 sectors of 4 blocks and 8 sectors of  
16 blocks. One block contains 16 bytes.  
MF1S70yyX_V1  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2014. All rights reserved.  
Product data sheet  
COMPANY PUBLIC  
Rev. 3.0 — 3 March 2014  
279330  
8 of 41  
MF1S70yyX/V1  
NXP Semiconductors  
MIFARE Classic EV1 4K - Mainstream contactless smart card IC  
Byte Number within a Block  
Sector  
39  
Block  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
Key B  
Description  
15  
14  
13  
:
Key A  
Access Bits  
Sector Trailer 39  
Data  
Data  
:
:
:
2
1
0
:
Data  
Data  
Data  
:
:
:
:
:
32  
15  
14  
13  
:
Key A  
Access Bits  
Key B  
Sector Trailer 32  
Data  
Data  
:
:
:
2
1
0
3
2
1
0
:
Data  
Data  
Data  
31  
Key A  
Access Bits  
Key B  
Sector Trailer 31  
Data  
Data  
Data  
:
:
:
:
:
0
3
2
1
0
Key A  
Access Bits  
Key B  
Sector Trailer 0  
Data  
Data  
Manufacturer Data  
Manufacturer Block  
001aan021  
Fig 5. Memory organization  
MF1S70yyX_V1  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2014. All rights reserved.  
Product data sheet  
COMPANY PUBLIC  
Rev. 3.0 — 3 March 2014  
279330  
9 of 41  
MF1S70yyX/V1  
NXP Semiconductors  
MIFARE Classic EV1 4K - Mainstream contactless smart card IC  
8.6.1 Manufacturer block  
This is the first data block (block 0) of the first sector (sector 0). It contains the IC  
manufacturer data. This block is programmed and write protected in the production test.  
The manufacturer block is shown in Figure 6 and Figure 7 for the 4-byte NUID and 7-byte  
UID version respectively.  
Block 0/Sector 0  
Byte  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
NUID  
Manufacturer Data  
001aan010  
Fig 6. Manufacturer block for MF1S503yX with 4-byte NUID  
Block 0/Sector 0  
Byte  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
UID  
Manufacturer Data  
001aam204  
Fig 7. Manufacturer block for MF1S500yX with 7-byte UID  
8.6.2 Data blocks  
One block consists of 16 bytes. The first 32 sectors contain 3 blocks and the last 8 sectors  
contain 15 blocks for storing data (Sector 0 contains only two data blocks and the  
read-only manufacturer block).  
The data blocks can be configured by the access bits as  
• read/write blocks  
• value blocks  
Value blocks can be used for e.g. electronic purse applications, where additional  
commands like increment and decrement for direct control of the stored value are  
provided  
A successful authentication has to be performed to allow any memory operation.  
Remark: The default content of the data blocks at delivery is not defined.  
8.6.2.1 Value blocks  
Value blocks allow performing electronic purse functions (valid commands are: read,  
write, increment, decrement, restore, transfer). Value blocks have a fixed data format  
which permits error detection and correction and a backup management.  
A value block can only be generated through a write operation in value block format:  
• Value: Signifies a signed 4-byte value. The lowest significant byte of a value is stored  
in the lowest address byte. Negative values are stored in standard 2´s complement  
format. For reasons of data integrity and security, a value is stored three times, twice  
non-inverted and once inverted.  
MF1S70yyX_V1  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2014. All rights reserved.  
Product data sheet  
COMPANY PUBLIC  
Rev. 3.0 — 3 March 2014  
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MF1S70yyX/V1  
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MIFARE Classic EV1 4K - Mainstream contactless smart card IC  
• Adr: Signifies a 1-byte address, which can be used to save the storage address of a  
block, when implementing a powerful backup management. The address byte is  
stored four times, twice inverted and non-inverted. During increment, decrement,  
restore and transfer operations the address remains unchanged. It can only be  
altered via a write command.  
Byte Number  
Description  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
value  
value  
value  
adr adr adr adr  
001aan018  
Fig 8. Value blocks  
An example of a valid value block format for the decimal value 1234567d and the block  
address 17d is shown in Table 4. First, the decimal value has to be converted to the  
hexadecimal representation of 0012D687h. The LSByte of the hexadecimal value is  
stored in Byte 0, the MSByte in Byte 3. The bit inverted hexadecimal representation of the  
value is FFED2978h where the LSByte is stored in Byte 4 and the MSByte in Byte 7.  
The hexadecimal value of the address in the example is 11h, the bit inverted hexadecimal  
value is EEh.  
Table 4.  
Value block format example  
Byte Number  
Description  
Values [hex]  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
adr adr adr adr  
value  
value  
value  
87 D6 12 00 78 29 ED FF 87 D6 12 00 11 EE 11 EE  
8.6.3 Sector trailer  
The sector trailer is always the last block in one sector. For the first 32 sectors this is block  
3 and for the remaining 8 sectors it is block 15. Each sector has a sector trailer containing  
the  
• secret keys A (mandatory) and B (optional), which return logical “0”s when read and  
• the access conditions for the blocks of that sector, which are stored in bytes 6...9. The  
access bits also specify the type (data or value) of the data blocks.  
If key B is not needed, the last 6 bytes of the sector trailer can be used as data bytes. The  
access bits for the sector trailer have to be configured accordingly, see Section 8.7.2.  
Byte 9 of the sector trailer is available for user data. For this byte the same access rights  
as for byte 6, 7 and 8 apply.  
When the sector trailer is read, the key bytes are blanked out by returning logical zeros. If  
key B is configured to be readable, the data stored in bytes 10 to 15 is returned, see  
Section 8.7.2.  
All keys are set to FFFF FFFF FFFFh at chip delivery and the bytes 6, 7 and 8 are set to  
FF0780h.  
MF1S70yyX_V1  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2014. All rights reserved.  
Product data sheet  
COMPANY PUBLIC  
Rev. 3.0 — 3 March 2014  
279330  
11 of 41  
MF1S70yyX/V1  
NXP Semiconductors  
MIFARE Classic EV1 4K - Mainstream contactless smart card IC  
Byte Number  
Description  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
Key A  
Access Bits  
Key B (optional)  
001aan013  
Fig 9. Sector trailer  
8.7 Memory access  
Before any memory operation can be done, the card has to be selected and authenticated  
as described in Section 8.2. The possible memory operations for an addressed block  
depend on the key used during authentication and the access conditions stored in the  
associated sector trailer.  
Table 5.  
Operation  
Read  
Memory operations  
Description  
Valid for Block Type  
reads one memory block  
read/write, value and sector trailer  
read/write, value and sector trailer  
value  
Write  
writes one memory block  
Increment  
increments the contents of a block and  
stores the result in the internal Transfer  
Buffer  
Decrement  
decrements the contents of a block and value  
stores the result in the internal Transfer  
Buffer  
Transfer  
Restore  
writes the contents of the internal  
Transfer Buffer to a block  
value and read/write  
reads the contents of a block into the  
internal Transfer Buffer  
value  
MF1S70yyX_V1  
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© NXP Semiconductors N.V. 2014. All rights reserved.  
Product data sheet  
COMPANY PUBLIC  
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MIFARE Classic EV1 4K - Mainstream contactless smart card IC  
8.7.1 Access conditions  
The access conditions for every data block and sector trailer are defined by 3 bits, which  
are stored non-inverted and inverted in the sector trailer of the specified sector.  
The access bits control the rights of memory access using the secret keys A and B. The  
access conditions may be altered, provided one knows the relevant key and the current  
access condition allows this operation.  
Remark: With each memory access the internal logic verifies the format of the access  
conditions. If it detects a format violation the whole sector is irreversibly blocked.  
Remark: In the following description the access bits are mentioned in the non-inverted  
mode only.  
The internal logic of the MF1S70yyX/V1 ensures that the commands are executed only  
after a successful authentication.  
Table 6.  
Access conditions  
Access Bits Valid Commands  
Block  
Block(s)  
Description  
(sectors 0 - 31) (sectors 32-39)  
C13 C23 C33 read, write  
3  
15  
sector trailer  
data block(s)  
C12 C22 C32 read, write, increment,  
decrement, transfer, restore  
2  
1  
0  
10-14  
C11 C21 C31 read, write, increment,  
decrement, transfer, restore  
5-9  
0-4  
data block(s)  
data block(s)  
C10 C20 C30 read, write, increment,  
decrement, transfer, restore  
Byte Number  
Description  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
Key B (optional)  
Key A  
Access Bits  
Bit  
7
6
5
4
3
2
1
0
Byte 6  
Byte 7  
Byte 8  
Byte 9  
C2  
C2  
2
C1  
2
C3  
2
C2  
C2  
C1  
C1  
C1  
C1  
3
3
3
1
1
1
0
0
0
3
3
3
2
2
2
1
1
1
0
0
0
C1  
C3  
C1  
C3  
C1  
C3  
C3  
C2  
C3  
C2  
C3  
C2  
C3  
C2  
user data  
001aan003  
Fig 10. Access conditions  
MF1S70yyX_V1  
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© NXP Semiconductors N.V. 2014. All rights reserved.  
Product data sheet  
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MIFARE Classic EV1 4K - Mainstream contactless smart card IC  
8.7.2 Access conditions for the sector trailer  
Depending on the access bits for the sector trailer (block 3, respectively block 15) the  
read/write access to the keys and the access bits is specified as ‘never’, ‘key A’, ‘key B’ or  
key A|B’ (key A or key B).  
On chip delivery the access conditions for the sector trailers and key A are predefined as  
transport configuration. Since key B may be read in the transport configuration, new cards  
must be authenticated with key A. Since the access bits themselves can also be blocked,  
special care has to be taken during the personalization of cards.  
Table 7.  
Access bits Access condition for  
KEYA Access bits  
C1 C2 C3 read  
Access conditions for the sector trailer  
Remark  
KEYB  
write  
read  
write  
read  
write  
0
0
1
1
0
0
1
0
1
0
0
0
0
0
1
never  
never  
never  
never  
never  
key A  
never  
key B  
never  
key A  
key A  
key A  
never key A  
never key A  
key A Key B may be read[1]  
never Key B may be read[1]  
key A|B never never  
key A|B never never  
key B  
never  
key A  
key A key A  
key A Key B may be read,  
transport configuration[1]  
0
1
1
1
0
1
1
1
1
never  
never  
never  
key B  
never  
never  
key A|B key B never  
key A|B key B never  
key A|B never never  
key B  
never  
never  
[1] For this access condition key B is readable and may be used for data  
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8.7.3 Access conditions for data blocks  
Depending on the access bits for data blocks (blocks 0...2) the read/write access is  
specified as ‘never’, ‘key A’, ‘key B’ or ‘key A|B’ (key A or key B). The setting of the  
relevant access bits defines the application and the corresponding applicable commands.  
• Read/write block: the operations read and write are allowed.  
• Value block: Allows the additional value operations increment, decrement, transfer  
and restore. With access condition ‘001’ only read and decrement are possible which  
reflects a non-rechargeable card. For access condition ‘110’ recharging is possible by  
using key B.  
• Manufacturer block: the read-only condition is not affected by the access bits setting!  
• Key management: in transport configuration key A must be used for authentication  
Table 8.  
Access bits  
C1 C2 C3 read  
Access conditions for data blocks  
Access condition for  
Application  
write  
increment  
key A|B  
decrement,  
transfer,  
restore  
0
0
0
key A|B  
key A|B  
key A|B  
transport  
configuration[1]  
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
0
0
1
1
1
1
key A|B  
key A|B  
key A|B  
key A|B  
key B  
never  
key B  
key B  
never  
key B  
never  
never  
never  
never  
key B  
never  
never  
never  
never  
never  
read/write block[1]  
read/write block[1]  
value block[1]  
never  
key A|B  
key A|B  
never  
value block[1]  
read/write block[1]  
read/write block[1]  
read/write block  
key B  
never  
never  
never  
[1] If key B may be read in the corresponding Sector Trailer it cannot serve for authentication (see grey marked  
lines in Table 7). As a consequences, if the reader authenticates any block of a sector which uses such  
access conditions for the Sector Trailer and using key B, the card will refuse any subsequent memory  
access after authentication.  
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9. Command overview  
The MIFARE Classic card activation follows the ISO/IEC 14443 Type A. After the  
MIFARE Classic card has been selected, it can either be deactivated using the  
ISO/IEC 14443 Halt command, or the MIFARE Classic commands can be performed. For  
more details about the card activation refer to Ref. 4.  
9.1 MIFARE Classic command overview  
All MIFARE Classic commands typically use the MIFARE CRYPTO1 and require an  
authentication.  
All available commands for the MIFARE Classic EV1 4K are shown in Table 9.  
Table 9.  
Command overview  
Command  
ISO/IEC 14443  
Command code  
(hexadecimal)  
Request  
Wake-up  
REQA  
26h (7 bit)  
52h (7 bit)  
93h 20h  
93h 70h  
95h 20h  
95h 70h  
50h 00h  
60h  
WUPA  
Anticollision CL1  
Select CL1  
Anticollision CL1  
Select CL1  
Anticollision CL2  
Select CL2  
Anticollision CL2  
Select CL2  
Halt  
Halt  
Authentication with Key A  
Authentication with Key B  
Personalize UID Usage  
SET_MOD_TYPE  
MIFARE Read  
-
-
-
-
-
-
-
-
-
-
61h  
40h  
43h  
30h  
MIFARE Write  
A0h  
MIFARE Decrement  
MIFARE Increment  
MIFARE Restore  
MIFARE Transfer  
C0h  
C1h  
C2h  
B0h  
All commands use the coding and framing as described in Ref. 3 and Ref. 4 if not  
otherwise specified.  
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9.2 Timings  
The timing shown in this document are not to scale and values are rounded to 1 s.  
All given times refer to the data frames including start of communication and end of  
communication. A PCD data frame contains the start of communication (1 “start bit”) and  
the end of communication (one logic 0 + 1 bit length of unmodulated carrier). A PICC data  
frame contains the start of communication (1 “start bit”) and the end of communication (1  
bit length of no subcarrier).  
The minimum command response time is specified according to Ref. 4 as an integer n  
which specifies the PCD to PICC frame delay time. The frame delay time from PICC to  
PCD is at least 87 s. The maximum command response time is specified as a time-out  
value. Depending on the command, the TACK value specified for command responses  
defines the PCD to PICC frame delay time. It does it for either the 4-bit ACK value  
specified in Section 9.3 or for a data frame.  
All command timings are according to ISO/IEC 14443-3 frame specification as shown for  
the Frame Delay Time in Figure 11. For more details refer to Ref. 3 and Ref. 4.  
last data bit transmitted by the PCD  
FDT = (n* 128 + 84)/fc  
first modulation of the PICC  
128/fc  
logic „1“  
256/fc  
end of communication (E)  
128/fc  
start of  
communication (S)  
FDT = (n* 128 + 20)/fc  
128/fc  
logic „0“  
256/fc  
128/fc  
start of  
end of communication (E)  
communication (S)  
aaa-006279  
Fig 11. Frame Delay Time (from PCD to PICC) and TACK and TNAK  
Remark: Due to the coding of commands, the measured timings usually excludes (a part  
of) the end of communication. Consider this factor when comparing the specified with the  
measured times.  
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9.3 MIFARE Classic ACK and NAK  
The MIFARE Classic uses a 4 bit ACK / NAK as shown in Table 10.  
Table 10. MIFARE ACK and NAK  
Code (4-bit)  
Transfer Buffer Validity  
Description  
Ah  
0h  
1h  
4h  
5h  
Acknowledge (ACK)  
invalid operation  
parity or CRC error  
invalid operation  
parity or CRC error  
valid  
valid  
invalid  
invalid  
9.4 ATQA and SAK responses  
For details on the type identification procedure please refer to Ref. 2.  
The MF1S70yyX/V1 answers to a REQA or WUPA command with the ATQA value shown  
in Table 11 and to a Select CL1 command (CL2 for the 7-byte UID variant) with the SAK  
value shown in Table 12.  
Table 11. ATQA response of the MF1S70yyX/V1  
Bit Number  
Sales Type  
MF1S700yX  
MF1S703yX  
Hex Value  
00 42h  
16 15 14 13 12 11 10 9  
8
0
0
7
1
0
6
0
0
5
0
0
4
0
0
3
0
0
2
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
00 02h  
Table 12. SAK response of the MF1S70yyX/V1  
Bit Number  
Sales Type  
Hex Value  
8
7
6
5
4
3
2
1
MF1S70yyX/V1  
18  
0
0
0
1
1
0
0
0
Remark: The ATQA coding in bits 7 and 8 indicate the UID size according to  
ISO/IEC 14443 independent from the settings of the UID usage.  
Remark: The bit numbering in the ISO/IEC 14443 starts with LSBit = bit 1, but not LSBit =  
bit 0. So one byte counts bit 1 to 8 instead of bit 0 to 7.  
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10. UID Options and Handling  
The MF1S70yyX/V1 product family offers two delivery options for the UID which is stored  
in block 0 of sector 0.  
• 7-byte UID  
• 4-byte NUID (Non-Unique ID)  
This section describes the MIFARE Classic MF1S70yyX/V1 operation when using one of  
the 2 UID options with respect to card selection, authentication and personalization. See  
also Ref. 6 for details on how to handle UIDs and NUIDs with MIFARE Classic products.  
10.1 7-byte UID Operation  
All MF1S70yXDyy products are featuring a 7-byte UID. This 7-byte UID is stored in  
block 0 of sector 0 as shown in Figure 7. The behaviour during anti-collision, selection and  
authentication can be configured during personalization for this UID variant.  
10.1.1 Personalization Options  
The 7-byte UID variants of the MF1S70yyX/V1 can be operated with four different  
functionalities, denoted as UIDFn (UID Functionality n).  
1. UIDF0: anti-collision and selection with the double size UID according to ISO/IEC  
14443-3  
2. UIDF1: anti-collision and selection with the double size UID according to ISO/IEC  
14443-3 and optional usage of a selection process shortcut  
3. UIDF2: anti-collision and selection with a single size random ID according to ISO/IEC  
14443-3  
4. UIDF3: anti-collision and selection with a single size NUID according to ISO/IEC  
14443-3 where the NUID is calculated out of the 7-byte UID  
The anti-collision and selection procedure and the implications on the authentication  
process are detailed in Section 10.1.2 and Section 10.1.3.  
The default configuration at delivery is option 1 which enables the ISO/IEC 14443-3  
compliant anti-collision and selection. This configuration can be changed using the  
‘Personalize UID Usage’ command. The execution of this command requires an  
authentication to sector 0. Once this command has been issued and accepted by the  
PICC, the configuration is automatically locked. A subsequently issued ‘Personalize UID  
Usage’ command is not executed and a NAK is replied by the PICC.  
Remark: As the configuration is changeable at delivery, it is strongly recommended to  
send this command at personalization of the card to prevent unwanted changes in the  
field. This should also be done if the default configuration is used.  
Remark: The configuration becomes effective only after PICC unselect or PICC field  
reset.  
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Cmd  
Type  
CRC  
PCD  
ACK  
59 µs  
PICC `ACK`  
T
T
368 µs  
ACK  
NAK  
59 µs  
PICC `NAK`  
TimeOut  
NAK  
T
TimeOut  
001aan919  
Fig 12. Personalize UID Usage  
Table 13. Personalize UID Usage command  
Name  
Code  
Description  
Length  
Cmd  
40h  
Set anti-collision, selection and  
authentication behaviour  
1 byte  
Type  
-
Encoded type of UID usage:  
UIDF0:00h  
1 byte  
UIDF1:40h  
UIDF2:20h  
UIDF3:60h  
CRC  
-
CRC according to Ref. 4  
see Section 9.3  
2 bytes  
4-bit  
ACK, NAK  
see Table 10  
Table 14. Personalize UID Usage timing  
TACK min TACK max  
Personalize UID Usage n=9 TTimeOut  
TNAK min  
TNAK max  
TTimeOut  
10 ms  
n=9  
TTimeOut  
10.1.2 Anti-collision and Selection  
Depending on the chosen personalization option there are certain possibilities to perform  
anti-collision and selection. To bring the MIFARE Classic into the ACTIVE state according  
to ISO/IEC 14443-3, the following sequences are available.  
Sequence 1: ISO/IEC 14443-3 compliant anti-collision and selection using the cascade  
level 1 followed by the cascade level 2 SEL command  
Sequence 2: using cascade level 1 anti-collision and selection procedure followed by a  
Read command from block 0  
Sequence 3: ISO/IEC 14443-3 compliant anti-collision and selection using the cascade  
level 1 SEL command  
Remark: The Read from Block 0 in Sequence 2 does not require a prior authentication to  
Sector 0 and is transmitted in plain data. For all other sequences, the readout from Block  
0 in Sector 0 is encrypted and requires an authentication to that sector.  
Remark: The settings done with Personalize UID Usage do not change the ATQA coding.  
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Table 15. Available activation sequences for 7-byte UID options  
UID Functionality  
Available Activation Sequences  
Sequence 1  
UIDF0  
UIDF1  
UIDF2  
UIDF3  
Sequence 1, Sequence 2  
Sequence 3  
Sequence 3  
10.1.3 Authentication  
During the authentication process, 4-byte of the UID are passed on to the MIFARE Classic  
Authenticate command of the contactless reader IC. Depending on the activation  
sequence, those 4-byte are chosen differently. In general, the input parameter to the  
MIFARE Classic Authenticate command is the set of 4 bytes retrieved during the last  
cascade level from the ISO/IEC 14443-3 Type A anticollision.  
Table 16. Input parameter to MIFARE Classic Authenticate  
UID Functionality  
Sequence 1  
Input to MIFARE Classic Authenticate Command  
CL2 bytes (UID3...UID6)  
Sequence 2  
CL1 bytes (CT, UID0...UID2)  
Sequence 3  
4-byte NUID/RID (UID0...UID3)  
10.2 4-byte UID Operation  
All MF1S703yXDyy products are featuring a 4-byte NUID. This 4-byte NUID is stored in  
block 0 of sector 0 as shown in Figure 6.  
10.2.1 Anti-collision and Selection  
The anti-collision and selection process for the product variants featuring 4-byte NUIDs is  
done according to ISO/IEC 14443-3 Type A using cascade level 1 only.  
10.2.2 Authentication  
The input parameter to the MIFARE Classic Authenticate command is the full 4-byte UID  
retrieved during the anti-collision procedure. This is the same as for the activation  
Sequence 3 in the 7-byte UID variant.  
11. Load Modulation Strength Option  
The MIFARE Classic EV1 4K features the possibility to set the load modulation strength to  
high or normal. The default level is set to a high modulation strength and it is  
recommended for optimal performance to maintain this level and only switch to the low  
load modulation strength if the contactless system requires it.  
Remark: The configuration becomes effective only after a PICC unselect or a PICC field  
reset. The configuration can be changed multiple times by asserting the command.  
Remark: The MIFARE Classic EV1 4K needs to be authenticated to sector 0 with Key A  
to perform the SET_MOD_TYPE command. The Access Bits for sector 0 are irrelevant.  
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Cmd  
Type  
CRC  
PCD  
ACK  
59 µs  
PICC `ACK`  
T
T
368 µs  
ACK  
NAK  
59 µs  
PICC `NAK`  
TimeOut  
NAK  
T
TimeOut  
001aan919  
Fig 13. SET_MOD_TYPE  
Table 17. SET_MOD_TYPE command  
Name  
Cmd  
Code  
43h  
-
Description  
Length  
Set load modulation strength  
Encoded load modulation strength:  
strong modulation:01h (default)  
normal modulation:00h  
1 byte  
1 byte  
Type  
CRC  
-
CRC according to Ref. 4  
see Section 9.3  
2 bytes  
4-bit  
ACK, NAK  
see Table 10  
Table 18. SET_MOD_TYPE timing  
TACK min  
TACK max  
TNAK min  
TNAK max  
TTimeOut  
5 ms  
SET_MOD_TYPE  
n=9  
TTimeOut  
n=9  
TTimeOut  
The configured load modulation is shown in the manufacturer data of block 0 in sector 0.  
The exact location is shown below in Figure 14 and Table 19.  
Block 0/Sector 0  
Byte  
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
Load Modulation Status Byte  
aaa-012192  
Fig 14. Byte Location of Load Modulation Status in Block 0 / Sector 0  
Table 19. Load Modulation Status Indication  
Bit Number  
Load Modulation Type  
strong load modulation  
normal load modulation  
Hex Value  
20h (default)  
00h  
7
0
0
6
0
0
5
1
0
4
0
0
3
0
0
2
0
0
1
0
0
0
0
0
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12. MIFARE Classic commands  
12.1 MIFARE Authentication  
The MIFARE authentication is a 3-pass mutual authentication which needs two pairs of  
command-response. These two parts, MIFARE authentication part 1 and part 2 are shown  
in Figure 15, Figure 16 and Table 20.  
Table 21 shows the required timing.  
PCD  
Auth  
Addr  
CRC  
Token RB  
PICC ,,ACK''  
T
T
ACK  
368 μs  
359 μs  
PICC ,,NAK''  
NAK  
NAK  
59 μs  
T
TimeOut  
Time out  
001aan004  
Fig 15. MIFARE Authentication part 1  
PCD  
Token AB  
708 µs  
Token BA  
PICC `ACK`  
T
ACK  
359 µs  
T
TimeOut  
TimeOut  
001aan917  
Fig 16. MIFARE Authentication part 2  
Table 20. MIFARE authentication command  
Name  
Code  
Description  
Length  
Auth (with Key A) 60h  
Auth (with Key B) 61h  
Authentication with Key A  
Authentication with Key B  
1 byte  
1 byte  
Addr  
-
MIFARE Block address (00h to FFh) 1 byte  
CRC  
-
CRC according to Ref. 4  
Challenge 1 (Random Number)  
Challenge 2 (encrypted data)  
Challenge 2 (encrypted data)  
see Section 9.3  
2 bytes  
4 bytes  
8 bytes  
4 bytes  
4-bit  
Token RB  
Token AB  
Token BA  
NAK  
-
-
-
see Table 10  
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Table 21. MIFARE authentication timing  
TACK min TACK max  
n=9 TTimeOut  
n=9 TTimeOut  
TNAK min  
TNAK max  
TTimeOut  
1 ms  
Authentication part 1  
Authentication part 2  
n=9  
n=9  
1 ms  
Remark: The minimum required time between MIFARE Authentication part 1 and part 2 is  
the minimum required FDT according to Ref. 4. There is no maximum time specified.  
Remark: The MIFARE authentication and encryption requires an MIFARE reader IC (e.g.  
the CL RC632). For more details about the authentication command refer to the  
corresponding data sheet (e.g. Ref. 5). The 4-byte input parameter for the MIFARE  
Classic Authentication is detailed in Section 10.1.3 and Section 10.2.2.  
12.2 MIFARE Read  
The MIFARE Read requires a block address, and returns the 16 bytes of one  
MIFARE Classic block. The command structure is shown in Figure 17 and Table 22.  
Table 23 shows the required timing.  
PCD  
Cmd  
Addr  
CRC  
Data  
CRC  
PICC ,,ACK''  
T
T
ACK  
368 μs  
1548 μs  
PICC ,,NAK''  
NAK  
NAK  
59 μs  
T
TimeOut  
Time out  
001aan014  
Fig 17. MIFARE Read  
Table 22. MIFARE Read command  
Name  
Cmd  
Addr  
CRC  
Data  
NAK  
Code  
Description  
Read one block  
Length  
30h  
1 byte  
-
MIFARE Block address (00h to FFh) 1 byte  
CRC according to Ref. 4 2 bytes  
Data content of the addressed block 16 bytes  
see Section 9.3 4-bit  
-
-
see Table 10  
Table 23. MIFARE Read timing  
TACK min  
TACK max  
TNAK min  
n=9  
TNAK max  
TTimeOut  
5 ms  
Read  
n=9  
TTimeOut  
TTimeOut  
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12.3 MIFARE Write  
The MIFARE Write requires a block address, and writes 16 bytes of data into the  
addressed MIFARE Classic EV1 4K block. It needs two pairs of command-response.  
These two parts, MIFARE Write part 1 and part 2 are shown in Figure 18 and Figure 19  
and Table 24.  
Table 25 shows the required timing.  
PCD  
Cmd  
Addr  
CRC  
ACK  
PICC ,,ACK''  
T
T
ACK  
368 μs  
59 μs  
PICC ,,NAK''  
NAK  
NAK  
59 μs  
T
TimeOut  
Time out  
001aan015  
Fig 18. MIFARE Write part 1  
PCD  
Data  
CRC  
ACK  
PICC ,,ACK''  
T
T
ACK  
1558 μs  
59 μs  
PICC ,,NAK''  
NAK  
NAK  
59 μs  
T
TimeOut  
Time out  
001aan016  
Fig 19. MIFARE Write part 2  
Table 24. MIFARE Write command  
Name  
Cmd  
Addr  
Code  
A0h  
-
Description  
Length  
Write one block  
1 byte  
MIFARE Block or Page address (00h 1 byte  
to FFh)  
CRC  
Data  
NAK  
-
CRC according to Ref. 4  
Data  
2 bytes  
16 bytes  
4-bit  
-
see Table 10  
see Section 9.3  
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Table 25. MIFARE Write timing  
TACK min  
n=9  
n=9  
TACK max  
TTimeOut  
TNAK min  
n=9  
TNAK max  
TTimeOut  
TTimeOut  
TTimeOut  
5 ms  
Write part 1  
Write part 2  
TTimeOut  
n=9  
10 ms  
Remark: The minimum required time between MIFARE Write part 1 and part 2 is the  
minimum required FDT according to Ref. 4. There is no maximum time specified.  
12.4 MIFARE Increment, Decrement and Restore  
The MIFARE Increment requires a source block address and an operand. It adds the  
operand to the value of the addressed block, and stores the result in the Transfer Buffer.  
The MIFARE Decrement requires a source block address and an operand. It subtracts the  
operand from the value of the addressed block, and stores the result in the Transfer  
Buffer.  
The MIFARE Restore requires a source block address. It copies the value of the  
addressed block into the Transfer Buffer. The 4 byte Operand in the second part of the  
command is not used and may contain arbitrary values.  
All three commands are responding with a NAK to the first command part if the addressed  
block is not formatted to be a valid value block, see Section 8.6.2.1.  
The two parts of each command are shown in Figure 20 and Figure 21 and Table 26.  
Table 27 shows the required timing.  
PCD  
Cmd  
Addr  
CRC  
ACK  
PICC ,,ACK''  
T
T
ACK  
368 μs  
59 μs  
PICC ,,NAK''  
NAK  
NAK  
59 μs  
T
TimeOut  
Time out  
001aan015  
Fig 20. MIFARE Increment, Decrement, Restore part 1  
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PCD  
Data  
CRC  
PICC ,,ACK''  
538 μs  
PICC ,,NAK''  
NAK  
T
NAK  
59 μs  
T
TimeOut  
Time out  
001aan009  
(1) Increment, Decrement and Restore part 2 does not acknowledge  
Fig 21. MIFARE Increment, Decrement, Restore part 2  
Table 26. MIFARE Increment, Decrement and Restore command  
Name  
Cmd  
Cmd  
Cmd  
Addr  
CRC  
Data  
NAK  
Code  
Description  
Increment  
Decrement  
Restore  
Length  
C1h  
1 byte  
1 byte  
1 byte  
C0h  
C2h  
-
MIFARE source block address (00h to FFh) 1 byte  
-
CRC according to Ref. 4  
Operand (4 byte signed integer)  
see Section 9.3  
2 bytes  
4 bytes  
4-bit  
-
see Table 10  
Table 27. MIFARE Increment, Decrement and Restore timing  
TACK min  
TACK max  
TNAK min  
TNAK max  
TTimeOut  
Increment,  
n=9  
TTimeOut  
n=9  
TTimeOut  
5 ms  
Decrement, and  
Restore part 1  
Increment,  
n=9  
TTimeOut  
n=9  
TTimeOut  
5 ms  
Decrement, and  
Restore part 2  
Remark: The minimum required time between MIFARE Increment, Decrement, and  
Restore part 1 and part 2 is the minimum required FDT according to Ref. 4. There is no  
maximum time specified.  
Remark: The MIFARE Increment, Decrement, and Restore commands require a MIFARE  
Transfer to store the value into a destination block.  
Remark: The MIFARE Increment, Decrement, and Restore command part 2 does not  
provide an acknowledgement, so the regular time out has to be used instead.  
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12.5 MIFARE Transfer  
The MIFARE Transfer requires a destination block address, and writes the value stored in  
the Transfer Buffer into one MIFARE Classic block. The command structure is shown in  
Figure 22 and Table 28.  
Table 29 shows the required timing.  
PCD  
Cmd  
Addr  
CRC  
ACK  
PICC ,,ACK''  
T
T
ACK  
368 μs  
59 μs  
PICC ,,NAK''  
NAK  
NAK  
59 μs  
T
TimeOut  
Time out  
001aan015  
Fig 22. MIFARE Transfer  
Table 28. MIFARE Transfer command  
Name  
Code  
Description  
Length  
Cmd  
B0h  
Write the value from the Transfer  
Buffer into destination block  
1 byte  
Addr  
-
MIFARE destination block address  
(00h to FFh)  
1 byte  
CRC  
NAK  
-
CRC according to Ref. 4  
see Section 9.3  
2 bytes  
4-bit  
see Table 10  
Table 29. MIFARE Transfer timing  
TACK min  
TACK max  
TNAK min  
TNAK max  
TTimeOut  
10 ms  
Transfer  
n=9  
TTimeOut  
n=9  
TTimeOut  
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13. Limiting values  
Stresses above one or more of the limiting values may cause permanent damage to the  
device. Exposure to limiting values for extended periods may affect device reliability.  
Table 30. Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol  
II  
Parameter  
Min  
-
Max  
30  
Unit  
mA  
mW  
C  
input current  
Ptot/pack  
Tstg  
total power dissipation per package  
storage temperature  
-
120  
125  
70  
55  
25  
2
Tamb  
ambient temperature  
C  
[1]  
VESD  
electrostatic discharge voltage on LA/LB  
-
kV  
[1] ANSI/ESDA/JEDEC JS-001; Human body model: C = 100 pF, R = 1.5 k  
14. Characteristics  
Table 31. Characteristics  
Symbol  
Parameter  
Conditions  
Min  
14.9  
-
Typ  
Max  
19.0  
-
Unit  
[1]  
Ci  
fi  
input capacitance  
input frequency  
16.9  
pF  
13.56  
MHz  
EEPROM characteristics  
tret  
retention time  
Tamb = 22 C  
Tamb = 22 C  
10  
-
-
-
year  
Nendu(W)  
write endurance  
100000  
200000  
cycle  
[1] Tamb=22°C, f=13,56Mhz, VLaLb = 1,5 V RMS  
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15. Wafer specification  
For more details on the wafer delivery forms see Ref. 9.  
Table 32. Wafer specifications MF1S70yyXDUy  
Wafer  
diameter  
200 mm typical (8 inches)  
210 mm  
maximum diameter after foil expansion  
thicknessMF1S70yyXDUD  
MF1S70yyXDUF  
flatness  
120 m 15 m  
75 m 10 m  
not applicable  
64727  
Potential Good Dies per Wafer (PGDW)  
Wafer backside  
material  
Si  
treatment  
ground and stress relieve  
Ra max = 0.5 m  
Rt max = 5 m  
roughness  
Chip dimensions  
step size[1]  
x = 658 m  
y = 713 m  
gap between chips[1]  
typical = 19 m  
minimum = 5 m  
Passivation  
type  
sandwich structure  
PSG / nitride  
material  
thickness  
500 nm / 600 nm  
Au bump (substrate connected to VSS)  
material  
> 99.9 % pure Au  
35 to 80 HV 0.005  
> 70 MPa  
hardness  
shear strength  
height  
18 m  
height uniformity  
within a die = 2 m  
within a wafer = 3 m  
wafer to wafer = 4 m  
minimum = 1.5 m  
LA, LB, VSS, TEST[2] = 66 m 66 m  
5 m  
flatness  
size  
size variation  
under bump metallization  
sputtered TiW  
[1] The step size and the gap between chips may vary due to changing foil expansion  
[2] Pads VSS and TESTIO are disconnected when wafer is sawn.  
15.1 Fail die identification  
Electronic wafer mapping covers the electrical test results and additionally the results of  
mechanical/visual inspection. No ink dots are applied.  
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15.2 Package outline  
For more details on the contactless modules MOA4 and MOA8 please refer to Ref. 7 and  
Ref. 8.  
PLLMC: plastic leadless module carrier package; 35 mm wide tape  
SOT500-2  
X
D
A
detail X  
0
10  
20 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
max.  
UNIT  
D
For unspecified dimensions see PLLMC-drawing given in the subpackage code.  
35.05  
34.95  
mm  
0.33  
Note  
1. Total package thickness, exclusive punching burr.  
REFERENCES  
JEDEC  
OUTLINE  
VERSION  
EUROPEAN  
PROJECTION  
ISSUE DATE  
IEC  
JEITA  
03-09-17  
06-05-22  
SOT500-2  
- - -  
- - -  
- - -  
Fig 23. Package outline SOT500-2  
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PLLMC: plastic leadless module carrier package; 35 mm wide tape  
SOT500-4  
X
D
A
detail X  
0
10  
20 mm  
scale  
Dimensions  
Unit  
(1)  
A
D
For unspecified dimensions see PLLMC-drawing given in the subpackage code.  
max 0.26 35.05  
mm nom  
min  
35.00  
34.95  
Note  
1. Total package thickness, exclusive punching burr.  
sot500-4_po  
References  
Outline  
version  
European  
projection  
Issue date  
11-02-18  
IEC  
- - -  
JEDEC  
- - -  
JEITA  
- - -  
SOT500-4  
Fig 24. Package outline SOT500-4  
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16. Bare die outline  
For more details on the wafer delivery forms, see Ref. 9.  
x [µm]  
y [µm]  
(1)  
(1)  
658  
713  
Chip Step  
Bump size  
60  
60  
LA, LB, VSS, TEST  
(1)  
typ. 18  
min. 5  
(1)  
typ. 18  
min. 5  
238  
LA  
TESTIO  
(1)  
typ. 713  
633  
43  
VSS  
LB  
43  
y
578  
(1)  
x
typ. 658  
aaa-012193  
(1) The air gap and thus the step size may vary due to varying foil expansion  
(2) All dimensions in µm, pad locations measured from metal ring edge (see detail)  
Fig 25. Bare die outline MF1S70yyXDUz/V1  
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17. Abbreviations  
Table 33. Abbreviations and symbols  
Acronym Description  
ACK  
ATQA  
CRC  
CT  
ACKnowledge  
Answer To reQuest, Type A  
Cyclic Redundancy Check  
Cascade Tag (value 88h) as defined in ISO/IEC 14443-3 Type A  
Electrically Erasable Programmable Read-Only Memory  
Frame Delay Time  
EEPROM  
FDT  
FFC  
Film Frame Carrier  
IC  
Integrated Circuit  
LCR  
LSB  
L = inductance, Capacitance, Resistance (LCR meter)  
Least Significant Bit  
NAK  
NUID  
NV  
Not AcKnowledge  
Non-Unique IDentifier  
Non-Volatile memory  
PCD  
PICC  
REQA  
RID  
Proximity Coupling Device (Contactless Reader)  
Proximity Integrated Circuit Card (Contactless Card)  
REQuest command, Type A  
Random ID  
RF  
Radio Frequency  
RMS  
RNG  
SAK  
SECS-II  
TiW  
Root Mean Square  
Random Number Generator  
Select AcKnowledge, type A  
SEMI Equipment Communications Standard part 2  
Titanium Tungsten  
UID  
Unique IDentifier  
WUPA  
Wake-Up Protocol type A  
18. References  
[1] MIFARE (Card) Coil Design Guide — Application note, BU-ID Document  
number 0117**1  
[2] MIFARE Type Identification Procedure — Application note, BU-ID Document  
number 0184**1  
[3] ISO/IEC 14443-2 — 2001  
[4] ISO/IEC 14443-3 — 2001  
[5] MIFARE & I-CODE CL RC632 Multiple protocol contactless reader IC —  
Product data sheet  
1. ** ... document version number  
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[6] MIFARE and handling of UIDs — Application note, BU-ID Document number  
1907**1  
[7] Contactless smart card module specification MOA4 — Delivery Type  
Description, BU-ID Document number 0823**1  
[8] Contactless smart card module specification MOA8 — Delivery Type  
Description, BU-ID Document number 1636**1  
[9] General specification for 8" wafer on UV-tape; delivery types — Delivery Type  
Description, BU-ID Document number 1005**1  
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19. Revision history  
Table 34. Revision history  
Document ID  
Release date  
20140303  
Data sheet status  
Change notice  
Supersedes  
MF1S70yyX_V1 v.3.0  
Product data sheet  
-
-
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20. Legal information  
20.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
Suitability for use — NXP Semiconductors products are not designed,  
20.2 Definitions  
authorized or warranted to be suitable for use in life support, life-critical or  
safety-critical systems or equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors and its suppliers accept no liability for  
inclusion and/or use of NXP Semiconductors products in such equipment or  
applications and therefore such inclusion and/or use is at the customer’s own  
risk.  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
Customers are responsible for the design and operation of their applications  
and products using NXP Semiconductors products, and NXP Semiconductors  
accepts no liability for any assistance with applications or customer product  
design. It is customer’s sole responsibility to determine whether the NXP  
Semiconductors product is suitable and fit for the customer’s applications and  
products planned, as well as for the planned application and use of  
customer’s third party customer(s). Customers should provide appropriate  
design and operating safeguards to minimize the risks associated with their  
applications and products.  
Product specification — The information and data provided in a Product  
data sheet shall define the specification of the product as agreed between  
NXP Semiconductors and its customer, unless NXP Semiconductors and  
customer have explicitly agreed otherwise in writing. In no event however,  
shall an agreement be valid in which the NXP Semiconductors product is  
deemed to offer functions and qualities beyond those described in the  
Product data sheet.  
NXP Semiconductors does not accept any liability related to any default,  
damage, costs or problem which is based on any weakness or default in the  
customer’s applications or products, or the application or use by customer’s  
third party customer(s). Customer is responsible for doing all necessary  
testing for the customer’s applications and products using NXP  
Semiconductors products in order to avoid a default of the applications and  
the products or of the application or use by customer’s third party  
customer(s). NXP does not accept any liability in this respect.  
20.3 Disclaimers  
Limited warranty and liability — Information in this document is believed to  
be accurate and reliable. However, NXP Semiconductors does not give any  
representations or warranties, expressed or implied, as to the accuracy or  
completeness of such information and shall have no liability for the  
consequences of use of such information. NXP Semiconductors takes no  
responsibility for the content in this document if provided by an information  
source outside of NXP Semiconductors.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) will cause permanent  
damage to the device. Limiting values are stress ratings only and (proper)  
operation of the device at these or any other conditions above those given in  
the Recommended operating conditions section (if present) or the  
Characteristics sections of this document is not warranted. Constant or  
repeated exposure to limiting values will permanently and irreversibly affect  
the quality and reliability of the device.  
In no event shall NXP Semiconductors be liable for any indirect, incidental,  
punitive, special or consequential damages (including - without limitation - lost  
profits, lost savings, business interruption, costs related to the removal or  
replacement of any products or rework charges) whether or not such  
damages are based on tort (including negligence), warranty, breach of  
contract or any other legal theory.  
Terms and conditions of commercial sale — NXP Semiconductors  
products are sold subject to the general terms and conditions of commercial  
sale, as published at http://www.nxp.com/profile/terms, unless otherwise  
agreed in a valid written individual agreement. In case an individual  
agreement is concluded only the terms and conditions of the respective  
agreement shall apply. NXP Semiconductors hereby expressly objects to  
applying the customer’s general terms and conditions with regard to the  
purchase of NXP Semiconductors products by customer.  
Notwithstanding any damages that customer might incur for any reason  
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards  
customer for the products described herein shall be limited in accordance  
with the Terms and conditions of commercial sale of NXP Semiconductors.  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
No offer to sell or license — Nothing in this document may be interpreted or  
construed as an offer to sell products that is open for acceptance or the grant,  
conveyance or implication of any license under any copyrights, patents or  
other industrial or intellectual property rights.  
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Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from competent authorities.  
whenever customer uses the product for automotive applications beyond  
NXP Semiconductors’ specifications such use shall be solely at customer’s  
own risk, and (c) customer fully indemnifies NXP Semiconductors for any  
liability, damages or failed product claims resulting from customer design and  
use of the product for automotive applications beyond NXP Semiconductors’  
standard warranty and NXP Semiconductors’ product specifications.  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
Translations — A non-English (translated) version of a document is for  
reference only. The English version shall prevail in case of any discrepancy  
between the translated and English versions.  
Non-automotive qualified products — Unless this data sheet expressly  
states that this specific NXP Semiconductors product is automotive qualified,  
the product is not suitable for automotive use. It is neither qualified nor tested  
in accordance with automotive testing or application requirements. NXP  
Semiconductors accepts no liability for inclusion and/or use of  
20.4 Trademarks  
non-automotive qualified products in automotive equipment or applications.  
In the event that customer uses the product for design-in and use in  
automotive applications to automotive specifications and standards, customer  
(a) shall use the product without NXP Semiconductors’ warranty of the  
product for such automotive applications, use and specifications, and (b)  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
MIFARE — is a trademark of NXP Semiconductors N.V.  
21. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
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22. Tables  
Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2  
Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3  
Table 3. Pin allocation table . . . . . . . . . . . . . . . . . . . . . . .4  
Table 4. Value block format example . . . . . . . . . . . . . . .11  
Table 5. Memory operations. . . . . . . . . . . . . . . . . . . . . .12  
Table 6. Access conditions. . . . . . . . . . . . . . . . . . . . . . .13  
Table 7. Access conditions for the sector trailer . . . . . .14  
Table 8. Access conditions for data blocks. . . . . . . . . . .15  
Table 9. Command overview . . . . . . . . . . . . . . . . . . . . .16  
Table 10. MIFARE ACK and NAK . . . . . . . . . . . . . . . . . .18  
Table 11. ATQA response of the MF1S70yyX/V1 . . . . . .18  
Table 12. SAK response of the MF1S70yyX/V1. . . . . . . .18  
Table 13. Personalize UID Usage command . . . . . . . . . .20  
Table 14. Personalize UID Usage timing . . . . . . . . . . . . .20  
Table 15. Available activation sequences for  
7-byte UID options . . . . . . . . . . . . . . . . . . . . . .21  
Table 16. Input parameter to MIFARE Classic  
Authenticate . . . . . . . . . . . . . . . . . . . . . . . . . . .21  
Table 17. SET_MOD_TYPE command . . . . . . . . . . . . . .22  
Table 18. SET_MOD_TYPE timing . . . . . . . . . . . . . . . . .22  
Table 19. Load Modulation Status Indication . . . . . . . . . .22  
Table 20. MIFARE authentication command . . . . . . . . . .23  
Table 21. MIFARE authentication timing . . . . . . . . . . . . .24  
Table 22. MIFARE Read command . . . . . . . . . . . . . . . . .24  
Table 23. MIFARE Read timing . . . . . . . . . . . . . . . . . . . .24  
Table 24. MIFARE Write command . . . . . . . . . . . . . . . . .25  
Table 25. MIFARE Write timing . . . . . . . . . . . . . . . . . . . .26  
Table 26. MIFARE Increment, Decrement  
and Restore command . . . . . . . . . . . . . . . . . . .27  
Table 27. MIFARE Increment, Decrement  
and Restore timing . . . . . . . . . . . . . . . . . . . . . .27  
Table 28. MIFARE Transfer command . . . . . . . . . . . . . . .28  
Table 29. MIFARE Transfer timing . . . . . . . . . . . . . . . . . .28  
Table 30. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .29  
Table 31. Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .29  
Table 32. Wafer specifications MF1S70yyXDUy . . . . . . .30  
Table 33. Abbreviations and symbols . . . . . . . . . . . . . . .34  
Table 34. Revision history . . . . . . . . . . . . . . . . . . . . . . . .36  
MF1S70yyX_V1  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2014. All rights reserved.  
Product data sheet  
COMPANY PUBLIC  
Rev. 3.0 — 3 March 2014  
279330  
39 of 41  
MF1S70yyX/V1  
NXP Semiconductors  
MIFARE Classic EV1 4K - Mainstream contactless smart card IC  
23. Figures  
Fig 1. Contactless MIFARE system . . . . . . . . . . . . . . . . .1  
Fig 2. Block diagram of MF1S70yyX/V1 . . . . . . . . . . . . .3  
Fig 3. Pin configuration for SOT500-2 (MOA4) . . . . . . . .4  
Fig 4. MIFARE Classic command flow diagram. . . . . . . .6  
Fig 5. Memory organization . . . . . . . . . . . . . . . . . . . . . . .9  
Fig 6. Manufacturer block for MF1S503yX  
with 4-byte NUID . . . . . . . . . . . . . . . . . . . . . . . . .10  
Fig 7. Manufacturer block for MF1S500yX  
with 7-byte UID . . . . . . . . . . . . . . . . . . . . . . . . . .10  
Fig 8. Value blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . .11  
Fig 9. Sector trailer . . . . . . . . . . . . . . . . . . . . . . . . . . . .12  
Fig 10. Access conditions . . . . . . . . . . . . . . . . . . . . . . . .13  
Fig 11. Frame Delay Time (from PCD to PICC)  
and TACK and TNAK. . . . . . . . . . . . . . . . . . . . . . . .17  
Fig 12. Personalize UID Usage . . . . . . . . . . . . . . . . . . . .20  
Fig 13. SET_MOD_TYPE . . . . . . . . . . . . . . . . . . . . . . . .22  
Fig 14. Byte Location of Load Modulation Status  
in Block 0 / Sector 0. . . . . . . . . . . . . . . . . . . . . . .22  
Fig 15. MIFARE Authentication part 1 . . . . . . . . . . . . . . .23  
Fig 16. MIFARE Authentication part 2 . . . . . . . . . . . . . . .23  
Fig 17. MIFARE Read . . . . . . . . . . . . . . . . . . . . . . . . . . .24  
Fig 18. MIFARE Write part 1 . . . . . . . . . . . . . . . . . . . . . .25  
Fig 19. MIFARE Write part 2 . . . . . . . . . . . . . . . . . . . . . .25  
Fig 20. MIFARE Increment, Decrement, Restore part 1 .26  
Fig 21. MIFARE Increment, Decrement, Restore part 2 .27  
Fig 22. MIFARE Transfer . . . . . . . . . . . . . . . . . . . . . . . . .28  
Fig 23. Package outline SOT500-2 . . . . . . . . . . . . . . . . .31  
Fig 24. Package outline SOT500-4 . . . . . . . . . . . . . . . . .32  
Fig 25. Bare die outline MF1S70yyXDUz/V1. . . . . . . . . .33  
MF1S70yyX_V1  
All information provided in this document is subject to legal disclaimers.  
© NXP Semiconductors N.V. 2014. All rights reserved.  
Product data sheet  
COMPANY PUBLIC  
Rev. 3.0 — 3 March 2014  
279330  
40 of 41  
MF1S70yyX/V1  
NXP Semiconductors  
MIFARE Classic EV1 4K - Mainstream contactless smart card IC  
24. Contents  
1
General description. . . . . . . . . . . . . . . . . . . . . . 1  
11  
Load Modulation Strength Option . . . . . . . . . 21  
1.1  
1.2  
1.3  
1.4  
Anticollision. . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Simple integration and user convenience. . . . . 1  
Security and privacy . . . . . . . . . . . . . . . . . . . . . 1  
Delivery options . . . . . . . . . . . . . . . . . . . . . . . . 1  
12  
MIFARE Classic commands. . . . . . . . . . . . . . 23  
MIFARE Authentication . . . . . . . . . . . . . . . . . 23  
MIFARE Read . . . . . . . . . . . . . . . . . . . . . . . . 24  
MIFARE Write . . . . . . . . . . . . . . . . . . . . . . . . 25  
MIFARE Increment, Decrement and Restore 26  
MIFARE Transfer . . . . . . . . . . . . . . . . . . . . . . 28  
12.1  
12.2  
12.3  
12.4  
12.5  
2
2.1  
3
Features and benefits . . . . . . . . . . . . . . . . . . . . 2  
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2  
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2  
Ordering information. . . . . . . . . . . . . . . . . . . . . 3  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 3  
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
13  
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . 29  
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 29  
Wafer specification . . . . . . . . . . . . . . . . . . . . . 30  
Fail die identification . . . . . . . . . . . . . . . . . . . 30  
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 31  
Bare die outline . . . . . . . . . . . . . . . . . . . . . . . . 33  
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 34  
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34  
Revision history . . . . . . . . . . . . . . . . . . . . . . . 36  
14  
4
15  
5
15.1  
15.2  
16  
6
7
7.1  
17  
8
8.1  
8.2  
8.2.1  
8.2.2  
8.2.3  
8.2.4  
8.2.5  
8.3  
Functional description . . . . . . . . . . . . . . . . . . . 5  
Block description . . . . . . . . . . . . . . . . . . . . . . . 5  
Communication principle . . . . . . . . . . . . . . . . . 5  
Request standard / all. . . . . . . . . . . . . . . . . . . . 5  
Anticollision loop. . . . . . . . . . . . . . . . . . . . . . . . 5  
Select card . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6  
Three pass authentication . . . . . . . . . . . . . . . . 6  
Memory operations. . . . . . . . . . . . . . . . . . . . . . 7  
Data integrity. . . . . . . . . . . . . . . . . . . . . . . . . . . 7  
Three pass authentication sequence . . . . . . . . 7  
RF interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 8  
Memory organization . . . . . . . . . . . . . . . . . . . . 8  
Manufacturer block. . . . . . . . . . . . . . . . . . . . . 10  
Data blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Value blocks . . . . . . . . . . . . . . . . . . . . . . . . . . 10  
Sector trailer . . . . . . . . . . . . . . . . . . . . . . . . . . 11  
Memory access . . . . . . . . . . . . . . . . . . . . . . . 12  
Access conditions. . . . . . . . . . . . . . . . . . . . . . 13  
Access conditions for the sector trailer. . . . . . 14  
Access conditions for data blocks. . . . . . . . . . 15  
18  
19  
20  
Legal information . . . . . . . . . . . . . . . . . . . . . . 37  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 37  
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 37  
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 38  
20.1  
20.2  
20.3  
20.4  
21  
22  
23  
24  
Contact information . . . . . . . . . . . . . . . . . . . . 38  
Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39  
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40  
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41  
8.4  
8.5  
8.6  
8.6.1  
8.6.2  
8.6.2.1  
8.6.3  
8.7  
8.7.1  
8.7.2  
8.7.3  
9
Command overview. . . . . . . . . . . . . . . . . . . . . 16  
MIFARE Classic command overview . . . . . . . 16  
Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17  
MIFARE Classic ACK and NAK . . . . . . . . . . . 18  
ATQA and SAK responses . . . . . . . . . . . . . . . 18  
9.1  
9.2  
9.3  
9.4  
10  
10.1  
UID Options and Handling . . . . . . . . . . . . . . . 19  
7-byte UID Operation . . . . . . . . . . . . . . . . . . . 19  
Personalization Options . . . . . . . . . . . . . . . . . 19  
Anti-collision and Selection. . . . . . . . . . . . . . . 20  
Authentication. . . . . . . . . . . . . . . . . . . . . . . . . 21  
4-byte UID Operation . . . . . . . . . . . . . . . . . . . 21  
Anti-collision and Selection. . . . . . . . . . . . . . . 21  
Authentication. . . . . . . . . . . . . . . . . . . . . . . . . 21  
10.1.1  
10.1.2  
10.1.3  
10.2  
10.2.1  
10.2.2  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP Semiconductors N.V. 2014.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 3 March 2014  
279330  

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