MFRC522_09 [NXP]

Contactless reader IC; 非接触式读卡器IC
MFRC522_09
型号: MFRC522_09
厂家: NXP    NXP
描述:

Contactless reader IC
非接触式读卡器IC

文件: 总96页 (文件大小:507K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
MFRC522  
Contactless reader IC  
Rev. 3.3 — 26 October 2009  
112133  
Product data sheet  
PUBLIC  
1. Introduction  
This document describes the functionality and electrical specifications of the contactless  
reader/writer MFRC522.  
2. General description  
The MFRC522 is a highly integrated reader/writer IC for contactless communication  
at 13.56 MHz. The MFRC522 reader supports ISO/IEC 14443 A/MIFARE mode.  
The MFRC522’s internal transmitter is able to drive a reader/writer antenna designed to  
communicate with ISO/IEC 14443 A/MIFARE cards and transponders without additional  
active circuitry. The receiver module provides a robust and efficient implementation for  
demodulating and decoding signals from ISO/IEC 14443 A/MIFARE compatible cards and  
transponders. The digital module manages the complete ISO/IEC 14443 A framing and  
error detection (parity and CRC) functionality.  
The MFRC522 supports MF1xxS20, MF1xxS70 and MF1xxS50 products. The MFRC522  
supports contactless communication and uses MIFARE higher transfer speeds up to  
848 kBd in both directions.  
The following host interfaces are provided:  
Serial Peripheral Interface (SPI)  
Serial UART (similar to RS232 with voltage levels dependant on pin voltage supply)  
I2C-bus interface  
3. Features  
I Highly integrated analog circuitry to demodulate and decode responses  
I Buffered output drivers for connecting an antenna with the minimum number of  
external components  
I Supports ISO/IEC 14443 A/MIFARE  
I Typical operating distance in Read/Write mode up to 50 mm depending on the  
antenna size and tuning  
I Supports MF1xxS20, MF1xxS70 and MF1xxS50 encryption in Read/Write mode  
I Supports ISO/IEC 14443 A higher transfer speed communication up to 848 kBd  
I Supports MFIN/MFOUT  
I Additional internal power supply to the smart card IC connected via MFIN/MFOUT  
I Supported host interfaces  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
N SPI up to 10 Mbit/s  
N I2C-bus interface up to 400 kBd in Fast mode, up to 3400 kBd in High-speed mode  
N RS232 Serial UART up to 1228.8 kBd, with voltage levels dependant on pin voltage  
supply  
I FIFO buffer handles 64 byte send and receive  
I Flexible interrupt modes  
I Hard reset with low power function  
I Power-down by software mode  
I Programmable timer  
I Internal oscillator for connection to 27.12 MHz quartz crystal  
I 2.5 V to 3.3 V power supply  
I CRC coprocessor  
I Programmable I/O pins  
I Internal self-test  
4. Quick reference data  
Table 1.  
Quick reference data  
Symbol Parameter  
Conditions  
Min  
2.5  
2.5  
2.5  
1.6  
1.6  
Typ  
3.3  
3.3  
3.3  
1.8  
-
Max  
3.6  
3.6  
3.6  
3.6  
3.6  
Unit  
V
[1][2]  
[3]  
VDDA  
VDDD  
analog supply voltage  
digital supply voltage  
V
V
DD(PVDD) VDDA = VDDD = VDD(TVDD)  
SSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V  
;
V
VDD(TVDD) TVDD supply voltage  
VDD(PVDD) PVDD supply voltage  
VDD(SVDD) SVDD supply voltage  
V
V
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V  
VDDA = VDDD = VDD(TVDD) = VDD(PVDD) = 3 V  
hard power-down; pin NRSTPD set LOW  
soft power-down; RF level detector on  
pin DVDD; VDDD = 3 V  
V
Ipd  
power-down current  
[4]  
[4]  
-
-
-
-
-
5
µA  
-
10  
9
µA  
IDDD  
IDDA  
digital supply current  
analog supply current  
6.5  
7
mA  
mA  
pin AVDD; VDDA = 3 V, CommandReg register’s  
RcvOff bit = 0  
10  
pin AVDD; receiver switched off; VDDA = 3 V,  
CommandReg register’s RcvOff bit = 1  
-
3
5
mA  
[5]  
IDD(PVDD) PVDD supply current  
IDD(TVDD) TVDD supply current  
pin PVDD  
-
-
40  
mA  
mA  
°C  
[6][7][8]  
pin TVDD; continuous wave  
HVQFN32  
-
60  
-
100  
+85  
Tamb  
ambient temperature  
25  
[1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance.  
[2] VDDA, VDDD and VDD(TVDD) must always be the same voltage.  
[3] VDD(PVDD) must always be the same or lower voltage than VDDD  
[4] Ipd is the total current for all supplies.  
.
[5] IDD(PVDD) depends on the overall load at the digital pins.  
[6] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2.  
[7] During typical circuit operation, the overall current is below 100 mA.  
[8] Typical value using a complementary driver configuration and an antenna matched to 40 between pins TX1 and TX2 at 13.56 MHz.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
2 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
5. Ordering information  
Table 2.  
Ordering information  
Type number  
Package  
Name  
Description  
Version  
MFRC52201HN1/TRAYB[1]  
HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;  
SOT617-1  
32 terminal; body 5 × 5 × 0.85 mm  
MFRC52201HN1/TRAYBM[2] HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;  
SOT617-1  
32 terminal; body 5 × 5 × 0.85 mm  
[1] Delivered in one tray.  
[2] Delivered in five trays.  
6. Block diagram  
The analog interface handles the modulation and demodulation of the analog signals.  
The contactless UART manages the protocol requirements for the communication  
protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data  
transfer to and from the host and the contactless UART and vice versa.  
Various host interfaces are implemented to meet different customer requirements.  
REGISTER BANK  
ANALOG  
INTERFACE  
CONTACTLESS  
UART  
ANTENNA  
FIFO  
BUFFER  
SERIAL UART  
SPI  
I C-BUS  
HOST  
2
001aaj627  
Fig 1. Simplified block diagram of the MFRC522  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
3 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
D6/ADR_0/  
MOSI/MX  
D2/ADR_4  
D1/ADR_5 D3/ADR_3  
25 26 27  
D4/ADR_2  
D5/ADR_1/  
D7/SCL/  
SDA/NSS/RX EA I2C  
24 32  
PVDD PVSS  
SCK/DTRQ  
MISO/TX  
1
28  
29  
30  
31  
2
5
3
DVDD  
VOLTAGE  
MONITOR  
AND  
POWER ON  
DETECT  
4
DVSS  
2
SPI, UART, I C-BUS INTERFACE CONTROL  
15  
18  
AVDD  
AVSS  
FIFO CONTROL  
STATE MACHINE  
64-BYTE FIFO  
BUFFER  
RESET  
CONTROL  
COMMAND REGISTER  
PROGRAMABLE TIMER  
INTERRUPT CONTROL  
CRC16  
6
POWER-DOWN  
CONTROL  
NRSTPD  
IRQ  
CONTROL REGISTER  
BANK  
23  
MIFARE CLASSIC UNIT  
GENERATION AND CHECK  
RANDOM NUMBER  
GENERATOR  
PARALLEL/SERIAL  
CONVERTER  
BIT COUNTER  
PARITY GENERATION AND CHECK  
FRAME GENERATION AND CHECK  
BIT DECODING  
BIT ENCODING  
7
8
9
MFIN  
SERIAL DATA SWITCH  
MFOUT  
SVDD  
21  
22  
CLOCK  
OSCIN  
GENERATION,  
FILTERING AND  
DISTRIBUTION  
AMPLITUDE  
RATING  
OSCILLATOR  
ANALOG TO DIGITAL  
CONVERTER  
OSCOUT  
REFERENCE  
VOLTAGE  
Q-CLOCK  
GENERATION  
TEMPERATURE  
SENSOR  
ANALOG TEST  
MULTIPLEXOR  
AND  
DIGITAL TO  
ANALOG  
I-CHANNEL  
AMPLIFIER  
Q-CHANNEL  
AMPLIFIER  
TRANSMITTER CONTROL  
I-CHANNEL  
DEMODULATOR  
Q-CHANNEL  
DEMODULATOR  
CONVERTER  
16  
19  
20  
17  
RX  
10, 14  
TVSS  
11  
TX1  
13  
TX2  
12  
VMID AUX1 AUX2  
TVDD  
001aak602  
Fig 2. Detailed block diagram of the MFRC522  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
4 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
7. Pinning information  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
I2C  
PVDD  
SDA/NSS/RX  
IRQ  
DVDD  
OSCOUT  
OSCIN  
AUX2  
AUX1  
AVSS  
RX  
DVSS  
MFRC522  
PVSS  
NRSTPD  
MFIN  
MFOUT  
001aaj819  
Transparent top view  
Fig 3. Pinning configuration HVQFN32 (SOT617-1)  
7.1 Pin description  
Table 3.  
Pin description  
Pin  
1
Symbol  
I2C  
Type[1] Description  
I
I2C-bus enable input[2]  
2
PVDD  
DVDD  
DVSS  
PVSS  
NRSTPD  
P
P
G
G
I
pin power supply  
3
digital power supply  
digital ground[3]  
4
5
pin power supply ground  
reset and power-down input:  
6
power-down: enabled when LOW; internal current sinks are switched off, the oscillator  
is inhibited and the input pins are disconnected from the outside world  
reset: enabled by a positive edge  
7
MFIN  
MFOUT  
SVDD  
TVSS  
TX1  
I
MIFARE signal input  
8
O
P
G
O
P
O
G
P
MIFARE signal output  
9
MFIN and MFOUT pin power supply  
transmitter output stage 1 ground  
10  
11  
12  
13  
14  
15  
transmitter 1 modulated 13.56 MHz energy carrier output  
transmitter power supply: supplies the output stage of transmitters 1 and 2  
transmitter 2 modulated 13.56 MHz energy carrier output  
transmitter output stage 2 ground  
TVDD  
TX2  
TVSS  
AVDD  
analog power supply  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
5 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 3.  
Pin  
16  
Pin description …continued  
Symbol  
VMID  
RX  
Type[1] Description  
P
I
internal reference voltage  
17  
RF signal input  
18  
AVSS  
AUX1  
AUX2  
OSCIN  
G
O
O
I
analog ground  
19  
auxiliary outputs for test purposes  
auxiliary outputs for test purposes  
20  
21  
crystal oscillator inverting amplifier input; also the input for an externally generated clock  
(fclk = 27.12 MHz)  
22  
23  
24  
OSCOUT  
IRQ  
O
crystal oscillator inverting amplifier output  
interrupt request output: indicates an interrupt event  
I2C-bus serial data line input/output[2]  
SPI signal input[2]  
O
SDA  
NSS  
RX  
I/O  
I
I
UART address input[2]  
25  
26  
27  
28  
29  
D1  
I/O  
I/O  
I/O  
I
test port[2]  
I2C-bus address 5 input[2]  
ADR_5  
D2  
test port  
ADR_4  
D3  
I2C-bus address 4 input[2]  
test port  
I2C-bus address 3 input[2]  
I/O  
I
ADR_3  
D4  
I/O  
I
test port  
ADR_2  
D5  
I2C-bus address 2 input[2]  
test port  
I2C-bus address 1 input[2]  
SPI serial clock input[2]  
I/O  
I
ADR_1  
SCK  
DTRQ  
D6  
I
O
UART request to send output to microcontroller[2]  
30  
31  
32  
I/O  
I
test port  
ADR_0  
MOSI  
MX  
I2C-bus address 0 input[2]  
SPI master out, slave in[2]  
UART output to microcontroller[2]  
test port  
I2C-bus clock input/output[2]  
SPI master in, slave out[2]  
UART data output to microcontroller[2]  
external address input for coding I2C-bus address[2]  
I/O  
O
D7  
I/O  
I/O  
I/O  
O
SCL  
MISO  
TX  
EA  
I
[1] Pin types: I = Input, O = Output, I/O = Input/Output, P = Power and G = Ground.  
[2] The pin functionality of these pins is explained in Section 8.1 “Digital interfaces”.  
[3] Connection of heatsink pad on package bottom side is not necessary. Optional connection to pin DVSS is possible.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
6 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
8. Functional description  
The MFRC522 transmission module supports the Read/Write mode for  
ISO/IEC 14443 A/MIFARE using various transfer speeds and modulation protocols.  
BATTERY  
MFRC522  
ISO/IEC 14443 A CARD  
MICROCONTROLLER  
contactless card  
001aak583  
reader/writer  
Fig 4. MFRC522 Read/Write mode  
The physical level communication is shown in Figure 5.  
(1)  
ISO/IEC 14443 A  
READER  
ISO/IEC 14443 A CARD  
(2)  
MFRC522  
001aak584  
(1) Reader to card 100 % ASK, Miller encoded, transfer speed 106 kBd to 848 kBd.  
(2) Card to reader subcarrier load modulation, Manchester encoded or BPSK, transfer speed 106 kBd  
to 848 kBd.  
Fig 5. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram  
The physical parameters are described in Table 4.  
Table 4.  
Communication overview for ISO/IEC 14443 A/MIFARE reader/writer  
Communication  
direction  
Signal type  
Transfer speed  
106 kBd  
212 kBd  
424 kBd  
848 kBd  
Reader to card (send  
data from the  
reader side  
modulation  
100 % ASK  
100 % ASK  
100 % ASK  
100 % ASK  
MFRC522 to a card)  
bit encoding  
modified Miller  
encoding  
modified Miller  
encoding  
modified Miller  
encoding  
modified Miller  
encoding  
bit length  
128 (13.56 µs)  
64 (13.56 µs)  
32 (13.56 µs)  
16 (13.56 µs)  
Card to reader  
(MFRC522 receives  
data from a card)  
card side  
modulation  
subcarrier load  
modulation  
subcarrier load  
modulation  
subcarrier load  
modulation  
subcarrier load  
modulation  
subcarrier  
frequency  
13.56 MHz/16  
13.56 MHz/16  
13.56 MHz/16  
13.56 MHz/16  
bit encoding  
Manchester  
encoding  
BPSK  
BPSK  
BPSK  
The MFRC522’s contactless UART and dedicated external host must manage the  
complete ISO/IEC 14443 A/MIFARE protocol. Figure 6 shows the data coding and  
framing according to ISO/IEC 14443 A/MIFARE.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
7 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
ISO/IEC 14443 A framing at 106 kBd  
start  
8-bit data  
8-bit data  
8-bit data  
odd  
odd  
odd  
parity  
parity  
parity  
start bit is 1  
ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd  
start  
even  
parity  
8-bit data  
8-bit data  
8-bit data  
odd  
parity  
odd  
parity  
start bit is 0  
burst of 32  
subcarrier clocks  
even parity at the  
end of the frame  
001aak585  
Fig 6. Data coding and framing according to ISO/IEC 14443 A  
The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A  
part 3 and handles parity generation internally according to the transfer speed. Automatic  
parity generation can be switched off using the MfRxReg register’s ParityDisable bit.  
8.1 Digital interfaces  
8.1.1 Automatic microcontroller interface detection  
The MFRC522 supports direct interfacing of hosts using SPI, I2C-bus or serial UART  
interfaces. The MFRC522 resets its interface and checks the current host interface type  
automatically after performing a power-on or hard reset. The MFRC522 identifies the host  
interface by sensing the logic levels on the control pins after the reset phase. This is done  
using a combination of fixed pin connections. Table 5 shows the different connection  
configurations.  
Table 5.  
Pin  
Connection protocol for detecting different interface types  
Interface type  
UART (input)  
SPI (output)  
I2C-bus (I/O)  
SDA  
SDA  
I2C  
EA  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
RX  
NSS  
0
0
1
0
1
EA  
TX  
MISO  
SCL  
MX  
MOSI  
ADR_0  
ADR_1  
ADR_2  
ADR_3  
ADR_4  
ADR_5  
DTRQ  
SCK  
-
-
-
-
-
-
-
-
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
8 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
8.1.2 Serial Peripheral Interface  
A serial peripheral interface (SPI compatible) is supported to enable high-speed  
communication to the host. The interface can handle data speeds up to 10 Mbit/s. When  
communicating with a host, the MFRC522 acts as a slave, receiving data from the  
external host for register settings, sending and receiving data relevant for RF interface  
communication.  
An interface compatible with SPI enables high-speed serial communication between the  
MFRC522 and a microcontroller. The implemented interface is in accordance with the SPI  
standard.  
The timing specification is given in Section 14.1 on page 75.  
MFRC522  
SCK  
SCK  
MOSI  
MOSI  
MISO  
MISO  
NSS  
NSS  
001aak586  
Fig 7. SPI connection to host  
The MFRC522 acts as a slave during SPI communication. The SPI clock signal SCK must  
be generated by the master. Data communication from the master to the slave uses the  
MOSI line. The MISO line is used to send data from the MFRC522 to the master.  
Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSI  
and MISO lines must be stable on the rising edge of the clock and can be changed on the  
falling edge. Data is provided by the MFRC522 on the falling clock edge and is stable  
during the rising clock edge.  
8.1.2.1 SPI read data  
Reading data using SPI requires the byte order shown in Table 6 to be used. It is possible  
to read out up to n-data bytes.  
The first byte sent defines both the mode and the address.  
Table 6.  
Line  
MOSI and MISO byte order  
Byte 0  
address 0  
X[1]  
Byte 1  
Byte 2  
To  
...  
Byte n  
Byte n + 1  
00  
MOSI  
MISO  
address 1  
data 0  
address 2  
data 1  
address n  
data n 1  
...  
data n  
[1] X = Do not care.  
Remark: The MSB must be sent first.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
9 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
8.1.2.2 SPI write data  
To write data to the MFRC522 using SPI requires the byte order shown in Table 7. It is  
possible to write up to n data bytes by only sending one address byte.  
The first send byte defines both the mode and the address byte.  
Table 7.  
Line  
MOSI and MISO byte order  
Byte 0  
address 0  
X[1]  
Byte 1  
data 0  
X[1]  
Byte 2  
data 1  
X[1]  
To  
...  
Byte n  
data n 1  
X[1]  
Byte n + 1  
data n  
X[1]  
MOSI  
MISO  
...  
[1] X = Do not care.  
Remark: The MSB must be sent first.  
8.1.2.3 SPI address byte  
The address byte must meet the following format.  
The MSB of the first byte defines the mode used. To read data from the MFRC522 the  
MSB is set to logic 1. To write data to the MFRC522 the MSB must be set to logic 0. Bits 6  
to 1 define the address and the LSB is set to logic 0.  
Table 8.  
7 (MSB)  
Address byte 0 register; address MOSI  
6
5
4
3
2
1
0 (LSB)  
1 = read  
0 = write  
address  
0
8.1.3 UART interface  
8.1.3.1 Connection to a host  
MFRC522  
RX  
TX  
RX  
TX  
DTRQ  
MX  
DTRQ  
MX  
001aak587  
Fig 8. UART connection to microcontrollers  
Remark: Signals DTRQ and MX can be disabled by clearing TestPinEnReg register’s  
RS232LineEn bit.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
10 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
8.1.3.2 Selectable UART transfer speeds  
The internal UART interface is compatible with an RS232 serial interface.  
The default transfer speed is 9.6 kBd. To change the transfer speed, the host controller  
must write a value for the new transfer speed to the SerialSpeedReg register. Bits  
BR_T0[2:0] and BR_T1[4:0] define the factors for setting the transfer speed in the  
SerialSpeedReg register.  
The BR_T0[2:0] and BR_T1[4:0] settings are described in Table 9. Examples of different  
transfer speeds and the relevant register settings are given in Table 10.  
Table 9.  
BR_T0 and BR_T1 settings  
BR_Tn  
Bit 0  
Bit 1  
Bit 2  
Bit 3  
Bit 4  
Bit 5  
Bit 6  
Bit 7  
BR_T0 factor  
BR_T1 range  
1
1
2
4
8
16  
32  
64  
1 to 32 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64  
Table 10. Selectable UART transfer speeds  
Transfer speed (kBd)  
SerialSpeedReg value  
Transfer speed accuracy  
(%)[1]  
Decimal  
250  
235  
218  
203  
171  
154  
122  
116  
90  
Hexadecimal  
FAh  
7.2  
0.25  
0.32  
9.6  
EBh  
14.4  
19.2  
38.4  
57.6  
115.2  
128  
DAh  
0.25  
0.32  
CBh  
ABh  
0.32  
9Ah  
0.25  
0.25  
0.06  
0.25  
0.25  
1.45  
7Ah  
74h  
230.4  
460.8  
921.6  
1228.8  
5Ah  
58  
3Ah  
28  
1Ch  
21  
15h  
0.32  
[1] The resulting transfer speed error is less than 1.5 % for all described transfer speeds.  
The selectable transfer speeds shown in Table 10 are calculated according to the  
following equations:  
If BR_T0[2:0] = 0:  
27.12 × 106  
(BR_T0 + 1)  
transfer speed =  
(1)  
(2)  
--------------------------------  
If BR_T0[2:0] > 0:  
27.12 × 106  
-----------------------------------  
(BR_T1 + 33)  
-----------------------------------  
transfer speed =  
2(BR_T 0 1)  
Remark: Transfer speeds above 1228.8 kBd are not supported.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
11 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
8.1.3.3 UART framing  
Table 11. UART framing  
Bit  
Length  
1-bit  
Value  
0
Start  
Data  
Stop  
8 bits  
1-bit  
data  
1
Remark: The LSB for data and address bytes must be sent first. No parity bit is used  
during transmission.  
Read data: To read data using the UART interface, the flow shown in Table 12 must be  
used. The first byte sent defines both the mode and the address.  
Table 12. Read data byte order  
Pin  
Byte 0  
address  
-
Byte 1  
-
RX (pin 24)  
TX (pin 31)  
data 0  
ADDRESS  
RX  
SA  
A0  
A1  
A2  
A3  
A4  
A5  
(1)  
R/W SO  
DATA  
TX  
SA  
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
SO  
MX  
DTRQ  
001aak588  
(1) Reserved.  
Fig 9. UART read data timing diagram  
Write data: To write data to the MFRC522 using the UART interface, the structure shown  
in Table 13 must be used.  
The first byte sent defines both the mode and the address.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
12 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 13. Write data byte order  
Pin  
Byte 0  
Byte 1  
RX (pin 24)  
TX (pin 31)  
address 0  
-
data 0  
address 0  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
13 of 96  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx  
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
ADDRESS  
DATA  
RX  
SA A0 A1 A2 A3 A4 A5  
(1) R/W SO  
SA D0 D1 D2 D3 D4 D5 D6 D7 SO  
ADDRESS  
TX  
SA A0 A1 A2 A3 A4 A5  
(1) R/W SO  
MX  
DTRQ  
001aak589  
(1) Reserved.  
Fig 10. UART write data timing diagram  
Remark: The data byte can be sent directly after the address byte on pin RX.  
Address byte: The address byte has to meet the following format:  
The MSB of the first byte sets the mode used. To read data from the MFRC522, the MSB is set to logic 1. To write data to the  
MFRC522 the MSB is set to logic 0. Bit 6 is reserved for future use, and bits 5 to 0 define the address; see Table 14.  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 14. Address byte 0 register; address MOSI  
7 (MSB)  
6
5
4
3
2
1
0 (LSB)  
1 = read  
0 = write  
reserved  
address  
8.1.4 I2C-bus interface  
An I2C-bus (Inter-IC) interface is supported to enable a low-cost, low pin count serial bus  
interface to the host. The I2C-bus interface is implemented according to  
NXP Semiconductors’ I2C-bus interface specification, rev. 2.1, January 2000. The  
interface can only act in Slave mode. Therefore the MFRC522 does not implement clock  
generation or access arbitration.  
PULL-UP  
NETWORK  
PULL-UP  
NETWORK  
MFRC522  
SDA  
SCL  
MICROCONTROLLER  
I2C  
CONFIGURATION  
WIRING  
EA  
ADR_[5:0]  
001aak590  
Fig 11. I2C-bus interface  
The MFRC522 can act either as a slave receiver or slave transmitter in Standard mode,  
Fast mode and High-speed mode.  
SDA is a bidirectional line connected to a positive supply voltage using a current source or  
a pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. The  
MFRC522 has a 3-state output stage to perform the wired-AND function. Data on the  
I2C-bus can be transferred at data rates of up to 100 kBd in Standard mode, up to  
400 kBd in Fast mode or up to 3.4 Mbit/s in High-speed mode.  
If the I2C-bus interface is selected, spike suppression is activated on lines SCL and SDA  
as defined in the I2C-bus interface specification.  
See Table 155 on page 76 for timing requirements.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
15 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
8.1.4.1 Data validity  
Data on the SDA line must be stable during the HIGH clock period. The HIGH or LOW  
state of the data line must only change when the clock signal on SCL is LOW.  
SDA  
SCL  
data line  
stable;  
data valid  
change  
of data  
allowed  
mbc621  
Fig 12. Bit transfer on the I2C-bus  
8.1.4.2 START and STOP conditions  
To manage the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions  
are defined.  
A START condition is defined with a HIGH-to-LOW transition on the SDA line while  
SCL is HIGH.  
A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while  
SCL is HIGH.  
The I2C-bus master always generates the START and STOP conditions. The bus is busy  
after the START condition. The bus is free again a certain time after the STOP condition.  
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition.  
The START (S) and repeated START (Sr) conditions are functionally identical. Therefore,  
S is used as a generic term to represent both the START (S) and repeated START (Sr)  
conditions.  
SDA  
SCL  
SDA  
SCL  
S
P
START condition  
STOP condition  
mbc622  
Fig 13. START and STOP conditions  
8.1.4.3 Byte format  
Each byte must be followed by an acknowledge bit. Data is transferred with the MSB first;  
see Figure 16. The number of transmitted bytes during one data transfer is unrestricted  
but must meet the read/write cycle format.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
16 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
8.1.4.4 Acknowledge  
An acknowledge must be sent at the end of one data byte. The acknowledge-related clock  
pulse is generated by the master. The transmitter of data, either master or slave, releases  
the SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down the  
SDA line during the acknowledge clock pulse so that it remains stable LOW during the  
HIGH period of this clock pulse.  
The master can then generate either a STOP (P) condition to stop the transfer or a  
repeated START (Sr) condition to start a new transfer.  
A master-receiver indicates the end of data to the slave-transmitter by not generating an  
acknowledge on the last byte that was clocked out by the slave. The slave-transmitter  
releases the data line to allow the master to generate a STOP (P) or repeated START (Sr)  
condition.  
data output  
by transmitter  
not acknowledge  
data output  
by receiver  
acknowledge  
SCL from  
master  
1
2
8
9
S
clock pulse for  
acknowledgement  
START  
condition  
mbc602  
Fig 14. Acknowledge on the I2C-bus  
P
SDA  
Sr  
acknowledgement  
signal from slave  
acknowledgement  
signal from receiver  
MSB  
byte complete,  
interrupt within slave  
clock line held LOW while  
interrupts are serviced  
S
or  
Sr  
Sr  
or  
P
SCL  
1
2
7
8
9
1
2
3 - 8  
9
ACK  
ACK  
START or  
repeated START  
condition  
STOP or  
repeated START  
condition  
msc608  
Fig 15. Data transfer on the I2C-bus  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
17 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
8.1.4.5 7-Bit addressing  
During the I2C-bus address procedure, the first byte after the START condition is used to  
determine which slave will be selected by the master.  
Several address numbers are reserved. During device configuration, the designer must  
ensure that collisions with these reserved addresses cannot occur. Check the I2C-bus  
specification for a complete list of reserved addresses.  
The I2C-bus address specification is dependent on the definition of pin EA. Immediately  
after releasing pin NRSTPD or after a power-on reset, the device defines the I2C-bus  
address according to pin EA.  
If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by  
NXP Semiconductors and set to 0101b for all MFRC522 devices. The remaining 3 bits  
(ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer  
to prevent collisions with other I2C-bus devices.  
If pin EA is set HIGH, ADR_0 to ADR_5 can be completely specified at the external pins  
according to Table 5 on page 8. ADR_6 is always set to logic 0.  
In both modes, the external address coding is latched immediately after releasing the  
reset condition. Further changes at the used pins are not taken into consideration.  
Depending on the external wiring, the I2C-bus address pins can be used for test signal  
outputs.  
MSB  
bit 6  
LSB  
R/W  
bit 5  
bit 4  
bit 3  
bit 2  
bit 1  
bit 0  
slave address  
001aak591  
Fig 16. First byte following the START procedure  
8.1.4.6 Register write access  
To write data from the host controller using the I2C-bus to a specific register in the  
MFRC522 the following frame format must be used.  
The first byte of a frame indicates the device address according to the I2C-bus rules.  
The second byte indicates the register address followed by up to n-data bytes.  
In one frame all data bytes are written to the same register address. This enables fast  
FIFO buffer access. The Read/Write (R/W) bit is set to logic 0.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
18 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
8.1.4.7 Register read access  
To read out data from a specific register address in the MFRC522, the host controller must  
use the following procedure:  
Firstly, a write access to the specific register address must be performed as indicated  
in the frame that follows  
The first byte of a frame indicates the device address according to the I2C-bus rules  
The second byte indicates the register address. No data bytes are added  
The Read/Write bit is 0  
After the write access, read access can start. The host sends the device address of the  
MFRC522. In response, the MFRC522 sends the content of the read access register. In  
one frame all data bytes can be read from the same register address. This enables fast  
FIFO buffer access or register polling.  
The Read/Write (R/W) bit is set to logic 1.  
write cycle  
2
I C-BUS  
SLAVE ADDRESS  
[A7:A0]  
0
(W)  
JOINER REGISTER  
ADDRESS [A5:A0]  
DATA  
[7:0]  
S
A
0
0
A
[0:n]  
A
P
read cycle  
0
2
I C-BUS  
0
(W)  
JOINER REGISTER  
ADDRESS [A5:A0]  
SLAVE ADDRESS  
[A7:A0]  
S
A
0
A
P
optional, if the previous access was on the same register address  
[0:n]  
2
I C-BUS  
1
(R)  
DATA  
[7:0]  
SLAVE ADDRESS  
[A7:A0]  
S
A
[0:n]  
A
A
DATA  
[7:0]  
P
sent by master  
S
P
A
start condition  
stop condition  
acknowledge  
A
not acknowledge  
write cycle  
W
R
sent by slave  
read cycle  
001aak592  
Fig 17. Register read and write access  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
19 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
8.1.4.8 High-speed mode  
In High-speed mode (HS mode), the device can transfer information at data rates of up to  
3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard mode  
(F/S mode) for bidirectional communication in a mixed-speed bus system.  
8.1.4.9 High-speed transfer  
To achieve data rates of up to 3.4 Mbit/s the following improvements have been made to  
I2C-bus operation.  
The inputs of the device in HS mode incorporate spike suppression, a Schmitt trigger  
on the SDA and SCL inputs and different timing constants when compared to  
F/S mode  
The output buffers of the device in HS mode incorporate slope control of the falling  
edges of the SDA and SCL signals with different fall times compared to F/S mode  
8.1.4.10 Serial data transfer format in HS mode  
The HS mode serial data transfer format meets the Standard mode I2C-bus specification.  
HS mode can only start after all of the following conditions (all of which are in F/S mode):  
1. START condition (S)  
2. 8-bit master code (00001XXXb)  
3. Not-acknowledge bit (A)  
When HS mode starts, the active master sends a repeated START condition (Sr) followed  
by a 7-bit slave address with a R/W bit address and receives an acknowledge bit (A) from  
the selected MFRC522.  
Data transfer continues in HS mode after the next repeated START (Sr), only switching  
back to F/S mode after a STOP condition (P). To reduce the overhead of the master code,  
a master links a number of HS mode transfers, separated by repeated START conditions  
(Sr).  
HS mode (current-source for SCL HIGH enabled)  
F/S mode  
F/S mode  
S
MASTER CODE  
A
Sr SLAVE ADDRESS R/W  
A
DATA  
A/A  
P
(n-bytes + A)  
HS mode continues  
SLAVE ADDRESS  
001aak749  
Sr  
Fig 18. I2C-bus HS mode protocol switch  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
20 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
t
1
A
8-bit master code 0000 1xxx  
S
t
H
SDA high  
SCL high  
1
2 to 5  
6
7
8
9
F/S mode  
n + (8-bit data  
+
A/A)  
R/W  
A
7-bit SLA  
Sr  
Sr P  
SDA high  
SCL high  
1
2 to 5  
6
7
8
9
1
2 to 5  
6
7
8
9
If P then  
HS mode  
F/S mode  
If Sr (dotted lines)  
then HS mode  
t
H
t
FS  
= Master current source pull-up  
= Resistor pull-up  
msc618  
Fig 19. I2C-bus HS mode protocol frame  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
21 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
8.1.4.11 Switching between F/S mode and HS mode  
After reset and initialization, the MFRC522 is in Fast mode (which is in effect F/S mode as  
Fast mode is downward-compatible with Standard mode). The connected MFRC522  
recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast  
mode setting to the HS mode setting.  
The following actions are taken:  
1. Adapt the SDA and SCL input filters according to the spike suppression requirement  
in HS mode.  
2. Adapt the slope control of the SDA output stages.  
It is possible for system configurations that do not have other I2C-bus devices involved in  
the communication to switch to HS mode permanently. This is implemented by setting  
Status2Reg register’s I2CForceHS bit to logic 1. In permanent HS mode, the master code  
is not required to be sent. This is not defined in the specification and must only be used  
when no other devices are connected on the bus. In addition, spikes on the I2C-bus lines  
must be avoided because of the reduced spike suppression.  
8.1.4.12 MFRC522 at lower speed modes  
MFRC522 is fully downward-compatible and can be connected to an F/S mode I2C-bus  
system. The device stays in F/S mode and communicates at F/S mode speeds because a  
master code is not transmitted in this configuration.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
22 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
8.2 Analog interface and contactless UART  
8.2.1 General  
The integrated contactless UART supports the external host online with framing and error  
checking of the protocol requirements up to 848 kBd. An external circuit can be connected  
to the communication interface pins MFIN and MFOUT to modulate and demodulate the  
data.  
The contactless UART handles the protocol requirements for the communication protocols  
in cooperation with the host. Protocol handling generates bit and byte-oriented framing. In  
addition, it handles error detection such as parity and CRC, based on the various  
supported contactless communication protocols.  
Remark: The size and tuning of the antenna and the power supply voltage have an  
important impact on the achievable operating distance.  
8.2.2 TX p-driver  
The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an  
envelope signal. It can be used to drive an antenna directly using a few passive  
components for matching and filtering; see Section 15 on page 78. The signal on pins  
TX1 and TX2 can be configured using the TxControlReg register; see Section 9.3.2.5 on  
page 48.  
The modulation index can be set by adjusting the impedance of the drivers. The  
impedance of the p-driver can be configured using registers CWGsPReg and  
ModGsPReg. The impedance of the n-driver can be configured using the GsNReg  
register. The modulation index also depends on the antenna design and tuning.  
The TxModeReg and TxSelReg registers control the data rate and framing during  
transmission and the antenna driver setting to support the different requirements at the  
different modes and transfer speeds.  
Table 15. Register and bit settings controlling the signal on pin TX1  
Bit  
Tx1RFEn Force  
100ASK  
Bit  
Bit  
Bit  
Envelope Pin  
TX1  
GSPMos GSNMos Remarks  
InvTx1RFOn InvTx1RFOff  
0
X[1]  
X[1]  
0
X[1]  
X[1]  
X[1]  
X[1]  
X[1]  
X[1]  
not specified if RF is  
switched off  
1
0
0
1
0
1
0
1
0
1
RF  
RF  
RF  
RF  
0
pMod  
pCW  
pMod  
pCW  
pMod  
nMod  
nCW  
nMod  
nCW  
nMod  
nCW  
100 % ASK: pin TX1  
pulled to logic 0,  
independent of the  
InvTx1RFOff bit  
1
1
X[1]  
X[1]  
RF_n pCW  
[1] X = Do not care.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
23 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 16. Register and bit settings controlling the signal on pin TX2  
Bit  
Tx1RFEn Force  
100ASK  
Bit  
Bit  
Bit  
Bit  
Envelope Pin  
TX2  
GSPMos GSNMos Remarks  
Tx2CW InvTx2RFOn InvTx2RFOff  
0
X[1]  
X[1]  
X[1]  
X[1]  
X[1]  
X[1]  
X[1]  
X[1]  
not specified if  
RF is switched  
off  
1
0
0
0
1
X[1]  
X[1]  
0
RF  
RF  
pMod  
pCW  
nMod  
nCW  
nMod  
nCW  
nCW  
nCW  
-
1
0
RF_n pMod  
RF_n pCW  
1
1
0
0
1
X[1]  
X[1]  
X[1]  
X[1]  
RF  
pCW  
conductance  
always CW for  
the Tx2CW bit  
RF_n pCW  
1
0
1
X[1]  
X[1]  
0
0
pMod  
pCW  
pMod  
nMod  
nCW  
nMod  
nCW  
nCW  
nCW  
100 % ASK: pin  
TX2 pulled  
to logic 0  
(independent of  
the  
InvTx2RFOn/Inv  
Tx2RFOff bits)  
1
RF  
0
0
1
RF_n pCW  
RF pCW  
RF_n pCW  
1
0
1
X[1]  
X[1]  
X[1]  
X[1]  
[1] X = Do not care.  
The following abbreviations have been used in Table 15 and Table 16:  
RF: 13.56 MHz clock derived from 27.12 MHz quartz crystal oscillator divided by 2  
RF_n: inverted 13.56 MHz clock  
GSPMos: conductance, configuration of the PMOS array  
GSNMos: conductance, configuration of the NMOS array  
pCW: PMOS conductance value for continuous wave defined by the CWGsPReg  
register  
pMod: PMOS conductance value for modulation defined by the ModGsPReg register  
nCW: NMOS conductance value for continuous wave defined by the GsNReg  
register’s CWGsN[3:0] bits  
nMod: NMOS conductance value for modulation defined by the GsNReg register’s  
ModGsN[3:0] bits  
X = do not care.  
Remark: If only one driver is switched on, the values for CWGsPReg, ModGsPReg and  
GsNReg registers are used for both drivers.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
24 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
8.2.3 Serial data switch  
Two main blocks are implemented in the MFRC522. The digital block comprises the state  
machines, encoder/decoder logic. The analog block comprises the modulator and  
antenna drivers, the receiver and amplifiers. It is possible for the interface between these  
two blocks to be configured so that the interfacing signals are routed to pins MFIN and  
MFOUT.  
This topology allows the analog block of the MFRC522 to be connected to the digital block  
of another device.  
The serial signal switch is controlled by the TxSelReg and RxSelReg registers.  
Figure 20 shows the serial data switch for p-driver TX1 and TX2.  
DriverSel[1:0]  
3-state  
1
00  
01  
10  
11  
envelope  
INTERNAL  
CODER  
INVERT IF  
InvMod = 1  
to driver TX1 and TX2  
0 = impedance = modulated  
1 = impedance = CW  
INVERT IF  
PolMFin = 0  
MFIN  
001aak593  
Fig 20. Serial data switch for p-driver TX1 and TX2  
8.2.4 MFIN and MFOUT interface support  
The MFRC522 is divided into a digital circuit block and an analog circuit block. The digital  
block contains state machines, encoder and decoder logic and so on. The analog block  
contains the modulator and antenna drivers, receiver and amplifiers. The interface  
between these two blocks can be configured so that the interfacing signals can be routed  
to pins MFIN and MFOUT; see Figure 21 on page 26. This configuration is implemented  
using TxSelReg register’s MFOutSel[3:0] and DriverSel[1:0] bits and RxSelReg register’s  
UARTSel[1:0] bits.  
This topology allows some parts of the analog block to be connected to the digital block of  
another device.  
Switch MFOutSel in the TxSelReg register can be used to measure MIFARE and  
ISO/IEC14443 A related signals. This is especially important during the design-in phase  
or for test purposes as it enables checking of the transmitted and received data.  
The most important use of pins MFIN and MFOUT is found in the active antenna concept.  
An external active antenna circuit can be connected to the MFRC522’s digital block.  
Switch MFOutSel must be configured so that the internal Miller encoded signal is sent to  
pin MFOUT (MFOutSel = 100b). UARTSel[1:0] must be configured to receive a  
Manchester signal with subcarrier from pin MFIN (UARTSel[1:0] = 01).  
It is possible to connect a passive antenna to pins TX1, TX2 and RX (using the  
appropriate filter and matching circuit) and an active antenna to pins MFOUT and MFIN at  
the same time. In this configuration, two RF circuits can be driven (one after another) by a  
single host processor.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
25 of 96  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx  
xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x  
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx  
xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx  
Remark: Pins MFIN and MFOUT have a dedicated supply on pin SVDD with the ground on pin PVSS. If pin MFIN is not  
used it must be connected to either pin SVDD or pin PVSS. If pin SVDD is not used it must be connected to either pin DVDD,  
pin PVDD or any other voltage supply pin.  
MFOUT  
3-state  
LOW  
0
1
2
3
4
5
6
7
3-state  
internal envelope  
envelope from pin MFIN  
HIGH  
0
1
2
3
TX2  
TX1  
TX bit stream  
MILLER  
CODER  
MODULATOR  
DRIVER  
MFOutSel[3:0]  
HIGH  
DRIVER  
Sel[1:0]  
test bus  
internal envelope  
TX serial data stream  
reserved  
DIGITAL MODULE  
ANALOG MODULE  
MFRC522  
RX serial data stream  
MFRC522  
SUBCARRIER  
DEMODULATOR  
0
1
2
3
LOW  
Manchester with subcarrier  
internal modulated  
RX bit stream  
MANCHESTER  
DECODER  
DEMODULATOR  
RX  
UART  
NRZ coding without subcarrier (> 106 kBd)  
Sel[1:0]  
MFIN  
001aak594  
Fig 21. Overview of MFIN and MFOUT signal routing  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
8.2.5 CRC coprocessor  
The following CRC coprocessor parameters can be configured:  
The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on  
the ModeReg register’s CRCPreset[1:0] bits setting  
The CRC polynomial for the 16-bit CRC is fixed to x16 + x12 + x5 + 1  
The CRCResultReg register indicates the result of the CRC calculation. This register  
is split into two 8-bit registers representing the higher and lower bytes.  
The ModeReg register’s MSBFirst bit indicates that data will be loaded with the MSB  
first.  
Table 17. CRC coprocessor parameters  
Parameter  
Value  
CRC register length  
CRC algorithm  
CRC preset value  
16-bit CRC  
algorithm according to ISO/IEC 14443 A and ITU-T  
0000h, 6363h, A671h or FFFFh depending on the setting of the  
ModeReg register’s CRCPreset[1:0] bits  
8.3 FIFO buffer  
An 8 × 64 bit FIFO buffer is used in the MFRC522. It buffers the input and output data  
stream between the host and the MFRC522’s internal state machine. This makes it  
possible to manage data streams up to 64 bytes long without the need to take timing  
constraints into account.  
8.3.1 Accessing the FIFO buffer  
The FIFO buffer input and output data bus is connected to the FIFODataReg register.  
Writing to this register stores one byte in the FIFO buffer and increments the internal FIFO  
buffer write pointer. Reading from this register shows the FIFO buffer contents stored in  
the FIFO buffer read pointer and decrements the FIFO buffer read pointer. The distance  
between the write and read pointer can be obtained by reading the FIFOLevelReg  
register.  
When the microcontroller starts a command, the MFRC522 can, while the command is in  
progress, access the FIFO buffer according to that command. Only one FIFO buffer has  
been implemented which can be used for input and output. The microcontroller must  
ensure that there are not any unintentional FIFO buffer accesses.  
8.3.2 Controlling the FIFO buffer  
The FIFO buffer pointers can be reset by setting FIFOLevelReg register’s FlushBuffer bit  
to logic 1. Consequently, the FIFOLevel[6:0] bits are all set to logic 0 and the ErrorReg  
register’s BufferOvfl bit is cleared. The bytes stored in the FIFO buffer are no longer  
accessible allowing the FIFO buffer to be filled with another 64 bytes.  
8.3.3 FIFO buffer status information  
The host can get the following FIFO buffer status information:  
Number of bytes stored in the FIFO buffer: FIFOLevelReg register’s FIFOLevel[6:0]  
FIFO buffer almost full warning: Status1Reg register’s HiAlert bit  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
27 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
FIFO buffer almost empty warning: Status1Reg register’s LoAlert bit  
FIFO buffer overflow warning: ErrorReg register’s BufferOvfl bit. The BufferOvfl bit can  
only be cleared by setting the FIFOLevelReg register’s FlushBuffer bit.  
The MFRC522 can generate an interrupt signal when:  
ComIEnReg register’s LoAlertIEn bit is set to logic 1. It activates pin IRQ when  
Status1Reg register’s LoAlert bit changes to logic 1.  
ComIEnReg register’s HiAlertIEn bit is set to logic 1. It activates pin IRQ when  
Status1Reg register’s HiAlert bit changes to logic 1.  
If the maximum number of WaterLevel bytes (as set in the WaterLevelReg register) or less  
are stored in the FIFO buffer, the HiAlert bit is set to logic 1. It is generated according to  
Equation 3:  
HiAlert = (64 FIFOLength) ≤ WaterLevel  
(3)  
If the number of WaterLevel bytes (as set in the WaterLevelReg register) or less are stored  
in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to Equation 4:  
LoAlert = FIFOLength WaterLevel  
(4)  
8.4 Interrupt request system  
The MFRC522 indicates certain events by setting the Status1Reg register’s IRq bit and, if  
activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its  
interrupt handling capabilities. This allows the implementation of efficient host software.  
8.4.1 Interrupt sources overview  
Table 18 shows the available interrupt bits, the corresponding source and the condition for  
its activation. The ComIrqReg register’s TimerIRq interrupt bit indicates an interrupt set by  
the timer unit which is set when the timer decrements from 1 to 0.  
The ComIrqReg register’s TxIRq bit indicates that the transmitter has finished. If the state  
changes from sending data to transmitting the end of the frame pattern, the transmitter  
unit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqReg  
register’s CRCIRq bit after processing all the FIFO buffer data which is indicated by  
CRCReady bit = 1.  
The ComIrqReg register’s RxIRq bit indicates an interrupt when the end of the received  
data is detected. The ComIrqReg register’s IdleIRq bit is set if a command finishes and  
the Command[3:0] value in the CommandReg register changes to idle (see Table 149 on  
page 67).  
The ComIrqReg register’s HiAlertIRq bit is set to logic 1 when the Status1Reg register’s  
HiAlert bit is set to logic 1 which means that the FIFO buffer has reached the level  
indicated by the WaterLevel[5:0] bits.  
The ComIrqReg register’s LoAlertIRq bit is set to logic 1 when the Status1Reg register’s  
LoAlert bit is set to logic 1 which means that the FIFO buffer has reached the level  
indicated by the WaterLevel[5:0] bits.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
28 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART  
during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg.  
Table 18. Interrupt sources  
Interrupt flag Interrupt source  
Trigger action  
TimerIRq  
TxIRq  
timer unit  
the timer counts from 1 to 0  
a transmitted data stream ends  
all data from the FIFO buffer has been processed  
a received data stream ends  
command execution finishes  
the FIFO buffer is almost full  
the FIFO buffer is almost empty  
an error is detected  
transmitter  
CRCIRq  
RxIRq  
CRC coprocessor  
receiver  
IdleIRq  
ComIrqReg register  
FIFO buffer  
HiAlertIRq  
LoAlertIRq  
ErrIRq  
FIFO buffer  
contactless UART  
8.5 Timer unit  
The MFRC522A has a timer unit which the external host can use to manage timing tasks.  
The timer unit can be used in one of the following timer/counter configurations:  
Timeout counter  
Watchdog counter  
Stop watch  
Programmable one shot  
Periodical trigger  
The timer unit can be used to measure the time interval between two events or to indicate  
that a specific event occurred after a specific time. The timer can be triggered by events  
explained in the paragraphs below. The timer does not influence any internal events, for  
example, a time-out during data reception does not automatically influence the reception  
process. Furthermore, several timer-related bits can be used to generate an interrupt.  
The timer has an input clock of 6.78 MHz derived from the 27.12 MHz quartz crystal  
oscillator. The timer consists of two stages: prescaler and counter.  
The prescaler (TPrescaler) is a 12-bit counter. The reload values (TReloadVal_Hi[7:0] and  
TReloadVal_Lo[7:0]) for TPrescaler can be set between 0 and 4095 in the TModeReg  
register’s TPrescaler_Hi[3:0] bits and TPrescalerReg register’s TPrescaler_Lo[7:0] bits.  
The reload value for the counter is defined by 16 bits between 0 and 65535 in the  
TReloadReg register.  
The current value of the timer is indicated in the TCounterValReg register.  
When the counter reaches 0, an interrupt is automatically generated, indicated by the  
ComIrqReg register’s TimerIRq bit setting. If enabled, this event can be indicated on  
pin IRQ. The TimerIRq bit can be set and reset by the host. Depending on the  
configuration, the timer will stop at 0 or restart with the value set in the TReloadReg  
register.  
The timer status is indicated by the Status1Reg register’s TRunning bit.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
29 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
The timer can be started manually using the ControlReg register’s TStartNow bit and  
stopped using the ControlReg register’s TStopNow bit.  
The timer can also be activated automatically to meet any dedicated protocol  
requirements, by setting the TModeReg register’s TAuto bit to logic 1.  
The time delay of a timer stage is calculated with Equation 5 adding 1 to the reload values  
below:  
TPrescaler reload value = 4095  
TReloadVal reload value = 65535  
65536  
6.78 MHz  
Maximum time = 4096 ×  
= 39.59 s  
(5)  
------------------------  
Example: To indicate 100 µs, 678 clock cycles must be counted, so the TPrescaler value  
must be set to 677 using register TModeReg bits TPrescaler_Hi[3:0] and TPrescalerReg  
bits TPrescaler_Lo[7:0]. This gives the timer an input clock of 100 µs that enables it to  
count up to 65535 time slots for each 100 µs.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
30 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
8.6 Power reduction modes  
8.6.1 Hard power-down  
Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current  
sinks including the oscillator. All digital input buffers are separated from the input pins and  
clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or  
LOW level.  
8.6.2 Soft power-down mode  
Soft Power-down mode is entered immediately after the CommandReg register’s  
PowerDown bit is set to logic 1. All internal current sinks are switched off, including the  
oscillator buffer. However, the digital input buffers are not separated from the input pins  
and keep their functionality. The digital output pins do not change their state.  
During soft power-down, all register values, the FIFO buffer content and the configuration  
keep their current contents.  
After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft power-down  
mode is exited indicated by the PowerDown bit. Setting it to logic 0 does not immediately  
clear it. It is cleared automatically by the MFRC522 when Soft power-down mode is  
exited.  
Remark: If the internal oscillator is used, you must take into account that it is supplied by  
pin AVDD and it will take a certain time (tosc) until the oscillator is stable and the clock  
cycles can be detected by the internal logic. It is recommended for the serial UART, to first  
send the value 55h to the MFRC522. The oscillator must be stable for further access to  
the registers. To ensure this, perform a read access to address 0 until the MFRC522  
answers to the last read command with the register content of address 0. This indicates  
that the MFRC522 is ready.  
8.6.3 Transmitter power-down mode  
The Transmitter Power-down mode switches off the internal antenna drivers thereby,  
turning off the RF field. Transmitter power-down mode is entered by setting either the  
TxControlReg register’s Tx1RFEn bit or Tx2RFEn bit to logic 0.  
8.7 Oscillator circuit  
MFRC522  
OSCOUT  
OSCIN  
27.12 MHz  
001aak595  
Fig 22. Quartz crystal connection  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
31 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
The clock applied to the MFRC522 provides a time basis for the synchronous system’s  
encoder and decoder. The stability of the clock frequency, therefore, is an important factor  
for correct operation. To obtain optimum performance, clock jitter must be reduced as  
much as possible. This is best achieved using the internal oscillator buffer with the  
recommended circuitry.  
If an external clock source is used, the clock signal must be applied to pin OSCIN. In this  
case, special care must be taken with the clock duty cycle and clock jitter and the clock  
quality must be verified.  
8.8 Reset and oscillator start-up time  
8.8.1 Reset timing requirements  
The reset signal is filtered by a hysteresis circuit and a spike filter before it enters the  
digital circuit. The spike filter rejects signals shorter than 10 ns. In order to perform a  
reset, the signal must be LOW for at least 100 ns.  
8.8.2 Oscillator start-up time  
If the MFRC522 has been set to a Power-down mode or is powered by a VDDX supply, the  
start-up time for the MFRC522 depends on the oscillator used and is shown in Figure 23.  
The time (tstartup) is the start-up time of the crystal oscillator circuit. The crystal oscillator  
start-up time is defined by the crystal.  
The time (td) is the internal delay time of the MFRC522 when the clock signal is stable  
before the MFRC522 can be addressed.  
The delay time is calculated by:  
1024  
27 µs  
td  
=
= 37.74 µs  
(6)  
-------------  
The time (tosc) is the sum of td and tstartup  
.
device activation  
oscillator  
clock stable  
clock ready  
t
startup  
t
d
t
osc  
t
001aak596  
Fig 23. Oscillator start-up time  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
32 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
9. MFRC522 registers  
9.1 Register bit behavior  
Depending on the functionality of a register, the access conditions to the register can vary.  
In principle, bits with same behavior are grouped in common registers. The access  
conditions are described in Table 19.  
Table 19. Behavior of register bits and their designation  
Abbreviation Behavior  
Description  
R/W  
read and write These bits can be written and read by the microcontroller. Since  
they are used only for control purposes, their content is not  
influenced by internal state machines, for example the  
ComIEnReg register can be written and read by the  
microcontroller. It will also be read by internal state machines but  
never changed by them.  
D
R
dynamic  
These bits can be written and read by the microcontroller.  
Nevertheless, they can also be written automatically by internal  
state machines, for example the CommandReg register changes  
its value automatically after the execution of the command.  
read only  
These register bits hold values which are determined by internal  
states only, for example the CRCReady bit cannot be written  
externally but shows internal states.  
W
write only  
-
Reading these register bits always returns zero.  
reserved  
These registers are reserved for future use and must not be  
changed. In case of a write access, it is recommended to always  
write the value “0”.  
RFT  
-
These register bits are reserved for future use or are for  
production tests and must not be changed.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
33 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
9.2 Register overview  
Table 20. MFRC522 register overview  
Address  
(hex)  
Register name  
Function  
Refer to  
Page 0: Command and status  
00h  
01h  
02h  
03h  
04h  
05h  
06h  
Reserved  
reserved for future use  
Table 21 on page 36  
Table 23 on page 36  
Table 25 on page 36  
Table 27 on page 37  
Table 29 on page 37  
Table 31 on page 38  
Table 33 on page 39  
CommandReg  
ComlEnReg  
DivlEnReg  
ComIrqReg  
DivIrqReg  
starts and stops command execution  
enable and disable interrupt request control bits  
enable and disable interrupt request control bits  
interrupt request bits  
interrupt request bits  
ErrorReg  
error bits showing the error status of the last command  
executed  
07h  
08h  
09h  
0Ah  
0Bh  
0Ch  
0Dh  
0Eh  
Status1Reg  
Status2Reg  
FIFODataReg  
FIFOLevelReg  
WaterLevelReg  
ControlReg  
communication status bits  
Table 35 on page 40  
Table 37 on page 41  
Table 39 on page 42  
Table 41 on page 42  
Table 43 on page 42  
Table 45 on page 43  
Table 47 on page 44  
Table 49 on page 44  
receiver and transmitter status bits  
input and output of 64 byte FIFO buffer  
number of bytes stored in the FIFO buffer  
level for FIFO underflow and overflow warning  
miscellaneous control registers  
BitFramingReg  
CollReg  
adjustments for bit-oriented frames  
bit position of the first bit-collision detected on the RF  
interface  
0Fh  
Reserved  
reserved for future use  
Table 51 on page 45  
Page 1: Command  
10h  
11h  
12h  
13h  
14h  
Reserved  
reserved for future use  
Table 53 on page 45  
Table 55 on page 46  
Table 57 on page 46  
Table 59 on page 47  
ModeReg  
defines general modes for transmitting and receiving  
defines transmission data rate and framing  
defines reception data rate and framing  
TxModeReg  
RxModeReg  
TxControlReg  
controls the logical behavior of the antenna driver pins TX1 Table 61 on page 48  
and TX2  
15h  
16h  
17h  
18h  
19h  
1Ah  
1Bh  
1Ch  
1Dh  
1Eh  
1Fh  
TxASKReg  
TxSelReg  
controls the setting of the transmission modulation  
selects the internal sources for the antenna driver  
selects internal receiver settings  
selects thresholds for the bit decoder  
defines demodulator settings  
Table 63 on page 49  
Table 65 on page 49  
Table 67 on page 50  
Table 69 on page 51  
Table 71 on page 51  
Table 73 on page 52  
Table 75 on page 52  
RxSelReg  
RxThresholdReg  
DemodReg  
Reserved  
reserved for future use  
Reserved  
reserved for future use  
MfTxReg  
controls some MIFARE communication transmit parameters Table 77 on page 52  
controls some MIFARE communication receive parameters Table 79 on page 53  
MfRxReg  
Reserved  
reserved for future use  
Table 81 on page 53  
Table 83 on page 53  
SerialSpeedReg  
selects the speed of the serial UART interface  
Page 2: Configuration  
20h  
Reserved  
reserved for future use  
Table 85 on page 54  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
34 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 20. MFRC522 register overview …continued  
Address  
(hex)  
Register name  
Function  
Refer to  
21h  
22h  
23h  
24h  
25h  
26h  
27h  
CRCResultReg  
shows the MSB and LSB values of the CRC calculation  
Table 87 on page 54  
Table 89 on page 54  
Table 91 on page 55  
Table 93 on page 55  
Table 95 on page 55  
Table 97 on page 56  
Reserved  
ModWidthReg  
Reserved  
RFCfgReg  
GsNReg  
reserved for future use  
controls the ModWidth setting  
reserved for future use  
configures the receiver gain  
selects the conductance of the antenna driver pins TX1 and Table 99 on page 56  
TX2 for modulation  
28h  
29h  
CWGsPReg  
ModGsPReg  
defines the conductance of the p-driver output during  
periods of no modulation  
Table 101 on page 57  
defines the conductance of the p-driver output during  
periods of modulation  
Table 103 on page 57  
2Ah  
2Bh  
2Ch  
2Dh  
2Eh  
2Fh  
TModeReg  
defines settings for the internal timer  
defines the 16-bit timer reload value  
shows the 16-bit timer value  
Table 105 on page 57  
Table 107 on page 58  
Table 109 on page 59  
Table 111 on page 59  
Table 113 on page 59  
Table 115 on page 59  
TPrescalerReg  
TReloadReg  
TCounterValReg  
Page 3: Test register  
30h  
31h  
32h  
33h  
34h  
35h  
36h  
37h  
38h  
39h  
3Ah  
3Bh  
Reserved  
reserved for future use  
Table 117 on page 60  
Table 119 on page 60  
Table 121 on page 60  
Table 123 on page 61  
TestSel1Reg  
TestSel2Reg  
TestPinEnReg  
TestPinValueReg  
TestBusReg  
AutoTestReg  
VersionReg  
general test signal configuration  
general test signal configuration and PRBS control  
enables pin output driver on pins D1 to D7  
defines the values for D1 to D7 when it is used as an I/O bus Table 125 on page 61  
shows the status of the internal test bus  
controls the digital self test  
Table 127 on page 62  
Table 129 on page 62  
Table 131 on page 63  
Table 133 on page 63  
Table 135 on page 65  
Table 137 on page 65  
Table 139 on page 65  
shows the software version  
AnalogTestReg  
TestDAC1Reg  
TestDAC2Reg  
TestADCReg  
controls the pins AUX1 and AUX2  
defines the test value for TestDAC1  
defines the test value for TestDAC2  
shows the value of ADC I and Q channels  
reserved for production tests  
3Ch to 3Fh Reserved  
Table 141 to Table 147  
on page 66  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
35 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
9.3 Register descriptions  
9.3.1 Page 0: Command and status  
9.3.1.1 Reserved register 00h  
Functionality is reserved for future use.  
Table 21. Reserved register (address 00h); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
reserved  
-
Table 22. Reserved register bit descriptions  
Bit  
Symbol  
Description  
7 to 0  
-
reserved  
9.3.1.2 CommandReg register  
Starts and stops command execution.  
Table 23. CommandReg register (address 01h); reset value: 20h bit allocation  
Bit  
7
6
5
4
PowerDown  
D
3
2
1
0
Symbol:  
Access:  
reserved  
-
RcvOff  
R/W  
Command[3:0]  
D
Table 24. CommandReg register bit descriptions  
Bit Symbol Value Description  
7 to 6 reserved  
-
reserved for future use  
5
4
RcvOff  
1
1
0
analog part of the receiver is switched off  
Soft power-down mode entered  
PowerDown  
MFRC522 starts the wake up procedure during which this bit is  
read as a logic 1; it is read as a logic 0 when the MFRC522 is  
ready; see Section 8.6.2 on page 31  
Remark: The PowerDown bit cannot be set when the SoftReset  
command is activated  
3 to 0 Command[3:0] -  
activates a command based on the Command value; reading this  
register shows which command is executed; see Section 10.3 on  
page 67  
9.3.1.3 ComIEnReg register  
Control bits to enable and disable the passing of interrupt requests.  
Table 25. ComIEnReg register (address 02h); reset value: 80h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
IRqInv  
R/W  
TxIEn  
R/W  
RxIEn  
R/W  
IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn  
R/W R/W R/W R/W R/W  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
36 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 26. ComIEnReg register bit descriptions  
Bit Symbol Value Description  
7
IRqInv  
1
signal on pin IRQ is inverted with respect to the Status1Reg register’s IRq  
bit  
0
signal on pin IRQ is equal to the IRq bit; in combination with the  
DivIEnReg register’s IRqPushPull bit, the default value of logic 1 ensures  
that the output level on pin IRQ is 3-state  
6
5
TxIEn  
RxIEn  
-
-
allows the transmitter interrupt request (TxIRq bit) to be propagated to pin  
IRQ  
allows the receiver interrupt request (RxIRq bit) to be propagated to pin  
IRQ  
4
3
IdleIEn  
-
-
allows the idle interrupt request (IdleIRq bit) to be propagated to pin IRQ  
HiAlertIEn  
allows the high alert interrupt request (HiAlertIRq bit) to be propagated to  
pin IRQ  
2
LoAlertIEn -  
allows the low alert interrupt request (LoAlertIRq bit) to be propagated to  
pin IRQ  
1
0
ErrIEn  
-
-
allows the error interrupt request (ErrIRq bit) to be propagated to pin IRQ  
TimerIEn  
allows the timer interrupt request (TimerIRq bit) to be propagated to pin  
IRQ  
9.3.1.4 DivIEnReg register  
Control bits to enable and disable the passing of interrupt requests.  
Table 27. DivIEnReg register (address 03h); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
IRQPushPull  
R/W  
reserved  
-
MfinActIEn  
R/W  
reserved  
-
CRCIEn  
R/W  
reserved  
-
Table 28. DivIEnReg register bit descriptions  
Bit  
Symbol  
Value Description  
7
IRQPushPull  
1
0
-
pin IRQ is a standard CMOS output pin  
pin IRQ is an open-drain output pin  
reserved for future use  
6 to 5 reserved  
4
MfinActIEn  
-
allows the MFIN active interrupt request to be propagated to  
pin IRQ  
3
2
reserved  
CRCIEn  
-
-
reserved for future use  
allows the CRC interrupt request, indicated by the DivIrqReg  
register’s CRCIRq bit, to be propagated to pin IRQ  
1 to 0 reserved  
-
reserved for future use  
9.3.1.5 ComIrqReg register  
Interrupt request bits.  
Table 29. ComIrqReg register (address 04h); reset value: 14h bit allocation  
Bit  
7
6
5
4
3
HiAlertIRq  
D
2
LoAlertIRq  
D
1
0
Symbol  
Access  
Set1 TxIRq RxIRq IdleIRq  
ErrIRq TimerIRq  
W
D
D
D
D
D
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
37 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 30. ComIrqReg register bit descriptions  
All bits in the ComIrqReg register are cleared by software.  
Bit Symbol Value Description  
7
Set1  
1
0
1
1
indicates that the marked bits in the ComIrqReg register are set  
indicates that the marked bits in the ComIrqReg register are cleared  
set immediately after the last bit of the transmitted data was sent out  
receiver has detected the end of a valid data stream  
6
5
TxIRq  
RxIRq  
if the RxModeReg register’s RxNoErr bit is set to logic 1, the RxIRq bit is  
only set to logic 1 when data bytes are available in the FIFO  
4
IdleIRq  
1
If a command terminates, for example, when the CommandReg changes  
its value from any command to the Idle command (see Table 149 on  
page 67)  
if an unknown command is started, the CommandReg register  
Command[3:0] value changes to the idle state and the IdleIRq bit is set  
The microcontroller starting the Idle command does not set the IdleIRq  
bit  
3
2
HiAlertIRq  
LoAlertIRq  
1
1
the Status1Reg register’s HiAlert bit is set  
in opposition to the HiAlert bit, the HiAlertIRq bit stores this event and  
can only be reset as indicated by the Set1 bit in this register  
Status1Reg register’s LoAlert bit is set  
in opposition to the LoAlert bit, the LoAlertIRq bit stores this event and  
can only be reset as indicated by the Set1 bit in this register  
1
0
ErrIRq  
1
1
any error bit in the ErrorReg register is set  
TimerIRq  
the timer decrements the timer value in register TCounterValReg to zero  
9.3.1.6 DivIrqReg register  
Interrupt request bits.  
Table 31. DivIrqReg register (address 05h); reset value: x0h bit allocation  
Bit  
7
Set2  
W
6
5
4
3
2
1
0
Symbol  
Access  
reserved  
MfinActIRq reserved CRCIRq  
reserved  
-
-
D
-
D
Table 32. DivIrqReg register bit descriptions  
All bits in the DivIrqReg register are cleared by software.  
Bit  
Symbol  
Value Description  
7
Set2  
1
0
-
indicates that the marked bits in the DivIrqReg register are set  
indicates that the marked bits in the DivIrqReg register are cleared  
6 to 5 reserved  
reserved for future use  
MFIN is active  
4
MfinActIRq 1  
this interrupt is set when either a rising or falling signal edge is  
detected  
3
2
reserved  
CRCIRq  
-
reserved for future use  
1
-
the CalcCRC command is active and all data is processed  
reserved for future use  
1 to 0 reserved  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
38 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
9.3.1.7 ErrorReg register  
Error bit register showing the error status of the last command executed.  
Table 33. ErrorReg register (address 06h); reset value: 00h bit allocation  
Bit  
Symbol WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr  
Access  
7
6
5
4
3
2
1
0
R
R
-
R
R
R
R
R
Table 34: ErrorReg register bit descriptions  
Bit Symbol Value Description  
7
WrErr  
1
data is written into the FIFO buffer by the host during the MFAuthent  
command or if data is written into the FIFO buffer by the host during the  
time between sending the last bit on the RF interface and receiving the  
last bit on the RF interface  
6
TempErr[1]  
1
internal temperature sensor detects overheating, in which case the  
antenna drivers are automatically switched off  
5
4
reserved  
-
reserved for future use  
BufferOvfl  
1
the host or a MFRC522’s internal state machine (e.g. receiver) tries to  
write data to the FIFO buffer even though it is already full  
3
CollErr  
1
a bit-collision is detected  
cleared automatically at receiver start-up phase  
only valid during the bitwise anticollision at 106 kBd  
always set to logic 0 during communication protocols at 212 kBd,  
424 kBd and 848 kBd  
2
1
CRCErr  
1
1
the RxModeReg register’s RxCRCEn bit is set and the CRC calculation  
fails  
automatically cleared to logic 0 during receiver start-up phase  
parity check failed  
ParityErr  
automatically cleared during receiver start-up phase  
only valid for ISO/IEC 14443 A/MIFARE communication at 106 kBd  
set to logic 1 if the SOF is incorrect  
0
ProtocolErr  
1
automatically cleared during receiver start-up phase  
bit is only valid for 106 kBd  
during the MFAuthent command, the ProtocolErr bit is set to logic 1 if the  
number of bytes received in one data stream is incorrect  
[1] Command execution clears all error bits except the TempErr bit. Cannot be set by software.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
39 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
9.3.1.8 Status1Reg register  
Contains status bits of the CRC, interrupt and FIFO buffer.  
Table 35. Status1Reg register (address 07h); reset value: 21h bit allocation  
Bit  
Symbol reserved CRCOk CRCReady  
Access  
7
6
5
4
IRq  
R
3
2
1
0
TRunning reserved HiAlert LoAlert  
-
R
R
R
-
R
R
Table 36. Status1Reg register bit descriptions  
Bit Symbol Value Description  
7
6
reserved  
CRCOk  
-
reserved for future use  
the CRC result is zero  
1
for data transmission and reception, the CRCOk bit is undefined: use the  
ErrorReg register’s CRCErr bit  
indicates the status of the CRC coprocessor, during calculation the  
value changes to logic 0, when the calculation is done correctly the  
value changes to logic 1  
5
CRCReady 1  
the CRC calculation has finished  
only valid for the CRC coprocessor calculation using the CalcCRC  
command  
4
3
IRq  
-
indicates if any interrupt source requests attention with respect to the  
setting of the interrupt enable bits: see the ComIEnReg and DivIEnReg  
registers  
TRunning  
1
MFRC522’s timer unit is running, i.e. the timer will decrement the  
TCounterValReg register with the next timer clock  
Remark: in gated mode, the TRunning bit is set to logic 1 when the  
timer is enabled by TModeReg register’s TGated[1:0] bits; this bit is not  
influenced by the gated signal  
2
1
reserved  
HiAlert  
-
reserved for future use  
1
the number of bytes stored in the FIFO buffer corresponds to equation:  
HiAlert = (64 FIFOLength) ≤ WaterLevel  
example:  
FIFO length = 60, WaterLevel = 4 HiAlert = 1  
FIFO length = 59, WaterLevel = 4 HiAlert = 0  
0
LoAlert  
1
the number of bytes stored in the FIFO buffer corresponds to equation:  
LoAlert = FIFOLength WaterLevel  
example:  
FIFO length = 4, WaterLevel = 4 LoAlert = 1  
FIFO length = 5, WaterLevel = 4 LoAlert = 0  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
40 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
9.3.1.9 Status2Reg register  
Contains status bits of the receiver, transmitter and data mode detector.  
Table 37. Status2Reg register (address 08h); reset value: 00h bit allocation  
Bit  
Symbol TempSensClear I2CForceHS  
Access R/W R/W  
7
6
5
4
3
2
1
0
reserved  
-
MFCrypto1On  
D
ModemState[2:0]  
R
Table 38. Status2Reg register bit descriptions  
Bit  
Symbol  
Value Description  
7
TempSensClear  
1
clears the temperature error if the temperature is below the  
alarm limit of 125 °C  
6
I2CForceHS  
I2C-bus input filter settings:  
1
the I2C-bus input filter is set to the High-speed mode  
independent of the I2C-bus protocol  
0
-
the I2C-bus input filter is set to the I2C-bus protocol used  
5 to 4 reserved  
reserved  
3
MFCrypto1On  
-
indicates that the MIFARE Crypto1 unit is switched on and  
therefore all data communication with the card is encrypted  
can only be set to logic 1 by a successful execution of the  
MFAuthent command  
only valid in Read/Write mode for MIFARE standard cards  
this bit is cleared by software  
2 to 0 ModemState[2:0]  
-
shows the state of the transmitter and receiver state  
machines:  
000  
001  
010  
idle  
wait for the BitFramingReg register’s StartSend bit  
TxWait: wait until RF field is present if the TModeReg  
register’s TxWaitRF bit is set to logic 1  
the minimum time for TxWait is defined by the TxWaitReg  
register  
011  
100  
transmitting  
RxWait: wait until RF field is present if the TModeReg  
register’s TxWaitRF bit is set to logic 1  
the minimum time for RxWait is defined by the  
RxWaitReg register  
101  
110  
wait for data  
receiving  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
41 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
9.3.1.10 FIFODataReg register  
Input and output of 64 byte FIFO buffer.  
Table 39. FIFODataReg register (address 09h); reset value: xxh bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
FIFOData[7:0]  
D
Table 40. FIFODataReg register bit descriptions  
Bit  
Symbol  
Description  
7 to 0  
FIFOData[7:0] data input and output port for the internal 64-byte FIFO buffer  
FIFO buffer acts as parallel in/parallel out converter for all serial data  
stream inputs and outputs  
9.3.1.11 FIFOLevelReg register  
Indicates the number of bytes stored in the FIFO.  
Table 41. FIFOLevelReg register (address 0Ah); reset value: 00h bit allocation  
Bit  
Symbol FlushBuffer  
Access  
7
6
5
4
3
2
1
0
FIFOLevel[6:0]  
R
W
Table 42. FIFOLevelReg register bit descriptions  
Bit  
Symbol  
Value Description  
7
FlushBuffer 1  
immediately clears the internal FIFO buffer’s read and write pointer  
and ErrorReg register’s BufferOvfl bit  
reading this bit always returns 0  
6 to 0 FIFOLevel  
[6:0]  
-
indicates the number of bytes stored in the FIFO buffer  
writing to the FIFODataReg register increments and reading  
decrements the FIFOLevel value  
9.3.1.12 WaterLevelReg register  
Defines the level for FIFO under- and overflow warning.  
Table 43. WaterLevelReg register (address 0Bh); reset value: 08h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
reserved  
-
WaterLevel[5:0]  
R/W  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
42 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 44. WaterLevelReg register bit descriptions  
Bit  
Symbol  
Description  
7 to 6  
5 to 0  
reserved  
reserved for future use  
WaterLevel  
[5:0]  
defines a warning level to indicate a FIFO buffer overflow or underflow:  
Status1Reg register’s HiAlert bit is set to logic 1 if the remaining  
number of bytes in the FIFO buffer space is equal to, or less than the  
defined number of WaterLevel bytes  
Status1Reg register’s LoAlert bit is set to logic 1 if equal to, or less  
than the WaterLevel bytes in the FIFO buffer  
Remark: to calculate values for HiAlert and LoAlert see  
Section 9.3.1.8 on page 40.  
9.3.1.13 ControlReg register  
Miscellaneous control bits.  
Table 45. ControlReg register (address 0Ch); reset value: 10h bit allocation  
Bit  
Symbol TStopNow TStartNow  
Access  
7
6
5
4
3
2
1
0
reserved  
-
RxLastBits[2:0]  
R
W
W
Table 46. ControlReg register bit descriptions  
Bit  
Symbol  
Value Description  
7
TStopNow  
1
timer stops immediately  
reading this bit always returns it to 0  
timer starts immediately  
6
TStartNow  
1
reading this bit always returns it to 0  
reserved for future use  
5 to 3 reserved  
-
-
2 to 0 RxLastBits[2:0]  
indicates the number of valid bits in the last received byte  
if this value is zero, the whole byte is valid  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
43 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
9.3.1.14 BitFramingReg register  
Adjustments for bit-oriented frames.  
Table 47. BitFramingReg register (address 0Dh); reset value: 00h bit allocation  
Bit  
Symbol StartSend  
Access  
7
6
5
4
3
2
1
0
RxAlign[2:0]  
R/W  
reserved  
-
TxLastBits[2:0]  
R/W  
W
Table 48. BitFramingReg register bit descriptions  
Bit  
Symbol  
Value Description  
7
StartSend  
1
starts the transmission of data  
only valid in combination with the Transceive command  
6 to 4  
RxAlign[2:0]  
used for reception of bit-oriented frames: defines the bit  
position for the first bit received to be stored in the FIFO buffer  
example:  
0
1
7
LSB of the received bit is stored at bit position 0, the second  
received bit is stored at bit position 1  
LSB of the received bit is stored at bit position 1, the second  
received bit is stored at bit position 2  
LSB of the received bit is stored at bit position 7, the second  
received bit is stored in the next byte that follows at bit  
position 0  
These bits are only to be used for bitwise anticollision at  
106 kBd, for all other modes they are set to 0  
3
reserved  
-
-
reserved for future use  
2 to 0  
TxLastBits[2:0]  
used for transmission of bit oriented frames: defines the  
number of bits of the last byte that will be transmitted  
000b indicates that all bits of the last byte will be transmitted  
9.3.1.15 CollReg register  
Defines the first bit-collision detected on the RF interface.  
Table 49. CollReg register (address 0Eh); reset value: xxh bit allocation  
Bit  
Symbol ValuesAfterColl reserved CollPosNotValid  
Access R/W  
7
6
5
4
3
2
CollPos[4:0]  
R
1
0
-
R
Table 50. CollReg register bit descriptions  
Bit  
Symbol  
Value Description  
7
ValuesAfterColl  
0
all received bits will be cleared after a collision  
only used during bitwise anticollision at 106 kBd,  
otherwise it is set to logic 1  
6
5
reserved  
-
reserved for future use  
CollPosNotValid  
1
no collision detected or the position of the collision is  
out of the range of CollPos[4:0]  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
44 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 50. CollReg register bit descriptions …continued  
Bit Symbol Value Description  
4 to 0 CollPos[4:0]  
-
shows the bit position of the first detected collision in a  
received frame  
only data bits are interpreted  
example:  
00h  
01h  
08h  
indicates a bit-collision in the 32nd bit  
indicates a bit-collision in the 1st bit  
indicates a bit-collision in the 8th bit  
These bits will only be interpreted if the  
CollPosNotValid bit is set to logic 0  
9.3.1.16 Reserved register 0Fh  
Functionality is reserved for future use.  
Table 51. Reserved register (address 0Fh); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
reserved  
-
Table 52. Reserved register bit descriptions  
Bit  
Symbol  
Description  
reserved for future use  
7 to 0  
reserved  
9.3.2 Page 1: Communication  
9.3.2.1 Reserved register 10h  
Functionality is reserved for future use.  
Table 53. Reserved register (address 10h); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
reserved  
-
Table 54. Reserved register bit descriptions  
Bit  
Symbol  
Description  
reserved for future use  
7 to 0  
reserved  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
45 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
9.3.2.2 ModeReg register  
Defines general mode settings for transmitting and receiving.  
Table 55. ModeReg register (address 11h); reset value: 3Fh bit allocation  
Bit  
Symbol MSBFirst reserved TxWaitRF reserved PolMFin reserved  
Access R/W R/W R/W  
7
6
5
4
3
2
1
0
CRCPreset[1:0]  
R/W  
-
-
-
Table 56. ModeReg register bit descriptions  
Bit  
Symbol  
Value Description  
7
MSBFirst  
1
CRC coprocessor calculates the CRC with MSB first  
in the CRCResultReg register the values for the  
CRCResultMSB[7:0] bits and the CRCResultLSB[7:0] bits are bit  
reversed  
Remark: during RF communication this bit is ignored  
reserved for future use  
6
5
4
3
reserved  
TxWaitRF  
reserved  
PolMFin  
-
1
-
transmitter can only be started if an RF field is generated  
reserved for future use  
defines the polarity of pin MFIN  
Remark: the internal envelope signal is encoded active LOW,  
changing this bit generates a MFinActIRq event  
1
0
-
polarity of pin MFIN is active HIGH  
polarity of pin MFIN is active LOW  
reserved for future use  
2
reserved  
1 to 0 CRCPreset  
[1:0]  
defines the preset value for the CRC coprocessor for the CalcCRC  
command  
Remark: during any communication, the preset values are  
selected automatically according to the definition of bits in the  
RxModeReg and TxModeReg registers  
00  
01  
10  
11  
0000h  
6363h  
A671h  
FFFFh  
9.3.2.3 TxModeReg register  
Defines the data rate during transmission.  
Table 57. TxModeReg register (address 12h); reset value: 00h bit allocation  
Bit  
Symbol TxCRCEn  
Access R/W  
7
6
5
TxSpeed[2:0]  
D
4
3
2
1
0
InvMod  
R/W  
reserved  
-
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
46 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 58. TxModeReg register bit descriptions  
Bit  
Symbol  
Value  
Description  
7
TxCRCEn  
1
enables CRC generation during data transmission  
Remark: can only be set to logic 0 at 106 kBd  
defines the bit rate during data transmission  
6 to 4  
TxSpeed[2:0]  
the MFRC522 handles transfer speeds up to  
848 kBd  
000  
001  
010  
011  
100  
101  
110  
111  
1
106 kBd  
212 kBd  
424 kBd  
848 kBd  
reserved  
reserved  
reserved  
reserved  
3
InvMod  
modulation of transmitted data is inverted  
reserved for future use  
2 to 0  
reserved  
-
9.3.2.4 RxModeReg register  
Defines the data rate during reception.  
Table 59. RxModeReg register (address 13h); reset value: 00h bit allocation  
Bit  
Symbol RxCRCEn  
Access R/W  
7
6
5
RxSpeed[2:0]  
D
4
3
2
1
0
RxNoErr RxMultiple  
R/W R/W  
reserved  
-
Table 60. RxModeReg register bit descriptions  
Bit  
Symbol  
Value Description  
7
RxCRCEn  
1
enables the CRC calculation during reception  
Remark: can only be set to logic 0 at 106 kBd  
defines the bit rate while receiving data  
6 to 4 RxSpeed[2:0]  
the MFRC522 handles transfer speeds up to 848 kBd  
000  
001  
010  
011  
100  
101  
110  
111  
1
106 kBd  
212 kBd  
424 kBd  
848 kBd  
reserved  
reserved  
reserved  
reserved  
3
RxNoErr  
an invalid received data stream (less than 4 bits received) will  
be ignored and the receiver remains active  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
47 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 60. RxModeReg register bit descriptions …continued  
Bit  
Symbol  
Value Description  
2
RxMultiple  
0
1
receiver is deactivated after receiving a data frame  
able to receive more than one data frame  
only valid for data rates above 106 kBd in order to handle the  
polling command  
after setting this bit the Receive and Transceive commands will  
not terminate automatically. Multiple reception can only be  
deactivated by writing any command (except the Receive  
command) to the CommandReg register, or by the host clearing  
the bit  
if set to logic 1, an error byte is added to the FIFO buffer at the  
end of a received data stream which is a copy of the ErrorReg  
register value  
1 to 0 reserved  
-
reserved for future use  
9.3.2.5 TxControlReg register  
Controls the logical behavior of the antenna driver pins TX1 and TX2.  
Table 61. TxControlReg register (address 14h); reset value: 80h bit allocation  
Bit  
Symbol InvTx2RF InvTx1RF InvTx2RF InvTx1RF Tx2CW reserved Tx2RFEn Tx1RFEn  
7
6
5
4
3
2
1
0
On  
On  
Off  
Off  
Access  
R/W  
R/W  
R/W  
R/W  
R/W  
-
R/W  
R/W  
Table 62. TxControlReg register bit descriptions  
Bit Symbol Value Description  
InvTx2RFOn 1  
7
6
5
4
3
output signal on pin TX2 inverted when driver TX2 is enabled  
output signal on pin TX1 inverted when driver TX1 is enabled  
output signal on pin TX2 inverted when driver TX2 is disabled  
output signal on pin TX1 inverted when driver TX1 is disabled  
InvTx1RFOn 1  
InvTx2RFOff 1  
InvTx1RFOff 1  
Tx2CW  
1
output signal on pin TX2 continuously delivers the unmodulated  
13.56 MHz energy carrier  
0
-
Tx2CW bit is enabled to modulate the 13.56 MHz energy carrier  
reserved for future use  
2
1
reserved  
Tx2RFEn  
1
output signal on pin TX2 delivers the 13.56 MHz energy carrier  
modulated by the transmission data  
0
Tx1RFEn  
1
output signal on pin TX1 delivers the 13.56 MHz energy carrier  
modulated by the transmission data  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
48 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
9.3.2.6 TxASKReg register  
Controls transmit modulation settings.  
Table 63. TxASKReg register (address 15h); reset value: 00h bit allocation  
Bit  
Symbol reserved Force100ASK  
Access R/W  
7
6
5
4
3
2
1
0
reserved  
-
-
Table 64. TxASKReg register bit descriptions  
Bit  
7
Symbol  
Value Description  
reserved for future use  
reserved  
-
6
Force100ASK 1  
forces a 100 % ASK modulation independent of the ModGsPReg  
register setting  
5 to 0 reserved  
-
reserved for future use  
9.3.2.7 TxSelReg register  
Selects the internal sources for the analog module.  
Table 65. TxSelReg register (address 16h); reset value: 10h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol:  
Access:  
reserved  
-
DriverSel[1:0]  
R/W  
MFOutSel[3:0]  
R/W  
Table 66. TxSelReg register bit descriptions  
Bit  
Symbol  
Value  
Description  
7 to 6 reserved  
-
reserved for future use  
5 to 4 DriverSel  
[1:0]  
-
selects the input of drivers TX1 and TX2  
00  
3-state; in soft power-down the drivers are only in 3-state  
mode if the DriverSel[1:0] value is set to 3-state mode  
01  
modulation signal (envelope) from the internal encoder, Miller  
pulse encoded  
10  
11  
modulation signal (envelope) from pin MIFIN  
HIGH; the HIGH level depends on the setting of bits  
InvTx1RFOn/InvTx1RFOff and InvTx2RFOn/InvTx2RFOff  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
49 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 66. TxSelReg register bit descriptions …continued  
Bit  
Symbol  
Value  
Description  
3 to 0 MFOutSel  
[3:0]  
selects the input for pin MFOUT  
0000  
0001  
0010  
0011  
3-state  
LOW  
HIGH  
test bus signal as defined by the TestSel1Reg register’s  
TstBusBitSel[2:0] value  
0100  
0101  
modulation signal (envelope) from the internal encoder, Miller  
pulse encoded  
serial data stream to be transmitted, data stream before Miller  
encoder  
0110  
0111  
reserved  
serial data stream received, data stream after Manchester  
decoder  
1000 to  
1111  
reserved  
9.3.2.8 RxSelReg register  
Selects internal receiver settings.  
Table 67. RxSelReg register (address 17h); reset value: 84h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
UARTSel[1:0]  
R/W  
RxWait[5:0]  
R/W  
Table 68. RxSelReg register bit descriptions  
Bit  
Symbol Value Description  
7 to 6 UARTSel  
[1:0]  
selects the input of the contactless UART  
constant LOW  
00  
01  
10  
11  
Manchester with subcarrier from pin MFIN  
modulated signal from the internal analog module, default  
NRZ coding without subcarrier from pin MFIN which is only valid  
for transfer speeds above 106 kBd  
5 to 0 RxWait  
[5:0]  
-
after data transmission the activation of the receiver is delayed for  
RxWait bit-clocks, during this ‘frame guard time’ any signal on pin RX  
is ignored  
this parameter is ignored by the Receive command  
all other commands, such as Transceive, MFAuthent use this  
parameter  
the counter starts immediately after the external RF field is switched  
on  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
50 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
9.3.2.9 RxThresholdReg register  
Selects thresholds for the bit decoder.  
Table 69. RxThresholdReg register (address 18h); reset value: 84h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
MinLevel[3:0]  
R/W  
reserved  
-
CollLevel[2:0]  
R/W  
Table 70. RxThresholdReg register bit descriptions  
Bit  
Symbol  
Description  
7 to 4  
MinLevel  
[3:0]  
defines the minimum signal strength at the decoder input that will be  
accepted  
if the signal strength is below this level it is not evaluated  
reserved for future use  
3
reserved  
2 to 0  
CollLevel  
[2:0]  
defines the minimum signal strength at the decoder input that must be  
reached by the weaker half-bit of the Manchester encoded signal to  
generate a bit-collision relative to the amplitude of the stronger half-bit  
9.3.2.10 DemodReg register  
Defines demodulator settings.  
Table 71. DemodReg register (address 19h); reset value: 4Dh bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
AddIQ[1:0]  
R/W  
FixIQ  
R/W  
reserved  
-
TauRcv[1:0]  
R/W  
TauSync[1:0]  
R/W  
Table 72. DemodReg register bit descriptions  
Bit  
Symbol Value Description  
7 to 6 AddIQ  
[1:0]  
-
defines the use of I and Q channel during reception  
Remark: the FixIQ bit must be set to logic 0 to enable the following  
settings:  
00  
01  
selects the stronger channel  
selects the stronger channel and freezes the selected channel  
during communication  
10  
11  
1
reserved  
reserved  
5
4
FixIQ  
if AddIQ[1:0] are set to X0b, the reception is fixed to I channel  
if AddIQ[1:0] are set to X1b, the reception is fixed to Q channel  
reserved for future use  
reserved  
-
-
3 to 2 TauRcv  
[1:0]  
changes the time-constant of the internal PLL during data reception  
Remark: if set to 00b the PLL is frozen during data reception  
changes the time constant of the internal PLL during burst  
1 to 0 TauSync  
[1:0]  
-
9.3.2.11 Reserved register 1Ah  
Functionality is reserved for future use.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
51 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 73. Reserved register (address 1Ah); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
1
0
0
0
Symbol  
Access  
reserved  
-
Table 74. Reserved register bit descriptions  
Bit  
Symbol  
Description  
reserved for future use  
7 to 0  
reserved  
9.3.2.12 Reserved register 1Bh  
Functionality is reserved for future use.  
Table 75. Reserved register (address 1Bh); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
1
Symbol  
Access  
reserved  
-
Table 76. Reserved register bit descriptions  
Bit  
Symbol  
Description  
reserved for future use  
7 to 0  
reserved  
9.3.2.13 MfTxReg register  
Controls some MIFARE communication transmit parameters.  
Table 77. MfTxReg register (address 1Ch); reset value: 62h bit allocation  
Bit  
7
6
5
4
3
2
1
Symbol  
Access  
reserved  
-
TxWait[1:0]  
R/W  
Table 78. MfTxReg register bit descriptions  
Bit  
Symbol  
reserved  
TxWait  
Description  
reserved for future use  
defines the additional response time  
7 bits are added to the value of the register bit by default  
7 to 2  
1 to 0  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
52 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
9.3.2.14 MfRxReg register  
Table 79. MfRxReg register (address 1Dh); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
reserved  
-
ParityDisable  
R/W  
reserved  
-
Table 80. MfRxReg register bit descriptions  
Bit Symbol Value Description  
7 to 5 reserved reserved for future use  
ParityDisable 1  
-
4
generation of the parity bit for transmission and the parity check for  
receiving is switched off  
the received parity bit is handled like a data bit  
reserved for future use  
3 to 0 reserved  
-
9.3.2.15 Reserved register 1Eh  
Functionality is reserved for future use.  
Table 81. Reserved register (address 1Eh); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
reserved  
-
Table 82. Reserved register bit descriptions  
Bit  
Symbol  
Description  
reserved for future use  
7 to 0  
reserved  
9.3.2.16 SerialSpeedReg register  
Selects the speed of the serial UART interface.  
Table 83. SerialSpeedReg register (address 1Fh); reset value: EBh bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
BR_T0[2:0]  
R/W  
BR_T1[4:0]  
R/W  
Table 84. SerialSpeedReg register bit descriptions  
Bit  
Symbol  
Description  
7 to 5  
BR_T0[2:0]  
factor BR_T0 adjusts the transfer speed: for description, see  
Section 8.1.3.2 on page 11  
4 to 0  
BR_T1[4:0]  
factor BR_T1 adjusts the transfer speed: for description, see  
Section 8.1.3.2 on page 11  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
53 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
9.3.3 Page 2: Configuration  
9.3.3.1 Reserved register 20h  
Functionality is reserved for future use.  
Table 85. Reserved register (address 20h); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
-
reserved  
Table 86. Reserved register bit descriptions  
Bit  
Symbol  
Description  
reserved for future use  
7 to 0  
reserved  
9.3.3.2 CRCResultReg registers  
Shows the MSB and LSB values of the CRC calculation.  
Remark: The CRC is split into two 8-bit registers.  
Table 87. CRCResultReg (higher bits) register (address 21h); reset value: FFh bit  
allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
CRCResultMSB[7:0]  
R
Table 88. CRCResultReg register higher bit descriptions  
Bit  
Symbol  
Description  
7 to 0  
CRCResultMSB shows the value of the CRCResultReg register’s most significant  
[7:0]  
byte  
only valid if Status1Reg register’s CRCReady bit is set to logic 1  
Table 89. CRCResultReg (lower bits) register (address 22h); reset value: FFh bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
CRCResultLSB[7:0]  
R
Table 90. CRCResultReg register lower bit descriptions  
Bit  
Symbol  
Description  
7 to 0  
CRCResultLSB shows the value of the least significant byte of the CRCResultReg  
[7:0]  
register  
only valid if Status1Reg register’s CRCReady bit is set to logic 1  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
54 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
9.3.3.3 Reserved register 23h  
Functionality is reserved for future use.  
Table 91. Reserved register (address 23h); reset value: 88h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
reserved  
-
Table 92. Reserved register bit descriptions  
Bit  
Symbol  
Description  
reserved for future use  
7 to 0  
reserved  
9.3.3.4 ModWidthReg register  
Sets the modulation width.  
Table 93. ModWidthReg register (address 24h); reset value: 26h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
ModWidth[7:0]  
R/W  
Table 94. ModWidthReg register bit descriptions  
Bit  
Symbol  
ModWidth[7:0] defines the width of the Miller modulation as multiples of the carrier  
frequency (ModWidth + 1 / fclk  
the maximum value is half the bit period  
Description  
7 to 0  
)
9.3.3.5 Reserved register 25h  
Functionality is reserved for future use.  
Table 95. Reserved register (address 25h); reset value: 87h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
reserved  
-
Table 96. Reserved register bit descriptions  
Bit  
Symbol  
Description  
7 to 0  
reserved  
reserved for future use  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
55 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
9.3.3.6 RFCfgReg register  
Configures the receiver gain.  
Table 97. RFCfgReg register (address 26h); reset value: 48h bit allocation  
Bit  
Symbol reserved  
Access  
7
6
5
4
3
2
1
0
RxGain[2:0]  
R/W  
reserved  
-
-
Table 98. RFCfgReg register bit descriptions  
Bit  
7
Symbol  
Value  
Description  
reserved  
-
reserved for future use  
6 to 4  
RxGain  
[2:0]  
defines the receiver’s signal voltage gain factor:  
000  
001  
010  
011  
100  
101  
110  
111  
-
18 dB  
23 dB  
18 dB  
23 dB  
33 dB  
38 dB  
43 dB  
48 dB  
3 to 0  
reserved  
reserved for future use  
9.3.3.7 GsNReg register  
Defines the conductance of the antenna driver pins TX1 and TX2 for the n-driver when the  
driver is switched on.  
Table 99. GsNReg register (address 27h); reset value: 88h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
CWGsN[3:0]  
R/W  
ModGsN[3:0]  
R/W  
Table 100. GsNReg register bit descriptions  
Bit  
Symbol  
Description  
7 to 4  
CWGsN  
[3:0]  
defines the conductance of the output n-driver during periods without  
modulation which can be used to regulate the output power and  
subsequently current consumption and operating distance  
Remark: the conductance value is binary-weighted  
during soft Power-down mode the highest bit is forced to logic 1  
value is only used if driver TX1 or TX2 is switched on  
3 to 0  
ModGsN  
[3:0]  
defines the conductance of the output n-driver during periods without  
modulation which can be used to regulate the modulation index  
Remark: the conductance value is binary weighted  
during soft Power-down mode the highest bit is forced to logic 1  
value is only used if driver TX1 or TX2 is switched on  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
56 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
9.3.3.8 CWGsPReg register  
Defines the conductance of the p-driver output during periods of no modulation.  
Table 101. CWGsPReg register (address 28h); reset value: 20h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
reserved  
-
CWGsP[5:0]  
R/W  
Table 102. CWGsPReg register bit descriptions  
Bit  
Symbol  
Description  
7 to 6  
5 to 0  
reserved  
reserved for future use  
CWGsP[5:0]  
defines the conductance of the p-driver output which can be used to  
regulate the output power and subsequently current consumption and  
operating distance  
Remark: the conductance value is binary weighted  
during soft Power-down mode the highest bit is forced to logic 1  
9.3.3.9 ModGsPReg register  
Defines the conductance of the p-driver output during modulation.  
Table 103. ModGsPReg register (address 29h); reset value: 20h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
reserved  
-
ModGsP[5:0]  
R/W  
Table 104. ModGsPReg register bit descriptions  
Bit  
Symbol  
Description  
7 to 6  
5 to 0  
reserved  
reserved for future use  
ModGsP[5:0] defines the conductance of the p-driver output during modulation  
which can be used to regulate the modulation index  
Remark: the conductance value is binary weighted  
during soft Power-down mode the highest bit is forced to logic 1  
if the TxASKReg register’s Force100ASK bit is set to logic 1 the value  
of ModGsP has no effect  
9.3.3.10 TModeReg and TPrescalerReg registers  
These registers define the timer settings.  
Remark: The TPrescaler setting higher 4 bits are in the TModeReg register and the lower  
8 bits are in the TPrescalerReg register.  
Table 105. TModeReg register (address 2Ah); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
TAuto  
R/W  
TGated[1:0]  
R/W  
TAutoRestart  
R/W  
TPrescaler_Hi[3:0]  
R/W  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
57 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 106. TModeReg register bit descriptions  
Bit  
Symbol  
Value Description  
7
TAuto  
1
timer starts automatically at the end of the transmission in all  
communication modes at all speeds  
if the RxModeReg register’s RxMultiple bit is not set, timer  
stops immediately after receiving the first data bit  
if the RxMultiple bit is set to logic 1 the timer never stops, in  
which case the timer can be stopped by setting the  
ControlReg register’s TStopNow bit to logic 1  
0
indicates that the timer is not influenced by the protocol  
internal timer is running in gated mode  
6 to 5 TGated[1:0]  
Remark: in gated mode, the Status1Reg register’s TRunning  
bit is logic 1 when the timer is enabled by the TModeReg  
register bits  
this bit does not influence the gating signal  
00  
01  
10  
11  
1
non-gated mode  
gated by pin MFIN  
gated by pin AUX1  
-
4
TAutoRestart  
timer automatically restarts its count-down from the 16-bit  
timer reload value instead of counting down to zero  
0
-
timer decrements to 0 and the ComIrqReg register’s  
TimerIRq bit is set to logic 1  
3 to 0 TPrescaler_Hi  
[3:0]  
defines the higher 4 bits of the TPrescaler value  
the following formula is used to calculate ftimer  
:
13.56 × 106  
TPrescaler + 1  
f timer  
=
--------------------------------------  
where 13.56 is the carrier frequency in MHz; for detailed  
description, see Section 8.5 “Timer unit”  
Table 107. TPrescalerReg register (address 2Bh); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
TPrescaler_Lo[7:0]  
R/W  
Table 108. TPrescalerReg register bit descriptions  
Bit  
Symbol  
Description  
7 to 0  
TPrescaler_Lo[7:0] defines the lower 8 bits of the TPrescaler value  
the following formula is used to calculate ftimer  
:
13.56 × 106  
TPrescaler + 1  
f timer  
=
--------------------------------------  
where 13.56 is the carrier frequency in MHz; for detailed  
description, see Section 8.5 “Timer unit”  
9.3.3.11 TReloadReg register  
Defines the 16-bit timer reload value.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
58 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Remark: The reload value bits are contained in two 8-bit registers.  
Table 109. TReloadReg (higher bits) register (address 2Ch); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
TReloadVal_Hi[7:0]  
R/W  
Table 110. TReloadReg register higher bit descriptions  
Bit  
Symbol  
Description  
7 to 0  
TReloadVal_Hi defines the higher 8 bits of the 16-bit timer reload value  
[7:0]  
on a start event, the timer loads the timer reload value  
changing this register affects the timer only at the next start event  
Table 111. TReloadReg (lower bits) register (address 2Dh); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
TReloadVal_Lo[7:0]  
R/W  
Table 112. TReloadReg register lower bit descriptions  
Bit  
Symbol  
Description  
7 to 0  
TReloadVal_Lo defines the lower 8 bits of the 16-bit timer reload value  
[7:0]  
on a start event, the timer loads the timer reload value  
changing this register affects the timer only at the next start event  
9.3.3.12 TCounterValReg register  
Contains the timer value.  
Remark: The timer value bits are contained in two 8-bit registers.  
Table 113. TCounterValReg (higher bits) register (address 2Eh); reset value: xxh bit  
allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
TCounterVal_Hi[7:0]  
R
Table 114. TCounterValReg register higher bit descriptions  
Bit  
Symbol  
Description  
7 to 0  
TCounterVal_Hi timer value higher 8 bits  
[7:0]  
Table 115. TCounterValReg (lower bits) register (address 2Fh); reset value: xxh bit  
allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
TCounterVal_Lo[7:0]  
R
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
59 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 116. TCounterValReg register lower bit descriptions  
Bit  
Symbol  
Description  
7 to 0  
TCounterVal_Lo timer value lower 8 bits  
[7:0]  
9.3.4 Page 3: Test  
9.3.4.1 Reserved register 30h  
Functionality is reserved for future use.  
Table 117. Reserved register (address 30h); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
reserved  
-
Table 118. Reserved register bit descriptions  
Bit  
Symbol  
Description  
reserved for future use  
7 to 0  
reserved  
9.3.4.2 TestSel1Reg register  
General test signal configuration.  
Table 119. TestSel1Reg register (address 31h); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
reserved  
-
TstBusBitSel[2:0]  
R/W  
Table 120. TestSel1Reg register bit descriptions  
Bit  
Symbol  
Description  
7 to 3  
2 to 0  
reserved  
reserved for future use  
TstBusBitSel selects a test bus signal which is output at pin MFOUT  
[2:0]  
if AnalogSelAux2[3:0] = FFh in AnalogTestReg register, test bus signal  
is also output at pins AUX1 or AUX2  
9.3.4.3 TestSel2Reg register  
General test signal configuration and PRBS control.  
Table 121. TestSel2Reg register (address 32h); reset value: 00h bit allocation  
Bit  
Symbol TstBusFlip PRBS9 PRBS15  
Access R/W R/W R/W  
7
6
5
4
3
2
1
0
TestBusSel[4:0]  
R/W  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
60 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 122. TestSel2Reg register bit descriptions  
Bit  
Symbol  
Value Description  
7
TstBusFlip  
1
test bus is mapped to the parallel port in the following order:  
TstBusBit4,TstBusBit3, TstBusBit2, TstBusBit6, TstBusBit5,  
TstBusBit0; see Section 16.1 on page 79  
6
5
PRBS9  
-
starts and enables the PRBS9 sequence according to ITU-TO150  
Remark: all relevant registers to transmit data must be configured  
before entering PRBS9 mode  
the data transmission of the defined sequence is started by the  
Transmit command  
PRBS15  
-
starts and enables the PRBS15 sequence according to ITU-TO150  
Remark: all relevant registers to transmit data must be configured  
before entering PRBS15 mode  
the data transmission of the defined sequence is started by the  
Transmit command  
4 to 0 TestBusSel -  
[4:0]  
selects the test bus; see Section 16.1 “Test signals”  
9.3.4.4 TestPinEnReg register  
Enables the test bus pin output driver.  
Table 123. TestPinEnReg register (address 33h); reset value: 80h bit allocation  
Bit  
Symbol RS232LineEn  
Access R/W  
7
6
5
4
3
2
1
0
TestPinEn[5:0]  
R/W  
reserved  
-
Table 124. TestPinEnReg register bit descriptions  
Bit  
Symbol  
Value Description  
7
RS232LineEn 0  
serial UART lines MX and DTRQ are disabled  
6 to 1 TestPinEn  
[5:0]  
-
enables the output driver on one of the data pins D1 to D7 which  
outputs a test signal  
Example:  
setting bit 1 to logic 1 enables pin D1 output  
setting bit 5 to logic 1 enables pin D5 output  
Remark: If the SPI is used, only pins D1 to D4 can be used. If the  
serial UART interface is used and the RS232LineEn bit is set to  
logic 1 only pins D1 to D4 can be used.  
0
reserved  
-
reserved for future use  
9.3.4.5 TestPinValueReg register  
Defines the HIGH and LOW values for the test port D1 to D7 when it is used as I/O.  
Table 125. TestPinValueReg register (address 34h); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
UseIO  
R/W  
TestPinValue[5:0]  
R/W  
reserved  
-
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
61 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 126. TestPinValueReg register bit descriptions  
Bit  
Symbol  
Value Description  
7
UseIO  
1
enables the I/O functionality for the test port when one of the serial  
interfaces is used  
the input/output behavior is defined by value TestPinEn[5:0] in the  
TestPinEnReg register  
the value for the output behavior is defined by TestPinValue[5:0]  
6 to 1 TestPinValue  
[5:0]  
-
defines the value of the test port when it is used as I/O and each  
output must be enabled by TestPinEn[5:0] in the TestPinEnReg  
register  
Remark: Reading the register indicates the status of pins D6 to D1  
if the UseIO bit is set to logic 1. If the UseIO bit is set to logic 0, the  
value of the TestPinValueReg register is read back.  
0
reserved  
-
reserved for future use  
9.3.4.6 TestBusReg register  
Shows the status of the internal test bus.  
Table 127. TestBusReg register (address 35h); reset value: xxh bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
TestBus[7:0]  
R
Table 128. TestBusReg register bit descriptions  
Bit  
Symbol  
Description  
7 to 0  
TestBus[7:0]  
shows the status of the internal test bus  
the test bus is selected using the TestSel2Reg register; see  
Section 16.1 on page 79  
9.3.4.7 AutoTestReg register  
Controls the digital self-test.  
Table 129. AutoTestReg register (address 36h); reset value: 40h bit allocation  
Bit  
Symbol reserved AmpRcv  
Access R/W  
7
6
5
4
3
2
1
0
RFT  
-
SelfTest[3:0]  
R/W  
-
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
62 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 130. AutoTestReg register bit descriptions  
Bit  
7
Symbol  
reserved  
AmpRcv  
Value Description  
-
reserved for production tests  
6
1
internal signal processing in the receiver chain is performed  
non-linearly which increases the operating distance in communication  
modes at 106 kBd  
Remark: due to non-linearity, the effect of the RxThresholdReg  
register’s MinLevel[3:0] and the CollLevel[2:0] values is also  
non-linear  
5 to 4 RFT  
-
-
reserved for production tests  
enables the digital self test  
3 to 0 SelfTest  
[3:0]  
the self test can also be started by the CalcCRC command; see  
Section 10.3.1.4 on page 68  
the self test is enabled by 1001b  
Remark: for default operation the self test must be disabled by 0000b  
9.3.4.8 VersionReg register  
Shows the MFRC522 software version.  
Table 131. VersionReg register (address 37h); reset value: xxh bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
Version[7:0]  
R
Table 132. VersionReg register bit descriptions  
Bit  
Symbol  
Description  
indicates current software version of the MFRC522  
Remark: the current version of the MFRC522 is 90h or 91h  
7 to 0  
Version[7:0]  
9.3.4.9 AnalogTestReg register  
Determines the analog output test signal at, and status of, pins AUX1 and AUX2.  
Table 133. AnalogTestReg register (address 38h); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
AnalogSelAux1[3:0]  
R/W  
AnalogSelAux2[3:0]  
R/W  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
63 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 134. AnalogTestReg register bit descriptions  
Bit Symbol Value Description  
controls pin AUX1  
3-state  
7 to 4 AnalogSelAux1  
[3:0]  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
output of TestDAC1 (AUX1), output of TestDAC2 (AUX2)[1]  
test signal Corr1[1]  
reserved  
DAC: test signal MinLevel[1]  
DAC: test signal ADC_I[1]  
DAC: test signal ADC_Q[1]  
reserved  
reserved, test signal for production test[1]  
reserved  
HIGH  
LOW  
TxActive:  
at 106 kBd: HIGH during Start bit, Data bit, Parity and CRC  
at 212 kBd: 424 kBd and 848 kBd: HIGH during data and  
CRC  
1101  
1110  
RxActive:  
at 106 kBd: HIGH during Data bit, Parity and CRC  
at 212 kBd: 424 kBd and 848 kBd: HIGH during data and  
CRC  
subcarrier detected:  
106 kBd: not applicable  
212 kBd: 424 kBd and 848 kBd: HIGH during last part of  
data and CRC  
1111  
test bus bit as defined by the TestSel1Reg register’s  
TstBusBitSel[2:0] bits  
Remark: all test signals are described in Section 16.1 on  
page 79  
3 to 0 AnalogSelAux2  
[3:0]  
-
controls pin AUX2 (see bit descriptions for AUX1)  
[1] Remark: Current source output; the use of 1 kpull-down resistor on AUXn is recommended.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
64 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
9.3.4.10 TestDAC1Reg register  
Defines the test value for TestDAC1.  
Table 135. TestDAC1Reg register (address 39h); reset value: xxh bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
reserved  
-
TestDAC1[5:0]  
R/W  
Table 136. TestDAC1Reg register bit descriptions  
Bit  
7
Symbol  
reserved  
reserved  
Description  
reserved for production tests  
reserved for future use  
6
5 to 0  
TestDAC1[5:0] defines the test value for TestDAC1  
output of DAC1 can be routed to AUX1 by setting value  
AnalogSelAux1[3:0] to 0001b in the AnalogTestReg register  
9.3.4.11 TestDAC2Reg register  
Defines the test value for TestDAC2.  
Table 137. TestDAC2Reg register (address 3Ah); reset value: xxh bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
reserved  
-
TestDAC2[5:0]  
R/W  
Table 138. TestDAC2Reg register bit descriptions  
Bit  
Symbol  
Description  
7 to 6  
5 to 0  
reserved  
reserved for future use  
TestDAC2[5:0] defines the test value for TestDAC2  
output of DAC2 can be routed to AUX2 by setting value  
AnalogSelAux2[3:0] to 0001b in the AnalogTestReg register  
9.3.4.12 TestADCReg register  
Shows the values of ADC I and Q channels.  
Table 139. TestADCReg register (address 3Bh); reset value: xxh bit allocation  
Bit  
7
6
5
4
3
2
1
0
Symbol  
Access  
ADC_I[3:0]  
ADC_Q[3:0]  
R
R
Table 140. TestADCReg register bit descriptions  
Bit  
Symbol  
Description  
7 to 4  
3 to 0  
ADC_I[3:0]  
ADC_Q[3:0]  
ADC I channel value  
ADC Q channel value  
9.3.4.13 Reserved register 3Ch  
Functionality reserved for production test.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
65 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 141. Reserved register (address 3Ch); reset value: FFh bit allocation  
Bit  
7
6
5
4
3
2
1
1
1
1
0
0
0
0
Symbol  
Access  
RFT  
-
Table 142. Reserved register bit descriptions  
Bit  
Symbol  
Description  
reserved for production tests  
7 to 0  
reserved  
Table 143. Reserved register (address 3Dh); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
Symbol  
Access  
RFT  
-
Table 144. Reserved register bit descriptions  
Bit  
Symbol  
Description  
reserved for production tests  
7 to 0  
reserved  
Table 145. Reserved register (address 3Eh); reset value: 03h bit allocation  
Bit  
7
6
5
4
3
2
Symbol  
Access  
RFT  
-
Table 146. Reserved register bit descriptions  
Bit  
Symbol  
Description  
reserved for production tests  
7 to 0  
reserved  
Table 147. Reserved register (address 3Fh); reset value: 00h bit allocation  
Bit  
7
6
5
4
3
2
Symbol  
Access  
reserved  
-
Table 148. Reserved register bit descriptions  
Bit  
Symbol  
Description  
7 to 0  
reserved  
reserved for production tests  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
66 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
10. MFRC522 command set  
10.1 General description  
The MFRC522 operation is determined by a state machine capable of performing a set of  
commands. A command is executed by writing a command code (see Table 149) to the  
CommandReg register.  
Arguments and/or data necessary to process a command are exchanged via the FIFO  
buffer.  
10.2 General behavior  
Each command that needs a data bit stream (or data byte stream) as an input  
immediately processes any data in the FIFO buffer. An exception to this rule is the  
Transceive command. Using this command, transmission is started with the  
BitFramingReg register’s StartSend bit.  
Each command that needs a certain number of arguments, starts processing only  
when it has received the correct number of arguments from the FIFO buffer.  
The FIFO buffer is not automatically cleared when commands start. This makes it  
possible to write command arguments and/or the data bytes to the FIFO buffer and  
then start the command.  
Each command can be interrupted by the host writing a new command code to the  
CommandReg register, for example, the Idle command.  
10.3 MFRC522 command overview  
Table 149. Command overview  
Command  
Command Action  
code  
Idle  
0000  
0001  
no action, cancels current command execution  
Mem  
stores 25 bytes into the internal buffer  
generates a 10-byte random ID number  
activates the CRC coprocessor or performs a self test  
transmits data from the FIFO buffer  
Generate RandomID 0010  
CalcCRC  
0011  
0100  
0111  
Transmit  
NoCmdChange  
no command change, can be used to modify the  
CommandReg register bits without affecting the command,  
for example, the PowerDown bit  
Receive  
1000  
1100  
activates the receiver circuits  
Transceive  
transmits data from FIFO buffer to antenna and automatically  
activates the receiver after transmission  
-
1101  
1110  
1111  
reserved for future use  
MFAuthent  
SoftReset  
performs the MIFARE standard authentication as a reader  
resets the MFRC522  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
67 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
10.3.1 MFRC522 command descriptions  
10.3.1.1 Idle  
Places the MFRC522 in Idle mode. The Idle command also terminates itself.  
10.3.1.2 Mem  
Transfers 25 bytes from the FIFO buffer to the internal buffer.  
To read out the 25 bytes from the internal buffer the Mem command must be started with  
an empty FIFO buffer. In this case, the 25 bytes are transferred from the internal buffer to  
the FIFO.  
During a hard power-down (using pin NRSTPD), the 25 bytes in the internal buffer remain  
unchanged and are only lost if the power supply is removed from the MFRC522.  
This command automatically terminates when finished and the Idle command becomes  
active.  
10.3.1.3 Generate RandomID  
This command generates a 10-byte random number which is initially stored in the internal  
buffer. This then overwrites the 10 bytes in the internal 25-byte buffer. This command  
automatically terminates when finished and the MFRC522 returns to Idle mode.  
10.3.1.4 CalcCRC  
The FIFO buffer content is transferred to the CRC coprocessor and the CRC calculation is  
started. The calculation result is stored in the CRCResultReg register. The CRC  
calculation is not limited to a dedicated number of bytes. The calculation is not stopped  
when the FIFO buffer is empty during the data stream. The next byte written to the FIFO  
buffer is added to the calculation.  
The CRC preset value is controlled by the ModeReg register’s CRCPreset[1:0] bits. The  
value is loaded in to the CRC coprocessor when the command starts.  
This command must be terminated by writing a command to the CommandReg register,  
such as, the Idle command.  
If the AutoTestReg register’s SelfTest[3:0] bits are set correctly, the MFRC522 enters Self  
Test mode. Starting the CalcCRC command initiates a digital self test. The result of the  
self test is written to the FIFO buffer.  
10.3.1.5 Transmit  
The FIFO buffer content is immediately transmitted after starting this command. Before  
transmitting the FIFO buffer content, all relevant registers must be set for data  
transmission.  
This command automatically terminates when the FIFO buffer is empty. It can be  
terminated by another command written to the CommandReg register.  
10.3.1.6 NoCmdChange  
This command does not influence any running command in the CommandReg register. It  
can be used to manipulate any bit except the CommandReg register Command[3:0] bits,  
for example, the RcvOff bit or the PowerDown bit.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
68 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
10.3.1.7 Receive  
The MFRC522 activates the receiver path and waits for a data stream to be received. The  
correct settings must be chosen before starting this command.  
This command automatically terminates when the data stream ends. This is indicated  
either by the end of frame pattern or by the length byte depending on the selected frame  
type and speed.  
Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Receive  
command will not automatically terminate. It must be terminated by starting another  
command in the CommandReg register.  
10.3.1.8 Transceive  
This command continuously repeats the transmission of data from the FIFO buffer and the  
reception of data from the RF field. The first action is transmit and after transmission the  
command is changed to receive a data stream.  
Each transmit process must be started by setting the BitFramingReg register’s StartSend  
bit to logic 1. This command must be cleared by writing any command to the  
CommandReg register.  
Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Transceive  
command never leaves the receive state because this state cannot be cancelled  
automatically.  
10.3.1.9 MFAuthent  
This command manages MIFARE authentication to enable a secure communication to  
any MIFARE Mini, MIFARE 1K and MIFARE 4K card. The following data is written to the  
FIFO buffer before the command can be activated:  
Authentication command code (60h, 61h)  
Block address  
Sector key byte 0  
Sector key byte 1  
Sector key byte 2  
Sector key byte 3  
Sector key byte 4  
Sector key byte 5  
Card serial number byte 0  
Card serial number byte 1  
Card serial number byte 2  
Card serial number byte 3  
In total 12 bytes are written to the FIFO.  
Remark: When the MFAuthent command is active all access to the FIFO buffer is blocked.  
However, if there is access to the FIFO buffer, the ErrorReg register’s WrErr bit is set.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
69 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
This command automatically terminates when the MIFARE card is authenticated and the  
Status2Reg register’s MFCrypto1On bit is set to logic 1.  
This command does not terminate automatically if the card does not answer, so the timer  
must be initialized to automatic mode. In this case, in addition to the IdleIRq bit, the  
TimerIRq bit can be used as the termination criteria. During authentication processing, the  
RxIRq bit and TxIRq bit are blocked. The Crypto1On bit is only valid after termination of  
the MFAuthent command, either after processing the protocol or writing Idle to the  
CommandReg register.  
If an error occurs during authentication, the ErrorReg register’s ProtocolErr bit is set to  
logic 1 and the Status2Reg register’s Crypto1On bit is set to logic 0.  
10.3.1.10 SoftReset  
This command performs a reset of the device. The configuration data of the internal buffer  
remains unchanged. All registers are set to the reset values. This command automatically  
terminates when finished.  
Remark: The SerialSpeedReg register is reset and therefore the serial data rate is set to  
9.6 kBd.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
70 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
11. Limiting values  
Table 150. Limiting values  
In accordance with the Absolute Maximum Rating System (IEC 60134).  
Symbol Parameter  
Conditions  
Min  
Max  
+4.0  
+4.0  
+4.0  
+4.0  
+4.0  
Unit  
V
VDDA  
VDDD  
analog supply voltage  
digital supply voltage  
0.5  
0.5  
0.5  
0.5  
0.5  
V
VDD(PVDD) PVDD supply voltage  
VDD(TVDD) TVDD supply voltage  
VDD(SVDD) SVDD supply voltage  
V
V
V
VI  
input voltage  
all input pins except pins MFIN and  
RX  
V
SS(PVSS) 0.5 VDD(PVDD) + 0.5 V  
pin MFIN  
V
-
SS(PVSS) 0.5 VDD(SVDD) + 0.5 V  
Ptot  
total power dissipation  
junction temperature  
per package; and VDDD in shortcut  
mode  
200  
mW  
Tj  
-
-
100  
°C  
VESD  
electrostatic discharge voltage HBM; 1500 , 100 pF;  
2000  
V
JESD22-A114-B  
MM; 0.75 µH, 200 pF;  
-
200  
V
JESD22-A114-A  
12. Recommended operating conditions  
Table 151. Operating conditions  
Symbol  
Parameter  
Conditions  
Min  
Typ  
Max Unit  
[1][2]  
[1][2]  
[1][2]  
[3]  
VDDA  
analog supply voltage  
V
V
DD(PVDD) VDDA = VDDD = VDD(TVDD)  
SSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V  
;
2.5  
3.3  
3.3  
3.3  
1.8  
3.6  
3.6  
3.6  
3.6  
V
V
V
V
digital supply voltage  
V
V
DD(PVDD) VDDA = VDDD = VDD(TVDD)  
SSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V  
;
2.5  
2.5  
1.6  
VDDD  
VDD(TVDD) TVDD supply voltage  
VDD(PVDD) PVDD supply voltage  
VDD(SVDD) SVDD supply voltage  
V
V
DD(PVDD) VDDA = VDDD = VDD(TVDD)  
SSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V  
;
V
V
DD(PVDD) VDDA = VDDD = VDD(TVDD)  
SSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V  
;
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V  
HVQFN32  
1.6  
-
-
3.6  
V
Tamb  
ambient temperature  
25  
+85  
°C  
[1] Supply voltages below 3 V reduce the performance (the achievable operating distance).  
[2] VDDA, VDDD and VDD(TVDD) must always be the same voltage.  
[3] VDD(PVDD) must always be the same or lower voltage than VDDD  
13. Thermal characteristics  
Table 152. Thermal characteristics  
.
Symbol Parameter  
Conditions  
Package  
Typ Unit  
Rth(j-a)  
thermal resistance from junction to  
ambient  
in still air with exposed pin soldered on a  
4 layer JEDEC PCB  
HVQFN32 40 K/W  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
71 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
14. Characteristics  
Table 153. Characteristics  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
Input characteristics  
Pins EA, I2C and NRSTPD  
ILI  
input leakage current  
HIGH-level input voltage  
LOW-level input voltage  
1  
-
-
-
+1  
µA  
V
VIH  
0.7VDD(PVDD)  
-
-
VIL  
0.3VDD(PVDD)  
V
Pin MFIN  
ILI  
input leakage current  
HIGH-level input voltage  
LOW-level input voltage  
1  
-
-
-
+1  
µA  
V
VIH  
0.7VDD(SVDD)  
-
-
VIL  
0.3VDD(SVDD)  
V
Pin SDA  
ILI  
input leakage current  
HIGH-level input voltage  
LOW-level input voltage  
1  
-
-
-
+1  
µA  
V
VIH  
0.7VDD(PVDD)  
-
-
VIL  
0.3VDD(PVDD)  
V
Pin RX[1]  
Vi  
Ci  
input voltage  
1  
-
VDDA +1  
-
V
input capacitance  
VDDA = 3 V; receiver active;  
-
10  
pF  
VRX(p-p) = 1 V; 1.5 V (DC)  
offset  
Ri  
input resistance  
VDDA = 3 V; receiver active;  
-
350  
-
VRX(p-p) = 1 V; 1.5 V (DC)  
offset  
Input voltage range; see Figure 24  
Vi(p-p)(min) minimum peak-to-peak input Manchester encoded;  
voltage DDA = 3 V  
Vi(p-p)(max) maximum peak-to-peak input Manchester encoded;  
-
-
100  
4
-
-
mV  
V
V
voltage  
VDDA = 3 V  
Input sensitivity; see Figure 24  
Vmod  
modulation voltage  
minimum Manchester  
encoded; VDDA = 3 V;  
RxGain[2:0] = 111b (48 dB)  
-
5
-
mV  
Pin OSCIN  
ILI  
input leakage current  
HIGH-level input voltage  
LOW-level input voltage  
input capacitance  
1  
-
+1  
µA  
V
VIH  
VIL  
Ci  
0.7VDDA  
-
-
-
-
-
0.3VDDA  
-
V
VDDA = 2.8 V; DC = 0.65 V;  
AC = 1 V (p-p)  
2
pF  
Input/output characteristics  
pins D1, D2, D3, D4, D5, D6 and D7  
ILI  
input leakage current  
HIGH-level input voltage  
LOW-level input voltage  
1  
-
-
-
+1  
µA  
V
VIH  
VIL  
0.7VDD(PVDD)  
-
-
0.3VDD(PVDD)  
V
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
72 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 153. Characteristics …continued  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
VOH  
HIGH-level output voltage  
VDD(PVDD) = 3 V; IO = 4 mA  
VDD(PVDD)  
0.4  
-
VDD(PVDD)  
V
VOL  
LOW-level output voltage  
VDD(PVDD) = 3 V; IO = 4 mA  
VSS(PVSS)  
-
VSS(PVSS)  
0.4  
+
V
IOH  
IOL  
HIGH-level output current  
LOW-level output current  
VDD(PVDD) = 3 V  
VDD(PVDD) = 3 V  
-
-
-
-
4
4
mA  
mA  
Output characteristics  
Pin MFOUT  
VOH  
HIGH-level output voltage  
VDD(SVDD) = 3 V; IO = 4 mA  
VDD(SVDD) = 3 V; IO = 4 mA  
VDD(SVDD)  
0.4  
-
-
VDD(SVDD)  
V
V
VOL  
LOW-level output voltage  
VSS(PVSS)  
VSS(PVSS)  
0.4  
+
IOL  
LOW-level output current  
HIGH-level output current  
VDD(SVDD) = 3 V  
VDD(SVDD) = 3 V  
-
-
-
-
4
4
mA  
mA  
IOH  
Pin IRQ  
VOH  
HIGH-level output voltage  
LOW-level output voltage  
VDD(PVDD) = 3 V; IO = 4 mA  
VDD(PVDD) = 3 V; IO = 4 mA  
VDD(PVDD)  
0.4  
-
-
VDD(PVDD)  
V
V
VOL  
VSS(PVSS)  
VSS(PVSS)  
0.4  
+
+
IOL  
IOH  
LOW-level output current  
HIGH-level output current  
VDD(PVDD) = 3 V  
VDD(PVDD) = 3 V  
-
-
-
-
4
4
mA  
mA  
Pins AUX1 and AUX2  
VOH  
VOL  
HIGH-level output voltage  
VDDD = 3 V; IO = 4 mA  
VDDD = 3 V; IO = 4 mA  
V
DDD 0.4  
-
-
VDDD  
V
V
LOW-level output voltage  
VSS(PVSS)  
VSS(PVSS)  
0.4  
IOL  
IOH  
LOW-level output current  
HIGH-level output current  
VDDD = 3 V  
VDDD = 3 V  
-
-
-
-
4
4
mA  
mA  
Pins TX1 and TX2  
VOH  
HIGH-level output voltage  
VDD(TVDD) = 3 V;  
VDD(TVDD)  
0.15  
-
-
-
-
-
-
-
-
V
V
V
V
IDD(TVDD) = 32 mA;  
CWGsP[5:0] = 3Fh  
V
DD(TVDD) = 3 V;  
DD(TVDD) = 80 mA;  
CWGsP[5:0] = 3Fh  
VDD(TVDD)  
0.4  
I
V
DD(TVDD) = 2.5 V;  
DD(TVDD) = 32 mA;  
CWGsP[5:0] = 3Fh  
VDD(TVDD)  
0.24  
I
V
DD(TVDD) = 2.5 V;  
DD(TVDD) = 80 mA;  
CWGsP[5:0] = 3Fh  
VDD(TVDD)  
0.64  
I
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
73 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 153. Characteristics …continued  
Symbol Parameter  
Conditions  
Min  
Typ  
Max  
Unit  
VOL  
LOW-level output voltage  
VDD(TVDD) = 3 V;  
-
-
0.15  
V
IDD(TVDD) = 32 mA;  
CWGsP[5:0] = 0Fh  
VDD(TVDD) = 3 V;  
-
-
-
-
-
-
0.4  
V
V
V
IDD(TVDD) = 80 mA;  
CWGsP[5:0] = 0Fh  
VDD(TVDD) = 2.5 V;  
0.24  
0.64  
IDD(TVDD) = 32 mA;  
CWGsP[5:0] = 0Fh  
VDD(TVDD) = 2.5 V;  
IDD(TVDD) = 80 mA;  
CWGsP[5:0] = 0Fh  
Current consumption  
Ipd  
power-down current  
VDDA = VDDD = VDD(TVDD) =  
VDD(PVDD) = 3 V  
[2]  
[2]  
hard power-down; pin  
NRSTPD set LOW  
-
-
-
-
5
µA  
µA  
soft power-down; RF level  
detector on  
10  
IDDD  
IDDA  
digital supply current  
analog supply current  
pin DVDD; VDDD = 3 V  
-
-
6.5  
7
9
mA  
mA  
pin AVDD; VDDA = 3 V;  
bit RcvOff = 0  
10  
pin AVDD; receiver  
switched off; VDDA = 3 V;  
bit RcvOff = 1  
-
3
5
mA  
[3]  
[4][5][6]  
[7]  
IDD(PVDD) PVDD supply current  
IDD(TVDD) TVDD supply current  
IDD(SVDD) SVDD supply current  
Clock frequency  
pin PVDD  
-
-
-
-
40  
100  
4
mA  
mA  
mA  
pin TVDD; continuous wave  
pin SVDD  
60  
-
fclk  
δclk  
tjit  
clock frequency  
clock duty cycle  
jitter time  
-
27.12  
-
MHz  
%
40  
-
50  
-
60  
10  
RMS  
ps  
Crystal oscillator  
VOH  
VOL  
Ci  
HIGH-level output voltage  
pin OSCOUT  
pin OSCOUT  
pin OSCOUT  
pin OSCIN  
-
-
-
-
1.1  
0.2  
2
-
-
-
-
V
LOW-level output voltage  
input capacitance  
V
pF  
pF  
2
Typical input requirements  
fxtal  
crystal frequency  
-
-
-
-
27.12  
-
-
MHz  
ESR  
CL  
equivalent series resistance  
load capacitance  
100  
-
10  
pF  
Pxtal  
crystal power dissipation  
50  
100  
mW  
[1] The voltage on pin RX is clamped by internal diodes to pins AVSS and AVDD.  
[2] Ipd is the total current for all supplies.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
74 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
[3] IDD(PVDD) depends on the overall load at the digital pins.  
[4] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2.  
[5] During typical circuit operation, the overall current is below 100 mA.  
[6] Typical value using a complementary driver configuration and an antenna matched to 40 between pins TX1 and TX2 at 13.56 MHz.  
[7] IDD(SVDD) depends on the load at pin MFOUT.  
V
DDA  
+ 1 V  
V
mod  
V
V
i(p-p)(min)  
i(p-p)(max)  
VMID  
13.56 MHz  
carrier  
0 V  
001aak012  
1 V  
Fig 24. Pin RX input voltage range  
14.1 Timing characteristics  
Table 154. SPI timing characteristics  
Symbol  
tWL  
Parameter  
Conditions  
line SCK  
Min  
Typ  
Max  
Unit  
ns  
pulse width LOW  
pulse width HIGH  
50  
50  
25  
-
-
-
-
-
-
tWH  
line SCK  
ns  
th(SCKH-D)  
SCK HIGH to data input SCK to changing  
hold time MOSI  
ns  
tsu(D-SCKH) data input to SCK HIGH changing MOSI to  
set-up time SCK  
25  
-
-
-
-
-
ns  
ns  
ns  
th(SCKL-Q)  
SCK LOW to data output SCK to changing  
hold time MISO  
25  
-
t(SCKL-NSSH) SCK LOW to NSS HIGH  
time  
0
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
75 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 155. I2C-bus timing in Fast mode  
Symbol Parameter  
Conditions  
Fast mode High-speed Unit  
mode  
Min Max Min Max  
fSCL  
SCL clock frequency  
0
400  
-
0
3400 kHz  
tHD;STA  
hold time (repeated) START  
condition  
after this period,  
the first clock pulse  
is generated  
600  
160  
-
ns  
tSU;STA  
set-up time for a repeated  
START condition  
600  
-
160  
-
ns  
tSU;STO set-up time for STOP condition  
600  
1300  
600  
0
-
160  
160  
60  
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tLOW  
tHIGH  
tHD;DAT  
tSU;DAT  
tr  
LOW period of the SCL clock  
HIGH period of the SCL clock  
data hold time  
-
-
-
-
900  
-
0
70  
-
data set-up time  
rise time  
100  
20  
10  
SCL signal  
SCL signal  
300 10  
300 10  
300 10  
40  
40  
80  
tf  
fall time  
20  
tr  
rise time  
SDA and SCL  
signals  
20  
tf  
fall time  
SDA and SCL  
signals  
20  
300 10  
80  
-
ns  
tBUF  
bus free time between a STOP  
and START condition  
1.3  
-
1.3  
µs  
t
t
t
t
SCKL  
SCKL  
SCKH  
SHDX  
SCK  
t
SLDX  
t
t
DXSH  
DXSH  
MOSI  
MISO  
NSS  
MSB  
MSB  
LSB  
LSB  
t
SLNH  
001aaj634  
Remark: The signal NSS must be LOW to be able to send several bytes in one data stream.  
To send more than one data stream NSS must be set HIGH between the data streams.  
Fig 25. Timing diagram for SPI  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
76 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
SDA  
SCL  
t
t
t
t
r
f
SU;DAT  
SP  
t
t
t
t
BUF  
LOW  
f
HD;STA  
t
t
t
SU;STO  
r
HIGH  
t
t
SU;STA  
HD;STA  
t
HD;DAT  
S
Sr  
P
S
001aaj635  
Fig 26. Timing for Fast and Standard mode devices on the I2C-bus  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
77 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
15. Application information  
A typical application diagram using a complementary antenna connection to the  
MFRC522 is shown in Figure 27.  
The antenna tuning and RF part matching is described in the application note Ref. 1 and  
Ref. 2.  
supply  
DVDD  
AVDD  
15  
TVDD  
12  
3
C
Rx  
PVDD  
PVSS  
RX  
2
5
6
17  
16  
R1  
C
vmid  
VMID  
TX1  
R2  
C1  
C1  
L0  
Ra  
C2  
NRSTPD  
11  
antenna  
Lant  
host  
interface  
C0  
C0  
MFRC522  
TVSS  
TX2  
MICRO-  
PROCESSOR  
10, 14  
13  
C2  
Ra  
L0  
IRQ  
23  
18  
AVSS  
DVSS  
4
21  
22  
OSCOUT  
OSCIN  
27.12 MHz  
001aaj636  
Fig 27. Typical application diagram  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
78 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
16. Test information  
16.1 Test signals  
16.1.1 Self test  
The MFRC522 has the capability to perform a digital self test. The self test is started by  
using the following procedure:  
1. Perform a soft reset.  
2. Clear the internal buffer by writing 25 bytes of 00h and implement the Config  
command.  
3. Enable the self test by writing 09h to the AutoTestReg register.  
4. Write 00h to the FIFO buffer.  
5. Start the self test with the CalcCRC command.  
6. The self test is initiated.  
7. When the self test has completed, the FIFO buffer contains the following 64 bytes:  
FIFO buffer byte values for version 90h:  
00h, 87h, 98h, 0fh, 49h, FFh, 07h, 19h  
BFh, 22h, 30h, 49h, 59h, 63h, ADh, CAh  
7Fh, E3h, 4Eh, 03h, 5Ch, 4Eh, 49h, 50h  
47h, 9Ah, 37h, 61h, E7h, E2h, C6h, 2Eh  
75h, 5Ah, EDh, 04h, 3Dh, 02h, 4Bh, 78h  
32h, FFh, 58h, 3Bh, 7Ch, E9h, 00h, 94h  
B4h, 4Ah, 59h, 5Bh, FDh, U9h, 29h, DFh  
35h, 96h, 98h, 9Eh, 4Fh, 30h, 32h, 8Dh  
FIFO buffer byte values for version 91h:  
00h, C6h, 37h, D5h, 32h, B7h, 57h, 5Ch  
C2h, D8h, 7Ch, 4Dh, D9h, 70h, C7h, 73h  
10h, E6h, D2h, AAh, 5Eh, A1h, 3Eh, 5Ah  
14h, AFh, 30h, 61h, C9h, 70h, DBh, 2Eh  
64h, 22h, 72h, B5h, BDh, 65h, F4h, ECh  
22h, BCh, D3h, 72h, 35h, CDh, AAh, 41h  
1Fh, A7h, F3h, 53h, 14h, DEh, 7Eh, 02h  
D9h, 0Fh, B5h, 5Eh, 25h, 1Dh, 29h, 79h  
16.1.2 Test bus  
The test bus is used for production tests. The following configuration can be used to  
improve the design of a system using the MFRC522. The test bus allows internal signals  
to be routed to the digital interface. The test bus comprises two sets of test signals which  
are selected using their subaddress specified in the TestSel2Reg register’s  
TestBusSel[4:0] bits. The test signals and their related digital output pins are described in  
Table 156 and Table 157.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
79 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 156. Test bus signals: TestBusSel[4:0] = 07h  
Pins  
Internal  
Description  
signal name  
D6  
D5  
D4  
D3  
D2  
D1  
s_data  
s_coll  
s_valid  
s_over  
RCV_reset  
-
received data stream  
bit-collision detected (106 kBd only)  
s_data and s_coll signals are valid  
receiver has detected a stop condition  
receiver is reset  
reserved  
Table 157. Test bus signals: TestBusSel[4:0] = 0Dh  
Pins  
Internal test  
signal name  
Description  
D6  
clkstable  
oscillator output signal  
oscillator output signal divided by 8  
reserved  
D5  
clk27/8  
D4 to D3  
D2  
-
clk27  
-
oscillator output signal  
reserved  
D1  
16.1.3 Test signals on pins AUX1 or AUX2  
The MFRC522 allows the user to select internal signals for measurement on pins AUX1 or  
AUX2. These measurements can be helpful during the design-in phase to optimize the  
design or used for test purposes.  
Table 158 shows the signals that can be switched to pin AUX1 or AUX2 by setting  
AnalogSelAux1[3:0] or AnalogSelAux2[3:0] in the AnalogTestReg register.  
Remark: The DAC has a current output, therefore it is recommended that a 1 kΩ  
pull-down resistor is connected to pin AUX1 or AUX2.  
Table 158. Test signal descriptions  
AnalogSelAux1[3:0] Signal on pin AUX1 or pin AUX2  
or  
AnalogSelAux2[3:0]  
value  
0000  
3-state  
0001  
DAC: register TestDAC1 or TestDAC2  
DAC: test signal Corr1  
reserved  
0010  
0011  
0100  
DAC: test signal MinLevel  
DAC: test signal ADC_I  
DAC: test signal ADC_Q  
reserved  
0101  
0110  
0111 to 1001  
1010  
HIGH  
1011  
LOW  
1100  
TxActive  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
80 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 158. Test signal descriptions …continued  
AnalogSelAux1[3:0] Signal on pin AUX1 or pin AUX2  
or  
AnalogSelAux2[3:0]  
value  
1101  
1110  
1111  
RxActive  
subcarrier detected  
TstBusBit  
16.1.3.1 Example: Output test signals TestDAC1 and TestDAC2  
The AnalogTestReg register is set to 11h. The output on pin AUX1 has the test signal  
TestDAC1 and the output on pin AUX2 has the test signal TestDAC2. The signal values of  
TestDAC1 and TestDAC2 are controlled by the TestDAC1Reg and TestDAC2Reg registers.  
Figure 28 shows test signal TestDAC1 on pin AUX1 and TestDAC2 on pin AUX2 when the  
TestDAC1Reg register is programmed with a slope defined by values 00h to 3Fh and the  
TestDAC2Reg register is programmed with a rectangular signal defined by values 00h and  
3Fh.  
001aak597  
(1)  
(2)  
100 ms/div  
(1) TestDAC1 (500 mV/div) on pin AUX1.  
(2) TestDAC2 (500 mV/div) on pin AUX2.  
Fig 28. Output test signals TestDAC1 on pin AUX1 and TestDAC2 on pin AUX2  
16.1.3.2 Example: Output test signals Corr1 and MinLevel  
Figure 29 shows test signals Corr1 and MinLevel on pins AUX1 and AUX2, respectively.  
The AnalogTestReg register is set to 24h.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
81 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
001aak598  
(1)  
(2)  
(3)  
10 µs/div  
(1) MinLevel (1 V/div) on pin AUX2.  
(2) Corr1 (1 V/div) on pin AUX1.  
(3) RF field.  
Fig 29. Output test signals Corr1 on pin AUX1 and MinLevel on pin AUX2  
16.1.3.3 Example: Output test signals ADC channel I and ADC channel Q  
Figure 30 shows the channel behavior test signals ADC_I and ADC_Q on pins AUX1 and  
AUX2, respectively. The AnalogTestReg register is set to 56h.  
001aak599  
(1)  
(2)  
(3)  
5 µs/div  
(1) ADC_I (1 V/div) on pin AUX1.  
(2) ADC_Q (500 mV/div) on pin AUX2.  
(3) RF field.  
Fig 30. Output ADC channel I on pin AUX1 and ADC channel Q on pin AUX2  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
82 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
16.1.3.4 Example: Output test signals RxActive and TxActive  
Figure 31 shows the RxActive and TxActive test signals relating to RF communication.  
The AnalogTestReg register is set to CDh.  
At 106 kBd, RxActive is HIGH during data bits, parity and CRC reception. Start bits  
are not included  
At 106 kBd, TxActive is HIGH during start bits, data bits, parity and CRC transmission  
At 212 kBd, 424 kBd and 848 kBd, RxActive is HIGH during data bits and CRC  
reception. Start bits are not included  
At 212 kBd, 424 kBd and 848 kBd, TxActive is HIGH during data bits and CRC  
transmission  
001aak600  
(1)  
(2)  
(3)  
10 µs/div  
(1) RxActive (2 V/div) on pin AUX1.  
(2) TxActive (2 V/div) on pin AUX2.  
(3) RF field.  
Fig 31. Output RxActive on pin AUX1 and TxActive on pin AUX2  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
83 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
16.1.3.5 Example: Output test signal RX data stream  
Figure 32 shows the data stream that is currently being received. The TestSel2Reg  
register’s TestBusSel[4:0] bits are set to 07h to enable test bus signals on pins D1 to D6;  
see Section 16.1.2 on page 79. The TestSel1Reg register’s TstBusBitSel[2:0] bits are set  
06h (pin D6 = s_data) and AnalogTestReg register is set to FFh (TstBusBit) which outputs  
the received data stream on pins AUX1 and AUX2.  
001aak601  
(1)  
(2)  
20 µs/div  
(1) s_data (received data stream) (2 V/div).  
(2) RF field.  
Fig 32. Received data stream on pins AUX1 and AUX2  
16.1.3.6 PRBS  
The pseudo-random binary sequences PRBS9 and PRBS15 are based on ITU-TO150  
and are defined with the TestSel2Reg register. Transmission of either data stream is  
started by the Transmit command. The preamble/sync byte/start bit/parity bit are  
automatically generated depending on the mode selected.  
Remark: All relevant registers for transmitting data must be configured in accordance with  
ITU-TO150 before selecting PRBS transmission.  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
84 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
17. Package outline  
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;  
32 terminals; body 5 x 5 x 0.85 mm  
SOT617-1  
B
A
D
terminal 1  
index area  
A
A
1
E
c
detail X  
C
e
1
y
y
e
1/2 e  
v
M
M
b
C
C
A B  
C
1
w
9
16  
L
17  
8
e
e
E
h
2
1/2 e  
1
24  
terminal 1  
index area  
32  
25  
X
D
h
0
2.5  
5 mm  
scale  
DIMENSIONS (mm are the original dimensions)  
(1)  
A
(1)  
(1)  
UNIT  
A
b
c
E
e
e
e
2
y
D
D
E
L
v
w
y
1
1
h
1
h
max.  
0.05 0.30  
0.00 0.18  
5.1  
4.9  
3.25  
2.95  
5.1  
4.9  
3.25  
2.95  
0.5  
0.3  
mm  
0.05 0.1  
1
0.2  
0.5  
3.5  
3.5  
0.1  
0.05  
Note  
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.  
REFERENCES  
OUTLINE  
EUROPEAN  
PROJECTION  
ISSUE DATE  
VERSION  
IEC  
JEDEC  
JEITA  
01-08-08  
02-10-18  
SOT617-1  
- - -  
MO-220  
- - -  
Fig 33. Package outline SOT617-1 (HVQFN32)  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
85 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Detailed package information can be found at:  
http://www.nxp.com/package/SOT617-1.html.  
18. Handling information  
Moisture Sensitivity Level (MSL) evaluation has been performed according to  
SNW-FQ-225B rev.04/07/07 (JEDEC J-STD-020C). MSL for this package is level 1 which  
means 260 °C convection reflow temperature.  
Dry pack is not required.  
Unlimited out-of-pack floor life at maximum ambient 30 °C/85 % RH.  
19. Packing information  
strap 46 mm from corner  
The straps around the package of  
stacked trays inside the piano-box  
have sufficient pre-tension to avoid  
loosening of the trays.  
tray  
ESD warning preprinted  
barcode label (permanent)  
barcode label (peel-off)  
chamfer  
PIN 1  
chamfer  
PIN 1  
QA seal  
Hyatt patent preprinted  
In the traystack (2 trays)  
only ONE tray type* allowed  
printed piano box  
*one supplier and one revision number.  
001aaj740  
Fig 34. Packing information 1 tray  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
86 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
20. Abbreviations  
Table 159. Abbreviations  
Acronym  
ADC  
BPSK  
CRC  
CW  
Description  
Analog-to-Digital Converter  
Binary Phase Shift Keying  
Cyclic Redundancy Check  
Continuous Wave  
DAC  
HBM  
I2C  
Digital-to-Analog Converter  
Human Body Model  
Inter-integrated Circuit  
Least Significant Bit  
Master In Slave Out  
Machine Model  
LSB  
MISO  
MM  
MOSI  
MSB  
NRZ  
NSS  
PLL  
Master Out Slave In  
Most Significant Bit  
Not Return to Zero  
Not Slave Select  
Phase-Locked Loop  
Pseudo-Random Bit Sequence  
Receiver  
PRBS  
RX  
SOF  
SPI  
Start Of Frame  
Serial Peripheral Interface  
Transmitter  
TX  
UART  
Universal Asynchronous Receiver Transmitter  
21. References  
[1] Application note — MFRC52x Reader IC Family Directly Matched Antenna  
Design  
[2] Application note — MIFARE (ISO/IEC 14443 A) 13.56 MHz RFID Proximity  
Antennas  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
87 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
22. Revision history  
Table 160. Revision history  
Document ID  
MFRC522_33  
Modifications:  
Release date  
20091026  
Data sheet status  
Change notice  
Supersedes  
Product data sheet  
-
112132  
The format of this data sheet has been redesigned to comply with the new identity  
guidelines of NXP Semiconductors.  
Legal texts have been adapted to the new company name where appropriate.  
General re-wording of MIFARE designation and commercial conditions.  
Table 106 “TModeReg register bit descriptions” and Table 108 “TPrescalerReg register bit  
descriptions”: changed value "fTimer = 13.56 MHz / (TPreScaler + 1)"  
Graphics: updated to latest standard  
Descriptive text: updated  
Register and bit names: updated  
Register tables: presentation updated  
Parameter symbols: updated  
Section 9 “MFRC522 registers” now follows Section 8 “Functional description”  
Section 16 “Test information” added, incorporating Section 16.1 “Test signals”  
112132  
112131  
112130  
May 2007  
Product data sheet  
200705005F  
112131  
112130  
112121  
September 2006 Product data sheet  
-
-
December 2005 Product data sheet  
PUBLIC  
112121  
112120  
112110  
112104  
112103  
September 2005 Product data sheet  
-
-
-
-
-
112120  
112110  
112104  
112103  
-
July 2005  
July 2005  
Preliminary data sheet  
Objective data sheet  
November 2004 Objective data sheet  
October 2004  
Objective data sheet  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
88 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
23. Legal information  
23.1 Data sheet status  
Document status[1][2]  
Product status[3]  
Development  
Definition  
Objective [short] data sheet  
This document contains data from the objective specification for product development.  
This document contains data from the preliminary specification.  
This document contains the product specification.  
Preliminary [short] data sheet Qualification  
Product [short] data sheet Production  
[1]  
[2]  
[3]  
Please consult the most recently issued document before initiating or completing a design.  
The term ‘short data sheet’ is explained in section “Definitions”.  
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status  
information is available on the Internet at URL http://www.nxp.com.  
the device at these or any other conditions above those given in the  
Characteristics sections of this document is not implied. Exposure to limiting  
values for extended periods may affect device reliability.  
23.2 Definitions  
Draft — The document is a draft version only. The content is still under  
internal review and subject to formal approval, which may result in  
modifications or additions. NXP Semiconductors does not give any  
representations or warranties as to the accuracy or completeness of  
information included herein and shall have no liability for the consequences of  
use of such information.  
Terms and conditions of sale — NXP Semiconductors products are sold  
subject to the general terms and conditions of commercial sale, as published  
at http://www.nxp.com/profile/terms, including those pertaining to warranty,  
intellectual property rights infringement and limitation of liability, unless  
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of  
any inconsistency or conflict between information in this document and such  
terms and conditions, the latter will prevail.  
Short data sheet — A short data sheet is an extract from a full data sheet  
with the same product type number(s) and title. A short data sheet is intended  
for quick reference only and should not be relied upon to contain detailed and  
full information. For detailed and full information see the relevant full data  
sheet, which is available on request via the local NXP Semiconductors sales  
office. In case of any inconsistency or conflict with the short data sheet, the  
full data sheet shall prevail.  
No offer to sell or license — Nothing in this document may be interpreted  
or construed as an offer to sell products that is open for acceptance or the  
grant, conveyance or implication of any license under any copyrights, patents  
or other industrial or intellectual property rights.  
Export control — This document as well as the item(s) described herein  
may be subject to export control regulations. Export might require a prior  
authorization from national authorities.  
23.3 Disclaimers  
Quick reference data — The Quick reference data is an extract of the  
product data given in the Limiting values and Characteristics sections of this  
document, and as such is not complete, exhaustive or legally binding.  
General — Information in this document is believed to be accurate and  
reliable. However, NXP Semiconductors does not give any representations or  
warranties, expressed or implied, as to the accuracy or completeness of such  
information and shall have no liability for the consequences of use of such  
information.  
23.4 Licenses  
Right to make changes — NXP Semiconductors reserves the right to make  
changes to information published in this document, including without  
limitation specifications and product descriptions, at any time and without  
notice. This document supersedes and replaces all information supplied prior  
to the publication hereof.  
Purchase of NXP ICs with ISO/IEC 14443 type B functionality  
This NXP Semiconductors IC is ISO/IEC 14443 Type B  
software enabled and is licensed under Innovatron’s  
Contactless Card patents license for ISO/IEC 14443 B.  
Suitability for use — NXP Semiconductors products are not designed,  
authorized or warranted to be suitable for use in medical, military, aircraft,  
space or life support equipment, nor in applications where failure or  
malfunction of an NXP Semiconductors product can reasonably be expected  
to result in personal injury, death or severe property or environmental  
damage. NXP Semiconductors accepts no liability for inclusion and/or use of  
NXP Semiconductors products in such equipment or applications and  
therefore such inclusion and/or use is at the customer’s own risk.  
The license includes the right to use the IC in systems  
and/or end-user equipment.  
RATP/Innovatron  
Technology  
23.5 Trademarks  
Notice: All referenced brands, product names, service names and trademarks  
are the property of their respective owners.  
Applications — Applications that are described herein for any of these  
products are for illustrative purposes only. NXP Semiconductors makes no  
representation or warranty that such applications will be suitable for the  
specified use without further testing or modification.  
I2C-bus — logo is a trademark of NXP B.V.  
MIFARE — is a trademark of NXP B.V.  
Limiting values — Stress above one or more limiting values (as defined in  
the Absolute Maximum Ratings System of IEC 60134) may cause permanent  
damage to the device. Limiting values are stress ratings only and operation of  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
89 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
24. Contact information  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
90 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
25. Tables  
Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2  
Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3  
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5  
Table 4. Communication overview for  
Table 37. Status2Reg register (address 08h);  
reset value: 00h bit allocation . . . . . . . . . . . . . 41  
Table 38. Status2Reg register bit descriptions . . . . . . . . 41  
Table 39. FIFODataReg register (address 09h);  
ISO/IEC 14443 A/MIFARE reader/writer . . . . . .7  
reset value: xxh bit allocation . . . . . . . . . . . . . 42  
Table 5. Connection protocol for detecting different  
interface types . . . . . . . . . . . . . . . . . . . . . . . . . .8  
Table 40. FIFODataReg register bit descriptions . . . . . . 42  
Table 41. FIFOLevelReg register (address 0Ah);  
Table 6. MOSI and MISO byte order . . . . . . . . . . . . . . . .9  
Table 7. MOSI and MISO byte order . . . . . . . . . . . . . . .10  
Table 8. Address byte 0 register; address MOSI . . . . . .10  
Table 9. BR_T0 and BR_T1 settings . . . . . . . . . . . . . . .11  
Table 10. Selectable UART transfer speeds . . . . . . . . . .11  
Table 11. UART framing . . . . . . . . . . . . . . . . . . . . . . . . .12  
Table 12. Read data byte order . . . . . . . . . . . . . . . . . . . .12  
Table 13. Write data byte order . . . . . . . . . . . . . . . . . . . .13  
Table 14. Address byte 0 register; address MOSI . . . . . .15  
Table 15. Register and bit settings controlling the  
reset value: 00h bit allocation . . . . . . . . . . . . . 42  
Table 42. FIFOLevelReg register bit descriptions . . . . . . 42  
Table 43. WaterLevelReg register (address 0Bh);  
reset value: 08h bit allocation . . . . . . . . . . . . . 42  
Table 44. WaterLevelReg register bit descriptions . . . . . 43  
Table 45. ControlReg register (address 0Ch);  
reset value: 10h bit allocation . . . . . . . . . . . . . 43  
Table 46. ControlReg register bit descriptions . . . . . . . . 43  
Table 47. BitFramingReg register (address 0Dh);  
reset value: 00h bit allocation . . . . . . . . . . . . . 44  
signal on pin TX1 . . . . . . . . . . . . . . . . . . . . . . .23  
Table 16. Register and bit settings controlling the  
Table 48. BitFramingReg register bit descriptions . . . . . 44  
Table 49. CollReg register (address 0Eh); reset value:  
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 44  
signal on pin TX2 . . . . . . . . . . . . . . . . . . . . . . .24  
Table 17. CRC coprocessor parameters . . . . . . . . . . . . .27  
Table 18. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .29  
Table 19. Behavior of register bits and their designation .33  
Table 20. MFRC522 register overview . . . . . . . . . . . . . .34  
Table 21. Reserved register (address 00h); reset value:  
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .36  
Table 50. CollReg register bit descriptions . . . . . . . . . . . 44  
Table 51. Reserved register (address 0Fh); reset value:  
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 45  
Table 52. Reserved register bit descriptions . . . . . . . . . . 45  
Table 53. Reserved register (address 10h); reset value:  
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 45  
Table 22. Reserved register bit descriptions . . . . . . . . . .36  
Table 23. CommandReg register (address 01h); reset  
value: 20h bit allocation . . . . . . . . . . . . . . . . . .36  
Table 54. Reserved register bit descriptions . . . . . . . . . . 45  
Table 55. ModeReg register (address 11h); reset value:  
3Fh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 46  
Table 24. CommandReg register bit descriptions . . . . . .36  
Table 25. ComIEnReg register (address 02h); reset value:  
80h bit allocation . . . . . . . . . . . . . . . . . . . . . . .36  
Table 56. ModeReg register bit descriptions . . . . . . . . . . 46  
Table 57. TxModeReg register (address 12h); reset value:  
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 46  
Table 26. ComIEnReg register bit descriptions . . . . . . . .37  
Table 27. DivIEnReg register (address 03h); reset value:  
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .37  
Table 58. TxModeReg register bit descriptions . . . . . . . . 47  
Table 59. RxModeReg register (address 13h); reset value:  
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 47  
Table 28. DivIEnReg register bit descriptions . . . . . . . . .37  
Table 29. ComIrqReg register (address 04h); reset value:  
14h bit allocation . . . . . . . . . . . . . . . . . . . . . . .37  
Table 60. RxModeReg register bit descriptions . . . . . . . 47  
Table 61. TxControlReg register (address 14h);  
reset value: 80h bit allocation . . . . . . . . . . . . . 48  
Table 30. ComIrqReg register bit descriptions . . . . . . . .38  
Table 31. DivIrqReg register (address 05h); reset value: x0h  
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .38  
Table 62. TxControlReg register bit descriptions . . . . . . 48  
Table 63. TxASKReg register (address 15h); reset value:  
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 49  
Table 32. DivIrqReg register bit descriptions . . . . . . . . . .38  
Table 33. ErrorReg register (address 06h); reset value: 00h  
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .39  
Table 64. TxASKReg register bit descriptions . . . . . . . . 49  
Table 65. TxSelReg register (address 16h); reset value:  
10h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 49  
Table 34: ErrorReg register bit descriptions . . . . . . . . . .39  
Table 35. Status1Reg register (address 07h); reset value:  
21h bit allocation . . . . . . . . . . . . . . . . . . . . . . .40  
Table 66. TxSelReg register bit descriptions . . . . . . . . . 49  
Table 67. RxSelReg register (address 17h); reset value:  
84h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 50  
Table 36. Status1Reg register bit descriptions . . . . . . . .40  
Table 68. RxSelReg register bit descriptions . . . . . . . . . 50  
continued >>  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
91 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 69. RxThresholdReg register (address 18h); reset  
value: 84h bit allocation . . . . . . . . . . . . . . . . . .51  
Table 70. RxThresholdReg register bit descriptions . . . .51  
Table 71. DemodReg register (address 19h); reset value:  
4Dh bit allocation . . . . . . . . . . . . . . . . . . . . . . .51  
Table 72. DemodReg register bit descriptions . . . . . . . . .51  
Table 73. Reserved register (address 1Ah); reset value:  
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .52  
Table 74. Reserved register bit descriptions . . . . . . . . . .52  
Table 75. Reserved register (address 1Bh); reset value:  
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .52  
Table 76. Reserved register bit descriptions . . . . . . . . . .52  
Table 77. MfTxReg register (address 1Ch); reset value:  
62h bit allocation . . . . . . . . . . . . . . . . . . . . . . .52  
Table 78. MfTxReg register bit descriptions . . . . . . . . . .52  
Table 79. MfRxReg register (address 1Dh); reset value:  
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .53  
Table 80. MfRxReg register bit descriptions . . . . . . . . . .53  
Table 81. Reserved register (address 1Eh); reset value:  
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .53  
Table 82. Reserved register bit descriptions . . . . . . . . . .53  
Table 83. SerialSpeedReg register (address 1Fh); reset  
value: EBh bit allocation . . . . . . . . . . . . . . . . .53  
Table 84. SerialSpeedReg register bit descriptions . . . .53  
Table 85. Reserved register (address 20h); reset value:  
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .54  
Table 86. Reserved register bit descriptions . . . . . . . . . .54  
Table 87. CRCResultReg (higher bits) register (address  
21h); reset value: FFh bit allocation . . . . . . . . .54  
Table 88. CRCResultReg register higher bit descriptions . .  
54  
Table 102.CWGsPReg register bit descriptions . . . . . . . . 57  
Table 103.ModGsPReg register (address 29h);  
reset value: 20h bit allocation . . . . . . . . . . . . . 57  
Table 104.ModGsPReg register bit descriptions . . . . . . . 57  
Table 105.TModeReg register (address 2Ah); reset value:  
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 57  
Table 106.TModeReg register bit descriptions . . . . . . . . 58  
Table 107.TPrescalerReg register (address 2Bh); reset  
value: 00h bit allocation . . . . . . . . . . . . . . . . . . 58  
Table 108.TPrescalerReg register bit descriptions . . . . . 58  
Table 109.TReloadReg (higher bits) register (address  
2Ch); reset value: 00h bit allocation . . . . . . . . 59  
Table 110.TReloadReg register higher bit descriptions . . 59  
Table 111.TReloadReg (lower bits) register (address 2Dh);  
reset value: 00h bit allocation . . . . . . . . . . . . . 59  
Table 112.TReloadReg register lower bit descriptions . . 59  
Table 113.TCounterValReg (higher bits) register  
(address 2Eh); reset value: xxh bit allocation . 59  
Table 114.TCounterValReg register higher bit descriptions .  
59  
Table 115.TCounterValReg (lower bits) register (address  
2Fh); reset value: xxh bit allocation . . . . . . . . . 59  
Table 116.TCounterValReg register lower bit  
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 60  
Table 117.Reserved register (address 30h); reset value:  
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 60  
Table 118.Reserved register bit descriptions . . . . . . . . . . 60  
Table 119.TestSel1Reg register (address 31h);  
reset value: 00h bit allocation . . . . . . . . . . . . . 60  
Table 120.TestSel1Reg register bit descriptions . . . . . . . 60  
Table 121.TestSel2Reg register (address 32h);  
Table 89. CRCResultReg (lower bits) register (address  
22h); reset value: FFh bit allocation . . . . . . . . .54  
Table 90. CRCResultReg register lower bit descriptions .54  
Table 91. Reserved register (address 23h); reset value:  
88h bit allocation . . . . . . . . . . . . . . . . . . . . . . .55  
Table 92. Reserved register bit descriptions . . . . . . . . . .55  
Table 93. ModWidthReg register (address 24h);  
reset value: 26h bit allocation . . . . . . . . . . . . .55  
Table 94. ModWidthReg register bit descriptions . . . . . .55  
Table 95. Reserved register (address 25h); reset value:  
87h bit allocation . . . . . . . . . . . . . . . . . . . . . . .55  
Table 96. Reserved register bit descriptions . . . . . . . . . .55  
Table 97. RFCfgReg register (address 26h); reset value:  
48h bit allocation . . . . . . . . . . . . . . . . . . . . . . .56  
Table 98. RFCfgReg register bit descriptions . . . . . . . . .56  
Table 99. GsNReg register (address 27h); reset value:  
88h bit allocation . . . . . . . . . . . . . . . . . . . . . . .56  
Table 100.GsNReg register bit descriptions . . . . . . . . . . .56  
Table 101.CWGsPReg register (address 28h); reset value:  
20h bit allocation . . . . . . . . . . . . . . . . . . . . . . .57  
reset value: 00h bit allocation . . . . . . . . . . . . . 60  
Table 122.TestSel2Reg register bit descriptions . . . . . . . 61  
Table 123.TestPinEnReg register (address 33h);  
reset value: 80h bit allocation . . . . . . . . . . . . . 61  
Table 124.TestPinEnReg register bit descriptions . . . . . . 61  
Table 125.TestPinValueReg register (address 34h);  
reset value: 00h bit allocation . . . . . . . . . . . . . 61  
Table 126.TestPinValueReg register bit descriptions . . . . 62  
Table 127.TestBusReg register (address 35h); reset value:  
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 62  
Table 128.TestBusReg register bit descriptions . . . . . . . . 62  
Table 129.AutoTestReg register (address 36h);  
reset value: 40h bit allocation . . . . . . . . . . . . . 62  
Table 130.AutoTestReg register bit descriptions . . . . . . . 63  
Table 131.VersionReg register (address 37h); reset value:  
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 63  
Table 132.VersionReg register bit descriptions . . . . . . . . 63  
Table 133.AnalogTestReg register (address 38h); reset  
value: 00h bit allocation . . . . . . . . . . . . . . . . . . 63  
Table 134.AnalogTestReg register bit descriptions . . . . . 64  
continued >>  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
92 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
Table 135.TestDAC1Reg register (address 39h);  
reset value: xxh bit allocation . . . . . . . . . . . . . .65  
Table 136.TestDAC1Reg register bit descriptions . . . . . .65  
Table 137.TestDAC2Reg register (address 3Ah);  
reset value: xxh bit allocation . . . . . . . . . . . . . .65  
Table 138.TestDAC2Reg register bit descriptions . . . . . .65  
Table 139.TestADCReg register (address 3Bh);  
reset value: xxh bit allocation . . . . . . . . . . . . . .65  
Table 140.TestADCReg register bit descriptions . . . . . . .65  
Table 141.Reserved register (address 3Ch); reset value:  
FFh bit allocation . . . . . . . . . . . . . . . . . . . . . . .66  
Table 142.Reserved register bit descriptions . . . . . . . . . .66  
Table 143.Reserved register (address 3Dh); reset value:  
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .66  
Table 144.Reserved register bit descriptions . . . . . . . . . .66  
Table 145.Reserved register (address 3Eh); reset value:  
03h bit allocation . . . . . . . . . . . . . . . . . . . . . . .66  
Table 146.Reserved register bit descriptions . . . . . . . . . .66  
Table 147.Reserved register (address 3Fh); reset value:  
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .66  
Table 148.Reserved register bit descriptions . . . . . . . . . .66  
Table 149.Command overview . . . . . . . . . . . . . . . . . . . . .67  
Table 150.Limiting values . . . . . . . . . . . . . . . . . . . . . . . . .71  
Table 151.Operating conditions . . . . . . . . . . . . . . . . . . . .71  
Table 152.Thermal characteristics . . . . . . . . . . . . . . . . . .71  
Table 153.Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .72  
Table 154.SPI timing characteristics . . . . . . . . . . . . . . . .75  
Table 155.I2C-bus timing in Fast mode . . . . . . . . . . . . . . .76  
Table 156.Test bus signals: TestBusSel[4:0] = 07h . . . . .80  
Table 157.Test bus signals: TestBusSel[4:0] = 0Dh . . . . .80  
Table 158.Test signal descriptions . . . . . . . . . . . . . . . . . .80  
Table 159.Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .87  
Table 160.Revision history . . . . . . . . . . . . . . . . . . . . . . . .88  
continued >>  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
93 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
26. Figures  
Fig 1. Simplified block diagram of the MFRC522. . . . . . .3  
Fig 2. Detailed block diagram of the MFRC522 . . . . . . . .4  
Fig 3. Pinning configuration HVQFN32 (SOT617-1) . . . .5  
Fig 4. MFRC522 Read/Write mode . . . . . . . . . . . . . . . . .7  
Fig 5. ISO/IEC 14443 A/MIFARE Read/Write mode  
communication diagram. . . . . . . . . . . . . . . . . . . . .7  
Fig 6. Data coding and framing according to  
ISO/IEC 14443 A . . . . . . . . . . . . . . . . . . . . . . . . . .8  
Fig 7. SPI connection to host. . . . . . . . . . . . . . . . . . . . . .9  
Fig 8. UART connection to microcontrollers. . . . . . . . . .10  
Fig 9. UART read data timing diagram. . . . . . . . . . . . . .12  
Fig 10. UART write data timing diagram . . . . . . . . . . . . .14  
Fig 11. I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . .15  
Fig 12. Bit transfer on the I2C-bus . . . . . . . . . . . . . . . . . .16  
Fig 13. START and STOP conditions. . . . . . . . . . . . . . . .16  
Fig 14. Acknowledge on the I2C-bus . . . . . . . . . . . . . . . .17  
Fig 15. Data transfer on the I2C-bus . . . . . . . . . . . . . . . .17  
Fig 16. First byte following the START procedure . . . . . .18  
Fig 17. Register read and write access . . . . . . . . . . . . . .19  
Fig 18. I2C-bus HS mode protocol switch . . . . . . . . . . . .20  
Fig 19. I2C-bus HS mode protocol frame. . . . . . . . . . . . .21  
Fig 20. Serial data switch for p-driver TX1 and TX2 . . . .25  
Fig 21. Overview of MFIN and MFOUT signal routing. . .26  
Fig 22. Quartz crystal connection . . . . . . . . . . . . . . . . . .31  
Fig 23. Oscillator start-up time. . . . . . . . . . . . . . . . . . . . .32  
Fig 24. Pin RX input voltage range . . . . . . . . . . . . . . . . .75  
Fig 25. Timing diagram for SPI . . . . . . . . . . . . . . . . . . . .76  
Fig 26. Timing for Fast and Standard mode devices  
on the I2C-bus . . . . . . . . . . . . . . . . . . . . . . . . . . .77  
Fig 27. Typical application diagram . . . . . . . . . . . . . . . . .78  
Fig 28. Output test signals TestDAC1 on pin AUX1 and  
TestDAC2 on pin AUX2 . . . . . . . . . . . . . . . . . . . .81  
Fig 29. Output test signals Corr1 on pin AUX1 and  
MinLevel on pin AUX2 . . . . . . . . . . . . . . . . . . . . .82  
Fig 30. Output ADC channel I on pin AUX1 and ADC  
channel Q on pin AUX2 . . . . . . . . . . . . . . . . . . . .82  
Fig 31. Output RxActive on pin AUX1 and TxActive  
on pin AUX2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .83  
Fig 32. Received data stream on pins AUX1 and AUX2 .84  
Fig 33. Package outline SOT617-1 (HVQFN32) . . . . . . .85  
Fig 34. Packing information 1 tray . . . . . . . . . . . . . . . . . .86  
continued >>  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
94 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
27. Contents  
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
9.1  
9.2  
9.3  
9.3.1  
9.3.1.1  
9.3.1.2  
9.3.1.3  
9.3.1.4  
9.3.1.5  
9.3.1.6  
9.3.1.7  
9.3.1.8  
9.3.1.9  
Register bit behavior . . . . . . . . . . . . . . . . . . . 33  
Register overview. . . . . . . . . . . . . . . . . . . . . . 34  
Register descriptions . . . . . . . . . . . . . . . . . . . 36  
Page 0: Command and status . . . . . . . . . . . . 36  
Reserved register 00h . . . . . . . . . . . . . . . . . . 36  
CommandReg register. . . . . . . . . . . . . . . . . . 36  
ComIEnReg register. . . . . . . . . . . . . . . . . . . . 36  
DivIEnReg register. . . . . . . . . . . . . . . . . . . . . 37  
ComIrqReg register . . . . . . . . . . . . . . . . . . . . 37  
DivIrqReg register . . . . . . . . . . . . . . . . . . . . . 38  
ErrorReg register . . . . . . . . . . . . . . . . . . . . . . 39  
Status1Reg register . . . . . . . . . . . . . . . . . . . . 40  
Status2Reg register . . . . . . . . . . . . . . . . . . . . 41  
2
General description . . . . . . . . . . . . . . . . . . . . . . 1  
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1  
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2  
Ordering information. . . . . . . . . . . . . . . . . . . . . 3  
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3  
Pinning information. . . . . . . . . . . . . . . . . . . . . . 5  
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5  
3
4
5
6
7
7.1  
8
8.1  
8.1.1  
8.1.2  
Functional description . . . . . . . . . . . . . . . . . . . 7  
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . 8  
Automatic microcontroller interface detection. . 8  
Serial Peripheral Interface . . . . . . . . . . . . . . . . 9  
SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . . 9  
SPI write data . . . . . . . . . . . . . . . . . . . . . . . . . 10  
SPI address byte . . . . . . . . . . . . . . . . . . . . . . 10  
UART interface . . . . . . . . . . . . . . . . . . . . . . . . 10  
Connection to a host. . . . . . . . . . . . . . . . . . . . 10  
Selectable UART transfer speeds. . . . . . . . . . 11  
UART framing . . . . . . . . . . . . . . . . . . . . . . . . . 12  
I2C-bus interface. . . . . . . . . . . . . . . . . . . . . . . 15  
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
START and STOP conditions . . . . . . . . . . . . . 16  
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . 16  
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 17  
7-Bit addressing . . . . . . . . . . . . . . . . . . . . . . . 18  
Register write access . . . . . . . . . . . . . . . . . . . 18  
Register read access . . . . . . . . . . . . . . . . . . . 19  
High-speed mode . . . . . . . . . . . . . . . . . . . . . . 20  
High-speed transfer . . . . . . . . . . . . . . . . . . . . 20  
9.3.1.10 FIFODataReg register . . . . . . . . . . . . . . . . . . 42  
9.3.1.11 FIFOLevelReg register. . . . . . . . . . . . . . . . . . 42  
9.3.1.12 WaterLevelReg register . . . . . . . . . . . . . . . . . 42  
9.3.1.13 ControlReg register . . . . . . . . . . . . . . . . . . . . 43  
9.3.1.14 BitFramingReg register . . . . . . . . . . . . . . . . . 44  
9.3.1.15 CollReg register . . . . . . . . . . . . . . . . . . . . . . . 44  
9.3.1.16 Reserved register 0Fh . . . . . . . . . . . . . . . . . . 45  
8.1.2.1  
8.1.2.2  
8.1.2.3  
8.1.3  
8.1.3.1  
8.1.3.2  
8.1.3.3  
8.1.4  
8.1.4.1  
8.1.4.2  
8.1.4.3  
8.1.4.4  
8.1.4.5  
8.1.4.6  
8.1.4.7  
8.1.4.8  
8.1.4.9  
9.3.2  
Page 1: Communication. . . . . . . . . . . . . . . . . 45  
Reserved register 10h . . . . . . . . . . . . . . . . . . 45  
ModeReg register. . . . . . . . . . . . . . . . . . . . . . 46  
TxModeReg register. . . . . . . . . . . . . . . . . . . . 46  
RxModeReg register . . . . . . . . . . . . . . . . . . . 47  
TxControlReg register . . . . . . . . . . . . . . . . . . 48  
TxASKReg register . . . . . . . . . . . . . . . . . . . . 49  
TxSelReg register . . . . . . . . . . . . . . . . . . . . . 49  
RxSelReg register . . . . . . . . . . . . . . . . . . . . . 50  
RxThresholdReg register . . . . . . . . . . . . . . . . 51  
9.3.2.1  
9.3.2.2  
9.3.2.3  
9.3.2.4  
9.3.2.5  
9.3.2.6  
9.3.2.7  
9.3.2.8  
9.3.2.9  
9.3.2.10 DemodReg register . . . . . . . . . . . . . . . . . . . . 51  
9.3.2.11 Reserved register 1Ah . . . . . . . . . . . . . . . . . . 51  
9.3.2.12 Reserved register 1Bh . . . . . . . . . . . . . . . . . . 52  
9.3.2.13 MfTxReg register . . . . . . . . . . . . . . . . . . . . . . 52  
9.3.2.14 MfRxReg register . . . . . . . . . . . . . . . . . . . . . . 53  
9.3.2.15 Reserved register 1Eh . . . . . . . . . . . . . . . . . . 53  
9.3.2.16 SerialSpeedReg register . . . . . . . . . . . . . . . . 53  
8.1.4.10 Serial data transfer format in HS mode . . . . . 20  
8.1.4.11 Switching between F/S mode and HS mode . 22  
8.1.4.12 MFRC522 at lower speed modes . . . . . . . . . . 22  
8.2  
Analog interface and contactless UART . . . . . 23  
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
TX p-driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 23  
Serial data switch . . . . . . . . . . . . . . . . . . . . . . 25  
MFIN and MFOUT interface support . . . . . . . 25  
CRC coprocessor . . . . . . . . . . . . . . . . . . . . . . 27  
FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 27  
Accessing the FIFO buffer . . . . . . . . . . . . . . . 27  
Controlling the FIFO buffer . . . . . . . . . . . . . . . 27  
FIFO buffer status information . . . . . . . . . . . . 27  
Interrupt request system. . . . . . . . . . . . . . . . . 28  
Inerrupt sources overview. . . . . . . . . . . . . . . . 28  
Timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29  
Power reduction modes . . . . . . . . . . . . . . . . . 31  
Hard power-down . . . . . . . . . . . . . . . . . . . . . . 31  
Soft power-down mode. . . . . . . . . . . . . . . . . . 31  
Transmitter power-down mode . . . . . . . . . . . . 31  
Oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . 31  
Reset and oscillator start-up time. . . . . . . . . . 32  
Reset timing requirements . . . . . . . . . . . . . . . 32  
Oscillator start-up time . . . . . . . . . . . . . . . . . . 32  
8.2.1  
8.2.2  
8.2.3  
8.2.4  
8.2.5  
8.3  
8.3.1  
8.3.2  
8.3.3  
8.4  
8.4.1  
8.5  
8.6  
8.6.1  
8.6.2  
8.6.3  
8.7  
9.3.3  
Page 2: Configuration. . . . . . . . . . . . . . . . . . . 54  
Reserved register 20h . . . . . . . . . . . . . . . . . . 54  
CRCResultReg registers . . . . . . . . . . . . . . . . 54  
Reserved register 23h . . . . . . . . . . . . . . . . . . 55  
ModWidthReg register . . . . . . . . . . . . . . . . . . 55  
Reserved register 25h . . . . . . . . . . . . . . . . . . 55  
RFCfgReg register . . . . . . . . . . . . . . . . . . . . . 56  
GsNReg register . . . . . . . . . . . . . . . . . . . . . . 56  
CWGsPReg register. . . . . . . . . . . . . . . . . . . . 57  
ModGsPReg register . . . . . . . . . . . . . . . . . . . 57  
9.3.3.1  
9.3.3.2  
9.3.3.3  
9.3.3.4  
9.3.3.5  
9.3.3.6  
9.3.3.7  
9.3.3.8  
9.3.3.9  
9.3.3.10 TModeReg and TPrescalerReg registers. . . . 57  
9.3.3.11 TReloadReg register . . . . . . . . . . . . . . . . . . . 58  
9.3.3.12 TCounterValReg register . . . . . . . . . . . . . . . . 59  
9.3.4  
Page 3: Test . . . . . . . . . . . . . . . . . . . . . . . . . . 60  
Reserved register 30h . . . . . . . . . . . . . . . . . . 60  
TestSel1Reg register . . . . . . . . . . . . . . . . . . . 60  
TestSel2Reg register . . . . . . . . . . . . . . . . . . . 60  
TestPinEnReg register . . . . . . . . . . . . . . . . . . 61  
TestPinValueReg register. . . . . . . . . . . . . . . . 61  
9.3.4.1  
9.3.4.2  
9.3.4.3  
9.3.4.4  
9.3.4.5  
8.8  
8.8.1  
8.8.2  
9
MFRC522 registers . . . . . . . . . . . . . . . . . . . . . 33  
MFRC522_33  
© NXP B.V. 2009. All rights reserved.  
Product data sheet  
PUBLIC  
Rev. 3 — 26 October 2009  
112133  
95 of 96  
MFRC522  
NXP Semiconductors  
Contactless reader IC  
9.3.4.6  
9.3.4.7  
9.3.4.8  
9.3.4.9  
TestBusReg register . . . . . . . . . . . . . . . . . . . . 62  
21  
22  
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 87  
Revision history . . . . . . . . . . . . . . . . . . . . . . . 88  
AutoTestReg register . . . . . . . . . . . . . . . . . . . 62  
VersionReg register . . . . . . . . . . . . . . . . . . . . 63  
AnalogTestReg register . . . . . . . . . . . . . . . . . 63  
23  
Legal information . . . . . . . . . . . . . . . . . . . . . . 89  
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 89  
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 89  
Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 89  
Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89  
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 89  
23.1  
23.2  
23.3  
23.4  
23.5  
9.3.4.10 TestDAC1Reg register . . . . . . . . . . . . . . . . . . 65  
9.3.4.11 TestDAC2Reg register . . . . . . . . . . . . . . . . . . 65  
9.3.4.12 TestADCReg register . . . . . . . . . . . . . . . . . . . 65  
9.3.4.13 Reserved register 3Ch . . . . . . . . . . . . . . . . . . 65  
10  
MFRC522 command set . . . . . . . . . . . . . . . . . 67  
General description. . . . . . . . . . . . . . . . . . . . . 67  
General behavior . . . . . . . . . . . . . . . . . . . . . . 67  
MFRC522 command overview . . . . . . . . . . . . 67  
MFRC522 command descriptions . . . . . . . . . 68  
24  
25  
26  
27  
Contact information . . . . . . . . . . . . . . . . . . . . 90  
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91  
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94  
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95  
10.1  
10.2  
10.3  
10.3.1  
10.3.1.1 Idle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68  
10.3.1.2 Mem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68  
10.3.1.3 Generate RandomID. . . . . . . . . . . . . . . . . . . . 68  
10.3.1.4 CalcCRC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68  
10.3.1.5 Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68  
10.3.1.6 NoCmdChange. . . . . . . . . . . . . . . . . . . . . . . . 68  
10.3.1.7 Receive. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69  
10.3.1.8 Transceive. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69  
10.3.1.9 MFAuthent. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69  
10.3.1.10 SoftReset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70  
11  
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 71  
Recommended operating conditions. . . . . . . 71  
Thermal characteristics. . . . . . . . . . . . . . . . . . 71  
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 72  
Timing characteristics. . . . . . . . . . . . . . . . . . . 75  
Application information. . . . . . . . . . . . . . . . . . 78  
12  
13  
14  
14.1  
15  
16  
16.1  
16.1.1  
16.1.2  
16.1.3  
Test information. . . . . . . . . . . . . . . . . . . . . . . . 79  
Test signals. . . . . . . . . . . . . . . . . . . . . . . . . . . 79  
Self test. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79  
Test bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79  
Test signals on pins AUX1 or AUX2 . . . . . . . . 80  
16.1.3.1 Example: Output test signals TestDAC1 and  
TestDAC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81  
16.1.3.2 Example: Output test signals Corr1 and MinLevel  
81  
16.1.3.3 Example: Output test signals ADC channel I and  
ADC channel Q. . . . . . . . . . . . . . . . . . . . . . . . 82  
16.1.3.4 Example: Output test signals RxActive and  
TxActive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83  
16.1.3.5 Example: Output test signal RX data stream . 84  
16.1.3.6 PRBS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84  
17  
18  
19  
20  
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 85  
Handling information. . . . . . . . . . . . . . . . . . . . 86  
Packing information. . . . . . . . . . . . . . . . . . . . . 86  
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 87  
Please be aware that important notices concerning this document and the product(s)  
described herein, have been included in section ‘Legal information’.  
© NXP B.V. 2009.  
All rights reserved.  
For more information, please visit: http://www.nxp.com  
For sales office addresses, please send an email to: salesaddresses@nxp.com  
Date of release: 26 October 2009  
112133  
Document identifier: MFRC522_33  

相关型号:

SI9130DB

5- and 3.3-V Step-Down Synchronous Converters

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1

SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135LG-T1-E3

SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9135_11

SMBus Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9136_11

Multi-Output Power-Supply Controller

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130CG-T1-E3

Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130LG-T1-E3

Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9130_11

Pin-Programmable Dual Controller - Portable PCs

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137

Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137DB

Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9137LG

Multi-Output, Sequence Selectable Power-Supply Controller for Mobile Applications

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY

SI9122E

500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification Drivers

Warning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY