MFRC52302HN1/TRAYB [NXP]
SPECIALTY TELECOM CIRCUIT, PQCC32, 5 X 5 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT617-1, HVQFN-32;![MFRC52302HN1/TRAYB](http://pdffile.icpdf.com/pdf2/p00238/img/icpdf/MFRC52302HN1_1393689_icpdf.jpg)
型号: | MFRC52302HN1/TRAYB |
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描述: | SPECIALTY TELECOM CIRCUIT, PQCC32, 5 X 5 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT617-1, HVQFN-32 电信 电信集成电路 |
文件: | 总98页 (文件大小:851K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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MFRC523
Contactless reader IC
Rev. 3.7 — 8 November 2011
115237
Product data sheet
COMPANY PUBLIC
1. Introduction
This document describes the functionality and electrical specifications of the contactless
reader/writer MFRC523.
Remark: The MFRC523 supports all variants of the MIFARE Mini, MIFARE 1K and
MIFARE 4K RF identification protocols. To aid readability throughout this data sheet, the
MIFARE Mini, MIFARE 1K and MIFARE 4K products and protocols have the generic
name MIFARE.
2. General description
The MFRC523 is a highly integrated reader/writer for contactless communication at
13.56 MHz. The MFRC523 reader supports ISO/IEC 14443 A/MIFARE mode.
The MFRC523’s internal transmitter is able to drive a reader/writer antenna designed to
communicate with ISO/IEC 14443 A/MIFARE cards and transponders without additional
active circuitry. The receiver module provides a robust and efficient implementation for
demodulating and decoding signals from ISO/IEC 14443 A/MIFARE compatible cards and
transponders. The digital module manages the complete ISO/IEC 14443 A framing and
error detection (parity and CRC) functionality.
All protocol layers of the ISO/IEC 14443 A and ISO/IEC 14443 B communication
standards are supported provided:
• additional components, such as the oscillator, power supply, coil etc are correctly
applied
• standardized protocols, such as ISO/IEC 14443-4 and/or ISO/IEC 14443 B
anticollision are correctly implemented
Using this NXP Semiconductors’ device according to ISO/IEC 14443 B may infringe third
party patent rights.
The MFRC523 supports contactless communication using MIFARE higher baud rates
(see Section 8.3.4.11 on page 22) at transfer speeds up to 848 kBd in both directions.
The following host interfaces are provided:
• Serial Peripheral Interface (SPI)
• Serial UART (similar to RS232 with voltage levels dependent on pin voltage supply)
• I2C-bus interface
MFRC523
NXP Semiconductors
Contactless reader IC
3. Features and benefits
Highly integrated analog circuitry to demodulate and decode responses
Buffered output drivers for connecting an antenna with the minimum number of
external components
Supports ISO/IEC 14443 A/MIFARE
Supports ISO/IEC 14443 B Read/Write modes
Typical operating distance in Read/Write mode up to 50 mm depending on the
antenna size and tuning
Supports MIFARE Mini, MIFARE 1K and MIFARE 4K encryption in Read/Write mode
Supports ISO/IEC 14443 A higher transfer speed communication at 212 kBd, 424 kBd
and 848 kBd
Supports MFIN/MFOUT
Additional internal power supply to the smart card IC connected via MFIN/MFOUT
Supported host interfaces
SPI up to 10 Mbit/s
I2C-bus interface up to 400 kBd in Fast mode, up to 3400 kBd in High-speed mode
RS232 Serial UART up to 1228.8 kBd, with voltage levels dependant on pin
voltage supply
FIFO buffer handles 64 byte send and receive
Flexible interrupt modes
Hard reset with low power function
Power-down by software mode
Programmable timer
Internal oscillator for connection to 27.12 MHz quartz crystal
2.5 V to 3.3 V power supply
CRC coprocessor
Programmable I/O pins
Internal self-test
4. Quick reference data
Table 1.
Quick reference data
Symbol Parameter
Conditions
Min
2.5
2.5
2.5
1.6
1.6
Typ
3.3
3.3
3.3
1.8
-
Max
3.6
3.6
3.6
3.6
3.6
Unit
V
[1][2]
[3]
VDDA
VDDD
analog supply voltage
digital supply voltage
VDD(PVDD) VDDA = VDDD = VDD(TVDD);
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V
V
VDD(TVDD) TVDD supply voltage
VDD(PVDD) PVDD supply voltage
VDD(SVDD) SVDD supply voltage
V
V
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V
VDDA = VDDD = VDD(TVDD) = VDD(PVDD) = 3 V
hard power-down; pin NRSTPD set LOW
soft power-down; RF level detector on
pin DVDD; VDDD = 3 V
V
Ipd
power-down current
[4]
[4]
-
-
-
-
5
A
A
mA
-
10
9
IDDD
digital supply current
6.5
MFRC523
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
2 of 98
MFRC523
NXP Semiconductors
Contactless reader IC
Table 1.
Quick reference data …continued
Symbol Parameter
Conditions
Min
Typ
Max
Unit
IDDA
analog supply current
pin AVDD; VDDA = 3 V, CommandReg register’s
RcvOff bit = 0
-
7
10
mA
pin AVDD; receiver switched off; VDDA = 3 V,
CommandReg register’s RcvOff bit = 1
-
3
5
mA
[5]
IDD(PVDD) PVDD supply current
IDD(TVDD) TVDD supply current
pin PVDD
-
-
40
mA
mA
C
[6][7][8]
pin TVDD; continuous wave
HVQFN32
-
60
-
100
+85
Tamb
ambient temperature
25
[1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance.
[2] VDDA, VDDD and VDD(TVDD) must always be the same voltage.
[3] VDD(PVDD) must always be the same or lower voltage than VDDD
.
[4] Ipd is the total current for all supplies.
[5] IDD(PVDD) depends on the overall load at the digital pins.
[6] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2.
[7] During typical circuit operation, the overall current is below 100 mA.
[8] Typical value using a complementary driver configuration and an antenna matched to 40 between pins TX1 and TX2 at 13.56 MHz.
5. Ordering information
Table 2.
Ordering information
Type number
Package
Name
Description
Version
MFRC52302HN1/TRAYB[1]
HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;
SOT617-1
32 terminal; body 5 5 0.85 mm
MFRC52302HN1/TRAYBM[2] HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;
SOT617-1
32 terminal; body 5 5 0.85 mm
[1] Delivered in one tray.
[2] Delivered in five trays.
MFRC523
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© NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
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MFRC523
NXP Semiconductors
Contactless reader IC
6. Block diagram
The analog interface manages the modulation and demodulation of the analog signals.
The contactless UART manages the protocol requirements for the communication
protocols in cooperation with the host. The FIFO buffer ensures fast and convenient data
transfers to/from the host and the contactless UART.
Various host interfaces are implemented to meet different customer requirements.
REGISTER BANK
ANALOG
INTERFACE
CONTACTLESS
UART
ANTENNA
FIFO
BUFFER
SERIAL UART
SPI
I C-BUS
HOST
2
001aaj627
Fig 1. Simplified block diagram of the MFRC523
MFRC523
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© NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
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MFRC523
NXP Semiconductors
Contactless reader IC
D6/ADR_0/
MOSI/MX
D2/ADR_4
D1/ADR_5 D3/ADR_3
25 26 27
D4/ADR_2
D5/ADR_1/
D7/SCL/
SDA/NSS/RX EA I2C
24 32
PVDD PVSS
SCK/DTRQ
MISO/TX
1
28
29
30
31
2
5
3
DVDD
VOLTAGE
MONITOR
AND
POWER ON
DETECT
4
DVSS
2
SPI, UART, I C-BUS INTERFACE CONTROL
15
18
AVDD
AVSS
FIFO CONTROL
STATE MACHINE
64-BYTE FIFO
BUFFER
RESET
CONTROL
COMMAND REGISTER
PROGRAMABLE TIMER
INTERRUPT CONTROL
CRC16
6
POWER-DOWN
CONTROL
NRSTPD
IRQ
CONTROL REGISTER
BANK
23
MIFARE CLASSIC UNIT
GENERATION AND CHECK
RANDOM NUMBER
GENERATOR
PARALLEL/SERIAL
CONVERTER
BIT COUNTER
PARITY GENERATION AND CHECK
FRAME GENERATION AND CHECK
BIT DECODING
BIT ENCODING
7
8
9
MFIN
SERIAL DATA SWITCH
MFOUT
SVDD
21
22
CLOCK
OSCIN
GENERATION,
FILTERING AND
DISTRIBUTION
AMPLITUDE
RATING
OSCILLATOR
ANALOG TO DIGITAL
CONVERTER
OSCOUT
REFERENCE
VOLTAGE
Q-CLOCK
GENERATION
TEMPERATURE
SENSOR
ANALOG TEST
MULTIPLEXOR
AND
DIGITAL TO
ANALOG
I-CHANNEL
AMPLIFIER
Q-CHANNEL
AMPLIFIER
TRANSMITTER CONTROL
I-CHANNEL
DEMODULATOR
Q-CHANNEL
DEMODULATOR
CONVERTER
16
19
20
17
RX
10, 14
TVSS
11
TX1
13
TX2
12
VMID AUX1 AUX2
TVDD
001aak602
Fig 2. Detailed block diagram of the MFRC523
MFRC523
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© NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
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MFRC523
NXP Semiconductors
Contactless reader IC
7. Pinning information
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
I2C
PVDD
SDA/NSS/RX
IRQ
DVDD
OSCOUT
OSCIN
AUX2
AUX1
AVSS
RX
DVSS
MFRC523
PVSS
NRSTPD
MFIN
MFOUT
001aal155
Transparent top view
Fig 3. Pinning configuration HVQFN32 (SOT617-1)
7.1 Pin description
Table 3.
Pin description
Pin
1
Symbol
I2C
Type[1] Description
I[2]
I2C-bus enable input
2
PVDD
DVDD
DVSS
PVSS
NRSTPD
P
pin power supply
3
P
digital power supply
4
G[3]
G
I
digital ground
5
pin power supply ground
reset and power-down input:
reset: enabled by a positive edge
6
power-down: enabled when LOW; internal current sinks are switched off, the oscillator
is inhibited and the input pins are disconnected from the outside world
7
MFIN
MFOUT
SVDD
TVSS
TX1
I
MIFARE signal input
8
O
P
G
O
P
O
G
P
MIFARE signal output
9
MFIN and MFOUT pin power supply
transmitter output stage 1 ground
10
11
12
13
14
15
transmitter 1 modulated 13.56 MHz energy carrier output
transmitter power supply: supplies the output stage of transmitters 1 and 2
transmitter 2 modulated 13.56 MHz energy carrier output
transmitter output stage 2 ground
TVDD
TX2
TVSS
AVDD
analog power supply
MFRC523
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© NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
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MFRC523
NXP Semiconductors
Contactless reader IC
Table 3.
Pin
16
Pin description …continued
Symbol
VMID
RX
Type[1] Description
P
I
internal reference voltage
17
RF signal input
18
AVSS
AUX1
AUX2
OSCIN
G
O
O
I
analog ground
19
auxiliary outputs for test purposes
auxiliary outputs for test purposes
20
21
crystal oscillator inverting amplifier input; also the input for an externally generated clock
(fclk = 27.12 MHz)
22
23
24
OSCOUT
IRQ
SDA[2]
NSS[2]
RX[2]
O
crystal oscillator inverting amplifier output
interrupt request output: indicates an interrupt event
I2C-bus serial data line input/output
SPI signal input
O
I/O
I
I
UART address input
25
26
27
28
29
D1[2]
ADR_5[2]
I/O
I/O
I/O
I
test port
I2C-bus address 5 input
D2
test port
ADR_4[2]
D3
ADR_3[2]
I2C-bus address 4 input
test port
I2C-bus address 3 input
I/O
I
D4
I/O
I
test port
ADR_2[2]
D5
ADR_1[2]
SCK[2]
DTRQ[2]
D6
ADR_0[2]
MOSI[2]
MX[2]
I2C-bus address 2 input
test port
I2C-bus address 1 input
I/O
I
I
SPI serial clock input
O
UART request to send output to microcontroller
test port
I2C-bus address 0 input
SPI master out, slave in
UART output to microcontroller
test port
I2C-bus clock input/output
SPI master in, slave out
UART data output to microcontroller
external address input for coding I2C-bus address
30
31
32
I/O
I
I/O
O
D7
I/O
I/O
I/O
O
SCL[2]
MISO[2]
TX[2]
EA[2]
I
[1] Pin types: I = Input, O = Output, I/O = Input/Output, P = Power and G = Ground.
[2] The pin functionality of these pins is explained in Section 8.3 “Digital interfaces”.
[3] Connection of heatsink pad on package underside is not necessary. Optional connection to pin DVSS is possible.
MFRC523
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© NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
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MFRC523
NXP Semiconductors
Contactless reader IC
8. Functional description
The MFRC523 transmission module supports ISO/IEC 14443 A and ISO/IEC 14443 B
Read/Write mode at various transfer speeds and modulation protocols.
BATTERY
MFRC523
ISO/IEC 14443 A CARD
MICROCONTROLLER
contactless card
reader/writer
001aal156
Fig 4. MFRC523 Read/Write mode
8.1 ISO/IEC 14443 A functionality
The physical level communication is shown in Figure 5.
(1)
ISO/IEC 14443 A
READER
ISO/IEC 14443 A CARD
(2)
MFRC523
001aal157
(1) Reader to card (MFRC523 sends data to a card).
(2) Card to reader (card sends data to the MFRC523).
Fig 5. ISO/IEC 14443 A/MIFARE Read/Write mode communication diagram
The physical parameters are described in Table 4.
Table 4.
Communication overview for ISO/IEC 14443 A reader/writer
Communication
direction
Signal type
Transfer speed
106 kBd
212 kBd
424 kBd
848 kBd
Reader to card
reader side
100 % ASK
100 % ASK
100 % ASK
100 % ASK
(MFRC523 sends data modulation
to a card)
bit encoding
modified Miller
encoding
modified Miller
encoding
modified Miller
encoding
modified Miller
encoding
bit length
128 (13.56 s)
64 (13.56 s)
32 (13.56 s)
16 (13.56 s)
Card to reader (card
sends data to the
MFRC523)
card side
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier load
modulation
subcarrier
frequency
13.56 MHz / 16
13.56 MHz / 16
13.56 MHz / 16
13.56 MHz / 16
bit encoding
Manchester
encoding
BPSK
BPSK
BPSK
The MFRC523’s contactless UART and dedicated external host must manage the
ISO/IEC 14443 A protocol. Figure 6 shows the data coding and framing according to
ISO/IEC 14443 A.
MFRC523
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© NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
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8 of 98
MFRC523
NXP Semiconductors
Contactless reader IC
ISO/IEC 14443 A framing at 106 kBd
start
8-bit data
8-bit data
8-bit data
odd
odd
odd
parity
parity
parity
start bit is 1
ISO/IEC 14443 A framing at 212 kBd, 424 kBd and 848 kBd
start
even
parity
8-bit data
8-bit data
8-bit data
odd
parity
odd
parity
start bit is 0
burst of 32
subcarrier clocks
even parity at the
end of the frame
001aak585
Fig 6. Data coding and framing according to ISO/IEC 14443 A
The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A
part 3 and handles parity generation internally based on the transfer speed. Automatic
parity generation can be switched off using the ManualRCVReg register’s ParityDisable
bit.
8.2 ISO/IEC 14443 B functionality
The MFRC523 reader IC fully supports the ISO 14443 international standard which
includes the communication schemes ISO 14443 A and ISO 14443 B. Refer to the
ISO 14443 reference documents Identification cards - Contactless integrated circuit cards
- Proximity cards (parts 1 to 4).
Remark: NXP Semiconductors does not offer a software library to enable design-in of the
ISO 14443 B protocol.
8.3 Digital interfaces
8.3.1 Automatic microcontroller interface detection
The MFRC523 supports direct interfacing to hosts using SPI, I2C-bus or serial UART
interfaces. The MFRC523 resets its interface and checks the current host interface type
automatically after performing a power-on or hard reset.
The MFRC523 identifies the host interface by sensing the logic levels on the control pins
after the reset phase. This is done using a combination of fixed pin connections. Table 5
shows the different pin connection configurations.
MFRC523
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© NXP B.V. 2011. All rights reserved.
Product data sheet
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Rev. 3.7 — 8 November 2011
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MFRC523
NXP Semiconductors
Contactless reader IC
Table 5.
Connection protocol for detecting different interface types
Interface type
Pin
UART (input)
SPI (output)
I2C-bus (I/O)
SDA
SDA
I2C
EA
D7
D6
D5
D4
D3
D2
D1
RX
NSS
0
0
1
0
1
EA
TX
MISO
SCL
MX
MOSI
ADR_0
ADR_1
ADR_2
ADR_3
ADR_4
ADR_5
DTRQ
SCK
-
-
-
-
-
-
-
-
8.3.2 Serial Peripheral Interface
The 5-wire Serial Peripheral Interface (SPI) is supported and enables high-speed
communication with the host. The interface can manage data speeds up to 10 Mbit/s.
When communicating with a host, the MFRC523 acts as a slave. As such, it receives data
from the external host for register settings, sends and receives data relevant for RF
interface communication.
An interface compatible with SPI enables high-speed serial communication between the
MFRC523 and a microcontroller. The implemented interface meets with the SPI standard.
The timing specification is given in Section 14.1 on page 76.
MFRC523
SCK
SCK
MOSI
MOSI
MISO
MISO
NSS
NSS
001aal159
Fig 7. SPI connection to host
The MFRC523 acts as a slave during SPI communication and is timed using the SPI clock
signal (SCK) generated by the master. Data communication from the master to the slave
uses the MOSI line. The MISO line is used to send data from the MFRC523 to the master.
Data bytes on both MOSI and MISO lines are sent with the MSB first. Data on both MOSI
and MISO lines must be stable on the rising edge of the clock and can be changed on the
falling edge. Data is sent by the MFRC523 on the falling clock edge and is stable during
the rising clock edge.
8.3.2.1 SPI read data
Reading data using SPI requires the byte order shown in Table 6 to be used. It is possible
to read out up to n-data bytes.
MFRC523
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Product data sheet
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MFRC523
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Contactless reader IC
The first byte sent defines both the mode and the address.
Table 6. MOSI and MISO byte order
Line
Byte 0
address 0
X[1]
Byte 1
Byte 2
To
...
Byte n
Byte n + 1
00
MOSI
MISO
address 1
data 0
address 2
data 1
address n
...
data n 1
data n
[1] X = Do not care.
Remark: The MSB must be sent first.
8.3.2.2 SPI write data
To write data to the MFRC523 using SPI requires the byte order shown in Table 7. It is
possible to write up to n-data bytes by only sending one address byte.
The first send byte defines both the mode and the address byte.
Table 7.
Line
MOSI and MISO byte order
Byte 0
address 0
X[1]
Byte 1
data 0
X[1]
Byte 2
data 1
X[1]
To
...
Byte n
data n 1
X[1]
Byte n + 1
data n
X[1]
MOSI
MISO
...
[1] X = Do not care.
Remark: The MSB must be sent first.
8.3.2.3 SPI Read and Write address byte
The read address byte must meet the following criteria:
• the Most Significant Bit (MSB) of the first byte sets the mode. To read data from the
MFRC523, the MSB is set to logic 1; see Table 8
• bits [6:1] define the address
• the Least Significant Bit (LSB) should be set to logic 0
Table 8.
SPI read address
Address
(MOSI)
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
byte 0
1
address address address address address address
0
MFRC523
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Product data sheet
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MFRC523
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Contactless reader IC
The write address byte must meet the following criteria:
• the MSB of the first byte sets the mode. To write data to the MFRC523, the MSB is set
to logic 0; see Table 9
• bits [6:1] define the address
• the LSB should be set to logic 0
Table 9.
SPI write address
Address line
(MOSI)
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
byte 0
0
address address address address address address
0
8.3.3 UART interface
8.3.3.1 Connection to a host
MFRC523
RX
TX
RX
TX
DTRQ
DTRQ
MX
MX
001aal158
Fig 8. UART connection to microcontrollers
Remark: Signals DTRQ and MX can be disabled by clearing TestPinEnReg register’s
RS232LineEn bit.
8.3.3.2 Selectable UART transfer speeds
The internal UART interface is compatible with the RS232 serial interface.
The default transfer speed is 9.6 kBd. To change the transfer speed, the host controller
must write a value for the new transfer speed to the SerialSpeedReg register. Bits
BR_T0[2:0] and BR_T1[4:0] define the factors for setting the transfer speed in the
SerialSpeedReg register.
The BR_T0[2:0] and BR_T1[4:0] settings are described in Table 10. Examples of different
transfer speeds and the relevant register settings are given in Table 11.
Table 10. BR_T0 and BR_T1 settings
BR_Tn
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
BR_T0 factor
BR_T1 range
1
1
2
4
8
16
32
64
1 to 32 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64
MFRC523
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MFRC523
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Contactless reader IC
Table 11. Selectable UART transfer speeds
Transfer speed (kBd) SerialSpeedReg value
Transfer speed accuracy (%)[1]
Decimal
250
235
218
203
171
154
122
116
90
Hexadecimal
FAh
7.2
0.25
0.32
9.6
EBh
14.4
19.2
38.4
57.6
115.2
128
DAh
0.25
0.32
CBh
ABh
0.32
9Ah
0.25
0.25
0.06
0.25
0.25
1.45
7Ah
74h
230.4
460.8
921.6
1228.8
5Ah
58
3Ah
28
1Ch
21
15h
0.32
[1] The resulting transfer speed error is less than 1.5 % for all described transfer speeds.
The selectable transfer speeds shown in Table 11 are calculated according to the
following equations:
If BR_T0[2:0] = 0:
27.12 106
BR_T0 + 1
-------------------------------
transfer speed =
(1)
(2)
If BR_T0[2:0] > 0:
27.12 106
----------------------------------
transfer speed =
BR_T1 + 33
----------------------------------
2BR_T0 – 1
Remark: Transfer speeds above 1228.8 kBd are not supported.
8.3.3.3 UART framing
Table 12. UART framing
Bit
Length
1-bit
Value
0
Start
Data
Stop
8-bit
data
1
1-bit
Remark: The LSB for data and address bytes must be sent first. No parity bit is used
during transmission.
To read data using the UART interface, the flow shown in Table 13 must be used. The first
byte sent defines both the mode and the address.
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Table 13. Read data byte order
Pin
RX
TX
Byte 0
address
-
Byte 1
-
data 0
ADDRESS
RX
SA
A0
A1
A2
A3
A4
A5
(1)
R/W SO
DATA
TX
SA
D0
D1
D2
D3
D4
D5
D6
D7
SO
MX
DTRQ
001aak588
(1) Reserved.
Fig 9. UART read data timing diagram
To write data to the MFRC523 using the UART interface, the structure shown in Table 14
must be used.
The first byte sent defines both the mode and the address.
Table 14. Write data byte order
Pin
RX
TX
Byte 0
Byte 1
address 0
-
data 0
address 0
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ADDRESS
DATA
RX
SA A0 A1 A2 A3 A4 A5
(1) R/W SO
SA D0 D1 D2 D3 D4 D5 D6 D7 SO
ADDRESS
TX
SA A0 A1 A2 A3 A4 A5
(1) R/W SO
MX
DTRQ
001aak589
(1) Reserved.
Remark: The data byte can be sent directly after the address byte on pin RX.
Fig 10. UART write data timing diagram
MFRC523
NXP Semiconductors
Contactless reader IC
The address byte must meet the following formats:
• the MSB of the first byte sets the mode used
– the MSB is set to logic 0 to write data to the MFRC523
– the MSB is set to logic 1 to read data from the MFRC523
• bit 6 is reserved for future use
• bits [5:0] define the address; see Table 15
Table 15. Address byte 0 register; address MOSI
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(MSB)
(LSB)
1 or 0
reserved
address
address
address
address
address
address
8.3.4 I2C Bus Interface
An I2C-bus interface is supported and enables implementation of a low-cost, low pin count
serial bus interface to the host. The I2C-bus interface is implemented based on
NXP Semiconductors’ I2C-bus interface specification, rev. 2.1, January 2000. The
interface can only act in slave mode. Therefore the MFRC523 does not perform clock
generation or access arbitration.
PULL-UP
NETWORK
PULL-UP
NETWORK
MFRC523
SDA
SCL
MICROCONTROLLER
I2C
CONFIGURATION
WIRING
EA
ADR_[5:0]
001aal160
Fig 11. I2C-bus interface
The MFRC523 can act as a slave receiver or slave transmitter in Standard mode, Fast
mode and High-speed mode.
SDA is a bidirectional line connected to a positive supply voltage using a current source or
a pull-up resistor. Both SDA and SCL lines are set HIGH when data is not transmitted. The
MFRC523 has a 3-state output stage to perform the wired-AND function. Data on the
I2C-bus can be transferred at data rates of up to 100 kBd in Standard mode, up to
400 kBd in Fast mode or up to 3.4 Mbit/s in High-speed mode.
If the I2C-bus interface is selected, spike suppression is activated on lines SCL and SDA
as defined in the I2C-bus interface specification.
See Table 156 on page 77 for timing requirements.
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8.3.4.1 Data validity
Data on the SDA line must be stable during the HIGH clock period. The HIGH or LOW
state of the data line must only change when the clock signal on SCL is LOW.
SDA
SCL
data line
stable;
data valid
change
of data
allowed
mbc621
Fig 12. Bit transfer on the I2C-bus
8.3.4.2 START and STOP conditions
To manage the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions
are defined.
• A START condition is defined with a HIGH-to-LOW transition on the SDA line while
SCL is HIGH.
• A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while
SCL is HIGH.
The I2C-bus master always generates the START and STOP conditions. The bus is busy
after the START condition. The bus is free again a certain time after the STOP condition.
The bus stays busy if a repeated START (Sr) is generated instead of a STOP condition.
The START (S) and repeated START (Sr) conditions are functionally identical. Therefore,
S is used as a generic term to represent both the START (S) and repeated START (Sr)
conditions.
SDA
SCL
SDA
SCL
S
P
START condition
STOP condition
mbc622
Fig 13. START and STOP conditions
8.3.4.3 Byte format
Each byte must be followed by an acknowledge bit. Data is transferred with the MSB first;
see Figure 16. The number of transmitted bytes during one data transfer is unrestricted
but must meet the read/write cycle format.
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8.3.4.4 Acknowledge
An acknowledge must be sent at the end of one data byte. The acknowledge-related clock
pulse is generated by the master. The transmitter of data, either master or slave, releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver pulls down the
SDA line during the acknowledge clock pulse so that it remains stable LOW during the
HIGH period of this clock pulse.
The master can then generate either a STOP (P) condition to stop the transfer or a
repeated START (Sr) condition to start a new transfer.
A master-receiver indicates the end of data to the slave-transmitter by not generating an
acknowledge on the last byte that was clocked out by the slave. The slave-transmitter
releases the data line to allow the master to generate a STOP (P) or repeated START (Sr)
condition.
data output
by transmitter
not acknowledge
data output
by receiver
acknowledge
SCL from
master
1
2
8
9
S
clock pulse for
acknowledgement
START
condition
mbc602
Fig 14. Acknowledge on the I2C-bus
P
SDA
Sr
acknowledgement
signal from slave
acknowledgement
signal from receiver
MSB
byte complete,
interrupt within slave
clock line held LOW while
interrupts are serviced
S
or
Sr
Sr
or
P
SCL
1
2
7
8
9
1
2
3 - 8
9
ACK
ACK
START or
repeated START
condition
STOP or
repeated START
condition
msc608
Fig 15. Data transfer on the I2C-bus
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8.3.4.5 7-Bit addressing
During the I2C-bus address procedure, the first byte after the START condition is used to
determine which slave will be selected by the master.
Several address numbers are reserved. During device configuration, the designer must
ensure that collisions with these reserved addresses cannot occur. Check the I2C-bus
specification for a complete list of reserved addresses.
The I2C-bus address specification is dependent on the definition of pin EA. Immediately
after releasing pin NRSTPD or after a power-on reset, the device defines the I2C-bus
address according to pin EA.
If pin EA is set LOW, the upper 4 bits of the device bus address are reserved by
NXP Semiconductors and set to 0101b for all MFRC523 devices. The remaining 3 bits
(ADR_0, ADR_1, ADR_2) of the slave address can be freely configured by the customer
to prevent collisions with other I2C-bus devices.
If pin EA is set HIGH, ADR_0 to ADR_5 can be completely specified at the external pins
according to Table 5 on page 10. ADR_6 is always set to logic 0.
In both modes, the external address coding is latched immediately after releasing the
reset condition. Further changes at the used pins are not taken into consideration.
Depending on the external wiring, the I2C-bus address pins can be used for test signal
outputs.
MSB
bit 6
LSB
R/W
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
slave address
001aak591
Fig 16. First byte following the START procedure
8.3.4.6 Register write access
To write data from the host controller using the I2C-bus to a specific register in the
MFRC523 the following frame format must be used.
• The first byte of a frame indicates the device address according to the I2C-bus rules.
• The second byte indicates the register address followed by up to n-data bytes.
In one frame, all data bytes are written to the same register address. This enables fast
FIFO buffer access. The Read/Write (R/W) bit is set to logic 0.
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8.3.4.7 Register read access
To read out data from a specific register address in the MFRC523, the host controller must
use the following procedure:
• Firstly, a write access to the specific register address must be performed as indicated
in the frame that follows
• The first byte of a frame indicates the device address according to the I2C-bus rules
• The second byte indicates the register address. No data bytes are added
• The Read/Write bit is 0
After the write access, read access can start. The host sends the device address of the
MFRC523. In response, the MFRC523 sends the content of the read access register. In
one frame all data bytes can be read from the same register address. This enables fast
FIFO buffer access or register polling.
The Read/Write (R/W) bit is set to logic 1.
write cycle
2
I C-BUS
SLAVE ADDRESS
[A7:A0]
0
(W)
JOINER REGISTER
ADDRESS [A5:A0]
DATA
[7:0]
S
A
0
0
A
[0:n]
A
P
read cycle
0
2
I C-BUS
0
(W)
JOINER REGISTER
ADDRESS [A5:A0]
SLAVE ADDRESS
[A7:A0]
S
A
0
A
P
optional, if the previous access was on the same register address
[0:n]
2
I C-BUS
1
(R)
DATA
[7:0]
SLAVE ADDRESS
[A7:A0]
S
A
[0:n]
A
A
DATA
[7:0]
P
sent by master
S
P
A
start condition
stop condition
acknowledge
A
not acknowledge
write cycle
W
R
sent by slave
read cycle
001aak592
Fig 17. Register read and write access
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8.3.4.8 High-speed mode
In High-speed mode (HS mode), the device can transfer information at data rates of up to
3.4 Mbit/s, while remaining fully downward-compatible with Fast or Standard modes
(F/S modes) for bidirectional communication in a mixed-speed bus system.
8.3.4.9 High-speed transfer
To achieve data rates of up to 3.4 Mbit/s the following improvements have been made to
I2C-bus operation.
• The inputs of the device in HS mode incorporate spike suppression, a Schmitt trigger
on the SDA and SCL inputs and different timing constants when compared to
F/S mode
• The output buffers of the device in HS mode incorporate slope control of the falling
edges of the SDA and SCL signals with different fall times compared to F/S mode
8.3.4.10 Serial data transfer format in HS mode
The HS mode serial data transfer format meets the Standard mode I2C-bus specification.
HS mode can only start after all of the following conditions (all of which are in F/S mode):
1. START condition (S)
2. 8-bit master code (00001 XXXb)
3. Not-acknowledge bit (A)
When HS mode starts, the active master sends a repeated START condition (Sr) followed
by a 7-bit slave address with a R/W bit address and receives an acknowledge bit (A) from
the selected MFRC523.
Data transfer continues in HS mode after the next repeated START (Sr), only switching
back to F/S mode after a STOP condition (P). To reduce the overhead of the master code,
a master links a number of HS mode transfers, separated by repeated START conditions
(Sr).
HS mode (current-source for SCL HIGH enabled)
F/S mode
F/S mode
S
MASTER CODE
A
Sr SLAVE ADDRESS R/W
A
DATA
A/A
P
(n-bytes + A)
HS mode continues
SLAVE ADDRESS
Sr
001aak749
Fig 18. I2C-bus HS mode protocol switch
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t
1
A
8-bit master code 0000 1xxx
S
t
H
SDA high
SCL high
1
2 to 5
6
7
8
9
F/S mode
n + (8-bit data
+
A/A)
R/W
A
7-bit SLA
Sr
Sr P
SDA high
SCL high
1
2 to 5
6
7
8
9
1
2 to 5
6
7
8
9
If P then
HS mode
F/S mode
If Sr (dotted lines)
then HS mode
t
H
t
FS
= Master current source pull-up
= Resistor pull-up
msc618
Fig 19. I2C-bus HS mode protocol frame
8.3.4.11 Switching between F/S mode and HS mode
After reset and initialization, the MFRC523 is in Fast mode (which is in effect F/S mode as
Fast mode is downward-compatible with Standard mode). The connected MFRC523
recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast
mode setting to the HS mode setting.
The following actions are taken:
1. Adapt the SDA and SCL input filters according to the spike suppression requirement
in HS mode.
2. Adapt the slope control of the SDA output stages.
It is possible for system configurations that do not have other I2C-bus devices involved in
the communication to switch to HS mode permanently. This is implemented by setting
Status2Reg register’s I2CForceHS bit to logic 1. In permanent HS mode, the master code
is not required to be sent. This is not defined in the specification and must only be used
when no other devices are connected on the bus. In addition, spikes on the I2C-bus lines
must be avoided because of the reduced spike suppression.
8.3.4.12 MFRC523 in lower speed modes
MFRC523 is fully downward-compatible and can be connected to an F/S mode I2C-bus
system. The device stays in F/S mode and communicates at F/S mode speeds because a
master code is not transmitted in this configuration.
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8.4 Analog interface and contactless UART
8.4.1 General
The integrated contactless UART supports the external host online with framing and error
checking of the protocol requirements up to 848 kBd. An external circuit can be connected
to the communication interface pins MFIN and MFOUT to modulate and demodulate the
data.
The contactless UART manage the protocol requirements for the communication
protocols in cooperation with the host. Protocol handling generates bit and byte-oriented
framing. In addition, it manages error detection such as parity and CRC, based on the
various supported contactless communication protocols.
Remark: The size and tuning of the antenna and the power supply voltage have an
important impact on the achievable operating distance.
8.4.2 TX p-driver
The signal on pins TX1 and TX2 is the 13.56 MHz energy carrier modulated by an
envelope signal. It can be used to drive an antenna directly using a few passive
components for matching and filtering; see Section 15 on page 79. The signal on pins TX1
and TX2 can be configured using the TxControlReg register; see Section 9.2.2.5 on
page 48.
The modulation index can be set by adjusting the impedance of the drivers. The
impedance of the p-driver can be configured using registers CWGsPReg and
ModGsPReg. The impedance of the n-driver can be configured using the GsNReg
register. The modulation index also depends on the antenna design and tuning.
The TxModeReg and TxSelReg registers control the data rate and framing during
transmission and the antenna driver setting to support the different requirements at the
different modes and transfer speeds.
Table 16. Register and bit settings controlling the signal on pin TX1
Bit
Tx1RFEn Force
100ASK
Bit
Bit
Bit
Envelope Pin
TX1
GSPMos GSNMos Remarks
InvTx1RFOn InvTx1RFOff
0
X[1]
X[1]
0
X[1]
X[1]
X[1]
X[1]
X[1]
X[1]
not specified if RF is
switched off
1
0
0
1
0
1
0
1
0
1
RF
RF
RF
RF
0
pMod
pCW
pMod
pCW
pMod
nMod
nCW
nMod
nCW
nMod
nCW
100 % ASK: pin TX1
pulled to logic 0,
independently of the
InvTx1RFOff bit
1
1
X[1]
X[1]
RF_n pCW
[1] X = Do not care.
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Table 17. Register and bit settings controlling the signal on pin TX2
Bit
Tx1RFEn Force
100ASK
Bit
Bit
Bit
Bit
Envelope Pin
TX2
GSPMos GSNMos Remarks
Tx2CW InvTx2RFOn InvTx2RFOff
0
X[1]
X[1]
X[1]
X[1]
X[1]
X[1]
X[1]
X[1]
not specified if
RF is switched
off
1
0
0
0
1
X[1]
X[1]
0
RF
RF
pMod
pCW
nMod
nCW
nMod
nCW
nCW
nCW
-
1
0
RF_n pMod
RF_n pCW
1
1
0
0
1
X[1]
X[1]
X[1]
X[1]
RF
pCW
conductance
always CW for
the Tx2CW bit
RF_n pCW
1
0
1
X[1]
X[1]
0
0
pMod
pCW
pMod
nMod
nCW
nMod
nCW
nCW
nCW
100 % ASK: pin
TX2 pulled
to logic 0
(independent of
the
InvTx2RFOn/Inv
Tx2RFOff bits)
1
RF
0
0
1
RF_n pCW
RF pCW
RF_n pCW
1
0
1
X[1]
X[1]
X[1]
X[1]
[1] X = Do not care.
The following abbreviations have been used in Table 16 and Table 17:
• RF: 13.56 MHz clock derived from 27.12 MHz quartz crystal oscillator divided by 2
• RF_n: inverted 13.56 MHz clock
• GSPMos: conductance, configuration of the PMOS array
• GSNMos: conductance, configuration of the NMOS array
• pCW: PMOS conductance value for continuous wave defined by the CWGsPReg
register
• pMod: PMOS conductance value for modulation defined by the ModGsPReg register
• nCW: NMOS conductance value for continuous wave defined by the GsNReg
register’s CWGsN[3:0] bits
• nMod: NMOS conductance value for modulation defined by the GsNReg register’s
ModGsN[3:0] bits
• X = Do not care
Remark: If only one driver is switched on, the values for CWGsPReg, ModGsPReg and
GsNReg registers are used for both drivers.
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8.4.3 Serial data switch
Two main blocks are implemented in the MFRC523. The digital block comprises the state
machines, encoder/decoder logic. The analog block comprises the modulator and
antenna drivers, the receiver and amplifiers. It is possible for the interface between these
two blocks to be configured so that the interfacing signals are routed to pins MFIN and
MFOUT. This topology allows the analog block of the MFRC523 to be connected to the
digital block of another device.
The serial signal switch is controlled by the TxSelReg and RxSelReg registers.
Figure 20 shows the serial data switch for TX1 and TX2.
DriverSel[1:0]
3-state
1
00
01
10
11
envelope
INTERNAL
CODER
INVERT IF
InvMod = 1
to driver TX1 and TX2
0 = impedance = modulated
1 = impedance = CW
INVERT IF
PolMFin = 0
MFIN
001aak593
Fig 20. Serial data switch for TX1 and TX2
8.4.4 MFIN and MFOUT interface support
The MFRC523 is divided into a digital circuit block and an analog circuit block. The digital
block contains state machines, encoder and decoder logic, etc. The analog block contains
the modulator and antenna drivers, receiver and amplifiers. The interface between these
two blocks can be configured to enable the interfacing signals to be routed to pins MFIN
and MFOUT; see Figure 21 on page 26. This configuration is implemented using
TxSelReg register’s MFOutSel[3:0]/DriverSel[1:0] bits and RxSelReg register’s
UARTSel[1:0] bits. This topology allows some parts of the analog block to be connected to
the digital block of another device.
Switch MFOutSel in the TxSelReg register can be used to measure MIFARE and
ISO/IEC14443 A related signals. This is especially important during the design-in phase
or for testing purposes as it enables checking of the transmitted and received data.
The most important use of pins MFIN and MFOUT is found in the active antenna concept.
An external active antenna circuit can be connected to the MFRC523’s digital block.
Switch MFOutSel must be configured so that the internal Miller encoded signal is sent to
pin MFOUT (MFOutSel = 100b). UARTSel[1:0] must be configured to receive a
Manchester signal with subcarrier from pin MFIN (UARTSel[1:0] = 01).
It is possible to connect a passive antenna to pins TX1, TX2 and RX (using the
appropriate filter and matching circuit) and an active antenna to pins MFOUT and MFIN at
the same time. In this configuration, two RF circuits can be driven (one after another) by a
single host processor.
Remark: Pins MFIN and MFOUT have a dedicated supply on pin SVDD with the ground
on pin PVSS.
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MFOUT
3-state
LOW
0
1
2
3
4
5
6
7
3-state
internal envelope
envelope from pin MFIN
HIGH
0
1
2
3
TX2
TX1
TX bit stream
MILLER
CODER
MODULATOR
DRIVER
MFOutSel[3:0]
HIGH
DRIVER
Sel[1:0]
test bus
internal envelope
TX serial data stream
reserved
DIGITAL MODULE
ANALOG MODULE
MFRC523
RX serial data stream
MFRC523
SUBCARRIER
DEMODULATOR
0
1
2
3
LOW
Manchester with subcarrier
internal modulated
RX bit stream
MANCHESTER
DECODER
DEMODULATOR
RX
UART
NRZ coding without subcarrier (> 106 kBd)
Sel[1:0]
MFIN
001aal161
Fig 21. Overview of MFIN and MFOUT signal routing
MFRC523
NXP Semiconductors
Contactless reader IC
8.4.5 CRC coprocessor
The following CRC coprocessor parameters can be configured:
• The CRC preset value can be either 0000h, 6363h, A671h or FFFFh depending on
the ModeReg register’s CRCPreset[1:0] bits setting
• The CRC polynomial for the 16-bit CRC is fixed to x16 + x12 + x5 + 1
• The CRCResultReg register indicates the result of the CRC calculation. This register
is split into two 8-bit registers representing the higher and lower bytes.
• The ModeReg register’s MSB first bit indicates that data will be loaded with the MSB
first.
Table 18. CRC coprocessor parameters
Parameter
Value
CRC register length
CRC algorithm
CRC preset value
16-bit CRC
algorithm according to ISO/IEC 14443 A and ITU-T
0000h, 6363h, A671h or FFFFh depending on the setting of the
ModeReg register’s CRCPreset[1:0] bits
8.5 FIFO buffer
An 8 64 bit FIFO buffer is used in the MFRC523. It buffers the input and output data
stream between the host and the MFRC523’s internal state machine. This makes it
possible to manage data streams up to 64 bytes long without the need to take timing
constraints into account.
8.5.1 Accessing the FIFO buffer
The FIFO buffer input and output data bus is connected to the FIFODataReg register.
Writing to this register stores one byte in the FIFO buffer and increments the internal FIFO
buffer write pointer. Reading from this register shows the FIFO buffer contents stored in
the FIFO buffer read pointer and decrements the FIFO buffer read pointer. The distance
between the write and read pointer can be obtained by reading the FIFOLevelReg
register.
When the microcontroller starts a command, the MFRC523 can, while the command is in
progress, access the FIFO buffer according to that command. Only one FIFO buffer has
been implemented which can be used for input and output. The microcontroller must
ensure that there are not any unintentional FIFO buffer accesses.
8.5.2 Controlling the FIFO buffer
The FIFO buffer pointers can be reset by setting FIFOLevelReg register’s FlushBuffer bit
to logic 1. Consequently, the FIFOLevel[6:0] bits are all set to logic 0 and the ErrorReg
register’s BufferOvfl bit is cleared. The bytes stored in the FIFO buffer are no longer
accessible allowing the FIFO buffer to be filled with another 64 bytes.
8.5.3 FIFO buffer status information
The host can get the following FIFO buffer status information:
• Number of bytes stored in the FIFO buffer: FIFOLevelReg register’s FIFOLevel[6:0]
• FIFO buffer almost full warning: Status1Reg register’s HiAlert bit
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• FIFO buffer almost empty warning: Status1Reg register’s LoAlert bit
• FIFO buffer overflow warning: ErrorReg register’s BufferOvfl bit. The BufferOvfl bit
can only be cleared by setting the FIFOLevelReg register’s FlushBuffer bit.
The MFRC523 can generate an interrupt signal when:
• ComIEnReg register’s LoAlertIEn bit is set to logic 1. It activates pin IRQ when
Status1Reg register’s LoAlert bit changes to logic 1.
• ComIEnReg register’s HiAlertIEn bit is set to logic 1. It activates pin IRQ when
Status1Reg register’s HiAlert bit changes to logic 1.
If the maximum number of WaterLevel[5:0] bits (as set in the WaterLevelReg register) or
less are stored in the FIFO buffer, the HiAlert bit is set to logic 1. It is generated according
to Equation 3:
HiAlert = 64 – FIFOLength WaterLevel
(3)
If the number of WaterLevel[5:0] bits (as set in the WaterLevelReg register) or less are
stored in the FIFO buffer, the LoAlert bit is set to logic 1. It is generated according to
Equation 4:
LoAlert = FIFOLength WaterLevel
(4)
8.6 Interrupt request system
The MFRC523 indicates certain events by setting the Status1Reg register’s IRq bit and, if
activated, by pin IRQ. The signal on pin IRQ can be used to interrupt the host using its
interrupt handling capabilities. This allows the implementation of efficient host software.
8.6.1 Interrupt sources overview
Table 19 shows the available interrupt bits, the corresponding source and the condition for
its activation. The ComIrqReg register’s TimerIRq interrupt bit indicates an interrupt set by
the timer unit which is set when the timer decrements from 1 to 0.
The ComIrqReg register’s TxIRq bit indicates that the transmitter has finished. If the state
changes from sending data to transmitting the end of the frame pattern, the transmitter
unit automatically sets the interrupt bit. The CRC coprocessor sets the DivIrqReg
register’s CRCIRq bit after processing all the FIFO buffer data which is indicated by
CRCReady bit = 1.
The ComIrqReg register’s RxIRq bit indicates an interrupt when the end of the received
data is detected. The ComIrqReg register’s IdleIRq bit is set if a command finishes and
the Command[3:0] value in the CommandReg register changes to idle (see Table 150 on
page 68).
The ComIrqReg register’s HiAlertIRq bit is set to logic 1 when the Status1Reg register’s
HiAlert bit is set to logic 1 which means that the FIFO buffer has reached the level
indicated by the WaterLevel[5:0] bits.
The ComIrqReg register’s LoAlertIRq bit is set to logic 1 when the Status1Reg register’s
LoAlert bit is set to logic 1 which means that the FIFO buffer has reached the level
indicated by the WaterLevel[5:0] bits.
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The ComIrqReg register’s ErrIRq bit indicates an error detected by the contactless UART
during send or receive. This is indicated when any bit is set to logic 1 in register ErrorReg.
Table 19. Interrupt sources
Interrupt flag Interrupt source
Trigger action
TimerIRq
TxIRq
timer unit
the timer counts from 1 to 0
a transmitted data stream ends
all data from the FIFO buffer has been processed
a received data stream ends
command execution finishes
the FIFO buffer is almost full
the FIFO buffer is almost empty
an error is detected
transmitter
CRCIRq
RxIRq
CRC coprocessor
receiver
IdleIRq
ComIrqReg register
FIFO buffer
HiAlertIRq
LoAlertIRq
ErrIRq
FIFO buffer
contactless UART
8.7 Timer unit
The MFRC523A has a timer unit which the external host can use to manage timing tasks.
The timer unit can be used in one of the following timer/counter configurations:
• Timeout counter
• Watchdog counter
• Stop watch
• Programmable one shot
• Periodic trigger
The timer unit can be used to measure the time interval between two events or to indicate
that a specific event occurred after a specific time. The timer can be triggered by events
explained in the paragraphs below. The timer does not influence any internal events, for
example, a time-out during data reception does not automatically influence the reception
process. In addition, several timer-related bits can be used to generate an interrupt.
The timer has an input clock of 13.56 MHz derived from the 27.12 MHz quartz crystal
oscillator. The timer consists of two stages: prescaler and counter.
The prescaler (TPrescaler) is a 12-bit counter. The reload values (TReloadVal_Hi[7:0] and
TReloadVal_Lo[7:0]) for TPrescaler can be set between 0 and 4095 in the TModeReg
register’s TPrescaler_Hi[3:0] bits and TPrescalerReg register’s TPrescaler_Lo[7:0] bits.
The reload value for the counter is defined by 16 bits between 0 and 65535 in the
TReloadReg register.
The current value of the timer is indicated in the TCounterValReg register.
When the counter reaches 0, an interrupt is automatically generated, indicated by the
ComIrqReg register’s TimerIRq bit setting. If enabled, this event can be indicated on
pin IRQ. The TimerIRq bit can be set and reset by the host. Depending on the
configuration, the timer will stop at 0 or restart with the value set in the TReloadReg
register.
The timer status is indicated by the Status1Reg register’s TRunning bit.
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The timer can be started manually using the ControlReg register’s TStartNow bit and
stopped using the ControlReg register’s TStopNow bit.
The timer can also be activated automatically to meet any dedicated protocol
requirements, by setting the TModeReg register’s TAuto bit to logic 1.
The delay time of a timer stage is set by the reload value + 1. The total delay time (td) is
calculated using Equation 5:
TPrescaler 2 + 1 TReloadVal + 1
---------------------------------------------------------------------------------------------------------
td
=
(5)
13.56 MHz
or if the TPrescalEven bit is set, using Equation 6:
TPrescaler 2 + 2 TReloadVal + 1
---------------------------------------------------------------------------------------------------------
=
td
(6)
13.56 MHz
An example of calculating total delay time (td) is shown in Equation 7, where the
TPrescaler value = 4095 and TReloadVal = 65535:
4095 2 + 1 65535 + 1
----------------------------------------------------------------------
39.59 s =
(7)
13.56 MHz
Example: To give a delay time of 25 s requires 339 clock cycles to be counted and a
TPrescaler value of 169. This configures the timer to count up to 65535 time-slots for
every 25 s period.
8.8 Power reduction modes
8.8.1 Hard power-down
Hard power-down is enabled when pin NRSTPD is LOW. This turns off all internal current
sinks including the oscillator. All digital input buffers are separated from the input pins and
clamped internally (except pin NRSTPD). The output pins are frozen at either a HIGH or
LOW level.
8.8.2 Soft power-down mode
Soft power-down mode is entered immediately after the CommandReg register’s
PowerDown bit is set to logic 1. All internal current sinks are switched off, including the
oscillator buffer. However, the digital input buffers are not separated from the input pins
and keep their functionality. The digital output pins do not change their state.
During soft power-down, all register values, the FIFO buffer content and the configuration
keep their current contents.
After setting the PowerDown bit to logic 0, it takes 1024 clocks until the Soft power-down
mode is exited indicated by the PowerDown bit. Setting it to logic 0 does not immediately
clear it. It is automatically cleared by the MFRC523 when Soft power-down mode is
exited.
Remark: When the internal oscillator is used, time (tosc) is required for the oscillator to
become stable. This is because the internal oscillator is supplied by VDDA and any clock
cycles will not be detected by the internal logic until VDDA is stable. It is recommended for
the serial UART, to first send the value 55h to the MFRC523. The oscillator must be stable
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for further access to the registers. To ensure this, perform a read access to address 0 until
the MFRC523 answers to the last read command with the register content of address 0.
This indicates that the MFRC523 is ready.
8.8.3 Transmitter Power-down mode
The Transmitter Power-down mode switches off the internal antenna drivers and the RF
field. Transmitter Power-down mode is entered by setting either the TxControlReg
register’s Tx1RFEn bit or Tx2RFEn bit to logic 0.
8.9 Oscillator circuit
MFRC523
OSCOUT
OSCIN
27.12 MHz
001aal162
Fig 22. Quartz crystal connection
The clock applied to the MFRC523 provides a time basis for the synchronous system’s
encoder and decoder. The stability of the clock frequency is an important factor for correct
operation. To obtain optimum performance, clock jitter must be reduced as much as
possible. This is best achieved using the internal oscillator buffer with the recommended
circuitry.
If an external clock source is used, the clock signal must be applied to pin OSCIN. In this
case, be very careful in optimizing clock duty cycle and clock jitter. Ensure the clock
quality has been verified.
8.10 Reset and oscillator start-up time
8.10.1 Reset timing requirements
The reset signal is filtered by a hysteresis circuit and a spike filter before it enters the
digital circuit. The spike filter rejects signals shorter than 10 ns. In order to perform a reset,
the signal must be LOW for at least 100 ns.
8.10.2 Oscillator start-up time
If the MFRC523 has been set to a Power-down mode or is powered by a VDDX supply, the
start-up time for the MFRC523 depends on the oscillator used and is shown in Figure 23.
The time (tstartup) is the start-up time of the crystal oscillator circuit. The crystal oscillator
start-up time is defined by the crystal.
The time (td) is the internal delay time of the MFRC523 when the clock signal is stable
before the MFRC523 can be addressed.
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The delay time is calculated by:
1024
27 s
-------------
td
=
= 37.74 s
(8)
The time (tosc) is the sum of td and tstartup
.
device activation
oscillator
clock stable
clock ready
t
startup
t
d
t
osc
t
001aak596
Fig 23. Oscillator start-up time
9. MFRC523 registers
9.1 Register bit behavior
Depending on the functionality of a register, the access conditions to the register can vary.
In principle, bits with same behavior are grouped in common registers. The access
conditions are described in Table 20.
Table 20. Behavior of register bits and their designation
Abbreviation Behavior
Description
R/W
read and write These bits can be written and read by the microcontroller. Since
they are used only for control purposes, their content is not
influenced by internal state machines, for example the
ComIEnReg register can be written and read by the
microcontroller. It will also be read by internal state machines but
never changed by them.
D
R
dynamic
These bits can be written and read by the microcontroller.
Nevertheless, they can also be written automatically by internal
state machines, for example the CommandReg register changes
its value automatically after the execution of the command.
read only
These register bits hold values which are determined by internal
states only, for example the CRCReady bit cannot be written
externally but shows internal states.
W
write only
-
Reading these register bits always returns zero.
reserved
Registers which are indicated as being reserved must not be
changed. However, in the case of a write access, it is
recommended that 0 is always written.
-
Registers which are indicated as being reserved for future use or
are for production tests must not be changed.
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9.1.1 MFRC523 register overview
Table 21. MFRC523 register overview
Subaddress Register name
(Hex)
Function
Refer to
Page 0: Command and status
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
Reserved
reserved for future use
Table 22 on page 36
Table 24 on page 36
Table 26 on page 37
Table 28 on page 37
Table 30 on page 38
Table 32 on page 39
CommandReg
ComlEnReg
DivlEnReg
starts and stops command execution
enable and disable interrupt request control bits
enable and disable interrupt request control bits
interrupt request bits
ComIrqReg
DivIrqReg
interrupt request bits
ErrorReg
error bits showing the error status of the last command executed Table 36 on page 40
Status1Reg
Status2Reg
FIFODataReg
FIFOLevelReg
WaterLevelReg
ControlReg
BitFramingReg
CollReg
communication status bits
Table 36 on page 40
Table 38 on page 41
Table 40 on page 42
Table 42 on page 42
Table 44 on page 43
Table 46 on page 43
Table 48 on page 44
Table 50 on page 44
Table 52 on page 45
receiver and transmitter status bits
input and output of 64 byte FIFO buffer
number of bytes stored in the FIFO buffer
level for FIFO underflow and overflow warning
miscellaneous control registers
adjustments for bit-oriented frames
bit position of the first bit-collision detected on the RF interface
reserved for future use
Reserved
Page 1: Command
Reserved
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
reserved for future use
Table 54 on page 45
Table 56 on page 46
Table 58 on page 47
Table 60 on page 47
Table 62 on page 48
Table 64 on page 49
Table 66 on page 49
Table 68 on page 50
Table 70 on page 51
Table 72 on page 51
Table 74 on page 52
Table 76 on page 52
Table 78 on page 52
Table 80 on page 53
Table 82 on page 53
Table 84 on page 54
ModeReg
defines general modes for transmitting and receiving
defines transmission data rate and framing
defines reception data rate and framing
controls the antenna driver pins TX1 and TX2
controls the setting of the transmission modulation
selects the internal sources for the antenna driver
selects internal receiver settings
TxModeReg
RxModeReg
TxControlReg
TxASKReg
TxSelReg
RxSelReg
RxThresholdReg selects thresholds for the bit decoder
DemodReg
Reserved
Reserved
MfTxReg
MfRxReg
TypeBReg
defines demodulator settings
reserved for future use
reserved for future use
controls MIFARE communication transmit parameters
controls MIFARE communication receive parameters
controls the ISO/IEC 14443 B functionality
SerialSpeedReg selects the speed of the serial UART interface
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Table 21. MFRC523 register overview …continued
Subaddress Register name
(Hex)
Function
Refer to
Page 2: Configuration
20h
21h
22h
23h
24h
25h
26h
27h
Reserved
reserved for future use
Table 86 on page 55
Table 88 on page 55
Table 90 on page 55
Table 92 on page 56
Table 94 on page 56
Table 96 on page 56
Table 98 on page 57
CRCResultReg
CRCResultReg
Reserved
shows the MSB and LSB values of the CRC calculation
shows the MSB and LSB values of the CRC calculation
reserved for future use
ModWidthReg
Reserved
controls the ModWidth setting
reserved for future use
RFCfgReg
GsNReg
configures the receiver gain
selects the conductance of the antenna driver pins TX1 and TX2 Table 100 on
for modulation
page 57
28h
29h
2Ah
2Bh
CWGsPReg
ModGsPReg
TModeReg
defines the conductance of the p-driver output when not active
Table 102 on
page 58
defines the conductance of the p-driver output during modulation Table 104 on
page 58
defines settings for the internal timer
Table 106 on
page 58
TPrescalerReg
Table 108 on
page 59
2Ch
2Dh
2Eh
2Fh
TReloadReg
TReloadReg
defines the 16-bit timer reload value
defines the 16-bit timer reload value
Table 110 on page 60
Table 112 on page 60
Table 114 on page 60
Table 116 on page 61
TCounterValReg shows the 16-bit timer value
TCounterValReg shows the 16-bit timer value
Page 3: Test register
30h
31h
Reserved
reserved for future use
Table 118 on page 61
TestSel1Reg
TestSel2Reg
TestPinEnReg
general test signal configuration
Table 120 on
page 61
32h
33h
34h
35h
36h
37h
38h
39h
general test signal configuration and PRBS control
enables pin output driver on pins D1 to D7
Table 122 on
page 62
Table 124 on
page 62
TestPinValueReg defines the values for D1 to D7 when it is used as an I/O bus
Table 126 on
page 63
TestBusReg
AutoTestReg
VersionReg
shows the status of the internal test bus
controls the digital self-test
Table 128 on
page 63
Table 130 on
page 63
shows the software version
Table 132 on
page 64
AnalogTestReg
TestDAC1Reg
controls the pins AUX1 and AUX2
defines the test value for TestDAC1
Table 134 on
page 64
Table 136 on
page 66
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Table 21. MFRC523 register overview …continued
Subaddress Register name
(Hex)
Function
Refer to
3Ah
TestDAC2Reg
TestADCReg
Reserved
defines the test value for TestDAC2
shows the value of ADC I-channel and Q-channel
reserved for production tests
Table 138 on
page 66
3Bh
Table 140 on
page 66
3Ch to 3Fh
Table 142 to
Table 148 on
page 67
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9.2 Register descriptions
9.2.1 Page 0: Command and status
9.2.1.1 Reserved register 00h
Functionality is reserved for future use.
Table 22. Reserved register (address 00h); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
reserved
-
Table 23. Reserved register bit descriptions
Bit Symbol Value Description
7 to 0 reserved reserved for future use
-
9.2.1.2 CommandReg register
Starts and stops command execution.
Table 24. CommandReg register (address 01h); reset value: 20h bit allocation
Bit
7
6
5
4
PowerDown
D
3
2
1
0
Symbol:
Access:
00
-
RcvOff
R/W
Command[3:0]
D
Table 25. CommandReg register bit descriptions
Bit Symbol Value Description
7 to 6 00
0
1
1
0
reserved
5
4
RcvOff
PowerDown
analog part of the receiver is switched off
Soft Power-down mode entered
MFRC523 starts the wake up procedure during which this bit is
read as a logic 1; it is read as a logic 0 when the MFRC523 is
ready; see Section 8.8.2 on page 30
Remark: The PowerDown bit cannot be set when the SoftReset
command is activated
3 to 0 Command[3:0] -
activates a command based on the Command value; reading this
register shows which command is executed; see Section 10.3 on
page 68
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9.2.1.3 ComIEnReg register
Control bits to enable and disable the passing of interrupt requests.
Table 26. ComIEnReg register (address 02h); reset value: 80h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
IRqInv
R/W
TxIEn
R/W
RxIEn
R/W
IdleIEn HiAlertIEn LoAlertIEn ErrIEn TimerIEn
R/W R/W R/W R/W R/W
Table 27. ComIEnReg register bit descriptions
Bit Symbol Value Description
7
IRqInv
1
signal on pin IRQ is inverted with respect to the Status1Reg register’s IRq
bit
0
signal on pin IRQ is equal to the IRq bit; in combination with the
DivIEnReg register’s IRqPushPull bit, the default value of logic 1 ensures
that the output level on pin IRQ is 3-state
6
5
TxIEn
RxIEn
-
-
allows the transmitter interrupt request (TxIRq bit) to be propagated to pin
IRQ
allows the receiver interrupt request (RxIRq bit) to be propagated to pin
IRQ
4
3
IdleIEn
-
-
allows the idle interrupt request (IdleIRq bit) to be propagated to pin IRQ
HiAlertIEn
allows the high alert interrupt request (HiAlertIRq bit) to be propagated to
pin IRQ
2
LoAlertIEn -
allows the low alert interrupt request (LoAlertIRq bit) to be propagated to
pin IRQ
1
0
ErrIEn
-
-
allows the error interrupt request (ErrIRq bit) to be propagated to pin IRQ
TimerIEn
allows the timer interrupt request (TimerIRq bit) to be propagated to pin
IRQ
9.2.1.4 DivIEnReg register
Control bits to enable and disable the passing of interrupt requests.
Table 28. DivIEnReg register (address 03h); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
IRQPushPull
R/W
reserved
-
MfinActIEn
R/W
reserved
-
CRCIEn
R/W
reserved
-
Table 29. DivIEnReg register bit descriptions
Bit
Symbol
Value Description
7
IRQPushPull
1
0
-
pin IRQ is a standard CMOS output pin
pin IRQ is an open-drain output pin
reserved for future use
6 to 5 reserved
4
MfinActIEn
-
allows the MFIN active interrupt request to be propagated to
pin IRQ
3
2
reserved
CRCIEn
-
-
reserved for future use
allows the CRC interrupt request, indicated by the DivIrqReg
register’s CRCIRq bit, to be propagated to pin IRQ
1 to 0 reserved
-
reserved for future use
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9.2.1.5 ComIrqReg register
Interrupt request bits.
Table 30. ComIrqReg register (address 04h); reset value: 14h bit allocation
Bit
7
6
5
4
3
HiAlertIRq
D
2
LoAlertIRq
D
1
0
Symbol
Access
Set1 TxIRq RxIRq IdleIRq
ErrIRq TimerIRq
W
D
D
D
D
D
Table 31. ComIrqReg register bit descriptions
All bits in the ComIrqReg register are cleared by software.
Bit Symbol
Value Description
7
Set1
1
0
1
1
indicates that the marked bits in the ComIrqReg register are set
indicates that the marked bits in the ComIrqReg register are cleared
set immediately after the last bit of the transmitted data was sent out
receiver has detected the end of a valid data stream
6
5
TxIRq
RxIRq
if the RxModeReg register’s RxNoErr bit is set to logic 1, the RxIRq bit is
only set to logic 1 when data bytes are available in the FIFO
4
IdleIRq
1
if a command terminates, for example, when the CommandReg changes
its value from any command to the Idle command (see Table 150 on
page 68)
if an unknown command is started, the CommandReg register
Command[3:0] value changes to the idle state and the IdleIRq bit is set
the microcontroller starting the Idle command does not set the IdleIRq bit
the Status1Reg register’s HiAlert bit is set
3
2
HiAlertIRq
LoAlertIRq
1
1
the HiAlertIRq bit stores this event and can only be reset as indicated by
the Set1 bit in this register
Status1Reg register’s LoAlert bit is set
the LoAlertIRq bit stores this event and can only be reset as indicated by
the Set1 bit in this register
1
0
ErrIRq
1
1
any error bit in the ErrorReg register is set
TimerIRq
the timer decrements the timer value in register TCounterValReg to zero
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9.2.1.6 DivIrqReg register
Interrupt request bits.
Table 32. DivIrqReg register (address 05h); reset value: x0h bit allocation
Bit
7
Set2
W
6
5
4
3
2
1
0
Symbol
Access
reserved
MfinActIRq reserved CRCIRq
reserved
-
-
D
-
D
Table 33. DivIrqReg register bit descriptions
All bits in the DivIrqReg register are cleared by software.
Bit
Symbol
Value Description
7
Set2
1
0
-
indicates that the marked bits in the DivIrqReg register are set
indicates that the marked bits in the DivIrqReg register are cleared
reserved for future use
6 to 5 reserved
4
MfinActIRq 1
MFIN is active; this interrupt is set when either a rising or falling signal
edge is detected
3
2
reserved
CRCIRq
-
reserved for future use
1
-
the CalcCRC command is active and all data is processed
reserved for future use
1 to 0 reserved
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9.2.1.7 ErrorReg register
Error bit register showing the error status of the last command executed.
Table 34. ErrorReg register (address 06h); reset value: 00h bit allocation
Bit
Symbol WrErr TempErr reserved BufferOvfl CollErr CRCErr ParityErr ProtocolErr
Access
7
6
5
4
3
2
1
0
R
R
-
R
R
R
R
R
Table 35. ErrorReg register bit descriptions
Bit Symbol Value Description
7
WrErr
1
data is written into the FIFO buffer by the host during the MFAuthent
command or if data is written into the FIFO buffer by the host during the
time between sending the last bit on the RF interface and receiving the
last bit on the RF interface
6
TempErr[1]
1
internal temperature sensor detects overheating, in which case the
antenna drivers are automatically switched off
5
4
reserved
-
reserved for future use
BufferOvfl
1
the host or a MFRC523’s internal state machine (e.g. receiver) tries to
write data to the FIFO buffer even though it is already full
3
CollErr
1
a bit-collision is detected
cleared automatically at receiver start-up phase
only valid during the bitwise anticollision at 106 kBd
always set to logic 0 during communication protocols at 212 kBd,
424 kBd and 848 kBd
2
1
CRCErr
1
1
the RxModeReg register’s RxCRCEn bit is set and the CRC calculation
fails
automatically cleared to logic 0 during receiver start-up phase
parity check failed
ParityErr
automatically cleared during receiver start-up phase
only valid for ISO/IEC 14443 A/MIFARE communication at 106 kBd
set to logic 1 if the SOF is incorrect
0
ProtocolErr
1
automatically cleared during receiver start-up phase
bit is only valid for 106 kBd
during the MFAuthent command, the ProtocolErr bit is set to logic 1 if the
number of bytes received in one data stream is incorrect
[1] Command execution clears all error bits except the TempErr bit. Cannot be set by software.
9.2.1.8 Status1Reg register
Contains status bits of the CRC, interrupt and FIFO buffer.
Table 36. Status1Reg register (address 07h); reset value: 21h bit allocation
Bit
Symbol reserved CRCOk CRCReady
Access
7
6
5
4
IRq
R
3
2
1
0
LoAlert
R
TRunning reserved HiAlert
-
R
R
R
-
R
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Table 37. Status1Reg register bit descriptions
Bit Symbol Value Description
7
6
reserved
CRCOk
-
reserved for future use
the CRC result is zero
1
the CRCOk bit is undefined for data transmission and reception: use
the ErrorReg register’s CRCErr bit
indicates the status of the CRC coprocessor, during calculation the
value changes to logic 0, when the calculation is done correctly the
value changes to logic 1
5
4
CRCReady
IRq
1
-
the CRC calculation has finished; only valid for the CRC coprocessor
calculation using the CalcCRC command
indicates if any interrupt source requests attention with respect to the
setting of the interrupt enable bits: see the ComIEnReg and DivIEnReg
registers
3
TRunning
1
MFRC523’s timer unit is running, i.e. the timer will decrement the
TCounterValReg register with the next timer clock
Remark: in gated mode, the TRunning bit is set to logic 1 when the
timer is enabled by TModeReg register’s TGated[1:0] bits; this bit is not
influenced by the gated signal
2
1
reserved
HiAlert
-
reserved for future use
1
the alert level for the number of bytes in the FIFO buffer
(FIFOLength[6:0]) is: HiAlert = 64 – FIFOLength WaterLevel
otherwise value = logic 0
Example:
FIFOLength = 60, WaterLevel = 4 then HiAlert = logic 1
FIFOLength = 59, WaterLevel = 4 then HiAlert = logic 0
0
LoAlert
1
the alert level for number of bytes in the FIFO buffer (FIFOLength[6:0])
is:
LoAlert = FIFOLength WaterLevel otherwise value = logic 0
Example:
FIFOLength = 4, WaterLevel = 4 then LoAlert = logic 1
FIFOLength = 5, WaterLevel = 4 then LoAlert = logic 0
9.2.1.9 Status2Reg register
Contains status bits of the receiver, transmitter and data mode detector.
Table 38. Status2Reg register (address 08h); reset value: 00h bit allocation
Bit
Symbol TempSensClear I2CForceHS
Access R/W R/W
7
6
5
4
3
2
1
0
reserved
-
MFCrypto1On
D
ModemState[2:0]
R
Table 39. Status2Reg register bit descriptions
Bit
Symbol
Value Description
7
TempSensClear
1
clears the temperature error if the temperature is below the
alarm limit of 125 C
MFRC523
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Table 39. Status2Reg register bit descriptions …continued
Bit
Symbol
I2CForceHS
Value Description
I2C-bus input filter settings:
6
1
the I2C-bus input filter is set to the High-speed mode
independent of the I2C-bus protocol
0
-
the I2C-bus input filter is set to the I2C-bus protocol used
5 to 4 reserved
reserved
3
MFCrypto1On
-
indicates that the MIFARE Crypto1 unit is switched on and
all data communication with the card is encrypted; this bit is
cleared by software; can only be set to logic 1 by a
successful execution of the MFAuthent command only valid
in Read/Write mode for MIFARE standard cards
2 to 0 ModemState[2:0]
-
shows the state of the transmitter and receiver state
machines:
000
001
010
idle
wait for the BitFramingReg register’s StartSend bit
TxWait: wait until RF field is present if the TModeReg
register’s TxWaitRF bit is set to logic 1. The minimum
time for TxWait is defined by the TxWaitReg register
011
100
transmitting
RxWait: wait until RF field is present if the TModeReg
register’s TxWaitRF bit is set to logic 1. The minimum
time for RxWait is defined by the RxWaitReg register
101
110
wait for data
receiving
9.2.1.10 FIFODataReg register
Input and output of 64 byte FIFO buffer.
Table 40. FIFODataReg register (address 09h); reset value: xxh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
FIFOData[7:0]
D
Table 41. FIFODataReg register bit descriptions
Bit
Symbol
Description
7 to 0
FIFOData[7:0] data input and output port for the internal 64-byte FIFO buffer. FIFO
buffer acts as parallel in/parallel out converter for all serial data stream
inputs and outputs
9.2.1.11 FIFOLevelReg register
Indicates the number of bytes stored in the FIFO.
Table 42. FIFOLevelReg register (address 0Ah); reset value: 00h bit allocation
Bit
Symbol FlushBuffer
Access
7
6
5
4
3
2
1
0
FIFOLevel[6:0]
R
W
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Table 43. FIFOLevelReg register bit descriptions
Bit
Symbol
Value Description
7
FlushBuffer
1
immediately clears the internal FIFO buffer’s read and write
pointer and ErrorReg register’s BufferOvfl bit. Reading this bit
always returns 0
6 to 0 FIFOLevel[6:0]
-
indicates the number of bytes stored in the FIFO buffer. Writing to
the FIFODataReg register increments and reading decrements
the FIFOLevel value
9.2.1.12 WaterLevelReg register
Defines the level for FIFO under- and overflow warning.
Table 44. WaterLevelReg register (address 0Bh); reset value: 08h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
reserved
-
WaterLevel[5:0]
R/W
Table 45. WaterLevelReg register bit descriptions
Bit
Symbol
Description
7 to 6 reserved
reserved for future use
5 to 0 WaterLevel[5:0] defines a warning level to indicate a FIFO buffer overflow or underflow:
Status1Reg register’s HiAlert bit is set to logic 1 if the remaining
number of bytes in the FIFO buffer space is equal to, or less than the
defined number of WaterLevel[5:0] bits
Status1Reg register’s LoAlert bit is set to logic 1 if equal to, or less
than the WaterLevel[5:0] bits in the FIFO buffer
Remark: to calculate values for HiAlert and LoAlert, see
Section 9.2.1.9 on page 41.
9.2.1.13 ControlReg register
Miscellaneous control bits.
Table 46. ControlReg register (address 0Ch); reset value: 10h bit allocation
Bit
Symbol TStopNow TStartNow
Access
7
6
5
4
3
2
1
0
reserved
-
RxLastBits[2:0]
R
W
W
Table 47. ControlReg register bit descriptions
Bit
7
Symbol
Value Description
TStopNow
TStartNow
1
1
-
timer stops immediately
6
timer starts immediately. Reading this bit always returns it to 0
reserved for future use
5 to 3 reserved
2 to 0 RxLastBits[2:0]
-
indicates the number of valid bits in the last received byte. If this
value is zero, the whole byte is valid
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9.2.1.14 BitFramingReg register
Adjustments for bit-oriented frames.
Table 48. BitFramingReg register (address 0Dh); reset value: 00h bit allocation
Bit
Symbol StartSend
Access
7
6
5
4
3
2
1
0
RxAlign[2:0]
R/W
reserved
-
TxLastBits[2:0]
R/W
W
Table 49. BitFramingReg register bit descriptions
Bit
Symbol
Value Description
7
StartSend
1
starts the transmission of data
only valid in combination with the Transceive command
6 to 4
RxAlign[2:0]
used for reception of bit-oriented frames: defines the bit
position for the first bit received to be stored in the FIFO buffer
example:
0
1
7
LSB of the received bit is stored at bit position 0, the second
received bit is stored at bit position 1
LSB of the received bit is stored at bit position 1, the second
received bit is stored at bit position 2
LSB of the received bit is stored at bit position 7, the second
received bit is stored in the next byte that follows at bit
position 0
These bits are only to be used for bitwise anticollision at
106 kBd, for all other modes they are set to 0
3
reserved
-
-
reserved for future use
2 to 0
TxLastBits[2:0]
used for transmission of bit oriented frames: defines the
number of bits of the last byte that will be transmitted. 000b
indicates that all bits of the last byte will be transmitted
9.2.1.15 CollReg register
Defines the first bit-collision detected on the RF interface.
Table 50. CollReg register (address 0Eh); reset value: xxh bit allocation
Bit
Symbol ValuesAfterColl reserved CollPosNotValid
Access R/W
7
6
5
4
3
2
CollPos[4:0]
R
1
0
-
R
Table 51. CollReg register bit descriptions
Bit
Symbol
Value Description
7
ValuesAfterColl
0
all received bits will be cleared after a collision
only used during bitwise anticollision at 106 kBd,
otherwise it is set to logic 1
6
5
reserved
-
reserved for future use
CollPosNotValid
1
no collision detected or the position of the collision is
out of the range of CollPos[4:0]
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Table 51. CollReg register bit descriptions …continued
Bit Symbol Value Description
4 to 0 CollPos[4:0]
-
shows the bit position of the first detected collision in a
received frame
only data bits are interpreted
example:
00h
01h
08h
indicates a bit-collision in the 32nd bit
indicates a bit-collision in the 1st bit
indicates a bit-collision in the 8th bit
these bits will only be interpreted if the
CollPosNotValid bit is set to logic 0
9.2.1.16 Reserved register 0Fh
Functionality is reserved for future use.
Table 52. Reserved register (address 0Fh); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
reserved
-
Table 53. Reserved register bit descriptions
Bit
Symbol
Description
reserved for future use
7 to 0
reserved
9.2.2 Page 1: Communication
9.2.2.1 Reserved register 10h
Functionality is reserved for future use.
Table 54. Reserved register (address 10h); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
reserved
-
Table 55. Reserved register bit descriptions
Bit
Symbol
Description
reserved for future use
7 to 0
reserved
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9.2.2.2 ModeReg register
Defines general mode settings for transmitting and receiving.
Table 56. ModeReg register (address 11h); reset value: 3Fh bit allocation
Bit
Symbol MSBFirst reserved TxWaitRF reserved PolMFin reserved
Access R/W R/W R/W
7
6
5
4
3
2
1
0
CRCPreset[1:0]
R/W
-
-
-
Table 57. ModeReg register bit descriptions
Bit
Symbol
Value Description
7
MSBFirst
1
CRC coprocessor calculates the CRC with MSB first. In the
CRCResultReg register the values for the CRCResultMSB[7:0]
bits and the CRCResultLSB[7:0] bits are bit reversed
Remark: during RF communication this bit is ignored
reserved for future use
6
5
4
3
reserved
TxWaitRF
reserved
PolMFin
-
1
-
transmitter can only be started if an RF field is generated
reserved for future use
defines the polarity of pin MFIN
Remark: the internal envelope signal is encoded active LOW,
changing this bit generates a MFinActIRq event
1
0
-
polarity of pin MFIN is active HIGH
polarity of pin MFIN is active LOW
reserved for future use
2
reserved
1 to 0 CRCPreset
[1:0]
defines the preset value for the CRC coprocessor for the CalcCRC
command
Remark: during any communication, the preset values are
selected automatically according to the definition of bits in the
RxModeReg and TxModeReg registers
00
01
10
11
0000h
6363h
A671h
FFFFh
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9.2.2.3 TxModeReg register
Defines the data rate during transmission.
Table 58. TxModeReg register (address 12h); reset value: 00h bit allocation
Bit
Symbol TxCRCEn
Access R/W
7
6
5
TxSpeed[2:0]
D
4
3
2
1
TxFraming
D
0
InvMod
R/W
Table 59. TxModeReg register bit descriptions
Bit
Symbol
Value
Description
7
TxCRCEn
1
enables CRC generation during data transmission
Remark: can only be set to logic 0 at 106 kBd
defines the bit rate during data transmission
6 to 4
TxSpeed[2:0]
the MFRC523 handles transfer speeds up to
848 kBd
000
001
010
011
100
101
110
111
1
106 kBd
212 kBd
424 kBd
848 kBd
reserved
reserved
reserved
reserved
3
InvMod
modulation of transmitted data is inverted
defines the framing used for data transmission
ISO/IEC 14443 A/MIFARE
reserved
2 to 0
TxFraming[1:0]
00
01
10
11
reserved
ISO/IEC 14443 B
9.2.2.4 RxModeReg register
Defines the data rate during reception.
Table 60. RxModeReg register (address 13h); reset value: 00h bit allocation
Bit
Symbol RxCRCEn
Access R/W
7
6
5
RxSpeed[2:0]
D
4
3
2
1
0
RxNoErr RxMultiple
R/W R/W
RxFraming
D
Table 61. RxModeReg register bit descriptions
Bit
Symbol
Value Description
7
RxCRCEn
1
enables the CRC calculation during reception
Remark: can only be set to logic 0 at 106 kBd
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Table 61. RxModeReg register bit descriptions …continued
Bit Symbol Value Description
6 to 4 RxSpeed[2:0] defines the bit rate while receiving data. The MFRC523
manages transfer speeds up to 848 kBd
000
001
010
011
100
101
110
111
1
106 kBd
212 kBd
424 kBd
848 kBd
reserved
reserved
reserved
reserved
3
2
RxNoErr
an invalid received data stream (less than 4 bits received) will
be ignored and the receiver remains active
RxMultiple
0
1
receiver is deactivated after receiving a data frame
able to receive more than one data frame
only valid for data rates above 106 kBd in order to handle the
polling command
after setting this bit, the Receive and Transceive commands will
not terminate automatically. Multiple reception can only be
deactivated by writing any command (except the Receive
command) to the CommandReg register, or by the host clearing
the bit
if set to logic 1, an error byte is added to the FIFO buffer at the
end of a received data stream which is a copy of the ErrorReg
register value
1 to 0 RxFraming
defines the expected framing for data reception
00
01
10
11
ISO/IEC 14443 A/MIFARE
reserved
reserved
ISO/IEC 14443 B
9.2.2.5 TxControlReg register
Controls the logical behavior of the antenna driver pins TX1 and TX2.
Table 62. TxControlReg register (address 14h); reset value: 80h bit allocation
Bit
Symbol InvTx2RF InvTx1RF InvTx2RF InvTx1RF Tx2CW reserved Tx2RFEn Tx1RFEn
7
6
5
4
3
2
1
0
On
On
Off
Off
Access
R/W
R/W
R/W
R/W
R/W
-
R/W
R/W
Table 63. TxControlReg register bit descriptions
Bit Symbol Value Description
InvTx2RFOn 1
7
6
5
4
output signal on pin TX2 inverted when driver TX2 is enabled
output signal on pin TX1 inverted when driver TX1 is enabled
output signal on pin TX2 inverted when driver TX2 is disabled
output signal on pin TX1 inverted when driver TX1 is disabled
InvTx1RFOn 1
InvTx2RFOff 1
InvTx1RFOff 1
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Table 63. TxControlReg register bit descriptions …continued
Bit Symbol Value Description
3
Tx2CW
1
output signal on pin TX2 continuously delivers the unmodulated
13.56 MHz energy carrier
0
-
Tx2CW bit is enabled to modulate the 13.56 MHz energy carrier
reserved for future use
2
1
reserved
Tx2RFEn
1
output signal on pin TX2 delivers the 13.56 MHz energy carrier
modulated by the transmission data
0
Tx1RFEn
1
output signal on pin TX1 delivers the 13.56 MHz energy carrier
modulated by the transmission data
9.2.2.6 TxASKReg register
Controls transmit modulation settings.
Table 64. TxASKReg register (address 15h); reset value: 00h bit allocation
Bit
Symbol reserved Force100ASK
Access R/W
7
6
5
4
3
2
1
0
reserved
-
-
Table 65. TxASKReg register bit descriptions
Bit
7
Symbol
Value Description
- reserved for future use
reserved
6
Force100ASK 1
forces 100 % ASK modulation independently of the ModGsPReg
register setting
5 to 0 reserved
-
reserved for future use
9.2.2.7 TxSelReg register
Selects the internal sources for the analog module.
Table 66. TxSelReg register (address 16h); reset value: 10h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol:
Access:
reserved
-
DriverSel[1:0]
R/W
MFOutSel[3:0]
R/W
Table 67. TxSelReg register bit descriptions
Bit Symbol Value Description
7 to 6 reserved
-
reserved for future use
5 to 4 DriverSel[1:0]
-
selects the input of drivers TX1 and TX2
00
3-state; in soft power-down the drivers are only in 3-state
mode if the DriverSel[1:0] value is set to 3-state mode
01
modulation signal (envelope) from the internal encoder, Miller
pulse encoded
10
11
modulation signal (envelope) from pin MFIN
HIGH; the HIGH level depends on the setting of bits
InvTx1RFOn/InvTx1RFOff and InvTx2RFOn/InvTx2RFOff
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Table 67. TxSelReg register bit descriptions …continued
Bit Symbol Value Description
selects the input for pin MFOUT
3-state
3 to 0 MFOutSel[3:0]
0000
0001
0010
0011
LOW
HIGH
test bus signal as defined by the TestSel1Reg register’s
TstBusBitSel[2:0] value
0100
0101
modulation signal (envelope) from the internal encoder, Miller
pulse encoded
serial data stream to be transmitted, data stream before Miller
encoder
0110
0111
reserved
serial data stream received, data stream after Manchester
decoder
1000
to
reserved
1111
9.2.2.8 RxSelReg register
Selects internal receiver settings.
Table 68. RxSelReg register (address 17h); reset value: 84h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
UARTSel[1:0]
R/W
RxWait[5:0]
R/W
Table 69. RxSelReg register bit descriptions
Bit Symbol Value Description
7 to 6 UARTSel[1:0]
selects the input of the contactless UART
constant LOW
00
01
10
11
Manchester with subcarrier from pin MFIN
modulated signal from the internal analog module, default
NRZ coding without subcarrier from pin MFIN which is only
valid for transfer speeds above 106 kBd
5 to 0 RxWait[5:0]
-
after data transmission the activation of the receiver is delayed
for RxWait bit-clocks, during this ‘frame guard time’ any signal on
pin RX is ignored
this parameter is ignored by the Receive command
all other commands, such as Transceive, MFAuthent use this
parameter
the counter starts immediately after the external RF field is
switched on
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9.2.2.9 RxThresholdReg register
Selects thresholds for the bit decoder.
Table 70. RxThresholdReg register (address 18h); reset value: 84h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
MinLevel[3:0]
R/W
reserved
-
CollLevel[2:0]
R/W
Table 71. RxThresholdReg register bit descriptions
Bit
Symbol
Description
7 to 4
MinLevel[3:0]
defines the minimum signal strength at the decoder input that will be
accepted. If the signal strength is below this level it is not evaluated
3
reserved
reserved for future use
2 to 0
CollLevel[2:0] defines the minimum signal strength at the decoder input that must be
reached by the weaker half-bit of the Manchester encoded signal to
generate a bit-collision relative to the amplitude of the stronger half-bit
9.2.2.10 DemodReg register
Defines demodulator settings.
Table 72. DemodReg register (address 19h); reset value: 4Dh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
AddIQ[1:0]
FixIQ
TPrescal
Even
TauRcv[1:0]
TauSync[1:0]
Access
R/W
R/W
-
R/W
R/W
Table 73. DemodReg register bit descriptions
Bit Symbol Value Description
7 to 6 AddIQ[1:0]
-
defines the use of I-channel and Q-channel during reception
Remark: the FixIQ bit must be set to logic 0 to enable the
following settings:
00
01
selects the stronger channel
selects the stronger channel and freezes the selected channel
during communication
10
11
1
reserved
reserved
5
FixIQ
if the bits of AddIQ are set to X0, the reception is fixed to
I-channel
if the bits of AddIQ are set to X1, the reception is fixed to
Q-channel
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Table 73. DemodReg register bit descriptions …continued
Bit
Symbol
Value Description
4
TPrescalEven 0
the following formula is used to calculate fTimer of the prescaler:
fTimer = 13.56 MHz / (2 * TPreScaler + 1).
1
the following formula is used to calculate fTimer of the prescaler:
fTimer = 13.56 MHz / (2 * TPreScaler + 2).
(Default TPrescalEven is logic 0)
3 to 2 TauRcv[1:0]
1 to 0 TauSync[1:0]
-
changes the time-constant of the internal PLL during data
reception
Remark: if set to 00b the PLL is frozen during data reception
-
changes the time constant of the internal PLL during burst
9.2.2.11 Reserved register 1Ah
Functionality is reserved for future use.
Table 74. Reserved register (address 1Ah); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
1
0
0
0
Symbol
Access
reserved
-
Table 75. Reserved register bit descriptions
Bit
Symbol
Description
reserved for future use
7 to 0
reserved
9.2.2.12 Reserved register 1Bh
Functionality is reserved for future use.
Table 76. Reserved register (address 1Bh); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
1
Symbol
Access
reserved
-
Table 77. Reserved register bit descriptions
Bit
Symbol
Description
reserved for future use
7 to 0
reserved
9.2.2.13 MfTxReg register
Controls some MIFARE communication transmit parameters.
Table 78. MfTxReg register (address 1Ch); reset value: 62h bit allocation
Bit
7
6
5
4
3
2
1
Symbol
Access
reserved
-
TxWait[1:0]
R/W
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Table 79. MfTxReg register bit descriptions
Bit
Symbol
reserved
TxWait
Description
7 to 2
1 to 0
reserved for future use
defines the additional response time. 7 bits are added to the value of
the register bit by default
9.2.2.14 MfRxReg register
Table 80. MfRxReg register (address 1Dh); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
reserved
-
ParityDisable
R/W
reserved
-
Table 81. MfRxReg register bit descriptions
Bit Symbol Value Description
7 to 5 reserved reserved for future use
ParityDisable 1
-
4
generation of the parity bit for transmission and the parity check for
receiving is switched off. The received parity bit is handled like a
data bit
3 to 0 reserved
-
reserved for future use
9.2.2.15 TypeBReg register
Configures the ISO/IEC 14443 B functionality.
Table 82. TypeBReg register (address 1Eh); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol RxSOFReq RxEOFReq reserved EOFSOF NoTxSOF NoTxEOF
Width
TxEGT[1:0]
Access
R/W
R/W
-
R/W
R/W
R/W
R/W
Table 83. TypeBReg register bit descriptions
Bit
Symbol
Value Description
7
RxSOFReq
1
0
requires SOF; a datastream starting without SOF is ignored
accepts a datastream starting with or without SOF; an SOF is
removed and not written into the FIFO
6
5
RxEOFReq
reserved
1
0
-
requires EOF; a datastream ending without EOF generates a
protocol error
accepts a datastream ending with or without EOF; an EOF is
removed and not written into the FIFO
reserved for future use
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Table 83. TypeBReg register bit descriptions …continued
Bit
Symbol
Value Description
4
EOFSOFWidth
1
if this bit is set to logic 1 and EOFSOFAdjust bit (AutoTestReg
register) is logic 0, the SOF and EOF will have the maximum
length defined in ISO/IEC 14443 B.
if this bit is set to logic 1 and the EOFSOFAadjust bit is logic 1:
then
SOF low = (11 ETU 8 cycles) / fclk
SOF high = (2 ETU + 8 cycles) / fclk
EOF low = (11 ETU 8 cycles) / fclk
0
if this bit is cleared and EOFSOFAdjust bit is logic 0, the SOF
and EOF will have the minimum length defined in
ISO/IEC 14443 B.
if this bit is set to logic 0 and the EOFSOFAdjust bit is logic 1
results in an incorrect system behavior in respect to ISO
specification
3
2
NoTxSOF
NoTxEOF
1
1
SOF is suppressed
EOF is suppressed
defines EGT bit length
no bits
1 to 0 TxEGT
00
01
10
11
1 bit
2 bits
3 bits
9.2.2.16 SerialSpeedReg register
Selects the speed of the serial UART interface.
Table 84. SerialSpeedReg register (address 1Fh); reset value: EBh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
BR_T0[2:0]
R/W
BR_T1[4:0]
R/W
Table 85. SerialSpeedReg register bit descriptions
Bit
Symbol
Description
7 to 5
BR_T0[2:0]
factor BR_T0 adjusts the transfer speed: for description, see
Section 8.3.3.2 on page 12
4 to 0
BR_T1[4:0]
factor BR_T1 adjusts the transfer speed: for description, see
Section 8.3.3.2 on page 12
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9.2.3 Page 2: Configuration
9.2.3.1 Reserved register 20h
Functionality is reserved for future use.
Table 86. Reserved register (address 20h); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
reserved
-
Table 87. Reserved register bit descriptions
Bit
Symbol
Description
reserved for future use
7 to 0
reserved
9.2.3.2 CRCResultReg registers
Shows the MSB and LSB values of the CRC calculation.
Remark: The CRC is split into two 8-bit registers.
Table 88. CRCResultReg (higher bits) register (address 21h); reset value: FFh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
CRCResultMSB[7:0]
R
Table 89. CRCResultReg register higher bit descriptions
Bit
Symbol
Description
7 to 0
CRCResultMSB[7:0] shows the value of the CRCResultReg register’s most
significant byte. Only valid if Status1Reg register’s CRCReady
bit is set to logic 1
Table 90. CRCResultReg (lower bits) register (address 22h); reset value: FFh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
CRCResultLSB[7:0]
R
Table 91. CRCResultReg register lower bit descriptions
Bit Symbol Description
7 to 0 CRCResultLSB[7:0] shows the value of the least significant byte of the CRCResultReg
register. Only valid if Status1Reg register’s CRCReady bit is set to
logic 1
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9.2.3.3 Reserved register 23h
Functionality is reserved for future use.
Table 92. Reserved register (address 23h); reset value: 88h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
reserved
-
Table 93. Reserved register bit descriptions
Bit
Symbol
Description
reserved for future use
7 to 0
reserved
9.2.3.4 ModWidthReg register
Sets the modulation width.
Table 94. ModWidthReg register (address 24h); reset value: 26h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
ModWidth[7:0]
R/W
Table 95. ModWidthReg register bit descriptions
Bit
Symbol
Description
7 to 0
ModWidth[7:0] defines the width of the Miller modulation as multiples of the carrier
frequency (ModWidth + 1 / fclk). The maximum value is half the bit
period
9.2.3.5 Reserved register 25h
Functionality is reserved for future use.
Table 96. Reserved register (address 25h); reset value: 87h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
reserved
-
Table 97. Reserved register bit descriptions
Bit
Symbol
Description
reserved for future use
7 to 0
reserved
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9.2.3.6 RFCfgReg register
Configures the receiver gain.
Table 98. RFCfgReg register (address 26h); reset value: 48h bit allocation
Bit
Symbol reserved
Access
7
6
5
4
3
2
1
0
RxGain[2:0]
R/W
reserved
-
-
Table 99. RFCfgReg register bit descriptions
Bit
7
Symbol
Value
Description
reserved
RxGain[2:0]
-
reserved for future use
6 to 4
defines the receiver’s signal voltage gain factor:
000
001
010
011
100
101
110
111
-
18 dB
23 dB
18 dB
23 dB
33 dB
38 dB
43 dB
48 dB
3 to 0
reserved
reserved for future use
9.2.3.7 GsNReg register
Defines the conductance of the antenna driver pins TX1 and TX2 for the n-driver when the
driver is switched on.
Table 100. GsNReg register (address 27h); reset value: 88h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
CWGsN[3:0]
R/W
ModGsN[3:0]
R/W
Table 101. GsNReg register bit descriptions
Bit
Symbol
Description
7 to 4
CWGsN[3:0] defines the conductance of the output n-driver during periods without
modulation which can be used to regulate the output power and
subsequently current consumption and operating distance. The value is
only used if driver TX1 or TX2 is switched on
during Soft power-down mode the highest bit is forced to logic 1
Remark: the conductance value is binary-weighted
3 to 0
ModGsN[3:0] defines the conductance of the output n-driver during periods without
modulation which can be used to regulate the modulation index. The
value is only used if driver TX1 or TX2 is switched on
during Soft power-down mode the highest bit is forced to logic 1
Remark: the conductance value is binary weighted
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9.2.3.8 CWGsPReg register
Defines the conductance of the p-driver output during periods of no modulation.
Table 102. CWGsPReg register (address 28h); reset value: 20h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
reserved
-
CWGsP[5:0]
R/W
Table 103. CWGsPReg register bit descriptions
Bit
Symbol
Description
7 to 6
5 to 0
reserved
reserved for future use
CWGsP[5:0]
defines the conductance of the p-driver output which can be used to
regulate the output power and subsequently current consumption and
operating distance
during Soft power-down mode the highest bit is forced to logic 1
Remark: the conductance value is binary weighted
9.2.3.9 ModGsPReg register
Defines the conductance of the p-driver output during modulation.
Table 104. ModGsPReg register (address 29h); reset value: 20h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
reserved
-
ModGsP[5:0]
R/W
Table 105. ModGsPReg register bit descriptions
Bit
Symbol
Description
7 to 6
5 to 0
reserved
reserved for future use
ModGsP[5:0] defines the conductance of the p-driver output during modulation
which can be used to regulate the modulation index. If the TxASKReg
register’s Force100ASK bit is set to logic 1 the value of ModGsP has
no effect
during Soft power-down mode the highest bit is forced to logic 1
Remark: the conductance value is binary weighted
9.2.3.10 TModeReg and TPrescalerReg registers
These registers define the timer settings.
Remark: The TPrescaler setting higher 4 bits are in the TModeReg register and the lower
8 bits are in the TPrescalerReg register.
Table 106. TModeReg register (address 2Ah); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
TAuto
R/W
TGated[1:0]
R/W
TAutoRestart
R/W
TPrescaler_Hi[3:0]
R/W
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Table 107. TModeReg register bit descriptions
Bit
Symbol
Value Description
7
TAuto
1
the timer starts automatically at the end of the transmission in
all communication modes at all speeds or when InvTxnRFOn
bits are set to logic 1 and the RF field is switched on
when RxMultiple bit in register RxModeReg is logic 0: in
MIFARE mode and ISO/IEC 14443 B at 106 kBd, the timer
stops after the 5th bit (1 start bit, 4 data bits). In all other
modes, the timer stops after the 4th bit
if the RxMultiple bit is set to logic 1, the timer never stops. In
this case the timer can be stopped by setting the TStopNow
bit in register ControlReg to logic 1
0
indicates that the timer is not influenced by the protocol
internal timer is runs in gated or non-gated mode
6 to 5 TGated[1:0]
Remark: in gated mode, the Status1Reg register’s TRunning
bit is logic 1 when the timer is enabled by the TModeReg
register bits
these bits do not influence the gating signal
00
01
10
11
1
non-gated mode
gated by pin MFIN
gated by pin AUX1
-
4
TAutoRestart
timer automatically restarts its count-down from the 16-bit
timer reload value instead of counting down to zero
0
timer decrements to 0 and the ComIrqReg register’s
TimerIRq bit is set to logic 1
3 to 0 TPrescaler_Hi[3:0] -
defines the higher 4 bits of the TPrescaler value
the following formula is used to calculate fTimer if
TPrescalEven bit in Demod Reg is set to logic 0:
fTimer = 13.56 MHz / (2 * TPreScaler + 1).
where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo]
(TPrescaler value on 12 bits). The default TPrescalEven is
logic 0
the following formula is used to calculate fTimer if
TPrescalEven bit in Demod Reg is set to logic 1:
fTimer = 13.56 MHz / (2 * TPreScaler + 2); see Section 8.7
“Timer unit”
Table 108. TPrescalerReg register (address 2Bh); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
TPrescaler_Lo[7:0]
R/W
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Table 109. TPrescalerReg register bit descriptions
Bit
Symbol
TPrescaler_Lo[7:0] defines the lower 8 bits of the TPrescaler value
the following formula is used to calculate fTimer if TPrescalEven bit in
Description
7 to 0
Demot Reg is set to logic 0:
fTimer = 13.56 MHz / (2 * TPreScaler + 1)
where TPreScaler = [TPrescaler_Hi:TPrescaler_Lo] (TPrescaler
value on 12 bits). The default TPrescalEven is logic 0;
f
Timer = 13.56 MHz / (2 * TPreScaler + 2); see Section 8.7 “Timer
unit”
9.2.3.11 TReloadReg register
Defines the 16-bit timer reload value.
Remark: The reload value bits are contained in two 8-bit registers.
Table 110. TReloadReg (higher bits) register (address 2Ch); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
TReloadVal_Hi[7:0]
R/W
Table 111. TReloadReg register higher bit descriptions
Bit
Symbol
Description
7 to 0
TReloadVal_Hi[7:0]
defines the higher 8 bits of the 16-bit timer reload value. On a
start event, the timer loads the timer reload value. Changing
this register affects the timer only at the next start event
Table 112. TReloadReg (lower bits) register (address 2Dh); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
TReloadVal_Lo[7:0]
R/W
Table 113. TReloadReg register lower bit descriptions
Bit
Symbol
Description
7 to 0
TReloadVal_Lo[7:0] defines the lower 8 bits of the 16-bit timer reload value. On a
start event, the timer loads the timer reload value. Changing this
register affects the timer only at the next start event
9.2.3.12 TCounterValReg register
Contains the timer value.
Remark: The timer value bits are contained in two 8-bit registers.
Table 114. TCounterValReg (higher bits) register (address 2Eh); reset value: xxh bit
allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
TCounterVal_Hi[7:0]
R
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Table 115. TCounterValReg register higher bit descriptions
Bit
Symbol
Description
7 to 0
TCounterVal_Hi[7:0] timer value higher 8 bits
Table 116. TCounterValReg (lower bits) register (address 2Fh); reset value: xxh bit
allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
TCounterVal_Lo[7:0]
R
Table 117. TCounterValReg register lower bit descriptions
Bit
Symbol
Description
7 to 0
TCounterVal_Lo[7:0] timer value lower 8 bits
9.2.4 Page 3: Test
9.2.4.1 Reserved register 30h
Functionality is reserved for future use.
Table 118. Reserved register (address 30h); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
reserved
-
Table 119. Reserved register bit descriptions
Bit
Symbol
Description
reserved for future use
7 to 0
reserved
9.2.4.2 TestSel1Reg register
General test signal configuration.
Table 120. TestSel1Reg register (address 31h); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
reserved
-
TstBusBitSel[2:0]
R/W
Table 121. TestSel1Reg register bit descriptions
Bit
Symbol
Description
7 to 3
2 to 0
reserved
reserved for future use
TstBusBitSel[2:0] selects a test bus signal which is output at pin MFOUT. If
AnalogSelAux2[3:0] = FFh in AnalogTestReg register, test bus
signal is also output at pins AUX1 or AUX2
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9.2.4.3 TestSel2Reg register
General test signal configuration and PRBS control.
Table 122. TestSel2Reg register (address 32h); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
TstBusFlip
R/W
PRBS9 PRBS15
R/W R/W
TestBusSel[4:0]
R/W
Table 123. TestSel2Reg register bit descriptions
Bit
Symbol
Value Description
7
TstBusFlip
1
test bus is mapped to the parallel port in the following order:
TstBusBit4,TstBusBit3, TstBusBit2, TstBusBit6, TstBusBit5,
TstBusBit0; see Section 16.1 on page 80
6
5
PRBS9
-
starts and enables the PRBS9 sequence according to
ITU-TO150; the data transmission of the defined sequence is
started by the Transmit command
Remark: all relevant registers to transmit data must be
configured before entering PRBS9 mode
PRBS15
-
-
starts and enables the PRBS15 sequence according to
ITU-TO150; the data transmission of the defined sequence is
started by the Transmit command
Remark: all relevant registers to transmit data must be
configured before entering PRBS15 mode
4 to 0 TestBusSel[4:0]
selects the test bus; see Section 16.1 “Test signals” on page 80
9.2.4.4 TestPinEnReg register
Enables the test bus pin output driver.
Table 124. TestPinEnReg register (address 33h); reset value: 80h bit allocation
Bit
Symbol RS232LineEn
Access R/W
7
6
5
4
3
2
1
0
TestPinEn[5:0]
R/W
reserved
-
Table 125. TestPinEnReg register bit descriptions
Bit
Symbol
Value Description
7
RS232LineEn
0
-
serial UART lines MX and DTRQ are disabled
6 to 1 TestPinEn[5:0]
enables the output driver on one of the data pins D1 to D7 which
outputs a test signal
Example:
setting bit 1 to logic 1 enables pin D1 output
setting bit 5 to logic 1 enables pin D5 output
Remark: If the SPI is used, only pins D1 to D4 can be used. If the
serial UART interface is used and the RS232LineEn bit is set to
logic 1 only pins D1 to D4 can be used.
0
reserved
-
reserved for future use
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9.2.4.5 TestPinValueReg register
Defines the high and low values for the test port D1 to D7 when it is used as I/O.
Table 126. TestPinValueReg register (address 34h); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
UseIO
R/W
TestPinValue[5:0]
R/W
reserved
-
Table 127. TestPinValueReg register bit descriptions
Bit
Symbol
Value Description
7
UseIO
1
enables the I/O functionality for the test port when one of the
serial interfaces is used. The input/output behavior is defined
by value TestPinEn[5:0] in the TestPinEnReg register
6 to 1 TestPinValue[5:0]
-
defines the value of the test port when it is used as I/O and
each output must be enabled by TestPinEn[5:0] in the
TestPinEnReg register
Remark: Reading the register indicates the status of pins D6
to D1 if the UseIO bit is set to logic 1. If the UseIO bit is set to
logic 0, the value of the TestPinValueReg register is read back.
0
reserved
-
reserved for future use
9.2.4.6 TestBusReg register
Shows the status of the internal test bus.
Table 128. TestBusReg register (address 35h); reset value: xxh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
TestBus[7:0]
R
Table 129. TestBusReg register bit descriptions
Bit
Symbol
Description
7 to 0
TestBus[7:0]
shows the status of the internal test bus. The test bus is selected using
the TestSel2Reg register; see Section 16.1 on page 80
9.2.4.7 AutoTestReg register
Controls the digital self-test.
Table 130. AutoTestReg register (address 36h); reset value: 40h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol reserved AmpRcv reserved EOFSOF
Adjust
SelfTest[3:0]
Access
-
R/W
-
R/W
R/W
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Table 131. AutoTestReg register bit descriptions
Bit
7
Symbol
reserved
AmpRcv
Value Description
-
reserved for production tests
6
1
internal signal processing in the receiver chain is performed
non-linearly which increases the operating distance in
communication modes at 106 kBd
Remark: due to non-linearity, the effect of the RxThresholdReg
register’s MinLevel[3:0] and the CollLevel[2:0] values is also
non-linear
5
4
reserved
-
reserved for production tests
EOFSOFAdjust
0
If set to logic 0 and the EOFSOFwidth bit is set to logic 1 it
results in the maximum length of SOF and EOF according to
ISO/IEC 14443 B
If set to logic 0 and the EOFSOFwidth bit is set to logic 0 it
results in the minimum length of SOF and EOF according to
ISO/IEC 14443 B
1
-
If this bit is set to logic 1 and the EOFSOFwidth bit is logic 1, it
results in
SOF high = (2 ETU + 8 cycles) / fclk
SOF low = (11 ETU 8 cycles) / fclk
EOF low = (11 ETU 8 cycles) / fclk
3 to 0 SelfTest[3:0]
enables the digital self-test. The self-test can also be started by
the CalcCRC command; see Section 10.3.1.4 “CalcCRC
command” on page 69. Self-test is enabled by 1001b.
Remark: for default operation the self-test must be disabled
by 0000b
9.2.4.8 VersionReg register
Shows the MFRC523 software version.
Table 132. VersionReg register (address 37h); reset value: xxh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
Version[7:0]
R
Table 133. VersionReg register bit descriptions
Bit
Symbol
Description
indicates current MFRC523 software version
Remark: the current version of the MFRC523 is B1h or B2h
7 to 0
Version[7:0]
9.2.4.9 AnalogTestReg register
Determines the analog output test signal at, and status of, pins AUX1 and AUX2.
Table 134. AnalogTestReg register (address 38h); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
AnalogSelAux1[3:0]
R/W
AnalogSelAux2[3:0]
R/W
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Table 135. AnalogTestReg register bit descriptions
Bit Symbol Value Description
7 to 4 AnalogSelAux1[3:0] controls pin AUX1
3-state
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
output of TestDAC1 (AUX1), output of TestDAC2 (AUX2)[1]
test signal Corr1[1]
reserved
DAC: test signal MinLevel[1]
DAC: test signal ADC_I[1]
DAC: test signal ADC_Q[1]
reserved
reserved, test signal for production test[1]
reserved
HIGH
LOW
TxActive:
106 kBd: HIGH during start bit, data bit, parity and CRC
212 kBd, 424 kBd and 848 kBd: HIGH during data and
CRC
1101
1110
1111
RxActive:
106 kBd: HIGH during data bit, parity and CRC
212 kBd, 424 kBd and 848 kBd: HIGH during data and
CRC
subcarrier detected:
106 kBd: not applicable
212 kBd: 424 kBd and 848 kBd: HIGH during last part of
data and CRC
test bus bit as defined by the TestSel1Reg register’s
TstBusBitSel[2:0] bits
Remark: all test signals are described in Section 16.1 “Test
signals” on page 80
3 to 0 AnalogSelAux2[3:0] -
controls pin AUX2 (see bit descriptions for AUX1)
[1] Remark: Current source output; the use of 1 k pull-down resistor on AUXn is recommended.
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9.2.4.10 TestDAC1Reg register
Defines the test value for TestDAC1.
Table 136. TestDAC1Reg register (address 39h); reset value: xxh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
reserved
-
TestDAC1[5:0]
R/W
Table 137. TestDAC1Reg register bit descriptions
Bit
7
Symbol
reserved
reserved
Description
reserved for production tests
reserved for future use
6
5 to 0
TestDAC1[5:0] defines the test value for TestDAC1. Output of DAC1 can be routed to
AUX1 by setting value AnalogSelAux1[3:0] to 0001b in the
AnalogTestReg register
9.2.4.11 TestDAC2Reg register
Defines the test value for TestDAC2.
Table 138. TestDAC2Reg register (address 3Ah); reset value: xxh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
reserved
-
TestDAC2[5:0]
R/W
Table 139. TestDAC2Reg register bit descriptions
Bit
Symbol
Description
7 to 6
5 to 0
reserved
reserved for future use
TestDAC2[5:0] defines the test value for TestDAC2. DAC2 output can be routed to
AUX2 by setting value AnalogSelAux2[3:0] to 0001b in the
AnalogTestReg register
9.2.4.12 TestADCReg register
Shows the values of ADC I-channel and Q-channel.
Table 140. TestADCReg register (address 3Bh); reset value: xxh bit allocation
Bit
7
6
5
4
3
2
1
0
Symbol
Access
ADC_I[3:0]
ADC_Q[3:0]
R
R
Table 141. TestADCReg register bit descriptions
Bit
Symbol
Description
7 to 4
3 to 0
ADC_I[3:0]
ADC_Q[3:0]
ADC I-channel value
ADC Q-channel value
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9.2.4.13 Reserved register 3Ch
Functionality reserved for production test.
Table 142. Reserved register (address 3Ch); reset value: FFh bit allocation
Bit
7
6
5
4
3
2
1
1
1
1
0
0
0
0
Symbol
Access
reserved
-
Table 143. Reserved register bit descriptions
Bit
Symbol
Description
reserved for production tests
7 to 0
reserved
Table 144. Reserved register (address 3Dh); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
Symbol
Access
reserved
-
Table 145. Reserved register bit descriptions
Bit
Symbol
Description
reserved for production tests
7 to 0
reserved
Table 146. Reserved register (address 3Eh); reset value: 03h bit allocation
Bit
7
6
5
4
3
2
Symbol
Access
reserved
-
Table 147. Reserved register bit descriptions
Bit
Symbol
Description
reserved for production tests
7 to 0
reserved
Table 148. Reserved register (address 3Fh); reset value: 00h bit allocation
Bit
7
6
5
4
3
2
Symbol
Access
reserved
-
Table 149. Reserved register bit descriptions
Bit
Symbol
Description
reserved for production tests
7 to 0
reserved
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10. MFRC523 command set
The MFRC523 operation is determined by a state machine capable of performing a set of
commands. A command is executed by writing a command code (see Table 150) to the
CommandReg register.
Arguments and data necessary to process a command are exchanged using the FIFO
buffer.
10.1 General description
The MFRC523 operation is determined by a state machine capable of performing a set of
commands. A command is executed by writing a command code (see Table 150) to the
CommandReg register.
Arguments and/or data necessary to process a command are exchanged via the FIFO
buffer.
10.2 General behavior
• Each command that needs a data bit stream (or data byte stream) as an input
immediately processes any data in the FIFO buffer. An exception to this rule is the
Transceive command. Using this command, transmission is started with the
BitFramingReg register’s StartSend bit.
• Each command that needs a certain number of arguments, starts processing only
when it has received the correct number of arguments from the FIFO buffer.
• The FIFO buffer is not automatically cleared when commands start. This makes it
possible to write command arguments and/or the data bytes to the FIFO buffer and
then start the command.
• Each command can be interrupted by the host writing a new command code to the
CommandReg register, for example, the Idle command.
10.3 MFRC523 command overview
Table 150. Command overview
Command
Command Action
code
Idle
0000
0001
no action, cancels current command execution
Mem
stores 25 bytes into the internal buffer
Generate RandomID 0010
generates a 10-byte random ID number
activates the CRC coprocessor or performs a self-test
transmits data from the FIFO buffer
CalcCRC
0011
0100
0111
Transmit
NoCmdChange
no command change, can be used to modify the
CommandReg register bits without affecting the command,
for example, the PowerDown bit
Receive
1000
1100
activates the receiver circuits
Transceive
transmits data from FIFO buffer to antenna and automatically
activates the receiver after transmission
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Table 150. Command overview …continued
Command
Command Action
code
-
1101
1110
1111
reserved for future use
MFAuthent
SoftReset
performs the MIFARE standard authentication as a reader
resets the MFRC523
10.3.1 MFRC523 command descriptions
10.3.1.1 Idle mode
Places the MFRC523 in Idle mode. The Idle command also terminates itself.
10.3.1.2 Mem command
Transfers 25 bytes from the FIFO buffer to the internal buffer. To read out the 25 bytes
from the internal buffer the Mem command must be started with an empty FIFO buffer. In
this case, the 25 bytes are transferred from the internal buffer to the FIFO.
During a hard power-down (using pin NRSTPD), the 25 bytes in the internal buffer remain
unchanged and are only lost if the power supply is removed from the MFRC523.
This command automatically terminates when finished and the Idle command becomes
active.
10.3.1.3 Generate RandomID
This command generates a 10-byte random number which is initially stored in the internal
buffer. This then overwrites the 10 bytes in the internal 25-byte buffer. This command
automatically terminates when finished and the MFRC523 returns to Idle mode.
10.3.1.4 CalcCRC command
The FIFO buffer content is transferred to the CRC coprocessor and the CRC calculation is
started. The calculation result is stored in the CRCResultReg register. The CRC
calculation is not limited to a dedicated number of bytes. The calculation is not stopped
when the FIFO buffer is empty during the data stream. The next byte written to the FIFO
buffer is added to the calculation.
The CRC preset value is controlled by the ModeReg register’s CRCPreset[1:0] bits. The
value is loaded in to the CRC coprocessor when the command starts. This command
must be terminated by writing a command to the CommandReg register, such as, the Idle
command.
If the AutoTestReg register’s SelfTest[3:0] bits are set correctly, the MFRC523 enters
Self-test mode. Starting the CalcCRC command initiates a digital self-test. The result of
the self-test is written to the FIFO buffer.
10.3.1.5 Transmit command
The FIFO buffer content is immediately transmitted after starting this command. Before
transmitting the FIFO buffer content, all relevant registers must be set for data
transmission.
This command automatically terminates when the FIFO buffer is empty. It can be
terminated by another command written to the CommandReg register.
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10.3.1.6 NoCmdChange command
This command does not influence any running command in the CommandReg register. It
can be used to manipulate any bit except the CommandReg register Command[3:0] bits,
for example, the RcvOff bit or the PowerDown bit.
10.3.1.7 Receive command
The MFRC523 activates the receiver path and waits for a data stream to be received. The
correct settings must be chosen before starting this command.
This command automatically terminates when the data stream ends. This is indicated
either by the end of frame pattern or by the length byte depending on the selected frame
type and speed.
Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Receive
command does not automatically terminate. It must be terminated by starting another
command in the CommandReg register.
10.3.1.8 Transceive command
This command continuously repeats the transmission of data from the FIFO buffer and the
reception of data from the RF field. The first action is transmit and after transmission the
command is changed to receive a data stream.
Each transmit process must be started by setting the BitFramingReg register’s StartSend
bit to logic 1. This command must be cleared by writing any command to the
CommandReg register.
Remark: If the RxModeReg register’s RxMultiple bit is set to logic 1, the Transceive
command never leaves the receive state because this state cannot be cancelled
automatically.
10.3.1.9 MFAuthent command
This command manages MIFARE authentication to enable a secure communication to
any MIFARE card. The following data is written to the FIFO buffer before the command
can be activated:
• Authentication command code (60h, 61h)
• Block address
• Sector key byte 0
• Sector key byte 1
• Sector key byte 2
• Sector key byte 3
• Sector key byte 4
• Sector key byte 5
• Card serial number byte 0
• Card serial number byte 1
• Card serial number byte 2
• Card serial number byte 3
12 bytes in total are written to the FIFO.
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Remark: When the MFAuthent command is active all access to the FIFO buffer is
blocked. However, if there is access to the FIFO buffer, the ErrorReg register’s WrErr bit is
set.
This command automatically terminates when the MIFARE card is authenticated and the
Status2Reg register’s MFCrypto1On bit is set to logic 1.
This command does not terminate automatically if the card does not answer, so the timer
must be initialized to automatic mode. In this case, in addition to the IdleIRq bit, the
TimerIRq bit can be used as the termination criteria. During authentication processing, the
RxIRq bit and TxIRq bit are blocked. The Crypto1On bit is only valid after termination of
the MFAuthent command, either after processing the protocol or writing Idle to the
CommandReg register.
If an error occurs during authentication, the ErrorReg register’s ProtocolErr bit is set to
logic 1 and the Status2Reg register’s Crypto1On bit is set to logic 0.
10.3.1.10 SoftReset command
This command performs a reset of the device. The configuration data of the internal buffer
remains unchanged. All registers are set to the reset values. This command automatically
terminates when finished.
Remark: The SerialSpeedReg register is reset and therefore the serial data rate is set to
9.6 kBd.
11. Limiting values
Table 151. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
+4.0
+4.0
+4.0
+4.0
+4.0
Unit
V
VDDA
VDDD
analog supply voltage
digital supply voltage
0.5
0.5
0.5
0.5
0.5
V
VDD(PVDD) PVDD supply voltage
VDD(TVDD) TVDD supply voltage
VDD(SVDD) SVDD supply voltage
V
V
V
VI
input voltage
all input pins except pins MFIN and
RX
VSS(PVSS) 0.5 VDD(PVDD) + 0.5 V
pin MFIN
VSS(PVSS) 0.5 VDD(SVDD) + 0.5 V
Ptot
total power dissipation
junction temperature
per package; VDDD in shortcut
mode
-
200
mW
Tj
-
-
100
C
VESD
electrostatic discharge voltage HBM; 1500 , 100 pF;
2000
V
JESD22-A114-B
MM; 0.75 H, 200 pF;
-
200
V
JESD22-A114-A
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12. Recommended operating conditions
Table 152. Operating conditions
Symbol
Parameter
Conditions
Min
Typ
Max Unit
[1][2]
[1][2]
[1][2]
[3]
VDDA
analog supply voltage
VDD(PVDD) VDDA = VDDD = VDD(TVDD)
;
2.5
3.3
3.6
3.6
3.6
3.6
V
V
V
V
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V
VDDD
digital supply voltage
VDD(PVDD) VDDA = VDDD = VDD(TVDD)
;
2.5
2.5
1.6
3.3
3.3
1.8
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V
VDD(PVDD) VDDA = VDDD = VDD(TVDD)
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V
VDD(PVDD) VDDA = VDDD = VDD(TVDD)
SSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V
VDD(TVDD) TVDD supply voltage
VDD(PVDD) PVDD supply voltage
VDD(SVDD) SVDD supply voltage
;
;
V
VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V
HVQFN32
1.6
-
-
3.6
V
Tamb
ambient temperature
25
+85
C
[1] Supply voltages below 3 V reduce the performance in, for example, the achievable operating distance.
[2] VDDA, VDDD and VDD(TVDD) must always be the same voltage.
[3] VDD(PVDD) must always be the same or lower voltage than VDDD
13. Thermal characteristics
Table 153. Thermal characteristics
.
Symbol Parameter
Rth(j-a) thermal resistance from junction to
ambient
Conditions
Package
Typ Unit
in still air with exposed pin soldered on a
4 layer JEDEC PCB
HVQFN32 40
K/W
14. Characteristics
Table 154. Characteristics
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Input characteristics
Pins EA, I2C and NRSTPD
ILI
input leakage
current
1
-
-
-
+1
A
V
VIH
VIL
HIGH-level input
voltage
0.7VDD(PVDD)
-
-
LOW-level input
voltage
0.3VDD(PVDD)
V
Pin MFIN
ILI
input leakage
current
1
-
-
-
+1
A
V
VIH
VIL
HIGH-level input
voltage
0.7VDD(SVDD)
-
-
LOW-level input
voltage
0.3VDD(SVDD)
V
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Table 154. Characteristics …continued
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Pin SDA
ILI
input leakage
current
1
-
-
-
+1
A
V
VIH
VIL
HIGH-level input
voltage
0.7VDD(PVDD)
-
-
LOW-level input
voltage
0.3VDD(PVDD)
V
Pin RX[1]
Vi
Ci
input voltage
1
-
VDDA +1
-
V
input capacitance
VDDA = 3 V; receiver active;
VRX(p-p) = 1 V; 1.5 V (DC)
offset
-
10
pF
Ri
input resistance
VDDA = 3 V; receiver active;
-
350
-
VRX(p-p) = 1 V; 1.5 V (DC)
offset
Input voltage range; see Figure 24
Vi(p-p)(min) minimum Manchester encoded;
peak-to-peak input VDDA = 3 V
-
-
100
4
-
-
mV
V
voltage
Vi(p-p)(max) maximum
Manchester encoded;
peak-to-peak input VDDA = 3 V
voltage
Input sensitivity; see Figure 24
Vmod
modulation voltage minimum Manchester
encoded; VDDA = 3 V;
-
5
-
mV
RxGain[2:0] = 111b (48 dB)
Pin OSCIN
ILI
input leakage
current
1
-
+1
A
V
VIH
VIL
Ci
HIGH-level input
voltage
0.7VDDA
-
-
LOW-level input
voltage
-
-
-
0.3VDDA
-
V
input capacitance
VDDA = 2.8 V; DC = 0.65 V;
AC = 1 V (p-p)
2
pF
Input/output characteristics
pins D1, D2, D3, D4, D5, D6 and D7
ILI
input leakage
current
1
-
-
-
-
-
+1
A
V
VIH
VIL
VOH
VOL
HIGH-level input
voltage
0.7VDD(PVDD)
-
VDD(PVDD) 0.4
VSS(PVSS)
-
LOW-level input
voltage
0.3VDD(PVDD)
VDD(PVDD)
VSS(PVSS) + 0.4
V
HIGH-level output
voltage
VDD(PVDD) = 3 V; IO = 4 mA
VDD(PVDD) = 3 V; IO = 4 mA
V
LOW-level output
voltage
V
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Table 154. Characteristics …continued
Symbol Parameter
IOH HIGH-level output
Conditions
VDD(PVDD) = 3 V
Min
Typ
Max
Unit
-
-
4
mA
current
IOL
LOW-level output
current
VDD(PVDD) = 3 V
-
-
4
mA
Output characteristics
Pin MFOUT
VOH
VOL
IOL
HIGH-level output
voltage
VDD(SVDD) = 3 V; IO = 4 mA
VDD(SVDD) = 3 V; IO = 4 mA
VDD(SVDD) = 3 V
VDD(SVDD) 0.4
-
-
-
-
VDD(SVDD)
V
LOW-level output
voltage
VSS(PVSS)
VSS(PVSS) + 0.4
V
LOW-level output
current
-
-
4
4
mA
mA
IOH
HIGH-level output
current
VDD(SVDD) = 3 V
Pin IRQ
VOH
HIGH-level output
voltage
VDD(PVDD) = 3 V; IO = 4 mA
VDD(PVDD) = 3 V; IO = 4 mA
VDD(PVDD) = 3 V
VDD(PVDD) 0.4
-
-
-
-
VDD(PVDD)
V
VOL
IOL
LOW-level output
voltage
VSS(PVSS)
VSS(PVSS) + 0.4
V
LOW-level output
current
-
-
4
4
mA
mA
IOH
HIGH-level output
current
VDD(PVDD) = 3 V
Pins AUX1 and AUX2
VOH
VOL
IOL
HIGH-level output
voltage
VDDD = 3 V; IO = 4 mA
VDDD = 3 V; IO = 4 mA
VDDD = 3 V
VDDD 0.4
-
-
-
-
VDDD
V
LOW-level output
voltage
VSS(PVSS)
VSS(PVSS) + 0.4
V
LOW-level output
current
-
-
4
4
mA
mA
IOH
HIGH-level output
current
VDDD = 3 V
Pins TX1 and TX2
VOH
HIGH-level output
voltage
VDD(TVDD) = 3 V;
IDD(TVDD) = 32 mA;
CWGsP[5:0] = 3Fh
VDD(TVDD) 0.15
VDD(TVDD) 0.4
VDD(TVDD) 0.24
VDD(TVDD) 0.64
-
-
-
-
-
-
-
-
V
V
V
V
V
DD(TVDD) = 3 V;
DD(TVDD) = 80 mA;
CWGsP[5:0] = 3Fh
I
VDD(TVDD) = 2.5 V;
IDD(TVDD) = 32 mA;
CWGsP[5:0] = 3Fh
VDD(TVDD) = 2.5 V;
IDD(TVDD) = 80 mA;
CWGsP[5:0] = 3Fh
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Table 154. Characteristics …continued
Symbol Parameter
VOL LOW-level output
voltage
Conditions
Min
Typ
Max
Unit
VDD(TVDD) = 3 V;
IDD(TVDD) = 32 mA;
CWGsP[5:0] = 0Fh
-
-
0.15
V
V
I
DD(TVDD) = 3 V;
DD(TVDD) = 80 mA;
CWGsP[5:0] = 0Fh
-
-
-
-
-
-
0.4
V
V
V
VDD(TVDD) = 2.5 V;
0.24
0.64
IDD(TVDD) = 32 mA;
CWGsP[5:0] = 0Fh
VDD(TVDD) = 2.5 V;
IDD(TVDD) = 80 mA;
CWGsP[5:0] = 0Fh
Current consumption
Ipd
power-down current VDDA = VDDD = VDD(TVDD) =
VDD(PVDD) = 3 V
[2]
[2]
hard power-down; pin
NRSTPD set LOW
-
-
-
-
-
5
A
soft power-down; RF
level detector on
-
10
9
A
IDDD
IDDA
digital supply
current
pin DVDD; VDDD = 3 V
6.5
7
mA
mA
analog supply
current
pin AVDD; VDDA = 3 V;
CommandReg register’s
bit RcvOff = 0
10
pin AVDD; receiver
switched off; VDDA = 3 V;
CommandReg register’s
bit RcvOff = 1
-
3
5
mA
[3]
[4][5][6]
[7]
IDD(PVDD) PVDD supply
current
pin PVDD
-
-
-
-
40
100
4
mA
mA
mA
IDD(TVDD) TVDD supply
current
pin TVDD; continuous wave
pin SVDD
60
-
IDD(SVDD) SVDD supply
current
Clock frequency
fclk
clk
tjit
clock frequency
clock duty cycle
jitter time
-
27.12
-
MHz
%
40
-
50
-
60
10
RMS
ps
Crystal oscillator
VOH
VOL
Ci
HIGH-level output
voltage
pin OSCOUT
pin OSCOUT
-
-
1.1
0.2
-
-
V
V
LOW-level output
voltage
input capacitance
pin OSCOUT
pin OSCIN
-
-
2
2
-
-
pF
pF
MFRC523
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Table 154. Characteristics …continued
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Typical input requirements
fxtal
crystal frequency
-
-
27.12
-
-
MHz
ESR
equivalent series
resistance
100
CL
load capacitance
-
-
10
50
-
pF
Pxtal
crystal power
dissipation
100
W
[1] The voltage on pin RX is clamped by internal diodes to pins AVSS and AVDD.
[2] Ipd is the total current for all supplies.
[3] IDD(PVDD) depends on the overall load at the digital pins.
[4] IDD(TVDD) depends on VDD(TVDD) and the external circuit connected to pins TX1 and TX2.
[5] During typical circuit operation, the overall current is below 100 mA.
[6] Typical value using a complementary driver configuration and an antenna matched to 40 between pins TX1 and TX2 at 13.56 MHz.
[7] IDD(SVDD) depends on the load at pin MFOUT.
V
DDA
+ 1 V
V
mod
V
V
i(p-p)(min)
i(p-p)(max)
VMID
13.56 MHz
carrier
0 V
001aak012
−1 V
Fig 24. Pin RX input voltage range
14.1 Timing characteristics
Table 155. SPI timing characteristics
Symbol
tWL
Parameter
Conditions
line SCK
Min
50
Typ
Max Unit
pulse width LOW
pulse width HIGH
-
-
-
-
-
-
ns
ns
ns
tWH
line SCK
50
th(SCKH-D)
SCK HIGH to data input SCK to changing MOSI
hold time
25
tsu(D-SCKH) data input to SCK HIGH changing MOSI to SCK
set-up time
25
-
-
ns
MFRC523
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Table 155. SPI timing characteristics …continued
Symbol Parameter Conditions
th(SCKL-Q)
Min
Typ
Max Unit
SCK LOW to data output SCK to changing MISO
hold time
-
-
25
ns
ns
ns
t(SCKL-NSSH) SCK LOW to NSS HIGH
time
0
-
-
-
tNSSH
NSS HIGH time
before communication
50
-
Table 156. I2C-bus timing in Fast mode
Symbol Parameter
Conditions
Fast mode High-speed Unit
mode
Min Max Min Max
fSCL
SCL clock frequency
0
400
-
0
3400 kHz
tHD;STA
hold time (repeated) START
condition
after this period,
the first clock pulse
is generated
600
160
-
ns
tSU;STA
set-up time for a repeated
START condition
600
-
160
-
ns
tSU;STO set-up time for STOP condition
600
1300
600
0
-
160
160
60
0
-
ns
ns
ns
ns
ns
ns
ns
ns
tLOW
tHIGH
LOW period of the SCL clock
HIGH period of the SCL clock
-
-
-
-
tHD;DAT data hold time
900
-
70
-
tSU;DAT
data set-up time
rise time
100
20
10
tr
tf
tr
SCL signal
SCL signal
300 10
300 10
300 10
40
40
80
fall time
20
rise time
SDA and SCL
signals
20
tf
fall time
SDA and SCL
signals
20
300 10
80
-
ns
tBUF
bus free time between a STOP
and START condition
1.3
-
1.3
s
MFRC523
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t
t
t
t
SCKL
SCKL
SCKH
SHDX
SCK
t
SLDX
t
t
DXSH
DXSH
MOSI
MISO
NSS
MSB
MSB
LSB
LSB
t
SLNH
001aaj634
Remark: The signal NSS must be LOW to be able to send several bytes in one data stream.
To send more than one data stream NSS must be set HIGH between the data streams.
Fig 25. Timing diagram for SPI
SDA
t
t
t
t
r
f
SU;DAT
SP
t
t
t
t
BUF
LOW
f
HD;STA
SCL
t
t
t
SU;STO
r
HIGH
t
t
SU;STA
HD;STA
t
HD;DAT
S
Sr
P
S
001aaj635
Fig 26. Timing for Fast and Standard mode devices on the I2C-bus
MFRC523
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15. Application information
A typical application diagram using a complementary antenna connection to the
MFRC523 is shown in Figure 27.
The antenna tuning and RF part matching is described in the application note Ref. 1 and
Ref. 2.
supply
DVDD
AVDD
15
TVDD
12
3
C
Rx
PVDD
PVSS
RX
2
5
6
17
16
R1
C
vmid
VMID
TX1
R2
C1
C1
L0
Ra
C2
NRSTPD
11
antenna
Lant
host
interface
C0
C0
MFRC523
TVSS
TX2
MICRO-
PROCESSOR
10, 14
13
C2
Ra
L0
IRQ
23
18
AVSS
DVSS
4
21
22
OSCOUT
OSCIN
27.12 MHz
001aal163
Fig 27. Typical application diagram
MFRC523
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16. Test information
16.1 Test signals
16.1.1 Self-test
The MFRC523 has the capability to perform a digital self-test. The self-test is started by
using the following procedure:
1. Perform a soft reset.
2. Clear the internal buffer by writing 25 bytes of 00h and implement the Config
command.
3. Enable the self-test by writing 09h to the AutoTestReg register.
4. Write 00h to the FIFO buffer.
5. Start the self-test with the CalcCRC command.
6. The self-test is initiated.
7. When the self-test has completed, the FIFO buffer contains the following 64 bytes:
FIFO buffer byte values for version B2h:
0x00, 0xEB, 0x66, 0xBA, 0x57, 0xBF, 0x23, 0x95, 0xD0, 0xE3, 0x0D, 0x3D, 0x27, 0x89,
0x5C, 0xDE, 0x9D, 0x3B, 0xA7, 0x00, 0x21, 0x5B, 0x89, 0x82, 0x51, 0x3A, 0xEB,
0x02, 0x0C, 0xA5, 0x00, 0x49, 0x7C, 0x84, 0x4D, 0xB3, 0xCC, 0xD2, 0x1B, 0x81,
0x5D, 0x48, 0x76, 0xD5, 0x71, 0x61, 0x21, 0xA9, 0x86, 0x96, 0x83, 0x38, 0xCF,
0x9D, 0x5B, 0x6D, 0xDC, 0x15, 0xBA, 0x3E, 0x7D, 0x95, 0x3B, 0x2F
16.1.2 Test bus
The test bus is used for production tests. The following configuration can be used to
improve the design of a system using the MFRC523. The test bus allows internal signals
to be routed to the digital interface. The test bus comprises two sets of test signals which
are selected using their subaddress specified in the TestSel2Reg register’s
TestBusSel[4:0] bits. The test signals and their related digital output pins are described in
Table 157 and Table 158.
Table 157. Test bus signals: TestBusSel[4:0] = 07h
Pins
Internal
Description
signal name
D6
D5
D4
D3
D2
D1
s_data
s_coll
received data stream
bit-collision detected (106 kBd only)
s_data and s_coll signals are valid
receiver has detected a stop condition
receiver is reset
s_valid
s_over
RCV_reset
-
reserved
MFRC523
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Table 158. Test bus signals: TestBusSel[4:0] = 0Dh
Pins
Internal test
signal name
Description
D6
clkstable
oscillator output signal
oscillator output signal divided by 8
reserved
D5
clk27/8
D4 to D3
D2
-
clk27
-
oscillator output signal
reserved
D1
16.1.3 Test signals on pins AUX1 or AUX2
The MFRC523 allows the user to select internal signals for measurement on pins AUX1 or
AUX2. These measurements can be helpful during the design-in phase to optimize the
design or used for test purposes.
Table 159 shows the signals that can be switched to pin AUX1 or AUX2 by setting
AnalogSelAux1[3:0] or AnalogSelAux2[3:0] in the AnalogTestReg register.
Remark: The DAC has a current output, therefore it is recommended that a 1 k
pull-down resistor is connected to pin AUX1 or pin AUX2.
Table 159. Test signal descriptions
AnalogSelAuxn[3:0] Signal on pin AUXn
0000
0001
0010
0011
3-state
DAC: register TestDAC1 or TestDAC2
DAC: test signal Corr1
reserved
0100
0101
0110
DAC: test signal MinLevel
DAC: test signal ADC_I
DAC: test signal ADC_Q
reserved
0111 to 1001
1010
1011
HIGH
LOW
1100
TxActive
1101
RxActive
1110
subcarrier detected
TstBusBit
1111
16.1.3.1 Example: Output test signals TestDAC1 and TestDAC2
The AnalogTestReg register is set to 11h. The output on pin AUX1 has the test signal
TestDAC1 and the output on pin AUX2 has the test signal TestDAC2. The signal values of
TestDAC1 and TestDAC2 are controlled by the TestDAC1Reg and TestDAC2Reg
registers.
Figure 28 shows test signal TestDAC1 on pin AUX1 and TestDAC2 on pin AUX2 when the
TestDAC1Reg register is programmed with a slope defined by values 00h to 3Fh and the
TestDAC2Reg register is programmed with a rectangular signal defined by values 00h
and 3Fh.
MFRC523
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001aak597
(1)
(2)
100 ms/div
(1) TestDAC1 (500 mV/div) on pin AUX1.
(2) TestDAC2 (500 mV/div) on pin AUX2.
Fig 28. Output test signals TestDAC1 on pin AUX1 and TestDAC2 on pin AUX2
16.1.3.2 Example: Output test signals Corr1 and MinLevel
Figure 29 shows test signals Corr1 and MinLevel on pins AUX1 and AUX2, respectively.
The AnalogTestReg register is set to 24h.
001aak598
(1)
(2)
(3)
10 μs/div
(1) MinLevel (1 V/div) on pin AUX2.
(2) Corr1 (1 V/div) on pin AUX1.
(3) RF field.
Fig 29. Output test signals Corr1 on pin AUX1 and MinLevel on pin AUX2
MFRC523
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16.1.3.3 Example: Output test signals ADC I-channel and ADC Q-channel
Figure 30 shows the channel behavior test signals ADC_I and ADC_Q on pins AUX1 and
AUX2, respectively. The AnalogTestReg register is set to 56h.
001aak599
(1)
(2)
(3)
5 μs/div
(1) ADC_I (1 V/div) on pin AUX1.
(2) ADC_Q (500 mV/div) on pin AUX2.
(3) RF field.
Fig 30. Output ADC I-channel on pin AUX1 and ADC Q-channel on pin AUX2
16.1.3.4 Example: Output test signals RxActive and TxActive
Figure 31 shows the RxActive and TxActive test signals relating to RF communication.
The AnalogTestReg register is set to CDh.
• At 106 kBd, RxActive is HIGH during data bits, parity and CRC reception. Start bits
are not included
• At 106 kBd, TxActive is HIGH during start bits, data bits, parity and CRC transmission
• At 212 kBd, 424 kBd and 848 kBd, RxActive is HIGH during data bits and CRC
reception. Start bits are not included
• At 212 kBd, 424 kBd and 848 kBd, TxActive is HIGH during data bits and CRC
transmission
MFRC523
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001aak600
(1)
(2)
(3)
10 μs/div
(1) RxActive (2 V/div) on pin AUX1.
(2) TxActive (2 V/div) on pin AUX2.
(3) RF field.
Fig 31. Output RxActive on pin AUX1 and TxActive on pin AUX2
16.1.3.5 Example: Output test signal RX data stream
Figure 32 shows the data stream that is currently being received. The TestSel2Reg
register’s TestBusSel[4:0] bits are set to 07h to enable test bus signals on pins D1 to D6;
see Section 16.1.2 “Test bus” on page 80. The TestSel1Reg register’s TstBusBitSel[2:0]
bits are set 06h (pin D6 = s_data) and AnalogTestReg register is set to FFh (TstBusBit)
which outputs the received data stream on pins AUX1 and AUX2.
001aak601
(1)
(2)
20 μs/div
(1) s_data (received data stream) (2 V/div).
(2) RF field.
Fig 32. Received data stream on pins AUX1 and AUX2
MFRC523
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16.1.3.6 Pseudo-Random Binary Sequences (PRBS)
The pseudo-random binary sequences PRBS9 and PRBS15 are based on ITU-TO150
and are defined with the TestSel2Reg register. Transmission of either data stream is
started by the Transmit command. The preamble/sync byte/start bit/parity bit are
automatically generated depending on the mode selected.
Remark: All relevant registers for transmitting data must be configured in accordance with
ITU-TO150 before selecting PRBS transmission.
MFRC523
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17. Package outline
HVQFN32: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
SOT617-1
B
A
D
terminal 1
index area
A
A
1
E
c
detail X
C
e
1
y
y
e
1/2 e
v
M
M
b
C
C
A B
C
1
w
9
16
L
17
8
e
e
E
h
2
1/2 e
1
24
terminal 1
index area
32
25
X
D
h
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
(1)
A
(1)
(1)
UNIT
A
1
b
c
E
e
e
e
2
y
D
D
E
L
v
w
y
1
h
1
h
max.
0.05 0.30
0.00 0.18
5.1
4.9
3.25
2.95
5.1
4.9
3.25
2.95
0.5
0.3
mm
0.05 0.1
1
0.2
0.5
3.5
3.5
0.1
0.05
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
01-08-08
02-10-18
SOT617-1
- - -
MO-220
- - -
Fig 33. Package outline SOT617-1 (HVQFN32)
MFRC523
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Detailed package information can be found at: www.nxp.com/package/SOT617-1.html
18. Handling information
Moisture Sensitivity Level (MSL) evaluation has been performed according to
SNW-FQ-225B rev.04/07/07 (JEDEC J-STD-020C). MSL for this package is level 1 which
means 260 C convection reflow temperature.
Dry pack is not required.
Unlimited out-of-pack floor life at maximum ambient 30 C/85 % RH.
19. Packing information
strap 46 mm from corner
The straps around the package of
stacked trays inside the piano-box
have sufficient pre-tension to avoid
loosening of the trays.
tray
ESD warning preprinted
barcode label (permanent)
barcode label (peel-off)
chamfer
PIN 1
chamfer
PIN 1
QA seal
Hyatt patent preprinted
In the traystack (2 trays)
only ONE tray type* allowed
printed piano box
*one supplier and one revision number.
001aaj740
Fig 34. Packing information 1 tray
MFRC523
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strap 46 mm from corner
The straps around the package of
stacked trays inside the piano-box
have sufficient pre-tension to avoid
loosening of the trays.
tray
ESD warning preprinted
chamfer
barcode label (permanent)
barcode label (peel-off)
PIN 1
chamfer
PIN 1
QA seal
Hyatt patent preprinted
In the traystack (2 trays)
only ONE tray type* allowed
printed piano box
*one supplier and one revision number.
001aal164
Fig 35. Packing information 5 trays
MFRC523
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20. Abbreviations
Table 160. Abbreviations
Acronym
ADC
ASK
BPSK
CRC
CW
Description
Analog-to-Digital Converter
Amplitude Shift Keying
Binary Phase Shift Keying
Cyclic Redundancy Check
Continuous Wave
DAC
EOF
ETU
HBM
I2C
Digital-to-Analog Converter
End Of Frame
Elementary Time Unit
Human Body Model
Inter-integrated Circuit
Least Significant Bit
Master In Slave Out
Machine Model
LSB
MISO
MM
MOSI
MSB
NRZ
NSS
PCB
PLL
Master Out Slave In
Most Significant Bit
Not Return to Zero
Not Slave Select
Printed-Circuit Board
Phase-Locked Loop
Pseudo-Random Bit Sequence
Receiver
PRBS
RX
SOF
SPI
Start Of Frame
Serial Peripheral Interface
Transmitter
TX
UART
Universal Asynchronous Receiver Transmitter
21. Glossary
Modulation index — Defined as the voltage ratio (Vmax Vmin) / (Vmax + Vmin).
Load modulation index — Defined as the voltage ratio for the card
(Vmax Vmin) / (Vmax + Vmin) measured at the card’s coil.
22. References
[1] Application note — MFRC52x Reader IC Family Directly Matched Antenna
Design
[2] Application note — MIFARE (ISO/IEC 14443 A) 13.56 MHz RFID Proximity
Antennas
MFRC523
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23. Revision history
Table 161. Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
MFRC523 v. 3.7 20111108
Product data sheet
-
MFRC523 v. 3.6
Modifications:
• Table 2 “Ordering information”: updated
• Table 154 “Characteristics”: unit of Pxtal corrected
MFRC523 v. 3.6 20110628
Product data sheet
• Section 9.2.1.7 “ErrorReg register” on page 40 added
20100924 Product data sheet
-
-
MFRC523_35
MFRC523_34
MFRC523_33
Modifications:
MFRC523_35
Modifications:
MFRC523_34
Modifications:
• Table 131 “VersionReg register bit descripitons” on page 63 changed
20100715 Product data sheet
-
• Section 9.2.2.10 “DemodReg register”: register updated.
• Section 9.2.2.15 “TypeBReg register”: register updated.
• Section 9.2.3.10 “TModeReg and TPrescalerReg registers”: register updated.
• Section 9.2.4.7 “AutoTestReg register”: register updated.
• Section 8.7 “Timer unit”: timer calculation updated.
• Section 9.2.4.8 “VersionReg register”: version: B2h updated.
• Section 16.1 “Test signals”: selftest result updated.
MFRC523_33
Modifications:
20100305
Product data sheet
-
MFRC523_32
• Table 106 “TModeReg register bit descriptions” and Table 108
“TPrescalerReg register bit descriptions”: text updated.
• Section 8.7 “Timer unit”: input clock frequency changed to 13.56 MHz and
text updated.
• Table 154 “SPI timing characteristics”: NSS HIGH time, tNSSH added.
MFRC523_32
Modifications:
20100112
Product data sheet
-
115231
• The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP
Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• General re-wording of MIFARE designation and commercial conditions.
• Table 106 “TModeReg register bit descriptions” and Table 108 “TPrescalerReg register bit
descriptions”: changed value "fTimer = 13.56 MHz / (TPreScaler + 1)".
• Graphics: updated to latest standard.
• Descriptive text: updated.
• Register and bit names: updated.
• Register tables: presentation updated.
• Parameter symbols: updated.
• Section 9 “MFRC523 registers” now follows Section 8 “Functional description”.
• Section 16 “Test information” added, incorporating Section 16.1 “Test signals”.
115231
115230
115220
May 2007
Product data sheet
Product data sheet
Preliminary data sheet
-
-
-
115230
115220
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September 2006
August 2006
MFRC523
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
90 of 98
MFRC523
NXP Semiconductors
Contactless reader IC
24. Legal information
24.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
malfunction of an NXP Semiconductors product can reasonably be expected
24.2 Definitions
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
24.3 Disclaimers
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
MFRC523
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
91 of 98
MFRC523
NXP Semiconductors
Contactless reader IC
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
24.4 Licenses
Purchase of NXP ICs with ISO/IEC 14443 type B functionality
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
This NXP Semiconductors IC is ISO/IEC 14443 Type B
software enabled and is licensed under Innovatron’s
Contactless Card patents license for ISO/IEC 14443 B.
The license includes the right to use the IC in systems
and/or end-user equipment.
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
RATP/Innovatron
Technology
24.5 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
MIFARE — is a trademark of NXP B.V.
25. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
MFRC523
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
92 of 98
MFRC523
NXP Semiconductors
Contactless reader IC
26. Tables
Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .2
Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .3
Table 3. Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6
Table 4. Communication overview for ISO/IEC 14443 A
reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Table 37. Status1Reg register bit descriptions . . . . . . . . 41
Table 38. Status2Reg register (address 08h); reset value:
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 41
Table 39. Status2Reg register bit descriptions . . . . . . . . 41
Table 40. FIFODataReg register (address 09h); reset value:
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 42
Table 41. FIFODataReg register bit descriptions . . . . . . 42
Table 42. FIFOLevelReg register (address 0Ah); reset
value: 00h bit allocation . . . . . . . . . . . . . . . . . 42
Table 43. FIFOLevelReg register bit descriptions . . . . . . 43
Table 44. WaterLevelReg register (address 0Bh); reset
value: 08h bit allocation . . . . . . . . . . . . . . . . . 43
Table 45. WaterLevelReg register bit descriptions . . . . . 43
Table 46. ControlReg register (address 0Ch); reset value:
10h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 43
Table 47. ControlReg register bit descriptions . . . . . . . . 43
Table 48. BitFramingReg register (address 0Dh); reset
value: 00h bit allocation . . . . . . . . . . . . . . . . . 44
Table 49. BitFramingReg register bit descriptions . . . . . 44
Table 50. CollReg register (address 0Eh); reset value: xxh
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table 5. Connection protocol for detecting different
interface types . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 6. MOSI and MISO byte order . . . . . . . . . . . . . . .11
Table 7. MOSI and MISO byte order . . . . . . . . . . . . . . .11
Table 8. SPI read address . . . . . . . . . . . . . . . . . . . . . . .11
Table 9. SPI write address . . . . . . . . . . . . . . . . . . . . . .12
Table 10. BR_T0 and BR_T1 settings . . . . . . . . . . . . . . .12
Table 11. Selectable UART transfer speeds . . . . . . . . . .13
Table 12. UART framing . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 13. Read data byte order . . . . . . . . . . . . . . . . . . . .14
Table 14. Write data byte order . . . . . . . . . . . . . . . . . . . .14
Table 15. Address byte 0 register; address MOSI . . . . . .16
Table 16. Register and bit settings controlling the signal on
pin TX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Table 17. Register and bit settings controlling the signal on
pin TX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Table 18. CRC coprocessor parameters . . . . . . . . . . . . .27
Table 19. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .29
Table 20. Behavior of register bits and their designation .32
Table 21. MFRC523 register overview . . . . . . . . . . . . . .33
Table 22. Reserved register (address 00h); reset value: 00h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Table 51. CollReg register bit descriptions . . . . . . . . . . . 44
Table 52. Reserved register (address 0Fh); reset value: 00h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 53. Reserved register bit descriptions . . . . . . . . . . 45
Table 54. Reserved register (address 10h); reset value: 00h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 23. Reserved register bit descriptions . . . . . . . . . .36
Table 24. CommandReg register (address 01h); reset
value: 20h bit allocation . . . . . . . . . . . . . . . . . .36
Table 55. Reserved register bit descriptions . . . . . . . . . . 45
Table 56. ModeReg register (address 11h); reset value: 3Fh
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table 25. CommandReg register bit descriptions . . . . . .36
Table 26. ComIEnReg register (address 02h); reset value:
80h bit allocation . . . . . . . . . . . . . . . . . . . . . . .37
Table 57. ModeReg register bit descriptions . . . . . . . . . 46
Table 58. TxModeReg register (address 12h); reset value:
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 47
Table 27. ComIEnReg register bit descriptions . . . . . . . .37
Table 28. DivIEnReg register (address 03h); reset value:
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .37
Table 59. TxModeReg register bit descriptions . . . . . . . 47
Table 60. RxModeReg register (address 13h); reset value:
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 47
Table 29. DivIEnReg register bit descriptions . . . . . . . . .37
Table 30. ComIrqReg register (address 04h); reset value:
14h bit allocation . . . . . . . . . . . . . . . . . . . . . . .38
Table 61. RxModeReg register bit descriptions . . . . . . . 47
Table 62. TxControlReg register (address 14h); reset value:
80h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 48
Table 31. ComIrqReg register bit descriptions . . . . . . . .38
Table 32. DivIrqReg register (address 05h); reset value: x0h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Table 63. TxControlReg register bit descriptions . . . . . . 48
Table 64. TxASKReg register (address 15h); reset value:
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 49
Table 33. DivIrqReg register bit descriptions . . . . . . . . . .39
Table 34. ErrorReg register (address 06h); reset value: 00h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .40
Table 65. TxASKReg register bit descriptions . . . . . . . . 49
Table 66. TxSelReg register (address 16h); reset value: 10h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table 35. ErrorReg register bit descriptions . . . . . . . . . .40
Table 36. Status1Reg register (address 07h); reset value:
21h bit allocation . . . . . . . . . . . . . . . . . . . . . . .40
Table 67. TxSelReg register bit descriptions . . . . . . . . . 49
Table 68. RxSelReg register (address 17h); reset value: 84h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 50
continued >>
MFRC523
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
93 of 98
MFRC523
NXP Semiconductors
Contactless reader IC
Table 69. RxSelReg register bit descriptions . . . . . . . . . .50
Table 70. RxThresholdReg register (address 18h); reset
value: 84h bit allocation . . . . . . . . . . . . . . . . . .51
Table 103. CWGsPReg register bit descriptions . . . . . . . 58
Table 104. ModGsPReg register (address 29h); reset value:
20h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 58
Table 71. RxThresholdReg register bit descriptions . . . .51
Table 72. DemodReg register (address 19h); reset value:
4Dh bit allocation . . . . . . . . . . . . . . . . . . . . . . .51
Table 105. ModGsPReg register bit descriptions . . . . . . . 58
Table 106. TModeReg register (address 2Ah); reset value:
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 58
Table 73. DemodReg register bit descriptions . . . . . . . . .51
Table 74. Reserved register (address 1Ah); reset value: 00h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 107. TModeReg register bit descriptions . . . . . . . . 59
Table 108. TPrescalerReg register (address 2Bh); reset
value: 00h bit allocation . . . . . . . . . . . . . . . . . 59
Table 75. Reserved register bit descriptions . . . . . . . . . .52
Table 76. Reserved register (address 1Bh); reset value: 00h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 109. TPrescalerReg register bit descriptions . . . . . 60
Table 110. TReloadReg (higher bits) register (address 2Ch);
reset value: 00h bit allocation . . . . . . . . . . . . . 60
Table 77. Reserved register bit descriptions . . . . . . . . . .52
Table 78. MfTxReg register (address 1Ch); reset value: 62h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .52
Table 111. TReloadReg register higher bit descriptions . . 60
Table 112. TReloadReg (lower bits) register (address 2Dh);
reset value: 00h bit allocation . . . . . . . . . . . . . 60
Table 79. MfTxReg register bit descriptions . . . . . . . . . .53
Table 80. MfRxReg register (address 1Dh); reset value: 00h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Table 113. TReloadReg register lower bit descriptions . . 60
Table 114. TCounterValReg (higher bits) register (address
2Eh); reset value: xxh bit allocation . . . . . . . . 60
Table 81. MfRxReg register bit descriptions . . . . . . . . . .53
Table 82. TypeBReg register (address 1Eh); reset value:
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .53
Table 83. TypeBReg register bit descriptions . . . . . . . . .53
Table 84. SerialSpeedReg register (address 1Fh); reset
value: EBh bit allocation . . . . . . . . . . . . . . . . .54
Table 115. TCounterValReg register higher bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 116. TCounterValReg (lower bits) register (address
2Fh); reset value: xxh bit allocation . . . . . . . . 61
Table 117. TCounterValReg register lower bit
descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 85. SerialSpeedReg register bit descriptions . . . . .54
Table 86. Reserved register (address 20h); reset value: 00h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Table 87. Reserved register bit descriptions . . . . . . . . . .55
Table 88. CRCResultReg (higher bits) register (address
21h); reset value: FFh bit allocation . . . . . . . .55
Table 89. CRCResultReg register higher bit descriptions 55
Table 90. CRCResultReg (lower bits) register (address
22h); reset value: FFh bit allocation . . . . . . . .55
Table 91. CRCResultReg register lower bit descriptions .55
Table 92. Reserved register (address 23h); reset value: 88h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 93. Reserved register bit descriptions . . . . . . . . . .56
Table 94. ModWidthReg register (address 24h); reset value:
26h bit allocation . . . . . . . . . . . . . . . . . . . . . . .56
Table 95. ModWidthReg register bit descriptions . . . . . .56
Table 96. Reserved register (address 25h); reset value: 87h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 97. Reserved register bit descriptions . . . . . . . . . .56
Table 98. RFCfgReg register (address 26h); reset value:
48h bit allocation . . . . . . . . . . . . . . . . . . . . . . .57
Table 99. RFCfgReg register bit descriptions . . . . . . . . .57
Table 100. GsNReg register (address 27h); reset value: 88h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Table 118. Reserved register (address 30h); reset value: 00h
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 119. Reserved register bit descriptions . . . . . . . . . 61
Table 120. TestSel1Reg register (address 31h); reset value:
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 61
Table 121. TestSel1Reg register bit descriptions . . . . . . . 61
Table 122. TestSel2Reg register (address 32h); reset value:
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 62
Table 123. TestSel2Reg register bit descriptions . . . . . . . 62
Table 124. TestPinEnReg register (address 33h); reset
value: 80h bit allocation . . . . . . . . . . . . . . . . . 62
Table 125. TestPinEnReg register bit descriptions . . . . . 62
Table 126. TestPinValueReg register (address 34h); reset
value: 00h bit allocation . . . . . . . . . . . . . . . . . 63
Table 127. TestPinValueReg register bit descriptions . . . 63
Table 128. TestBusReg register (address 35h); reset value:
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 63
Table 129. TestBusReg register bit descriptions . . . . . . . 63
Table 130. AutoTestReg register (address 36h); reset value:
40h bit allocation . . . . . . . . . . . . . . . . . . . . . . . 63
Table 131. AutoTestReg register bit descriptions . . . . . . . 64
Table 132. VersionReg register (address 37h); reset value:
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . . 64
Table 133. VersionReg register bit descriptions . . . . . . . . 64
Table 134. AnalogTestReg register (address 38h); reset
value: 00h bit allocation . . . . . . . . . . . . . . . . . 64
Table 101. GsNReg register bit descriptions . . . . . . . . . .57
Table 102. CWGsPReg register (address 28h); reset value:
20h bit allocation . . . . . . . . . . . . . . . . . . . . . . .58
Table 135. AnalogTestReg register bit descriptions . . . . . 65
continued >>
MFRC523
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Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
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MFRC523
NXP Semiconductors
Contactless reader IC
Table 136. TestDAC1Reg register (address 39h); reset
value: xxh bit allocation . . . . . . . . . . . . . . . . . .66
Table 137. TestDAC1Reg register bit descriptions . . . . . .66
Table 138. TestDAC2Reg register (address 3Ah); reset
value: xxh bit allocation . . . . . . . . . . . . . . . . . .66
Table 139. TestDAC2Reg register bit descriptions . . . . . .66
Table 140. TestADCReg register (address 3Bh); reset value:
xxh bit allocation . . . . . . . . . . . . . . . . . . . . . . .66
Table 141. TestADCReg register bit descriptions . . . . . . .66
Table 142. Reserved register (address 3Ch); reset value:
FFh bit allocation . . . . . . . . . . . . . . . . . . . . . . .67
Table 143. Reserved register bit descriptions . . . . . . . . . .67
Table 144. Reserved register (address 3Dh); reset value:
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .67
Table 145. Reserved register bit descriptions . . . . . . . . . .67
Table 146. Reserved register (address 3Eh); reset value:
03h bit allocation . . . . . . . . . . . . . . . . . . . . . . .67
Table 147. Reserved register bit descriptions . . . . . . . . . .67
Table 148. Reserved register (address 3Fh); reset value:
00h bit allocation . . . . . . . . . . . . . . . . . . . . . . .67
Table 149. Reserved register bit descriptions . . . . . . . . . .67
Table 150. Command overview . . . . . . . . . . . . . . . . . . . .68
Table 151. Limiting values . . . . . . . . . . . . . . . . . . . . . . . .71
Table 152. Operating conditions . . . . . . . . . . . . . . . . . . . .72
Table 153. Thermal characteristics . . . . . . . . . . . . . . . . . .72
Table 154. Characteristics . . . . . . . . . . . . . . . . . . . . . . . .72
Table 155. SPI timing characteristics . . . . . . . . . . . . . . . .76
Table 156. I2C-bus timing in Fast mode . . . . . . . . . . . . . .77
Table 157. Test bus signals: TestBusSel[4:0] = 07h . . . . .80
Table 158. Test bus signals: TestBusSel[4:0] = 0Dh . . . . .81
Table 159. Test signal descriptions . . . . . . . . . . . . . . . . . .81
Table 160. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . .89
Table 161. Revision history . . . . . . . . . . . . . . . . . . . . . . . .90
continued >>
MFRC523
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© NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
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MFRC523
NXP Semiconductors
Contactless reader IC
27. Figures
Fig 1. Simplified block diagram of the MFRC523. . . . . . .4
Fig 2. Detailed block diagram of the MFRC523. . . . . . . .5
Fig 3. Pinning configuration HVQFN32 (SOT617-1) . . . .6
Fig 4. MFRC523 Read/Write mode . . . . . . . . . . . . . . . . .8
Fig 5. ISO/IEC 14443 A/MIFARE Read/Write mode
communication diagram. . . . . . . . . . . . . . . . . . . . .8
Fig 6. Data coding and framing according to
ISO/IEC 14443 A . . . . . . . . . . . . . . . . . . . . . . . . . .9
Fig 7. SPI connection to host. . . . . . . . . . . . . . . . . . . . .10
Fig 8. UART connection to microcontrollers . . . . . . . . .12
Fig 9. UART read data timing diagram . . . . . . . . . . . . .14
Fig 10. UART write data timing diagram . . . . . . . . . . . . .15
Fig 11. I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . . .16
Fig 12. Bit transfer on the I2C-bus . . . . . . . . . . . . . . . . . .17
Fig 13. START and STOP conditions . . . . . . . . . . . . . . .17
Fig 14. Acknowledge on the I2C-bus . . . . . . . . . . . . . . . .18
Fig 15. Data transfer on the I2C-bus . . . . . . . . . . . . . . . .18
Fig 16. First byte following the START procedure . . . . . .19
Fig 17. Register read and write access . . . . . . . . . . . . . .20
Fig 18. I2C-bus HS mode protocol switch . . . . . . . . . . . .21
Fig 19. I2C-bus HS mode protocol frame. . . . . . . . . . . . .22
Fig 20. Serial data switch for TX1 and TX2 . . . . . . . . . . .25
Fig 21. Overview of MFIN and MFOUT signal routing. . .26
Fig 22. Quartz crystal connection . . . . . . . . . . . . . . . . . .31
Fig 23. Oscillator start-up time. . . . . . . . . . . . . . . . . . . . .32
Fig 24. Pin RX input voltage range . . . . . . . . . . . . . . . . .76
Fig 25. Timing diagram for SPI . . . . . . . . . . . . . . . . . . . .78
Fig 26. Timing for Fast and Standard mode devices on the
I2C-bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
Fig 27. Typical application diagram . . . . . . . . . . . . . . . . .79
Fig 28. Output test signals TestDAC1 on pin AUX1 and
TestDAC2 on pin AUX2 . . . . . . . . . . . . . . . . . . . .82
Fig 29. Output test signals Corr1 on pin AUX1 and MinLevel
on pin AUX2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Fig 30. Output ADC I-channel on pin AUX1 and ADC
Q-channel on pin AUX2. . . . . . . . . . . . . . . . . . . .83
Fig 31. Output RxActive on pin AUX1 and TxActive on pin
AUX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84
Fig 32. Received data stream on pins AUX1 and AUX2 .84
Fig 33. Package outline SOT617-1 (HVQFN32) . . . . . . .86
Fig 34. Packing information 1 tray . . . . . . . . . . . . . . . . . .87
Fig 35. Packing information 5 trays . . . . . . . . . . . . . . . . .88
continued >>
MFRC523
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
96 of 98
MFRC523
NXP Semiconductors
Contactless reader IC
28. Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
8.8
Power reduction modes . . . . . . . . . . . . . . . . . 30
Hard power-down. . . . . . . . . . . . . . . . . . . . . . 30
Soft power-down mode . . . . . . . . . . . . . . . . . 30
Transmitter Power-down mode . . . . . . . . . . . 31
Oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . 31
Reset and oscillator start-up time . . . . . . . . . 31
Reset timing requirements. . . . . . . . . . . . . . . 31
Oscillator start-up time. . . . . . . . . . . . . . . . . . 31
8.8.1
8.8.2
8.8.3
8.9
8.10
8.10.1
8.10.2
2
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 2
Quick reference data . . . . . . . . . . . . . . . . . . . . . 2
Ordering information. . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information. . . . . . . . . . . . . . . . . . . . . . 6
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
4
5
6
7
7.1
9
9.1
9.1.1
9.2
MFRC523 registers . . . . . . . . . . . . . . . . . . . . . 32
Register bit behavior . . . . . . . . . . . . . . . . . . . 32
MFRC523 register overview . . . . . . . . . . . . . 33
Register descriptions . . . . . . . . . . . . . . . . . . . 36
Page 0: Command and status . . . . . . . . . . . . 36
Reserved register 00h . . . . . . . . . . . . . . . . . . 36
CommandReg register. . . . . . . . . . . . . . . . . . 36
ComIEnReg register . . . . . . . . . . . . . . . . . . . 37
DivIEnReg register. . . . . . . . . . . . . . . . . . . . . 37
ComIrqReg register . . . . . . . . . . . . . . . . . . . . 38
DivIrqReg register . . . . . . . . . . . . . . . . . . . . . 39
ErrorReg register . . . . . . . . . . . . . . . . . . . . . . 40
Status1Reg register . . . . . . . . . . . . . . . . . . . . 40
Status2Reg register . . . . . . . . . . . . . . . . . . . . 41
8
8.1
8.2
8.3
8.3.1
8.3.2
Functional description . . . . . . . . . . . . . . . . . . . 8
ISO/IEC 14443 A functionality . . . . . . . . . . . . . 8
ISO/IEC 14443 B functionality . . . . . . . . . . . . . 9
Digital interfaces . . . . . . . . . . . . . . . . . . . . . . . . 9
Automatic microcontroller interface detection. . 9
Serial Peripheral Interface . . . . . . . . . . . . . . . 10
SPI read data . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI write data . . . . . . . . . . . . . . . . . . . . . . . . . 11
SPI Read and Write address byte . . . . . . . . . 11
UART interface . . . . . . . . . . . . . . . . . . . . . . . . 12
Connection to a host. . . . . . . . . . . . . . . . . . . . 12
Selectable UART transfer speeds . . . . . . . . . 12
UART framing. . . . . . . . . . . . . . . . . . . . . . . . . 13
I2C Bus Interface . . . . . . . . . . . . . . . . . . . . . . 16
Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . 17
START and STOP conditions . . . . . . . . . . . . . 17
Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 18
7-Bit addressing . . . . . . . . . . . . . . . . . . . . . . . 19
Register write access . . . . . . . . . . . . . . . . . . . 19
Register read access . . . . . . . . . . . . . . . . . . . 20
High-speed mode . . . . . . . . . . . . . . . . . . . . . . 21
High-speed transfer . . . . . . . . . . . . . . . . . . . . 21
9.2.1
9.2.1.1
9.2.1.2
9.2.1.3
9.2.1.4
9.2.1.5
9.2.1.6
9.2.1.7
9.2.1.8
9.2.1.9
8.3.2.1
8.3.2.2
8.3.2.3
8.3.3
8.3.3.1
8.3.3.2
8.3.3.3
8.3.4
8.3.4.1
8.3.4.2
8.3.4.3
8.3.4.4
8.3.4.5
8.3.4.6
8.3.4.7
8.3.4.8
8.3.4.9
9.2.1.10 FIFODataReg register . . . . . . . . . . . . . . . . . . 42
9.2.1.11 FIFOLevelReg register. . . . . . . . . . . . . . . . . . 42
9.2.1.12 WaterLevelReg register . . . . . . . . . . . . . . . . . 43
9.2.1.13 ControlReg register . . . . . . . . . . . . . . . . . . . . 43
9.2.1.14 BitFramingReg register . . . . . . . . . . . . . . . . . 44
9.2.1.15 CollReg register . . . . . . . . . . . . . . . . . . . . . . . 44
9.2.1.16 Reserved register 0Fh . . . . . . . . . . . . . . . . . . 45
9.2.2
Page 1: Communication. . . . . . . . . . . . . . . . . 45
Reserved register 10h . . . . . . . . . . . . . . . . . . 45
ModeReg register . . . . . . . . . . . . . . . . . . . . . 46
TxModeReg register . . . . . . . . . . . . . . . . . . . 47
RxModeReg register . . . . . . . . . . . . . . . . . . . 47
TxControlReg register . . . . . . . . . . . . . . . . . . 48
TxASKReg register . . . . . . . . . . . . . . . . . . . . 49
TxSelReg register . . . . . . . . . . . . . . . . . . . . . 49
RxSelReg register . . . . . . . . . . . . . . . . . . . . . 50
RxThresholdReg register. . . . . . . . . . . . . . . . 51
9.2.2.1
9.2.2.2
9.2.2.3
9.2.2.4
9.2.2.5
9.2.2.6
9.2.2.7
9.2.2.8
9.2.2.9
8.3.4.10 Serial data transfer format in HS mode . . . . . 21
8.3.4.11 Switching between F/S mode and HS mode . 22
8.3.4.12 MFRC523 in lower speed modes . . . . . . . . . . 22
8.4
Analog interface and contactless UART. . . . . 23
General. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TX p-driver . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Serial data switch . . . . . . . . . . . . . . . . . . . . . . 25
MFIN and MFOUT interface support . . . . . . . 25
CRC coprocessor . . . . . . . . . . . . . . . . . . . . . . 27
FIFO buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Accessing the FIFO buffer . . . . . . . . . . . . . . . 27
Controlling the FIFO buffer . . . . . . . . . . . . . . . 27
FIFO buffer status information . . . . . . . . . . . . 27
Interrupt request system. . . . . . . . . . . . . . . . . 28
Interrupt sources overview . . . . . . . . . . . . . . . 28
Timer unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.5
8.5.1
8.5.2
8.5.3
8.6
9.2.2.10 DemodReg register . . . . . . . . . . . . . . . . . . . . 51
9.2.2.11 Reserved register 1Ah . . . . . . . . . . . . . . . . . . 52
9.2.2.12 Reserved register 1Bh . . . . . . . . . . . . . . . . . . 52
9.2.2.13 MfTxReg register . . . . . . . . . . . . . . . . . . . . . . 52
9.2.2.14 MfRxReg register. . . . . . . . . . . . . . . . . . . . . . 53
9.2.2.15 TypeBReg register . . . . . . . . . . . . . . . . . . . . . 53
9.2.2.16 SerialSpeedReg register . . . . . . . . . . . . . . . . 54
9.2.3
9.2.3.1
Page 2: Configuration . . . . . . . . . . . . . . . . . . 55
Reserved register 20h . . . . . . . . . . . . . . . . . . 55
8.6.1
8.7
continued >>
MFRC523
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
COMPANY PUBLIC
Rev. 3.7 — 8 November 2011
115237
97 of 98
MFRC523
NXP Semiconductors
Contactless reader IC
9.2.3.2
9.2.3.3
9.2.3.4
9.2.3.5
9.2.3.6
9.2.3.7
9.2.3.8
9.2.3.9
CRCResultReg registers . . . . . . . . . . . . . . . . 55
16.1.2
16.1.3
Test bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Test signals on pins AUX1 or AUX2. . . . . . . . 81
Reserved register 23h . . . . . . . . . . . . . . . . . . 56
ModWidthReg register . . . . . . . . . . . . . . . . . . 56
Reserved register 25h . . . . . . . . . . . . . . . . . . 56
RFCfgReg register . . . . . . . . . . . . . . . . . . . . . 57
GsNReg register. . . . . . . . . . . . . . . . . . . . . . . 57
CWGsPReg register . . . . . . . . . . . . . . . . . . . . 58
ModGsPReg register . . . . . . . . . . . . . . . . . . . 58
16.1.3.1 Example: Output test signals TestDAC1 and
TestDAC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
16.1.3.2 Example: Output test signals Corr1 and
MinLevel. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
16.1.3.3 Example: Output test signals ADC I-channel
and ADC Q-channel. . . . . . . . . . . . . . . . . . . . 83
16.1.3.4 Example: Output test signals RxActive and
TxActive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
16.1.3.5 Example: Output test signal RX data stream. 84
16.1.3.6 Pseudo-Random Binary Sequences (PRBS). 85
9.2.3.10 TModeReg and TPrescalerReg registers . . . . 58
9.2.3.11 TReloadReg register . . . . . . . . . . . . . . . . . . . 60
9.2.3.12 TCounterValReg register . . . . . . . . . . . . . . . . 60
9.2.4
Page 3: Test . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Reserved register 30h . . . . . . . . . . . . . . . . . . 61
TestSel1Reg register . . . . . . . . . . . . . . . . . . . 61
TestSel2Reg register . . . . . . . . . . . . . . . . . . . 62
TestPinEnReg register . . . . . . . . . . . . . . . . . . 62
TestPinValueReg register . . . . . . . . . . . . . . . . 63
TestBusReg register . . . . . . . . . . . . . . . . . . . . 63
AutoTestReg register . . . . . . . . . . . . . . . . . . . 63
VersionReg register . . . . . . . . . . . . . . . . . . . . 64
AnalogTestReg register . . . . . . . . . . . . . . . . . 64
9.2.4.1
9.2.4.2
9.2.4.3
9.2.4.4
9.2.4.5
9.2.4.6
9.2.4.7
9.2.4.8
9.2.4.9
17
18
19
20
21
22
23
Package outline. . . . . . . . . . . . . . . . . . . . . . . . 86
Handling information . . . . . . . . . . . . . . . . . . . 87
Packing information . . . . . . . . . . . . . . . . . . . . 87
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 89
Glossary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Revision history . . . . . . . . . . . . . . . . . . . . . . . 90
24
Legal information . . . . . . . . . . . . . . . . . . . . . . 91
Data sheet status. . . . . . . . . . . . . . . . . . . . . . 91
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Licenses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.2.4.10 TestDAC1Reg register . . . . . . . . . . . . . . . . . . 66
9.2.4.11 TestDAC2Reg register . . . . . . . . . . . . . . . . . . 66
9.2.4.12 TestADCReg register . . . . . . . . . . . . . . . . . . . 66
9.2.4.13 Reserved register 3Ch . . . . . . . . . . . . . . . . . . 67
24.1
24.2
24.3
24.4
24.5
10
MFRC523 command set . . . . . . . . . . . . . . . . . 68
General description . . . . . . . . . . . . . . . . . . . . 68
General behavior . . . . . . . . . . . . . . . . . . . . . . 68
MFRC523 command overview . . . . . . . . . . . . 68
MFRC523 command descriptions . . . . . . . . . 69
10.1
10.2
10.3
10.3.1
25
26
27
28
Contact information . . . . . . . . . . . . . . . . . . . . 92
Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
10.3.1.1 Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
10.3.1.2 Mem command. . . . . . . . . . . . . . . . . . . . . . . . 69
10.3.1.3 Generate RandomID . . . . . . . . . . . . . . . . . . . 69
10.3.1.4 CalcCRC command . . . . . . . . . . . . . . . . . . . . 69
10.3.1.5 Transmit command. . . . . . . . . . . . . . . . . . . . . 69
10.3.1.6 NoCmdChange command . . . . . . . . . . . . . . . 70
10.3.1.7 Receive command . . . . . . . . . . . . . . . . . . . . . 70
10.3.1.8 Transceive command . . . . . . . . . . . . . . . . . . . 70
10.3.1.9 MFAuthent command . . . . . . . . . . . . . . . . . . . 70
10.3.1.10 SoftReset command . . . . . . . . . . . . . . . . . . . . 71
11
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 71
Recommended operating conditions. . . . . . . 72
Thermal characteristics . . . . . . . . . . . . . . . . . 72
Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 72
Timing characteristics. . . . . . . . . . . . . . . . . . . 76
Application information. . . . . . . . . . . . . . . . . . 79
12
13
14
14.1
15
16
16.1
16.1.1
Test information. . . . . . . . . . . . . . . . . . . . . . . . 80
Test signals. . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Self-test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2011.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 8 November 2011
115237
相关型号:
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MFRC52302HN1/TRAYBM
SPECIALTY TELECOM CIRCUIT, PQCC32, 5 X 5 MM, 0.85 MM PITCH, PLASTIC, MO-220, SOT617-1, HVQFN-32
NXP
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