MIMX8MM4CVTLZCA_技术文档

Document Number: IMX8MMCEC

Rev. 1, 07/2020

NXP Semiconductors

Data Sheet: Technical Data

MIMX8MM6DVTLZAA MIMX8MM5DVTLZAA

MIMX8MM5DVTLZCA MIMX8MM5DVTLZDA

MIMX8MM4DVTLZAA MIMX8MM3DVTLZAA

MIMX8MM2DVTLZAA MIMX8MM1DVTLZAA

i.MX 8M Mini Applications

Processor Datasheet for

Consumer Products

Package Information

Plastic Package

FCBGA 14 x 14 mm, 0.5 mm pitch

Ordering Information

See Table 2 on page 6

1 i.MX 8M Mini introduction

The i.MX 8M Mini applications processor represents

NXP’s latest video and audio experience combining

1. i.MX 8M Mini introduction . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6

2. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.1. Recommended connections for unused input/output 12

3. Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14

3.1. Chip-level conditions . . . . . . . . . . . . . . . . . . . . . . 14

3.2. Power supplies requirements and restrictions . . . 23

3.3. PLL electrical characteristics . . . . . . . . . . . . . . . . 26

3.4. On-chip oscillators . . . . . . . . . . . . . . . . . . . . . . . . 27

3.6. I/O AC parameters . . . . . . . . . . . . . . . . . . . . . . . 29

3.5. General purpose I/O (GPIO) DC parameters . . . 28

3.7. Output buffer impedance parameters . . . . . . . . . 30

3.8. System modules timing . . . . . . . . . . . . . . . . . . . . 32

3.9. External peripheral interface parameters . . . . . . 33

4. Boot mode configuration . . . . . . . . . . . . . . . . . . . . . . . . 68

4.1. Boot mode configuration pins . . . . . . . . . . . . . . . 68

4.2. Boot device interface allocation . . . . . . . . . . . . . . 69

5. Package information and contact assignments . . . . . . . 70

5.1. 14 x 14 mm package information . . . . . . . . . . . . 70

5.2. DDR pin function list . . . . . . . . . . . . . . . . . . . . . . 87

6. Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

state-of-the-art

media-specific

features

with

high-performance processing while optimized for lowest

power consumption.

The i.MX 8M Mini family of processors features

®

advanced implementation of a quad Arm

Cor-

®

tex -A53 core, which operates at speeds of up to

®

1.8 GHz. A general purpose Cortex -M4 400 MHz

core processor is for low-power processing. The DRAM

controller supports 32-bit/16-bit LPDDR4, DDR4, and

DDR3L memory. A wide range of audio interfaces are

available, including I2S, AC97, TDM, and S/PDIF.

There are a number of other interfaces for connecting

peripherals, such as USB, PCIe, and Ethernet.

NXP reserves the right to change the production detail specifications as may be required

to permit improvements in the design of its products.

i.MX 8M Mini introduction

Table 1. Features

Subsystem

Features

Arm Cortex-A53 MPCore platform

Quad symmetric Cortex-A53 processors

• 32 KB L1 Instruction Cache

• 32 KB L1 Data Cache

• Media Processing Engine (MPE) with NEON technology supporting the Advanced

Single Instruction Multiple Data architecture:

• Floating Point Unit (FPU) with support of the VFPv4-D16 architecture

Support of 64-bit Armv8-A architecture

512 KB unified L2 cache

Arm Cortex-M4 core platform

Low power microcontroller available for customer application:

• low power standby mode

• IoT features including Weave

• Manage IR or Wireless Remote

Cortex M4 CPU:

• 16 KB L1 Instruction Cache

• 16 KB L1 Data Cache

• 256 KB tightly coupled memory (TCM)

Connectivity

One PCI Express (PCIe)

• Single lane supporting PCIe Gen2

• Dual mode operation to function as root complex or endpoint

• Integrated PHY interface

• Support L1 low power sub-state

Two USB 2.0 OTG controllers with integrated PHY interfaces:

• Spread spectrum clock support

Three Ultra Secure Digital Host Controller (uSDHC) interfaces:

• MMC 5.1 compliance with HS400 DDR signaling to support up to 400 MB/sec

• SD/SDIO 3.0 compliance with 200 MHz SDR signaling to support up to 100

MB/sec

• Support for SDXC (extended capacity)

One Gigabit Ethernet controller with support for Energy Efficient Ethernet (EEE),

Ethernet AVB, and IEEE 1588

Four Universal Asynchronous Receiver/Transmitter (UART) modules

Four I²C modules

Three ECSPI modules

On-chip memory

Boot ROM (256 KB)

On-chip RAM (256 KB + 32 KB)

GPIO and pin multiplexing

Power management

General-purpose input/output (GPIO) modules with interrupt capability

Input/output multiplexing controller (IOMUXC) to provide centralized pad control

Temperature sensor with programmable trip points

Flexible power domain partitioning with internal power switches to support efficient

power management

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

2

i.MX 8M Mini introduction

Table 1. Features (continued)

Features

Subsystem

External memory interface

32/16-bit DRAM interfaces:

• LPDDR4 (up to 1.5 GHz)

• DDR4-2400

• DDR3L-1600

8-bit NAND-Flash, including support for Raw MLC/SLC devices, BCH ECC up to

62-bit, and ONFi3.2 compliance (clock rates up to 100 MHz and data rates up to 200

MB/sec)

eMMC 5.1 Flash (2 interfaces, uSDHC1 and uSDHC3)

SPI NOR Flash (3 interfaces)

FlexSPI with support for XIP (for ME in low-power mode) and parallel read mode of

two identical FLASH devices

Multimedia

Video Processing Unit:

• 1080p60 VP9 Profile 0, 2 (10-bit)

• 1080p60 HEVC/H.265 Decoder

• 1080p60 AVC/H.264 Baseline, Main, High decoder

• 1080p60 VP8

• 1080p60 AVC/H.264 Encoder

• 1080p60 VP8

• TrustZone support

Graphic Processing Unit:

• GCNanoUltra for 3D acceleration

• GC320 for 2D acceleration

LCDIF Display Controller:

• Support up to 2 layers of overlay

• Support up to 1080p60 display through MIPI DSI

MIPI Interface:

• 4-lane MIPI CSI interface

• 4-lane MIPI DSI interface

Audio:

• S/PDIF input and output, including a new Raw Capture input mode

• Five synchronous audio interface (SAI) modules supporting I2S, AC97, TDM,

codec/DSP, and DSD interfaces, including one SAI with 8 Tx and 8 Rx lanes, one

SAI with 4 Tx and 4 Rx lanes, two SAI with 2 Tx and 2 Rx lanes, and one SAI with

1 Tx and 1Rx lane. Support over 20 channels of audio subject to I/O limitations.

• 8-Channel Pulse Density Modulation (PDM) input

System debug

Arm CoreSight debug and trace architecture

Trace Port Interface Unit (TPIU) to support off-chip real-time trace

Embedded Trace FIFO (ETF) with 4 KB internal storage to provide trace buffering

Unified trace capability for Quad Cortex-A53 and Cortex-M4 CPUs

Cross Triggering Interface (CTI)

Support for 5-pin (JTAG) debug interface

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

3

i.MX 8M Mini introduction

Table 1. Features (continued)

Features

Subsystem

Security

Resource Domain Controller (RDC) supports four domains and up to eight regions of

DDR

Arm TrustZone (TZ) architecture:

• Support Arm Cortex-A53 MPCore TrustZone

On-chip RAM (OCRAM) secure region protection using OCRAM controller

High Assurance Boot (HAB)

Cryptographic acceleration and assurance (CAAM) module and Assurance Module:

• Support Widevine and PlayReady content protection

• Public Key Cryptography (PKHA) with RSA and Elliptic Curve (ECC) algorithms

• Real-time integrity checker (RTIC)

• DRM support for RSA, AES, 3DES, DES

• Side channel attack resistance

• True random number generation (RNG)

• Manufacturing protection support

Secure non-volatile storage (SNVS):

• Secure real-time clock (RTC)

Secure JTAG controller (SJC)

NOTE

The actual feature set depends on the part numbers as described in Table 2.

Functions such as display and camera interfaces, and connectivity

interfaces, may not be enabled for specific part numbers.

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

4

NXP Semiconductors

i.MX 8M Mini introduction

1.1

Block diagram

Figure 1 shows the functional modules in the i.MX 8M Mini applications processor system.

Security

Main CPU Platform

Connectivity and I/O

1 GB Ethernet

TrustZone

Quad Cortex-A53

(IEEE1588, EEE, and AVB)

DRM Ciphers

Secure Clock

32 KB I-cache

NEON

32 KB D-cache

FPU

S/PDIF Rx and Tx

5x I2S/SAI

eFuse Key Storage

Random Number

512 KB L2 Cache

2x USB 2.0 OTG and PHY

1x PCIe 2.0 (1-lane)

Low Power, Security CPU

32 KB Secure RAM

Cortex-M4

4x UART

4x I2C, 3x ECSPI

PDM

System Control

16 KB D-cache

256 KB TCM

16 KB I-cache

3x Smart DMA

XTAL

PLLs

Multimedia

3D Graphics: GC NanoUltra

External Memory

3x Watchdog

4x PWM

6x Timer

LPDDR4/DDR4/DDR3L

2D Graphics: GC320

1080p60 H265, VP9 decoder

1080p60 H264, VP8 decoder

2x eMMC 5.1/3x SD 3.0

NAND CTL (BCH62)

1x FlexSPI

1080p60 H.264, VP8 encoder

Secure JTAG

4-lane MIPI-CSI Interface

4-lane MIPI-DSI Interface

Temperature Sensor

Figure 1. i.MX 8M Mini system block diagram

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

5

i.MX 8M Mini introduction

1.2

Ordering information

Table 2 shows examples of orderable sample part numbers covered by this data sheet. This table does not

include all possible orderable part numbers. If your desired part number is not listed in the table, or you

have questions about available parts, contact your NXP representative.

Table 2. Orderable part numbers

Cortex-A53

CPU speed

grade

Qualification Temperat

Family

Part number

Part differentiator

Package

tier

ure T_j(C)

i.MX 8M Mini MIMX8MM6DVTLZAA 4x A53, M4, GPU, VPU

Quad

1.8 GHz

Consumer

0 to +95 14 x 14 mm,

0.5 mm pitch

i.MX 8M Mini MIMX8MM5DVTLZAA

QuadLite

4x A53, M4, GPU

Consumer

0 to +95 14 x 14 mm,

0.5 mm pitch

i.MX 8M Mini MIMX8MM5DVTLZCA

QuadLite

4x A53, M4, GPU,

Immersiv3D with Dolby

ATMOS support¹

0 to +95 14 x 14 mm,

0.5 mm pitch

i.MX 8M Mini MIMX8MM5DVTLZDA

QuadLite

4x A53, M4, GPU,

Immersiv3D with Dolby

ATMOS and DTS

support¹

1.8 GHz

Consumer

0 to +95 14 x 14 mm,

0.5 mm pitch

i.MX 8M Mini MIMX8MM4DVTLZAA 2x A53, M4, GPU, VPU

Dual

1.8 GHz

Consumer

0 to +95 14 x 14 mm,

0.5 mm pitch

i.MX 8M Mini MIMX8MM3DVTLZAA

DualLite

2x A53, M4, GPU

0 to +95 14 x 14 mm,

0.5 mm pitch

i.MX 8M Mini MIMX8MM2DVTLZAA 1x A53, M4, GPU, VPU

Solo

0 to +95 14 x 14 mm,

0.5 mm pitch

i.MX 8M Mini MIMX8MM1DVTLZAA

SoloLite

1x A53, M4, GPU

0 to +95 14 x 14 mm,

0.5 mm pitch

1

Supply of this Implementation of Dolby technology does not convey a license nor imply a right under any patent, or any other

industrial or intellectual property right of Dolby Laboratories, to use this Implementation in any finished end-user or

ready-to-use final product. It is hereby notified that a license for such use is required from Dolby Laboratories.

Figure 2 describes the part number nomenclature so that the users can identify the characteristics of the

specific part number.

Contact an NXP representative for additional details.

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

6

NXP Semiconductors

i.MX 8M Mini introduction

MIMX8MM@+VT$$%A

Silicon revision

Qualification level

Part number series

Part differentiator

Fusing options

Primary core frequency

Package type – all ROHS

Qualification tier Tj

Qualification Level

Samples

Part differentiator

@

Frequency

1.8 GHz

$$

LZ

Temperature Tj

+

D

Consumer: 0 to +95^oC

P

i.MX 8M Mini Quad

4x A53, M4, GPU, VPU

6

Industrial: -40 to 105^oC

C

1.6 GHz

KZ

Mass Production

M

i.MX 8M Mini QuadLite

4x A53, M4, GPU

5

4

3

2

1

ROHS

Part number series

Name

Fusing

Package Type

FCBGA486

14 x 14 mm, 0.5 mm pitch

%

A

i.MX 8M Mini Dual

2x A53, M4, GPU, VPU

VT

Default

IMX8MM

i.MX 8M Mini

Immersiv3D enabled w/Dolby Atmos

C

D

i.MX 8M Mini DualLite

2x A53, M4, GPU

Immersiv3D enabled w/Dolby Atmos

and DTS

i.MX 8M Mini Solo

1x A53, M4, GPU, VPU

Silicon rev

A

i.MX 8M Mini SoloLite

1x A53, M4, GPU

Rev A0

A

Figure 2. Part number nomenclature—i.MX 8M Mini family of processors

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

7

Modules list

2 Modules list

The i.MX 8M Mini family of processors contains a variety of digital and analog modules. Table 3

describes these modules in alphabetical order.

Table 3. i.MX 8M Mini modules list

Block mnemonic

Block name

Brief description

32k Oscillator

Clock system

32 KHz oscillator is used as the clock source for RTC and internal

low speed clock. It can be supplied by external 32.768 KHz oscillator.

APBH-DMA

Arm

NAND Flash and BCH ECC

DMA Controller

DMA controller used for GPMI2 operation.

Arm Platform

The Arm Core Platform includes a quad Cortex-A53 core and a

Cortex-M4 core. The Cortex-A53 core includes associated

sub-blocks, such as the Level 2 Cache Controller, Snoop Control

Unit (SCU), General Interrupt Controller (GIC), private timers,

watchdog, and CoreSight debug modules. The Cortex-M4 core is

used as a customer microcontroller.

BCH

Binary-BCH ECC Processor The BCH module provides up to 62-bit ECC encryption/decryption

for NAND Flash controller (GPMI)

CAAM

Cryptographic accelerator and CAAM is a cryptographic accelerator and assurance module. CAAM

assurance module

implements several encryption and hashing functions, a run-time

integrity checker, entropy source generator, and a Pseudo Random

Number Generator (PRNG). The PRNG is certifiable by the

Cryptographic Algorithm Validation Program (CAVP) of the National

Institute of Standards and Technology (NIST).

CAAM also implements a Secure Memory mechanism. In i.MX 8M

Mini processors, the secure memory provided is 32 KB.

CCM

GPC

SRC

Clock Control Module, General These modules are responsible for clock and reset distribution in the

PowerController, SystemReset system, and also for the system power management.

Controller

CSU

Central Security Unit

The Central Security Unit (CSU) is responsible for setting

comprehensive security policy within the i.MX 8M Mini platform.

CTI-0

CTI-1

CTI-2

CTI-3

CTI-4

Cross Trigger Interface

Cross Trigger Interface (CTI) allows cross-triggering based on inputs

from masters attached to CTIs. The CTI module is internal to the

Cortex-A53 core platform.

DAP

Debug Access Port

The DAP provides real-time access for the debugger without halting

the core to access:

• System memory and peripheral registers

• All debug configuration registers

The DAP also provides debugger access to JTAG scan chains.

DDRC

Double Data Rate Controller The DDR Controller has the following features:

• Supports 32/16-bit LPDDR4 (up to 1.5 GHz), DDR4-2400, and

DDR3L-1600

• Supports up to 8 Gbyte DDR memory space

eCSPI1

eCSPI2

eCSPI3

Configurable SPI

Full-duplex enhanced Synchronous Serial Interface, with data rate

up to 52 Mbit/s. Configurable to support Master/Slave modes, only

one chip select is supported.

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

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8

Modules list

Table 3. i.MX 8M Mini modules list (continued)

Block mnemonic

Block name

Brief description

ENET1

Ethernet Controller

The Ethernet Media Access Controller (MAC) is designed to support

10/100/1000 Mbps Ethernet/IEEE 802.3 networks. An external

transceiver interface and transceiver function are required to

complete the interface to the media. The module has dedicated

hardware to support the IEEE 1588 standard. See the ENET chapter

of the i.MX 8M Mini Applications Processor Reference Manual

(IMX8MMRM) for details.

FlexSPI

The FlexSPI module acts as an interface to external serial flash

devices. This module contains the following features:

• Flexible sequence engine to support various flash vendor devices

• Single pad/Dual pad/Quad pad mode of operation

• Single Data Rate/Double Data Rate mode of operation

• Parallel Flash mode

• DMA support

• Memory mapped read access to connected flash devices

• Multi master access with priority and flexible and configurable

buffer for each master

GIC

Generic Interrupt Controller

The GIC handles all interrupts from the various subsystems and is

ready for virtualization.

GPIO1

GPIO2

GPIO3

GPIO4

GPIO5

General Purpose I/O Modules Used for general purpose input/output to external ICs. Each GPIO

module supports up to 32 bits of I/O.

GPMI

General Purpose Memory

Interface

The GPMI module supports up to 8x NAND devices and 62-bit ECC

encryption/decryption for NAND Flash Controller (GPMI2). GPMI

supports separate DMA channels for each NAND device.

GPT1

GPT2

GPT3

GPT4

GPT5

GPT6

General Purpose Timer

Each GPT is a 32-bit “free-running” or “set-and-forget” mode timer

with programmable prescaler and compare and capture register. A

timer counter value can be captured using an external event and can

be configured to trigger a capture event on either the leading or

trailing edges of an input pulse. When the timer is configured to

operate in “set-and-forget” mode, it is capable of providing precise

interrupts at regular intervals with minimal processor intervention.

The counter has output compare logic to provide the status and

interrupt at comparison. This timer can be configured to run either on

an external clock or on an internal clock.

GPU3D

Graphics Processing Unit-3D The GPU3D provides hardware acceleration for 3D graphics

algorithms with sufficient processor power to run desktop quality

interactive graphics applications on displays.

I2C1

I2C2

I2C3

I2C4

I²C Interface

I²C provides serial interface for external devices. Data rates of up to

320 kbps are supported.

IOMUXC

IOMUX Control

This module enables flexible I/O multiplexing. Each IO pad has a

default as well as several alternate functions. The alternate functions

are software configurable.

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

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9

Modules list

Table 3. i.MX 8M Mini modules list (continued)

Block mnemonic

Block name

Brief description

MIPI CSI2 (four-lane)

MIPI Camera Serial Interface This module provides one four-lane MIPI camera serial interfaces,

which operates up to a maximum bit rate of 1.5 Gbps.

MIPI DSI (four-lane)

OCOTP_CTRL

MIPI Display Serial Interface This module provides a four-lane MIPI display serial interface

operating up to a maximum bit rate of 1.5 Gbps.

OTP Controller

The On-Chip OTP controller (OCOTP_CTRL) provides an interface

for reading, programming, and/or overriding identification and control

information stored in on-chip fuse elements. The module supports

electrically programmable poly fuses (eFUSEs). The OCOTP_CTRL

also provides a set of volatile software-accessible signals that can be

used for software control of hardware elements, not requiring non

volatility. The OCOTP_CTRL provides the primary user-visible

mechanism for interfacing with on-chip fuse elements. Among the

uses for the fuses are unique chip identifiers, mask revision

numbers, cryptographic keys, JTAG secure mode, boot

characteristics, and various control signals requiring permanent non

volatility.

OCRAM

On-Chip Memory controller

The On-Chip Memory controller (OCRAM) module is designed as an

interface between the system’s AXI bus and the internal (on-chip)

SRAM memory module.

In i.MX 8M Mini processors, the OCRAM is used for controlling the

256 KB multimedia RAM through a 64-bit AXI bus.

PCIe1

PDM

PMU

PCI Express 2.0

The PCIe IP provides PCI Express Gen 2.0 functionality.

The PDM supports up to 8-channels (4 lanes).

Pulse Density Modulation

Power Management Unit

Integrated power management unit. Used to provide power to

various SoC domains.

PWM1

PWM2

PWM3

PWM4

Pulse Width Modulation

The pulse-width modulator (PWM) has a 16-bit counter and is

optimized to generate sound from stored sample audio images. It

can also generate tones. It uses 16-bit resolution and a 4x16 data

FIFO to generate sound.

SAI1

SAI2

SAI3

SAI5

SAI6

Synchronous Audio Interface The SAI module provides a synchronous audio interface (SAI) that

supports full duplex serial interfaces with frame synchronization,

such as I2S, AC97, TDM, and codec/DSP interfaces.

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

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10

Modules list

Table 3. i.MX 8M Mini modules list (continued)

Block name Brief description

Block mnemonic

SDMA

Smart Direct Memory Access The SDMA is a multichannel flexible DMA engine. It helps in

maximizing system performance by offloading the various cores in

dynamic data routing. It has the following features:

• Powered by a 16-bit Instruction-Set micro-RISC engine

• Multi channel DMA supporting up to 32 time-division multiplexed

DMA channels

• 48 events with total flexibility to trigger any combination of

channels

• Memory accesses including linear, FIFO, and 2D addressing

• Shared peripherals between Arm and SDMA

• Very fast Context-Switching with 2-level priority based preemptive

multi tasking

• DMA units with auto-flush and prefetch capability

• Flexible address management for DMA transfers (increment,

decrement, and no address changes on source and destination

address)

• DMA ports can handle unidirectional and bidirectional flows (Copy

mode)

• Up to 8-word buffer for configurable burst transfers for EMIv2.5

• Support of byte-swapping and CRC calculations

• Library of Scripts and API is available

SJC

Secure JTAG Controller

The SJC provides JTAG interface (designed to be compatible with

JTAG TAP standards) to internal logic. The i.MX 8M Mini family of

processors uses JTAG port for production, testing, and system

debugging. Additionally, the SJC provides BSR (Boundary Scan

Register) standard support, designed to be compatible with IEEE

1149. 1.

The JTAG port must be accessible during platform initial laboratory

bring-up, for manufacturing tests and troubleshooting, as well as for

software debugging by authorized entities. The i.MX 8M Mini SJC

incorporates three security modes for protecting against

unauthorized accesses. Modes are selected through eFUSE

configuration.

SNVS

Secure Non-Volatile Storage Secure Non-Volatile Storage, including Secure Real Time Clock,

Security State Machine, Master Key Control, and Violation/Tamper

Detection and reporting.

SPDIF1

Sony Philips Digital

Interconnect Format

A standard audio file transfer format, developed jointly by the Sony

and Phillips corporations. It supports Transmitter and Receiver

functionality.

TEMPSENSOR

TZASC

Temperature Sensor

Temperature sensor

Trust-Zone Address Space

Controller

The TZASC (TZC-380 by Arm) provides security address region

control functions required for intended application. It is used on the

path to the DRAM controller.

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

11

Modules list

Table 3. i.MX 8M Mini modules list (continued)

Block mnemonic

Block name

Brief description

UART1

UART2

UART3

UART4

UART Interface

Each of the UARTv2 modules supports the following serial data

transmit/receive protocols and configurations:

• 7- or 8-bit data words, 1 or 2 stop bits, programmable parity (even,

odd, or none)

• Programmable baud rates up to 4 Mbps. This is a higher max

baud rate relative to the 1.875 MHz, which is stated by the

TIA/EIA-232-F standard.

• 32-byte FIFO on Tx and 32 half-word FIFO on Rx supporting

auto-baud

uSDHC1

uSDHC2

uSDHC3

SD/MMC and SDXC

i.MX 8M Mini SoC characteristics:

Enhanced Multi-Media Card / All the MMC/SD/SDIO controller IPs are based on the uSDHC IP.

Secure Digital Host Controller They are designed to support:

• SD/SDIO standard, up to version 3.0.

• MMC standard, up to version 5.1.

• 1.8 V and 3.3 V operation, but do not support 1.2 V operation.

• 1-bit/4-bit SD and SDIO modes, 1-bit/4-bit/8-bit MMC mode.

Two uSDHC controllers (uSDHC1 and uSDHC3) can support up to

an 8-bit interface, the other controller (uSDHC2) can only support up

to a 4-bit interface.

USB1

USB2

2x USB 2.0 controllers and

PHYs

Two USB controllers and PHYs that support USB 2.0. Each USB

instance contains:

• USB 2.0 core, which can operate in 2.0 mode

VPU

Video Processing Unit

A high performing video processing unit (VPU), which covers many

SD-level and HD-level video decoders. See the i.MX 8M Mini

Applications Processor Reference Manual (IMX8MMRM) for a

complete list of the VPU’s decoding and encoding capabilities.

WDOG1

WDOG2

WDOG3

Watchdog

The watchdog (WDOG) timer supports two comparison points

during each counting period. Each of the comparison points is

configurable to evoke an interrupt to the Arm core, and a second

point evokes an external event on the WDOG line.

XTALOSC

Crystal Oscillator interface

The XTALOSC module enables connectivity to an external crystal

oscillator device. In a typical application use case, it is used for a 24

MHz oscillator.

2.1

Recommended connections for unused input/output

If a function of the i.MX 8M Mini is not in use, the I/Os and power rails of that function can be terminated

to reduce overall board power.

Table 4 shows the recommended connections for unused power supply rails.

Table 4. Recommended connections for unused power supply rails

Recommendations

Function

Ball Name

if Unused

MIP-CSI and

MIPI-DSI

VDD_MIPI_0P9, VDD_MIPI_1P2, VDD_MIPI_1P8

Leave unconnected

PCIe

VDD_PCI_0P8, VDD_PCI_1P8

Leave unconnected

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

12

Modules list

Table 4. Recommended connections for unused power supply rails (continued)

Recommendations

if Unused

Function

Ball Name

USB1 and USB2 VDD_USB_0P8, VDD_USB_1P8, VDD_USB_3P3

Leave unconnected

All digital I/O

VPU

GPU

VDD_VPU

VDD_GPU

Digital I/O

supplies

NVCC_CLK, NVCC_ECSPI, NVCC_ENET, NVCC_GPIO1, NVCC_I2C,

NVCC_JTAG, NVCC_NAND, NVCC_SAI1, NVCC_SAI2, NVCC_SAI3, NVCC_SAI5, supplies listed in this

NVCC_SD1, NVCC_SD2, NVCC_UART, NVCC_SNVS_1P8, PVCC0_1P8,

PVCC1_1P8, PVCC2_1P8

table must be

powered under

normal conditions

whether the

associated I/O pins

are in use or not, and

associated I/O pins

need to enable pull

in pad control

register to limit any

floating gate current.

Table 5 shows recommended connections for unused signal contacts/interfaces.

Table 5. Recommended connections for unused signal contacts/interfaces

Recommendations

Function

Ball Name

if Unused

MIPI-CSI

MIPI_CSI_CLK_P, MIPI_CSI_CLK_N, MIPI_CSI_Dx_P, MIPI_CSI_Dx_N

Tie all signals to

ground

MIPI-DSI

PCIe

MIPI_VREG_CAP, MIPI_DSI_CLK_P, MIPI_DSI_CLK_N, MIPI_DSI_Dx_P,

MIPI_DSI_Dx_N

Leave unconnected

PCIE_CLK_P, PCIE_CLK_N, PCIE_TXN_P, PCIE_TXN_N, PCIE_RXN_P,

PCIE_RXN_N, PCIE_RESREF

Leave unconnected

USB1

USB2

USB1_VBUS, USB1_DN, USB1_DP, USB1_ID, USB1_TXRTUNE

USB2_VBUS, USB2_DN, USB2_DP, USB2_ID, USB2_TXRTUNE

Leave unconnected

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

13

Electrical characteristics

3 Electrical characteristics

This section provides the device and module-level electrical characteristics for the i.MX 8M Mini family

of processors.

3.1

Chip-level conditions

This section provides the device-level electrical characteristics for the IC. See Table 6 for a quick reference

to the individual tables and sections.

Table 6. i.MX 8M Mini chip-level conditions

For these characteristics, …

Absolute maximum ratings

Topic appears …

on page 14

on page 16

on page 17

on page 19

on page 20

FCBGA package thermal resistance

Operating ranges

External clock sources

Maximum supply currents

3.1.1

Absolute maximum ratings

CAUTION

Stresses beyond those listed under Table 7 may affect reliability or cause

permanent damage to the device. These are stress ratings only. Functional

operation of the device at these or any other conditions beyond those

indicated in the operating ranges or parameters tables is not implied.

Table 7. Absolute maximum ratings

Parameter description

Symbol

Min

Max

Unit

Notes

Core supply voltages

VDD_ARM

VDD_SOC

-0.3

1.15

V

—

Power supply for GPU

Power supply for VPU

DDR PHY supply voltage

DDR I/O supply voltage

DRAM PLL supply voltage

VDD_GPU

VDD_VPU

-0.3

1.15

1.575

1.15

2.15

0.95

V

—

VDD_DRAM

NVCC_DRAM

VDD_DRAM_PLL_0P8

VDD_DRAM_PLL_1P8

NVCC_SNVS_1V8

VDD_SNVS_0V8

SNVS IO supply voltage

VDD_SNVS supply voltage

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

14

Electrical characteristics

Table 7. Absolute maximum ratings (continued)

Parameter description

Symbol

Min

Max

Unit

Notes

GPIO supply voltage

NVCC_JTAG,

NVCCGPIO1,

NVCC_ENET,

NVCC_SD1,

NVCC_SD2,

NVCC_NAND,

NVCC_SA1,

NVCC_SAI2,

NVCC_SAI3,

NVCC_SAI5,

NVCC_ECSPI,

NVCC_I2C,

-0.3

3.8

V

—

NVCC_UART,

NVCC_CLK

GPIO pre-driver supply voltage

PVCC0_1P8,

PVCC1_1P8,

PVCC2_1P8

-0.3

2.15

V

—

Isolated core supply voltage

Analog core supply voltage

VDD_ANA_0P8

VDD_ANA0_1P8

VDD_ANA1_1P8

VDD_ARM_PLL_0P8

VDD_ARM_PLL_1P8

VDD_MIPI_0P9

VDD_MIPI_1P2

VDD_MIPI_1P8

VDD_PCIE_0P8

VDD_PCIE_1P8

VDD_USB_0P8

VDD_USB_1P8

VDD_USB_3P3

-0.3

1.15

2.15

0.95

2.15

1.05

1.45

2.15

0.95

2.15

0.95

2.15

3.95

V

—

Arm PLL supply voltage

MIPI PHY supply voltage

PCIe PHY supply voltage

USB PHY supply voltage

USB_VBUS input detected

USB1_VBUS,

USB2_VBUS

XTAL supply voltage

VDD_24M_XTAL_1P8

T_STORAGE

-0.3

-40

2.15

150

V

—

Storage temperature range

^oC

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

15

Electrical characteristics

Table 8. Electrostatic discharge and latch up ratings

Parameter description

Rating

Reference

Comment

Electrostatic Discharge

(ESD)

Human Body Model (HBM)

1000 V

250 V

JS-001-2017

JS-002-2018

—

Charged Device Model (CDM)

Latch UP (LU)

Immunity level:

• Class I@ 25 ^oC ambient

temperature

A

JESD78E

• Class II @ 105 ^oC ambient

temperature

3.1.2

Thermal resistance

3.1.2.1

FCBGA package thermal resistance

Table 9 displays the FCBGA package thermal resistance data.

Table 9. Thermal resistance data

Rating

Junction to Ambient

Test conditions

Symbol

R_JA

Value

Unit Notes

1, 2

Single layer board (1s)

30

^oC/W

Natural Convection

1, 2, 3

Junction to Ambient

Natural Convection

Four layer board (2s2p)

R_JA

22.9

^oC/W

1, 3

4

Junction to Ambient (@200 ft/min)

Junction to Board

Single layer board (1s)

R_JMA

R_JB

R_JC

_JT

24

18.5

7.8

4

^oC/W

Four layer board (2s2p)

—

5

Junction to Case

—

6

Junction to Package Top

Natural Convection

0.2

1

Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal

resistance.

2

3

4

Per SEMI G38-87 and JESD51-2 with the single layer board horizontal.

Per JEDEC JESD51-6 with the board horizontal.

Thermal resistance between the die and printed circuit board per JEDEC JESD51-8. Board temperature is measured on the

top surface of the board near the package.

5

6

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written

as Psi-JT.

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

16

NXP Semiconductors

Electrical characteristics

3.1.3

Operating ranges

Table 10 provides the operating ranges of the i.MX 8M Mini applications processor. For details on the

chip's power structure, see the “Power Management Unit (PMU)” chapter of the i.MX 8M Mini

Applications Processor Reference Manual (IMX8MMRM).

1

Table 10. Operating ranges

,

Symbol

Min

Typ

Max^{2 3}

Unit

Comment

VDD_ARM

0.805

0.900

0.950

0.780

0.805

0.850

0.950

1.000

0.820

0.850

0.950

1.000

1.050

0.900

V

Power supply for Quad-A53, 1.2 GHz

Power supply for Quad-A53, 1.6 GHz

Power supply for Quad-A53, 1.8 GHz⁴

Power supply for SoC logic⁵

VDD_SOC without PCIE

VDD_SOC with PCIE

VDD_GPU

Power supply for SoC logic⁵

Power supply for 3D GPU,

nominal mode, 800 MHz

0.855

—

0.900

—

1.000

—

V

Power supply for 3D GPU,

overdrive mode, 1000 MHz

VDD_VPU

—

Block

G2/G1/H1

0.805

0.855

0.900

0.805

0.850

0.900

0.950

0.850

0.900

0.950

1.000

0.900

V

Power supply for VPU, 450/450/450 MHz

Power supply for VPU, 600/650/650 MHz

Power supply for VPU, 700/750/750 MHz

VDD_DRAM

Power supply for DDRC, 0.85 V supports

up to 1.0 GHz (DDR clock)

0.855

0.900

0.950

1.000

V

Power supply for DDRC, 0.9 V supports

up to 1.2 GHz (DDR clock)

Power supply for DDRC, 0.95 V supports

up to 1.5 GHz (DDR clock)

VDD_SNVS_0P8

NVCC_SNVS_1P8

0.760

1.620

0.800

1.800

0.900

1.980

V

Power supply for SNVS core logic

Power supply for GPIO pre-driver in

SNVS bank

NVCC_JTAG,

NVCC_GPIO1,

1.650

3.000

1.800

3.300

1.950

3.600

V

Power supply for GPIO when it is in 1.8 V

mode

NVCC_ENET, NVCC_SD1,

NVCC_SD2,NVCC_NAND,

NVCC_SAI1, NVCC_SAI2,

NVCC_SAI3, NVCC_SAI5,

NVCC_ECSPI, NVCC_I2C,

NVCC_UART,

Power supply for GPIO when it is in 3.3 V

mode

NVCC_CLK

NVCC_ENET

2.250

2.500

2.750

V

Power supply for GPIO when it is in 2.5 V

mode

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

17

Electrical characteristics

Symbol

1

Table 10. Operating ranges (continued)

,

Min

Typ

Max^{2 3}

Unit

Comment

PVCC0_1P8,

PVCC1_1P8,

PVCC2_1P8

1.650

1.800

1.950

V

Power supply for GPIO pre-driver

VSS

—

1.35

1.2

—

V

Ground for all core logic and I/O

NVCC_DRAM

1.283

1.14

1.425

1.26

DDR3L

DDR4

1.06

1.1

1.17

LPDDR4

DRAM_VREF

0.49 x

0.5 x

0.51 x

Internal output, no connection is needed.

NVCC_DRAM NVCC_DRAM NVCC_DRAM

VDD_DRAM_PLL_0P8

0.805

0.850

1.000

V

0.8 V logic power supply for DSM. It

should be connected to the separate

logic power.

VDD_ANA0_1P8

VDD_ANA1_1P8

1.71

1.8

1.89

Analog 1.8 V core power

VDD_ANA_0P8

VDD_ARM_PLL_0P8

VDD_ARM_PLL_1P8

VDD_24M_XTAL_1P8

VDD_DRAM_PLL_1P8

VDD_MIPI_0P9

0.780

1.71

0.820

1.8

0.900

1.89

V

Isolated 0.8 V core power

Arm PLL 0.8 V power

Arm PLL 1.8 V power

1.71

1.8

1.89

XTAL 1.8 V power

1.71

1.8

1.89

Analog 1.8 V core power

0.9 V power for PLL and internal logic

1.2 V power for analog

0.855

1.14

0.9

1.000

1.26

VDD_MIPI_1P2

1.2

VDD_MIPI_1P8

1.71

1.8

1.89

1.8 V power for PLL and analog

Digital supply for PCIe PHY

1.8 V supply for PCIe PHY

VDD_PCI_0P8^6,7

VDD_PCI_1P8⁶

0.805

1.71

0.850

1.800

0.820

0.900

1.890

0.900

VDD_USB_0P8

0.780

Digital power supply from PHY’s I/O

power pads

VDD_USB_1P8

VDD_USB_3P3

1.71

3.069

0.800

1.80

3.30

1.40

1.89

3.6

V

1.8 V analog power supply

3.3 V analog power supply

USB_VBUS input detect signal

USB1_VBUS

USB2_VBUS

3.60

Temperature Sensor

Accuracy⁸

—

0

3

5

°C Sensing temperature range 10°C to

105°C

T

J

—

+95

^oC See Table 2 for complete list of junction

temperature capabilities.

1

The BD71847MWV PMIC does not support 0.950 V for VDD_GPU, VDD_VPU, and VDD_DRAM. For this PMIC, 0.975 V

typical is acceptable and supported.

2

Applying the maximum voltage results in maximum power consumption and heat generation. A voltage set point = (Vmin + the

supply tolerance) is recommended. This results in an optimized power/speed ratio.

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NXP Semiconductors

Electrical characteristics

3

4

5

Overdrive maximum voltage includes all the nominal frequencies.

50% duty cycle for 5 years

Booting VDD_SOC at 0.800 V 5% is acceptable (Vmin = 0.760 V). Software is expected to program the VDD_SOC voltage

to the typical value in this table prior to first DRAM memory access.

6

Ensure the VDD_PCI_1P8 does not have more than 40 mVpp AC power supply noise superimposed on the high power supply

voltage for the PHY core (1.8 V nominal DC value). Simultaneously, the VDD_PCI_0P8 should have no more than 20 mVpp

AC power supply noise superimposed on the low power supply voltage for th PHY core (0.9 V nominal DC value for the

overdrive).

7

8

It can be min 0.78 V when supplied but not operating PCIe.

“EN” of TMU Enable Register (TMU_TER) is required to be always enabled for the part to operate correctly.

3.1.4

External clock sources

Each i.MX 8M Mini processor has two external input system clocks: a low frequency (RTC_XTALI) and

a high frequency (XTALI).

The RTC_XTALI is used for low-frequency functions. It supplies the clock for wake-up circuit,

power-down real time clock operation, and slow system and watch-dog counters. The clock input can only

be connected to an external oscillator. RTC_XTALO should be directly connected to VDD_SNVS_0P8.

The system clock input XTALI is used to generate the main system clock. It supplies the PLLs and other

peripherals. The system clock input can be connected to either an external oscillator or a crystal using

internal oscillator amplifier.

Table 11 shows the interface frequency requirements.

Table 11. External input clock frequency

Parameter Description

RTC_XTALI Oscillator¹

XTALI Oscillator^1,3

Symbol

Min

Typ

Max

Unit

f_ckil

f_xtal

—

32.768²

24

—

kHz

MHz

1

2

3

The required frequency stability of this clock source is application dependent.

Recommended nominal frequency 32.768 kHz.

External oscillator or a fundamental frequency crystal appropriately coupled to the internal oscillator amplifier.

The typical values shown in Table 11 are required for use with NXP software to ensure precise time

keeping and USB operation. For RTC_XTALI operation, an external oscillator is necessary. RTC_XTALO

should be directly connected to VDD_SNVS_0P8 when using an external 32.768 kHz oscillator.

NOTE

There is no internal RC oscillator.

Table 12 shows the external input clock for OSC32K.

Table 12. External input clock for OSC32K

Symbol

Min

Typ

Max

Unit

Frequency

f

—

32.768

—

kHz

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

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19

Electrical characteristics

Table 12. External input clock for OSC32K

Symbol

Min

Typ

Max

Unit

RTC_XTALI

VIH

VIL

0.7 x NVCC_SNVS_1P8

0

—

NVCC_SNVS_1P8

V

0.3 x NVCC_SNVS_1P8

3.1.5

Maximum supply currents

Power consumption is highly dependent on the application. Estimating the maximum supply currents

required for power supply design is difficult because the use cases that requires maximum supply current

is not a realistic use cases.

To help illustrate the effect of the application on power consumption, data was collected while running

consumer standard benchmarks that are designed to be compute and graphic intensive. The results

provided are intended to be used as guidelines for power supply design.

Table 13. Maximum supply currents

Power rail

Max current

Unit

VDD_ARM

VDD_SOC

2200

1000

500

mA

VDD_GPU

VDD_VPU

1000

50

VDD_DRAM

VDD_ANA_0P8

VDD_ANA0_1P8

VDD_ANA1_1P8

250

NVCC_SNVS_1P8

3

mA

VDD_ARM_PLL_1P8

VDD_24M_XTAL_1P8

100

PVCCx_1P8

NVCC_<XXX>

NVCC_DRAM

3

mA

I_max= N x C x V x (0.5 x F)

Where:

N—Number of IO pins supplied by the power line

C—Equivalent external capacitive load

V—IO voltage

(0.5 x F)—Data change rate. Up to 0.5 of the clock

rate (F).

In this equation, I_maxis in Amps, C in Farads, V in

Volts, and F in Hertz.

DRAM_VFEF

10

mA

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

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20

Electrical characteristics

3.1.6

Power modes

The i.MX 8M Mini processors support the following power modes:

•

RUN Mode: All external power rails are on, CPU is active and running; other internal modules can

be on/off based on application.

•

IDLE Mode: When there is no thread running and all high-speed devices are not active, the CPU

can automatically enter this mode. The CPU can be in the power-gated state but with L2 data

retained, DRAM and the bus clock are reduced. Most of the internal logic is clock gated but still

remains powered. The M4 core can remain running. Compared with RUN mode, all the external

power rails from the PMIC remain the same, and most of the modules still remain in their state.

•

SUSPEND Mode: The most efficient power saving mode where all the clocks are off and all the

unnecessary power supplies are off.

SNVS Mode: This mode is also called RTC mode. Only the power for the SNVS domain remains

on to keep RTC and SNVS logic alive.

OFF Mode: All power rails are off.

Table 14. Chip power in different LP mode

Mode

Supply

Typ.¹

Unit

SNVS

VDD_SNVS_0P8 (0.8 V)

NVCC_SNVS_1P8 (1.8 V)

Total²

0.02

0.09

0.11

1.20

0.50

0.10

0.60

2.20

0.10

4.00

0.10

3.00

11.90

mW

SUSPEND

NVCC (1.8 V)

NVCC_DRAM (1.1 V)

NVCC_ENET (1.8 V)

NVCC_SNVS_1P8 (1.8 V)

PVCC (1.8 V)

mW

VDD_MIPI_0P9 (0.9 V)

VDD_SNVS_0P8 (0.8 V)

VDD_SOC (0.82 V)

VDD_ARM_0P8 (0.82 V)

VDDA_PCIE_USB_0P8 (0.82 V)

Total²

1

All the power numbers defined in the table are for information only. These numbers are based on typical silicon at 25^oC, under

non-OS environment and use case dependent. For power numbers with OS and real use cases, see Power consumption

measurement application note for more details.

2

Sum of the listed supply rails.

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

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21

Electrical characteristics

Table 15 summarizes the external power supply states in all the power modes.

Table 15. The power supply states

Power rail

VDD_ARM

OFF

SNVS

SUSPEND

OFF

IDLE

RUN

OFF

ON

OFF

ON

VDD_SOC

ON

VDD_GPU

OFF

ON

ON/OFF

ON

VDD_VPU

VDD_DRAM

Misc_1P8¹

ON

Misc_0P8¹

ON

VDD_MIPI_1P2

VDD_MIPI_0P9

VDD_DRAM_PLL_0P8

VDD_SNVS_0P8

NVCC_SNVS_1P8

NVCC_<XXX>

PVCCx_1P8

OFF

ON

OFF

ON

NVCC_DRAM

ON

1

See Table 16

Table 16. Group name

VDD_24M_XTAL_1P8

Misc_1P8

VDD_ANA0_1P8

VDD_ANA1_1P8

VDD_ARM_PLL_1P8

VDD_DRAM_PLL_1P8

VDD_MIPI_1P8

VDD_PCI_1P8

VDD_USB_1P8

Misc_0P8

VDD_ANA_0P8

VDD_ARM_PLL_0P8

VDD_PCI_0P8

VDD_USB_0P8

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

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22

Electrical characteristics

3.2

Power supplies requirements and restrictions

The system design must comply with power-up sequence, power-down sequence, and steady state

guidelines as described in this section to guarantee the reliable operation of the device. Any deviation

from these sequences may result in the following situations:

•

Excessive current during power-up phase

Prevention of the device from booting

Irreversible damage to the processor (worst-case scenario)

3.2.1

Power-up sequence

Figure 5 illustrates the power-up sequence of i.MX 8M Mini processor.

NVCC_SNVS_1P8

T1

VDD_SNVS_0P8

T2

RTC_RESET_B

T3

32K RTC_XTALI

t1

PMIC_ON_REQ

T4

VDD_SOC,VDD_ANA_0P8,VDD_ARM_PLL_0P8

VDD_PCI_0P8,VDD_USB_0P8

T5

VDD_GPU,VDD_VPU,VDD_DRAM,

VDD_DRAM_PLL_0P8

T6

VDD_MIPI_0P9

T7

VDD_ARM

VDD_ANAx_1P8,VDD_DRAM_PLL_1P8,VDD_MIPI_1P8,

VDD_24M_XTAL_1P8,VDD_USB_1P8,VDD_PCI_1P8

VDD_ARM_PLL_1P8

T8

T9

PVCCx_1P8, NVCC_xxx (1.8 V)

T10

T11

NVCC_DRAM

NVCC_xxx (2.5 and 3.3 V),VDD_USB_3P3

T12

T13

VDD_MIPI_1P2

POR_B

Figure 3. The power-up sequence

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

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23

Electrical characteristics

Table 17 represents the timing parameters of the power-up sequence.

Table 17. Power-up sequence

Description

Min

Typ

Max

Unit

T1

T2

Delay from NVCC_SNVS_1P8 to VDD_SNVS_0P8

Delay from VDD_SNVS_0P8 high or RTC_SET_B de-assert

Delay from RTC_RESET_B de-assert to stable 32 k existed

Delay from PMIC_ON_REQ assert to analog 0.8 V on

Delay from analog 0.8 V on to analog 0.8/0/9 V on

Delay from analog 0.8/0.9 V on to PHY 0.9 V on

Delay from PHY 0.9 V on to VDD_ARM on

0

—

0

2

10

40

0.2

2

—

100

—

ms

s

T3

T4

ms

s

T5

T6

15

2

T7

ms

s

T8

Delay from VDD_ARM on to analog 1.8 V on

15

2

T9

Delay from analog 1.8 V on to digital 1.8 V on

ms

T10

T11

T12

T13¹

t1

Delay from digital 1.8 V on to NVCC_DRAM on

Delay from NVCC_DRAM on to digital 2.5 V and 3.3 V on

Delay from digital 2.5 V and 3.3 V on to PHY 1.2 V on

Delay from PHY 1.2 V on to POR_B de-assert

2

20

Uncertain period before PMIC_ON_REQ assert during VDD_SNVS_0P8 ramp up.

For ramp up requirement, only VDD_ANA0_1P8 has 5 s minimum requirement, others do not have such

requirement.

During power-up, make sure NVCC_xxx - PVCCx_1P8 < 2 V.

1

The values of T13 depend on T2. RTC_RESET_B must be de-assert before POR_B de-asserts.

3.2.2

Power-down sequence

Figure 5 illustrates the power-down sequence of i.MX 8M Mini processor.

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

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NXP Semiconductors

Electrical characteristics

VDD_MIPI_1P2

T1

NVCC_xxx (2.5 and 3.3 V)

NVCC_DRAM

T2

T3

PVCCx_1P8, NVCC_xxx (1.8V)

T4

VDD_ANAx_1P8, VDD_DRAM_PLL_1P8,VDD_MIPI_1P8

VDD_24M_XTAL_1P8,VDD_USB_1P8,VCC_PCI_1P8

T5

VDD_ARM

T6

VDD_MIPI_0P9

T7

VDD_GPU, VDD_VPU, VDD_DRAM

VDD_DRAM_PLL_0P8

T8

VDD_SOC, VDD_ANA_0P8

VDD_PCI_0P8, VDD_USB_0P8

T9

32K RTC_XTALI

RTC_RESET_B

T10

T11

T12

VDD_SNVS_0P8

NVCC_SNVS_1P8

Figure 4. The power-down sequence

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Table 18 represents the timing parameters of the power-down sequence.

Table 18. Power-down sequence

Description

Min

Typ

Max

Unit

T1

T2

Delay from PHY 1.2 V off to digital 2.5 V and 3.3 V off

Delay from digital 2.5 V and 3.3 V off to NVCC_DRAM off

Delay from NVCC_DRAM off to digital 1.8 V off

Delay from digital 1.8 V off to analog 1.8 V off

0

10

—

ms

T3

T4

T5

Delay from analog 1.8 V off to VDD_ARM off

T6

Delay from VDD_ARM off to PHY 0.9 V off

T7

Delay from PHY 0.9 V off to analog 0.8/0.9 V off

Delay from analog 0.8/0.9 V off to analog 0.8 V off

Delay from analog 0.8 V off to 32k off

T8

T9

T10

T11

T12

Delay from 32k off to RTC_RESET_B assert

Delay from RTC_RESET_B assert to VDD_SNVS_0P8 off

Delay from VDD_SNVS_0P8 off to NVCC_SNVS_1P8 off

During power-down, make sure NVCC_xxx - PVCCx_1P8 < 2 V.

3.3

PLL electrical characteristics

Table 19 shows PLL electrical characteristics.

Table 19. PLL electrical parameters

PLL type

Parameter

Value

AUDIO_PLL1

Clock output range

Reference clock

Lock time

Maximum 650 MHz

24 MHz

375 s

AUDIO_PLL2

VIDEO_PLL1

SYS_PLL1

Clock output range

Reference clock

Lock time

Maximum 650 MHz

24 MHz

375 s

Clock output range

Reference clock

Lock time

Maximum 650 MHz

24 MHz

375 s

Clock output range

Reference clock

Lock time

800 MHz

24 MHz

25 s

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Value

Table 19. PLL electrical parameters (continued)

Parameter

PLL type

SYS_PLL2

Clock output range

Reference clock

Lock time

1 GHz

24 MHz

25 s

SYS_PLL3

ARM_PLL

DRAM_PLL

GPU_PLL

VPU_PLL

Clock output range

Reference clock

Lock time

600 MHz ~ 1 GHz

24 MHz

25 s

Clock output range

Reference clock

Lock time

800 MHz ~1.6 GHz

24 MHz

25 s

Clock output range

Reference clock

Lock time

Maximum 750 MHz

24 MHz

375 s

Clock output range

Reference clock

Lock time

Maximum 1 GHz

24 MHz

25 s

Clock output range

Reference clock

Lock time

400 MHz ~ 800 MHz

24 MHz

25 s

3.4

On-chip oscillators

OSC24M

3.4.1

A 24 MHz oscillator is used as the primary clock source for the PLLs to generate the clock for the CPU,

BUS, and high-speed interfaces. For fractional PLLs, the 24 MHz clock from the oscillator can be used as

the PLL reference clock directly.

1

Table 20. Crystal specifications

Parameter Description

Min

Typ

Max

Unit

Frequency

Cload

—

24

12

—

80

MHz

pF

Drive level

ESR

100

—

W



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1

Actual working drive level is depend on real design. Please contact crystal vendor for selecting drive level of crystal.

3.4.2

OSC32K

An external 32.768 kHz oscillator is necessary.

3.5

General purpose I/O (GPIO) DC parameters

Table 21 shows DC parameters for GPIO pads. The parameters in Table 21 are guaranteed per the

operating ranges in Table 10, unless otherwise noted.

Table 21. GPIO DC parameters

Parameter

Symbol

Test Conditions

Min

Typ

Max

Unit

High-level output voltage V_{OH (1.8 V)}

V_{OH (3.3 V)}

I_OH= 1.6/3.2/6.4/9.6 mA (1.8 V)

I_OH= 2/4/8/12 mA (3.3 V)

0.8 x V_DD

—

22

23

24

33

—

V_DD

V

0.8 x V_DD

V_DD

Low-level output voltage

V_{OL (1.8 V)}

I_OL= 1.6/3.2/6.4/9.6 mA (1.8 V)

I_OL= 2/4/8/12 mA (3.3 V)

0

0.2 x V_DD

V

V_{OL (3.3 V)}

0.2 x V_DD

V

High-level input voltage

Low-level input voltage

Pull-up resistor

V_IH

V_IL

—

0.7 x V_DD

-0.3

12

V_DD+ 0.3

V

0.3 x V_DD

V

V_DD= 1.65 - 1.95V

Temp = 0 - 95 ^oC

49

48

69

—

4

K

A

Pull-down resistor

Pull-up resistor

—

13

—

V_DD= 2.25 - 2.75V

Temp = 0 - 95 ^oC

13

Pull-down resistor

Pull-up resistor¹

—

9.1

—

V_DD= 3.0 - 3.6V

Temp = 0 - 95 ^oC

Pull-down resistor¹

High level input current

Low level input current

—

IIH

IIL

—

-4

-0.7

0.7

1

Does not support internal pull-up or pull-down for 3.3 V IOs.

Table 22. Additional leakage parameters

Parameter

Symbol

Pins

Min

Max

Unit

PCIE_RXN, USBx_Dx

PCIE_CLK

-30

-8

30

8

High level input current

IIH

A

MIPI_CSI

-4

4

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Table 22. Additional leakage parameters (continued)

Parameter

Symbol

Pins

Min

Max

Unit

JTAG_TRST_B, USBx_ID

PCIE_CLK, USBx_Dx

PCIE_RXN

-200

-6

200

6

Low level input current

IIL

A

-2.5

-0.7

2.5

0.7

MIPI_CSI, ONOFF, POR_B

3.5.1

DDR I/O DC electrical characteristics

The DDR I/O pads support LPDDR 4, DDR4, and DDR3L operational modes. The DDR Memory

Controller (DDRMC) is designed to be compatible with JEDEC-compliant SDRAMs.

DDRMC operation is contingent upon the board’s DDR design adherence to the DDR design and layout

requirements stated in the hardware development guide for the i.MX 8M Mini applications processor.

3.6

I/O AC parameters

This section includes the AC parameters of the following I/O types:

General Purpose I/O (GPIO)

The GPIO load circuit and output transition time waveforms are shown in Figure 5 and Figure 6.

•

From Output

Under Test

Test Point

CL

CL includes package, probe and fixture capacitance

Figure 5. Load circuit for output

OVDD

0 V

80%

20%

80%

20%

tr

Output (at pad)

tf

Figure 6. Output transition time waveform

3.6.1

General purpose I/O AC parameters

This section presents the I/O AC parameters for GPIO in different modes.

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Table 23. Maximum frequency of operation for input

Maximum frequency (MHz)

VDD = 1.8 V, CL = 50 pF

VDD = 3.3 V, CL = 50 pF

450

440

Table 24. Maximum frequency of operation for output

Maximum Frequency (MHz)

Parameter

VDD = 1.8 V

VDD = 3.3 V

dse[2:0]

sre[1:0]

Driver type

CL = 10 pF

CL = 20 pF

CL = 10 pF

CL = 20 pF

00X

10X

01X

11X

0X

1X

0X

1X

0X

1X

0X

1X

1x Slow Slew

1x Fast Slew

2x Slow Slew

2x Fast Slew

4x Slow Slew

4x Fast Slew

6x Slow Slew

6x Fast Slew

150

160

200

250

80

120

150

180

200

65

90

80

90

80

100

130

90

100

3.7

Output buffer impedance parameters

This section defines the I/O impedance parameters of the i.MX 8M Mini family of processors for the

following I/O types:

NOTE

DDR I/O output driver impedance is measured with “long” transmission

line of impedance Ztl attached to I/O pad and incident wave launched into

transmission line. Rpu/Rpd and Ztl form a voltage divider that defines

specific voltage of incident wave relative to OVDD. Output driver

impedance is calculated from this voltage divider (see Figure 7).

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OVDD

PMOS (Rpu)

Ztl W, L = 20 inches

ipp_do

pad

predriver

Cload = 1p

NMOS (Rpd)

OVSS

U,(V)

VDD

(do)

Vin

t,(ns)

0

U,(V)

Vout (pad)

OVDD

Vref2

Vref1

Vref

t,(ns)

0

Vovdd - Vref1

Vref1

Rpu =

Rpd =

x Ztl

Vref2

Vovdd - Vref2

Figure 7. Impedance matching load for measurement

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3.7.1

DDR I/O output buffer impedance

Table 25 shows DDR I/O output buffer impedance of i.MX 8M Mini family of processors.

Table 25. DDR I/O output buffer impedance

Typical

Test Conditions DSE

Parameter

Symbol

Unit

(Drive Strength)

NVCC_DRAM=1.35 NVCC_DRAM = 1.2 NVCC_DRAM = 1.1

V (DDR3L)

V (DDR4)

V (LPDDR4)

Output Driver

Impedance

Rdrv

000000

Hi-Z

240

120

80

Hi-Z

240

120

80

Hi-Z

240

120

80

000010

001000

001010

011000

011010

111000

111010



60

48

40

34

Note:

1. Output driver impedance is controlled across PVTs using ZQ calibration procedure.

2. Calibration is done against 240  external reference resistor.

3. Output driver impedance deviation (calibration accuracy) is 5% (max/min impedance) across PVTs.

3.8

System modules timing

This section contains the timing and electrical parameters for the modules in each i.MX 8M Mini

processor.

3.8.1

Reset timings parameters

Figure 8 shows the reset timing and Table 26 lists the timing parameters.

POR_B

(Input)

CC1

Figure 8. Reset timing diagram

Table 26. Reset timing parameters

ID

Parameter

Min Max

Unit

RTC_XTALI cycle

CC1

Duration of POR_B to be qualified as valid.

1

—

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3.8.2

WDOG Reset timing parameters

Figure 9 shows the WDOG reset timing and Table 27 lists the timing parameters.

WDOGx_B

(Output)

CC3

Figure 9. WDOGx_B timing diagram

Table 27. WDOGx_B timing parameters

ID

Parameter

Duration of WDOGx_B Assertion

Min

Max

Unit

CC3

1

—

RTC_XTALI cycle

NOTE

RTC_XTALI is approximately 32 kHz. RTC_XTALI cycle is one period or

approximately 30 s.

NOTE

WDOGx_B output signals (for each one of the Watchdog modules) do not

have dedicated pins, but are muxed out through the IOMUX. See the

IOMUXC chapter of the i.MX 8M Mini Applications Processor Reference

Manual (IMX8MMRM) for detailed information.

3.9

External peripheral interface parameters

The following subsections provide information on external peripheral interfaces.

3.9.1

ECSPI timing parameters

This section describes the timing parameters of the ECSPI blocks. The ECSPI have separate timing

parameters for master and slave modes.

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3.9.1.1

ECSPI Master mode timing

Figure 10 depicts the timing of ECSPI in master mode. Table 28 lists the ECSPI master mode timing

characteristics.

ECSPIx_RDY_B

ECSPIx_SS_B

CS10

CS5

CS2

CS6

CS3

CS1

CS4

ECSPIx_SCLK

ECSPIx_MOSI

ECSPIx_MISO

CS2

CS3

CS7

CS9

CS8

Figure 10. ECSPI Master mode timing diagram

Table 28. ECSPI Master mode timing parameters

ID

Parameter

Symbol

Min

Max Unit

CS1 ECSPIx_SCLK Cycle Time–Read

ECSPIx_SCLK Cycle Time–Write

t_clk

43

15

—

ns

CS2 ECSPIx_SCLK High or Low Time–Read

ECSPIx_SCLK High or Low Time–Write

t_SW

21.5

7

CS3 ECSPIx_SCLK Rise or Fall¹

t_RISE/FALL

t_CSLH

t_SCS

—

1

ns

CS4 ECSPIx_SS_B pulse width

Half ECSPIx_SCLK period

CS5 ECSPIx_SS_B Lead Time (CS setup time)

CS6 ECSPIx_SS_B Lag Time (CS hold time)

CS7 ECSPIx_MOSI Propagation Delay (C_LOAD= 20 pF)

CS8 ECSPIx_MISO Setup Time

Half ECSPIx_SCLK period - 4

t_HCS

Half ECSPIx_SCLK period - 2

t_PDmosi

t_Smiso

t_Hmiso

t_SDRY

-1

18

0

—

CS9 ECSPIx_MISO Hold Time

CS10 RDY to ECSPIx_SS_B Time²

5

1

2

See specific I/O AC parameters Section 3.6, I/O AC parameters.”

SPI_RDY is sampled internally by ipg_clk and is asynchronous to all other CSPI signals.

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3.9.1.2

ECSPI Slave mode timing

Figure 11 depicts the timing of ECSPI in Slave mode. Table 29 lists the ECSPI Slave mode timing

characteristics.

ECSPIx_SS_B

CS5

CS6

CS2

CS1

CS4

ECSPIx_SCLK

ECSPIx_MISO

CS2

CS9

CS8

CS7

ECSPIx_MOSI

Figure 11. ECSPI Slave mode timing diagram

Table 29. ECSPI Slave mode timing parameters

ID

Parameter

Symbol

Min

Max Unit

CS1 ECSPIx_SCLK Cycle Time–Read

ECSPI_SCLK Cycle Time–Write

t_clk

15

43

—

ns

CS2 ECSPIx_SCLK High or Low Time–Read

ECSPIx_SCLK High or Low Time–Write

t_SW

7

21.5

CS4 ECSPIx_SS_B pulse width

t_CSLH

t_SCS

Half ECSPIx_SCLK period

—

19

ns

CS5 ECSPIx_SS_B Lead Time (CS setup time)

CS6 ECSPIx_SS_B Lag Time (CS hold time)

CS7 ECSPIx_MOSI Setup Time

5

4

t_HCS

t_Smosi

t_Hmosi

t_PDmiso

CS8 ECSPIx_MOSI Hold Time

CS9 ECSPIx_MISO Propagation Delay (C_LOAD= 20 pF)

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3.9.2

Ultra-high-speed SD/SDIO/MMC host interface (uSDHC) AC

timing

This section describes the electrical information of the uSDHC, which includes SD/eMMC 5.1 (single data

rate) timing, eMMC 5.1/SD3.0 (dual data rate) AC timing, and SDR50/SDR104 AC timing.

3.9.2.1

SD3.0/eMMC 5.1 (single data rate) AC timing

Figure 12 depicts the timing of SD3.0/eMMC5.1 (SDR), and Table 30 lists the SD3.0/eMMC5.1 (SDR)

timing characteristics.

SD4

SD2

SD1

SD5

SDx_CLK

SD3

SD6

Output from uSDHC to card

SDx_DATA[7:0]

SD7

SD8

Input from card to uSDHC

SDx_DATA[7:0]

Figure 12. SD3.0/eMMC5.1 (SDR) timing

Table 30. SD3.0/eMMC5.1 (SDR) interface timing specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

1

SD1 Clock Frequency (Low Speed)

f_PP

0

400

25/50

20/52

400

—

kHz

MHz

kHz

ns

2

Clock Frequency (SD/SDIO Full Speed/High Speed)

Clock Frequency (MMC Full Speed/High Speed)

Clock Frequency (Identification Mode)

f_PP

3

f_PP

0

f_OD

t_WL

100

7

SD2 Clock Low Time

SD3 Clock High Time

SD4 Clock Rise Time

SD5 Clock Fall Time

t_WH

t_TLH

t_THL

7

—

ns

—

3

ns

3

ns

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

SD6 uSDHC Output Delay t_OD6.6

3.6

ns

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Table 30. SD3.0/eMMC5.1 (SDR) interface timing specification (continued)

ID

Parameter

Symbols

Min

Max

Unit

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

SD7 uSDHC Input Setup Time

SD8 uSDHC Input Hold Time⁴

t_ISU

t_IH

2.5

1.5

—

ns

1

2

In Low-Speed mode, card clock must be lower than 400 kHz, voltage ranges from 2.7 to 3.6 V.

In Normal (Full) -Speed mode for SD/SDIO card, clock frequency can be any value between 0–25 MHz. In High-speed mode,

clock frequency can be any value between 0–50 MHz.

3

4

In Normal (Full) -Speed mode for MMC card, clock frequency can be any value between 0–20 MHz. In High-speed mode,

clock frequency can be any value between 0–52 MHz.

To satisfy hold timing, the delay difference between clock input and cmd/data input must not exceed 2 ns.

3.9.2.2

eMMC 5.1/SD3.0 (dual data rate) AC timing

Figure 13 depicts the timing of eMMC 5.1/SD3.0 (DDR). Table 31 lists the eMMC 5.1/SD3.0 (DDR)

timing characteristics. Be aware that only DATA is sampled on both edges of the clock (not applicable to

CMD).

SD1

SDx_CLK

SD2

Output from eSDHCv3 to card

SDx_DATA[7:0]

......

SD3

SD4

Input from card to eSDHCv3

SDx_DATA[7:0]

Figure 13. eMMC5.1/SD3.0 (DDR) timing

Table 31. eMMC5.1/SD3.0 (DDR) interface timing specification

ID

Parameter

Symbols

Card Input Clock

Min

Max

Unit

SD1

Clock Frequency (eMMC5.1 DDR)

Clock Frequency (SD3.0 DDR)

f_PP

0

52

50

MHz

uSDHC Output / Card Inputs SD_CMD, SDx_DATAx (Reference to CLK)

uSDHC Output Delay t_OD2.7

uSDHC Input / Card Outputs SD_CMD, SDx_DATAx (Reference to CLK)

SD2

6.9

ns

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Table 31. eMMC5.1/SD3.0 (DDR) interface timing specification (continued)

ID

Parameter

uSDHC Input Setup Time

Symbols

Min

Max

Unit

SD3

SD4

t_ISU

t_IH

2.4

1.3

—

ns

uSDHC Input Hold Time

3.9.2.3

HS400 DDR AC timing

Figure 14 depicts the timing of HS400 mode, and Table 32 lists the HS400 timing characteristics. Be

aware that only data is sampled on both edges of the clock (not applicable to CMD). The CMD

input/output timing for HS400 mode is the same as CMD input/output timing for SDR104 mode. Check

SD5, SD6, and SD7 parameters in Table 34 SDR50/SDR104 Interface Timing Specification for CMD

input/output timing for HS400 mode.

SD1

SD3

SD2

SCK

SD4

SD5

SD4

DAT0

Output from

uSDHC to eMMC

DAT1

...

DAT7

Strobe

DAT0

SD6

SD7

Input from

eMMC to uSDHC

DAT1

...

DAT7

Figure 14. HS400 timing

Table 32. HS400 interface timing specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1

SD2

SD3

Clock frequency

Clock low time

Clock high time

f_PP

t_CL

t_CH

0

200

MHz

ns

0.46 x t_CLK

0.54 x t_CLK

ns

uSDHC Output/Card Inputs DAT (Reference to SCK)

Output skew from data of edge of SCK

Output skew from edge of SCk to data

t_OSkew1

t_OSkew2

0.45

—

ns

SD4

SD5

uSDHC Input/Card Outputs DAT (Reference to Strobe)

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Table 32. HS400 interface timing specification (continued)

ID

Parameter

uSDHC input skew

Symbols

Min

Max

Unit

t_RQ

—

0.45

ns

SD6

SD7

uSDHC hold skew

t_RQH

—

0.45

ns

3.9.2.4

HS200 Mode AC timing

Figure 15 depicts the timing of HS200 mode, and Table 33 lists the HS200 timing characteristics.

SD1

SD2

SD3

SCK

SD4/SD5

8-bit output from uSDHC to eMMC

8-bit input from eMMC to uSDHC

SD8

Figure 15. HS200 timing

iti

Table 33. HS200 interface timing specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1 Clock Frequency Period

SD2 Clock Low Time

t_CLK

t_CL

5.0

—

ns

0.3 x t_CLK0.7 x t_CLK

SD3 Clock High Time

t_CH

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)

SD5 uSDHC Output Delay

t_OD

-1.6

1

ns

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in HS200 (Reference to CLK)¹

SD8 uSDHC Output Data Window

t_ODW

0.5 x t_CLK

—

1

HS200 is for 8 bits while SDR104 is for 4 bits.

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3.9.2.5

SDR50/SDR104 AC timing

Figure 16 depicts the timing of SDR50/SDR104, and Table 34 lists the SDR50/SDR104 timing

characteristics.

SD1

SD2

SD3

SCK

SD4/SD5

8-bit output from uSDHC to eMMC

8-bit input from eMMC to uSDHC

SD6

SD7

SD8

Figure 16. SDR50/SDR104 timing

Table 34. SDR50/SDR104 interface timing specification

ID

Parameter

Symbols

Min

Max

Unit

Card Input Clock

SD1 Clock Frequency Period

SD2 Clock Low Time

t_CLK

t_CL

5

—

ns

0.46 x t_CLK0.54 x t_CLK

SD3 Clock High Time

t_CH

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

SD4 uSDHC Output Delay t_OD-3

uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)

SD5 uSDHC Output Delay t_OD-1.6

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)

1

ns

SD6 uSDHC Input Setup Time

SD7 uSDHC Input Hold Time

t_ISU

t_IH

2.4

1.4

—

ns

uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)¹

SD8 uSDHC Output Data Window

t_ODW

0.5 x t_CLK

—

ns

1

Data window in SDR100 mode is variable.

3.9.2.6

Bus operation condition for 3.3 V and 1.8 V signaling

Signaling level of SD/eMMC4.5/5.0/5.1 can be 1.8 V or 3.3 V depending on the working mode. The DC

parameters for the NVCC_SD1, NVCC_SD2 and NVCC_SD3 supplies are identical to those shown in

Table 21, "GPIO DC parameters," on page 28.

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3.9.3

Ethernet controller (ENET) AC electrical specifications

The following timing specs are defined at the chip I/O pin and must be translated appropriately to arrive

at timing specs/constraints for the physical interface.

Table 35. ENET signal mapping

Pad name

Description

Mode

Alt mode

Direction

Comments

ENET_MDC

ENET_MDIO

ENET_TD3

ENET_TD2

enet1.MDC

enet1.MDIO

RGMII.TD3

RMII/RGMII

RGMII

ALT0

O

I/O

O

—

Only used for RGMII

RMII.CLK;

RGMII.TD2

RMII/RGMII

I/O

Used as RMII clock and RGMII data, there

are two RGMII clock schemes.

• MAC generate output 50M reference clock

for PHY, and MAC also use this 50M clock.

• MAC use external 50M clock.

ENET_TD1

ENET_TD0

RMII and

RGMII.TD1

RMII/RGMII

RGMII

ALT0

O

—

RMII and

RGMII.TD0

ENET_TX_CTL

ENET_TXC

RMII.TX_EN;

RGMII.TX_CTL

ALT0

RMII.TX_ERR;

RGMII. TX_CLK

ALT0/ALT1

For RMII—ENET_TXC works as

RMII.TX_ERR need to work in the ALT1

mode.

For RGMII—ENET_TXC works as

RGMII.TX_CLK need to work in the ALT0

mode.

ENET_RX_CTL

ENET_RXC

RMII.RX_EN

(CRS_DV);

RGMII.RC_CTL

RMII/RGMII

RGMII

ALT0

I

—

RMII.RX_ERR;

RGMII.RX_CLK

ALT0/ALT1

For RMII—ENET_RXC works as

RMII.RX_ERR need to work in the ALT1

mode.

For RGMII—ENET_RXC works as

RGMII.RX_CLK need to work in the ALT0

mode.

ENET_RD0

ENET_RD1

RMII and

RGMII.RD0

RMII/RGMII

ALT0

I

—

RMII and

—

RGMII.RD1

ENET_RD2

ENET_RD3

GPIO1_IO06

GPIO1_IO07

I2C1_SCL

RGMII.RD2

RGMII.RD3

enet1.MDC

enet1.MDIO

enet1.MDC

RGMII

ALT0

ALT1

I

—

RGMII

RMII/RGMII

O

I/O

O

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

41

Electrical characteristics

Table 35. ENET signal mapping (continued)

Pad name

Description

Mode

Alt mode

Direction

Comments

I2C1_SDA

I2C2_SCL

enet1.MDIO

RMII/RGMII

ALT1

I/O

O

—

enet1.1588_EV

ENT1_IN

I2C2_SDA

GPIO1_IO00

GPIO1_IO08

enet1.1588_EV

ENT1_OUT

RMII/RGMII

RGMII

ALT1

I/O

O

I

—

ENET_PHY_RE

F_CLK_ROOT

Reference clock for PHY.

enet1.1588_EV

ENT0_IN

RMII/RGMII

Capture/compare block input/output event

bus signal. When configured for capture and

a rising edge is detected, the current timer

value is latched and transferred into the

corresponding ENET_TCCRn register for

inspection by software. When configured for

compare, the corresponding signal

1588_EVENT is asserted for one cycle when

the timer reaches the compare value

programmed in register ENET_TCCRn. An

interrupt or DMA request can be triggered if

the corresponding bit in ENET_TCSRn[TIE]

or ENET_TSCRn[TDRE] is set.

GPIO1_IO09

enet1.1588_EV

ENT0_OUT

RMII/RGMII

ALT1

O

—

3.9.3.1

RMII mode timing

Figure 17 shows RMII mode timings. Table 36 describes the timing parameters (M16–M21) shown in the

figure.

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

42

NXP Semiconductors

Electrical characteristics

M16

M17

ENET_CLK (input)

M18

ENET_TX_DATA (output)

ENET_TX_EN

M19

ENET_RX_EN (input)

ENET_RX_DATA[1:0]

ENET_RX_ER

M20

M21

Figure 17. RMII mode signal timing diagram

Table 36. RMII signal timing

ID

Characteristic

Min.

Max.

Unit

M16

M17

M18

M19

M20

ENET_CLK pulse width high

ENET_CLK pulse width low

35%

4

65%

—

ENET_CLK period

ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA invalid

ENET_CLK to ENET0_TXD[1:0], ENET_TX_DATA valid

ns

—

15

ENET_RX_DATAD[1:0], ENET_RX_EN(ENET_RX_EN), ENET_RX_ER to

ENET_CLK setup

4

—

M21

ENET_CLK to ENET_RX_DATAD[1:0], ENET_RX_EN, ENET_RX_ER hold

2

—

ns

3.9.3.2

RGMII signal switching specifications

The following timing specifications meet the requirements for RGMII interfaces for a range of transceiver

devices.

1

Table 37. RGMII signal switching specifications

Symbol

Description

Min.

Max.

Unit

2

T_cyc

Clock cycle duration

7.2

-500

1

8.8

500

2.6

55

ns

ps

ns

%

3

T_skewT

Data to clock output skew at transmitter

Data to clock input skew at receiver

Duty cycle for Gigabit

3

T_skewR

Duty_G⁴

Duty_T⁴

Tr/Tf

45

Duty cycle for 10/100T

40

60

%

Rise/fall time (20–80%)

—

0.75

ns

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

43

Electrical characteristics

1

The timings assume the following configuration:

DDR_SEL = (11)b

DSE (drive-strength) = (111)b

2

For 10 Mbps and 100 Mbps, T_cycwill scale to 400 ns 40 ns and 40 ns 4 ns respectively.

3

For all versions of RGMII prior to 2.0; this implies that PC board design will require clocks to be routed such that an additional

trace delay of greater than 1.5 ns and less than 2.0 ns will be added to the associated clock signal. For 10/100, the Max value

is unspecified.

4

Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long

as minimum duty cycle is not violated and stretching occurs for no more than three Tcyc of the lowest speed transitioned

between.

2'-))?48# ꢀAT TRANSMITTERꢁ

4SKEW4

2'-))?48$N ꢀN ꢂ ꢃ TO ꢄ ꢁ

2'-))?48?#4,

48%.

48%22

4SKEW2

2'-))?48# ꢀAT RECEIVERꢁ

Figure 18. RGMII transmit signal timing diagram original

2'-))?28# ꢀAT TRANSMITTERꢁ

4SKEW4

2'-))?28$N ꢀN ꢂ ꢃ TO ꢄ ꢁ

2'-))?28?#4,

28$6

28%22

4SKEW2

2'-))?28# ꢀAT RECEIVERꢁ

Figure 19. RGMII receive signal timing diagram original

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

44

NXP Semiconductors

Electrical characteristics

)NTERNAL DELAY

2'-))?28# ꢀSOURCE OF DATAꢁ

2'-))?28$N ꢀN ꢂ ꢃ TO ꢄ ꢁ

4SETUP 4

4 HOLD 4

28$6

28%22

2'-))?28?#4,

4 SETUP 2

4 HOLD 2

2'-))?28# ꢀAT RECEIVERꢁ

Figure 20. RGMII receive signal timing diagram with internal delay

3.9.4

General-purpose media interface (GPMI) timing

The i.MX 8M Mini GPMI controller is a flexible interface NAND Flash controller with 8-bit data width,

up to 200 MB/s I/O speed and individual chip select.

It supports Asynchronous Timing mode, Source Synchronous Timing mode and Toggle Timing mode

separately, as described in the following subsections.

3.9.4.1

Asynchronous mode AC timing (ONFI 1.0 compatible)

Asynchronous mode AC timings are provided as multiplications of the clock cycle and fixed delay. The

maximum I/O speed of GPMI in Asynchronous mode is about 50 MB/s. Figure 21 through Figure 24

depicts the relative timing between GPMI signals at the module level for different operations under

Asynchronous mode. Table 38 describes the timing parameters (NF1–NF17) that are shown in the figures.

NF2

NF1

.!.$?#,%

NF3

NF4

.!.$?#%ꢃ?"

.!.$?7%?"

NF5

.!.$?!,%

NF6

NF8

Command

NF7

NF9

.!.$?$!4!XX

Figure 21. Command Latch cycle timing diagram

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

45

Electrical characteristics

NF1

.!.$?#,%

.!.$?#%ꢃ?"

.!.$?7%?"

NF3

NF10

NF5

NF11

NF7

.!.$?!,%

NF6

NF8

Address

NF9

NAND_DATAxx

Figure 22. Address Latch cycle timing diagram

NF1

.!.$?#,%

.!.$?#%ꢃ?"

.!.$?7%?"

NF3

NF10

NF5

NF11

NF7

NF6

NF8

Data to NF

.!.$?!,%

NF9

.!.$?$!4!XX

Figure 23. Write Data Latch cycle timing diagram

.!.$?#,%

.!.$?#%ꢃ?"

.!.$?2%?"

NF14

NF13

NF15

.!.$?2%!$9?"

NF12

NF16

NF17

Data from NF

.!.$?$!4!XX

Figure 24. Read Data Latch cycle timing diagram (Non-EDO Mode)

.!.$?#,%

.!.$?#%ꢃ?"

NF14

NF13

NF15

.!.$?2%?"

.!.$?2%!$9?"

NF12

NF17

NF16

NAND_DATAxx

Data from NF

Figure 25. Read Data Latch cycle timing diagram (EDO mode)

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

46

NXP Semiconductors

Electrical characteristics

1

Table 38. Asynchronous mode timing parameters

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min.

Max.

NF1

NF2

NF3

NF4

NF5

NF6

NF7

NF8

NF9

NAND_CLE setup time

NAND_CLE hold time

NAND_CE0_B setup time

NAND_CE0_B hold time

NAND_WE_B pulse width

NAND_ALE setup time

NAND_ALE hold time

Data setup time

tCLS

tCLH

tCS

(AS + DS)  T - 0.12 [see notes^2,3

DH  T - 0.72 [see note²]

]

ns

(AS + DS + 1)  T [see notes^3,2

(DH+1)  T - 1 [see note²]

DS  T [see note²]

]

tCH

tWP

tALS

tALH

tDS

(AS + DS)  T - 0.49 [see notes^3,2

DH  T - 0.42 [see note²]

DS  T - 0.26 [see note²]

DH  T - 1.37 [see note²]

(DS + DH)  T [see note²]

DH  T [see note²]

]

Data hold time

tDH

NF10 Write cycle time

tWC

tWH

tRR⁴

tRP

NF11 NAND_WE_B hold time

NF12 Ready to NAND_RE_B low

NF13 NAND_RE_B pulse width

NF14 READ cycle time

(AS + 2)  T [see ^3,2

]

—

DS  T [see note²]

(DS + DH)  T [see note²]

DH  T [see note²]

tRC

NF15 NAND_RE_B high hold time

NF16 Data setup on read

tREH

tDSR

—

(DS  T -0.67)/18.38 [see

notes^5,6

—

]

NF17 Data hold on read

tDHR

0.82/11.83 [see notes^5,6

]

ns

1

GPMI’s Asynchronous mode output timing can be controlled by the module’s internal registers

HW_GPMI_TIMING0_ADDRESS_SETUP, HW_GPMI_TIMING0_DATA_SETUP, and HW_GPMI_TIMING0_DATA_HOLD.

This AC timing depends on these registers settings. In the table, AS/DS/DH represents each of these settings.

2

3

4

5

6

AS minimum value can be 0, while DS/DH minimum value is 1.

T = GPMI clock period -0.075 ns (half of maximum p-p jitter).

NF12 is guaranteed by the design.

Non-EDO mode.

EDO mode, GPMI clock  100 MHz

(AS=DS=DH=1, GPMI_CTL1 [RDN_DELAY] = 8, GPMI_CTL1 [HALF_PERIOD] = 0).

In EDO mode (Figure 24), NF16/NF17 are different from the definition in non-EDO mode (Figure 23).

They are called tREA/tRHOH (RE# access time/RE# HIGH to output hold). The typical values for them

are 16 ns (max for tREA)/15 ns (min for tRHOH) at 50 MB/s EDO mode. In EDO mode, GPMI samples

NAND_DATAxx at the rising edge of delayed NAND_RE_B provided by an internal DPLL. The delay

value can be controlled by GPMI_CTRL1.RDN_DELAY (see the GPMI chapter of the i.MX 8M Mini

Applications Processor Reference Manual [IMX8MMRM]). The typical value of this control register is

0x8 at 50 MT/s EDO mode. But if the board delay is big enough and cannot be ignored, the delay value

should be made larger to compensate the board delay.

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

47

Electrical characteristics

3.9.4.2

Source synchronous mode AC timing (ONFI 2.x compatible)

Figure 26 to Figure 28 show the write and read timing of Source Synchronous mode.

NF19

NF18

.!.$?#%?"

NF23

NAND_CLE

NF26

NF25

NF24

NAND_ALE

NF25 NF26

NAND_WE/RE_B

NF22

NAND_CLK

NAND_DQS

Output enable

NF20

NF21

CMD

ADD

NAND_DATA[7:0]

Output enable

Figure 26. Source Synchronous mode command and address timing diagram

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

48

Electrical characteristics

NF19

NF18

.!.$?#%ꢃ?"

.!.$?#,%

NF23

NF24

NF25

NF26

.!.$?!,%

NAND_WE/RE_B

NF22

.!.$?#,+

.!.$?$13

NF27

.!.$?$13

Output enable

NF29

.!.$?$1;ꢅꢆꢃ=

NF28

.!.$?$1;ꢅꢆꢃ=

Output enable

Figure 27. Source Synchronous mode data write timing diagram

NF18

NF19

.!.$?#%?"

.!.$?#,%

NF24

NF23

NF26

NF25

NAND_ALE

NF25

.!.$?7%ꢇ2%

NF25

NF22

NF26

.!.$?#,+

.!.$?$13

/UTPUT ENABLE

.!.$?$!4!;ꢅꢆꢃ=

/UTPUT ENABLE

Figure 28. Source Synchronous mode data read timing diagram

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

49

Electrical characteristics

.!.$?$13

NF30

.!.$?$!4!;ꢅꢆꢃ=

D0

D1

D2

D3

NF30

NF31

Figure 29. NAND_DQS/NAND_DQ read valid window

1

Table 39. Source Synchronous mode timing parameters

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min.

Max.

NF18 NAND_CE0_B access time

NF19 NAND_CE0_B hold time

tCE

tCH

CE_DELAY  T - 0.79 [see note²]

0.5  tCK - 0.63 [see note²]

0.5  tCK - 0.05

ns

NF20 Command/address NAND_DATAxx setup time

NF21 Command/address NAND_DATAxx hold time

NF22 clock period

tCAS

tCAH

tCK

0.5  tCK - 1.23

—

NF23 preamble delay

tPRE

tPOST

tCALS

tCALH

tDQSS

—

PRE_DELAY  T - 0.29 [see note²]

POST_DELAY  T - 0.78 [see note²]

0.5  tCK - 0.86

NF24 postamble delay

NF25 NAND_CLE and NAND_ALE setup time

NF26 NAND_CLE and NAND_ALE hold time

NF27 NAND_CLK to first NAND_DQS latching transition

NF28 Data write setup

0.5  tCK - 0.37

T - 0.41 [see note²]

0.25  tCK - 0.35

NF29 Data write hold

—

0.25  tCK - 0.85

NF30 NAND_DQS/NAND_DQ read setup skew

NF31 NAND_DQS/NAND_DQ read hold skew

—

2.06

1.95

—

1

GPMI’s Source Synchronous mode output timing can be controlled by the module’s internal registers

GPMI_TIMING2_CE_DELAY,GPMI_TIMING_PREAMBLE_DELAY,GPMI_TIMING2_POST_DELAY.ThisACtimingdepends

on these registers settings. In the table, CE_DELAY/PRE_DELAY/POST_DELAY represents each of these settings.

2

T = tCK(GPMI clock period) –0.075 ns (half of maximum p-p jitter).

For DDR Source Synchronous mode, Figure 29 shows the timing diagram of

NAND_DQS/NAND_DATAxx read valid window. The typical value of tDQSQ is 0.85 ns (max) and 1 ns

(max) for tQHS at 200 MB/s. GPMI will sample NAND_DATA[7:0] at both rising and falling edge of an

delayed NAND_DQS signal, which can be provided by an internal DPLL. The delay value can be

controlled by GPMI register GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI

chapter of the i.MX 8M Mini Applications Processor Reference Manual [IMX8MMRM]). Generally, the

typical delay value of this register is equal to 0x7 which means 1/4 clock cycle delay expected. But if the

board delay is big enough and cannot be ignored, the delay value should be made larger to compensate the

board delay.

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50

NXP Semiconductors

Electrical characteristics

3.9.4.3

ONFI NV-DDR2 mode (ONFI 3.2 compatible)

Command and address timing

3.9.4.3.1

ONFI 3.2 mode command and address timing is the same as ONFI 1.0 compatible Async mode AC timing.

See Section 3.9.4.1, Asynchronous mode AC timing (ONFI 1.0 compatible),” for details.

3.9.4.3.2

Read and write timing

ONFI 3.2 mode read and write timing is the same as Toggle mode AC timing. See Section 3.9.4.4, Toggle

mode AC Timing,” for details.

3.9.4.4

Toggle mode AC Timing

3.9.4.4.1

Command and address timing

NOTE

Toggle mode command and address timing is the same as ONFI 1.0

compatible Asynchronous mode AC timing. See Section 3.9.4.1,

Asynchronous mode AC timing (ONFI 1.0 compatible),” for details.

3.9.4.4.2

Read and write timing

Figure 30. Toggle mode data write timing

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

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51

Electrical characteristics

DEV?CLK

.!.$?#%X?"

.& ꢈꢉ

.!.$?#,%

.!.$?!,%

ꢈ T #+

ꢈ

.&ꢊꢋ

.!.$?7%?"

.!.$?2%?"

ꢈ T #+

.& ꢊꢄ

ꢈ T #+

.!.$?$13

.!.$?$!4!;ꢅꢆꢃ=

Figure 31. Toggle mode data read timing

Table 40. Toggle mode timing parameters

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min.

Max.

NF1 NAND_CLE setup time

NF2 NAND_CLE hold time

NF3 NAND_CE0_B setup time

NF4 NAND_CE0_B hold time

NF5 NAND_WE_B pulse width

NF6 NAND_ALE setup time

NF7 NAND_ALE hold time

tCLS

tCLH

tCS

(AS + DS)  T - 0.12 [see note¹s^,2]

DH  T - 0.72 [see note²]

(AS + DS)  T - 0.58 [see notes^,2]

DH  T - 1 [see note²]

tCH

tWP

tALS

tALH

DS  T [see note²]

(AS + DS)  T - 0.49 [see notes^,2]

DH  T - 0.42 [see note²]

DS  T - 0.26 [see note²]

DH  T - 1.37 [see note²]

NF8 Command/address NAND_DATAxx setup time tCAS

NF9 Command/address NAND_DATAxx hold time

NF18 NAND_CEx_B access time

NF22 clock period

tCAH

tCE

CE_DELAY  T [see notes^3,2

]

—

ns

tCK

—

NF23 preamble delay

tPRE PRE_DELAY  T [see notes^4,2

]

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

52

Electrical characteristics

Table 40. Toggle mode timing parameters (continued)

Timing

T = GPMI Clock Cycle

ID

Parameter

Symbol

Unit

Min.

Max.

NF24 postamble delay

tPOST POST_DELAY  T + 0.43 [see

—

ns

note²]

NF28 Data write setup

NF29 Data write hold

tDS⁵

tDH⁵

tDQSQ⁶

tQHS⁶

0.25  tCK - 0.32

—

ns

0.25  tCK - 0.79

NF30 NAND_DQS/NAND_DQ read setup skew

NF31 NAND_DQS/NAND_DQ read hold skew

—

3.18

3.27

1

2

3

AS minimum value can be 0, while DS/DH minimum value is 1.

T = tCK (GPMI clock period) -0.075 ns (half of maximum p-p jitter).

CE_DELAY represents HW_GPMI_TIMING2[CE_DELAY]. NF18 is guaranteed by the design. Read/Write operation is started

with enough time of ALE/CLE assertion to low level.

4

5

6

PRE_DELAY+1  (AS+DS)

Shown in Figure 30.

Shown in Figure 31.

For DDR Toggle mode, Figure 29 shows the timing diagram of NAND_DQS/NAND_DATAxx read valid

window. The typical value of tDQSQ is 1.4 ns (max) and 1.4 ns (max) for tQHS at 133 MB/s. GPMI

samples NAND_DATA[7:0] at both the rising and falling edges of a delayed NAND_DQS signal, which

is provided by an internal DPLL. The delay value of this register can be controlled by the GPMI register

GPMI_READ_DDR_DLL_CTRL.SLV_DLY_TARGET (see the GPMI chapter of the i.MX 8M Mini

Applications Processor Reference Manual [IMX8MMRM]). Generally, the typical delay value is equal to

0x7, which means a 1/4 clock cycle delay is expected. But if the board delay is big enough and cannot be

ignored, the delay value should be made larger to compensate the board delay.

3.9.5

I²C bus characteristics

The Inter-Integrated Circuit (I2C) provides functionality of a standard I2C master and slave. The I2C is

designed to be compatible with the I2C Bus Specification, version 2.1, by Philips Semiconductor (now

NXP Semiconductors).

3.9.6

MIPI D-PHY timing parameters

MIPI D-PHY electrical specifications are compliance.

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

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53

Electrical characteristics

1

Table 41. MIPI PHY worst power dissipation

Power consume on

VDD_MIPI_0P9 (mW) VDD_MIPI_1P2 (mW) VDD_MIPI_1P8 (mW)

Power consume on Power consume on

Total power

consume (mW)

MODE

M4 on

S4 on

226.1

164.7

63.02

4.26

4.1

4.03

0

35.6

28.6

265.8

197.33

78.82

4.36

M4 on

2.1 Gbps

S4 off

M4 off

S4 on

15.8

0.0367

0.0584

ULPS

1

M4 indicates MIPI DSI have 4 data lane enable (at least 1 clock lane enable). S4 indicates MIPI CSI have 4 data lane enable

(at least 1 clock lane enable).

3.9.7

PCIe PHY parameters

The PCIe interface is designed to be compatible with PCIe specification Gen2 x1 lane and supports the

PCI Express 1.1/2.0 standard.

Table 42. PCIe DC electrical characteristics

Parameter

Description

Min

Typ

Max

Unit

PD

Power Consumption

Normal Gen2

Partial Mode

—

129.5

98.2

4.9

—

mW

Slumber Mode

Full Powerdown

0.1

3.9.7.1

PCIE_RESREF reference resistor connection

The impedance calibration process requires connection of reference resistor 8.2 k 1% precision resistor

on PCIE_RESREF pads to ground. It is used for termination impedance calibration.

3.9.8

PDM timing parameters

Figure 32 illustrates the input timing of the PDM.

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

54

Electrical characteristics

PDM Clock

PDM Bitstream

ipg_clk_app

Pulse right

pre_channel_1

ipg_dee_clk

Channel 1

Channel 0

Figure 32. PDM input timing

PDM clock operative range is from 500 kHz to 6 MHz. Within range, only need to configure ipg_clk_app

rate and CLKDIV without I/O timing concerns.

3.9.9

Pulse width modulator (PWM) timing parameters

This section describes the electrical information of the PWM. The PWM can be programmed to select one

of three clock signals as its source frequency. The selected clock signal is passed through a prescaler before

being input to the counter. The output is available at the pulse-width modulator output (PWMO) external

pin.

Figure 33 depicts the timing of the PWM, and Table 43 lists the PWM timing parameters.

0ꢈ

0ꢊ

07-N?/54

Figure 33. PWM timing

Table 43. PWM output timing parameters

ID

Parameter

Min

Max

Unit

PWM Module Clock Frequency

PWM output pulse width high

PWM output pulse width low

0

66 (ipg_clk)

MHz

ns

P1

P2

12

—

ns

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3.9.10 FlexSPI timing parameters

Measurements are with a load of 15 pF and an input slew rate of 1 V/ns.

3.9.10.1 FlexSPI input/read timing

There are three sources for the internal sample clock for FlexSPI read data:

•

Dummy read strobe generated by FlexSPI controller and looped back internally

(FlexSPIn_MCR0[RXCLKSRC] = 0x0)

Dummy read strobe generated by FlexSPI controller and looped back through the DQS pad

(FlexSPIn_MCR0[RXCLKSRC] = 0x1)

Read strobe provided by memory device and input from DQS pad

(FlexSPIn_MCR0[RXCLKSRC] = 0x3)

The following sections describe input signal timing for each of these four internal sample clock sources.

3.9.10.1.1 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

Table 44. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0

Symbol

Parameter

Min.

Max.

Unit

Notes

—

[D:] Frequency of operation

—

8.67

0

66

—

MHz

ns

—

1

F1

F2

[D:] Setup time for incoming data

[D:] Hold time for incoming data

ns

—

1

The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be

decreased by up to 2ns.

Table 45. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1

Symbol

Parameter

Min.

Max.

Unit

Notes

—

[D:] Frequency of operation

—

1.5

1

133

—

MHz

ns

—

1

F1

F2

[D:] Setup time for incoming data

[D:] Hold time for incoming data

—

ns

—

1

The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be

decreased by up to 2ns.

FLEXSPI_SCLK

F1

F2

F1

F2

FLEXSPI_DATA[7:0]

Internal Sample Clock

Figure 34. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

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NOTE

Timing shown is based on the memory generating read data on the SCK

falling edge, and FlexSPI controller sampling read data on the falling edge.

3.9.10.1.2 SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3

There are two cases when the memory provides both read data and the read strobe in SDR mode:

•

A1—Memory generates both read data and read strobe on SCK rising edge (or falling edge)

A2—Memory generates read data on SCK falling edge and generates read strobe on SCK rising

edge

Table 46. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1)

Symbol

Parameter

Min.

Max.

Unit

—

F3

F4

—

[D:] Frequency of operation

[D:] Time from SCK to data valid

[D:] Time from SCK to DQS

—

-2

166

—

2

MHz

ns

[D:] Time delta between TSCKD and

TSCKDQS

ns

FLEXSPI_SCLK

F3

F4

F3

FLEXSPI_DATA[7:0]

FLEXSPI_DQS

F4

Figure 35. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A1)

NOTE

Timing shown is based on the memory generating read data and read strobe

on the SCK rising edge. The FlexSPI controller samples read data on the

DQS falling edge.

Table 47. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2)

Symbol

Parameter

Min.

Max.

Unit

—

F5

F6

—

[D:] Frequency of operation

[D:] Time from SCK to data valid

[D:] Time from SCK to DQS

—

-2

166

—

2

MHz

ns

[D:] Time delta between TSCKD and

TSCKDQS

ns

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FLEXSPI_SCLK

F5

FLEXSPI_DATA[7:0]

F6

FLEXSPI_DQS

Internal Sample Clock

Figure 36. FlexSPI input timing in SDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case A2)

NOTE

Timing shown is based on the memory generating read data on the SCK

falling edge and read strobe on the SCK rising edge. The FlexSPI controller

samples read data on a half-cycle delayed DQS falling edge.

3.9.10.1.3 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

Table 48. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0

Symbol

Parameter

Min.

Max.

Unit

Notes

—

[D:] Frequency of operation

—

8.67

0

33

—

MHz

ns

—

1

F1

F2

[D:] Setup time for incoming data

[D:] Hold time for incoming data

ns

—

1

The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be

decreased by up to 2ns.

Table 49. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x1

Symbol

Parameter

Min.

Max.

Unit

Notes

—

[D:] Frequency of operation

—

1.5

1

66

—

MHz

ns

—

1

F1

F2

[D:] Setup time for incoming data

[D:] Hold time for incoming data

ns

—

1

The setup specification here assumes the data learning feature is not used. If data learning is enabled, then TIS can be

decreased by up to 2ns.

SCLK

F1 F2

F1

F2

SIO[0:7]

Internal Sample Clocks

Figure 37. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

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3.9.10.1.4 DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x3

Table 50. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3 (Case 1)

Symbol

Parameter

Min.

Max.

Unit

—

[D:] Frequency of operation

[D:] Time from SCK to data valid

[D:] Time from SCK to DQS

—

166

—

MHz

ns

T_SCKD

T_SCKDQS

T_{SCKD -}T_SCKDQS

—

ns

[D:] Time delta between TSCKD and

TSCKDQS

-0.6

0.6

ns

SCK

TSCKD

SIO[0:7]

DQS

TSCKDQS

Figure 38. FlexSPI input timing in DDR mode where FlexSPIn_MCR0[RXCLKSRC] = 0x3

3.9.10.2 FlexSPI output/write timing

The following sections describe output signal timing for the FlexSPI controller including control signals

and data outputs.

3.9.10.2.1 SDR mode

Table 51. FlexSPI output timing in SDR mode

Symbol

Parameter

Min.

Max.

Unit

—

[D:] Frequency of operation¹

[D:] SCK clock period

—

166

—

MHz

ns

T_CK

6.02

T_DSO

T_DHO

T_CSS

T_CSH

[D:] Output data setup time

[D:] Output data hold time

[D:] Chip select output setup time

[D:] Chip select output hold time

2

—

ns

2

—

ns

3 x T_CK- 1

—

ns

—

ns

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1

The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. See the

FlexSPI SDR input timing specifications.

NOTE

T

and T

are configured by the FlexSPIn_FLSHAxCR1 register, the

CSS

CSH

default values are shown above. See the i.MX 8M Mini Applications

Processor Reference Manual (IMX8MMRM) for more details.

SCK

CS

TCK

TCSS

TCSH

TDVO

SIO[0:7]

TDHO

Figure 39. FlexSPI output timing in SDR mode

3.9.10.2.2 DDR mode

Table 52. FlexSPI output timing in DDR mode

Symbol

Parameter

Min.

Max.

Unit

—

[D:] Frequency of operation¹

[D:] SCK clock period

—

6.02

166

—

MHz

ns

T_CK

T_DSO

T_DHO

T_CSS

T_CSH

[D:] Output data setup time

[D:] Output data hold time

[D:] Chip select output setup time

[D:] Chip select output hold time

—

0.6

—

ns

0.6

ns

3 x T_CK- 1.075

—

ns

—

ns

1

The actual maximum frequency supported is limited by the FlexSPIn_MCR0[RXCLKSRC] configuration used. See the

FlexSPI SDR input timing specifications.

NOTE

T

and T

are configured by the FlexSPIn_FLSHAxCR1 register, the

CSS

CSH

default values are shown above. See the i.MX 8M Mini Applications

Processor Reference Manual (IMX8MMRM) for more details.

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SCK

CS

TCSS

TCK

TCSH

TDVO

SIO[0:7]

TDHO

Figure 40. FlexSPI output timing in DDR mode

3.9.11 SAI/I2S switching specifications

This section provides theAC timings for the SAI in Master (clocks driven) and Slave (clocks input) modes.

All timings are given for non inverted serial clock polarity (SAI_TCR[TSCKP] = 0, SAI_RCR[RSCKP]

= 0) and non inverted frame sync (SAI_TCR[TFSI] = 0, SAI_RCR[RFSI] = 0). If the polarity of the clock

and/or the frame sync have been inverted, all the timings remain valid by inverting the clock signal

(SAI_BCLK) and/or the frame sync (SAI_FS) shown in the figures below.

1

Table 53. Master mode SAI timing (50 MHz)

Num

Characteristic

SAI_MCLK cycle time

Min

Max

Unit

S1

S2

S3

S4

S5

S6

S7

S8

S9

S10

20

40%

20

40%

—

0

—

ns

SAI_MCLK pulse width high/low

SAI_BCLK cycle time

60%

—

MCLK period

ns

SAI_BCLK pulse width high/low

SAI_BCLK to SAI_FS output valid

SAI_BCLK to SAI_FS output invalid

SAI_BCLK to SAI_TXD valid

60%

2

BCLK period

ns

—

0

2

SAI_BCLK to SAI_TXD invalid

—

SAI_RXD/SAI_FS input setup before SAI_BCLK

SAI_RXD/SAI_FS input hold after SAI_BCLK

2

—

0

—

1

To achieve 50 MHz for BCLK operation, clock must be set in feedback mode.

Table 54. Master mode SAI timing (25 MHz)

Characteristic Min

SAI_MCLK cycle time

Num

Max

Unit

S1

40

—

ns

S2

S3

S4

S5

SAI_MCLK pulse width high/low

SAI_BCLK cycle time

40%

40

60%

—

MCLK period

ns

SAI_BCLK pulse width high/low

SAI_BCLK to SAI_FS output valid

40%

—

60%

2

BCLK period

ns

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Num

Table 54. Master mode SAI timing (25 MHz) (continued)

Characteristic Min

Max

Unit

S6

S7

S8

S9

S10

SAI_BCLK to SAI_FS output invalid

SAI_BCLK to SAI_TXD valid

0

—

2

ns

—

0

SAI_BCLK to SAI_TXD invalid

—

SAI_RXD/SAI_FS input setup before SAI_BCLK

SAI_RXD/SAI_FS input hold after SAI_BCLK

12

0

Figure 41. SAI timing—Master modes

1

Table 55. Slave mode SAI timing (50 MHz)

Num

Characteristic

SAI_BCLK cycle time (input)

Min

Max

Unit

S11

S12

S13

S14

S17

S18

20

40%

2

—

ns

SAI_BCLK pulse width high/low (input)

SAI_FS input setup before SAI_BCLK

SAI_FA input hold after SAI_BCLK

SAI_RXD setup before SAI_BCLK

SAI_RXD hold after SAI_BCLK

60%

—

BCLK period

ns

2

—

2

—

2

—

1

TX does not support 50 MHz operation in Slave mode.

Table 56. Slave mode SAI timing (25 MHz)

Characteristic Min

Num

Max

Unit

S11

SAI_BCLK cycle time (input)

SAI_BCLK pulse width high/low (input)

40

—

ns

S12

40%

60%

BCLK period

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Table 56. Slave mode SAI timing (25 MHz) (continued)

Num

Characteristic

Min

Max

Unit

S13

S14

S15

S16

S17

S18

SAI_FS input setup before SAI_BCLK

SAI_FA input hold after SAI_BCLK

SAI_BCLK to SAI_TXD/SAI_FS output valid

SAI_BCLK to SAI_TXD/SAI_FS output invalid

SAI_RXD setup before SAI_BCLK

12

2

—

7

ns

—

0

—

12

2

SAI_RXD hold after SAI_BCLK

Figure 42. SAI Timing — Slave Modes

3.9.12 SPDIF timing parameters

The Sony/Philips Digital Interconnect Format (SPDIF) data is sent using the bi-phase marking code. When

encoding, the SPDIF data signal is modulated by a clock that is twice the bit rate of the data signal.

Table 57 and Figure 43 and Figure 44 show SPDIF timing parameters for the Sony/Philips Digital

Interconnect Format (SPDIF), including the timing of the modulating Rx clock (SPDIF_SR_CLK) for

SPDIF in Rx mode and the timing of the modulating Tx clock (SPDIF_ST_CLK) for SPDIF in Tx mode.

Table 57. SPDIF timing parameters

Timing Parameter Range

Parameter

Symbol

Unit

Min

Max

SPDIF_IN Skew: asynchronous inputs, no specs apply

—

0.7

ns

SPDIF_OUT output (Load = 50 pf)

• Skew

• Transition rising

• Transition falling

—

1.5

24.2

31.3

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Electrical characteristics

Table 57. SPDIF timing parameters (continued)

Timing Parameter Range

Parameter

Symbol

Unit

Min

Max

SPDIF_OUT output (Load = 30 pf)

• Skew

• Transition rising

• Transition falling

1.5

13.6

18.0

—

ns

Modulating Rx clock (SPDIF_SR_CLK) period

SPDIF_SR_CLK high period

srckp

srckph

srckpl

stclkp

stclkph

stclkpl

40.0

16.0

40.0

16.0

—

ns

SPDIF_SR_CLK low period

Modulating Tx clock (SPDIF_ST_CLK) period

SPDIF_ST_CLK high period

SPDIF_ST_CLK low period

srckp

srckpl

V_M

srckph

V_M

SPDIF_SR_CLK

(Output)

Figure 43. SPDIF_SR_CLK timing diagram

stclkp

stclkpl

V_M

stclkph

V_M

SPDIF_ST_CLK

(Input)

Figure 44. SPDIF_ST_CLK timing diagram

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3.9.13 UART I/O configuration and timing parameters

3.9.13.1 UART RS-232 I/O configuration in different modes

The i.MX 8M Mini UART interfaces can serve both as DTE or DCE device. This can be configured by

the DCEDTE control bit (default 0—DCE mode). Table 58 shows the UART I/O configuration based on

the enabled mode.

Table 58. UART I/O configuration vs. mode

DTE Mode

Description

DCE Mode

Description

Port

Direction

UARTx_RTS_B

UARTx_CTS_B

Output

Input

UARTx_RTS_B from DTE to DCE

UARTx_CTS_B from DCE to DTE

Serial data from DCE to DTE

Serial data from DTE to DCE

Input

Output

Input

UARTx_RTS_B from DTE to DCE

UARTx_CTS_B from DCE to DTE

Serial data from DCE to DTE

Serial data from DTE to DCE

UARTx_TX_DATA

UARTx_RX_DATA

Input

Output

3.9.13.2 UART RS-232 Serial mode timing

This section describes the electrical information of the UART module in the RS-232 mode.

3.9.13.2.1 UART transmitter

Figure 45 depicts the transmit timing of UART in the RS-232 Serial mode, with 8 data bit/1 stop bit

format. Table 59 lists the UART RS-232 Serial mode transmit timing characteristics.

Possible

UA1

Bit 3

Parity

Bit

Start

Bit

UARTx_TX_DATA

(output)

STOP

BIT

Bit 7

Bit 0

Bit 1

Bit 2

Bit 4

Bit 5

Bit 6

Par Bit

UA1

Figure 45. UART RS-232 Serial mode transmit timing diagram

Table 59. RS-232 Serial mode transmit timing parameters

ID

Parameter

Symbol

Min

Max

1/F_{baud_rate}+ T_{ref_clk}

Unit

2

UA1 Transmit Bit Time

t_Tbit

1/F_{baud_rate}¹- T_{ref_clk}

—

1

2

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

T_{ref_clk}: The period of UART reference clock ref_clk (ipg_perclk after RFDIV divider).

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3.9.13.2.2

UART receiver

Figure 46 depicts the RS-232 Serial mode receive timing with 8 data bit/1 stop bit format. Table 60 lists

Serial mode receive timing characteristics.

Possible

Parity

UA2

Bit 3

Bit

Start

Bit

STOP

BIT

UARTx_RX_DATA

(output)

Bit 7

Bit 0

Bit 1

Bit 2

Bit 4

Bit 5

Bit 6

Par Bit

UA2

Figure 46. UART RS-232 Serial mode receive timing diagram

Table 60. RS-232 Serial mode receive timing parameters

ID

Parameter

Symbol

Min

Max

Unit

UA2

Receive Bit Time¹

t_Rbit

1/F_{baud_rate}²- 1/(16

1/F_{baud_rate}

+

—

x F_{baud_rate}

)

1/(16 x F_{baud_rate})

1

2

The UART receiver can tolerate 1/(16 x F_{baud_rate}) tolerance in each bit. But accumulation tolerance in one frame must not

exceed 3/(16 x F_{baud_rate}).

F_{baud_rate}: Baud rate frequency. The maximum baud rate the UART can support is (ipg_perclk frequency)/16.

3.9.14 USB PHY parameters

This section describes the USB-OTG PHY parameters.

3.9.14.1 Pad/Package/Board connections

The USBx_VBUS pin cannot directly connect to the 5 V VBUS voltage on the USB2.0 link.

Each USBx_VBUS pin must be isolated by an external 30 K1% precision resistor.

The USB 2.0 PHY uses USBx_TXRTUNE and an external resistor to calibrate the USBx_DP/DN 45 

source impedance. The external resistor value is 200  1% precision on each of USBx_TXRTUNE pad to

ground.

3.9.14.2 USB PHY worst power consumption

Table 61 shows the USB 2.0 PHY worst power dissipation.

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Total Power

Table 61. USB 2.0 PHY worst power dissipation

VDD_USB_3P3

VDD_USB_1P8

Mode

VDD_USB_0P8

HS TX

FS TX

LS TX

8.286

6.767

4.63

23.409

5.968

70.448

63.22

12.52

mA

mW

7.001

0.752

0.761

13.58

0.164

0.163

6.224

0.106

67.779

Suspend

Sleep

1.465

1.472

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Boot mode configuration

4 Boot mode configuration

This section provides information on Boot mode configuration pins allocation and boot devices interfaces

allocation.

4.1

Boot mode configuration pins

Table 62 provides boot options, functionality, fuse values, and associated pins. Several input pins are also

sampled at reset and can be used to override fuse values, depending on the value of BT_FUSE_SEL fuse.

The boot option pins are in effect when BT_FUSE_SEL fuse is ‘0’ (cleared, which is the case for an

unblown fuse). For detailed Boot mode options configured by the Boot mode pins, see the “System Boot,

Fusemap, and eFuse” chapter in the i.MX 8M Mini Applications Processor Reference Manual

(IMX8MMRM).

Table 62. Fuses and associated pins used for boot

Directio

n

State during reset

(POR_B

State after reset

(POR_B

eFuse name

Details

at Reset

asserted)

deasserted)

BOOT_MODE0

BOOT_MODE1

SAI1_RXD0

SAI1_RXD1

SAI1_RXD2

SAI1_RXD3

SAI1_RXD4

SAI1_RXD5

SAI1_RXD6

SAI1_RXD7

SAI1_TXD0

SAI1_TXD1

SAI1_TXD2

SAI1_TXD3

SAI1_TXD4

SAI1_TXD5

SAI1_TXD6

Input

N/A

Input with pull down Input with pull down Boot mode selection

Input with pull down Input with pull down

N/A

BOOT_CFG[0]

BOOT_CFG[1]

BOOT_CFG[2]

BOOT_CFG[3]

BOOT_CFG[4]

BOOT_CFG[5]

BOOT_CFG[6]

BOOT_CFG[7]

BOOT_CFG[8]

BOOT_CFG[9]

Input with pull down Input with pull down Boot options pin value

overrides fuse settings for

Input with pull down Input with pull down

BT_FUSE_SEL = “0“. Signal

configuration as fuse override

input at power up. These are

Input with pull down Input with pull down

special I/O lines that control

the boot configuration during

product development. In

production, the boot

configuration can be

controlled by fuses.

BOOT_CFG[10] Input with pull down Input with pull down

BOOT_CFG[11] Input with pull down Input with pull down

BOOT_CFG[12] Input with pull down Input with pull down

BOOT_CFG[13] Input with pull down Input with pull down

BOOT_CFG[14] Input with pull down Input with pull down

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Boot mode configuration

4.2

Boot device interface allocation

Table 63 lists the interfaces that can be used by the boot process in accordance with the specific Boot

mode configuration. The table also describes the interface’s specific modes and IOMUXC allocation,

which are configured during boot when appropriate.

Table 63. Interface allocation during boot

Interface

IP Instance

Allocated Pads During Boot

Comment

SPI

ECSPI-1

ECSPI1_SCLK, ECSPI1_MOSI, ECSPI1_MISO,

ECSPI1_SS0

The chip-select pin used depends

on the fuse “CS select (SPI only)“.

SPI

ECSPI-2

ECSPI-3

GPMI

ECSPI2_SCLK, ECSPI2_MOSI, ECSPI2_MISO,

ECSPI2_SS0

The chip-select pin used depends

on the fuse “CS select (SPI only)“.

UART1_RXD, UART1_TXD, UART2_RXD,

UART2_TXD

The chip-select pin used depends

on the fuse “CS select (SPI only)“.

NAND Flash

NAND_ALE, NAND_CE0_B, NAND_CLE,

NAND_DATA00,NAND_DATA01,NAND_DATA02,

NAND_DATA03,NAND_DATA04,NAND_DATA05,

NAND_DATA06, NAND_DATA07, NAND_DQS,

NAND_RE_B, NAND_READY_B, NAND_WE_B,

NAND_WP_B

8-bit, only CS0 is supported.

SD/MMC

USDHC-1

GPIO1_IO03, GPIO1_IO06, GPIO1_IO07,

SD1_RESET_B, SD1_CLK, SD1_CMD,

SD1_STROBE, SD1_DATA0, SD1_DATA1,

SD1_DATA2, SD1_DATA3, SD1_DATA4,

SD1_DATA5, SD1_DATA6, SD1_DATA7

1, 4, or 8-bit

SD/MMC

USDHC-2

USDHC-3

GPIO1_IO04, GPIO1_IO08, GPIO1_IO07,

SD2_RESET_B, SD2_WP, SD2_CLK, SD2_CMD,

SD2_DATA0, SD2_DATA1, SD2_DATA2,

SD2_DATA3

1 or 4-bit

NAND_CE1_B, NAND_CE2_B, NAND_CE3_B,

NAND_CLE, NAND_DATA02, NAND_DATA03,

NAND_DATA04,NAND_DATA05,NAND_DATA06,

NAND_DATA07,NAND_RE_B,NAND_READY_B,

NAND_WE_B, NAND_WP_B

1, 4, or 8-bit

FlexSPI

NAND_ALE, NAND_CE0_B, NAND_CE1_B,

NAND_CE2_B, NAND_CE3_B, NAND_CLE,

NAND_DATA00,NAND_DATA01,NAND_DATA02,

NAND_DATA03,NAND_DATA04,NAND_DATA05,

NAND_DATA06, NAND_DATA07, NAND_DQS,

NAND_RE_B

For FlexSPI flash

USB

USB_OTG PHY Dedicated USB pins

—

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

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Package information and contact assignments

5 Package information and contact assignments

This section includes the contact assignment information and mechanical package drawing.

5.1

14 x 14 mm package information

14 x 14 mm, 0.5 mm pitch, ball matrix

5.1.1

Figure 47 shows the top, bottom, and side views of the 14 × 14 mm FCBGA package.

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

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Package information and contact assignments

Figure 47. 14 X 14 MM BGA, case x package top, bottom, and side views

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Package information and contact assignments

5.1.2

14 x 14 mm supplies contact assignments and functional contact

assignments

Table 64 shows supplies contact assignments for the 14 x 14 mm package.

Table 64. i.MX 8M Mini 14 x 14 mm supplies contact assignments

Supply Rail Name

Ball(s) Position(s)

Remark

NC

J18

—

NVCC_CLK

M19

Supply for CLK interface

Supply for DRAM interface

NVCC_DRAM

P7, K8, N8, R8, V8, K9, L9, M9, N9, R9, T9,

U9, V9

NVCC_ECSPI

NVCC_ENET

NVCC_GPIO1

NVCC_I2C

H10

Supply for ESCPI interface

Supply for ENET interface

Supply for GPIO1 interface

Supply for I2C interface

Supply for JTAG interface

Supply for NAND interface

Supply for SAI interface

Supply for SD interface

Supply for SNVS interface

Supply for UART interface

Digital IO pre-drive

W22

W12

J11

NVCC_JTAG

NVCC_NAND

NVCC_SAI1

L19

U19

W18

V19

NVCC_SAI2

NVCC_SAI3

Y10

NVCC_SAI5

W17

V20

NVCC_SD1

NVCC_SD2

V22

NVCC_SNVS_1P8

NVCC_UART

PVCC0_1P8

J22

J12

AB13

T19

PVCC1_1P8

Digital IO pre-drive

PVCC2_1P8

J13

Digital IO pre-drive

VDD_24M_XTAL_1P8

VDD_ANA_0P8

VDD_ANA0_1P8

VDD_ANA1_1P8

VDD_ARM

N19

Supply for XTAL

L17, N17

AA14, Y15

P19, N20

Supply for Analog logic

Supply for ARM

R13, T13, U13, V13, W13, T14, W14, R15,

T15, U15, V15, W15, V16, W16

VDD_ARM_PLL_0P8

VDD_ARM_PLL_1P8

VDD_DRAM

P16

Supply for ARM PLL

Supply for DRAM module

R19

J10, L10, N10, R10, U10, W10

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Package information and contact assignments

Table 64. i.MX 8M Mini 14 x 14 mm supplies contact assignments (continued)

VDD_DRAM_PLL_0P8

VDD_DRAM_PLL_1P8

VDD_GPU

P9

Supply for DRAM PLL

Supply for GPU

P5

R11, U11, W11, P12, V12

VDD_MIPI_0P9

VDD_MIPI_1P2

VDD_MIPI_1P8

VDD_PCI_0P8

VDD_PCI_1P8

VDD_SNVS_0P8

VDD_SOC

J14

J15

H13

J16

G14

K22

Supply for MIPI PHY

Supply for PCIe PHY

Supply for SNVS logic

N13, K15, L15, M15, N15, K16, R17, U17, L18, Supply for SOC logic

N18, R18, U18

VDD_USB_0P8

VDD_USB_1P8

VDD_USB_3P3

VDD_VPU

J17

Supply for USB PHY

Supply for VPU

—

H15

K19

L11, N11, K12, K13, L13, M13, M14

VSS

A1, AG1, C2, H2, Y2, AE2, B3, E3, F3, J3, K3,

N3, P3, R3, V3, W3, AB3, AC3, AF3, C5, AE5,

C6, AE6, G7, J7, K7, N7, R7, V7, W7, AA7, C9,

G9, AA9, AE9, C10, G10, AA10, AE10, L12,

M12, N12, R12, T12, U12, C13, G13, P13,

Y13, AA13, AE13, C14, AE14, C15, G15, P15,

AA15, AE15, L16, M16, N16, R16, T16, U16,

C18, G18, H18, Y18, AA18, AE18, C19, G19,

AA19, AE19, K20, R20, G21, J21, K21, N21,

P21, R21, V21, W21, AA21, C22, AE22, C23,

AE23, E25, F25, J25, K25, N25, P25, R25,

V25, W25, AB25, AC25, B26, A27, AG27

Table 65 shows an alpha-sorted list of functional contact assignments for the 14 x 14 mm package.

Table 65. i.MX 8M Mini 14 x 14 mm functional contact assignments

Reset condition

Ball name

Ball

Power group

Ball type

Input/

Output

status

Default

mode

Default function

24M_XTALI

24M_XTALO

B27

C26

VDD_24M_XTAL_ ANALOG

1P8

—

Input

VDD_24M_XTAL_ ANALOG

1P8

Output

BOOT_MODE0

BOOT_MODE1

G26

G27

NVCC_JTAG

GPIO

ALT0 ccmsrcgpcmix.BOOT_MODE[0] Input with PD

ALT0 ccmsrcgpcmix.BOOT_MODE[1] Input with PD

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Package information and contact assignments

Table 65. i.MX 8M Mini 14 x 14 mm functional contact assignments (continued)

Reset condition

Ball name

Ball

Power group

Ball type

Input/

Output

status

Default

mode

Default function

CLKIN1

CLKIN2

H27

J27

H26

NVCC_CLK

GPIO

—

Input without

PU/PD

Input without

PU/PD

CLKOUT1

Output low

without

PU/PD

CLKOUT2

J26

NVCC_CLK

GPIO

—

Output low

without

PU/PD

DRAM_AC00

DRAM_AC01

DRAM_AC02

DRAM_AC03

DRAM_AC04

DRAM_AC05

DRAM_AC06

DRAM_AC07

DRAM_AC08

DRAM_AC09

DRAM_AC10

DRAM_AC11

DRAM_AC12

DRAM_AC13

DRAM_AC14

DRAM_AC15

DRAM_AC16

DRAM_AC17

DRAM_AC19

DRAM_AC20

DRAM_AC21

DRAM_AC22

DRAM_AC23

F4

F5

NVCC_DRAM

DDR

—

Output low

Input

K4

J4

Input

L2

Input

L1

Input

F6

Input

J5

Input

J6

Input

K6

E4

D5

N4

N5

K5

N6

M1

M2

N2

AB4

AB5

W4

V4

Input

Output low

Input

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Package information and contact assignments

Table 65. i.MX 8M Mini 14 x 14 mm functional contact assignments (continued)

Reset condition

Ball name

Ball

Power group

Ball type

Input/

Output

status

Default

mode

Default function

DRAM_AC24

DRAM_AC25

DRAM_AC26

DRAM_AC27

DRAM_AC28

DRAM_AC29

DRAM_AC30

DRAM_AC31

DRAM_AC32

DRAM_AC33

DRAM_AC34

DRAM_AC35

DRAM_AC36

DRAM_AC37

DRAM_AC38

DRAM_ALERT_N

DRAM_DM0

DRAM_DM1

DRAM_DM2

DRAM_DM3

DRAM_DQ00

DRAM_DQ01

DRAM_DQ02

DRAM_DQ03

DRAM_DQ04

DRAM_DQ05

DRAM_DQ06

DRAM_DQ07

DRAM_DQ08

DRAM_DQ09

U2

U1

N1

R6

W6

V6

NVCC_DRAM

DDR

—

Input

AC4

AD5

R4

R5

T1

T2

V5

W5

AB6

R2

A4

F1

AB1

AG4

A5

B5

D2

D1

C1

B1

A3

B4

F2

G2

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Package information and contact assignments

Table 65. i.MX 8M Mini 14 x 14 mm functional contact assignments (continued)

Reset condition

Ball name

Ball

Power group

Ball type

Input/

Output

status

Default

mode

Default function

DRAM_DQ10

DRAM_DQ11

DRAM_DQ12

DRAM_DQ13

DRAM_DQ14

DRAM_DQ15

DRAM_DQ16

DRAM_DQ17

DRAM_DQ18

DRAM_DQ19

DRAM_DQ20

DRAM_DQ21

DRAM_DQ22

DRAM_DQ23

DRAM_DQ24

DRAM_DQ25

DRAM_DQ26

DRAM_DQ27

DRAM_DQ28

DRAM_DQ29

DRAM_DQ30

DRAM_DQ31

DRAM_DQS0_N

DRAM_DQS0_P

DRAM_DQS1_N

DRAM_DQS1_P

DRAM_DQS2_N

DRAM_DQS2_P

DRAM_DQS3_N

DRAM_DQS3_P

J1

J2

NVCC_DRAM

DDR

—

Input

K2

K1

E1

E2

AB2

AA2

W1

W2

V2

V1

AC1

AC2

AG5

AF5

AD2

AD1

AE1

AF1

AG3

AF4

B2

A2

DDRCLK

—

H1

G1

DDRCLK

—

Y1

AA1

AF2

AG2

DDRCLK

—

DDRCLK

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Package information and contact assignments

Table 65. i.MX 8M Mini 14 x 14 mm functional contact assignments (continued)

Reset condition

Ball name

Ball

Power group

Ball type

Input/

Output

status

Default

mode

Default function

DRAM_RESET_N

DRAM_VREF

DRAM_ZN

R1

P1

NVCC_DRAM

NVCC_ECSPI

NVCC_ENET

NVCC_GPIO1

DDR

—

Output low

—

P2

DDR

—

ECSPI1_MISO

ECSPI1_MOSI

ECSPI1_SCLK

ECSPI1_SS0

ECSPI2_MISO

ECSPI2_MOSI

ECSPI2_SCLK

ECSPI2_SS0

ENET_MDC

ENET_MDIO

ENET_RD0

A7

GPIO

ALT5

ALT0

GPIO5.IO[8]

GPIO5.IO[7]

GPIO5.IO[6]

GPIO5.IO[9]

GPIO5.IO[12]

GPIO5.IO[11]

GPIO5.IO[10]

GPIO5.IO[13]

GPIO1.IO[16]

GPIO1.IO[17]

GPIO1.IO[26]

GPIO1.IO[27]

GPIO1.IO[28]

GPIO1.IO[29]

GPIO1.IO[25]

GPIO1.IO[24]

GPIO1.IO[21]

GPIO1.IO[20]

GPIO1.IO[19]

GPIO1.IO[18]

GPIO1.IO[23]

GPIO1.IO[22]

GPIO1.IO[0]

GPIO1.IO[1]

GPIO1.IO[2]

GPIO1.IO[3]

GPIO1.IO[4]

Input with PD

Output low

B7

D6

B6

A8

B8

E6

A6

AC27

AB27

AE27

AD27

AD26

AC26

AE26

AF27

AG26

AF26

AG25

AF25

AG24

AF24

AG14

AF14

AG13

AF13

AG12

ENET_RD1

ENET_RD2

ENET_RD3

ENET_RXC

ENET_RX_CTL

ENET_TD0

ENET_TD1

ENET_TD2

ENET_TD3

ENET_TXC

ENET_TX_CTL

GPIO1_IO00

GPIO1_IO01¹

GPIO1_IO02

GPIO1_IO03

GPIO1_IO04

Input with PU

Input with PD

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Package information and contact assignments

Table 65. i.MX 8M Mini 14 x 14 mm functional contact assignments (continued)

Reset condition

Ball name

Ball

Power group

Ball type

Input/

Output

status

Default

mode

Default function

GPIO1_IO05²

GPIO1_IO06

GPIO1_IO07

GPIO1_IO08

GPIO1_IO09

GPIO1_IO10

GPIO1_IO11

GPIO1_IO12

GPIO1_IO13

GPIO1_IO14

GPIO1_IO15

I2C1_SCL

AF12

AG11

AF11

AG10

AF10

AD10

AC10

AB10

AD9

AC9

AB9

E9

NVCC_GPIO1

NVCC_I2C

GPIO

PHY

ALT0

ALT5

ALT0

—

GPIO1.IO[5]

GPIO1.IO[6]

GPIO1.IO[7]

GPIO1.IO[8]

GPIO1.IO[9]

GPIO1.IO[10]

GPIO1.IO[11]

GPIO1.IO[12]

GPIO1.IO[13]

GPIO1.IO[14]

GPIO1.IO[15]

GPIO5.IO[14]

GPIO5.IO[15]

GPIO5.IO[16]

GPIO5.IO[17]

GPIO5.IO[18]

GPIO5.IO[19]

GPIO5.IO[20]

GPIO5.IO[21]

cjtag_wrapper.MOD

cjtag_wrapper.TCK

cjtag_wrapper.TDI

cjtag_wrapper.TDO

cjtag_wrapper.TMS

cjtag_wrapper.TRST_B

—

Output high

Input with PD

Input with PU

Input with PD

Input with PU

Input

I2C1_SDA

F9

NVCC_I2C

I2C2_SCL

D10

D9

NVCC_I2C

I2C2_SDA

NVCC_I2C

I2C3_SCL

E10

F10

NVCC_I2C

I2C3_SDA

NVCC_I2C

I2C4_SCL

D13

E13

D27

F26

NVCC_I2C

I2C4_SDA

NVCC_I2C

JTAG_MOD

JTAG_TCK

NVCC_JTAG

VDD_MIPI_1P8

JTAG_TDI

E27

E26

F27

JTAG_TDO

JTAG_TMS

JTAG_TRST_B

MIPI_CSI_CLK_N

MIPI_CSI_CLK_P

MIPI_CSI_D0_N

MIPI_CSI_D0_P

MIPI_CSI_D1_N

C27

A16

B16

A14

B14

A15

PHY

—

Input

PHY

—

Input

PHY

—

Input

PHY

—

Input

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Package information and contact assignments

Table 65. i.MX 8M Mini 14 x 14 mm functional contact assignments (continued)

Reset condition

Ball name

Ball

Power group

Ball type

Input/

Output

status

Default

mode

Default function

MIPI_CSI_D1_P

MIPI_CSI_D2_N

MIPI_CSI_D2_P

MIPI_CSI_D3_N

MIPI_CSI_D3_P

MIPI_DSI_CLK_N

MIPI_DSI_CLK_P

MIPI_DSI_D0_N

MIPI_DSI_D0_P

MIPI_DSI_D1_N

MIPI_DSI_D1_P

MIPI_DSI_D2_N

MIPI_DSI_D2_P

MIPI_DSI_D3_N

MIPI_DSI_D3_P

MIPI_VREG_CAP

NAND_ALE

B15

A17

B17

A18

B18

A11

B11

A9

VDD_MIPI_1P8

0.35 - 0.45 V

PHY

—

Input

—

Input

PHY

—

Input

PHY

—

Input

PHY

—

Input

PHY

—

Output low

Output

PHY

—

PHY

—

B9

PHY

—

A10

B10

A12

B12

A13

B13

D15

N22

N24

P27

M27

L27

K27

P23

K24

K23

N23

M26

L26

K26

N26

PHY

—

PHY

—

PHY

—

PHY

—

PHY

—

PHY

—

PHY

—

NVCC_NAND

GPIO

ALT5

GPIO3.IO[0]

GPIO3.IO[1]

GPIO3.IO[2]

GPIO3.IO[3]

GPIO3.IO[4]

GPIO3.IO[5]

GPIO3.IO[6]

GPIO3.IO[7]

GPIO3.IO[8]

GPIO3.IO[9]

GPIO3.IO[10]

GPIO3.IO[11]

GPIO3.IO[12]

GPIO3.IO[13]

Input with PD

Input with PU

Input with PD

NAND_CE0_B

NAND_CE1_B

NAND_CE2_B

NAND_CE3_B

NAND_CLE

NAND_DATA00

NAND_DATA01

NAND_DATA02

NAND_DATA03

NAND_DATA04

NAND_DATA05

NAND_DATA06

NAND_DATA07

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Table 65. i.MX 8M Mini 14 x 14 mm functional contact assignments (continued)

Reset condition

Ball name

Ball

Power group

Ball type

Input/

Output

status

Default

mode

Default function

NAND_DQS

NAND_RE_B

NAND_READY_B

NAND_WE_B

NAND_WP_B

ONOFF

R22

N27

P26

R26

R27

A25

NVCC_NAND

NVCC_SNVS_1P8

GPIO

ALT5

ALT0

GPIO3.IO[14]

GPIO3.IO[15]

GPIO3.IO[16]

GPIO3.IO[17]

GPIO3.IO[18]

snvsmix.ONOFF

Input with PD

Input with PU

Input with PD

Input without

PU/PD

PCIE_CLK_N

PCIE_CLK_P

PCIE_RESREF

PCIE_RXN_N

PCIE_RXN_P

PCIE_TXN_N

A21

B21

D19

A19

B19

A20

VDD_PCI_1P8

PHY

—

High-Z

Input, High-Z

Output,

High-Z

PCIE_TXN_P

B20

A24

VDD_PCI_1P8

PHY

—

Output,

High-Z

PMIC_ON_REQ

NVCC_SNVS_1P8

GPIO

ALT0

snvsmix.PMIC_ON_REQ

Open-drain

output high

with PU

PMIC_STBY_REQ

POR_B

E24

B24

NVCC_SNVS_1P8

GPIO

ALT0 ccmsrcgpcmix.PMIC_STBY_RE Output low

Q

with PD

ALT0

snvsmix.POR_B

Input without

PU/PD

RTC_XTALI

RTC_XTALO

A26

B25

NVCC_SNVS_1P8 ANALOG

—

Input

Output,

inverted of

RTC_XTALI

RTC_RESET_B

F24

NVCC_SNVS_1P8

GPIO

ALT0

snvsmix.RTC_POR_B

Input without

PU/PD

SAI1_MCLK

SAI1_RXC

SAI1_RXD0

SAI1_RXD1

SAI1_RXD2

AB18

AF16

AG15

AF15

AG17

NVCC_SAI1

GPIO

ALT5

GPIO4.IO[20]

GPIO4.IO[1]

GPIO4.IO[2]

GPIO4.IO[3]

GPIO4.IO[4]

Input with PD

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

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Table 65. i.MX 8M Mini 14 x 14 mm functional contact assignments (continued)

Reset condition

Ball name

Ball

Power group

Ball type

Input/

Output

status

Default

mode

Default function

SAI1_RXD3

SAI1_RXD4

SAI1_RXD5

SAI1_RXD6

SAI1_RXD7

SAI1_RXFS

SAI1_TXC

AF17

AG18

AF18

AG19

AF19

AG16

AC18

AG20

AF20

AG21

AF21

AG22

AF22

AG23

AF23

AB19

AD19

AB22

AC24

AC19

AD22

AC22

AD23

AD6

NVCC_SAI1

NVCC_SAI2

NVCC_SAI3

GPIO

ALT5

GPIO4.IO[5]

GPIO4.IO[6]

GPIO4.IO[7]

GPIO4.IO[8]

GPIO4.IO[9]

GPIO4.IO[0]

GPIO4.IO[11]

GPIO4.IO[12]

GPIO4.IO[13]

GPIO4.IO[14]

GPIO4.IO[15]

GPIO4.IO[16]

GPIO4.IO[17]

GPIO4.IO[18]

GPIO4.IO[19]

GPIO4.IO[10]

GPIO4.IO[27]

GPIO4.IO[22]

GPIO4.IO[23]

GPIO4.IO[21]

GPIO4.IO[25]

GPIO4.IO[26]

GPIO4.IO[24]

GPIO5.IO[2]

GPIO4.IO[29]

GPIO4.IO[30]

GPIO4.IO[28]

GPIO5.IO[0]

GPIO5.IO[1]

GPIO4.IO[31]

Input with PD

SAI1_TXD0

SAI1_TXD1

SAI1_TXD2

SAI1_TXD3

SAI1_TXD4

SAI1_TXD5

SAI1_TXD6

SAI1_TXD7

SAI1_TXFS

SAI2_MCLK

SAI2_RXC

SAI2_RXD0

SAI2_RXFS

SAI2_TXC

SAI2_TXD0

SAI2_TXFS

SAI3_MCLK

SAI3_RXC

SAI3_RXD

SAI3_RXFS

SAI3_TXC

AG7

AF7

AG8

AG6

SAI3_TXD

AF6

SAI3_TXFS

AC6

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Table 65. i.MX 8M Mini 14 x 14 mm functional contact assignments (continued)

Reset condition

Ball name

Ball

Power group

Ball type

Input/

Output

status

Default

mode

Default function

SAI5_MCLK³

AD15

NVCC_SAI5

GPIO

ALT5

GPIO3.IO[25]

Input without

PU/PD

SAI5_RXC

SAI5_RXD0

SAI5_RXD1

SAI5_RXD2

SAI5_RXD3

SAI5_RXFS

SD1_CLK

AC15

AD18

AC14

AD13

AC13

AB15

V26

NVCC_SAI5

NVCC_SD1

NVCC_SD2

NVCC_SAI3

GPIO

ALT5

GPIO3.IO[20]

GPIO3.IO[21]

GPIO3.IO[22]

GPIO3.IO[23]

GPIO3.IO[24]

GPIO3.IO[19]

GPIO2.IO[0]

GPIO2.IO[1]

GPIO2.IO[2]

GPIO2.IO[3]

GPIO2.IO[4]

GPIO2.IO[5]

GPIO2.IO[6]

GPIO2.IO[7]

GPIO2.IO[8]

GPIO2.IO[9]

GPIO2.IO[10]

GPIO2.IO[11]

GPIO2.IO[12]

GPIO2.IO[13]

GPIO2.IO[14]

GPIO2.IO[15]

GPIO2.IO[16]

GPIO2.IO[17]

GPIO2.IO[18]

GPIO2.IO[19]

GPIO2.IO[20]

GPIO5.IO[5]

GPIO5.IO[4]

Input with PD

SD1_CMD

V27

SD1_DATA0

SD1_DATA1

SD1_DATA2

SD1_DATA3

SD1_DATA4

SD1_DATA5

SD1_DATA6

SD1_DATA7

SD1_RESET_B

SD1_STROBE

SD2_CD_B

SD2_CLK

Y27

Y26

T27

T26

U27

U26

W27

W26

R23

R24

AA26

W23

W24

AB23

AB24

V24

SD2_CMD

SD2_DATA0

SD2_DATA1

SD2_DATA2

SD2_DATA3

SD2_RESET_B

SD2_WP

V23

AB26

AA27

AF8

SPDIF_EXT_CLK

SPDIF_RX

AG9

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

82

Package information and contact assignments

Table 65. i.MX 8M Mini 14 x 14 mm functional contact assignments (continued)

Reset condition

Ball name

Ball

Power group

Ball type

Input/

Output

status

Default

mode

Default function

SPDIF_TX

AF9

D26

J23

NVCC_SAI3

NVCC_JTAG

GPIO

ALT5

ALT0

—

GPIO5.IO[3]

tcu.TEST_MODE

—

Input with PD

Output low

TEST_MODE

TSENSOR_TEST_

OUT

VDD_ANA1_1P8

ANALOG

TSENSOR_REST_

EXT

J24

VDD_ANA1_1P8

ANALOG

—

UART1_RXD

UART1_TXD

UART2_RXD

UART2_TXD

UART3_RXD

UART3_TXD

UART4_RXD

UART4_TXD

USB1_DN

E14

F13

F15

E15

E18

D18

F19

F18

A22

B22

D22

E19

F22

A23

B23

D23

E22

F23

NVCC_UART

VDD_USB_3P3

VDD_USB_1P8

VDD_USB_3P3

VDD_USB_1P8

VDD_USB_3P3

GPIO

PHY

ALT5

—

GPIO5.IO[22]

Input with PD

Input

GPIO5.IO[23]

GPIO5.IO[24]

GPIO5.IO[25]

GPIO5.IO[26]

GPIO5.IO[27]

GPIO5.IO[28]

GPIO5.IO[29]

—

USB1_DP

—

Input

USB1_ID

—

Input

USB1_TXRTUNE

USB1_VBUS

USB2_DN

—

Input

USB2_DP

—

Input

USB2_ID

—

Input

USB2_TXRTUNE

USB2_VBUS

—

1

2

3

Works as JTAG Active output when the internal reset is asserted, default is output low. After the internal reset is deasserted,

it becomes input with PD.

Works as INT_BOOT output when the internal reset is asserted, default is output high. After the internal reset is deasserted,

it becomes input with PU.

Works as TESTER_ACK input when the internal reset is asserted, default is input without PU/PD. After the internal reset is

deasserted, it becomes input with PD.

5.1.3

i.MX 8M Mini 14 x 14 mm 0.5 mm pitch ball map

Table 66 shows the i.MX 8M Mini 14 x 14 mm 0.5 mm pitch ball map.

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

83

Package information and contact assignments

Table 66. 14 x 14 mm, 0.5 mm pitch ball map

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

1

2

3

4

5

6

7

8

9

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

84

Package information and contact assignments

Table 66. 14 x 14 mm, 0.5 mm pitch ball map (continued)

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

1

2

3

4

5

6

7

8

9

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

85

Package information and contact assignments

Table 66. 14 x 14 mm, 0.5 mm pitch ball map (continued)

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

1

2

3

4

5

6

7

8

9

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

86

Package information and contact assignments

Table 66. 14 x 14 mm, 0.5 mm pitch ball map (continued)

10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27

1

2

3

4

5

6

7

8

9

5.2

DDR pin function list

Table 67 shows the DDR pin function list.

Table 67. DDR pin function list

Ball name

LPDDR4

DDR4

DDR3/3L

DRAM_DQS0_P

DRAM_DQS0_N

DRAM_DM0

DQS0_t_A

DQS0_c_A

DMI0_A

DQ0_A

DQSL_t_A

DQSL_c_A

DML_n_A / DBIL_n_A

DQL0_A

DQSL_A

DQSL#_A

DML_A

DRAM_DQ00

DRAM_DQ01

DRAM_DQ02

DRAM_DQ03

DRAM_DQ04

DRAM_DQ05

DQL0_A

DQL1_A

DQL2_A

DQL3_A

DQL4_A

DQL5_A

DQ1_A

DQL1_A

DQ2_A

DQL2_A

DQ3_A

DQL3_A

DQ4_A

DQL4_A

DQ5_A

DQL5_A

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

87

Package information and contact assignments

Table 67. DDR pin function list (continued)

DRAM_DQ06

DRAM_DQ07

DRAM_DQS1_P

DRAM_DQS1_N

DRAM_DM1

DQ6_A

DQ7_A

DQL6_A

DQL7_A

DQL6_A

DQL7_A

DQSU_A

DQSU#_A

DMU_A

DQS1_t_A

DQS1_c_A

DMI1_A

DQ08_A

DQ09_A

DQ10_A

DQ11_A

DQ12_A

DQ13_A

DQ14_A

DQ15_A

DQS0_t_B

DQS0_c_B

DMI0_B

DQ0_B

DQSU_t_A

DQSU_c_A

DMU_n_A / DBIU_n_A

DQU0_A

DRAM_DQ08

DRAM_DQ09

DRAM_DQ10

DRAM_DQ11

DRAM_DQ12

DRAM_DQ13

DRAM_DQ14

DRAM_DQ15

DRAM_DQS2_P

DRAM_DQS2_N

DRAM_DM2

DQU0_A

DQU1_A

DQU2_A

DQU3_A

DQU4_A

DQU5_A

DQU6_A

DQU7_A

DQSL_B

DQSL#_B

DML_B

DQU1_A

DQU2_A

DQU3_A

DQU4_A

DQU5_A

DQU6_A

DQU7_A

DQSL_t_B

DQSL_c_B

DML_n_B / DBIL_n_B

DQL0_B

DRAM_DQ16

DRAM_DQ17

DRAM_DQ18

DRAM_DQ19

DRAM_DQ20

DRAM_DQ21

DRAM_DQ22

DRAM_DQ23

DRAM_DQS3_P

DRAM_DQS3_N

DRAM_DM3

DQL0_B

DQL1_B

DQL2_B

DQL3_B

DQL4_B

DQL5_B

DQL6_B

DQL7_B

DQSU_B

DQSU#_B

DMU_B

DQ1_B

DQL1_B

DQ2_B

DQL2_B

DQ3_B

DQL3_B

DQ4_B

DQL4_B

DQ4_B

DQL4_B

DQ5_B

DQL5_B

DQ6_B

DQL6_B

DQ7_B

DQL7_B

DQS1_t_B

DQS1_c_B

DMI1_B

DQ08_B

DQ09_B

DQ10_B

DQ11_B

DQ12_B

DQ13_B

DQSU_t_B

DQSU_c_B

DMU_n_B / DBIU_n_B

DQU0_B

DRAM_DQ24

DRAM_DQ25

DRAM_DQ26

DRAM_DQ27

DRAM_DQ28

DRAM_DQ29

DQU0_B

DQU1_B

DQU2_B

DQU3_B

DQU4_B

DQU5_B

DQU1_B

DQU2_B

DQU3_B

DQU4_B

DQU5_B

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

88

Package information and contact assignments

Table 67. DDR pin function list (continued)

DRAM_DQ30

DRAM_DQ31

DRAM_RESET_N

DRAM_ALERT_N

DRAM_AC00

DRAM_AC01

DRAM_AC02

DRAM_AC03

DRAM_AC04

DRAM_AC05

DRAM_AC06

DRAM_AC07

DRAM_AC08

DRAM_AC09

DRAM_AC10

DRAM_AC11

DRAM_AC12

DRAM_AC13

DRAM_AC14

DRAM_AC15

DRAM_AC16

DRAM_AC17

DRAM_AC19

DRAM_AC20

DRAM_AC21

DRAM_AC22

DRAM_AC23

DRAM_AC24

DRAM_AC25

DRAM_AC26

DRAM_AC27

DRAM_AC28

DRAM_AC29

DRAM_AC30

DQ14_B

DQ15_B

RESET_N

MTEST1

CKE0_A

CKE1_A

CS0_A

CS1_A

CK_t_A

CK_c_A

—

DQU6_B

DQU7_B

RESET#

MTEST1

CKE0

CKE1

CS0#

—

DQU7_B

RESET_n

ALERT_n / MTEST1

CKE0

CKE1

CS0_n

C0

BG0

BG1

ACT_n

A9

BA2

A14

A15

—

A9

CA0_A

CA1_A

CA2_A

CA3_A

CA4_A

CA5_A

—

A12

A12 / BC#

A11

A7

A8

A6

A5

A4

—

A3

—

CK_t_A

CK_c_A

MTEST

CK_t_B

CK_c_B

—

CK_A

CK#_A

MTEST

CK_B

CK#_B

—

MTEST

CKE0_B

CKE1_B

CS1_B

CS0_B

CK_t_B

CK_c_B

—

A2

A1

BA1

—

PARITY

A13

—

CA0_B

CA1_B

CA2_B

A13

BA0

A10 / AP

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

89

Package information and contact assignments

Table 67. DDR pin function list (continued)

DRAM_AC31

DRAM_AC32

DRAM_AC33

DRAM_AC34

DRAM_AC35

DRAM_AC36

DRAM_AC37

DRAM_AC38

DRAM_ZN

CA3_B

CA4_B

CA5_B

—

A0

C2

A0

—

CAS_n / A15

WE_n / A14

RAS_n / A16

ODT0

CAS#

WE#

RAS#

ODT0

ODT1

CS1#

ZQ

—

ODT1

—

CS1_n

ZQ

DRAM_VREF

VREF

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

90

Revision history

6 Revision history

Table 68 provides a revision history for this data sheet.

Table 68. Revision history

Rev.

number

Date

Substantive change(s)

Rev. 1

07/2020 • Updated the eMMC descriptions in the Table 1, "Features"

• Updated numbers of SD 3.0 in the Figure 1, "i.MX 8M Mini system block diagram"

• Added two part numbers and updated the part differentiator in the Table 2, "Orderable part

numbers"

• Updated the part differentiator and Fusing in the Figure 2, "Part number nomenclature—i.MX 8M

Mini family of processors"

• Updated eCSPI, SJC, and uSDHC descriptions in the Table 3, "i.MX 8M Mini modules list"

• Updated a typo for NVCC_ENET in the Table 4, "Recommended connections for unused power

supply rails"

• Updated the min values and a typo in the Table 7, "Absolute maximum ratings"; removed ESD

parameters from the Table 7, "Absolute maximum ratings"

• Added the Table 8, "Electrostatic discharge and latch up ratings"

• Added a footnote in the Table 10, "Operating ranges"

• Added VDD_24M_XTAL_1P8, VDD_ARM_PLL_1P8, and PVCCx_1P8 in the Table 13, "Maximum

supply currents"

• Updated the Table 14, "Chip power in different LP mode"

• Updated the suspend mode state of VDD_MIPI_0P9 and VDD_MIPI_1P2 in the Table 15, "The

power supply states"

• Updated the maximum values of T1, T2, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13 and minimum

value of T3 in the Table 17, "Power-up sequence"

• Updated the maximum values in the Table 18, "Power-down sequence"

• Removed the USBx_ID, ONOFF, and POR_B from the Table 22, "Additional leakage parameters"

• Added GPIO1_09, I2C2_SCL, and I2C2_SDA in the Table 35, "ENET signal mapping"

• Removed 0x2 from the Section 3.9.10.1.1, SDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0,

0x1 and Section 3.9.10.1.3, DDR mode with FlexSPIn_MCR0[RXCLKSRC] = 0x0, 0x1

• Updated the parameters of GPIO1_IO00, GPIO1_IO01, GPIO1_IO05, GPIO1_IO09, and

SAI5_MCLK in the Table 65, "i.MX 8M Mini 14 x 14 mm functional contact assignments"

• Fixed a typo in the Table 66, "14 x 14 mm, 0.5 mm pitch ball map"

Rev. 0.2

04/2019 • Updated numbers of eMMC and FlexSPI in the Figure 1, "i.MX 8M Mini system block diagram"

• Updated the descriptions about USB and uSDHC in the Table 3, "i.MX 8M Mini modules list"

• Updated the comment of VDD_VPU and the LPDDR4 maximum value of NVCC_DRAM in the

Table 10, "Operating ranges"

Rev. 0.1

Rev. 0

02/2019 • Updated the SNVS states in the Table 15, "The power supply states"

02/2019 • Initial version

i.MX 8M Mini Applications Processor Datasheet for Consumer Products, Rev. 1, 07/2020

NXP Semiconductors

91

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EdgeScale, EdgeLock, eIQ, and Immersive3D are trademarks of NXP B.V. All other product

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Document Number: IMX8MMCEC

Rev. 1

07/2020


型号：	MIMX8MM4CVTLZCA
厂家：	NXP
描述：	i.MX 8M Mini Applications Processor Datasheet for Consumer Products
文件：	总92页 (文件大小：1676K)
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