MK80FN256VLQ15 [NXP]
Kinetis K80 Sub-Family;
| 型号： | MK80FN256VLQ15 |
| 厂家： | 
NXP |
| 描述： | Kinetis K80 Sub-Family |
| 文件： | 总95页 (文件大小：1134K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NXP Semiconductors
Data Sheet: Technical Data
K80P121M150SF5
Rev. 5, 11/2016
Kinetis K80 Sub-Family
MK80FN256VLL15
High performance ARM® Cortex®-M4F MCU with up to
256KB of Flash, 256KB of SRAM, Full Speed USB
connectivity, and QuadSPI for interfacing to Serial NOR
flash
MK80FN256VDC15
MK80FN256VLQ15
MK80FN256CAx15
The K80 sub-family extends Kinetis products with new features
including QuadSPI serial flash interface and separate voltage
domain for a sub-set of IO pins. The QuadSPI interface supports
connections to Non-Volatile Memory for data or code. The
extended memory resources allow developers to enhance their
embedded applications with greater capability and features.
Software compatibility with previous Kinetis devices ensures
quick transitions from other Kinetis subfamilies. Enhancements
include High Speed RUN for greater performance, and smart
Peripherals like LPUART which can operate in STOP modes.
121 XFBGA (DC)
8 x 8 x 0.5 mm Pitch
0.65 mm
100 LQFP (LL)
14 x 14 x 1.7 Pitch
0.5mm
144 LQFP (LQ)
20 x 20 x 1.6 Pitch 0.5
mm
121 WLCSP (Ax)
4.64 mm x 4.53 mm
Performance
• Up to 150 MHz ARM Cortex-M4 based core with DSP
Analog modules
• One 16-bit SAR ADCs, two 6-bit DAC and one
12-bit DAC
instructions and Single Precision Floating Point unit
• Two analog comparators (CMP) containing a
6-bit DAC and programmable reference input
• Voltage reference 1.2V
Memories and memory expansion
• Up to 256 KB program flash with 256 KB RAM
• FlexBus external bus interface and SDRAM controller
• Dual QuadSPI with OTF decryption and XIP
• 32 KB Boot ROM with built in bootloader
Operating Characteristics
• Main VDD Voltage and Flash write voltage
range:1.71V–3.6 V
• Supports SDR and DDR serial flash and octal configurations
• Temperature range (ambient): -40 to 105°C
• Independent VDDIO for PORTE (QuadSPI):
1.71V–3.6 V
System and Clocks
• Multiple low-power modes
• Memory protection unit with multi-master protection
• 3 to 32 MHz main crystal oscillator
• 32 kHz low power crystal oscillator
• 48 MHz internal reference
Communication interfaces
• USB full-/low-speed On-the-Go controller
• Secure Digital Host Controller (SDHC) and
FlexIO
Timers
• One I2S module, three SPI, four I2C modules
and five LPUART modules
• One 4 ch-Periodic interrupt timer
• Two 16-bit low-power timer PWM modules
• Two 8-ch motor control/general purpose/PWM timers
• Two 2-ch quadrature decoder/general purpose timers
• Real-time clock with independent 3.3V power domain
• Programmable delay block
Security
• Hardware random-number generator
• Supports DES, AES, SHA accelerator (CAU)
• Multiple levels of embedded flash security
Human-machine interface
• Low-power hardware touch sensor interface (TSI)
• General-purpose input/output
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information
Memory
Part Number
Maximum number of I\O's
Flash
SRAM
256 KB
256 KB
256 KB
256 KB
MK80FN256VLL15
MK80FN256VDC15
MK80FN256CAx15R1
MK80FN256VLQ152
256 KB
256 KB
256 KB
256 KB
66
87
87
102
1. The 121-pin WLCSP package for this product is not yet available, however it is included in a Package Your Way
program for Kinetis MCUs. Visit nxp.com/KPYW for more details.
2. The 144-pin LQFP package for this product is not yet available, however it is included in a Package Your Way program
for Kinetis MCUs. Visit nxp.com/KPYW for more details.
Device Revision Number
Device Mask Set Number
SIM_SDID[REVID]
JTAG ID Register[PRN]
1N03P
0001
0001
Related Resources
Description
Type
Product
Resource
The Product Selector lets you find the right Kinetis part for your design.
K-Series Product Selector
Selector
Fact Sheet
The Fact Sheet gives overview of the product key features and its uses. K8x Fact Sheet
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
K80P121M150SF5RM1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
This document.
Chip Errata
The chip mask set Errata provides additional or corrective information for Kinetis_K_1N03P1
a particular device mask set.
Package
drawing
Package dimensions are provided in package drawings.
• LQFP 100-pin:
98ASS23308W1
• XFBGA 121-pin:
98ASA00595D1
• LQFP 144-pin:
98ASS23177W2
• WLCSP 121-pin: Under
development2
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
2. This package for this product is not yet available, however it is included in a Package Your Way program for Kinetis
MCUs. Visit nxp.com/KPYW for more details.
2
Kinetis K80 Sub-Family, Rev. 5, 11/2016
NXP Semiconductors
Cryptographic
accelerator
(CAU)
RTC
OSC
ARM Cortex M4
MCG
Trace
Port
PIT
TPIU
PPB
ETM
NVIC
ITM
IRC
OSC
PLL
48 MHz
WIC
JTAG &
Serial Wire
AHB-AP
SWJ-DP
DSP
FPU
FPB
DWT
IRC
4 MHz
DMA
Mux x2
FLL
192 KByte
eDMA
eSDHC
MUX
64 KByte
Cache
SRAM
8 Kbyte
8 Kbyte
M2
M4
M0
M1
M3
Crossbar Switch (XBS)
System Memory Protection Unit (MPU)
S3
S2
S1
S5
S0
S4
BME2
RGPIO
Flash
Controller
BOOT
ROM
AHB to IPS 0
AHB to IPS 1
SDRAMC
FlexBus
QSPI
x128
EMVSIM
x2
6-bit DAC
& CMP x2
SPI
x3
Flash
256 KByte
PDB
PIT
FlexIO
FlexTimer
x4
I2C
x4
LPUART
x5
TRNG
16-bit ADC
TPM
x2
Vref
CMT
RTC
CRC
PMC
TSI
I2S
Low-power
timer x2
12-bit DAC
Figure 1. K80 Block Diagram
Kinetis K80 Sub-Family, Rev. 5, 11/2016
3
NXP Semiconductors
Table of Contents
1 Ratings....................................................................................5
3.5.2
3.5.3
3.5.4
CMP and 6-bit DAC electrical specifications.....50
1.1 Thermal handling ratings................................................. 5
1.2 Moisture handling ratings................................................ 5
1.3 ESD handling ratings.......................................................5
1.4 Voltage and current operating ratings............................. 5
12-bit DAC electrical characteristics................. 52
Voltage reference electrical specifications........55
3.6 Timers..............................................................................56
3.7 Communication interfaces............................................... 56
1.4.1
Recommended POR Sequencing ....................6
3.7.1
3.7.2
3.7.3
3.7.4
EMV SIM specifications.................................... 57
USB VREG electrical specifications..................61
USB DCD electrical specifications.................... 62
DSPI switching specifications (limited voltage
range)................................................................63
DSPI switching specifications (full voltage
2 General................................................................................... 8
2.1 AC electrical characteristics.............................................8
2.2 Nonswitching electrical specifications..............................9
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
Voltage and current operating requirements.....9
HVD, LVD and POR operating requirements....10
Voltage and current operating behaviors.......... 11
Power mode transition operating behaviors......12
Power consumption operating behaviors..........14
Electromagnetic Compatibility (EMC)
3.7.5
range)................................................................64
I2C switching specifications.............................. 66
UART switching specifications..........................66
LPUART switching specifications......................66
SDHC specifications......................................... 67
3.7.6
3.7.7
3.7.8
3.7.9
specifications.....................................................20
Designing with radiated emissions in mind....... 20
Capacitance attributes...................................... 20
2.2.7
2.2.8
3.7.10 I2S switching specifications.............................. 68
3.8 Human-machine interfaces (HMI)....................................74
2.3 Switching specifications...................................................21
3.8.1
TSI electrical specifications...............................74
2.3.1
2.3.2
Device clock specifications............................... 21
General switching specifications.......................21
4 Dimensions............................................................................. 74
4.1 Obtaining package dimensions....................................... 74
5 Pinout......................................................................................75
5.1 K80 Signal Multiplexing and Pin Assignments.................75
5.2 Recommended connection for unused analog and
2.4 Thermal specifications.....................................................23
2.4.1
2.4.2
Thermal operating requirements.......................23
Thermal attributes............................................. 23
3 Peripheral operating requirements and behaviors.................. 24
3.1 Core modules.................................................................. 24
digital pins........................................................................82
5.3 K80 Pinouts..................................................................... 84
6 Ordering parts......................................................................... 88
6.1 Determining valid orderable parts....................................88
7 Part identification.....................................................................89
7.1 Description.......................................................................89
7.2 Format............................................................................. 89
7.3 Fields............................................................................... 89
7.4 Example...........................................................................90
8 Terminology and guidelines.................................................... 90
8.1 Definitions........................................................................90
8.2 Examples.........................................................................91
8.3 Typical-value conditions.................................................. 91
8.4 Relationship between ratings and operating
3.1.1
3.1.2
Debug trace timing specifications..................... 24
JTAG electricals................................................25
3.2 Clock modules................................................................. 28
3.2.1
3.2.2
3.2.3
3.2.4
MCG specifications........................................... 28
IRC48M specifications...................................... 31
Oscillator electrical specifications..................... 32
32 kHz oscillator electrical characteristics.........34
3.3 Memories and memory interfaces................................... 34
3.3.1
3.3.2
3.3.3
3.3.4
QuadSPI AC specifications...............................34
Flash electrical specifications............................39
Flexbus switching specifications....................... 41
SDRAM controller specifications.......................43
3.4 Security and integrity modules........................................ 46
3.5 Analog............................................................................. 46
requirements....................................................................92
8.5 Guidelines for ratings and operating requirements..........92
9 Revision History...................................................................... 92
3.5.1
ADC electrical specifications.............................46
4
Kinetis K80 Sub-Family, Rev. 5, 11/2016
NXP Semiconductors
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
VHBM
Description
Min.
-2000
-500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
ILAT
Latch-up current at ambient temperature of 105°C
-100
+100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
1.4 Voltage and current operating ratings
Kinetis K80 Sub-Family, Rev. 5, 11/2016
5
NXP Semiconductors
Ratings
Symbol
Description
Min.
–0.3
Max.
3.8
Unit
V
VDD
VDDA
VDDIO_E
VBAT
IDD
Digital supply voltage
Analog supply voltage
VDDIO_E is an independent voltage supply for PORTE 1
VDD – 0.3
–0.3
VDD + 0.3
3.8
V
V
RTC supply voltage
–0.3
3.8
V
Digital supply current
—
300
mA
V
VIO
Input voltage (except PORTE, VBAT domain pins, and
USB0)2
–0.3
VDD + 0.3
VIO_E
ID
PORTE input voltage3
–0.3
–25
VDDIO_E + 0.3
V
mA
V
Maximum current single pin limit (digital output pins)
USB regulator input
25
6.0
VREGIN
VUSB0_Dx
–0.3
–0.3
USB0_DP and USB_DM input voltage
3.63
V
1. VDDIO_E is independent of the VDD domain and can operate at a voltage independent of VDD. However, it is required that
the VDD domain be powered up before VDDIO_E. VDDIO_E must never be higher than VDD during power ramp up, or power
down. VDD and VDDIO_E may ramp together if tied to the same power supply.
2. Includes ADC, CMP, and RESET_b inputs.
3. PORTE analog input voltages cannot exceed VDDIO_E supply when VDD ≥ VDDIO_E. PORTE analog input voltages cannot
exceed VDD supply when VDD < VDDIO_E
.
1.4.1 Recommended POR Sequencing
Cases
• VDD = VDDIO_E
• VDD > VDDIO_E
• VDD < VDDIO_E
6
Kinetis K80 Sub-Family, Rev. 5, 11/2016
NXP Semiconductors
Ratings
Figure 2. VDD = VDDIO_E
Figure 3. VDD > VDDIO_E
Kinetis K80 Sub-Family, Rev. 5, 11/2016
7
NXP Semiconductors
General
Figure 4. VDD < VDDIO_E
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 5. Input signal measurement reference
All digital I/O switching characteristics assume:
1. output pins
8
Kinetis K80 Sub-Family, Rev. 5, 11/2016
NXP Semiconductors
General
• have CL=15pF loads,
• are slew rate disabled, and
• are normal drive strength
2. input pins
• have their passive filter disabled (PORTx_PCRn[PFE]=0)
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 1. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
Max.
3.6
3.6
3.6
0.1
0.1
3.6
—
Unit
V
Notes
Supply voltage
Supply voltage
Analog supply voltage
VDDIO_E
VDDA
1.71
V
1.71
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
–0.1
V
–0.1
V
VBAT
VIH
RTC battery supply voltage
Input high voltage
1.71
V
0.7 × VDD
0.75 × VDD
V
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
V
VIL
Input low voltage
—
—
0.35 × VDD
0.3 × VDD
V
V
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
VIH_E
Input high voltage
0.7 ×
VDDIO_E
—
—
V
V
• 2.7 V ≤ VDDIO_E ≤ 3.6 V
• 1.7 V ≤ VDDIO_E ≤ 2.7 V
0.75 ×
VDDIO_E
VIL_E
Input low voltage
—
—
0.35 ×
VDDIO_E
V
V
• 2.7 V ≤ VDDIO_E ≤ 3.6 V
• 1.7 V ≤ VDDIO_E ≤ 2.7 V
0.3 ×
VDDIO_E
VHYS
Input hysteresis
Input hysteresis
0.06 × VDD
—
—
V
V
VHYS_E
0.06 ×
VDDIO_E
IICIO
I/O pin negative DC injection current — single pin
• VIN < VSS-0.3V
1
-5
—
mA
Table continues on the next page...
Kinetis K80 Sub-Family, Rev. 5, 11/2016
9
NXP Semiconductors
General
Table 1. Voltage and current operating requirements (continued)
Symbol
Description
Min.
Max.
Unit
Notes
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
-25
—
mA
• Negative current injection
VODPU
VRAM
Pseudo Open drain pullup voltage level
VDD voltage required to retain RAM
VDD
1.2
VDD
—
V
V
V
2
VRFVBAT VBAT voltage required to retain the VBAT register file VPOR_VBAT
—
1. All I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD or
VDDIO_E. If VIN is less than -0.3V, a current limiting resistor is required. The negative DC injection current limiting resistor
is calculated as R=(-0.3-VIN)/|IICIO|. The actual resistor value should be an order of magnitude higher to tolerate transient
voltages.
2. Open drain outputs must be pulled to VDD.
2.2.2 HVD, LVD and POR operating requirements
Table 2. VDD supply HVD, LVD and POR operating requirements
Symbol Description
Min.
—
Typ.
3.72
3.46
1.1
Max.
—
Unit
V
Notes
VHVDH
VHVDL
VPOR
High Voltage Detect (High Trip Point)
High Voltage Detect (Low Trip Point)
Falling VDD POR detect voltage
—
—
V
0.8
2.48
1.5
2.64
V
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.56
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
60
—
mV
V
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
40
—
mV
Table continues on the next page...
10
NXP Semiconductors
Kinetis K80 Sub-Family, Rev. 5, 11/2016
General
Table 2. VDD supply HVD, LVD and POR operating requirements (continued)
Symbol Description
Min.
0.97
900
Typ.
1.00
1000
Max.
1.03
Unit
V
Notes
VBG
tLPO
Bandgap voltage reference
Internal low power oscillator period — factory
trimmed
1100
μs
1. Rising threshold is the sum of falling threshold and hysteresis voltage
NOTE
There is no LVD circuit for VDDIO domain
Table 3. VBAT power operating requirements
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VPOR_VBAT Falling VBAT supply POR detect voltage
0.8
1.1
1.5
V
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol Description
Min.
Typ.1
Max.
Unit
Notes
VOH
Output high voltage — normal drive strength
IO Group 1
• 2.7 V ≤ VBAT ≤ 3.6 V, IOH = -5mA
2, 3
VBAT – 0.5
VBAT – 0.5
—
—
—
—
V
V
• 1.71 V ≤ VBAT ≤ 2.7 V, IOH = -2.5mA
IO Groups 2 and 3
—
—
—
—
V
V
VDD – 0.5
VDD – 0.5
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -5mA
IO Group 4
—
—
—
—
V
V
VDDIO_E – 0.5
VDDIO_E – 0.5
• 2.7 V ≤ VDDIO_E ≤ 3.6 V, IOH = -5mA
• 1.71 V ≤ VDDIO_E ≤ 2.7 V, IOH = -2.5mA
Output high voltage — High drive strength
IO Group 3
2
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -20mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -10mA
IO Group 4
VDDIO_E – 0.5
VDDIO_E – 0.5
—
—
—
—
V
V
• 2.7 V ≤ VDDIO_E ≤ 3.6 V, IOH = -15mA
• 1.71 V ≤ VDDIO_E ≤ 2.7 V, IOH = -7.5mA
IOHT
VOL
Output high current total for all ports
Output low voltage — normal drive strength
IO Group 1
—
—
100
mA
2, 4, 5
Table continues on the next page...
Kinetis K80 Sub-Family, Rev. 5, 11/2016
11
NXP Semiconductors
General
Table 4. Voltage and current operating behaviors (continued)
Symbol Description
• 2.7 V ≤ VBAT ≤ 3.6 V, IOL = -5mA
Min.
Typ.1
Max.
Unit
Notes
—
—
0.5
V
• 1.71 V ≤ VBAT ≤ 2.7 V, IOL = -2.5mA
—
—
0.5
V
IO Groups 2 and 3
—
—
—
—
0.5
0.5
V
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = -10mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = -5mA
IO Group 4
—
—
—
—
0.5
0.5
V
V
• 2.7 V ≤ VDDIO_E ≤ 3.6 V, IOL = -5mA
• 1.71 V ≤ VDDIO_E ≤ 2.7 V, IOL = -2.5mA
Output low voltage — High drive strength
IO Group 3
2, 4
—
—
—
—
0.5
0.5
V
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = -20mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = -10mA
IO Group 4
—
—
—
—
0.5
0.5
V
V
• 2.7 V ≤ VDDIO_E ≤ 3.6 V, IOL = -15mA
• 1.71 V ≤ VDDIO_E ≤ 2.7 V, IOL = -7.5mA
IOLT
IIN
Output low current total for all ports
Input leakage current
VDD domain pins
—
—
100
mA
6, 7, 8
—
—
0.002
0.002
0.5
0.5
µA
µA
• VSS ≤ VIN ≤ VDD
PORTE pins
• VSS ≤ VIN ≤ VDDIO_E
—
0.002
0.5
µA
VBAT domain pins
• VSS ≤ VIN ≤ VBAT
RPU
RPD
Internal pullup resistors
Internal pulldown resistors
20
20
—
—
50
50
kΩ
kΩ
9
10
1. Typical values characterized at 25°C and VDD = 3.6V unless otherwise noted.
2. IO Group 1 includes VBAT domain pins: RTC_WAKEUP_b. IO Group 2 includes VDD domain pins: PORTA, PORTB,
PORTC, and PORTD, except PTA4. IO Group 3 includes VDD domain pins: PTB0, PTB1, PTC3, PTC4, PTD4, PTD5,
PTD6, and PTD7. IO Group 4 includes VDDIO_E domain pins: PORTE.
3. PTA4 has lower drive strength: IOH = -5mA for high VDD range; IOH = -2.5mA for low VDD range.
4. Open drain outputs must be pulled to VDD
.
5. PTA4 has lower drive strength: IOL = 5mA for high VDD range; IOL = 2.5mA for low VDD range.
6. VDD domain pins include ADC, CMP, and RESET_b inputs. Measured at VDD = 3.6V.
7. PORTE analog input voltages cannot exceed VDDIO_E supply when VDD ≥ VDDIO_E. PORTE analog input voltages cannot
exceed VDD supply when VDD ˂ VDDIO_E
.
8. VBAT domain pins include EXTAL32, XTAL32, and RTC_WAKEUP_b pins.
9. Measured at minimum supply voltage and VIN = VSS
10. Measured at minimum supply voltage and VIN = VDD
12
Kinetis K80 Sub-Family, Rev. 5, 11/2016
NXP Semiconductors
General
2.2.4 Power mode transition operating behaviors
All specifications except tPOR, and VLLSx –> RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 100MHz
• Bus clock = 50MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
• MCG mode=FEI
Table 5. Power mode transition operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the point
VDD reaches 1.71 V to execution of the first
instruction across the operating temperature range
of the chip.
—
300
µs
—
—
—
—
—
—
—
—
154
154
92
µs
µs
µs
µs
µs
µs
µs
µs
• VLLS0 –> RUN
• VLLS1 –> RUN
• VLLS2 –> RUN
• VLLS3 –> RUN
• LLS2 –> RUN
• LLS3 –> RUN
• VLPS –> RUN
• STOP –> RUN
92
6.3
6.3
5.3
5.3
Table 6. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder.
Measured by entering STOP or VLPS mode
with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KH 32 kHz internal reference clock (IRC) adder.
52
52
52
52
52
52
µA
Measured by entering STOP mode with the
z
32 kHz IRC enabled.
Table continues on the next page...
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13
NXP Semiconductors
General
Table 6. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IEREFSTEN4MH External 4 MHz crystal clock adder.
206
228
237
245
251
258
uA
Measured by entering STOP or VLPS mode
z
with the crystal enabled.
IEREFSTEN32K External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN and
Hz
EREFSTEN] bits. Measured by entering all
modes with the crystal enabled.
nA
440
440
490
490
510
510
22
490
490
490
490
560
560
22
540
540
540
540
560
560
22
560
560
560
560
560
560
22
570
570
570
570
610
610
22
580
580
680
680
680
680
22
VLLS1
VLLS3
LLS2
LLS3
VLPS
STOP
ICMP
CMP peripheral adder measured by placing
the device in VLLS1 mode with CMP
enabled using the 6-bit DAC and a single
external input for compare. Includes 6-bit
DAC power consumption.
µA
nA
IRTC
RTC peripheral adder measured by placing
the device in VLLS1 mode with external 32
kHz crystal enabled by means of the
432
357
388
475
532
810
RTC_CR[OSCE] bit and the RTC ALARM
set for 1 minute. Includes ERCLK32K (32
kHz external crystal) power consumption.
IUART
UART peripheral adder measured by placing
the device in STOP or VLPS mode with
selected clock source waiting for RX data at
115200 baud rate. Includes selected clock
source power consumption.
µA
66
66
66
66
66
66
MCGIRCLK (4 MHz internal reference clock)
OSCERCLK (4 MHz external crystal)
214
45
234
45
246
45
254
45
260
45
268
45
IBG
Bandgap adder when BGEN bit is set and
device is placed in VLPx, LLS, or VLLSx
mode.
µA
µA
IADC
ADC peripheral adder combining the
366
366
366
366
366
366
measured values at VDD and VDDA by placing
the device in STOP or VLPS mode. ADC is
configured for low power mode using the
internal clock and continuous conversions.
14
NXP Semiconductors
Kinetis K80 Sub-Family, Rev. 5, 11/2016
General
2.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
Table 7. Power consumption operating behaviors
Symbol
IDDA
Description
Min.
Typ.
Max.
Unit
Notes
Analog supply current
—
—
See note
mA
1
2
IDD_RUN
Run mode current — all peripheral clocks disabled,
code executing from internal flash @ 3.0V
—
—
28
31.55
50.10
mA
mA
mA
• @ 25°C
39.6
• @ 105°C
IDD_RUN
Run mode current — all peripheral clocks enabled,
code executing from internal flash @ 3.0V
3, 4
—
—
43.30
57.80
46.85
68.30
• @ 25°C
• @ 105°C
IDD_RUNCO Run mode current in compute operation - 120 MHz
core / 24 MHz flash / bus clock disabled, code of
5
while(1) loop executing from internal flash at 3.0 V
—
—
25.1
37.8
28.65
48.30
• @ 25°C
• @ 105°C
IDD_HSRUN Run mode current — all peripheral clocks disabled,
code executing from internal flash @ 3.0V
6
—
—
38
40.70
65.04
mA
mA
• @ 25°C
51.7
• @ 105°C
IDD_HSRUN Run mode current — all peripheral clocks enabled,
code executing from internal flash @ 3.0V
7, 8
—
—
48
50.70
77.04
• @ 25°C
63.7
• @ 105°C
IDD_HSRUNCO HSRun mode current in compute operation – 150 MHz
core/ 25 MHz flash / bus clock disabled, code of
while(1) loop executing from internal flash at 3.0V
mA
—
—
34.5
50.3
37.2
• @ 25°C
• @ 105°C
63.64
IDD_WAIT Wait mode high frequency current at 3.0 V — all
peripheral clocks disabled
9
—
—
14.2
26.2
19.87
35.66
mA
mA
• @ 25°C
• @ 105°C
IDD_WAIT Wait mode reduced frequency current at 3.0 V — all
peripheral clocks enabled
9
—
24.4
30.07
Table continues on the next page...
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NXP Semiconductors
General
Table 7. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
• @ 25°C
—
36.6
46.06
• @ 105°C
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks disabled
10
—
—
0.94
3.99
1.10
7.62
mA
mA
• @ 25°C
• @ 105°C
IDD_VLPR Very-low-power run mode current at 3.0 V — all
peripheral clocks enabled
11
12
—
—
1.36
4.4
1.52
8.03
• @ 25°C
• @ 105°C
IDD_VLPRCO_ Very-low-power run mode current in compute
operation - 4 MHz core / 0.8 MHz flash / bus clock
disabled, LPTMR running with 4 MHz internal
reference clock, CoreMark benchmark code executing
from internal flash at 3.0 V
CM
—
—
1000
3650
—
—
μA
• @ 25°C
• @ 105°C
IDD_PSTOP2 Stop mode current with partial stop 2 clocking option -
core and system disabled / 10.5 MHz bus at 3.0 V
• @ 25°C
5
—
—
3.95
5.75
mA
mA
• @ 105°C
17.71
27.15
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks disabled
13
—
—
0.45
3.28
0.63
6.87
• @ 25°C
• @ 105°C
IDD_VLPW Very-low-power wait mode current at 3.0 V — all
peripheral clocks enabled
• @ 25°C
—
—
0.75
3.6
0.93
7.19
mA
• @ 105°C
IDD_STOP Stop mode current at 3.0 V
—
—
0.55
5.67
0.85
9.59
mA
μA
μA
• @ 25°C
• @ 105°C
IDD_VLPS Very-low-power stop mode current at 3.0 V
—
—
91.48
240.90
• @ 25°C
• @ 105°C
1798.38
3796.94
IDD_LLS2
Low leakage stop mode current at 3.0 V
—
—
4.94
7.14
• @ 25°C
• @ 105°C
73.68
121.9
Table continues on the next page...
16
NXP Semiconductors
Kinetis K80 Sub-Family, Rev. 5, 11/2016
General
Notes
Table 7. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_LLS3
Low leakage stop mode current at 3.0 V
—
—
7.78
13.16
μA
• @ 25°C
• @ 105°C
160.91
284.31
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
—
—
5.63
9.34
μA
μA
μA
μA
• @ 25°C
• @ 105°C
117.89
202.55
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
—
—
3.13
4.04
48.7
• @ 25°C
• @ 105°C
29.49
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
—
—
1.05
1.36
• @ 25°C
• @ 105°C
15.31
18.56
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with
POR detect circuit enabled
—
—
0.62
0.84
• @ 25°C
13.92
16.95
• @ 105°C
IDD_VLLS0 Very low-leakage stop mode 0 current at 3.0 V with
POR detect circuit disabled
—
—
0.33
0.53
μA
μA
μA
• @ 25°C
13.42
16.44
• @ 105°C
IDD_VBAT Average current with RTC and 32kHz disabled at 3.0
V
—
—
0.19
2.56
0.23
3.71
• @ 25°C
• @ 105°C
IDD_VBAT Average current when CPU is not accessing RTC
registers @ 1.8V
14
—
—
0.57
2.52
0.64
5.82
• @ 25°C
• @ 105°C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
3. 120 MHz core and system clock, 60 MHz bus and FlexBus clock, and 24 MHz flash clock. MCG configure for PEE
mode. All peripheral clocks enabled.
4. Max values are measured with CPU executing DSP instructions.
5. MCG configured for PEE mode.
6. 150 MHz core and system clock, 50 MHz bus and FlexBus clock, and 25 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
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17
NXP Semiconductors
General
7. 150 MHz core and system clock, 50 MHz bus and FlexBus clock, and 25 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled.
8. Max values are measured with CPU executing DSP instructions.
9. 120 MHz core and system clock, 60MHz bus clock, and FlexBus. MCG configured for PEE mode.
10. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled. Code executing from flash.
11. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks enabled but peripherals are not in active operation. Code executing from flash.
12. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized
for balanced.
13. 4 MHz core, system, FlexBus, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral
clocks disabled.
14. Includes 32kHz oscillator current and RTC operation.
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFE
• VDD=VDDA=VDDIO_E
18
Kinetis K80 Sub-Family, Rev. 5, 11/2016
NXP Semiconductors
General
Figure 6. Run mode supply current vs. core frequency
Kinetis K80 Sub-Family, Rev. 5, 11/2016
19
NXP Semiconductors
General
Figure 7. VLPR mode supply current vs. core frequency
2.2.6 Electromagnetic Compatibility (EMC) specifications
EMC measurements to IC-level IEC standards are available from NXP on request.
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
• Go to www.nxp.com.
• Perform a keyword search for “EMC design.”
20
Kinetis K80 Sub-Family, Rev. 5, 11/2016
NXP Semiconductors
General
2.2.8 Capacitance attributes
Table 8. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
Input capacitance: analog pins
Input capacitance: digital pins
7
7
pF
pF
CIN_D
—
2.3 Switching specifications
2.3.1 Device clock specifications
Table 9. Device clock specifications
Symbol
fSYS
Description
Min.
Max.
Unit
Notes
High Speed run mode
System and core clock
—
150
MHz
Normal run mode (and High Speed run mode unless otherwise specified above)
fSYS
System and core clock
—
120
—
MHz
MHz
System and core clock when Full Speed USB in
operation
20
fBUS
FB_CLK
fFLASH
Bus clock
—
—
—
—
75
75
28
25
MHz
MHz
MHz
MHz
FlexBus clock
Flash clock
fLPTMR
LPTMR clock
VLPR mode1
System and core clock
Bus clock
fSYS
fBUS
—
—
—
—
—
—
—
—
—
4
4
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
FB_CLK
fFLASH
FlexBus clock
Flash clock
4
1
fERCLK
fLPTMR_pin
External reference clock
LPTMR clock
16
25
8
fFlexCAN_ERCLK FlexCAN external reference clock
fI2S_MCLK
fI2S_BCLK
I2S master clock
I2S bit clock
12.5
4
1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for
any other module.
Kinetis K80 Sub-Family, Rev. 5, 11/2016
21
NXP Semiconductors
General
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
CMT, timers, and I2C signals.
Table 10. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
NMI_b pin interrupt pulse width (analog filter enabled)
— Asynchronous path
100
50
—
—
—
ns
ns
ns
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
3
External RESET_b input pulse width (digital glitch
filter disabled)
100
Port rise and fall time (high drive strength)
• Slew enabled
4, 5
ns
ns
—
—
34
16
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
ns
ns
• Slew disabled
—
—
10
8
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
Port rise and fall time (low drive strength)
• Slew enabled
6, 7
5, 8
7, 8
ns
ns
—
—
34
16
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
ns
ns
• Slew disabled
—
—
7
5
• 1.71 ≤ VDD ≤ 2.7V
• 2.7 ≤ VDD ≤ 3.6V
Port rise and fall time (high drive strength)
• Slew enabled
ns
ns
—
—
34
16
• 1.71 ≤ VDDIO_E ≤ 2.7V
• 2.7 ≤ VDDIO_E ≤ 3.6V
• Slew disabled
ns
ns
—
—
7
5
• 1.71 ≤ VDDIO_E ≤ 2.7V
• 2.7 ≤ VDDIO_E ≤ 3.6V
Port rise and fall time (low drive strength)
• Slew enabled
ns
ns
—
—
34
16
22
NXP Semiconductors
Kinetis K80 Sub-Family, Rev. 5, 11/2016
General
Notes
Table 10. General switching specifications
Symbol
Description
• 1.71 ≤ VDDIO_E ≤ 2.7V
• 2.7 ≤ VDDIO_E ≤ 3.6V
• Slew disabled
Min.
Max.
Unit
ns
—
—
7
5
ns
• 1.71 ≤ VDDIO_E ≤ 2.7V
• 2.7 ≤ VDDIO_E ≤ 3.6V
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry in run modes.
2. The greater synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS,
and VLLSx modes.
4. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6, and PTD7.
5. 75 pF load.
6. Ports A, B, C, and D.
7. 25 pF load.
8. Port E pins only.
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 11. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Notes
Die junction temperature
Ambient temperature
TA
105
°C
1,
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is:
TJ = TA + RθJA x chip power dissipation
2.4.2 Thermal attributes
Table 12. Thermal attributes
Board type
Symbol
RθJA
Description
100 LQFP
121
XFBGA
Unit
°C/W
°C/W
Notes
Single-layer (1S)
Four-layer (2s2p)
Thermal resistance, junction to
ambient (natural convection)
52
39
71
1
1
RθJA
Thermal resistance, junction to
ambient (natural convection)
36.8
Table continues on the next page...
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23
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 12. Thermal attributes (continued)
Board type
Symbol
RθJMA
RθJMA
RθJB
Description
100 LQFP
121
XFBGA
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
Notes
Single-layer (1S)
Thermal resistance, junction to
ambient (200 ft./min. air speed)
42
33
24
11
2
55
1
1
2
3
4
Four-layer (2s2p)
Thermal resistance, junction to
ambient (200 ft./min. air speed)
32.2
18
—
—
—
Thermal resistance, junction to
board
RθJC
Thermal resistance, junction to
case
12.2
0.25
ΨJT
Thermal characterization
parameter, junction to package top
outside center (natural convection)
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air) with the single layer board horizontal. Board meets JESD51-9 specification.
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 Debug trace timing specifications
Table 13. Debug trace operating behaviors
Symbol
Tcyc
Twl
Description
Min.
Max.
Unit
MHz
ns
Clock period
Frequency dependent
Low pulse width
High pulse width
Clock and data rise time
Clock and data fall time
Data setup
2
2
—
—
3
Twh
Tr
ns
—
—
1.5
1.0
ns
Tf
3
ns
Ts
—
—
ns
Th
Data hold
ns
24
NXP Semiconductors
Kinetis K80 Sub-Family, Rev. 5, 11/2016
Peripheral operating requirements and behaviors
TRACECLK
T
r
T
f
T
T
wh
wl
T
cyc
Figure 8. TRACE_CLKOUT specifications
TRACE_CLKOUT
TRACE_D[3:0]
Ts
Th
Ts
Th
Figure 9. Trace data specifications
3.1.2 JTAG electricals
Table 14. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
25
50
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
20
10
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
J4
J5
TCLK rise and fall times
—
20
2.0
—
—
8
3
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
—
—
28
25
—
—
J6
J7
J8
J9
J10
1
Table continues on the next page...
Kinetis K80 Sub-Family, Rev. 5, 11/2016
25
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 14. JTAG limited voltage range electricals (continued)
Symbol
J11
Description
Min.
—
Max.
19
Unit
ns
TCLK low to TDO data valid
TCLK low to TDO high-Z
TRST assert time
J12
—
17
ns
J13
100
8
—
ns
J14
TRST setup time (negation) to TCLK high
—
ns
Table 15. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
20
40
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
25
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
12.5
J4
J5
TCLK rise and fall times
—
20
2.0
—
—
8
3
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
J6
—
J7
30.6
25
J8
J9
—
J10
J11
J12
J13
J14
1.0
—
—
100
8
—
19.0
17.0
—
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
—
J2
J4
J3
J3
TCLK (input)
J4
Figure 10. Test clock input timing
26
NXP Semiconductors
Kinetis K80 Sub-Family, Rev. 5, 11/2016
Peripheral operating requirements and behaviors
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 11. Boundary scan (JTAG) timing
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 12. Test Access Port timing
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NXP Semiconductors
Peripheral operating requirements and behaviors
TCLK
J14
J13
TRST
Figure 13. TRST timing
3.2 Clock modules
3.2.1 MCG specifications
Table 16. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
39.0625
kHz
Iints
Internal reference (slow clock) current
—
—
—
20
32
0.3
—
µA
µs
tirefsts
[O: ] Internal reference (slow clock) startup time
—
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.6
%fdco
1
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
0.2
0.5
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
1
2
1
%fdco
%fdco
1
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
0.5
fintf_ft
fintf_t
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
3
4
—
5
MHz
MHz
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
—
Iintf
Internal reference (fast clock) current
—
—
25
10
—
—
15
—
µA
µs
tirefsts
floc_low
[L: ] Internal reference startup time (fast clock)
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
kHz
ext clk freq: above (3/5)fint never reset
Table continues on the next page...
28
NXP Semiconductors
Kinetis K80 Sub-Family, Rev. 5, 11/2016
Peripheral operating requirements and behaviors
Table 16. MCG specifications (continued)
Symbol Description
ext clk freq: between (2/5)fint and (3/5)fint maybe
Min.
Typ.
Max.
Unit
Notes
reset (phase dependency)
ext clk freq: below (2/5)fint always reset
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
ext clk freq: above (16/5)fint never reset
ext clk freq: between (15/5)fint and (16/5)fint
maybe reset (phase dependency)
ext clk freq: below (15/5)fint always reset
FLL
ffll_ref
FLL reference frequency range
31.25
16.0
—
39.0625
26.66
kHz
fdco_ut
DCO output
Low range
23.04
MHz
2
frequency range
— untrimmed
(DRS=00, DMX32=0)
640 × fints_ut
Mid range
32.0
48.0
46.08
69.12
92.16
26.35
52.70
79.09
105.44
53.32
79.99
106.65
30.50
60.99
91.53
122.02
(DRS=01, DMX32=0)
1280 × fints_ut
Mid-high range
(DRS=10, DMX32=0)
1920 × fints_ut
High range
64.0
(DRS=11, DMX32=0)
2560 × fints_ut
Low range
18.3
(DRS=00, DMX32=1)
732 × fints_ut
Mid range
36.6
(DRS=01, DMX32=1)
1464 × fints_ut
Mid-high range
(DRS=10, DMX32=1)
2197 × fints_ut
54.93
73.23
High range
(DRS=11, DMX32=1)
2929 × fints_ut
fdco
DCO output
frequency range
Low range (DRS=00)
640 × ffll_ref
20
40
20.97
41.94
25
50
MHz
MHz
3, 4
Mid range (DRS=01)
Table continues on the next page...
Kinetis K80 Sub-Family, Rev. 5, 11/2016
29
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 16. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
1280 × ffll_ref
Mid-high range (DRS=10)
1920 × ffll_ref
60
62.91
75
MHz
High range (DRS=11)
2560 × ffll_ref
80
—
—
—
—
83.89
23.99
47.97
71.99
95.98
100
—
MHz
MHz
MHz
MHz
MHz
ps
fdco_t_DMX3 DCO output
Low range (DRS=00)
732 × ffll_ref
5, 6
frequency
2
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
2197 × ffll_ref
—
High range (DRS=11)
2929 × ffll_ref
—
Jcyc_fll
FLL period jitter
—
—
180
150
—
—
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
7
PLL
fpll_ref
PLL reference frequency range
8
180
90
90
—
—
—
16
360
180
180
—
MHz
MHz
fvcoclk_2x VCO output frequency
fvcoclk
PLL output frequency
—
—
MHz
MHz
fvcoclk_90 PLL quadrature output frequency
Ipll
PLL operating current
8
8
9
1.1
2
mA
mA
• VCO @ 176 MHz (fpll_ref = 8 MHz, VDIV
multiplier = 22, PRDIV divide=1)
Ipll
PLL operating current
—
—
• VCO @ 360 MHz (fpll_ref = 8 MHz, VDIV
multiplier = 45, PRDIV divide=1)
Jcyc_pll
PLL period jitter (RMS)
• fvco = 180 MHz
—
—
100
75
—
—
ps
ps
• fvco = 360 MHz
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
• fvco = 180 MHz
9
—
—
600
300
—
—
ps
ps
• fvco = 360 MHz
Dunl
Lock exit frequency tolerance
Lock detector detection time
4.47
—
—
—
5.97
150 × 10-6
+ 1075(1/
%
s
tpll_lock
10
fpll_ref
)
30
NXP Semiconductors
Kinetis K80 Sub-Family, Rev. 5, 11/2016
Peripheral operating requirements and behaviors
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. This applies when SCTRIM at value (0x80) and SCFTRIM control bit at value (0x0).
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8. Excludes any oscillator currents that are also consuming power while PLL is in operation.
9. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
3.2.2 IRC48M specifications
Table 17. IRC48M specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
—
Unit
V
Notes
Supply voltage
IDD48M
firc48m
Supply current
520
48
μA
Internal reference frequency
—
—
MHz
Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at
low voltage (VDD=1.71V-1.89V) over temperature
• Regulator disable
—
—
0.5
0.5
1.0
1.5
%firc48m
(USB_CLK_RECOVER_IRC_EN[REG_EN]=0)
• Regulator enable
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over temperature
• Regulator enable
—
—
0.5
—
1.0
0.1
%firc48m
(USB_CLK_RECOVER_IRC_EN[REG_EN]=1)
Δfirc48m_cl Closed loop total deviation of IRC48M frequency
%fhost
1
2
over voltage and temperature
Jcyc_irc48m Period Jitter (RMS)
—
—
35
2
150
3
ps
μs
tirc48mst
Startup time
1. Closed loop operation of the IRC48M is only feasible for USB device operation; it is not usable for USB host operation.
It is enabled by configuring for USB Device, selecting IRC48M as USB clock source, and enabling the clock recover
function (USB_CLK_RECOVER_IRC_CTRL[CLOCK_RECOVER_EN]=1,
USB_CLK_RECOVER_IRC_EN[IRC_EN]=1).
2. IRC48M startup time is defined as the time between clock enablement and clock availability for system use. Enable
the clock by one of the following settings:
• USB_CLK_RECOVER_IRC_EN[IRC_EN]=1, or
• MCG_C7[OSCSEL]=10, or
• SIM_SOPT2[PLLFLLSEL]=11
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NXP Semiconductors
Peripheral operating requirements and behaviors
3.2.3 Oscillator electrical specifications
3.2.3.1 Oscillator DC electrical specifications
Table 18. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
600
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
7.5
500
650
2.5
3.25
4
—
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain
mode (HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
Table continues on the next page...
32
NXP Semiconductors
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Peripheral operating requirements and behaviors
Table 18. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
—
0
—
kΩ
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
—
—
—
0.6
VDD
0.6
—
—
—
—
V
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C, Internal capacitance = 20 pf
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.2.3.2 Oscillator frequency specifications
Table 19. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
fosc_hi_1 Oscillator crystal or resonator frequency —
high-frequency mode (low range)
3
8
—
—
8
MHz
MHz
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency —
high frequency mode (high range)
(MCG_C2[RANGE]=1x)
32
tdc_extal Input clock duty cycle (external clock mode)
40
—
50
60
—
%
tcst
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
1, 2
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Proper PC board layout procedures must be followed to achieve specifications.
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33
NXP Semiconductors
Peripheral operating requirements and behaviors
2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
3.2.4 32 kHz oscillator electrical characteristics
3.2.4.1 32 kHz oscillator DC electrical specifications
Table 20. 32kHz oscillator DC electrical specifications
Symbol
VBAT
RF
Description
Min.
1.71
—
Typ.
—
Max.
3.6
—
Unit
V
Supply voltage
Internal feedback resistor
100
5
MΩ
pF
Cpara
Parasitical capacitance of EXTAL32 and
XTAL32
—
7
1
Vpp
Peak-to-peak amplitude of oscillation
—
0.6
—
V
1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to
required oscillator components and must not be connected to any other devices.
3.2.4.2 32 kHz oscillator frequency specifications
Table 21. 32 kHz oscillator frequency specifications
Symbol Description
Min.
—
Typ.
32.768
1000
32.768
—
Max.
—
Unit
kHz
ms
Notes
fosc_lo
tstart
Oscillator crystal
Crystal start-up time
—
—
1
2
fec_extal32 Externally provided input clock frequency
vec_extal32 Externally provided input clock amplitude
—
—
kHz
mV
700
VBAT
2, 3
1. Proper PC board layout procedures must be followed to achieve specifications.
2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The
oscillator remains enabled and XTAL32 must be left unconnected.
3. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VBAT
.
3.3 Memories and memory interfaces
34
Kinetis K80 Sub-Family, Rev. 5, 11/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
3.3.1 QuadSPI AC specifications
• All data is based on a negative edge data launch from the device and a positive
edge data capture, as shown in the timing diagrams in this section.
• Measurements are with a load of 15pf (1.8V) and 35pf (3V) on output pins. Input
slew: 1ns
• Timings assume a setting of 0x0000_000x for QuadSPI _SMPR register (see the
reference manual for details).
The following table lists the QuadSPI delay chain read/write settings. Refer the device
reference manual for register and bit descriptions.
Table 22. QuadSPI delay chain read/write settings
Mode
QuadSPI registers
Notes
QuadSPI_MCR[DQ QuadSPI_SOCCR[ QuadSPI_MCR[SC QuadSPI_FLSHC
S_EN]
SOCCFG]
LKCFG]
R[TDH]
SDR
DDR
Yes
3Fh
5
No
Delay of 63
buffer and 64
mux
Yes
3Fh
0h
1
2
2
Delay of 63
buffer and 64
mux
Hyperflash
RDS driven from
Flash
No
Delay of 1 mux
SDR mode
1
2
3
Clock
SFCK
CS
Tck
Tcss
Tcsh
Tis
Tih
Data in
Figure 14. QuadSPI input timing (SDR mode) diagram
NOTE
• The below timing values are with default settings for
sampling registers like QuadSPI_SMPR.
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35
NXP Semiconductors
Peripheral operating requirements and behaviors
• A negative time indicates the actual capture edge inside
the device is earlier than clock appearing at pad.
• The below timing are for a load of 15pf (1.8V) and 35pf
(3V) or output pads
• All board delays need to be added appropriately
• Input hold time being negative does not have any
implication or max achievable frequency
Table 23. QuadSPI input timing (SDR mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
Tis
Tih
Setup time for incoming data
4
-
-
ns
ns
Hold time requirement for incoming data
1.5
1
2
3
Clock
SFCK
CS
Tck
Tcss
Tcsh
Toh
Tov
Data out
Figure 15. QuadSPI output timing (SDR mode) diagram
Table 24. QuadSPI output timing (SDR mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
Tov
Output Data Valid
Output Data Hold
SCK clock period
-
2.8
ns
Toh
Tck
-1.4
-
-
ns
100
MHz
ns
Tcss
Tcsh
Chip select output setup time
Chip select output hold time
2
-
-
-1
ns
NOTE
For any frequency setup and hold specifications of the
memory should be met.
36
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NXP Semiconductors
Peripheral operating requirements and behaviors
DDR Mode
1
2
3
Clock
SFCK
CS
Tck
Tcss
Tcsh
Tih
Tis
Data in
Figure 16. QuadSPI input timing (DDR mode) diagram
NOTE
• Numbers are for a load of 15pf (1.8V) and 35pf (3V)
• The numbers are for setting of hold condition in register
QuadSPI_SMPR[DDRSNP]
Table 25. QuadSPI input timing (DDR mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
Tis
Setup time for incoming data
4 (Without -
learning)
ns
ns
1 (With
learning)
Tih
Hold time requirement for incoming data
1.5
-
1
2
3
Clock
SFCK
CS
Tck
Tcss
Tcsh
Tov
Toh
Data out
Figure 17. QuadSPI output timing (DDR mode) diagram
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37
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 26. QuadSPI output timing (DDR mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
Tov
Toh
Tck
Output Data Valid
Output Data Hold
SCK clock period
-
4.5
ns
1.5
-
-
ns
75 (with learning)
MHz
-
45 (without learning)
Tcss
Tcsh
Chip select output setup time
Chip select output hold time
2
-
-
Clk(sck)
Clk(sck)
-1
Hyperflash mode
RDS
TsMIN
ThMIN
DI[7:0]
Figure 18. QuadSPI input timing (Hyperflash mode) diagram
Table 27. QuadSPI input timing (Hyperflash mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
TsMIN
ThMIN
Setup time for incoming data
2
2
-
-
ns
ns
Hold time requirement for incoming data
38
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NXP Semiconductors
Peripheral operating requirements and behaviors
CK
CK 2
TclkSKMAX
TclkSKMIN
THO
TDVO
Output Invalid Data
Figure 19. QuadSPI output timing (Hyperflash mode) diagram
Table 28. QuadSPI output timing (Hyperflash mode) specifications
Symbol
Parameter
Value
Unit
Min
Max
TdvMAX
Tho
Output Data Valid
Output Data Hold
-
4.3
-
ns
ns
1.3
-
TclkSKMAX
TclkSKMIN
Ck to Ck2 skew max
Ck to Ck2 skew min
T/4 + 0.5 ns
- ns
T/4 - 0.5
NOTE
Maximum clock frequency = 75 MHz.
3.3.2 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.3.2.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 29. NVM program/erase timing specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
thvpgm4 Longword Program high-voltage time
—
7.5
18
μs
—
Table continues on the next page...
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39
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 29. NVM program/erase timing specifications (continued)
Symbol Description
Min.
—
Typ.
13
Max.
113
Unit
ms
Notes
thversscr Sector Erase high-voltage time
1
1
thversall
Erase All high-voltage time
—
208
1808
ms
1. Maximum time based on expectations at cycling end-of-life.
3.3.2.2 Flash timing specifications — commands
Table 30. Flash command timing specifications
Symbol Description
Min.
—
—
—
—
—
—
—
—
—
—
Typ.
—
Max.
60
Unit
Notes
trd1sec4k Read 1s Section execution time (flash sector)
μs
μs
μs
μs
ms
ms
μs
μs
ms
μs
1
1
tpgmchk
trdrsrc
tpgm4
Program Check execution time
Read Resource execution time
Program Longword execution time
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
45
—
30
1
65
145
114
0.9
30
—
2
tersscr
trd1all
14
—
1
trdonce
—
1
tpgmonce Program Once execution time
100
280
—
—
—
2
tersall
Erase All Blocks execution time
2100
30
tvfykey
Verify Backdoor Access Key execution time
1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.3.2.3 Flash high voltage current behaviors
Table 31. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
3.3.2.4 Reliability specifications
Table 32. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
5
50
—
years
—
Table continues on the next page...
40
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NXP Semiconductors
Peripheral operating requirements and behaviors
Table 32. NVM reliability specifications (continued)
Symbol Description
Min.
20
Typ.1
Max.
—
Unit
years
cycles
Notes
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
100
—
2
10 K
50 K
—
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ °C.
3.3.3 Flexbus switching specifications
All processor bus timings are synchronous; input setup/hold and output delay are
given in respect to the rising edge of a reference clock, FB_CLK. The FB_CLK
frequency may be the same as the internal system bus frequency or an integer divider
of that frequency.
The following timing numbers indicate when data is latched or driven onto the
external bus, relative to the Flexbus output clock (FB_CLK). All other timing
relationships can be derived from these values.
Table 33. Flexbus limited voltage range switching specifications
Num
Description
Min.
Max.
3.6
Unit
V
Notes
Operating voltage
2.7
Frequency of operation
Clock period
—
FB_CLK
—
MHz
ns
FB1
FB2
FB3
FB4
FB5
1/FB_CLK
Address, data, and control output valid
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
—
1.0
6
11.8
—
ns
ns
1
2
—
ns
0.0
—
ns
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0],
FB_ALE, and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Table 34. Flexbus full voltage range switching specifications
Num
Description
Min.
1.71
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
Clock period
—
FB_CLK
—
MHz
ns
FB1
FB2
1/FB_CLK
—
Address, data, and control output valid
12.6
ns
Table continues on the next page...
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NXP Semiconductors
Peripheral operating requirements and behaviors
Table 34. Flexbus full voltage range switching specifications (continued)
Num
FB3
FB4
FB5
Description
Min.
1.0
12.5
0
Max.
—
Unit
ns
Notes
Address, data, and control output hold
Data and FB_TA input setup
Data and FB_TA input hold
1
—
ns
—
ns
2
1. Specification is valid for all FB_AD[31:0], FB_BE/BWEn, FB_CSn, FB_OE, FB_R/W,FB_TBST, FB_TSIZ[1:0], FB_ALE,
and FB_TS.
2. Specification is valid for all FB_AD[31:0] and FB_TA.
Read Timing Parameters
S0
S1
S2
S3
S0
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB5
FB3
Address
FB4
FB2
Address
Data
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
S1
S0
S2
S3
S0
Figure 20. FlexBus read timing diagram
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Peripheral operating requirements and behaviors
Write Timing Parameters
FB1
FB_CLK
FB_A[Y]
FB_D[X]
FB_RW
FB2
FB3
Address
Address
Data
FB_TS
FB_ALE
FB_CSn
FB_OEn
FB_BEn
FB_TA
AA=1
AA=0
FB4
FB5
AA=1
AA=0
FB_TSIZ[1:0]
TSIZ
Figure 21. FlexBus write timing diagram
3.3.4 SDRAM controller specifications
The figure below shows SDRAM read cycle.
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Peripheral operating requirements and behaviors
0
1
2
3
4
5
6
7
8
9
10
11
12
13
D0
CLKOUT
D3
D1
Row
Column
A[23:0]
D4
SRAS
SCAS
D2
1
D4
DRAMW
D[31:0]
D5
D6
D4
SDRAM_CS[1:0]
BS[3:0]
NOP
ACTV
NOP
READ
PRE
1
DACR[CASL] = 2
Figure 22. SDRAM read timing diagram
Table 35. SDRAM Timing (Full voltage range)
NUM
Characteristic 1
Symbol
1.71
MIn
Max
Unit
Operating voltage
3.6
V
Frequency of operation
—
CLKOUT
MHz
D0
D1
D2
D3
D4
D5
D6
D73
D83
Clock period
1/CLKOUT
tCHDAV
tCHDCV
tCHDAI
—
-
ns
2
CLKOUT high to SDRAM address valid
CLKOUT high to SDRAM control valid
CLKOUT high to SDRAM address invalid
CLKOUT high to SDRAM control invalid
SDRAM data valid to CLKOUT high
CLKOUT high to SDRAM data invalid
CLKOUT high to SDRAM data valid
CLKOUT high to SDRAM data invalid
11.2
ns
ns
ns
ns
ns
ns
ns
ns
11.1
1.0
1.0
12.0
1.0
-
-
tCHDCI
-
tDDVCH
tCHDDI
tCHDDVW
tCHDDIW
-
-
12.0
-
1.0
1. All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
2. CLKOUT is same as FB_CLK, maximum frequency can be 75 MHz
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Peripheral operating requirements and behaviors
3. D7 and D8 are for write cycles only.
Table 36. SDRAM Timing (Limited voltage range)
NUM
Characteristic 1
Symbol
2.7
MIn
3.6
Max
Unit
Operating voltage
V
Frequency of operation
—
1/CLKOUT
tCHDAV
tCHDCV
tCHDAI
CLKOUT
MHz
D0
D1
D2
D3
D4
D5
D6
D73
D83
Clock period
—
-
ns
2
CLKOUT high to SDRAM address valid
CLKOUT high to SDRAM control valid
CLKOUT high to SDRAM address invalid
CLKOUT high to SDRAM control invalid
SDRAM data valid to CLKOUT high
CLKOUT high to SDRAM data invalid
CLKOUT high to SDRAM data valid
CLKOUT high to SDRAM data invalid
11.1
ns
ns
ns
ns
ns
ns
ns
ns
11.1
1.0
1.0
7.3
1.0
-
-
tCHDCI
-
tDDVCH
tCHDDI
tCHDDVW
tCHDDIW
-
-
11.1
-
1.0
1. All timing specifications are based on taking into account, a 25pF load on the SDRAM output pins.
2. CLKOUT is same as FB_CLK, maximum frequency can be 75 MHz
3. D7 and D8 are for write cycles only.
Following figure shows an SDRAM write cycle.
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Peripheral operating requirements and behaviors
0
1
2
3
4
5
6
7
8
9
10
11
12
D0
CLKOUT
D3
D1
Row
Column
A[23:0]
SRAS
D2
1
SCAS
D4
DRAMW
D[31:0]
D7
D8
D4
SDRAM_CS[1:0]
D4
D2
BS[3:0]
D4
ACTV
NOP
WRITE
NOP
PALL
1
DACR[CASL] = 2
Figure 23. SDRAM write timing diagram
3.4 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.5 Analog
3.5.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 37 and Table 38 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
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Peripheral operating requirements and behaviors
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
3.5.1.1 ADC operating conditions
Table 37. ADC operating conditions
Symbol Description
VDDA Supply voltage
ΔVDDA Supply voltage
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
Absolute
—
Delta to VDD (VDD – VDDA
)
0
+100
+100
VDDA
mV
mV
V
2
2
ΔVSSA
Ground voltage Delta to VSS (VSS – VSSA
)
0
VREFH
ADC reference
voltage high
VDDA
VREFL
VADIN
ADC reference
voltage low
VSSA
VSSA
VSSA
V
V
Input voltage
• 16-bit differential mode
• All other modes
VREFL
VREFL
—
—
—
4
31/32 ×
VREFH
VREFH
5
CADIN
Input
capacitance
• 8-bit / 10-bit / 12-bit
modes
pF
kΩ
RADIN
RAS
Input series
resistance
—
2
5
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
3
—
—
—
5
kΩ
fADCK
Crate
ADC conversion ≤ 13-bit mode
clock frequency
1.0
18.0
MHz
4
5
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
20.000
—
818.330
ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
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NXP Semiconductors
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 24. ADC input impedance equivalency diagram
3.5.1.2 ADC electrical characteristics
Table 38. ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
6.1
7.3
9.5
Unit
Notes
IDDA_ADC Supply current
—
mA
3
ADC asynchronous
clock source
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
2.4
4.0
5.2
6.2
MHz
MHz
MHz
MHz
tADACK = 1/
fADACK
2.4
fADACK
3.0
4.4
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
0.7
0.2
–1.1 to
+1.9
–0.3 to
0.5
INL
Integral non-linearity
• 12-bit modes
—
1.0
–2.7 to
+1.9
LSB4
5
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 38. ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
—
0.5
–0.7 to
+0.5
• <12-bit modes
5
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• ≤13-bit modes
—
—
—
–4
–1.4
—
–5.4
–1.8
0.5
LSB4
LSB4
VADIN = VDDA
Quantization error
ENOB Effective number of 16-bit differential mode
6
bits
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg = 32
• Avg = 4
16-bit single-ended mode
• Avg = 32
12.2
11.4
13.9
13.1
—
—
bits
bits
dB
• Avg = 4
THD
Total harmonic
distortion
16-bit differential mode
• Avg = 32
7
7
—
—
-94
-85
—
—
dB
16-bit single-ended mode
• Avg = 32
SFDR Spurious free
dynamic range
16-bit differential mode
• Avg = 32
—
—
dB
dB
82
78
95
90
16-bit single-ended mode
• Avg = 32
EIL
Input leakage error
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
Temp sensor slope Across the full temperature
range of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
8
VTEMP25 Temp sensor voltage 25 °C
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
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Peripheral operating requirements and behaviors
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
12.30
12.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 25. Typical ENOB vs. ADC_CLK for 16-bit differential mode
3.5.2 CMP and 6-bit DAC electrical specifications
Table 39. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
VDD – 0.5
—
—
—
0.5
200
600
40
V
V
Output low
—
20
80
—
—
Propagation delay, high-speed mode (EN=1, PMODE=1)
Propagation delay, low-speed mode (EN=1, PMODE=0)
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
50
250
—
ns
ns
μs
μA
tDLS
IDAC6b
7
—
Table continues on the next page...
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NXP Semiconductors
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Peripheral operating requirements and behaviors
Table 39. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
INL
Description
Min.
–0.5
–0.3
Typ.
—
Max.
0.5
Unit
LSB3
LSB
6-bit DAC integral non-linearity
6-bit DAC differential non-linearity
DNL
—
0.3
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
0.06
HYSTCTR
Setting
0.05
0.04
0.03
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 26. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 27. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.5.3 12-bit DAC electrical characteristics
3.5.3.1 12-bit DAC operating requirements
Table 40. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
CL
Desciption
Min.
Max.
3.6
3.6
100
1
Unit
V
Notes
Supply voltage
Reference voltage
Output load capacitance
Output load current
1.13
—
V
1
2
pF
mA
IL
—
1. The DAC reference can be selected to be VDDA or VREFH
.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
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Peripheral operating requirements and behaviors
3.5.3.2 12-bit DAC operating behaviors
Table 41. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
150
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
100
15
700
200
30
μA
μs
μs
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-
speed mode
0.7
1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
—
—
—
—
—
—
100
mV
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
VDACR
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR > 2
V
Differential non-linearity error — VDACR
VREF_OUT
=
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
AC
Temperature coefficient offset voltage
Temperature coefficient gain error
Offset aging coefficient
3.7
—
μV/C
%FSR/C
μV/yr
Ω
6
0.000421
—
—
100
250
Rop
SR
Output resistance (load = 3 kΩ)
Slew rate -80h→ F7Fh→ 80h
—
V/μs
• High power (SPHP
• Low power (SPLP
)
1.2
1.7
—
—
)
0.05
0.12
CT
Channel to channel cross talk
3dB bandwidth
—
—
-80
dB
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
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Peripheral operating requirements and behaviors
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
8
6
4
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 28. Typical INL error vs. digital code
54
NXP Semiconductors
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Peripheral operating requirements and behaviors
1.499
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
85
25
105
125
-40
Temperature °C
Figure 29. Offset at half scale vs. temperature
3.5.4 Voltage reference electrical specifications
Table 42. VREF full-range operating requirements
Symbol
VDDA
TA
Description
Supply voltage
Temperature
Min.
Max.
Unit
Notes
3.6
V
Operating temperature
range of the device
°C
CL
Output load capacitance
100
nF
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
range of the device.
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Peripheral operating requirements and behaviors
Table 43. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.1915
1.195
1.1977
V
1
nominal VDDA and temperature=25C
Voltage reference output — factory trim
Voltage reference output — user trim
Voltage reference trim step
Vout
Vout
1.1584
1.193
—
—
—
1.2376
1.197
—
V
V
1
1
1
1
Vstep
Vtdrift
0.5
—
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range)
—
80
Ibg
Ilp
Bandgap only current
—
—
—
—
—
—
80
360
1
µA
uA
mA
µV
1
1
Low-power buffer current
High-power buffer current
Ihp
1
ΔVLOAD Load regulation
• current = 1.0 mA
1, 2
—
200
—
Tstup
Buffer startup time
—
—
—
—
100
35
µs
Tchop_osc_st Internal bandgap start-up delay with chop
ms
—
1
oscillator enabled
up
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
—
2
—
mV
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 44. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
50
°C
Table 45. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim
1.173
1.225
V
3.6 Timers
See General switching specifications.
3.7 Communication interfaces
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Peripheral operating requirements and behaviors
3.7.1 EMV SIM specifications
Each EMV SIM module interface consists of a total of five pins.
The interface is designed to be used with synchronous Smart cards, meaning the EMV
SIM module provides the clock used by the Smart card. The clock frequency is
typically 372 times the Tx/Rx data rate; however, the EMV SIM module can also
work with CLK frequencies of 16 times the Tx/Rx data rate.
There is no timing relationship between the clock and the data. The clock that the
EMV SIM module provides to the Smart card is used by the Smart card to recover the
clock from the data in the same manner as standard UART data exchanges. All five
signals of the EMV SIM module are asynchronous with each other.
There are no required timing relationships between signals in normal mode. The smart
card is initiated by the interface device; the Smart card responds with Answer to
Reset. Although the EMV SIM interface has no defined requirements, the ISO/IEC
7816 defines reset and power-down sequences (for detailed information see ISO/IEC
7816).
SI10
EMVSIMn_PD
EMVSIMn_RST
SI7
EMVSIMn_CLK
SI8
EMVSIMn_IO
SI9
EMVSIMn_VCCEN
Figure 30. EMV SIM Clock Timing Diagram
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The following table defines the general timing requirements for the EMV SIM
interface.
Table 46. Timing Specifications, High Drive Strength
ID
Parameter
Symbol
Min
Max
Unit
MHz
SI EMV SIM clock frequency (EMVSIMn_CLK)1
1
SI EMV SIM clock rise time (EMVSIMn_CLK)2
2
SI EMV SIM clock fall time (EMVSIMn_CLK)2
3
Sfreq
Srise
Sfall
1
5
—
—
20
—
—
0.09 × (1/Sfreq)
ns
ns
ns
ns
ns
0.09 × (1/Sfreq)
SI EMV SIM input transition time (EMVSIMn_IO,
4
Si EMV SIM I/O rise time / fall time (EMVSIMn_IO)3
5
Si EMV SIM RST rise time / fall time (EMVSIMn_RST)4
6
Stran
Tr/Tf
Tr/Tf
25
1
EMVSIMn_PD)
1
1. 50% duty cycle clock,
2. With C = 50 pF
3. With Cin = 30 pF, Cout = 30 pF,
4. With Cin = 30 pF,
3.7.1.1 EMV SIM Reset Sequences
Smart cards may have internal reset, or active low reset. The following subset describes
the reset sequences in these two cases.
3.7.1.1.1 Smart Cards with Internal Reset
Following figure shows the reset sequence for Smart cards with internal reset. The reset
sequence comprises the following steps:
• After power-up, the clock signal is enabled on EMVSIMn_CLK (time T0)
• After 200 clock cycles, EMVSIMn_IO must be asserted.
• The card must send a response on EMVSIMn_IO acknowledging the reset between
400–40000 clock cycles after T0.
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EMVSIMn_VCCEN
EMVSIMn_CLK
EMVSIMn_IO
RESPONSE
1
2
T0
Figure 31. Internal Reset Card Reset Sequence
The following table defines the general timing requirements for the SIM interface.
Table 47. Timing Specifications, Internal Reset Card Reset Sequence
Ref
Min
Max
Units
1
—
200
EMVSIMx_CLK
clock cycles
2
400
40,000
EMVSIMx_CLK
clock cycles
3.7.1.1.2 Smart Cards with Active Low Reset
Following figure shows the reset sequence for Smart cards with active low reset. The
reset sequence comprises the following steps::
• After power-up, the clock signal is enabled on EMVSIMn_CLK (time T0)
• After 200 clock cycles, EMVSIMn_IO must be asserted.
• EMVSIMn_RST must remain low for at least 40,000 clock cycles after T0 (no
response is to be received on RX during those 40,000 clock cycles)
• EMVSIMn_RST is asserted (at time T1)
• EMVSIMn_RST must remain asserted for at least 40,000 clock cycles after T1,
and a response must be received on EMVSIMn_IO between 400 and 40,000 clock
cycles after T1.
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EMVSIMn_VCCEN
EMVSIMn_RST
EMVSIMn_CLK
RESPONSE
EMVSIMn_IO
2
1
3
3
T0
T1
Figure 32. Active-Low-Reset Smart Card Reset Sequence
The following table defines the general timing requirements for the EMVSIM
interface..
Table 48. Timing Specifications, Internal Reset Card Reset Sequence
Ref No
Min
—
Max
200
Units
1
2
3
EMVSIMx_CLK clock cycles
EMVSIMx_CLK clock cycles
EMVSIMx_CLK clock cycles
400
40,000
—
40,000
3.7.1.2 EMVSIM Power-Down Sequence
Following figure shows the EMV SIM interface power-down AC timing diagram.Table
49 table shows the timing requirements for parameters (SI7–SI10) shown in the figure.
The power-down sequence for the EMV SIM interface is as follows:
• EMVSIMn_SIMPD port detects the removal of the Smart Card
• EMVSIMn_RST is negated
• EMVSIMn_CLK is negated
• EMVSIM_IO is negated
• EMVSIMx_VCCENy is negated
Each of the above steps requires one Frtcclk period (usually 32 kHz and selected by
SIM_SOPT1[OSC32KSEL]). Power-down may be initiated by a Smart card removal
detection; or it may be launched by the processor.
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SI10
EMVSIMn_PD
EMVSIMn_RST
SI7
EMVSIMn_CLK
EMVSIMn_IO
SI8
SI9
EMVSIMn_VCCEN
Figure 33. Smart Card Interface Power Down AC Timing
Table 49. Timing Requirements for Power-down Sequence
Ref No
Parameter
Symbol
Min
Max
Units
SI7
EMVSIM reset to SIM clock stop Srst2clk
0.9 × 1/
Frtcclk1
1.1 × 1/Frtcclk
μs
SI8
SI9
EMVSIM reset to SIM Tx data
low
Srst2dat
Srst2ven
Spd2rst
1.8 × 1/
Frtcclk
2.2 × 1/Frtcclk
3.3 × 1/Frtcclk
1.1 × 1/Frtcclk
μs
μs
μs
EMVSIM reset to SIM voltage
enable low
2.7 × 1/
Frtcclk
SI10
EMVSIM presence detect to
SIM reset low
0.9 × 1/
Frtcclk
1. Frtcclk is ERCLK32K, and this clock must be enabled during the power down sequence.
NOTE
Same timing is also followed when auto power down is
initiated. See Reference Manual for reference.
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3.7.2 USB VREG electrical specifications
Table 50. USB VREG electrical specifications
Symbol Description
Min.
2.7
—
Typ.1
Max.
5.5
Unit
V
Notes
VREGIN Input supply voltage
—
IDDon
IDDstby
IDDoff
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
125
186
μA
Quiescent current — Standby mode, load
current equal zero
—
1.1
10
μA
Quiescent current — Shutdown mode
—
—
650
—
—
4
nA
μA
• VREGIN = 5.0 V and temperature=25 °C
• Across operating voltage and temperature
ILOADrun Maximum load current — Run mode
ILOADstby Maximum load current — Standby mode
—
—
—
—
120
1
mA
mA
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
3
3.3
2.8
—
3.6
3.6
3.6
V
V
V
• Standby mode
2.1
2.1
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2
COUT
ESR
External output capacitor
1.76
1
2.2
—
8.16
100
μF
External output capacitor equivalent series
resistance
mΩ
ILIM
Short circuit current
—
290
—
mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad
.
3.7.3 USB DCD electrical specifications
Table 51. USB DCD electrical specifications
Symbol
VDP_SRC
Description
Min.
Typ.
Max.
Unit
,
USB_DP and USB_DM source voltages (up to 250
0.5
—
0.7
V
VDM_SRC μA)
VLGC
IDP_SRC
IDM_SINK
Threshold voltage for logic high
0.8
7
—
10
2.0
13
V
USB_DP source current
μA
μA
,
USB_DM and USB_DP sink currents
50
100
150
IDP_SINK
RDM_DWN D- pulldown resistance for data pin contact detect
VDAT_REF Data detect voltage
14.25
0.25
—
24.8
0.4
kΩ
V
0.33
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3.7.4 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 52. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
30
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
(tBUS x 2) −
2
—
ns
1
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
1.0
15.8
0
15.0
—
ns
ns
ns
ns
—
—
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 34. DSPI classic SPI timing — master mode
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Table 53. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
Frequency of operation
—
15 1
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
23.0
—
ns
ns
2.7
7.0
—
—
—
ns
—
ns
13
13
ns
ns
1. The maximum operating frequency is measured with non-continuous CS and SCK. When DSPI is configured with
continuous CS and SCK, there is a constraint that SPI clock should not be greater than 1/6 of bus clock, for example,
when bus clock is 60MHz, SPI clock should not be greater than 10MHz.
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 35. DSPI classic SPI timing — slave mode
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3.7.5 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 54. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
15
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
4 x tBUS
—
(tSCK/2) - 4 (tSCK/2) + 4
ns
(tBUS x 2) −
4
—
ns
2
3
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
1.0
19.1
0
16
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 36. DSPI classic SPI timing — master mode
Table 55. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Table continues on the next page...
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Table 55. Slave mode DSPI timing (full voltage range) (continued)
Num
Description
Min.
Max.
7.5
Unit
MHz
ns
Frequency of operation
—
DS9
DSPI_SCK input cycle time
8 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
23.1
—
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
ns
ns
2.6
7.0
—
—
—
ns
—
ns
13.0
13.0
ns
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 37. DSPI classic SPI timing — slave mode
3.7.6 I2C switching specifications
See General switching specifications.
3.7.7 UART switching specifications
See General switching specifications.
3.7.8 LPUART switching specifications
See General switching specifications.
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3.7.9 SDHC specifications
The following timing specs are defined at the chip I/O pin and must be translated
appropriately to arrive at timing specs/constraints for the physical interface.
Table 56. SDHC full voltage range switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
Card input clock
SD1
fpp
fpp
fpp
fOD
tWL
tWH
tTLH
tTHL
Clock frequency (low speed)
0
0
400
25/45
25/45
400
—
kHz
MHz
MHz
kHz
ns
Clock frequency (SD\SDIO full speed\high speed)
Clock frequency (MMC full speed\high speed)
Clock frequency (identification mode)
Clock low time
0
0
SD2
SD3
SD4
SD5
7
Clock high time
7
—
ns
Clock rise time
—
—
3
ns
Clock fall time
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC output delay (output valid) 8.1
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SD6
tOD
0
ns
SD7
SD8
tISU
tIH
SDHC input setup time
SDHC input hold time
5
0
—
—
ns
ns
Table 57. SDHC limited voltage range switching specifications
Num
Symbol
Description
Min.
Max.
Unit
Operating voltage
2.7
3.6
V
Card input clock
SD1
fpp
fpp
fpp
fOD
tWL
tWH
tTLH
tTHL
Clock frequency (low speed)
0
0
400
25\50
20\50
400
—
kHz
MHz
MHz
kHz
ns
Clock frequency (SD\SDIO full speed\high speed)
Clock frequency (MMC full speed\high speed)
Clock frequency (identification mode)
Clock low time
0
0
SD2
SD3
SD4
SD5
7
Clock high time
7
—
ns
Clock rise time
—
—
3
ns
Clock fall time
3
ns
SDHC output / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
SDHC output delay (output valid)
SD6
tOD
0
7
ns
SDHC input / card inputs SDHC_CMD, SDHC_DAT (reference to SDHC_CLK)
Table continues on the next page...
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Table 57. SDHC limited voltage range switching specifications (continued)
Num
SD7
SD8
Symbol
tISU
Description
Min.
Max.
—
Unit
ns
SDHC input setup time
SDHC input hold time
5
0
tIH
—
ns
SD3
SD6
SD2
SD1
SDHC_CLK
Output SDHC_CMD
Output SDHC_DAT[3:0]
Input SDHC_CMD
SD7
SD8
Input SDHC_DAT[3:0]
Figure 38. SDHC timing
3.7.10 I2S switching specifications
This section provides the AC timings for the I2S in master (clocks driven) and slave
modes (clocks input). All timings are given for non-inverted serial clock polarity
(TCR[TSCKP] = 0, RCR[RSCKP] = 0) and a non-inverted frame sync (TCR[TFSI] = 0,
RCR[RFSI] = 0). If the polarity of the clock and/or the frame sync have been inverted,
all the timings remain valid by inverting the clock signal (I2S_BCLK) and/or the frame
sync (I2S_FS) shown in the figures below.
Table 58. I2S master mode timing (limited voltage range)
Num
Description
Min.
2.7
40
Max.
3.6
—
Unit
Operating voltage
V
S1
S2
S3
S4
S5
S6
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
I2S_BCLK cycle time
45%
80
55%
—
MCLK period
ns
I2S_BCLK pulse width high/low
I2S_BCLK to I2S_FS output valid
I2S_BCLK to I2S_FS output invalid
45%
—
55%
15
BCLK period
ns
ns
0
—
Table continues on the next page...
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Table 58. I2S master mode timing (limited voltage range) (continued)
Num
S7
Description
Min.
—
0
Max.
15
Unit
ns
I2S_BCLK to I2S_TXD valid
S8
I2S_BCLK to I2S_TXD invalid
I2S_RXD/I2S_FS input setup before I2S_BCLK
I2S_RXD/I2S_FS input hold after I2S_BCLK
—
ns
S9
15
0
—
ns
S10
—
ns
S1
S2
S2
I2S_MCLK (output)
I2S_BCLK (output)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S3
S4
S4
S5
S7
S6
S10
S9
S7
S8
S8
S9
S10
I2S_RXD
Figure 39. I2S timing — master mode
Table 59. I2S slave mode timing (limited voltage range)
Num
Description
Operating voltage
Min.
2.7
80
45%
4.5
2
Max.
Unit
3.6
—
V
S11
S12
S13
S14
S15
S16
S17
S18
S19
I2S_BCLK cycle time (input)
ns
I2S_BCLK pulse width high/low (input)
I2S_FS input setup before I2S_BCLK
I2S_FS input hold after I2S_BCLK
55%
—
MCLK period
ns
ns
ns
ns
ns
ns
ns
—
I2S_BCLK to I2S_TXD/I2S_FS output valid
I2S_BCLK to I2S_TXD/I2S_FS output invalid
I2S_RXD setup before I2S_BCLK
—
20
—
0
4.5
2
—
I2S_RXD hold after I2S_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
25
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
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S11
S12
I2S_BCLK (input)
I2S_FS (output)
I2S_FS (input)
I2S_TXD
S12
S15
S16
S13
S14
S19
S15
S16
S15
S16
S17
S18
I2S_RXD
Figure 40. I2S timing — slave modes
3.7.10.1 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 60. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
40
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK (as an input) pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
45%
80
55%
—
MCLK period
ns
45%
—
55%
15
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
15
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
15
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
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Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 41. I2S/SAI timing — master modes
Table 61. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
1.71
80
3.6
—
V
S11
S12
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
(input)
55%
MCLK period
S13
S14
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
4.5
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
2
—
S15
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
0
23.1
—
ns
ns
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
S17
S18
S19
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
4.5
2
—
—
25
ns
ns
ns
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Kinetis K80 Sub-Family, Rev. 5, 11/2016
71
NXP Semiconductors
Peripheral operating requirements and behaviors
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 42. I2S/SAI timing — slave modes
3.7.10.2 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 62. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
62.5
45%
250
45%
—
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
55%
—
MCLK period
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
ns
55%
45
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
45
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
45
S10
I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK
0
—
ns
72
Kinetis K80 Sub-Family, Rev. 5, 11/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 43. I2S/SAI timing — master modes
Table 63. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
1.71
250
3.6
—
V
S11
ns
S12
S13
S14
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
(input)
55%
MCLK period
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
5
—
S15
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
0
56.5
—
ns
ns
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
S17
S18
S19
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
30
5
—
—
72
ns
ns
ns
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
Kinetis K80 Sub-Family, Rev. 5, 11/2016
73
NXP Semiconductors
Dimensions
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 44. I2S/SAI timing — slave modes
3.8 Human-machine interfaces (HMI)
3.8.1 TSI electrical specifications
Table 64. TSI electrical specifications
Symbol
TSI_RUNF
TSI_RUNV
Description
Min.
—
Typ.
100
—
Max.
Unit
µA
Fixed power consumption in run mode
—
Variable power consumption in run mode
(depends on oscillator's current selection)
1.0
128
µA
TSI_EN
TSI_DIS
Power consumption in enable mode
Power consumption in disable mode
TSI analog enable time
—
—
100
1.2
66
—
—
µA
µA
µs
pF
V
TSI_TEN
—
—
TSI_CREF
TSI_DVOLT
TSI reference capacitor
—
1.0
—
—
Voltage variation of VP & VM around nominal
values
0.19
1.03
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
74
Kinetis K80 Sub-Family, Rev. 5, 11/2016
NXP Semiconductors
Pinout
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
100-pin LQFP
Then use this document number
98ASS23308W
121-pin XFBGA
144-pin LQFP
98ASA00595D
98ASS23177W1
1. The 144-pin LQFP package for this product is not yet available, however it is included in a Package Your Way
program for Kinetis MCUs. Visit nxp.com/KPYW for more details.
5 Pinout
5.1 K80 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
The 144-pin LQFP and 121-WLCSP packages for this
product are not yet available, however they are included in a
Package Your Way program for Kinetis MCUs. Visit
nxp.com/KPYW for more details.
144
LQFP LQFP
100
121
XFB
GA
121
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
QSPI_SIP_
MODE
x
—
—
H6
—
K9
G8
NC
NC
NC
—
ADC0_
SE16
ADC0_
SE16
ADC0_
SE16
—
—
—
1
—
—
—
1
A11
J6
—
—
NC
NC
NC
NC
NC
NC
NC
J4
—
NC
NC
B1
C10
PTE0
DISABLED
PTE0
SPI1_
PCS1
LPUART1_ SDHC0_D1 QSPI0A_
TX DATA3
I2C1_SDA
I2C1_SCL
RTC_
CLKOUT
2
3
4
2
3
4
C2
C1
D2
D9
PTE1/
LLWU_P0
DISABLED
DISABLED
DISABLED
PTE1/
LLWU_P0
SPI1_SCK
LPUART1_ SDHC0_D0 QSPI0A_
SPI1_SIN
RX
SCLK
D10
B11
PTE2/
LLWU_P1
PTE2/
LLWU_P1
SPI1_
SOUT
LPUART1_ SDHC0_
QSPI0A_
DATA0
SPI1_SCK
CTS_b
LPUART1_ SDHC0_
RTS_b CMD
DCLK
PTE3
PTE3
SPI1_
PCS2
QSPI0A_
DATA2
SPI1_
SOUT
Kinetis K80 Sub-Family, Rev. 5, 11/2016
75
NXP Semiconductors
Pinout
144
LQFP LQFP
100
121
XFB
GA
121
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
QSPI_SIP_
MODE
5
6
7
5
6
7
F7
E5
D1
F6
F7
VSS
VSS
VSS
VDDIO_E
VDDIO_E
VDDIO_E
C11
PTE4/
LLWU_P2
DISABLED
PTE4/
LLWU_P2
SPI1_SIN
LPUART3_ SDHC0_D3 QSPI0A_
TX DATA1
8
8
E2
E1
F3
F2
F1
G2
G1
—
E8
E9
PTE5
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
PTE5
SPI1_
PCS0
LPUART3_ SDHC0_D2 QSPI0A_
FTM3_CH0 USB0_
SOF_OUT
RX
SS0_B
9
9
PTE6/
LLWU_P16
PTE6/
LLWU_P16 PCS3
SPI1_
LPUART3_ I2S0_
QSPI0B_
DATA3
FTM3_CH1 SDHC0_D4
CTS_b
MCLK
10
11
12
13
14
15
16
10
11
12
13
14
—
—
E10
D11
E11
F8
PTE7
PTE7
SPI2_SCK
LPUART3_ I2S0_RXD0 QSPI0B_
FTM3_CH2 QSPI0A_
SS1_B
RTS_b
SCLK
PTE8
PTE8
I2S0_RXD1 SPI2_
SOUT
I2S0_RX_
FS
QSPI0B_
DATA0
FTM3_CH3 SDHC0_D5
FTM3_CH4 SDHC0_D6
FTM3_CH5 SDHC0_D7
PTE9/
LLWU_P17
PTE9/
LLWU_P17
I2S0_TXD1 SPI2_
PCS1
I2S0_RX_
BCLK
QSPI0B_
DATA2
PTE10/
LLWU_P18
PTE10/
LLWU_P18
I2C3_SDA
SPI2_SIN
I2S0_TXD0 QSPI0B_
DATA1
F9
PTE11
PTE12
PTE13
PTE11
PTE12
PTE13
I2C3_SCL
SPI2_
PCS0
I2S0_TX_
FS
QSPI0B_
SS0_B
FTM3_CH6 QSPI0A_
DQS
—
LPUART2_ I2S0_TX_
QSPI0B_
DQS
FTM3_CH7 FXIO0_D2
QSPI0A_
DATA3
TX
BCLK
—
—
LPUART2_
RX
QSPI0B_
SS1_B
SDHC0_
CLKIN
FXIO0_D3
QSPI0A_
SCLK
17
18
19
15
16
—
—
—
—
F10
F11
—
VDDIO_E
VSS
VDDIO_E
VSS
VDDIO_E
VSS
PTE16
ADC0_
SE4a
ADC0_
SE4a
PTE16
SPI0_
PCS0
LPUART2_ FTM_
FTM0_
FLT3
FXIO0_D4
FXIO0_D5
QSPI0A_
DATA0
TX
CLKIN0
20
—
—
—
PTE17/
LLWU_P19 SE5a
ADC0_
ADC0_
SE5a
PTE17/
LLWU_P19
SPI0_SCK
LPUART2_ FTM_
LPTMR0_
ALT3/
QSPI0A_
DATA2
RX
CLKIN1
LPTMR1_
ALT3
21
22
—
—
—
—
—
—
PTE18/
LLWU_P20 SE6a
ADC0_
ADC0_
SE6a
PTE18/
LLWU_P20 SOUT
SPI0_
LPUART2_ I2C0_SDA
CTS_b
FXIO0_D6
FXIO0_D7
QSPI0A_
DATA1
PTE19
ADC0_
SE7a
ADC0_
SE7a
PTE19 SPI0_SIN
LPUART2_ I2C0_SCL
RTS_b
QSPI0A_
SS0_B
23
24
25
26
27
28
29
30
16
17
18
19
20
21
—
—
H3
H2
H1
J1
F11
G11
H11
G10
H10
G9
VSS
VSS
VSS
USB0_DP
USB0_DM
VOUT33
VREGIN
NC
USB0_DP
USB0_DM
VOUT33
VREGIN
NC
USB0_DP
USB0_DM
VOUT33
VREGIN
NC
J2
—
K2
K1
J10
K10
ADC0_DP0 ADC0_DP0 ADC0_DP0
ADC0_
DM0
ADC0_
DM0
ADC0_
DM0
31
—
J3
J11
ADC0_DP3 ADC0_DP3 ADC0_DP3
76
NXP Semiconductors
Kinetis K80 Sub-Family, Rev. 5, 11/2016
Pinout
144
LQFP LQFP
100
121
XFB
GA
121
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
QSPI_SIP_
MODE
32
—
K3
K11
ADC0_
DM3
ADC0_
DM3
ADC0_
DM3
33
34
35
36
37
38
22
23
24
25
26
27
F5
G5
G6
F6
L2
L1
H8
H9
J9
J8
—
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
ADC0_DP1 ADC0_DP1 ADC0_DP1
—
ADC0_
DM1
ADC0_
DM1
ADC0_
DM1
39
28
L3
L11
VREF_
OUT/
VREF_
OUT/
VREF_
OUT/
CMP1_IN5/ CMP1_IN5/ CMP1_IN5/
CMP0_IN5/ CMP0_IN5/ CMP0_IN5/
ADC0_
SE22
ADC0_
SE22
ADC0_
SE22
40
42
29
30
K4
K5
L10
H7
DAC0_
OUT/
DAC0_
OUT/
DAC0_
OUT/
CMP1_IN3/ CMP1_IN3/ CMP1_IN3/
ADC0_
SE23
ADC0_
SE23
ADC0_
SE23
RTC_
WAKEUP_
B
RTC_
WAKEUP_
B
RTC_
WAKEUP_
B
43
44
45
46
47
48
31
32
33
34
35
—
L4
L5
K6
—
L9
L8
K8
G7
F6
L7
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
XTAL32
EXTAL32
VBAT
VDD
VDD
VDD
—
VSS
VSS
VSS
H5
PTA20
DISABLED
PTA20
I2C0_SCL
I2C0_SDA
LPUART4_ FTM_
FXIO0_D8
FXIO0_D9
EWM_
OUT_b
TPM_
CLKIN1
TX
CLKIN1
49
50
—
J5
L7
K7
J7
PTA21/
LLWU_P21
DISABLED
PTA21/
LLWU_P21
LPUART4_
RX
EWM_IN
36
PTA0
JTAG_
TCLK/
TSI0_CH1
PTA0
LPUART0_ FTM0_CH5
CTS_b
FXIO0_D10 EMVSIM0_ JTAG_
CLK
TCLK/
SWD_CLK
SWD_CLK
51
52
37
38
H8
J7
J6
PTA1
PTA2
JTAG_TDI
TSI0_CH2
TSI0_CH3
PTA1
PTA2
LPUART0_ FTM0_CH6 I2C3_SDA
RX
FXIO0_D11 EMVSIM0_ JTAG_TDI
IO
K6
JTAG_
TDO/
LPUART0_ FTM0_CH7 I2C3_SCL
TX
FXIO0_D12 EMVSIM0_ JTAG_
PD
TDO/
TRACE_
SWO
TRACE_
SWO
53
54
39
40
H9
J8
L6
PTA3
JTAG_
TMS/
SWD_DIO
TSI0_CH4
TSI0_CH5
PTA3
LPUART0_ FTM0_CH0
RTS_b
FXIO0_D13 EMVSIM0_ JTAG_
RST
TMS/
SWD_DIO
H6
PTA4/
LLWU_P3
NMI_b
PTA4/
LLWU_P3
FTM0_CH1
FXIO0_D14 EMVSIM0_ NMI_b
VCCEN
Kinetis K80 Sub-Family, Rev. 5, 11/2016
77
NXP Semiconductors
Pinout
144
LQFP LQFP
100
121
XFB
GA
121
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
QSPI_SIP_
MODE
55
41
K7
H5
PTA5
DISABLED
PTA5
USB0_
CLKIN
FTM0_CH2
FXIO0_D15 I2S0_TX_
BCLK
JTAG_
TRST_b
56
57
58
—
—
—
L10
K10
—
G6
F5
—
VDD
VSS
VDD
VDD
VSS
VSS
PTA6
DISABLED
PTA6
PTA7
PTA8
I2C2_SCL
I2C2_SDA
FTM0_CH3 EMVSIM1_ CLKOUT
CLK
TRACE_
CLKOUT
59
60
—
—
—
—
—
—
PTA7
PTA8
ADC0_
SE10
ADC0_
SE10
FTM0_CH4 EMVSIM1_
IO
TRACE_D3
ADC0_
SE11
ADC0_
SE11
FTM1_CH0 EMVSIM1_
PD
FTM1_QD_ TRACE_D2
PHA/
TPM1_CH0
61
62
63
64
65
—
—
—
42
43
—
J9
—
L5
L4
K5
J5
PTA9
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
PTA9
FTM1_CH1 EMVSIM1_
RST
FTM1_QD_ TRACE_D1
PHB/
TPM1_CH1
PTA10/
LLWU_P22
PTA10/
LLWU_P22
I2C2_SDA
I2C2_SCL
FTM2_CH0 EMVSIM1_ FXIO0_D16 FTM2_QD_ TRACE_D0
VCCEN
PHA/
TPM2_CH0
H7
K8
L8
PTA11/
LLWU_P23
PTA11/
LLWU_P23
FTM2_CH1
FXIO0_D17 FTM2_QD_
PHB/
TPM2_CH1
PTA12
PTA12
FTM1_CH0 TRACE_
CLKOUT
FXIO0_D18 I2S0_TXD0 FTM1_QD_
PHA/
TPM1_CH0
PTA13/
LLWU_P4
PTA13/
LLWU_P4
FTM1_CH1 TRACE_D3 FXIO0_D19 I2S0_TX_
FS
FTM1_QD_
PHB/
TPM1_CH1
66
67
68
69
44
45
46
47
K9
L9
L3
K4
J4
PTA14
PTA15
PTA16
PTA17
DISABLED
DISABLED
DISABLED
DISABLED
PTA14
PTA15
PTA16
PTA17
SPI0_
PCS0
LPUART0_ TRACE_D2 FXIO0_D20 I2S0_RX_
I2S0_TXD1
TX
BCLK
SPI0_SCK
LPUART0_ TRACE_D1 FXIO0_D21 I2S0_RXD0
RX
J10
H10
SPI0_
SOUT
LPUART0_ TRACE_D0 FXIO0_D22 I2S0_RX_
I2S0_RXD1
CTS_b
FS
K3
SPI0_SIN
LPUART0_
RTS_b
FXIO0_D23 I2S0_
MCLK
70
71
72
48
49
50
E6
G7
L2
K2
L1
VDD
VDD
VDD
VSS
VSS
VSS
L11
PTA18
EXTAL0
EXTAL0
PTA18
PTA19
FTM0_
FLT2
FTM_
CLKIN0
TPM_
CLKIN0
73
51
K11
K1
PTA19
XTAL0
XTAL0
FTM1_
FLT0
FTM_
CLKIN1
LPTMR0_
ALT1/
TPM_
CLKIN1
LPTMR1_
ALT1
74
75
52
—
J11
—
J1
—
RESET_b
PTA24
RESET_b
RESET_b
DISABLED
PTA24
EMVSIM0_
CLK
FB_A29
78
NXP Semiconductors
Kinetis K80 Sub-Family, Rev. 5, 11/2016
Pinout
144
LQFP LQFP
100
121
XFB
GA
121
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
QSPI_SIP_
MODE
76
77
78
79
—
—
—
—
—
—
—
—
—
—
—
—
PTA25
PTA26
PTA27
PTA28
PTA29
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
PTA25
EMVSIM0_
IO
FB_A28
FB_A27
FB_A26
FB_A25
FB_A24
PTA26
PTA27
PTA28
PTA29
EMVSIM0_
PD
EMVSIM0_
RST
EMVSIM0_
VCCEN
80
81
—
H11
G11
J2
J3
53
PTB0/
LLWU_P5
ADC0_
SE8/
TSI0_CH0
ADC0_
SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL
I2C0_SDA
I2C0_SCL
I2C0_SDA
FTM1_CH0
FTM1_CH1
SDRAM_
CAS_b
FTM1_QD_ FXIO0_D0
PHA/
TPM1_CH0
82
83
84
54
55
56
G10
G9
H2
H1
H3
PTB1
PTB2
PTB3
ADC0_
SE9/
TSI0_CH6
ADC0_
SE9/
TSI0_CH6
PTB1
PTB2
PTB3
SDRAM_
RAS_b
FTM1_QD_ FXIO0_D1
PHB/
TPM1_CH1
ADC0_
SE12/
TSI0_CH7
ADC0_
SE12/
TSI0_CH7
LPUART0_
RTS_b
SDRAM_
WE
FTM0_
FLT3
FXIO0_D2
FXIO0_D3
G8
ADC0_
SE13/
ADC0_
SE13/
LPUART0_
CTS_b
SDRAM_
CS0_b
FTM0_
FLT0
TSI0_CH8
TSI0_CH8
85
86
87
—
—
—
B11
C11
F11
H4
G1
G2
PTB4
PTB5
PTB6
DISABLED
DISABLED
DISABLED
PTB4
PTB5
PTB6
EMVSIM1_
IO
SDRAM_
CS1_b
FTM1_
FLT0
EMVSIM1_
CLK
FTM2_
FLT0
EMVSIM1_
VCCEN
FB_AD23/
SDRAM_
D23
88
89
90
91
92
—
—
57
58
59
E11
D11
E10
D10
C10
G3
G4
G5
F1
F2
PTB7
PTB8
PTB9
PTB10
PTB11
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
PTB7
PTB8
PTB9
PTB10
PTB11
EMVSIM1_
PD
FB_AD22/
SDRAM_
D22
EMVSIM1_ LPUART3_
RST
FB_AD21/
SDRAM_
D21
RTS_b
SPI1_
PCS1
LPUART3_
CTS_b
FB_AD20/
SDRAM_
D20
SPI1_
PCS0
LPUART3_ I2C2_SCL
RX
FB_AD19/
SDRAM_
D19
FTM0_
FLT1
FXIO0_D4
FXIO0_D5
SPI1_SCK
LPUART3_ I2C2_SDA
TX
FB_AD18/
SDRAM_
D18
FTM0_
FLT2
93
94
60
61
L6
E7
F5
VSS
VDD
VSS
VDD
VSS
VDD
G6
Kinetis K80 Sub-Family, Rev. 5, 11/2016
79
NXP Semiconductors
Pinout
144
LQFP LQFP
100
121
XFB
GA
121
WLC
SP
Pin Name
PTB16
PTB17
PTB18
PTB19
PTB20
PTB21
PTB22
PTB23
PTC0
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
QSPI_SIP_
MODE
95
96
62
63
64
65
66
67
68
69
70
71
72
B10
E9
D9
C9
F10
F9
E1
F3
F4
E2
D1
E3
E4
D2
C1
D3
C2
TSI0_CH9
TSI0_CH9
PTB16
SPI1_
SOUT
LPUART0_ FTM_
FB_AD17/
SDRAM_
D17
EWM_IN
TPM_
CLKIN0
RX
CLKIN0
TSI0_CH10 TSI0_CH10 PTB17
TSI0_CH11 TSI0_CH11 PTB18
TSI0_CH12 TSI0_CH12 PTB19
SPI1_SIN
LPUART0_ FTM_
FB_AD16/
SDRAM_
D16
EWM_
OUT_b
TPM_
CLKIN1
TX
CLKIN1
97
FTM2_CH0 I2S0_TX_
BCLK
FB_AD15/
SDRAM_
A23
FTM2_QD_ FXIO0_D6
PHA/
TPM2_CH0
98
FTM2_CH1 I2S0_TX_
FS
FB_OE_b
FTM2_QD_ FXIO0_D7
PHB/
TPM2_CH1
99
DISABLED
DISABLED
DISABLED
DISABLED
PTB20
PTB21
PTB22
PTB23
PTC0
SPI2_
PCS0
FB_AD31/
SDRAM_
D31
CMP0_
OUT
FXIO0_D8
FXIO0_D9
FXIO0_D10
FXIO0_D11
100
101
102
103
104
105
SPI2_SCK
FB_AD30/
SDRAM_
D30
CMP1_
OUT
F8
SPI2_
SOUT
FB_AD29/
SDRAM_
D29
E8
B9
D8
C8
SPI2_SIN
SPI0_
PCS5
FB_AD28/
SDRAM_
D28
ADC0_
SE14/
TSI0_CH13 TSI0_CH13
ADC0_
SE14/
SPI0_
PCS4
PDB0_
EXTRG
USB0_
SOF_OUT
FB_AD14/
SDRAM_
A22
I2S0_TXD1 FXIO0_D12
I2S0_TXD0 FXIO0_D13
PTC1/
LLWU_P6
ADC0_
SE15/
TSI0_CH14 TSI0_CH14
ADC0_
SE15/
PTC1/
LLWU_P6
SPI0_
PCS3
LPUART1_ FTM0_CH0 FB_AD13/
RTS_b
SDRAM_
A21
PTC2
ADC0_
SE4b/
CMP1_IN0/ CMP1_IN0/
TSI0_CH15 TSI0_CH15
ADC0_
SE4b/
PTC2
SPI0_
PCS2
LPUART1_ FTM0_CH1 FB_AD12/
CTS_b
I2S0_TX_
FS
SDRAM_
A20
106
73
B8
B1
PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
SPI0_
PCS1
LPUART1_ FTM0_CH2 CLKOUT
RX
I2S0_TX_
BCLK
107
108
109
74
75
76
—
—
E5
G6
A1
VSS
VDD
VSS
VSS
VDD
VDD
A8
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_
PCS0
LPUART1_ FTM0_CH3 FB_AD11/
CMP1_
OUT
TX
SDRAM_
A19
110
111
77
78
D7
C7
B2
C3
PTC5/
LLWU_P9
DISABLED
CMP0_IN0
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_
ALT2/
LPTMR1_
ALT2
I2S0_RXD0 FB_AD10/
CMP0_
OUT
FTM0_CH2
FXIO0_D14
SDRAM_
A18
PTC6/
LLWU_P10
CMP0_IN0
PTC6/
LLWU_P10 SOUT
SPI0_
PDB0_
EXTRG
I2S0_RX_
BCLK
FB_AD9/
SDRAM_
A17
I2S0_
MCLK
80
NXP Semiconductors
Kinetis K80 Sub-Family, Rev. 5, 11/2016
Pinout
144
LQFP LQFP
100
121
XFB
GA
121
WLC
SP
Pin Name
PTC7
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
QSPI_SIP_
MODE
112
113
114
115
79
80
81
82
B7
A7
D6
C6
A2
B3
D4
A3
CMP0_IN1
CMP0_IN2
CMP0_IN3
DISABLED
CMP0_IN1
CMP0_IN2
CMP0_IN3
PTC7
SPI0_SIN
USB0_
SOF_OUT
I2S0_RX_
FS
FB_AD8/
SDRAM_
A16
FXIO0_D15
FXIO0_D16
FXIO0_D17
FXIO0_D18
FXIO0_D19
PTC8
PTC8
PTC9
PTC10
FTM3_CH4 I2S0_
MCLK
FB_AD7/
SDRAM_
A15
PTC9
FTM3_CH5 I2S0_RX_
BCLK
FB_AD6/
SDRAM_
A14
FTM2_
FLT0
PTC10
I2C1_SCL
I2C1_SDA
FTM3_CH6 I2S0_RX_
FS
FB_AD5/
SDRAM_
A13
116
117
83
84
C5
B6
C4
B4
PTC11/
LLWU_P11
DISABLED
DISABLED
PTC11/
LLWU_P11
FTM3_CH7 I2S0_RXD1 FB_RW_b
PTC12
PTC13
PTC14
PTC15
PTC12
PTC13
PTC14
PTC15
LPUART4_ FTM_
RTS_b
FB_AD27/
SDRAM_
D27
FTM3_
FLT0
TPM_
CLKIN0
CLKIN0
118
119
120
85
86
87
A6
A5
B5
A4
D5
C5
DISABLED
DISABLED
DISABLED
LPUART4_ FTM_
CTS_b
FB_AD26/
SDRAM_
D26
TPM_
CLKIN1
CLKIN1
LPUART4_
RX
FB_AD25/
SDRAM_
D25
FXIO0_D20
FXIO0_D21
LPUART4_
TX
FB_AD24/
SDRAM_
D24
121
122
123
88
89
—
—
—
F6
E6
A5
VSS
VSS
VSS
VDD
VDD
VDD
D5
PTC16
DISABLED
PTC16
PTC17
PTC18
LPUART3_
RX
FB_CS5_b/
FB_TSIZ1/
FB_BE23_
16_BLS15_
8_b/
SDRAM_
DQM2
124
125
90
—
C4
B4
B5
A6
PTC17
PTC18
DISABLED
DISABLED
LPUART3_
TX
FB_CS4_b/
FB_TSIZ0/
FB_BE31_
24_BLS7_
0_b/
SDRAM_
DQM3
LPUART3_
RTS_b
FB_TBST_
b/
FB_CS2_b/
FB_BE15_
8_BLS23_
16_b/
Kinetis K80 Sub-Family, Rev. 5, 11/2016
81
NXP Semiconductors
Pinout
144
LQFP LQFP
100
121
XFB
GA
121
WLC
SP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
QSPI_SIP_
MODE
SDRAM_
DQM1
126
—
A4
B6
PTC19
DISABLED
PTC19
LPUART3_
CTS_b
FB_CS3_b/ FB_TA_b
FB_BE7_
0_BLS31_
24_b/
SDRAM_
DQM0
127
91
D4
C6
PTD0/
DISABLED
PTD0/
SPI0_
LPUART2_ FTM3_CH0 FB_ALE/
FXIO0_D22
LLWU_P12
LLWU_P12 PCS0
RTS_b
FB_CS1_b/
FB_TS_b
128
129
92
93
D3
C3
D6
D7
PTD1
ADC0_
SE5b
ADC0_
SE5b
PTD1
SPI0_SCK
LPUART2_ FTM3_CH1 FB_CS0_b
CTS_b
FXIO0_D23
I2C0_SCL
PTD2/
LLWU_P13
DISABLED
DISABLED
DISABLED
PTD2/
LLWU_P13 SOUT
SPI0_
LPUART2_ FTM3_CH2 FB_AD4/
RX
SDRAM_
A12
130
131
132
133
94
95
96
97
B3
A3
A2
B2
A7
B7
C7
A8
PTD3
PTD3
SPI0_SIN
LPUART2_ FTM3_CH3 FB_AD3/
I2C0_SDA
TX
SDRAM_
A11
PTD4/
LLWU_P14
PTD4/
LLWU_P14 PCS1
SPI0_
LPUART0_ FTM0_CH4 FB_AD2/
EWM_IN
SPI1_
PCS0
RTS_b
SDRAM_
A10
PTD5
ADC0_
SE6b
ADC0_
SE6b
PTD5
SPI0_
PCS2
LPUART0_ FTM0_CH5 FB_AD1/
EWM_
OUT_b
SPI1_SCK
CTS_b
SDRAM_
A9
PTD6/
LLWU_P15 SE7b
ADC0_
ADC0_
SE7b
PTD6/
LLWU_P15 PCS3
SPI0_
LPUART0_ FTM0_CH6 FB_AD0
RX
FTM0_
FLT0
SPI1_
SOUT
134
135
136
98
99
—
—
F6
E7
B8
VSS
VSS
VSS
VDD
VDD
PTD7
VDD
100
A1
DISABLED
PTD7
CMT_IRO
LPUART0_ FTM0_CH7 SDRAM_
FTM0_
FLT1
SPI1_SIN
TX
CKE
137
—
A10
A9
PTD8/
LLWU_P24
DISABLED
PTD8/
LLWU_P24
I2C0_SCL
I2C0_SDA
FB_A16
FXIO0_D24
138
139
140
—
—
—
A9
E4
E3
C8
B9
PTD9
DISABLED
DISABLED
DISABLED
PTD9
FB_A17
FB_A18
FB_A19
FXIO0_D25
FXIO0_D26
FXIO0_D27
PTD10
PTD10
A10
PTD11/
PTD11/
SPI2_
LLWU_P25
LLWU_P25 PCS0
141
142
—
—
F4
D8
C9
PTD12
PTD13
DISABLED
DISABLED
PTD12
SPI2_SCK
FTM3_
FLT0
FB_A20
FB_A21
FXIO0_D28
FXIO0_D29
G3
PTD13
SPI2_
SOUT
143
144
—
—
G4
H4
B10
A11
PTD14
PTD15
DISABLED
DISABLED
PTD14
PTD15
SPI2_SIN
FB_A22
FB_A23
FXIO0_D30
FXIO0_D31
SPI2_
PCS1
82
NXP Semiconductors
Kinetis K80 Sub-Family, Rev. 5, 11/2016
Pinout
5.2 Recommended connection for unused analog and digital
pins
Table 65 shows the recommended connections for analog interface pins if those
analog interfaces are not used in the customer's application
Table 65. Recommended connection for unused analog interfaces
Pin Type
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
Analog/non GPIO
GPIO/Analog
Short recommendation
Float
Detailed recommendation
Analog input - Float
ADCx/CMPx
VREF_OUT
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Float
Analog output - Float
DAC0_OUT, DAC1_OUT
RTC_WAKEUP_B
XTAL32
Analog output - Float
Analog output - Float
Analog output - Float
EXTAL32
Analog input - Float
PTA18/EXTAL0
PTA19/XTAL0
PTx/ADCx
Analog input - Float
GPIO/Analog
Analog output - Float
GPIO/Analog
Float (default is analog input)
Float (default is analog input)
Float (default is analog input)
GPIO/Analog
PTx/CMPx
GPIO/Analog
PTx/TSIOx
GPIO/Digital
PTA0/JTAG_TCLK
Float (default is JTAG with
pulldown)
GPIO/Digital
GPIO/Digital
GPIO/Digital
GPIO/Digital
PTA1/JTAG_TDI
PTA2/JTAG_TDO
PTA3/JTAG_TMS
PTA4/NMI_b
Float
Float
Float
Float (default is JTAG with
pullup)
Float (default is JTAG with
pullup)
Float (default is JTAG with
pullup)
10kΩ pullup or disable and
float
Pull high or disable in PCR &
FOPT and float
GPIO/Digital
USB
PTx
Float
Float
Float
Float (default is disabled)
USB0_DP
USB0_DM
VOUT33
Float
Float
USB
USB
Tie to input and ground
through 10kΩ
Tie to input and ground
through 10kΩ
USB
VREGIN
Tie to output and ground
through 10kΩ
Tie to output and ground
through 10kΩ
USB
USB0_VSS
VBAT
Always connect to VSS
Float
Always connect to VSS
Float
VBAT
VDDA
VDDA
Always connect to VDD
potential
Always connect to VDD
potential
VREFH
VREFL
VREFH
VREFL
Always connect to VDD
potential
Always connect to VDD
potential
Always connect to VSS
potential
Always connect to VSS
potential
Table continues on the next page...
Kinetis K80 Sub-Family, Rev. 5, 11/2016
83
NXP Semiconductors
Pinout
Table 65. Recommended connection for unused analog interfaces (continued)
Pin Type
Short recommendation
Detailed recommendation
VSSA
VSSA
Always connect to VSS
potential
Always connect to VSS
potential
5.3 K80 Pinouts
The below figure shows the pinout diagram for the devices supported by this document.
Many signals may be multiplexed onto a single pin. To determine what signals can be
used on which pin, see the previous section.
84
Kinetis K80 Sub-Family, Rev. 5, 11/2016
NXP Semiconductors
Pinout
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PTE0
PTE1/LLWU_P0
PTE2/LLWU_P1
PTE3
VDD
VSS
2
3
PTC3/LLWU_P7
PTC2
4
5
PTC1/LLWU_P6
PTC0
VSS
6
VDDIO_E
PTE4/LLWU_P2
PTE5
7
PTB23
8
PTB22
9
PTB21
PTE6/LLWU_P16
PTE7
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PTB20
PTB19
PTE8
PTB18
PTE9/LLWU_P17
PTE10/LLWU_P18
PTE11
PTB17
PTB16
VDD
VDDIO_E
VSS VSS
USB0_DP
USB0_DM
VOUT33
VSS
PTB11
PTB10
PTB9
PTB3
VREGIN
PTB2
NC
PTB1
VDDA
PTB0/LLWU_P5
RESET_b
PTA19
VREFH
VREFL
VSSA
Figure 45. K80 100 LQFP Pinout Diagram
Kinetis K80 Sub-Family, Rev. 5, 11/2016
85
NXP Semiconductors
Pinout
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
PTD7
PTD5
PTD4/
LLWU_P14
PTC19
PTC14
PTC13
PTC8
PTC4/
LLWU_P8
PTD9
PTD8/
LLWU_P24
NC
A
B
C
D
E
F
G
H
J
PTE0
PTD6/
LLWU_P15
PTD3
PTC18
PTC17
PTC15
PTC12
PTC10
PTC9
VDD
PTC7
PTC3/
LLWU_P7
PTC0
PTB19
PTB18
PTB17
PTB21
PTB2
PTB16
PTB11
PTB10
PTB9
PTB4
PTB5
PTB8
PTB7
PTB6
PTE2/
PTE1/
PTD2/
PTC11/
LLWU_P11
PTC6/
LLWU_P10
PTC2
LLWU_P1 LLWU_P0 LLWU_P13
PTE4/
LLWU_P2
PTE3
PTE5
PTE8
PTD1
PTD0/
LLWU_P12
PTC16
VDDIO_E
VDDA
PTC5/
LLWU_P9 LLWU_P6
PTC1/
PTE6/
LLWU_P16
PTD11/
LLWU_P25
PTD10
PTD12
PTD14
PTD15
NC
VDD
VSS
VSS
PTB23
PTB22
PTB3
PTA1
PTE9/
LLWU_P17
PTE7
PTD13
VSS
VSSA
VREFL
NC
PTB20
PTB1
PTE11
PTE10/
LLWU_P18
VREFH
PTA20
PTB0/
LLWU_P5
USB0_DM USB0_DP
PTA11/
LLWU_P23
PTA3
PTA17
PTA16
VSS
PTA29
RESET_b
PTA19
VOUT33
VREGIN ADC0_DP3
PTA21/
LLWU_P21
NC
PTA2
PTA5
PTA4/
LLWU_P3 LLWU_P22
PTA10/
DAC0_OUT/
CMP1_IN3/
ADC0_SE23
K
L
ADC0_DM0 ADC0_DP0 ADC0_DM3
RTC_
WAKEUP_B
VBAT
PTA12
PTA14
K
L
VREF_OUT/
CMP1_IN5/
CMP0_IN5/
PTA13/
LLWU_P4
ADC0_DM1 ADC0_DP1
XTAL32
4
EXTAL32
5
VSS
6
PTA0
7
PTA15
9
VDD
10
PTA18
11
ADC0_SE22
1
2
3
8
Figure 46. K80 121 XFBGA Pinout Diagram
86
NXP Semiconductors
Kinetis K80 Sub-Family, Rev. 5, 11/2016
Pinout
PTE0
PTE1/LLWU_P0
PTE2/LLWU_P1
PTE3
1
108
107
106
105
104
103
102
101
100
99
VDD
2
VSS
3
PTC3/LLWU_P7
PTC2
4
VSS
5
PTC1/LLWU_P6
PTC0
VDDIO_E
PTE4/LLWU_P2
PTE5
6
7
PTB23
PTB22
PTB21
PTB20
PTB19
PTB18
PTB17
PTB16
VDD
8
PTE6/LLWU_P16
PTE7
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PTE8
98
PTE9/LLWU_P17
PTE10/LLWU_P18
PTE11
97
96
95
PTE12
94
PTE13
VSS
93
VDDIO_E
VSS
PTB11
PTB10
PTB9
92
91
PTE16
90
PTE17/LLWU_P19
PTE18/LLWU_P20
PTE19
PTB8
89
PTB7
88
PTB6
87
VSS
PTB5
86
USB0_DP
USB0_DM
VOUT33
PTB4
85
PTB3
84
PTB2
83
VREGIN
PTB1
82
NC
PTB0/LLWU_P5
PTA29
PTA28
PTA27
PTA26
PTA25
PTA24
RESET_b
PTA19
81
ADC0_DP0
ADC0_DM0
ADC0_DP3
ADC0_DM3
VDDA
80
79
78
77
76
VREFH
75
VREFL
74
VSSA
73
Figure 47. K80 144 LQFP Pinout Diagram
NOTE
The 144-pin LQFP package for this product is not yet
available, however it is included in a Package Your Way
program for Kinetis MCUs. Visit nxp.com/KPYW for more
details.
Kinetis K80 Sub-Family, Rev. 5, 11/2016
87
NXP Semiconductors
Ordering parts
1
2
3
4
5
6
7
8
9
10
11
A
PTC4/
LLWU_P8
PTC7
PTC10
PTC13
PTC16
PTC18
PTD3
PTD6/
PTD8/
PTD11/
PTD15
A
B
C
D
E
F
G
H
J
LLWU_P15 LLWU_P24 LLWU_P25
B
C
D
E
F
G
H
J
PTC3/
LLWU_P7 LLWU_P9
PTC5/
PTC8
PTC12
PTC11/
PTC17
PTC15
PTC14
VSS
PTC19
PTD4/
LLWU_P14
PTD7
PTD9
PTD12
PTE5
PTD10
PTD13
PTE1/
PTD14
PTE0
PTE3
PTC0
PTB20
PTB16
PTB10
PTB5
PTC2
PTB23
PTB19
PTB11
PTB6
PTB1
PTA29
VSS
PTC6/
LLWU_P10 LLWU_P11
PTD0/
LLWU_P12
PTD5
PTE4/
LLWU_P2
PTC1/
LLWU_P6
PTC9
PTB22
PTB18
PTB8
PTD1
VDD
PTD2/
LLWU_P13
PTE2/
PTE8
LLWU_P0 LLWU_P1
PTB21
PTB17
PTB7
VDD
VDDIO_E
VDD
PTE6/
LLWU_P16
PTE7
PTE9/
LLWU_P17
VSS VSS
VSS VSS
VSS VSS
PTB9
PTE10/
LLWU_P18
PTE11
NC
VDDIO_E VSS VSS
VDD VDD
VDD
ADC0_SE16
VDDA
VOUT33
USB0_DP
PTB2
PTB3
PTB4
PTA5
PTA4/
RTC_
VREFH
VREFL
NC
VREGIN USB0_DM
ADC0_DP0 ADC0_DP3
LLWU_P3 WAKEUP_B
RESET_b
PTA19
PTB0/
LLWU_P5
PTA16
PTA15
PTA11/
PTA13/
LLWU_P4
PTA1
PTA2
PTA0
VSSA
K
L
PTA17
PTA12
PTA21/
LLWU_P21
VBAT
ADC0_DM0 ADC0_DM3
VREF_OUT/
K
L
DAC0_OUT/
CMP1_IN5/
CMP1_IN3/
CMP0_IN5/
PTA18
1
VDD
2
PTA14
3
PTA10/
PTA3
6
PTA20
7
EXTAL32
8
XTAL32
9
ADC0_SE23
ADC0_SE22
LLWU_P23 LLWU_P22
4
5
10
11
Figure 48. K80 121 WLCSP Pinout Diagram
NOTE
The 121-pin WLCSP package for this product is not yet
available, however it is included in a Package Your Way
program for Kinetis MCUs. Visit nxp.com/KPYW for more
details.
6 Ordering parts
88
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NXP Semiconductors
Part identification
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable
part numbers for this device, go to nxp.com and perform a part number search for the
following device numbers: MK80.
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q K## A M FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
K##
A
Kinetis family
Key attribute
• K80
• D = Cortex-M4 w/ DSP
• F = Cortex-M4 w/ DSP and FPU
M
Flash memory type
• N = Program flash only
• X = Program flash and FlexMemory
FFF
Program flash memory size
• 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
• 512 = 512 KB
• 1M0 = 1 MB
• 2M0 = 2 MB
Table continues on the next page...
Kinetis K80 Sub-Family, Rev. 5, 11/2016
89
NXP Semiconductors
Terminology and guidelines
Field
Description
Values
R
Silicon revision
• Z = Initial
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
• C = –40 to 85
PP
• FM = 32 QFN (5 mm x 5 mm)
• FT = 48 QFN (7 mm x 7 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)
• LK = 80 LQFP (12 mm x 12 mm)
• LL = 100 LQFP (14 mm x 14 mm)
• MC = 121 MAPBGA (8 mm x 8 mm)
• DC = 121 XFBGA (8 mm x 8 mm x 0.5 mm)
• LQ = 144 LQFP (20 mm x 20 mm)
• MD = 144 MAPBGA (13 mm x 13 mm)
CC
Maximum CPU frequency (MHz)
• 5 = 50 MHz
• 7 = 72 MHz
• 10 = 100 MHz
• 12 = 120 MHz
• 15 = 150 MHz
• 18 = 180 MHz
N
Packaging type
• R = Tape and reel
• (Blank) = Trays
7.4 Example
This is an example part number:
MK80FN256VLL15
8 Terminology and guidelines
8.1 Definitions
Key terms are defined in the following table:
Term
Definition
Rating
A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
Table continues on the next page...
90
Kinetis K80 Sub-Family, Rev. 5, 11/2016
NXP Semiconductors
Terminology and guidelines
Term
Definition
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior
A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value
A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.
8.2 Examples
Operating rating:
EXAMPLE
EXAMPLE
Operating requirement:
Operating behavior that includes a typical value:
8.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Kinetis K80 Sub-Family, Rev. 5, 11/2016
91
NXP Semiconductors
Revision History
Symbol
Description
Ambient temperature
Supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
8.4 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
8.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
9 Revision History
The following table provides the revision history for this document.
92
Kinetis K80 Sub-Family, Rev. 5, 11/2016
NXP Semiconductors
Revision History
Table 66. Revision History
Rev. No.
Date
Substantial Changes
Initial release
• Updated dimensions of 121 WLCSP package drawing
0
1
08/2014
09/2014
• Updated instances of I2S module to one
• Updated the maximum number of I/Os
• Removed DDR specs all over the datasheet
• Updated Voltage and Current Operating behaviors table
• Updated QuadSPI input timing (SDR mode) diagram
• Updated 35 pf load to load of 15pf (1.8V), 35pf (3V)
• Updated Notes in QuadSPI AC specifications section
2
03/2015
• Updated frequencies of footnotes of Power Consumption Operating behaviors table
• Added entry of VDDIO in Voltage and current operating requirements
• Updated the footnotes of Voltage and current operating ratings
• Updated the description of of Ipll in MCG specs
• Updated the minimum value of FB4 in Flexbus limited voltage range switching
specifications table
• Updated the minimum value of D5 in SDRAM Timing (Limited voltage range) table
• Added SD1 clock frequencies for high speed
• Updated the package size of 121 XFBGA to 8x8x0.5mm with a 0.65mm pitch
• Added Recommended POR sequencing topic
• Updated the typical values of Power consumption operating behaviors table
• Updated the Run mode supply current vs. core frequency diagram
• Updated the number of I2C instances in front matter and deleted "0" after LPUART
• Updated VLPR mode supply current vs. core frequency figure
3
05/2015
• Added maximum number of I/Os in the Ordering Information table.
• Updated 'Voltage and current operating ratings' table.
• Updated 'Voltage and current operating requirements' table.
• Added rows for VIH_E, VIL_E, and VHYS_E
.
• Removed IICAIO parameter description from the table.
• Removed positive current injection specifications from IICcont
• Updated footnotes.
.
• Updated 'Voltage and current operating behaviors' table.
• Updated Max. values in the 'Power mode transition operating behaviors' table.
• Corrected Typ. values of IDD_LLS2 and IDD_LLS3 in 'Power consumption operating
behaviors' table.
• Updated 'General switching specifications' table.
• Updated 'Thermal operating requirements' table to include footnotes.
• Updated Typ. and Max. values of the fdco_t parameter in the 'MCG Specifications'
table.
• Updated Max. values for SD1 (fpp) and SD6 in the 'SDHC full voltage range
switching specifications' table and for SD6 in the 'SDHC limited voltage range
switching specifications' table.
4
09/2015
• Updated part numbers.
• Updated Related Resources table to include package drawing numbers and other
relevant resource information.
• Updated title of section 2.2.2 to 'HVD, LVD and POR operating requirements'.
• Updated 'VDD supply LVD and POR operating requirements' table.
• Added rows for VHVDH and VHVDL
.
• Updated 'Power consumption operating behaviors' table.
• Updated Typ. values and Max. values.
• Added data for 105°C.
• Updated IDD charts - Figure 6. Run mode supply current vs. core frequency and
Figure 7. VLPR mode supply current vs. core frequency.
Table continues on the next page...
Kinetis K80 Sub-Family, Rev. 5, 11/2016
93
NXP Semiconductors
Revision History
Rev. No.
Table 66. Revision History (continued)
Date
Substantial Changes
• Replaced section 2.2.6 'EMC radiated emissions operating behaviors' with
'Electromagnetic Compatibility (EMC) specifications'.
• Removed EZPort information from 'General switching specifications' table.
• Updated 100 LQFP and 121 XFBGA values in the 'Thermal attributes' table.
• Updated 'MCG specifications' table
• Updated Typ. value of Δfdco_t from -1 to 1.
• Removed Jacc_fll data.
• Updated description of Ipll and their corresponding Typ. values.
• Updated Typ. values of Jcyc_pll and Jacc_pll
.
• Updated footnote 2 in 'SDRAM Timing (Full voltage range)' table - corrected
maximum frequency of FB_CLK to 75MHz.
• Removed IALKG data from 'Comparator and 6-bit DAC electrical specifications' table.
• Updated Min and Max values of Sfreq in the 'Timing Specifications, High Drive
Strength' table.
• Updated the 'Timing Requirements for Power-down Sequence' table.
• Added a footnote - "Frtcclk is ERCLK32K, and this clock must be enabled
during the power down sequence."
• Updated unit from ns to μs.
• Added 121 WLCSP pin assignment information and diagram to the Pinout section.
5
11/2016
• Added 'Device Revision Number' table.
• Removed phrase "(except RTC_WAKEUP pins)" from RPU and RPD rows in 'Voltage
and current operating behaviors' table.
• Updated 'Power consumption operating behaviors' table
• Updated Typ. and Max. values of IDD_RUN Run mode current — all peripheral
clocks enabled.
• Updated footnote 3 to "120 MHz core and system clock, 60 MHz bus and
FlexBus clock, and 24 MHz flash clock. MCG configured for PEE mode. All
peripheral clocks enabled".
• In 'Thermal operating requirements' table, in footnote corrected TJ = TA + ΘJA to TJ
= TA + RΘJA.
94
Kinetis K80 Sub-Family, Rev. 5, 11/2016
NXP Semiconductors
How to Reach Us:
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based
on the information in this document. NXP reserves the right to make changes
without further notice to any products herein.
Home Page:
nxp.com
Web Support:
nxp.com/support
NXP makes no warranty, representation, or guarantee regarding the suitability of
its products for any particular purpose, nor does NXP assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in NXP data sheets and/or
specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be
validated for each customer application by customerʼs technical experts. NXP
does not convey any license under its patent rights nor the rights of others. NXP
sells products pursuant to standard terms and conditions of sale, which can be
found at the following address: nxp.com/SalesTermsandConditions.
NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER
WORLD, Freescale, the Freescale logo, and Kinetis are trademarks of NXP B.V.
All other product or service names are the property of their respective owners.
ARM, the ARM powered logo, and Cortex are registered trademarks of ARM
Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved.
© 2014 - 2016 NXP B.V.
Document Number K80P121M150SF5
Revision 5, 11/2016
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