MKE14Z128VLL7_技术文档

NXP Semiconductors

Data Sheet: Technical Data

KE1xZP100M72SF0

Rev. 4.2, 03/2021

Kinetis KE1xZ with up to 256 KB

MKE1xZ256VLL7

MKE1xZ256VLH7

MKE1xZ128VLL7

MKE1xZ128VLH7

Flash

Up to 72 MHz ARM® Cortex®-M0+ Based Microcontroller

Kinetis KE1xZ256 MCUs are the leading parts for the KE1xZ

familiy based on ARM^®Cortex^®-M0+ core. Providing up to 256

KB flash, up to 32 KB RAM, and the complete set of analog/

digital features, KE1xZ extends Kinetis E family to higher

performance and broader scalability. Robust TSI provides high-

level stability and accuracy to customer's HMI system. 1 Msps

ADC and FlexTimer help build a perfect solution for BLDC motor

control systems.

100 LQFP (LL)

14x14x1.4 mm P 0.5

64 LQFP (LH)

10x10x1.4 mm P 0.5

Core Processor and System

• ARM^®Cortex^®-M0+ core, supports up to 72 MHz

frequency

Memory and memory interfaces

• Up to 256 KB program flash

• Up to 32 KB SRAM

• ARM Core based on the ARMv6 Architecture and

• 32 KB FlexNVM for data flash and with EEPROM

emulation

Thumb^®-2 ISA

• Configurable Nested Vectored Interrupt Controller

(NVIC)

• 2 KB FlexRAM for EEPROM emulation

• 128 Bytes flash cache

• Memory-Mapped Divide and Square Root module

(MMDVSQ)

• 8-channel DMA controller extended up to 63 channels

with DMAMUX

• Boot ROM with built in bootloader

Mixed-signal analog

• 2× 12-bit analog-to-digital converter (ADC) with up

to 16 channel analog inputs per module, up to 1

Msps

Reliability, safety and security

• Flash Access Control (FAC)

• 2× high-speed analog comparators (CMP) with

internal 8-bit digital to analog converter (DAC); the

8-bit DAC of CMP0 supports an output option to pad

with a buffer

• Cyclic Redundancy Check (CRC) generator module

• 128-bit unique identification (ID) number

• Internal watchdog (WDOG) with independent clock

source

Timing and control

• External watchdog monitor (EWM) module

• ADC self calibration feature

• On-chip clock loss monitoring

• 3× Flex Timers (FTM) for PWM generation, offering

up to 8 standard channels

• 1× 16-bit Low-Power Timer (LPTMR) with flexible

wake up control

Human-machine interface (HMI)

• Supports up to 32 interrupt request (IRQ) sources

• Up to 89 GPIO pins with interrupt functionality

• Touch sensing input (TSI) module

• 1× Programmable Delay Block (PDB) with flexible

trigger system

• 1× 32-bit Low-power Periodic Interrupt Timer (LPIT)

with 4 channels

• Real timer clock (RTC)

NXP reserves the right to change the production detail specifications as may be

required to permit improvements in the design of its products.

Clock interfaces

Connectivity and communications interfaces

• 3× low-power universal asynchronous receiver/

transmitter (LPUART) modules with DMA support

and low power availability

• 4 - 40 MHz fast external oscillator (OSC)

• 32 kHz slow external oscillator (OSC32)

• 48 - 60 MHz high-accuracy (up to 1ꢀ) fast internal

reference clock (FIRC) for normal Run

• 8 MHz / 2 MHz high-accuracy (up to 3ꢀ) slow internal

reference clock (SIRC) for low-speed Run

• 128 kHz low power oscillator (LPO)

• Low-power FLL (LPFLL)

• 2× low-power serial peripheral interface (LPSPI)

modules with DMA support and low power

availability

• 2× low-power inter-integrated circuit (LPI2C)

modules with DMA support and low power

availability

• Up to 60 MHz DC external square wave input clock

• System clock generator (SCG)

• Real time counter (RTC)

• FlexIO module for flexible and high performance

serial interfaces

Power management

Debug functionality

• Low-power ARM Cortex-M0+ core with excellent

energy efficiency

• Power management controller (PMC) with multiple

power modes: Run, Wait, Stop, VLPR, VLPW and

VLPS

• Serial Wire Debug (SWD) debug interface

• Debug Watchpoint and Trace (DWT)

• Micro Trace Buffer (MTB)

Operating Characteristics

• Voltage range: 2.7 to 5.5 V

• Ambient temperature range: –40 to 105 °C

• Supports clock gating for unused modules, and specific

peripherals remain working in low power modes

• POR, LVD/LVR

Related Resources

Type

Selector

Guide

Description

Resource

Solution Advisor

The Solution Advisor is a web-based tool that features interactive

application wizards and a dynamic product selector.

Product Brief The Product Brief contains concise overview/summary information to

enable quick evaluation of a device for design suitability.

KE1xZ256PB ¹

Reference

Manual

The Reference Manual contains a comprehensive description of the

structure and function (operation) of a device.

KE1xZP100M72SF0RM ¹

Data Sheet

The Data Sheet includes electrical characteristics and signal

connections.

This document:

KE1xZP100M72SF0

Chip Errata

The chip mask set Errata provides additional or corrective information for Kinetis_E_1N36S ¹

a particular device mask set.

Kinetis_E_2N36S ¹

Package

drawing

Package dimensions are provided in package drawings.

100-LQFP: 98ASS23308W

64-LQFP: 98ASS23234W

1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.

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Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

NXP Semiconductors

Kinetis KE1xZ Sub-Family

ARM^®Cortex^®-M0+

System

eDMA

Memories and Memory Interfaces

Clocks

OSC

Core

Program

flash

RAM

FIRC

SIRC

LPFLL

OSC32

LPO

DMAMUX

Debug

interfaces

FlexMemory

Boot ROM

MMDVSQ

TRGMUX

WDOG

EWM

Interrupt

controller

Security

Communication Interfaces

Human-Machine

Interface (HMI)

Analog

Timers

and Integrity

LPI ²C

x2

FlexTimer

8ch x1

4ch x2

12-bit ADC

GPIO

CRC

upto 89

x2

LPUART

x3

High drive

I/O (8 pins)

CMP x2

FAC

PDB x1

8-bit DAC x1

LPSPI

x2

Digital filters

(port E)

(within CMP0,

LPIT, 4ch

output capable)

PMC

LPTMR

SRTC

PWT

TSI, 25ch

(optional)

FlexIO

Figure 1. Functional block diagram

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

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NXP Semiconductors

Table of Contents

1 Ordering information............................................................... 5

5.1.3

5.1.4

Typical-value conditions....................................41

2 Overview................................................................................. 5

2.1 System features...............................................................6

Relationship between ratings and operating

requirements..................................................... 41

Guidelines for ratings and operating

2.1.1

2.1.2

2.1.3

2.1.4

2.1.5

2.1.6

2.1.7

2.1.8

2.1.9

ARM Cortex-M0+ core...................................... 6

NVIC..................................................................7

AWIC.................................................................7

Memory............................................................. 8

Reset and boot..................................................8

Clock options.....................................................10

Security............................................................. 11

Power management..........................................12

Debug controller................................................13

5.1.5

requirements..................................................... 42

5.2 Ratings............................................................................ 42

5.2.1

5.2.2

5.2.3

5.2.4

Thermal handling ratings...................................42

Moisture handling ratings..................................43

ESD handling ratings........................................ 43

Voltage and current operating ratings...............43

5.3 General............................................................................44

5.3.1

5.3.2

5.3.3

Nonswitching electrical specifications...............44

Switching specifications.................................... 54

Thermal specifications...................................... 57

2.2 Peripheral features.......................................................... 13

2.2.1

2.2.2

2.2.3

2.2.4

2.2.5

2.2.6

2.2.7

2.2.8

2.2.9

eDMA and DMAMUX........................................ 13

FTM...................................................................14

ADC...................................................................14

CMP.................................................................. 15

RTC...................................................................16

LPIT...................................................................16

PDB...................................................................17

LPTMR..............................................................17

CRC.................................................................. 17

5.4 Peripheral operating requirements and behaviors...........60

5.4.1

5.4.2

5.4.3

5.4.4

5.4.5

5.4.6

5.4.7

5.4.8

System modules................................................60

Clock interface modules....................................60

Memories and memory interfaces.....................67

Security and integrity modules..........................69

Analog...............................................................70

Communication interfaces.................................76

Human-machine interfaces (HMI)..................... 80

Debug modules.................................................80

2.2.10 LPUART............................................................18

2.2.11 LPSPI................................................................18

2.2.12 LPI2C................................................................ 19

2.2.13 FlexIO................................................................20

2.2.14 Port control and GPIO.......................................20

3 Memory map........................................................................... 22

4 Pinouts.................................................................................... 24

4.1 KE1xZ Signal Multiplexing and Pin Assignments............ 24

4.2 Port control and interrupt summary................................. 27

4.3 Module Signal Description Tables................................... 28

4.4 Pinout diagram................................................................ 33

4.5 Package dimensions....................................................... 35

5 Electrical characteristics..........................................................40

5.1 Terminology and guidelines.............................................40

6 Design considerations.............................................................81

6.1 Hardware design considerations..................................... 82

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

Printed circuit board recommendations.............82

Power delivery system...................................... 82

Analog design................................................... 82

Digital design.....................................................83

Crystal oscillator................................................86

6.2 Software considerations.................................................. 87

7 Part identification.....................................................................88

7.1 Description.......................................................................88

7.2 Format............................................................................. 88

7.3 Fields............................................................................... 88

7.4 Example...........................................................................89

8 Revision history.......................................................................89

5.1.1

5.1.2

Definitions......................................................... 40

Examples.......................................................... 40

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Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

NXP Semiconductors

Ordering information

1 Ordering information

The following chips are available for ordering.

Table 1. Ordering information

Product

Memory

Package

IO and ADC channel

HMI

TSI

Part number

Flash

(KB)

SRAM

(KB)

FlexNVM/

FlexRAM

(KB)

Packag GPIOs

e

GPIOs

ADC

count

(INT/HD channel

1

)

s

MKE15Z256VLL7

MKE15Z256VLH7

MKE15Z128VLL7

MKE15Z128VLH7

MKE14Z256VLL7

MKE14Z256VLH7

MKE14Z128VLL7

MKE14Z128VLH7

256

128

256

128

32

16

32

16

32/2

100

64

LQFP

89

58

89

58

89

58

89

58

89/8

58/8

89/8

58/8

89/8

58/8

89/8

58/8

16+12

16+11

16+12

16+11

16+12

16+11

16+12

16+11

Yes

No

100

64

100

64

No

100

64

No

1. INT: interrupt pin numbers; HD: high drive pin numbers

2 Overview

The following figure shows the system diagram of this device.

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

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NXP Semiconductors

Overview

Slave

Master

M0

Cortex M0+

IOPORT

unified bus

for core

Flash

upto 256 KB

FMC

Debug

(SWD)

CM0+ core

S0

S1

NVIC

8 KB ROM

SRAM

upto 32 KB

various

peripheral

blocks

M2

DMA

MUX

eDMA

S2

MUX

System Clock Generator (SCG)

Fast IRC

Slow IRC

SOSC

LPFLL

Clock

Source

OSC32

LPO

Figure 2. System diagram

The crossbar switch connects bus masters and slaves using a crossbar switch structure.

This structure allows up to four bus masters to access different bus slaves

simultaneously, while providing arbitration among the bus masters when they access

the same slave.

2.1 System features

The following sections describe the high-level system features.

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Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

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Overview

2.1.1 ARM Cortex-M0+ core

The enhanced ARM Cortex M0+ is the member of the Cortex-M Series of processors

targeting microcontroller cores focused on very cost sensitive, low power

applications. It has a single 32-bit AMBA AHB-Lite interface and includes an NVIC

component. It also has hardware debug functionality including support for simple

program trace capability. The processor supports the ARMv6-M instruction set

(Thumb) architecture including all but three 16-bit Thumb opcodes (52 total) plus

seven 32-bit instructions. It is upward compatible with other Cortex-M profile

processors.

2.1.2 NVIC

The Nested Vectored Interrupt Controller supports nested interrupts and 4 priority

levels for interrupts. In the NVIC, each source in the IPR registers contains 2 bits. It

also differs in number of interrupt sources and supports 32 interrupt vectors.

The Cortex-M family uses a number of methods to improve interrupt latency to up to

15 clock cycles for Cortex-M0+. It also can be used to wake the MCU core from Wait

and VLPW modes.

2.1.3 AWIC

The asynchronous wake-up interrupt controller (AWIC) is used to detect

asynchronous wake-up events in Stop mode and signal to clock control logic to

resume system clocking. After clock restarts, the NVIC observes the pending interrupt

and performs the normal interrupt or event processing. The AWIC can be used to

wake MCU core from Partial Stop, Stop and VLPS modes.

Wake-up sources for this SoC are listed as below:

Table 2. AWIC Stop and VLPS Wake-up Sources

Wake-up source

Available system resets

Pin interrupts

ADCx

Description

RESET pin, WDOG , loss of clock(LOC) reset and loss of lock (LOL) reset

Port Control Module - Any enabled pin interrupt is capable of waking the system

ADCx is optional functional with clock source from SIRC or OSC

Functional in Stop/VLPS modes with clock source from SIRC or OSC

CMPx

LPI2C

LPUART

Table continues on the next page...

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

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NXP Semiconductors

Overview

Table 2. AWIC Stop and VLPS Wake-up Sources (continued)

Wake-up source

LPSPI

LPIT

Description

Functional in Stop/VLPS modes with clock source from SIRC or OSC

Functional in Stop/VLPS modes

FlexIO

LPTMR

RTC

Functional in Stop/VLPS modes

SCG

Functional in Stop mode (Only SIRC)

TSI

Touch sense wakeup

NMI

Non-maskable interrupt

2.1.4 Memory

This device has the following features:

• Upto 256 KB of embedded program flash memory.

• Upto 32 KB of embedded RAM accessible (read/write) at CPU clock speed with 0

wait states.

• The non-volatile memory is divided into several arrays:

• 32 KB of embedded data flash memory

• 2 KB of Emulated EEPROM

• 8 KB ROM (built-in bootloader to support UART, I2C, and SPI interfaces)

The program flash memory contains a 16-byte flash configuration field that stores

default protection settings and security information. The page size of program flash

is 1 KB.

The protection setting can protect 32 regions of the program flash memory from

unintended erase or program operations.

The security circuitry prevents unauthorized access to RAM or flash contents from

debug port.

2.1.5 Reset and boot

The following table lists all the reset sources supported by this device.

NOTE

In the following table, Y means the specific module, except

for the registers, bits or conditions mentioned in the footnote,

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Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

NXP Semiconductors

Overview

is reset by the corresponding Reset source. N means the

specific module is not reset by the corresponding Reset

source.

Table 3. Reset source

Reset

Descriptions

Modules

sources

PMC SIM SMC RCM

Reset

pin is

WDO SCG RTC LPTM Other

G

R

s

negated

POR reset

Power-on reset (POR)

Y

Y¹

Y

N

Y

System

resets

Low-voltage detect

(LVD)

External pin reset

(RESET)

Y¹

Y²

Y³

Y⁴

Y

Y⁵

Y⁶

N

Y

Watchdog (WDOG)

reset

Multipurpose clock

generator loss of clock

(LOC) reset

Multipurpose clock

generator loss of lock

(LOL) reset

Stop mode acknowledge Y¹

error (SACKERR)

Y¹

Y²

Y³

Y⁴

Y

Y⁵

Y⁶

N

Y

Software reset (SW)

Y¹

Y²

Y³

Y⁴

Y

Y⁵

Y⁶

N

Y

Lockup reset (LOCKUP)

MDM DAP system reset

Debug reset Debug reset

1. Except PMC_LVDSC1[LVDV] and PMC_LVDSC2[LVWV]

2. Except SIM_SOPT1

3. Except SMC_PMPROT, SMC_PMCTRL_RUM, SMC_PMCTRL_STOPM, SMC_STOPCTRL, SMC_PMSTAT

4. Except RCM_RPC, RCM_MR, RCM_FM, RCM_SRIE, RCM_SRS, RCM_SSRS

5. Except WDOG_CS[TST]

6. Except SCG_CSR and SCG_FIRCSTAT

This device supports booting from:

• internal flash

• boot ROM

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

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NXP Semiconductors

Overview

POR or Reset

N

RCM[FORCEROM] =00

Y

N

FOPT[BOOTPIN_OPT]=0

Y

BOOTCFG0 pin=0

Y

N

FOPT[BOOTSRC

_SEL]=10/11

Y

Boot from ROM

Boot from Flash

Figure 3. Boot flow chart

The blank chip is default to boot from ROM and remaps the vector table to ROM base

address, otherwise, it remaps to flash address.

2.1.6 Clock options

The SCG module controls which clock source is used to derive the system clocks. The

clock generation logic divides the selected clock source into a variety of clock domains,

including the clocks for the system bus masters, system bus slaves, and flash memory .

The clock generation logic also implements module-specific clock gating to allow

granular shutoff of modules.

The following figure is a high level block diagram of the clock generation. For more

details on the clock operation and configuration, see the Clocking chapter in the

Reference Manual.

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Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

NXP Semiconductors

Overview

00

01

10

11

PWT

TCLK0

TCLK1

TCLK2

00

01

SIM_CHIPCTL[PWTCLKSEL]

SIM_FTMOPT0[FTMxCLKSEL]

10

11

FTMx

SCG

SCG_LPFLLTCFG[TRIMSRC]

Core

RAM

GPIOC

48 MHz

Fast

IRC

01

00

0101

LPFLL

TRIMDIV

(SCG_LFLLTCFG)

10

11

DMAMUX

eDMA

PDB

0011

0010

default start up

DIVCORE

CORE_CLK/SYS_CLK

8MHz/2MHz

Slow

IRC

PCC

0001

Other

SYS_CLK

CRC

8-bit DAC

ACMPx

TSI

PCC_xxx[CGC]

BUS_CLK/FLASH_CLK

SCG_xCCR[SCS]

(x=R, V, H)

DIVSLOW

BUSOUT

FLL_CLK

FLLDIV2_CLK

FLLDIV2

Flash

Peripheral

Registers

SIRC_CLK

FIRC_CLK

SIRCDIV2_CLK

FIRCDIV2_CLK

ADCx

FlexIO

LPIT

SIRCDIV2

Async clock

FIRCDIV2

SCG_SOSCCFG[EREFS]

LPI2Cx

LPUARTx

LPSPIx

0

SOSCDIV2_CLK

SOSC_CLK

SOSCDIV2

EXTAL

High Range

OSC

1

PCC_xxx[PCS]

Other 0000 0001 0011 0010 0101

SCG_CLKOUTCNFG

[CLKOUTSEL]

XTAL

SCG_SOSCCSR

[SOSCERCLKEN]

OSC

OSC32_CR[ROSCEREFS]

0

SCG CLKOUT

00

WDOG

01

10

CLKOUTDIV

CLKOUT

EXTAL32

XTAL32

Low Range

OSC

11

1

SIM_CHIPCTL[CLKOUTSEL]

OSC32

LPO_CLK

OSC32_CLK

LPTMR

EWM

RTC

1kHz

LPO128K

1

÷128

PMC

RTC_CLKOUT

00

01

10

11

32kHz

RTC_CLKIN

0

PORT Control

RTC_CR[LPOS]

SIM_CHIPCTL[RTC32KCLKSEL]

Figure 4. Clocking block diagram

2.1.7 Security

Security state can be enabled via programming flash configure field (0x40e). After

enabling device security, the SWD port cannot access the memory resources of the

MCU.

External interface

Security

Unsecure

SWD port

Can't access memory source by SWD the debugger can write to the Flash

interface

Mass Erase in Progress field of the

MDM-AP Control register to trigger a

mass erase (Erase All Blocks)

command

2.1.7.1 Flash Access Control (FAC)

The FAC is a native or third-party configurable memory protection scheme optimized

to allow end users to utilize software libraries while offering programmable

restrictions to these libraries. The flash memory is divided into equal size segments

that provide protection to proprietary software libraries. The protection of these

segments is controlled as the FAC provides a cycle-by-cycle evaluation of the access

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

11

NXP Semiconductors

Overview

rights for each transaction routed to the on-chip flash memory. Configurability allows

an increasing number of protected segments while supporting two levels of vendors

adding their proprietary software to a device.

2.1.8 Power management

The Power Management Controller (PMC) expands upon ARM’s operational modes of

Run, Sleep, and Deep Sleep, to provide multiple configurable modes. These modes can

be used to optimize current consumption for a wide range of applications. The WFI or

WFE instruction invokes a Wait or a Stop mode, depending on the current

configuration. For more information on ARM’s operational modes, See the ARM^®

Cortex^®User Guide.

The PMC provides Normal Run (RUN), and Very Low Power Run (VLPR)

configurations in ARM’s Run operation mode. In these modes, the MCU core is active

and can access all peripherals. The difference between the modes is the maximum clock

frequency of the system and therefore the power consumption. The configuration that

matches the power versus performance requirements of the application can be selected.

The PMC provides Wait (Wait) and Very Low Power Wait (VLPW) configurations in

ARM’s Sleep operation mode. In these modes, even though the MCU core is inactive,

all of the peripherals can be enabled and operate as programmed. The difference

between the modes is the maximum clock frequency of the system and therefore the

power consumption.

The PMC provides Stop (Stop), Very Low Power Stop (VLPS) configurations in

ARM’s Deep Sleep operational mode. In these modes, the MCU core and most of the

peripherals are disabled. Depending on the requirements of the application, different

portions of the analog, logic, and memory can be retained or disabled to conserve

power.

The Nested Vectored Interrupt Controller (NVIC), the Asynchronous Wake-up

Interrupt Controller (AWIC) are used to wake up the MCU from low power states. The

NVIC is used to wake up the MCU core from WAIT and VLPW modes. The AWIC is

used to wake up the MCU core from STOP and VLPS modes.

For additional information regarding operational modes, power management, the NVIC,

AWIC, please refer to the Reference Manual.

The following table provides information about the state of the peripherals in the

various operational modes and the modules that can wake MCU from low power

modes.

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Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

NXP Semiconductors

Overview

Table 5. Peripherals states in different operational modes

Core mode

Device mode

Descriptions

Run mode

Run

In Run mode, all device modules are operational.

Very Low Power Run

In VLPR mode, all device modules are operational at a reduced frequency

except the Low Voltage Detect (LVD) monitor, which is disabled.

Sleep mode

Deep sleep

Wait

In Wait mode, all peripheral modules are operational. The MCU core is

placed into Sleep mode.

Very Low Power Wait

In VLPW mode, all peripheral modules are operational at a reduced

frequency except the Low Voltage Detect (LVD) monitor, which is disabled.

The MCU core is placed into Sleep mode.

Stop

In Stop mode, most peripheral clocks are disabled and placed in a static

state. Stop mode retains all registers and SRAMs while maintaining Low

Voltage Detection protection. In Stop mode, the ADC, CMP, LPTMR, RTC,

and pin interrupts are operational. The NVIC is disabled, but the AWIC can

be used to wake up from an interrupt.

Very Low Power Stop

In VLPS mode, the contents of the SRAM are retained. The CMP (low

speed), ADC, OSC, RTC, LPTMR, LPIT, FlexIO, LPUART, LPI2C,LPSPI,

and DMA are operational, LVD and NVIC are disabled, AWIC is used to

wake up from interrupt.

NOTE

When the MCU is in HSRUN or VLP mode, user cannot

write FlexRAM (EEPROM), and cannot launch an FTFE

command including flash programming/erasing.

2.1.9 Debug controller

This device has extensive debug capabilities including run control and tracing

capabilities. The standard ARM debug port supports SWD interface.

2.2 Peripheral features

The following sections describe the features of each peripherals of the chip.

2.2.1 eDMA and DMAMUX

The eDMA is a highly programmable data-transfer engine optimized to minimize any

required intervention from the host processor. It is intended for use in applications

where the data size to be transferred is statically known and not defined within the

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

13

NXP Semiconductors

Overview

transferred data itself. The DMA controller in this device implements 8 channels which

can be routed from up to 63 DMA request sources through DMA MUX module.

Main features of eDMA are listed below:

• All data movement via dual-address transfers: read from source, write to

destination

• 8-channel implementation that performs complex data transfers with minimal

intervention from a host processor

• Transfer control descriptor (TCD) organized to support two-deep, nested transfer

operations

• Channel activation via one of three methods

• Fixed-priority and round-robin channel arbitration

• Channel completion reported via programmable interrupt requests

• Programmable support for scatter/gather DMA processing

• Support for complex data structures

2.2.2 FTM

This device contains three FlexTimer modules.

The FlexTimer module (FTM) is a two-to-eight channel timer that supports input

capture, output compare, and the generation of PWM signals to control electric motor

and power management applications. The FTM time reference is a 16-bit counter that

can be used as an unsigned or signed counter.

Several key enhancements of this module are made:

• Signed up counter

• Deadtime insertion hardware

• Fault control inputs

• Enhanced triggering functionality

• Initialization and polarity control

2.2.3 ADC

This device contains two 12-bit SAR ADC modules. The ADC module supports

hardware triggers from FTM, LPTMR, PIT, RTC, external trigger pin and CMP output.

It supports wakeup of MCU in low power mode when using internal clock source or

external crystal clock.

ADC module has the following features:

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Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

NXP Semiconductors

Overview

• Linear successive approximation algorithm with up to 12-bit resolution

• Up to 16 single-ended external analog inputs

• Support 12-bit, 10-bit, and 8-bit single-ended output modes

• Single or continuous conversion

• Configurable sample time and conversion speed/power

• Input clock selectable from up to four sources

• Operation in low-power modes for lower noise

• Selectable hardware conversion trigger

• Automatic compare with interrupt for less-than, greater-than or equal-to, within

range, or out-of-range, programmable value

• Temperature sensor

• Hardware average function

• Selectable Voltage reference: from external or alternate

• Self-Calibration mode

2.2.3.1 Temperature sensor

This device contains one temperature sensor internally connected to the input channel

of AD26, see ADC electrical characteristics for details of the linearity factor.

The sensor must be calibrated to gain good accuracy, so as to provide good linearity,

see also AN3031 for more detailed application information of the temperature sensor.

2.2.4 CMP

There aretwo analog comparators on this device.

• Each CMP has its own independent 8-bit DAC.

• Each CMP supports up to 6 analog inputs from external pins.

• Each CMP is able to convert an internal reference from the bandgap.

• Each CMP supports the round-robin sampling scheme. In summary, this allow the

CMP to operate independently in VLPS and Stop modes, whilst being triggered

periodically to sample up to 8 inputs. Only if an input changes state is a full

wakeup generated.

The CMP has the following features:

• Inputs may range from rail to rail

• Programmable hysteresis control

• Selectable interrupt on rising-edge, falling-edge, or both rising and falling edges

of the comparator output

• Selectable inversion on comparator output

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

15

NXP Semiconductors

Overview

• Capability to produce a wide range of outputs such as sampled, windowed, or

digitally filtered

• External hysteresis can be used at the same time that the output filter is used for

internal functions

• Two software selectable performance levels: Shorter propagation delay at the

expense of higher power, and Low power with longer propagation delay

• DMA transfer support

• Functional in all power modes available on this MCU

• The window and filter functions are not available in STOP mode

• Integrated 8-bit DAC with selectable supply reference source and can be power

down to conserve power

2.2.5 RTC

The RTC is an always powered-on block that remains active in all low power modes.

The time counter within the RTC is clocked by a 32.768 kHz clock sourced from an

external crystal using the oscillator, or clock directly from RTC_CLKIN pin.

RTC is reset on power-on reset, and a software reset bit in RTC can also initialize all

RTC registers.

The RTC module has the following features

• 32-bit seconds counter with roll-over protection and 32-bit alarm

• 16-bit prescaler with compensation that can correct errors between 0.12 ppm and

3906 ppm

• Register write protection with register lock mechanism

• 1 Hz square wave or second pulse output with optional interrupt

2.2.6 LPIT

The Low Power Periodic Interrupt Timer (LPIT) is a multi-channel timer module

generating independent pre-trigger and trigger outputs. These timer channels can

operate individually or can be chained together. The LPIT can operate in low power

modes if configured to do so. The pre-trigger and trigger outputs can be used to trigger

other modules on the device.

This device contains one LPIT module with four channels. The LPIT generates periodic

trigger events to the DMAMUX.

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Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

NXP Semiconductors

Overview

2.2.7 PDB

The Programmable Delay Block (PDB) provides controllable delays from either an

internal or an external trigger, or a programmable interval tick, to the hardware trigger

inputs of ADCs and/or generates the interval triggers to DACs, so that the precise

timing between ADC conversions and/or DAC updates can be achieved. The PDB can

optionally provide pulse outputs (Pulse-Out's) that are used as the sample window in

the CMP block.

The PDB module has the following capabilities:

• trigger input sources and one software trigger source

• 1 DAC refresh trigger output, for this device

• configurable PDB channels for ADC hardware trigger

• 1 pulse output, for this device

2.2.8 LPTMR

The low-power timer (LPTMR) can be configured to operate as a time counter with

optional prescaler, or as a pulse counter with optional glitch filter, across all power

modes, including the low-leakage modes. It can also continue operating through most

system reset events, allowing it to be used as a time of day counter.

The LPTMR module has the following features:

• 16-bit time counter or pulse counter with compare

• Optional interrupt can generate asynchronous wakeup from any low-power

mode

• Hardware trigger output

• Counter supports free-running mode or reset on compare

• Configurable clock source for prescaler/glitch filter

• Configurable input source for pulse counter

2.2.9 CRC

This device contains one cyclic redundancy check (CRC) module which can generate

16/32-bit CRC code for error detection.

The CRC module provides a programmable polynomial, WAS, and other parameters

required to implement a 16-bit or 32-bit CRC standard.

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

17

NXP Semiconductors

Overview

The CRC module has the following features:

• Hardware CRC generator circuit using a 16-bit or 32-bit programmable shift

register

• Programmable initial seed value and polynomial

• Option to transpose input data or output data (the CRC result) bitwise or bytewise.

• Option for inversion of final CRC result

• 32-bit CPU register programming interface

2.2.10 LPUART

This product contains three Low-Power UART modules, and can work in Stop and

VLPS modes. The module also supports 4× to 32× data oversampling rate to meet

different applications.

The LPUART module has the following features:

• Programmable baud rates (13-bit modulo divider) with configurable oversampling

ratio from 4× to 32×

• Transmit and receive baud rate can operate asynchronous to the bus clock and can

be configured independently of the bus clock frequency, support operation in Stop

mode

• Interrupt, DMA or polled operation

• Hardware parity generation and checking

• Programmable 8-bit, 9-bit or 10-bit character length

• Programmable 1-bit or 2-bit stop bits

• Three receiver wakeup methods

• Idle line wakeup

• Address mark wakeup

• Receive data match

• Automatic address matching to reduce ISR overhead:

• Address mark matching

• Idle line address matching

• Address match start, address match end

• Optional 13-bit break character generation / 11-bit break character detection

• Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle

characters

• Selectable transmitter output and receiver input polarity

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Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

NXP Semiconductors

Overview

2.2.11 LPSPI

This device contains two LPSPI modules. The LPSPI is a low power Serial Peripheral

Interface (SPI) module that supports an efficient interface to an SPI bus as a master

and/or a slave. The LPSPI can continue operating in stop modes provided an

appropriate clock is available and is designed for low CPU overhead with DMA

offloading of FIFO register accesses.

The LPSPI module has the following features:

• Command/transmit FIFO of 4 words

• Receive FIFO of 4 words

• Host request input can be used to control the start time of an SPI bus transfer

2.2.12 LPI2C

This device contains two LPI2C modules. The LPI2C is a low power Inter-Integrated

Circuit (I2C) module that supports an efficient interface to an I2C bus as a master

and/or a slave. The LPI2C can continue operating in stop modes provided an

appropriate clock is available and is designed for low CPU overhead with DMA

offloading of FIFO register accesses. The LPI2C implements logic support for

standard-mode, fast-mode, fast-mode plus and ultra-fast modes of operation. The

LPI2C module also complies with the System Management Bus (SMBus)

Specification, version 2.

The LPI2C modules have the following features:

• Standard, Fast, Fast+ and Ultra Fast modes are supported

• HS-mode supported in slave mode

• Multi-master support including synchronization and arbitration

• Clock stretching

• General call, 7-bit and 10-bit addressing

• Software reset, START byte and Device ID require software support

• For master mode:

• command/transmit FIFO of 4 words

• receive FIFO of 4 words

• For slave mode:

• separate I2C slave registers to minimize software overhead due to master/

slave switching

• support for 7-bit or 10-bit addressing, address range, SMBus alert and general

call address

• transmit/receive data register supporting interrupt or DMA requests

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

19

NXP Semiconductors

Overview

2.2.13 FlexIO

The FlexIO is a highly configurable module providing a wide range of protocols

including, but not limited to UART, I2C, SPI, Camera IF, LCD RGB, PWM/Waveform

generation. The module supports programmable baud rates independent of bus clock

frequency, with automatic start/stop bit generation.

The FlexIO module has the following features:

• Functional in VLPR/VLPW/Stop/VLPS mode provided the clock it is using

remains enabled

• Four 32-bit double buffered shift registers with transmit, receive, and data match

modes, and continuous data transfer

• The timing of the shifter's shift, load and store events are controlled by the highly

flexible 16-bit timer assigned to the shifter

• Two or more shifters can be concatenated to support large data transfer sizes

• Each 16-bit timers operates independently, supports for reset, enable and disable on

a variety of internal or external trigger conditions with programmable trigger

polarity

• Flexible pin configuration supporting output disabled, open drain, bidirectional

output data and output mode

• Supports interrupt, DMA or polled transmit/receive operation

2.2.14 Port control and GPIO

The Port Control and Interrupt (PORT) module provides support for port control, digital

filtering, and external interrupt functions. The GPIO data direction and output data

registers control the direction and output data of each pin when the pin is configured for

the GPIO function. The GPIO input data register displays the logic value on each pin

when the pin is configured for any digital function, provided the corresponding Port

Control and Interrupt module for that pin is enabled.

The following figure shows the basic I/O pad structure. Pseudo open-drain pins have

the p-channel output driver disabled when configured for open-drain operation. None of

the I/O pins, including open-drain and pseudo open-drain pins, are allowed to go above

VDD.

NOTE

The RESET_b pin is also a normal I/O pad with pseudo open-

drain.

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Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

NXP Semiconductors

Overview

Digital input

IBE=1 whenever

MUX≠000

IFE

IBE

LPF

ESD

Bus

VDD

RPULL

PE

PS

Analog input

Digital output

DSE

Figure 5. I/O simplified block diagram

The PORT module has the following features:

• all PIN support interrupt enable

• Configurable edge (rising, falling, or both) or level sensitive interrupt type

• Support DMA request

• Asynchronous wake-up in low-power modes

• Configurable pullup, pulldown, and pull-disable on select pins

• Configurable high and low drive strength on selected pins

• Configurable passive filter on selected pins

• Individual mux control field supporting analog or pin disabled, GPIO, and up to

chip-specific digital functions

• Pad configuration fields are functional in all digital pin muxing modes.

The GPIO module has the following features:

• Port Data Input register visible in all digital pin-multiplexing modes

• Port Data Output register with corresponding set/clear/toggle registers

• Port Data Direction register

• GPIO support single-cycle access via fast GPIO.

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

21

NXP Semiconductors

Memory map

3 Memory map

This device contains various memories and memory-mapped peripherals which are

located in a 4 GB memory space. For more details of the system memory and peripheral

locations, see the Memory Map chapter in the Reference Manual.

22

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

NXP Semiconductors

Memory map

0x4000_0000

0x4000_1000

AIPS-Lite

Reserved

0x4000_2000

0x4000_8000

0x4000_9000

0x4000_A000

Reserved

Note:

eDMA

The size of Flash and SRAM varies for

devices with different part numbers.

See "Ordering information" in DataSheet for details.

DMA TCD

Reserved

0x4000_F000

0x4001_0000

GPIO controller(aliased to 400F_F000)

Reserved

0x0000_0000

Flash *

0x0003_FFFF

0x4002_0000

Flash memory unit

0x4002_1000

0x4002_2000

DMAMUX0

Reserved

0x0000_0000

0x07FF_FFFF

0x4002_7000

0x4002_8000

0x4002_C000

ADC1

Code space

Reserved

0x0800_0000

0x1000_0000

0x1000_8000

Reserved

LPSPI0

0x4002_D000

0x4002_E000

0x4003_2000

LPSPI1

Reserved

FlexNVM

Reserved

CRC

Reserved

0x1400_0000

0x1400_0800

0x1800_0000

FlexRAM

0x4003_3000

0x4003_6000

Reserved

PDB0

LPIT0

0x1C00_0000

0x4003_7000

0x4003_8000

0x4003_9000

0x1C00_0000

FTM0

FTM1

FTM2

ROM

Boot ROM

0x4003_A000

0x1C00_3FFF

0x4003_B000

0x4003_C000

0x4003_D000

0x4003_E000

0x4004_0000

ADC0

Reserved

0x1C00_4000

0x1FF0_0000

Reserved

Data Space

Reserved

0x1FF0_0000

SRAM_L

0x2000_0000

RTC

Reserved

0x2010_0000

0x2200_0000

LPTMR0

SRAM_U

0x200F_FFFF

Aliased to SRAM_U

bit-band region

0x4004_1000

Reserved

0x4004_5000

0x4004_6000

0x4004_8000

0x4004_9000

0x2400_0000

0x4000_0000

TSI0

Reserved

SIM

Public

peripheral

PORT A

PORT B

PORT C

PORT D

0x4000_0000

0x4004_A000

AIPS

peripherals

0x4004_B000

0x4004_C000

0x4010_0000

0x4400_0000

Reserved

0x4004_D000

PORT E

Reserved

0x4008_0000

Reserved

BME

0x4004_E000

0x4005_2000

0x4005_3000

0x400F_F000

GPIO

WDOG

Reserved

0x6000_0000

0xE000_0000

0x400F_FFFF

Reserved

0xE000_0000

0x4005_6000

Reserved

PWT

Reserved

0xE000_E000

System

0x4005_7000

0x4005_A000

FlexIO0

Reserved

control

space

0x4005_B000

0x4006_0000

0x4006_1000

Private

peripheral

OSC32

0xE000_F000

Reserved

EWM

TRGMUX0

0x4006_2000

0x4006_3000

0xE00F_F000

Core

0xE010_0000

0xF000_0000

TRGMUX1

SCG

ROM table

0x4006_4000

0x4006_5000

0x4006_6000

0x4006_7000

0xE00F_FFFF

Reserved

PCC

LPI2C0

0xF000_0000

MTB

0xF000_1000

MTBDWT

LPI2C1

Reserved

0x4006_8000

0x4006_A000

0xF000_2000

ROM Table

LPUART0

LPUART1

Private

peripheral

bus

0x4006_B000

0xF000_3000

MCM

0x4006_C000

0x4006_D000

0x4007_3000

0x4007_4000

LPUART2

Reserved

0xF000_4000

MMDVSQ

CMP0

0xF000_5000

CMP1

0xFFFF_FFFF

Reserved

0x4007_5000

0x4007_D000

0x4007_E000

Reserved

0xF800_0000

PMC

IOPORT

0xFFFF_FFFF

SMC

RCM

0x4007_F000

0x4007_FFFF

Figure 6. Memory map

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

23

NXP Semiconductors

Pinouts

4 Pinouts

4.1 KE1xZ Signal Multiplexing and Pin Assignments

The following table shows the signals available on each pin and the locations of these

pins on the devices supported by this document. The Port Control Module is responsible

for selecting which ALT functionality is available on each pin.

NOTE

On this device, there are several special ADC channels which

support hardware interleave between multiple ADCs. Taking

ADC0_SE4 and ADC1_SE14 channels as an example, these

two channels can work independently, but they can also be

hardware interleaved. In the hardware interleaved mode, a

signal on the pin PTB0 can be sampled by both ADC0 and

ADC1. The interleaved mode is enabled by

SIM_CHIPCTL[ADC_INTERLEAVE_EN] bits. For more

information, see "ADC Hardware Interleaved Channels" in

the ADC chapter of Reference Manual.

100

64

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

LQFP LQFP

—

1

10

—

1

VREFL/

VSS

VREFL/

VSS

VREFL/

VSS

PTE16

DISABLED

PTE16

FXIO_D3

FXIO_D2

FXIO_D1

FXIO_D0

FXIO_D5

FXIO_D4

TRGMUX_

OUT7

2

PTE15

PTD1

DISABLED

TSI0_CH5

TSI0_CH4

TSI0_CH3

TSI0_CH2

PTE15

PTD1

TRGMUX_

OUT6

3

TSI0_CH5

TSI0_CH4

TSI0_CH3

TSI0_CH2

FTM0_CH3

FTM0_CH2

PWT_IN1

CLKOUT

LPSPI1_SIN

LPSPI1_SCK

FTM2_CH1

FTM2_CH0

TRGMUX_

OUT2

4

2

PTD0

TRGMUX_

OUT1

5

3

PTE11

PTE10

PTE11

PTE10

LPTMR0_

ALT1

TRGMUX_

OUT5

6

4

TRGMUX_

OUT4

7

8

—

5

PTE13

PTE5

DISABLED

TSI0_CH0

PTE13

PTE5

TSI0_CH0

TSI0_CH1

TCLK2

FTM2_QD_

PHA

FTM2_CH3

FTM2_CH2

FXIO_D7

FXIO_D6

EWM_IN

9

6

PTE4

TSI0_CH1

PTE4

BUSOUT

FTM2_QD_

PHB

EWM_OUT_b

24

NXP Semiconductors

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

Pinouts

100

64

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

LQFP LQFP

10

11

12

13

14

15

16

17

18

7

VDD

8

VDDA

VREFH

VREFL

VSS

VDDA

VREFH

VREFL

VSS

9

VREFH

VREFL

VSS

—

11

12

—

13

PTB7

PTB6

PTE14

PTE3

EXTAL

XTAL

EXTAL

XTAL

PTB7

LPI2C0_SCL

LPI2C0_SDA

FTM0_FLT1

FTM0_FLT0

PTB6

PTE14

PTE3

DISABLED

TSI0_CH24

LPUART2_

RTS

TRGMUX_IN6

19

20

21

22

23

—

14

15

16

PTE12

PTD17

PTD16

PTD15

PTE9

DISABLED

DAC0_OUT

PTE12

PTD17

PTD16

PTD15

PTE9

FTM0_FLT3

FTM0_FLT2

FTM0_CH1

FTM0_CH0

FTM0_CH7

LPUART2_TX

LPUART2_RX

DAC0_OUT

LPUART2_

CTS

24

25

26

—

17

PTD14

PTD13

PTE8

DISABLED

PTD14

PTD13

PTE8

CLKOUT

RTC_CLKOUT

ACMP0_IN3/

TSI0_CH11

ACMP0_IN3/

TSI0_CH11

FTM0_CH6

27

28

18

19

PTB5

PTB4

TSI0_CH9

PTB5

PTB4

FTM0_CH5

FTM0_CH4

LPSPI0_PCS1

LPSPI0_SOUT

TRGMUX_IN0

TRGMUX_IN1

ACMP1_OUT

ACMP1_IN2/

TSI0_CH8

ACMP1_IN2/

TSI0_CH8

29

30

20

21

PTC3

PTC2

ADC0_SE11/

ACMP0_IN4/

EXTAL32

ADC0_SE11/

ACMP0_IN4/

EXTAL32

PTC3

PTC2

FTM0_CH3

FTM0_CH2

ADC0_SE10/

ACMP0_IN5/

XTAL32

ADC0_SE10/

ACMP0_IN5/

XTAL32

31

32

33

22

23

24

PTD7

PTD6

PTD5

TSI0_CH10

TSI0_CH7

TSI0_CH6

TSI0_CH10

TSI0_CH7

TSI0_CH6

PTD7

PTD6

PTD5

LPUART2_TX

LPUART2_RX

FTM2_CH3

FTM2_FLT3

FTM2_FLT2

LPTMR0_

ALT2

PWT_IN2

TRGMUX_IN7

34

35

36

—

PTD12

PTD11

PTD10

DISABLED

PTD12

PTD11

PTD10

FTM2_CH2

FTM2_CH1

FTM2_CH0

LPI2C1_HREQ

LPUART2_

RTS

FTM2_QD_

PHA

LPUART2_

CTS

FTM2_QD_

PHB

37

38

39

—

25

VSS

VDD

VSS

VDD

PTC1

ADC0_SE9/

ACMP1_IN3/

TSI0_CH23

ADC0_SE9/

ACMP1_IN3/

TSI0_CH23

PTC1

FTM0_CH1

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

25

NXP Semiconductors

Pinouts

100

64

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

LQFP LQFP

40

26

PTC0

ADC0_SE8/

ACMP1_IN4/

TSI0_CH22

ADC0_SE8/

ACMP1_IN4/

TSI0_CH22

PTC0

FTM0_CH0

41

42

43

44

45

46

47

—

27

28

29

30

31

PTD9

ACMP1_IN5

DISABLED

ACMP1_IN5

PTD9

LPI2C1_SCL

LPI2C1_SDA

FTM1_FLT3

FTM1_FLT2

FTM1_CH3

FTM1_CH2

FTM1_CH1

FTM2_FLT3

FTM2_FLT2

LPI2C1_SCLS

LPI2C1_SDAS

PTD8

PTC17

PTC16

PTC15

PTC14

PTB3

ADC0_SE15

ADC0_SE14

ADC0_SE13

ADC0_SE12

ADC0_SE15

ADC0_SE14

ADC0_SE13

ADC0_SE12

PTC17

PTC16

PTC15

PTC14

PTB3

ADC0_SE7/

TSI0_CH21

ADC0_SE7/

TSI0_CH21

LPSPI0_SIN

LPSPI0_SCK

FTM1_QD_

PHA

TRGMUX_IN2

TRGMUX_IN3

48

32

PTB2

ADC0_SE6/

TSI0_CH20

ADC0_SE6/

TSI0_CH20

PTB2

FTM1_CH0

FTM1_QD_

PHB

49

50

51

52

53

54

—

33

34

PTC13

PTC12

PTC11

PTC10

PTB1

DISABLED

ADC0_SE5

ADC0_SE4

PTC13

PTC12

PTC11

PTC10

PTB1

ADC0_SE5

ADC0_SE4

LPUART0_TX

LPUART0_RX

LPSPI0_SOUT TCLK0

PTB0

LPSPI0_PCS0 LPTMR0_

ALT3

PWT_IN3

55

56

57

58

35

36

37

38

PTC9

PTC8

PTA7

PTA6

DISABLED

PTC9

PTC8

PTA7

PTA6

PTE7

LPUART1_TX

LPUART1_RX

FTM0_FLT2

FTM0_FLT1

FTM0_CH7

LPUART0_

RTS

LPUART0_

CTS

ADC0_SE3/

ACMP1_IN1

ADC0_SE3/

ACMP1_IN1

RTC_CLKIN

LPUART1_

RTS

ADC0_SE2/

ACMP1_IN0

ADC0_SE2/

ACMP1_IN0

LPSPI1_PCS1

LPUART1_

CTS

59

60

61

62

63

64

65

66

67

68

69

70

71

72

39

40

41

—

42

43

44

45

46

47

PTE7

VSS

DISABLED

VSS

VDD

PTA17

PTB17

PTB16

PTB15

PTB14

PTB13

PTB12

PTD4

PTD3

PTD2

PTA3

DISABLED

ADC1_SE9

ADC1_SE8

ADC1_SE7

ADC1_SE6

NMI_b

PTA17

PTB17

PTB16

PTB15

PTB14

PTB13

PTB12

PTD4

FTM0_CH6

FTM0_CH5

FTM0_CH4

FTM0_CH3

FTM0_CH2

FTM0_CH1

FTM0_CH0

FTM0_FLT3

EWM_OUT_b

LPSPI1_PCS3

LPSPI1_SOUT

LPSPI1_SIN

ADC1_SE9

ADC1_SE8

ADC1_SE7

ADC1_SE6

ADC1_SE3

ADC1_SE2

ADC1_SE1

LPSPI1_SCK

PTD3

LPSPI1_PCS0 FXIO_D5

LPSPI1_SOUT FXIO_D4

TRGMUX_IN4

TRGMUX_IN5

LPUART0_TX

NMI_b

ADC1_SE2

ADC1_SE1

PTD2

PTA3

LPI2C0_SCL

EWM_IN

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Pinouts

100

64

Pin Name

Default

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

LQFP LQFP

73

74

75

76

77

78

48

—

49

PTA2

ADC1_SE0

DISABLED

ADC1_SE0

PTA2

LPI2C0_SDA

LPI2C0_HREQ

LPI2C0_SDAS

LPI2C0_SCLS

EWM_OUT_b

LPUART0_RX

PTB11

PTB10

PTB9

PTB8

PTA1

PTB11

PTB10

PTB9

PTB8

PTA1

ADC0_SE1/

ACMP0_IN1/

TSI0_CH18

ADC0_SE1/

ACMP0_IN1/

TSI0_CH18

FTM1_CH1

FTM2_CH1

LPI2C0_SDAS FXIO_D3

FTM1_QD_

PHA

LPUART0_

RTS

TRGMUX_

OUT0

79

50

PTA0

ADC0_SE0/

ACMP0_IN0/

TSI0_CH17

ADC0_SE0/

ACMP0_IN0/

TSI0_CH17

PTA0

LPI2C0_SCLS

FXIO_D2

FTM2_QD_

PHA

LPUART0_

CTS

TRGMUX_

OUT3

80

81

51

52

PTC7

PTC6

ADC1_SE5/

TSI0_CH16

ADC1_SE5/

TSI0_CH16

PTC7

PTC6

LPUART1_TX

LPUART1_RX

ADC1_SE4/

TSI0_CH15

ADC1_SE4/

TSI0_CH15

82

83

84

—

53

PTA16

PTA15

PTE6

DISABLED

ADC1_SE11

PTA16

PTA15

PTE6

FTM1_CH3

FTM1_CH2

LPSPI0_PCS2

LPSPI1_PCS2

LPSPI0_PCS3

ADC1_SE11

LPUART1_

RTS

85

54

PTE2

ADC1_SE10/

TSI0_CH19

ADC1_SE10/

TSI0_CH19

PTE2

LPSPI0_SOUT LPTMR0_

ALT3

PWT_IN3

LPUART1_

CTS

86

87

88

89

90

91

92

93

94

95

—

55

56

57

58

59

60

61

VSS

VDD

PTA14

PTA13

PTA12

PTA11

PTA10

PTE1

PTE0

PTC5

DISABLED

TSI0_CH14

TSI0_CH13

TSI0_CH12

PTA14

PTA13

PTA12

PTA11

PTA10

PTE1

FTM0_FLT0

EWM_IN

BUSOUT

LPI2C1_SCLS

LPI2C1_SDAS

FXIO_D1

LPUART0_RX

LPUART0_TX

FXIO_D0

TSI0_CH14

TSI0_CH13

TSI0_CH12

LPSPI0_SIN

LPSPI0_SCK

FTM2_CH0

LPI2C0_HREQ LPI2C1_SCL

TCLK1 LPI2C1_SDA

PTE0

FTM1_FLT2

PTC5

RTC_CLKOUT LPI2C1_HREQ

FTM2_QD_

PHB

96

62

PTC4

SWD_CLK

ACMP0_IN2

PTC4

FTM1_CH0

RTC_CLKOUT

EWM_IN

FTM1_QD_

PHB

SWD_CLK

97

98

63

64

—

PTA5

PTA4

PTA9

PTA8

RESET_b

SWD_DIO

DISABLED

PTA5

PTA4

PTA9

PTA8

TCLK1

RESET_b

SWD_DIO

ACMP0_OUT

FXIO_D7

FXIO_D6

EWM_OUT_b

99

FTM1_FLT3

100

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Pinouts

4.2 Port control and interrupt summary

The following table provides more information regarding the Port Control and Interrupt

configurations.

Table 6. Ports summary

Feature

Port A

Port B

Yes

Port C

Port D

Port E

Yes

Pull select control Yes

Yes

Pull select at reset PTA4/PTA5=Pull

up, Others=No

No

PTC4=Pull down, PTD3=Pull up,

No

Others=No

Pull enable control Yes

Yes

Pull enable at reset PTA4/

PTA5=Enabled;

Disabled

PTC4=Enabled;

Others=Disabled

PTD3=Enabled;

Others=Disabled

Disabled

Others=Disabled

Passive filter

enable control

PTA5=Yes;

Others=No

No

PTD3=Yes;

Others=No

No

Passive filter

enable at reset

PTA5=Enabled;

Others=Disabled

Disabled

Open drain enable I2C and UART

I2C and UART

Tx=Enabled;

I2C and UART

Tx=Enabled;

I2C and UART

Tx=Enabled;

I2C and UART

Tx=Enabled;

control

Tx=Enabled;

Others=Disabled

Open drain enable Disabled

at reset

Disabled

PTB4/PTB5 only

Disabled

Yes

Disabled

Drive strength

enable control

No

PTD0/PTD1/

PTD15/PTD16 only

PTE0/PTE1 only

Disabled

Drive strength

enable at reset

Disabled

Yes

Disabled

Pin mux control Yes

Yes

Pin mux at reset PTA4/PTA5=ALT7; ALT0

Others=ALT0

PTC4=ALT7;

Others=ALT0

PTD3=ALT7;

Others=ALT0

ALT0

Lock bit

Yes

Interrupt and DMA Yes

request

Digital glitch filter No

No

Yes

4.3 Module Signal Description Tables

The following sections correlate the chip-level signal name with the signal name used in

the module's chapter. They also briefly describe the signal function and direction.

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4.3.1 Core Modules

Table 7. SWD Signal Descriptions

Chip signal name

Module signal

name

Description

I/O

SWD_CLK

SWD_DIO

SWD_CLK

SWD_DIO

Serial Wire Clock

Serial Wire Data

I

I/O

4.3.2 System Modules

Table 8. System Signal Descriptions

Chip signal name

Module signal

Description

I/O

name

NMI_b

—

Non-maskable interrupt NOTE: Driving the NMI signal low forces

a non-maskable interrupt, if the NMI function is selected on the

corresponding pin.

I

RESET_b

VDD

—

Reset bidirectional signal

MCU power

I/O

I

VSS

MCU ground

Table 9. EWM Signal Descriptions

Chip signal name

Module signal

name

Description

I/O

EWM_IN

EWM_in

EWM input for safety status of external safety circuits. The

polarity of EWM_IN is programmable using the

I

EWM_CTRL[ASSIN] bit. The default polarity is active-low.

EWM_OUT_b

EWM_out

EWM reset out signal

O

4.3.3 Clock Modules

Table 10. OSC (in SCG) Signal Descriptions

Chip

signal

name

Module signal name

Description

I/O

EXTAL

XTAL

EXTAL

XTAL

External clock/Oscillator input

Oscillator output

I

O

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Table 11. RTC Oscillator (OSC32) Signal Descriptions

Chip signal name

Module signal

name

Description

I/O

EXTAL32

XTAL32

EXTAL32

XTAL32

32.768 kHz oscillator input

32.768 kHz oscillator output

I

O

4.3.4 Analog

Table 12. ADC0 Signal Descriptions

Chip signal name

Module signal

Description

I/O

name

AD[15:0]

V_REFSH

V_REFSL

V_DDA

ADC0_SE[15:0]

VREFH

Single-Ended Analog Channel Inputs

Voltage Reference Select High

Voltage Reference Select Low

Analog Power Supply

I

VREFL

VDDA

Table 13. ADC1 Signal Descriptions

Chip signal name

Module signal

Description

I/O

name

AD[11:0]

V_REFSH

V_REFSL

V_DDA

ADC1_SE[11:0]

VREFH

Single-Ended Analog Channel Inputs

Voltage Reference Select High

Voltage Reference Select Low

Analog Power Supply

I

VREFL

VDDA

Table 14. ACMP0 Signal Descriptions

Chip signal name

Module signal

Description

I/O

name

IN[5:0]

CMPO

—

ACMP0_IN[5:0]

ACMP0_OUT

DAC0_OUT

Analog voltage inputs

Comparator output

DAC output

I

O

Table 15. ACMP1 Signal Descriptions

Chip signal name

Module signal

Description

I/O

name

IN[5:0]

CMPO

ACMP1_IN[5:0]

ACMP1_OUT

Analog voltage inputs

Comparator output

I

O

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4.3.5 Timer Modules

Table 16. LPTMR0 Signal Descriptions

Chip signal name

Module signal

name

Description

I/O

LPTMR0_ALT[3:1]

LPTMR_ALTn

Pulse Counter Input pin

I

Table 17. RTC Signal Descriptions

Chip signal name

Module signal

Description

I/O

name

RTC_CLKOUT

1 Hz square-wave output or 32 kHz clock

O

Table 18. FTM0 Signal Descriptions

Chip signal name Module signal name Description

I/O

FTM0_CH[7:0]

FTM0_FLT[3:0]

TCLK[2:0]

CHn

FTM channel (n), where n can be 7-0

Fault input (j), where j can be 3-0

I/O

FAULTj

EXTCLK

I

External clock. FTM external clock can be selected to drive the

FTM counter.

Table 19. FTM1 Signal Descriptions

Chip signal name Module signal name Description

I/O

FTM1_CH[3:0]

FTM1_FLT[3:2]

TCLK[2:0]

CHn

FTM channel (n), where n can be 3-0

Fault input (j), where j can be 3-2

I/O

FAULTj

EXTCLK

I

External clock. FTM external clock can be selected to drive the

FTM counter.

Table 20. FTM2 Signal Descriptions

Chip signal name Module signal name Description

I/O

FTM2_CH[3:0]

FTM2_FLT[3:2]

TCLK[2:0]

CHn

FTM channel (n), where n can be 3-0

Fault input (j), where j can be 3-2

I/O

FAULTj

EXTCLK

I

External clock. FTM external clock can be selected to drive the

FTM counter.

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Pinouts

4.3.6 Communication Interfaces

Table 21. LPSPIn Signal Descriptions

Chip signal name

Module signal

Description

I/O

name

SOUT

SIN

LPSPIn_SOUT

LPSPIn_SIN

Serial Data Out

Serial Data In

O

I

LPSPIn_SCK

SCK

Serial Clock

I/O

LPSPIn_PCS[3:0]

PCS[3:0]

Peripheral Chip Select 0-3

Table 22. LPI2Cn Signal Descriptions

Chip signal name

Module signal

Description

I/O

name

LPI2Cn_SCL

LPI2Cn_SDA

LPI2Cn_HREQ

SCL

Bidirectional serial clock line of the I2C system.

Bidirectional serial data line of the I2C system.

I/O

I

SDA

HREQ

Host request, can initiate an LPI2C master transfer if asserted and

the I2C bus is idle.

LPI2Cn_SCLS

LPI2Cn_SDAS

SCLS

SDAS

Secondary I2C clock line.

Secondary I2C data line.

I/O

Table 23. LPUARTn Signal Descriptions

Chip signal name

Module signal

Description

I/O

name

LPUARTn_TX

LPUARTn_RX

LPUARTn_CTS

LPUARTn_RTS

LPUART_TXD

LPUART_RXD

LPUART_CTS

LPUART_RTS

Transmit data

Receive data

Clear to send

Request to send

I/O

I

O

Table 24. FlexIO Signal Descriptions

Chip signal name

Module signal

Description

I/O

name

FXIO_D[7:0]

Bidirectional FlexIO Shifter and Timer pin inputs/outputs

I/O

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Pinouts

4.3.7 Human-Machine Interfaces (HMI)

Table 25. GPIO Signal Descriptions

Chip signal name

Module signal

name

Description

I/O

PTA[17:0]

PTB[17:0]

PTC[17:0]

PTD[17:0]

PTE[16:0]

PORTA17–PORTA0 General-purpose input/output

PORTB17–PORTB0 General-purpose input/output

PORTC17–PORTC0 General-purpose input/output

PORTD17–PORTD0 General-purpose input/output

PORTE16–PORTE0 General-purpose input/output

I/O

Table 26. TSI0 Signal Descriptions

Chip signal name

Module signal

name

Description

I/O

TSI0_CH[24:0]

TSI[24:0]

TSI sensing pins or GPIO pins

I/O

4.4 Pinout diagram

The following figure shows the pinout diagram for the devices supported by this

document. Many signals may be multiplexed onto a single pin. To determine what

signals can be used on which pin, see the previous table of Pin Assignments.

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33

NXP Semiconductors

Pinouts

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

PTE16

PTE15

PTD1

PTB10

PTB11

PTA2

2

3

4

PTA3

PTD0

5

PTD2

PTD3

PTD4

PTB12

PTB13

PTB14

PTB15

PTB16

PTB17

PTA17

VDD

PTE11

PTE10

PTE13

PTE5

6

7

8

9

PTE4

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

VDD

VDDA

VREFH

VREFL

VSS

PTB7

VSS

PTB6

PTE7

PTA6

PTE14

PTE3

PTA7

PTE12

PTD17

PTD16

PTD15

PTE9

PTC8

PTC9

PTB0

PTB1

PTC10

PTC11

PTD14

PTD13

Figure 7. 100 LQFP Pinout Diagram

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NXP Semiconductors

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

Pinouts

PTD1

PTD0

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

PTA2

PTA3

PTD2

PTD3

PTD4

PTB12

PTB13

VDD

2

PTE11

PTE10

PTE5

3

4

5

PTE4

6

VDD

7

VDDA

8

VREFH

VREFL / VSS

PTB7

9

VSS

10

11

12

13

14

15

16

PTE7

PTA6

PTA7

PTC8

PTC9

PTB0

PTB1

PTB6

PTE3

PTD16

PTD15

PTE9

Figure 8. 64 LQFP Pinout Diagram

4.5 Package dimensions

The following figures show the dimensions of the package options for the devices

supported by this document.

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NXP Semiconductors

Pinouts

Figure 9. 100-pin LQFP package dimensions 1

36

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Pinouts

Figure 10. 100-pin LQFP package dimensions 2

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

37

NXP Semiconductors

Pinouts

Figure 11. 64-pin LQFP package dimensions 1

38

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

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Pinouts

Figure 12. 64-pin LQFP package dimensions 2

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

39

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Electrical characteristics

5 Electrical characteristics

5.1 Terminology and guidelines

5.1.1 Definitions

Key terms are defined in the following table:

Term

Definition

Rating

A minimum or maximum value of a technical characteristic that, if exceeded, may cause

permanent chip failure:

• Operating ratings apply during operation of the chip.

• Handling ratings apply when the chip is not powered.

NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic

begins to exceed one of its operating ratings.

Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during

operation to avoid incorrect operation and possibly decreasing the useful life of the chip

Operating behavior

A specified value or range of values for a technical characteristic that are guaranteed during

operation if you meet the operating requirements and any other specified conditions

Typical value

A specified value for a technical characteristic that:

• Lies within the range of values specified by the operating behavior

• Is representative of that characteristic during operation when you meet the typical-value

conditions or other specified conditions

NOTE: Typical values are provided as design guidelines and are neither tested nor guaranteed.

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Electrical characteristics

5.1.2 Examples

Operating rating:

EXAMPLE

Operating requirement:

Operating behavior that includes a typical value:

EXAMPLE

5.1.3 Typical-value conditions

Typical values assume you meet the following conditions (or other conditions as

specified):

Symbol

Description

Ambient temperature

Supply voltage

Value

Unit

T_A

25

°C

V

V_DD

5.0

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NXP Semiconductors

Electrical characteristics

5.1.4 Relationship between ratings and operating requirements

Fatal range

Degraded operating range

Normal operating range

Degraded operating range

Fatal range

Expected permanent failure

- No permanent failure

- Correct operation

- No permanent failure

Expected permanent failure

- Possible decreased life

- Possible incorrect operation

- Possible decreased life

- Possible incorrect operation

–∞

∞

Operating (power on)

Fatal range

Handling range

Fatal range

Expected permanent failure

No permanent failure

Expected permanent failure

–∞

∞

Handling (power off)

5.1.5 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings.

• During normal operation, don’t exceed any of the chip’s operating requirements.

• If you must exceed an operating requirement at times other than during normal

operation (for example, during power sequencing), limit the duration as much as

possible.

5.2 Ratings

5.2.1 Thermal handling ratings

Symbol

T_STG

Description

Min.

–55

—

Max.

150

Unit

°C

Notes

Storage temperature

Solder temperature, lead-free

1

2

T_SDR

260

°C

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

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Electrical characteristics

5.2.2 Moisture handling ratings

Symbol

Description

Min.

Max.

Unit

Notes

MSL

Moisture sensitivity level

—

3

—

1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

5.2.3 ESD handling ratings

Symbol

V_HBM

Description

Min.

Max.

Unit

Notes

Electrostatic discharge voltage, human body model

− 6000

6000

V

1

2

V_CDM

Electrostatic discharge voltage, charged-device

model

All pins except the corner pins

Corner pins only

− 500

− 750

− 100

500

750

100

V

I_LAT

Latch-up current at ambient temperature upper limit

mA

3

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human

Body Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

5.2.4 Voltage and current operating ratings

NOTE

Functional operating conditions appear in the "DC electrical

specifications". Absolute maximum ratings are stress ratings

only, and functional operation at the maximum values is not

guaranteed. Stress beyond the listed maximum values may

affect device reliability or cause permanent damage to the

device.

Table 27. Voltage and current operating ratings

Symbol

V_DD

Description

Min.

–0.3

—

Max.

5.8 ¹

60

Unit

V

Supply voltage

I_DD

Digital supply current

mA

Table continues on the next page...

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NXP Semiconductors

Electrical characteristics

Table 27. Voltage and current operating ratings (continued)

Symbol

V_IO

Description

Min.

V_SS– 0.3

–25

Max.

V_DD+ 0.3

25

Unit

V

IO pin input voltage

I_D

Instantaneous maximum current single pin limit (applies to

all port pins)

mA

V_DDA

Analog supply voltage

V_DD– 0.1

V_DD+ 0.1

V

1. 60s lifetime - No restrictions, i.e. the part can switch.

10 hours lifetime - Device in reset, i.e. the part cannot switch.

5.3 General

5.3.1 Nonswitching electrical specifications

5.3.1.1 Voltage and current operating requirements

Table 28. Voltage and current operating requirements

Symbol Description

Min.

2.7

Max.

5.5

Unit

V

Notes

V_DD

Supply voltage

V_DDA

Analog supply voltage

V_DD-to-V_DDAdifferential voltage

2.7

5.5

V

V_DD

–

– 0.1

0.1

V

V_DDA

V_SS

–

V_SS-to-V_SSAdifferential voltage

– 0.1

0.1

V

V_SSA

I_ICIO

DC injection current — single pin

V_IN< V_SS- 0.3 V (Negative current injection)

V_IN> V_DD+ 0.3 V (Positive current injection)

− 3

—

mA

1

2

+ 3

I_ICcont

Contiguous pin DC injection current —

regional limit, includes sum of negative

injection currents or sum of positive injection

currents of 16 contiguous pins

− 25

V_DD

+ 25

V_DD

mA

V

V_ODPUOpen drain pullup voltage level

1. All pins are internally clamped to V_SSand V_DDthrough ESD protection diodes. If V_INis less than V_SS– 0.3V or greater

than V_DD+ 0.3V, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated as

R=(V_SS– 0.3V–V_IN)/|I_ICIO|. The positive injection current limiting resistor is calculated as R=[V_IN–(V_DD+ 0.3V)]/|I_ICIO|.

The actual resistor values should be an order of magnitude higher to tolerate transient voltages.

2. Open drain outputs must be pulled to V_DD

.

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Electrical characteristics

5.3.1.2 DC electrical specifications at 3.3 V Range and 5.0 V Range

Table 29. DC electrical specifications

Symbol

Parameter

Value

Typ

3.3

Unit

Notes

Min

Max

V_DD

I/O Supply Voltage ¹

2.7

4

V

@ V_DD= 3.3 V

@ V_DD= 5.0 V

4

—

5.5

V

V_ih

Input Buffer High Voltage

@ V_DD= 3.3 V

0.7 × V_DD

V_DD+ 0.3

@ V_DD= 5.0 V

0.65 × V_DD

V_SS− 0.3

—

V_DD+ 0.3

0.3 × V_DD

V

V_il

Input Buffer Low Voltage

@ V_DD= 3.3 V

@ V_DD= 5.0 V

V_SS− 0.3

—

0.35 ×

V_DD

V

V_hys

Input Buffer Hysteresis

0.06 × V_DD

2.8

—

V

Ioh_5

Normal drive I/O current source capability

measured when pad = (V_DD− 0.8 V)

mA

@ V_DD= 3.3 V

@ V_DD= 5.0 V

4.8

2.4

—

mA

Iol_5

Ioh_20

Iol_20

Normal drive I/O current sink capability

measured when pad = 0.8 V

@ V_DD= 3.3 V

@ V_DD= 5.0 V

4.4

—

mA

High drive I/O current source capability

measured when pad = (V_DD− 0.8 V)^{, 2}

10.8

@ V_DD= 3.3 V

@ V_DD= 5.0 V

18.5

10.1

—

mA ³

mA

High drive I/O current sink capability measured

when pad = 0.8 V⁴

@ V_DD= 3.3 V

@ V_DD= 5.0 V

18.5

—

mA ³

nA

I_leak

V_OH

Hi-Z (Off state) leakage current (per pin)

Output high voltage

300

5, 6

7

Normal drive pad (2.7 V ≤ V_DD≤ 4.0 V, I_OH= − V_DD– 0.8

2.8 mA)

—

V

Normal drive pad (4.0 V ≤ V_DD≤ 5.5 V, I_OH= − V_DD– 0.8

4.8 mA)

High drive pad (2.7 V ≤ V_DD≤ 4.0 V, I_OH= −

10.8 mA)

V_DD– 0.8

—

V

High drive pad (4.0 V ≤ V_DD≤ 5.5 V, I_OH= −

18.5 mA)

—

V

I_OHT

Output high current total for all ports

100

mA

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NXP Semiconductors

Electrical characteristics

Symbol

Table 29. DC electrical specifications (continued)

Parameter

Value

Typ

Unit

Notes

Min

Max

V_OL

Output low voltage

7

Normal drive pad (2.7 V ≤ V_DD≤ 4.0 V, I_OH= −

2.8 mA)

—

0.8

100

V

Normal drive pad (4.0 V ≤ V_DD≤ 5.5 V, I_OH= −

4.8 mA)

High drive pad (2.7 V ≤ V_DD≤ 4.0 V, I_OH= −

10.8 mA)

V

High drive pad (4.0 V ≤ V_DD≤ 5.5 V, I_OH= −

18.5 mA)

V

I_OLT

I_IN

Output low current total for all ports

mA

Input leakage current (per pin) for full temperature range

@ V_DD= 3.3 V

8, 7

All pins other than high drive port pins

High drive port pins

—

0.002

0.004

0.5

μA

Input leakage current (per pin) for full temperature range

@ V_DD= 5.5 V

All pins other than high drive port pins

High drive port pins

Internal pull-up resistors

@ V_DD= 3.3 V

—

20

0.005

0.010

—

0.5

65

μA

kΩ

R_PU

9

@ V_DD= 5.0 V

20

—

50

65

kΩ

R_PD

Internal pull-down resistors

@ V_DD= 3.3 V

10

@ V_DD= 5.0 V

20

—

50

kΩ

1. Max power supply ramp rate is 500 V/ms.

2. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_5 value

given above.

3. The 20 mA I/O pin is capable of switching a 50 pF load at up to 40 MHz.

4. The value given is measured at high drive strength mode. For value at low drive strength mode see the Iol_5 value given

above.

5. Refers to the current that leaks into the core when the pad is in Hi-Z (Off state).

6. Maximum pin leakage current at the ambient temperature upper limit.

7. PTD0, PTD1, PTD15, PTD16, PTB4, PTB5, PTE0 and PTE1 I/O have both high drive and normal drive capability

selected by the associated Portx_PCRn[DSE] control bit. All other GPIOs are normal drive only.

8. Refers to the pin leakage on the GPIOs when they are OFF.

9. Measured at V_DDsupply voltage = V_DDmin and input V = V_SS

10. Measured at V_DDsupply voltage = V_DDmin and input V = V_DD

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Electrical characteristics

5.3.1.3 Voltage regulator electrical characteristics

C

DEC

VDD

VDDA

VDD

100 LQFP

Package

64 LQFP

Package

VREFH

VREFL

VDD

VSS

VREFH

VSS

VREFL / VSS

VSS

C

DEC

Figure 13. Pinout decoupling

Table 30. Voltage regulator electrical characteristics

Symbol

Description

Min.

—

Typ.

100

Max.

—

Unit

nF

, 1, 2

C_REF

ADC reference high decoupling capacitance

Recommended decoupling capacitance

2, 3

C_DEC

—

nF

1. For improved ADC performance it is recommended to use 1 nF X7R/C0G and 10 nF X7R ceramics in parallel.

2. The capacitors should be placed as close as possible to the VREFH/VREFL pins or corresponding V_DD/V_SSpins.

3. The requirement and value of of C_DECwill be decided by the device application requirement.

5.3.1.4 LVR, LVD and POR operating requirements

Table 31. V_DDsupply LVR, LVD and POR operating requirements

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

V_POR

Rising and Falling V_DDPOR detect

voltage

1.1

1.6

2.0

V

V_LVRX

LVRX falling threshold (RUN and STOP

modes)

2.53

2.58

2.64

V

LVRX hysteresis

—

45

—

mV

V

1

V_{LVRX_HYST}

V_{LVRX_LP}

LVRX falling threshold (VLPS/VLPR

modes)

1.97

2.12

2.44

V_{LVRX_LP_HYST}LVRX hysteresis (VLPS/VLPR modes)

—

2.8

—

40

2.88

50

—

3

mV

V

V_LVD

Falling low-voltage detect threshold

LVD hysteresis

—

mV

1

V_{LVD_HYST}

V_LVW

V_{LVW_HYST}

V_BG

Falling low-voltage warning threshold

LVW hysteresis

4.19

0.97

4.31

68

4.5

V

mV

V

Bandgap voltage reference

1.00

1.03

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Electrical characteristics

1. Rising threshold is the sum of falling threshold and hysteresis voltage.

5.3.1.5 Power mode transition operating behaviors

Table 32. Power mode transition operating behaviors

Description

System Clock

Core, Bus, Flash

frequency (MHz)

Min.

Typ. (μs)¹Max. (μs)²

STOP→RUN

FIRC

FLL

48, 24, 24

—

7.15

11.8

13.4

11.8

15.9

14.4

30.7

35.7

0.760

0.653

24.9

22.8

146

STOP→RUN

VLPS→RUN

RUN→VLPR

VLPR→RUN

WAIT→RUN

VLPW→VLPR

VLPS→VLPR

VLPW→RUN

72, 24, 24

7.51

7.15

9.8

FIRC

FLL

48, 24, 24

72, 24, 24

FLL→SIRC

SIRC→FIRC

SIRC→FLL

FIRC

72, 24, 24→4, 1, 1

4, 1, 1→48, 24, 24

4, 1, 1→72, 24, 24

48, 24, 24

13.6

24

27

0.660

0.516

20.7

17.9

127

111

FLL

72, 24, 24

SIRC

4, 1, 1

SIRC

4, 1, 1

FIRC (reset value)

48, 24, 24 (reset value)

3

t_POR

127

1. Typical value is the average of values tested at Temperature=25 ℃ and V_DD=3.3 V.

2. Max value is mean+6×sigma of tested values at the worst case of ambient temperature range and V_DD2.7 V to 5.5 V.

3. After a POR event, the amount of time from the point V_DDreaches the reference voltage 2.7 V to execution of the first

instruction, across the operating temperature range of the chip.

5.3.1.6 Power consumption

The following table shows the power consumption targets for the device in various

modes of operations.

NOTE

The maximum values stated in the following table represent

characterized results equivalent to the mean plus three times

the standard deviation (mean + 3 sigma).

Table 33. Power consumption operating behaviors

Mode

Symbol

Clock

Configura

tion

Description

Temperat Min

ure

Typ

Max¹Unit

RUN

I_{DD_RUN}

LPFLL

Running CoreMark in Flash in Compute 25 ℃

—

11.19

11.70

11.43

12.00

mA

Operation mode.

105 ℃

Core@72MHz, bus @24MHz, flash

@24MHz, VDD=5V

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Table 33. Power consumption operating behaviors (continued)

Mode

Symbol

Clock

Configura

tion

Description

Temperat Min

ure

Typ

Max¹Unit

LPFLL

Running CoreMark in Flash all peripheral 25 ℃

—

12.15

12.41

clock disabled.

105 ℃

12.67

12.99

Core@72MHz, bus @24MHz, flash

@24MHz, VDD=5V

LPFLL

Running CoreMark in Flash, all

peripheral clock enabled.

25 ℃

—

13.53

14.07

13.82

14.43

105 ℃

Core@72MHz, bus@24MHz, flash

@24MHz, VDD=5V

LPFLL

Running While(1) loop in Flash, all

peripheral clock disabled.

25 ℃

—

8.81

9.26

9.00

9.49

105 ℃

Core@72MHz, bus@24MHz, flash

@24MHz, VDD=5V

LPFLL

Running While(1) loop in Flash all

peripheral clock enabled.

25 ℃

—

10.22

10.67

10.44

10.94

105 ℃

Core@72MHz , bus@24MHz, flash

@24MHz, VDD=5V

IRC48M

IRC8M

Running CoreMark in Flash in Compute 25 ℃

—

8.50

8.88

8.69

9.08

Operation mode.

105 ℃

Core@48MHz, bus @24MHz, flash

@24MHz, VDD=5V

Running CoreMark in Flash all peripheral 25 ℃

—

9.37

9.76

9.58

9.98

clock disabled.

105 ℃

Core@48MHz, bus @24MHz, flash

@24MHz, VDD=5V

Running CoreMark in Flash, all

peripheral clock enabled.

25 ℃

—

10.51

10.90

10.75

11.15

105 ℃

Core@48MHz, bus@24MHz, flash

@24MHz, VDD=5V

Running While(1) loop in Flash, all

peripheral clock disabled.

25 ℃

—

7.00

7.41

7.16

7.58

105 ℃

Core@48MHz, bus@24MHz, flash

@24MHz, VDD=5V

VLPR

I_{DD_VLPR}

Very Low Power Run Core Mark in Flash 25 ℃

in Compute Operation mode.

—

1070

1110

1180

1136

1178

1253

μA

Core@4MHz, bus @1MHz, flash

@1MHz, VDD=5V

Very Low Power Run Core Mark in Flash 25 ℃

all peripheral clock disabled.

Core@4MHz, bus @1MHz, flash

@1MHz, VDD=5V

Very Low Power Run Core Mark in Flash 25 ℃

all peripheral clock enabled.

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Electrical characteristics

Table 33. Power consumption operating behaviors (continued)

Mode

Symbol

Clock

Configura

tion

Description

Temperat Min

ure

Typ

Max¹Unit

Core@4MHz, bus @1MHz, flash

@1MHz, VDD=5V

IRC8M

IRC2M

Very Low Power Run While(1) loop in

Flash all peripheral clock disabled.

25 ℃

—

747

793

Core@4MHz, bus @1MHz, flash

@1MHz, VDD=5V

Very Low Power Run While(1) loop in

Flash all peripheral clock enabled.

813

585

641

863

621

680

Core@4MHz, bus @1MHz, flash

@1MHz, VDD=5V

Very Low Power Run While(1) loop in

Flash all peripheral clock disabled.

Core@2MHz, bus @1MHz, flash

@1MHz, VDD=5V

Very Low Power Run While(1) loop in

Flash all peripheral clock enabled.

Core@2MHz, bus @1MHz, flash

@1MHz, VDD=5V

WAIT

I_{DD_WAIT}

LPFLL

IRC48M

IRC8M

IRC2M

-

core disabled, system@72MHz, bus

@24MHz, flash disabled (flash doze

enabled), VDD=5 V, all peripheral clocks

disabled

25 ℃

—

5.95

4.86

657

550

27

6.09

4.97

698

584

37

mA

core disabled, system@48 MHz, bus

@24MHz, flash disabled (flash doze

enabled), VDD=5 V, all peripheral clocks

disabled

VLPW

I_{DD_VLPW}

Very Low Power Wait current, core

disabled system@4MHz, bus and

flash@1MHz, all peripheral clocks

disabled, VDD=5V

μA

Very Low Power Wait current, core

disabled system@2MHz, bus and

flash@1MHz, all peripheral clocks

disabled, VDD=5V

STOP

I_{DD_STOP}

Stop mode current, VDD=5V, clock bias 25 ℃ and

μA

enabled ²

below

50 ℃

85 ℃

105 ℃

—

45

63

135

269

26

189

377

36

I_{DD_STOP}

-

Stop mode current, VDD=5V, clock bias 25 ℃ and

disabled ²

below

50 ℃

85 ℃

—

47

66

146

204

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Electrical characteristics

Table 33. Power consumption operating behaviors (continued)

Mode

Symbol

Clock

Configura

tion

Description

Temperat Min

ure

Typ

Max¹Unit

105 ℃

Very Low Power Stop current, VDD=5V, 25 ℃ and

—

277

388

VLPS

I_{DD_VLPS}

-

27

37

μA

clock bias enabled ²

below

50 ℃

85 ℃

105 ℃

—

45

64

134

267

21

187

375

29

VLPS

I_{DD_VLPS}

-

Very Low Power Stop current, VDD=5V, 25 ℃ and

clock bias disabled ²

below

50 ℃

85 ℃

105 ℃

—

29

41

66

92

109

153

1. These values are based on characterization but not covered by test limits in production.

2. PMC_REGSC[CLKBIASDIS] is the control bit to enable or disable bias under STOP/VLPS mode.

NOTE

CoreMark benchmark compiled using IAR 7.40 with

optimization level high, optimized for balanced.

5.3.1.6.1 Low power mode peripheral current adder — typical value

Symbol

Description

Typical

I_LPTMR

LPTMR peripheral adder measured by placing the device in VLPS

mode with LPTMR enabled using LPO. Includes LPO power

consumption.

366 nA

I_CMP

CMP peripheral adder measured by placing the device in VLPS mode

with CMP enabled using the 8-bit DAC and a single external input for

compare. 8-bit DAC enabled with half VDDA voltage, low speed mode.

Includes 8-bit DAC power consumption.

16 μA

I_RTC

RTC peripheral adder measured by placing the device in VLPS mode

with external 32 kHz crystal enabled by means of the RTC_CR[OSCE]

bit and the RTC counter enabled. Includes EXTAL32 (32 kHz external

crystal) power consumption.

312 nA

I_LPUART

LPUART peripheral adder measured by placing the device in VLPS

mode with selected clock source waiting for RX data at 115200 baud

rate. Includes selected clock source power consumption. (SIRC 8 MHz)

79 μA

45 μA

I_FTM

FTM peripheral adder measured by placing the device in VLPW mode

with selected clock source, outputting the edge aligned PWM of 100 Hz

frequency.

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Electrical characteristics

Symbol

Description

Typical

I_ADC

ADC peripheral adder combining the measured values at VDD and

VDDA by placing the device in VLPS mode. ADC is configured for low

power mode using SIRC clock source, 8-bit resolution and continuous

conversions.

484 μA

I_LPI2C

LPI2C peripheral adder measured by placing the device in VLPS mode

with selected clock source sending START and Slave address, waiting

for RX data. Includes the DMA power consumption.

179 μA

18 μA

I_LPIT

LPIT peripheral adder measured by placing the device in VLPS mode

with internal SIRC 8 MHz enabled in Stop mode. Includes selected

clock source power consumption.

I_LPSPI

LPSPI peripheral adder measured by placing the device in VLPS mode

with selected clock source, output data on SOUT pin with SCK 500

kbit/s. Includes the DMA power consumption.

565 μA

5.3.1.6.2 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

• SCG in SOSC for both Run and VLPR modes

• No GPIOs toggled

• Code execution from flash with cache enabled

• For the ALLOFF curve, all peripheral clocks are disabled except FTFE

Run mode Current vsCoreFreq

Temperature=25, VDD=5V

12.00E-03

10.00E-03

8.00E-03

Clock Gates

6.00E-03

ALLOFF

ALLON

4.00E-03

2.00E-03

000.00E+00

CoreFreq

Core: Flash

1

2

4

6

12

24

48

72

1-1

1-2

1-3

Figure 14. Run mode supply current vs. core frequency

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VLPRCurrent VsCore Freq

Temperature=25, VDD=5V

900.00E-06

800.00E-06

700.00E-06

600.00E-06

500.00E-06

400.00E-06

300.00E-06

200.00E-06

100.00E-06

000.00E+00

ClockGates

ALLOFF

ALLON

1

2

4

CoreFreq

Core: Flash

1-1

1-2

1-4

Figure 15. VLPR mode supply current vs. core frequency

5.3.1.7 EMC performance

Electromagnetic compatibility (EMC) performance is highly dependent on the

environment in which the MCU resides. Board design and layout, circuit topology

choices, location and characteristics of external components, and MCU software

operation play a significant role in the EMC performance. The system designer can

consult the following applications notes, available on http://www.nxp.com for advice

and guidance specifically targeted at optimizing EMC performance.

• AN2321: Designing for Board Level Electromagnetic Compatibility

• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS

Microcontrollers

• AN1263: Designing for Electromagnetic Compatibility with Single-Chip

Microcontrollers

• AN2764: Improving the Transient Immunity Performance of Microcontroller-

Based Applications

• AN1259: System Design and Layout Techniques for Noise Reduction in MCU-

Based Systems

5.3.1.7.1 EMC radiated emissions operating behaviors

EMC measurements to IC-level IEC standards are available from NXP on request.

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Electrical characteristics

5.3.1.7.2 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions.

1. Go to http://www.nxp.com.

2. Perform a keyword search for “EMC design”.

3. Select the "Documents" category and find the application notes.

5.3.1.8 Capacitance attributes

Table 34. Capacitance attributes

Symbol

C_{IN_A}

Description

Min.

—

Max.

Unit

pF

Input capacitance: analog pins

Input capacitance: digital pins

7

C_{IN_D}

—

pF

NOTE

Please refer to External Oscillator electrical specifications for

EXTAL/XTAL pins.

5.3.2 Switching specifications

5.3.2.1 Device clock specifications

Table 35. Device clock specifications

Symbol

Description

Min.

Max.

Unit

Notes

Normal run mode

f_SYS

f_BUS

f_FLASH

f_LPTMR

System and core clock

Bus clock

—

72

24

25

48

MHz

Flash clock

LPTMR clock

VLPR / VLPW mode¹

f_SYS

f_BUS

System and core clock

Bus clock

—

4

1

MHz

f_FLASH

f_ERCLK

f_LPTMR

Flash clock

1

External reference clock

LPTMR clock

16

13

1. The frequency limitations in VLPR / VLPW mode here override any frequency specification listed in the timing

specification for any other module.

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Electrical characteristics

5.3.2.2 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%

point, and rise and fall times are measured at the 20% and 80% points, as shown in the

following figure.

High

Low

V_IH

80%

50%

20%

Input Signal

Midpoint1

V_IL

Fall Time

Rise Time

The midpoint is V_IL+ (V_IH- V_IL) / 2

Figure 16. Input signal measurement reference

All digital I/O switching characteristics, unless otherwise specified, assume that the

output pins have the following characteristics.

• C_L=30 pF loads

• Normal drive strength

5.3.2.3 General AC specifications

These general purpose specifications apply to all signals configured for GPIO, UART,

and timers.

Table 36. General switching specifications

Symbol

Description

Min.

Max.

Unit

Notes

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

1.5

—

Bus clock

cycles

1, 2

External RESET and NMI pin interrupt pulse width —

Asynchronous path

100

50

—

ns

3

4

GPIO pin interrupt pulse width (digital glitch filter

disabled, passive filter disabled) — Asynchronous

path

ns

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses

may or may not be recognized. In Stop and VLPS modes, the synchronizer is bypassed so shorter pulses can be

recognized in that case.

2. The greater of synchronous and asynchronous timing must be met.

3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be

recognized.

4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be

recognized.

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5.3.2.4 AC specifications at 3.3 V range

Table 37. Functional pad AC specifications

Characteristic

Symbol

Min

Typ

Max

Unit

I/O Supply Voltage

Vdd ¹

2.7

4

V

1. Max power supply ramp rate is 500 V/ms.

Name

Prop Delay (ns) ¹

Rise/Fall Edge (ns) ²

Min Max

Drive Load (pF)

Max

17.5

28

Normal drive I/O pad

High drive I/O pad

CMOS Input ³

5

9

17

32

17

33

3

25

50

25

50

0.5

19

5

26

9

4

1.2

1. Propagation delay measured from 50ꢀ of core side input to 50ꢀ of the output.

2. Edges measured using 20ꢀ and 80ꢀ of the VDD supply.

3. Input slope = 2 ns.

NOTE

All measurements were taken accounting for 150 mV drop

across VDD and VSS.

5.3.2.5 AC specifications at 5 V range

Table 38. Functional pad AC specifications

Characteristic

Symbol

Min

Typ

Max

5.5

Unit

I/O Supply Voltage

Vdd ¹

4

V

1. Max power supply ramp rate is 500 V/ms.

Name

Prop Delay (ns) ¹

Rise/Fall Edge (ns) ²

Min Max

Drive Load (pF)

Max

12

18

13

19

3

Normal drive I/O pad

High drive I/O pad

CMOS Input ³

3.6

8

10

17

10

19

2.8

25

50

25

50

0.5

3.6

8

1.2

1. As measured from 50ꢀ of core side input to 50ꢀ of the output.

2. Edges measured using 20ꢀ and 80ꢀ of the VDD supply.

3. Input slope = 2 ns.

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Electrical characteristics

NOTE

All measurements were taken accounting for 150 mV drop

across VDD and VSS.

5.3.3 Thermal specifications

5.3.3.1 Thermal operating requirements

Table 39. Thermal operating requirements

Symbol

T_J

Description

Min.

–40

Max.

125

Unit

°C

Notes

Die junction temperature

Ambient temperature

T_A

105

°C

1

1. Maximum T_Acan be exceeded only if the user ensures that T_Jdoes not exceed maximum T_J. The simplest method to

determine T_Jis: T_J= T_A+ R_ΘJA× chip power dissipation.

5.3.3.2 Thermal attributes

5.3.3.2.1 Description

The tables in the following sections describe the thermal characteristics of the device.

NOTE

Junction temperature is a function of die size, on-chip power

dissipation, package thermal resistance, mounting side

(board) temperature, ambient temperature, air flow, power

dissipation or other components on the board, and board

thermal resistance.

5.3.3.2.2 Thermal characteristics for the 64-pin LQFP package

Table 40. Thermal characteristics for the 64-pin LQFP package

Rating

Conditions

Symbol

Value

Unit

Thermal resistance, Junction to Ambient

(Natural Convection)^{1, 2}

Single layer board (1s)

R_θJA

62

°C/W

Thermal resistance, Junction to Ambient

(Natural Convection)^{1, 2}

Four layer board (2s2p)

Single layer board (1s)

R_θJA

44

50

°C/W

Thermal resistance, Junction to Ambient

(@200 ft/min)^{1, 3}

R_θJMA

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Table 40. Thermal characteristics for the 64-pin LQFP package (continued)

Rating

Conditions

Symbol

Value

Unit

Thermal resistance, Junction to Ambient

(@200 ft/min)^{1, 3}

Four layer board (2s2p)

R_θJMA

37

°C/W

Thermal resistance, Junction to Board⁴

Thermal resistance, Junction to Case ⁵

Thermal resistance, Junction to Package Top⁶

—

R_θJB

R_θJC

ψ_JT

26

14

2

°C/W

Natural Convection

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

2. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for

1s or 2s2p board, respectively.

3. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s

or 2s2p board, respectively.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

5.3.3.2.3 Thermal characteristics for the 100-pin LQFP package

Table 41. Thermal characteristics for the 100-pin LQFP package

Rating

Conditions

Symbol

Value

Unit

Thermal resistance, Junction to Ambient

(Natural Convection)^{1, 2}

Single layer board (1s)

R_θJA

59

°C/W

Thermal resistance, Junction to Ambient

(Natural Convection)^{1, 2}

Four layer board (2s2p)

Single layer board (1s)

Four layer board (2s2p)

R_θJA

R_θJMA

46

49

40

°C/W

Thermal resistance, Junction to Ambient

(@200 ft/min)^{1, 3}

Thermal resistance, Junction to Ambient

(@200 ft/min)^{1, 3}

Thermal resistance, Junction to Board⁴

Thermal resistance, Junction to Case ⁵

Thermal resistance, Junction to Package Top⁶

—

R_θJB

R_θJC

ψ_JT

31

16

2

°C/W

Natural Convection

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

2. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for

1s or 2s2p board, respectively.

3. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s

or 2s2p board, respectively.

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured

on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

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6. Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2.

5.3.3.2.4 General notes for specifications at maximum junction temperature

An estimation of the chip junction temperature, T_J, can be obtained from this

equation:

T_J= T_A+ (R_θJA× P_D)

where:

• T_A= ambient temperature for the package (°C)

• R_θJA= junction to ambient thermal resistance (°C/W)

• P_D= power dissipation in the package (W)

The junction to ambient thermal resistance is an industry standard value that provides

a quick and easy estimation of thermal performance. Unfortunately, there are two

values in common usage: the value determined on a single layer board and the value

obtained on a board with two planes. For packages such as the PBGA, these values

can be different by a factor of two. Which value is closer to the application depends

on the power dissipated by other components on the board. The value obtained on a

single layer board is appropriate for the tightly packed printed circuit board. The value

obtained on the board with the internal planes is usually appropriate if the board has

low power dissipation and the components are well separated.

When a heat sink is used, the thermal resistance is expressed in the following equation

as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal

resistance:

R_θJA= R_θJC+ R_θCA

where:

• R_θJA= junction to ambient thermal resistance (°C/W)

• R_θJC= junction to case thermal resistance (°C/W)

• R_θCA= case to ambient thermal resistance (°C/W)

R_θJCis device related and cannot be influenced by the user. The user controls the

thermal environment to change the case to ambient thermal resistance, R_θCA. For

instance, the user can change the size of the heat sink, the air flow around the device,

the interface material, the mounting arrangement on printed circuit board, or change

the thermal dissipation on the printed circuit board surrounding the device.

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To determine the junction temperature of the device in the application when heat sinks

are not used, the Thermal Characterization Parameter (Ψ_JT) can be used to determine

the junction temperature with a measurement of the temperature at the top center of the

package case using this equation:

T_J= T_T+ (Ψ_JT× P_D)

where:

• T_T= thermocouple temperature on top of the package (°C)

• Ψ_JT= thermal characterization parameter (°C/W)

• P_D= power dissipation in the package (W)

The thermal characterization parameter is measured per JESD51-2 specification using a

40 gauge type T thermocouple epoxied to the top center of the package case. The

thermocouple should be positioned so that the thermocouple junction rests on the

package. A small amount of epoxy is placed over the thermocouple junction and over

about 1 mm of wire extending from the junction. The thermocouple wire is placed flat

against the package case to avoid measurement errors caused by cooling effects of the

thermocouple wire.

5.4 Peripheral operating requirements and behaviors

5.4.1 System modules

There are no specifications necessary for the device's system modules.

5.4.2 Clock interface modules

5.4.2.1 Oscillator electrical specifications

5.4.2.1.1 External Oscillator electrical specifications

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Single input buffer

(EXTAL32 WAVE)

ref_clk

mux

Differential input comparator

(VLP mode)

Peak detector

LP mode

Driver

(VLP mode)

Pull down resistor (OFF)

ESD PAD

300 ohms

ESD PAD

300 ohms

XTAL32 pin

EXTAL32 pin

Series resistor for current

limitation

Crystal or resonator

C1

C2

Figure 17. Oscillator connections scheme (OSC32)

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Electrical characteristics

Single input buffer

(EXTAL WAVE)

ref_clk

mux

Differential input comparator

(HG/LP mode)

Peak detector

LP mode

Driver

(HG/LP mode)

Pull down resistor (OFF)

ESD PAD

300 ohms

ESD PAD

40 ohms

XTAL pin

EXTAL pin

1

Series resistor for current

limitation

1M ohms Feedback Resistor

Crystal or resonator

C1

C2

NOTE:

1. 1M Feedback resistor is needed only for HG mode.

Figure 18. Oscillator connections scheme (OSC)

NOTE

Data values in the following "External Oscillator electrical

specifications" tables are from simulation.

Table 42. External Oscillator electrical specifications (OSC32)

Symbol Description

V_DDSupply voltage

Min.

Typ.

—

Max.

5.5

Unit

V

Notes

2.7

I_DDOSC32Supply current

—

6

500

—

nA

1

g_mXOSC32Oscillator transconductance

9

µA/V

V

V_IH

Input high voltage — EXTAL32 pin in external

clock mode

0.7 × V_DD

—

V_DD+0.3

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Table 42. External Oscillator electrical specifications (OSC32) (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

@V_DD=3.3 V

@V_DD=5.0 V

0.65 × V_DD

V_SS–0.3

—

V_DD+0.3

V

V_IL

Input low voltage — EXTAL32 pin in external

0.3 ×

V_DD

clock mode

@V_DD=3.3 V

@V_DD=5.0 V

V_SS–0.3

—

0.35 ×

V_DD

V

C₁

C₂

R_F

R_S

EXTAL32 load capacitance

XTAL32 load capacitance

Feedback resistor

—

2

—

MΩ

kΩ

V

Series resistor

—

V_{pp_OSC32}Peak-to-peak amplitude of oscillation (oscillator

mode)

0.6

3

1. Measured at V_DD= 5 V, Temperature = 25 °C. The current consumption is according to the crystal or resonator,

loading capacitance.

2. C1 and C2 must be provided by external capacitors and their load capacitance depends on the crystal or resonator

manufacturers' recommendation. Please check the crystal datasheet for the recommended values. And also consider

the parasitic capacitance of package and board.

3. The EXTAL32 and XTAL32 pins should only be connected to required oscillator components and must not be

connected to any other devices.

Table 43. External Oscillator electrical specifications (OSC)

Symbol

V_DD

Description

Min.

Typ.

Max.

Unit Notes

Supply voltage

2.7

—

5.5

V

I_DDOSC

Supply current — low-gain mode (low-power mode) (HGO=0)

1

4 MHz

—

200

300

1.2

1.6

2

—

µA

mA

1

8 MHz

16 MHz

24 MHz

32 MHz

40 MHz

2.6

I_DDOSC

Supply current — high-gain mode (HGO=1)

32 kHz

—

25

1

—

µA

mA

4 MHz

8 MHz

1.2

3.5

5

16 MHz

24 MHz

32 MHz

5.5

6

40 MHz

g_mXOSC

Fast external crystal oscillator transconductance

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Electrical characteristics

Table 43. External Oscillator electrical specifications (OSC)

(continued)

Symbol

Description

Min.

15

Typ.

—

Max.

45

Unit Notes

µA / V

32 kHz, Low Frequency Range, High Gain (32 kHz)

Medium Frequency Range (4-8 MHz)

2.2

16

—

9.7

37

mA / V

V

High Frequency Range (8-40 MHz)

V_IH

V_IL

Input high voltage — EXTAL pin in external clock

mode

1.75

—

V_DD

Input low voltage — EXTAL pin in external clock

mode

V_SS

1.20

V

C₁

C₂

R_F

EXTAL load capacitance

XTAL load capacitance

—

2

Feedback resistor

3

Low-frequency, high-gain mode (32 kHz)

—

10

—

MΩ

Medium/high-frequency, low-gain mode (low-power

mode) (4-8 MHz, 8-40 MHz)

MΩ

Medium/high-frequency, high-gain mode (4-8 MHz,

8-40 MHz)

—

1

—

MΩ

R_S

Series resistor

Low-frequency, high-gain mode (32 kHz)

—

200

0

—

kΩ

Medium/high-frequency, low-gain mode (low-power

mode) (4-8 MHz, 8-40 MHz)

Medium/high-frequency, high-gain mode (4-8 MHz,

8-40 MHz)

—

0

—

kΩ

V_pp

Peak-to-peak amplitude of oscillation (oscillator mode)

Low-frequency, high-gain mode

4

—

3.3

1.0

3.3

—

V

Medium/high-frequency, low-gain mode

Medium/high-frequency, high-gain mode

1. Measured at V_DD= 5 V, Temperature = 25 °C. The current consumption is according to the crystal or resonator, loading

capacitance.

2. C1 and C2 must be provided by external capacitors and their load capacitance depends on the crystal or resonator

manufacturers' recommendation. Please check the crystal datasheet for the recommended values. And also consider

the parasitic capacitance of package and board.

3. When low power mode is selected, R_Fis integrated and must not be attached externally.

4. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

any other devices.

5.4.2.1.2 External Oscillator frequency specifications

Table 44. External Oscillator frequency specifications (OSC32)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

f_{osc32_lo}Oscillator crystal or resonator frequency — low-

frequency mode

30

—

40

kHz

t_{dc_extal32}Input clock duty cycle (external clock mode)

40

50

60

ꢀ

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Electrical characteristics

Table 44. External Oscillator frequency specifications (OSC32) (continued)

Symbol Description

Min.

—

Typ.

—

Max.

40

Unit

kHz

ms

Notes

f_{ec_extal32}Input clock frequency (external clock mode)

t_cst32

Crystal startup time — 32 kHz low-frequency,

low-power mode (HGO=0)

—

2000

—

1

1. The start-up measured after 4096 cycles. Proper PC board layout procedures must be followed to achieve

specifications.

Table 45. External Oscillator frequency specifications (OSC)

Symbol Description

f_{osc_lo}Oscillator crystal or resonator frequency — Low

Frequency, High Gain Mode

Min.

Typ.

Max.

Unit

Notes

32

—

40

kHz

f_{osc_me}Oscillator crystal or resonator frequency —

Medium Frequency

4

8

—

8

MHz

f_{osc_hi}

Oscillator crystal or resonator frequency —

High Frequency

40

t_{dc_extal}Input clock duty cycle (external clock mode)

f_{ec_extal}Input clock frequency (external clock mode)

40

—

50

—

60

50

—

ꢀ

MHz

ms

t_cst

Crystal startup time — 32 kHz Low Frequency,

High-Gain Mode

500

1

Crystal startup time — 8 MHz Medium

Frequency, Low-Power Mode

—

1.5

2.5

2

—

Crystal startup time — 8 MHz Medium

Frequency, High-Gain Mode

Crystal startup time — 40 MHz High

Frequency, Low-Power Mode

Crystal startup time — 40 MHz High

Frequency, High-Gain Mode

2.5

1. The start-up measured after 4096 cycles. Proper PC board layout procedures must be followed to achieve

specifications.

5.4.2.2 System Clock Generation (SCG) specifications

5.4.2.2.1 Fast internal RC Oscillator (FIRC) electrical specifications

Table 46. Fast internal RC Oscillator electrical specifications

Symbol

Parameter

Value

Typ.

Unit

Min.

Max.

F_FIRC

I_VDD

Fast internal reference frequency

Supply current

—

MHz

µA

48

—

400

500

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Table 46. Fast internal RC Oscillator electrical specifications

(continued)

Symbol

Parameter

Value

Typ.

—

Unit

Min.

F_IRC

Max.

F_IRC

F_UntrimmedIRC frequency (untrimmed)

×

MHz

(1-0.3)

(1+0.3)

ΔF_OL

Open loop total deviation of IRC frequency over voltage and

temperature¹

Regulator enable

Startup time

—

0.5

—

1

3

ꢀF_FIRC

µs²

T_Startup

T_JIT

Period jitter (RMS)

35

150

ps

1. The limit is respected across process, voltage and full temperature range.

2. Startup time is defined as the time between clock enablement and clock availability for system use.

5.4.2.2.2 Slow internal RC oscillator (SIRC) electrical specifications

Table 47. Slow internal RC oscillator (SIRC) electrical specifications

Symbol

Parameter

Value

Typ.

2

Unit

Min.

Max.

F_SIRC

Slow internal reference frequency

—

MHz

8

I_VDD

F_Untrimmed

ΔF_OL

Supply current

—

23

—

µA

IRC frequency (untrimmed)

—

MHz

Open loop total deviation of IRC frequency over

voltage and temperature¹

Regulator enable

Startup time

—

6

3

ꢀF_SIRC

µs²

T_Startup

—

1. The limit is respected across process, voltage and full temperature range.

2. Startup time is defined as the time between clock enablement and clock availability for system use.

5.4.2.2.3 Low Power Oscillator (LPO) electrical specifications

Table 48. Low Power Oscillator (LPO) electrical specifications

Symbol

F_LPO

Parameter

Internal low power oscillator frequency

Current consumption

Min.

113

1

Typ.

128

3

Max.

139

7

Unit

kHz

µA

I_LPO

T_startup

Startup Time

—

20

µs

5.4.2.2.4 LPFLL electrical specifications

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Table 49. LPFLL electrical specifications

Symbol

I_avg

Parameter

Min.

Typ.

240

3.6

—

Max.

Unit

μA

μs

Power consumption

Start-up time

T_start

ΔF_ol

Frequency accuracy over temperature and

voltage in open loop after process trimmed

–10

–1 ¹

10

ꢀ

ΔF_cl

Frequency accuracy in closed loop

—

1 ¹

ꢀ

1. ΔF_clis dependent on reference clock accuracy. For example, if locked to crystal oscillator, ΔF_clis typically limited by

trimming ability of the module itself; if locked to other clock source which has 3ꢀ accuracy, then ΔF_clcan only be

3ꢀ.

5.4.3 Memories and memory interfaces

5.4.3.1 Flash memory module (FTFE) electrical specifications

This section describes the electrical characteristics of the flash memory module

(FTFE).

5.4.3.1.1 Flash timing specifications — program and erase

The following specifications represent the amount of time the internal charge pumps

are active and do not include command overhead.

Table 50. NVM program/erase timing specifications

Symbol Description

Min.

—

Typ.

7.5

13

Max.

18

Unit

μs

Notes

t_hvpgm8Program Phrase high-voltage time

t_hversscrErase Flash Sector high-voltage time

t_hversblk32kErase Flash Block high-voltage time for 32 KB

t_hversblk256kErase Flash Block high-voltage time for 256 KB

—

113

226

1808

ms

1

—

26

—

208

1. Maximum time based on expectations at cycling end-of-life.

5.4.3.1.2 Flash timing specifications — commands

Table 51. Flash command timing specifications

Symbol Description

Read 1s Block execution time

Min.

Typ.

Max.

Unit

Notes

t_rd1blk32k

• 32 KB data flash

—

0.3

1.8

ms

t_rd1blk256k

• 256 KB program flash

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Electrical characteristics

Table 51. Flash command timing specifications (continued)

Symbol Description

Min.

—

Typ.

—

Max.

75

Unit

μs

Notes

t_rd1sec2kRead 1s Section execution time (2 KB flash)

t_pgmchkProgram Check execution time

1

—

95

μs

t_rdrsrc

t_pgm8

Read Resource execution time

Program Phrase execution time

Erase Flash Block execution time

• 32 KB data flash

—

40

μs

—

90

150

μs

2

t_ersblk32k

—

28

240

ms

t_ersblk256k

• 256 KB program flash

220

1850

t_ersscr

Erase Flash Sector execution time

—

15

2.5

—

115

—

ms

μs

2

1

t_pgmsec512Program Section execution time (512B flash)

t_rd1all

Read 1s All Blocks execution time

Read Once execution time

2.2

30

t_rdonce

—

t_pgmonceProgram Once execution time

90

—

μs

t_ersall

t_vfykey

t_ersallu

Erase All Blocks execution time

250

—

2100

30

ms

μs

2

1

2

Verify Backdoor Access Key execution time

Erase All Blocks Unsecure execution time

Program Partition for EEPROM execution time

• 24 KB EEPROM backup

250

2100

ms

t_pgmpart24k

t_pgmpart32k

—

69

70

—

ms

• 32 KB EEPROM backup

Set FlexRAM Function execution time:

• Control Code 0xFF

t_setramff

t_setram24k

t_setram32k

—

50

0.6

0.8

—

μs

ms

• 24 KB EEPROM backup

• 32 KB EEPROM backup

1.1

1.2

Byte-write to FlexRAM execution time:

• 24 KB EEPROM backup

t_eewr8b24k

t_eewr8b32k

—

370

385

1625

1700

μs

• 32 KB EEPROM backup

16-bit write to FlexRAM execution time:

• 24 KB EEPROM backup

t_eewr16b24k

t_eewr16b32k

—

370

385

1625

1700

μs

• 32 KB EEPROM backup

t_eewr32bers32-bit write to erased FlexRAM location

execution time

—

360

1500

μs

32-bit write to FlexRAM execution time:

t_eewr32b24k

t_eewr32b32k

• 24 KB EEPROM backup

• 32 KB EEPROM backup

—

600

630

1950

2000

μs

1. Assumes 25MHz or greater flash clock frequency.

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

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5.4.3.1.3 Flash high voltage current behaviors

Table 52. Flash high voltage current behaviors

Symbol

Description

Min.

Typ.

Max.

Unit

I_{DD_PGM}

Average current adder during high voltage flash

programming operation

—

3.5

7.5

mA

I_{DD_ERS}

Average current adder during high voltage flash

erase operation

—

1.5

4.0

mA

5.4.3.1.4 Reliability specifications

Table 53. NVM reliability specifications

Symbol Description

Min.

Program Flash

Typ.¹

Max.

Unit

Notes

t_nvmretp10kData retention after up to 10 K cycles

t_nvmretp1kData retention after up to 1 K cycles

n_nvmcycpCycling endurance

5

50

—

years

cycles

20

100

50 K

10 K

2

Data Flash

t_nvmretd10kData retention after up to 10 K cycles

t_nvmretd1kData retention after up to 1 K cycles

n_nvmcycdCycling endurance

5

50

—

years

cycles

20

100

50 K

10 K

FlexRAM as EEPROM

t_nvmretee100Data retention up to 100ꢀ of write endurance

t_nvmretee10Data retention up to 10ꢀ of write endurance

n_nvmcyceeCycling endurance for EEPROM backup

Write endurance

5

50

—

years

cycles

20

100

50 K

20 K

2

3

n_nvmwree16

n_nvmwree128

n_nvmwree512

n_nvmwree1k

• EEPROM backup to FlexRAM ratio = 16

• EEPROM backup to FlexRAM ratio = 128

• EEPROM backup to FlexRAM ratio = 512

• EEPROM backup to FlexRAM ratio = 1,024

140 K

1.26 M

5 M

400 K

3.2 M

12.8 M

25 M

—

writes

10 M

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a

constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in

Engineering Bulletin EB619.

2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ T_j≤ 125 °C.

3. Write endurance represents the number of writes to each FlexRAM location at -40 °C ≤Tj ≤ 125 °C influenced by the

cycling endurance of the FlexNVM and the allocated EEPROM backup. Minimum and typical values assume all 16-bit

or 32-bit writes to FlexRAM; all 8-bit writes result in 50ꢀ less endurance.

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Electrical characteristics

5.4.4 Security and integrity modules

There are no specifications necessary for the device's security and integrity modules.

5.4.5 Analog

5.4.5.1 ADC electrical specifications

5.4.5.1.1 12-bit ADC operating conditions

Table 54. 12-bit ADC operating conditions

Symbol Description

Conditions

Absolute

Min.

2.7

Typ.¹

Max.

5.5

Unit

V

Notes

V_DDA

Supply voltage

—

ΔV_DDA

Delta to V_DD

-100

0

+100

mV

2

3

(V_DD– V_DDA

)

ΔV_SSA

Ground voltage

Delta to V_SS(V_SS

-100

2.5

0

+100

mV

V

– V_SSA

)

V_REFH

ADC reference voltage high

V_DDA

V_DDA+

100m

V_REFL

V_ADIN

R_S

ADC reference voltage low

Input voltage

− 100

V_REFL

—

0

100

V_REFH

5

mV

V

—

0.5

Source impedendance

f_ADCK< 4 MHz

kΩ

R_SW1

Channel Selection Switch

Impedance

—

1.2

R_AD

C_P1

C_P2

C_S

Sampling Switch Impedance

Pin Capacitance

—

2

3

5

—

5

kΩ

pF

Analog Bus Capacitance

Sampling capacitance

—

4

pF

5

pF

f_ADCK

ADC conversion clock

frequency

40

50

MHz

4, 5

7

C_rate

ADC conversion rate

No ADC

20

—

1200

Ksps

hardware

averaging⁶

Continuous

conversions

enabled,

subsequent

conversion time

1. Typical values assume V_DDA= 5 V, Temp = 25 °C, f_ADCK= 40 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

2. DC potential difference.

3. For packages without dedicated V_REFHand V_REFLpins, V_REFHis internally tied to V_DDA, and V_REFLis internally tied to

V_SSA

.

4. Clock and compare cycle need to be set according the guidelines in the block guide.

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5. ADC conversion will become less reliable above maximum frequency.

6. When using ADC hardware averaging, refer to the device Reference Manual to determine the most appropriate

setting for AVGS.

7. Max ADC conversion rate of 1200 Ksps is with 10-bit mode

Figure 19. ADC input impedance equivalency diagram

5.4.5.1.2 12-bit ADC electrical characteristics

NOTE

All the parameters in the table are given assuming system

clock as the clocking source for ADC.

NOTE

For ADC signals adjacent to VDD/VSS or the XTAL pins

some degradation in the ADC performance may be

observed.

NOTE

All values guarantee the performance of the ADC for the

multiple ADC input channel pins. When using the ADC to

monitor the internal analogue parameters, please assume

minor degradation.

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Table 55. 12-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA

)

Symbol Description

Conditions¹

Min.

Typ.²

Max. ³

Unit

Notes

I_{DDA_ADC}Supply current at 2.7 to

5.5 V

927

975 μA @

5 V

1023

μA

4

Sample Time

275

—

Refer to

the

ns

device's

Reference

Manual

TUE

DNL

INL

Total unadjusted error

at 2.7 to 5.5 V

—

4.5

0.8

1.4

–2

6.11

1.07

3.54

-3.60

-4.24

0.5

LSB⁵

bits

6

Differential non-

linearity at 2.7 to 5.5 V

6

Integral non-linearity at

2.7 to 5.5 V

6

E_FS

Full-scale error at 2.7

to 5.5 V

V_ADIN= V_DDA

E_ZS

Zero-scale error at 2.7

to 5.5 V

–2.7

—

E_Q

Quantization error at

2.7 to 5.5 V

ENOB

Effective number of bits

at 2.7 to 5.5 V

11.3

70

—

7

Signal-to-noise plus

See ENOB

—

SINAD = 6.02 ×

ENOB + 1.76

SINAD distortion at 2.7 to 5.5

V

dB

E_IL

Input leakage error at

2.7 to 5.5 V

I_In× R_AS

mV

I_In= leakage

current (refer to

the MCU's

voltage and

current operating

ratings)

V_{TEMP_S}Temp sensor slope at Across the full

1.492

730

1.564

740.5

1.636

751

mV/°C

mV

8, 9

2.7 to 5.5 V

temperature

range of the

device

V_TEMP25Temp sensor voltage at 25 °C

2.7 to 5.5 V

8, 9

1. All accuracy numbers assume the ADC is calibrated with V_REFH= V_DDA

2. Typical values assume V_DDA= 5.0 V, Temp = 25 °C, f_ADCK= 48 MHz unless otherwise stated.

3. These values are based on characterization but not covered by test limits in production.

4. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low

power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1

MHz ADC conversion clock speed.

5. 1 LSB = (V_REFH- V_REFL)/2^N

6. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = ꢀ1, AVGS = ꢀ11)

7. Input data is 100 Hz sine wave. ADC conversion clock < 40 MHz.

8. ADC conversion clock < 3 MHz

9. The sensor must be calibrated to gain good accuracy, so as to provide good linearity, see also AN3031 for more detailed

application information of the temperature sensor.

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5.4.5.2 CMP with 8-bit DAC electrical specifications

Table 56. Comparator with 8-bit DAC electrical specifications

Symbol

V_DD

Description

Min.

Typ. ¹

Max.

Unit

V

Supply voltage

2.7

—

5.5

I_DDHS

Supply current, High-speed mode²

within ambient temperature range

Supply current, Low-speed mode²

within ambient temperature range

Analog input voltage

μA

—

145

200

I_DDLS

μA

—

0

5

10

V_AIN

V_AIO

0 - V_DDX

V_DDX

V

Analog input offset voltage, High-speed mode

within ambient temperature range

Analog input offset voltage, Low-speed mode

within ambient temperature range

Propagation delay, High-speed mode³

within ambient temperature range

Propagation delay, Low-speed mode³

within ambient temperature range

Propagation delay, High-speed mode⁴

within ambient temperature range

Propagation delay, Low-speed mode⁴

within ambient temperature range

Initialization delay, High-speed mode ³

within ambient temperature range

Initialization delay, Low-speed mode³

within ambient temperature range

mV

-25

-40

—

1

4

25

40

200

2

V_AIO

t_DHSB

t_DLSB

t_DHSS

t_DLSS

t_IDHS

mV

ns

30

0.5

70

1

µs

ns

400

5

µs

μs

1.5

10

0

3

t_IDLS

μs

30

—

V_HYST0

Analog comparator hysteresis, Hyst0 (V_AIO

within ambient temperature range

)

mV

V_HYST1

Analog comparator hysteresis, Hyst1, High-speed

mode

within ambient temperature range

—

16

11

32

22

53

30

90

53

Analog comparator hysteresis, Hyst1, Low-speed

mode

within ambient temperature range

V_HYST2

Analog comparator hysteresis, Hyst2, High-speed

mode

mV

within ambient temperature range

Analog comparator hysteresis, Hyst2, Low-speed

mode

within ambient temperature range

Table continues on the next page...

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Electrical characteristics

Table 56. Comparator with 8-bit DAC electrical specifications (continued)

Symbol

Description

Min.

Typ. ¹

Max.

Unit

V_HYST3

Analog comparator hysteresis, Hyst3, High-speed

mode

mV

within ambient temperature range

—

48

133

Analog comparator hysteresis, Hyst3, Low-speed

mode

within ambient temperature range

8-bit DAC current adder (enabled)

8-bit DAC integral non-linearity

8-bit DAC differential non-linearity

—

33

10

—

80

16

I_DAC8b

INL

μA

LSB⁵

–0.6

–0.5

0.5

DNL

LSB

1. Typical values assumed at VDDA = 5.0 V, Temp = 25 ℃, unless otherwise stated.

2. Difference at input > 200mV

3. Applied (100 mV + Hyst) around switch point

4. Applied (30 mV + 2 × Hyst) around switch point

5. 1 LSB = V_reference/256

Figure 20. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

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Electrical characteristics

Figure 21. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

Figure 22. Typical hysteresis vs. Vin level (VDD = 5 V, PMODE = 0)

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Electrical characteristics

Figure 23. Typical hysteresis vs. Vin level (VDD = 5 V, PMODE = 1)

5.4.6 Communication interfaces

5.4.6.1 LPUART electrical specifications

Refer to General AC specifications for LPUART specifications.

5.4.6.2 LPSPI electrical specifications

The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus

with master and slave operations. Many of the transfer attributes are programmable.

The following tables provide timing characteristics for classic LPSPI timing modes.

All timing is shown with respect to 20% V_DDand 80% V_DDthresholds, unless noted, as

well as input signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins.

Table 57. LPSPI master mode timing

Num.

Symbol Description

f_SPSCKFrequency of SPSCK

t_SPSCK

Min.

Max.

Unit

Hz

Note

1

2

f_periph/2048

2 x t_periph

f_periph/2

1

2

SPSCK period

2048 x

t_periph

ns

3

4

t_Lead

t_Lag

Enable lead time

Enable lag time

1/2

—

t_SPSCK

—

Table continues on the next page...

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Electrical characteristics

Table 57. LPSPI master mode timing (continued)

Num.

Symbol Description

Min.

Max.

Unit

Note

5

t_WSPSCKClock (SPSCK) high or low time

t_periph- 30

1024 x

t_periph

ns

—

6

7

t_SU

t_HI

Data setup time (inputs)

Data hold time (inputs)

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

18

0

—

ns

—

15

8

t_v

—

0

9

t_HO

t_RI

—

10

—

t_periph- 25

t_FI

Fall time input

11

t_RO

t_FO

Rise time output

—

25

ns

—

Fall time output

1. f_periphis LPSPI peripheral functional clock. On this device, the max value of f_SPSCKshould not exceed 25 MHz.

2. t_periph= 1/f_periph

NOTE

High drive pin should be used for fast bit rate.

1

SS

(OUTPUT)

3

2

10

11

4

SPSCK

(CPOL=0)

(OUTPUT)

5

SPSCK

(CPOL=1)

(OUTPUT)

6

7

MISO

(INPUT)

2

BIT 6 . . . 1

8

MSB IN

LSB IN

9

MOSI

(OUTPUT)

2

BIT 6 . . . 1

MSB OUT

LSB OUT

1. If configured as an output.

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 24. LPSPI master mode timing (CPHA = 0)

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Electrical characteristics

1

SS

(OUTPUT)

2

10

11

4

3

SPSCK

(CPOL=0)

(OUTPUT)

5

SPSCK

(CPOL=1)

(OUTPUT)

6

7

MISO

(INPUT)

2

BIT 6 . . . 1

LSB IN

MSB IN

9

8

MOSI

(OUTPUT)

2

PORT DATA

BIT 6 . . . 1

MASTER MSB OUT

PORT DATA

MASTER LSB OUT

1.If configured as output

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Figure 25. LPSPI master mode timing (CPHA = 1)

Table 58. LPSPI slave mode timing

Num.

1

Symbol Description

Min.

Max.

Unit

Hz

Note

1

f_SPSCK

t_SPSCK

t_Lead

Frequency of SPSCK

SPSCK period

0

f_periph/2

2

2 x t_periph

—

ns

2

3

Enable lead time

Enable lag time

1

t_periph

ns

—

3

4

t_Lag

1

—

5

t_WSPSCKClock (SPSCK) high or low time

t_periph- 30

—

6

t_SU

t_HI

t_a

Data setup time (inputs)

Data hold time (inputs)

Slave access time

2.5

3.5

—

0

—

ns

7

—

ns

8

t_periph

31

ns

9

t_dis

t_v

Slave MISO disable time

Data valid (after SPSCK edge)

Data hold time (outputs)

Rise time input

ns

4

10

11

12

ns

—

t_HO

t_RI

t_FI

—

ns

—

t_periph- 25

ns

Fall time input

13

t_RO

t_FO

Rise time output

—

25

ns

—

Fall time output

1. f_periphis LPSPI peripheral functional clock. On this device, the max value of f_SPSCKshould not exceed 25 MHz.

2. t_periph= 1/f_periph

3. Time to data active from high-impedance state

4. Hold time to high-impedance state

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Electrical characteristics

SS

(INPUT)

2

12

13

4

SPSCK

(CPOL=0)

(INPUT)

5

3

SPSCK

(CPOL=1)

(INPUT)

9

8

10

11

see

note

SEE

NOTE

MISO

(OUTPUT)

BIT 6 . . . 1

SLAVE MSB

7

SLAVE LSB OUT

6

MOSI

(INPUT)

LSB IN

MSB IN

BIT 6 . . . 1

Figure 26. LPSPI slave mode timing (CPHA = 0)

SS

(INPUT)

4

2

12

13

3

SPSCK

(CPOL=0)

(INPUT)

5

SPSCK

(CPOL=1)

(INPUT)

11

9

10

SLAVE MSB OUT

see

note

MISO

(OUTPUT)

BIT 6 . . . 1

SLAVE LSB OUT

LSB IN

8

6

7

MOSI

(INPUT)

MSB IN

Figure 27. LPSPI slave mode timing (CPHA = 1)

5.4.6.3 LPI²C

Table 59. LPI²C specifications

Symbol Description

Min.

Max.

100

Unit

Notes

f_SCL

SCL clock frequency

Standard mode (Sm)

Fast mode (Fm)

0

kHz

1, 2, 3

400

Fast mode Plus (Fm+)

Ultra Fast mode (UFm)

High speed mode (Hs-mode)

1000

5000

3400

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Electrical characteristics

1. Hs-mode is only supported in slave mode.

2. The maximum SCL clock frequency in Fast mode with maximum bus loading (400pF) can only be achieved with

appropriate pull-up devices on the bus when using the high or normal drive pins across the full voltage range . The

maximum SCL clock frequency in Fast mode Plus can support maximum bus loading (400pF) with appropriate pull-up

devices when using the high drive pins. The maximum SCL clock frequency in Ultra Fast mode can support maximum

bus loading (400pF) when using the high drive pins. The maximum SCL clock frequency for slave in High speed mode

can support maximum bus loading (400pF) with appropriate pull-up devices when using the high drive pins. For more

information on the required pull-up devices, see I²C Bus Specification.

3. See the section "General switching specifications".

5.4.7 Human-machine interfaces (HMI)

5.4.7.1 Touch sensing input (TSI) electrical specifications

Table 60. TSI electrical specifications

Symbol

Description

Value

Typ

Unit

Min

Max

I_{DD_EN}

Power

—

500

600

µA

consumption in

operation mode

I_{DD_DIS}

Power

—

20

355

nA

consumption in

disable mode

V_BG

V_PRE

C_I

Internal bandgap

reference voltage

—

1.21

1.51

90

—

V

Internal bias

voltage

Internal integration

capacitance

pF

F_CLK

Internal main clock

frequency

16

MHz

5.4.8 Debug modules

5.4.8.1 SWD electricals

Table 61. SWD full voltage range electricals

Symbol

V_DDA

S1

Description

Min.

Max.

5.5

Unit

Operating voltage

2.7

0

V

SWD_CLK frequency of operation

25

MHz

Table continues on the next page...

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Design considerations

Table 61. SWD full voltage range electricals (continued)

Symbol

S2

Description

Min.

1/S1

15

Max.

—

Unit

ns

SWD_CLK cycle period

S3

SWD_CLK clock pulse width

—

ns

S4

SWD_CLK rise and fall times

—

3

ns

S9

SWD_DIO input data setup time to SWD_CLK rise

SWD_DIO input data hold time after SWD_CLK rise

SWD_CLK high to SWD_DIO data valid

SWD_CLK high to SWD_DIO high-Z

8

—

ns

S10

S11

S12

1.4

—

ns

25

—

ns

5

ns

S2

S4

S3

SWD_CLK (input)

S4

Figure 28. Serial wire clock input timing

SWD_CLK

SWD_DIO

S9

S10

Input data valid

S11

Output data valid

S12

S11

Output data valid

Figure 29. Serial wire data timing

6 Design considerations

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Design considerations

6.1 Hardware design considerations

This device contains protective circuitry to guard against damage due to high static

voltage or electric fields. However, take normal precautions to avoid application of any

voltages higher than maximum-rated voltages to this high-impedance circuit.

6.1.1 Printed circuit board recommendations

• Place connectors or cables on one edge of the board and do not place digital circuits

between connectors.

• Drivers and filters for I/O functions must be placed as close to the connectors as

possible. Connect TVS devices at the connector to a good ground. Connect filter

capacitors at the connector to a good ground. Consider to add ferrite bead or

inductor to some sensitive lines.

• Physically isolate analog circuits from digital circuits if possible.

• Place input filter capacitors as close to the MCU as possible.

• For best EMC performance, route signals as transmission lines; use a ground plane

directly under LQFP packages; and solder the exposed pad (EP) to ground directly

under QFN packages.

6.1.2 Power delivery system

Consider the following items in the power delivery system:

• Use a plane for ground.

• Use a plane for MCU VDD supply if possible.

• Always route ground first, as a plane or continuous surface, and never as sequential

segments.

• Always route the power net as star topology, and make each power trace loop as

minimum as possible.

• Route power next, as a plane or traces that are parallel to ground traces.

• Place bulk capacitance, 10 μF or more, at the entrance of the power plane.

• Place bypass capacitors for MCU power domain as close as possible to each

VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.

• The minimum bypass requirement is to place 0.1 μF capacitors positioned as near

as possible to the package supply pins.

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Design considerations

6.1.3 Analog design

Each ADC input must have an RC filter as shown in the following figure. The

maximum value of R must be RAS max if fast sampling and high resolution are

required. The value of C must be chosen to ensure that the RC time constant is very

small compared to the sample period.

MCU

1

2

Input signal

ADCx

R

C

Figure 30. RC circuit for ADC input

High voltage measurement circuits require voltage division, current limiting, and

over-voltage protection as shown the following figure. The voltage divider formed by

R1 – R4 must yield a voltage less than or equal to VREFH. The current must be

limited to less than the injection current limit. External clamp diodes can be added

here to protect against transient over-voltages.

MCU

R1

R2

R3

VDD

1

2

R5

1

2

ADCx

High voltage input

R4

1

2

C

BAT54SW

Figure 31. High voltage measurement with an ADC input

NOTE

For more details of ADC related usage, refer to AN5250:

How to Increase the Analog-to-Digital Converter Accuracy

in an Application.

6.1.4 Digital design

Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V).

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Design considerations

CAUTION

Do not provide power to I/O pins prior to VDD, especially the

RESET_b pin.

• RESET_b pin

The RESET_b pin is a pseudo open-drain I/O pin that has an internal pullup

resistor. An external RC circuit is recommended to filter noise as shown in the

following figure. The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the

recommended capacitance value is 0.1 μF. The RESET_b pin also has a selectable

digital filter to reject spurious noise.

VDD

MCU

10k

RESET_b

0.1uF

Figure 32. Reset circuit

When an external supervisor chip is connected to the RESET_b pin, a series

resistor must be used to avoid damaging the supervisor chip or the RESET_b pin,

as shown in the following figure. The series resistor value (RS below) must be in

the range of 100 Ω to 1 kΩ depending on the external reset chip drive strength. The

supervisor chip must have an active high, open-drain output.

VDD

Supervisor Chip

MCU

10k

1

2

OUT

RESET_b

RS

Active high,

open drain

0.1uF

Figure 33. Reset signal connection to external reset chip

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Design considerations

• NMI pin

Do not add a pull-down resistor or capacitor on the NMI_b pin, because a low

level on this pin will trigger non-maskable interrupt. When this pin is enabled as

the NMI function, an external pull-up resistor (10 kΩ) as shown in the following

figure is recommended for robustness.

If the NMI_b pin is used as an I/O pin, the non-maskable interrupt handler is

required to disable the NMI function by remapping to another function. The NMI

function is disabled by programming the FOPT[NMI_DIS] bit to zero.

VDD

MCU

10k

NMI_b

Figure 34. NMI pin biasing

• Debug interface

This MCU uses the standard ARM SWD interface protocol as shown in the

following figure. While pull-up or pull-down resistors are not required

(SWD_DIO has an internal pull-up and SWD_CLK has an internal pull-down),

external 10 kΩ pull resistors are recommended for system robustness. The

RESET_b pin recommendations mentioned above must also be considered.

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Design considerations

VDD

10k

VDD

J1

SWD_DIO

SWD_CLK

1

3

5

7

9

2

4

6

8

RESET_b

10k

10

0.1uF

HDR_5X2

Figure 35. SWD debug interface

• Unused pin

Unused GPIO pins must be left floating (no electrical connections) with the MUX

field of the pin’s PORTx_PCRn register equal to 0:0:0. This disables the digital

input path to the MCU.

6.1.5 Crystal oscillator

When using an external crystal or ceramic resonator as the frequency reference for the

MCU clock system, refer to the following table and diagrams.

The feedback resistor, RF, is incorporated internally with the low power oscillators. An

external feedback is required when using high gain (HGO=1) mode.

The series resistor, RS, is required in high gain (HGO=1) mode when the crystal or

resonator frequency is below 2 MHz. Otherwise, the low power oscillator (HGO=0)

must not have any series resistance; and the high frequency, high gain oscillator with a

frequency above 2 MHz does not require any series resistance.

OSC32

EXTAL32

XTAL32

1

2

Cx

Cy

CRYSTAL

Figure 36. RTC Oscillator (OSC32) module connection – Diagram 1

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Design considerations

Table 62. External crystal/resonator connections

Oscillator mode

Low frequency (32.768 kHz), high gain

High frequency (1-32 MHz), low power

High frequency (1-32 MHz), high gain

Oscillator mode

Diagram 3

Diagram 2

Diagram 3

OSCILLATOR

EXTAL

OSCILLATOR

XTAL

EXTAL

XTAL

1

2

1

3

CRYSTAL

Cx

Cy

RESONATOR

Figure 37. Crystal connection – Diagram 2

OSCILLATOR

EXTAL

OSCILLATOR

EXTAL

XTAL

1

2

1

2

RF

RS

1

2

1

3

CRYSTAL

Cx

Cy

RESONATOR

Figure 38. Crystal connection – Diagram 3

NOTE

For PCB layout, the user could consider to add the guard

ring to the crystal oscillator circuit.

6.2 Software considerations

All Kinetis MCUs are supported by comprehensive NXP and third-party hardware and

software enablement solutions, which can reduce development costs and time to

market. Featured software and tools are listed below. Visit http://www.nxp.com/

kinetis/sw for more information and supporting collateral.

Evaluation and Prototyping Hardware

• Freedom Development Platform: http://www.nxp.com/freedom

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

87

NXP Semiconductors

Part identification

IDEs for Kinetis MCUs

• Kinetis Design Studio IDE: http://www.nxp.com/kds

• Partner IDEs: http://www.nxp.com/kide

Run-time Software

• Kinetis SDK: http://www.nxp.com/ksdk

• Kinetis Bootloader: http://www.nxp.com/kboot

• ARM mbed Development Platform: http://www.nxp.com/mbed

For all other partner-developed software and tools, visit http://www.nxp.com/partners.

7 Part identification

7.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the

values of these fields to determine the specific part you have received.

7.2 Format

Part numbers for this device have the following format:

Q KE## A FFF R T PP CC N

7.3 Fields

This table lists the possible values for each field in the part number (not all

combinations are valid):

Table 63. Part number fields description

Field

Description

Values

Q

Qualification status

• M = Fully qualified, general market flow

• P = Prequalification

KE##

A

Kinetis family

Key attribute

• KE15, KE14

• Z = Cortex-M0+

Table continues on the next page...

88

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

NXP Semiconductors

Revision history

Table 63. Part number fields description (continued)

Field

Description

Program flash memory size

Values

FFF

R

• 128 = 128 KB

• 256 = 256 KB

Silicon revision

• (Blank) = Main

• A = Revision after main

T

Temperature range (°C)

Package identifier

• V = –40 to 105

PP

• LH = 64 LQFP (10 mm x 10 mm)

• LL = 100 LQFP (14 mm x 14 mm)

CC

N

Maximum CPU frequency (MHz)

Packaging type

• 7 = 72 MHz

• R = Tape and reel

• (Blank) = Trays

7.4 Example

This is an example part number:

MKE15Z256VLL7

8 Revision history

The following table provides a revision history for this document.

Table 64. Revision history

Rev. No.

Date

Substantial Changes

2

09/2016

Initial public release.

(public

release)

2.1

10/2016

• Updated the max value of "Frequency of operation", in the "LPSPI slave mode

timing" table.

• Minor correction: V_DDEsymbol should be V_DD, in the "DC electrical specifications"

table.

(internal

version)

• Minor update in the "Clocking block diagram" figure.

• Minor update in the "Analog design" section.

2.2

06/2017

08/2017

• Updated the "Voltage and current operating ratings" section.

• Minor update in the "Pinout decoupling" figure.

• Fixed the "Description" collumn of STOP and VLPS mode rows, in the "Power

consumption operating behaviors" table.

(internal

version)

2.3

• Minor update in the "Clock interfaces" section of the feature list, on the front matter

cover pages.

(internal

version)

Table continues on the next page...

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

89

NXP Semiconductors

Revision history

Rev. No.

Table 64. Revision history (continued)

Date

Substantial Changes

• Some updates in the "External Oscillator electrical specifications (OSC32)" and

"External Oscillator electrical specifications (OSC)" tables.

• Some updates in the "External Oscillator frequency specifications (OSC32)" and

"External Oscillator frequency specifications (OSC)" tables.

3

07/2018

• Updated the figure "Memory map".

• Minor updates in the figures "Oscillator connections scheme (OSC32)" and

"Oscillator connections scheme (OSC)".

• Some updates of V_IHand V_ILin the "External Oscillator electrical specifications

(OSC32)" and "External Oscillator electrical specifications (OSC)" tables, and minor

editorial fix.

(public

release)

• Updated the table "Fast internal RC Oscillator electrical specifications": FIRC is

trimmed to 48 MHz only, in this device.

• Updated the figure "ADC input impedance equivalency diagram".

• Corrected the unit as uA, in the I_{DDA_ADC}row of the table "12-bit ADC

characteristics".

• Footnote updated in the tables "LPSPI master mode timing" and "LPSPI slave mode

timing".

• Corrected the minimum and the maximum values of V_LVRXin the "V_DDsupply LVR,

LVD and POR operating requirements" table.

• Updated the "Voltage and current operating requirements" table.

4

06/2019

• Corrected the "Clock interfaces" section in the cover page: FIRC is trimmed to 48

MHz only in this device. Up to 50 MHz DC external square wave input clock.

• Minor fix in Figure 4.

(public

release)

• Note added after Table 5.

• Statement restored in the section RTC : The time counter within the RTC is clocked

by a 32.768 kHz clock sourced from an external crystal using the oscillator, or clock

directly from RTC_CLKIN pin.

• Minor fix in Table 23.

• Some major updates in Table 54.

• Some minor updates in tables "LPSPI master mode timing" and "LPSPI slave mode

timing", including the footnotes, in the section LPSPI electrical specifications.

4.1

07/2020

03/2021

• Minor correction in the FTM channel numbers of the "Module Signal Description

Tables" section.

• Minor correction in the "Functional block diagram" figure after the cover page: GPIO

and TSI blocks.

(internal

version)

• Minor correction in the "Ordering information" table: ADC channels collumn.

4.2

• Added errata for Mask 2N36S, in the "Related Resources" table of cover page.

(public

release)

90

Kinetis KE1xZ with up to 256 KB Flash, Rev. 4.2, 03/2021

NXP Semiconductors

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Date of release: 03/ 2021

Document identifier: KE1xZP100M72SF0


型号：	MKE14Z128VLL7
厂家：	NXP
描述：	Kinetis KE1xZ with up to 256 KB Flash Up to 72 MHz ARMÂ® CortexÂ®-M0 Based Microcontroller 微控制器
文件：	总92页 (文件大小：1385K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MKE14Z128VLL7 [NXP]

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