MKE1XZ64VLD4 [NXP]
Kinetis KE1xZ with up to 64 KB Flash;
| 型号： | MKE1XZ64VLD4 |
| 厂家： | 
NXP |
| 描述： | Kinetis KE1xZ with up to 64 KB Flash |
| 文件： | 总82页 (文件大小：1593K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NXP Semiconductors
Data Sheet: Technical Data
KE1xZP48M48SF0
Rev. 3, 06/2020
Kinetis KE1xZ with up to 64 KB
MKE1xZ64VLF4
MKE1xZ64VLD4
MKE1xZ64VFP4
MKE1xZ32VLF4
MKE1xZ32VLD4
MKE1xZ32VFP4
Flash
Up to 48 MHz Arm® Cortex®-M0+ Based Microcontroller
Providing up to 64 KB flash, up to 8 KB RAM, and a complete set
of analog/digital features, KE1xZ64 offers a robust Touch Sense
Interface (TSI) and CAN bus for industrial networking, which
provides high-level stability and accuracy in customer's home
appliance touch UI and industrial control systems.
48 LQFP (LF)
7x7x1.4 mm P 0.5
44 LQFP (LD)
10x10x1.4 mm P 0.8
40 QFN (FP)
5x5x0.85 mm P 0.4
Core Processor and System
• Arm® Cortex®-M0+ core, supports up to 48 MHz
frequency
Memory and memory interfaces
• Up to 64 KB program flash
• Up to 8 KB SRAM
• Arm Core based on the ARMv6 Architecture and
• 64 Bytes flash cache
Thumb®-2 ISA
Mixed-signal analog
• Configurable Nested Vectored Interrupt Controller
(NVIC)
• Memory-Mapped Divide and Square Root module
(MMDVSQ)
• 1× 12-bit analog-to-digital converter (ADC) with up
to 16 channel analog inputs per module, up to 1
Msps
• 1× high-speed analog comparators (CMP) with
internal 8-bit digital to analog converter (DAC)
Reliability, safety and security
• Cyclic Redundancy Check (CRC) generator module
• 128-bit unique identification (ID) number
• Internal watchdog (WDOG) with independent clock
source
• External watchdog monitor (EWM) module
• ADC self calibration feature
Timing and control
• 2× Flex Timers (FTM) for PWM generation, offering
6ch+2ch
• 1× 16-bit Low-Power Timer (LPTMR) with flexible
wake up control
• 1× Programmable Delay Block (PDB) with flexible
trigger system
• On-chip clock loss monitoring
Power management
• 1× 32-bit Low-power Periodic Interrupt Timer (LPIT)
with 2 independent channels
• Real timer clock (RTC)
• Low-power Arm Cortex-M0+ core with excellent energy
efficiency
• Power management controller (PMC) with multiple
power modes: Run, Wait, Stop, VLPR, VLPW and
VLPS
Debug functionality
• Serial Wire Debug (SWD) debug interface
• Debug Watchpoint and Trace (DWT)
• Micro Trace Buffer (MTB)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• Supports clock gating for unused modules, and specific
peripherals remain working in low power modes
• POR, LVD/LVR
Connectivity and communications interfaces
• 3× low-power universal asynchronous receiver/
transmitter (LPUART) modules with FIFO support
and low power availability
Clock interfaces
• OSC: high range 4 - 40 MHz (with low power or high-
gain mode) and low range 32 - 40 kHz (with high-gain
mode only)
• 48 MHz high-accuracy (up to 1ꢀ) fast internal
reference clock (FIRC) for normal Run
• 8 MHz / 2 MHz high-accuracy (up to 3ꢀ) slow internal
reference clock (SIRC) for low-speed Run
• 128 kHz low power oscillator (LPO)
• Low-power FLL (LPFLL)
• 1× low-power serial peripheral interface (LPSPI)
modules with FIFO support and low power
availability
• 1× low-power inter-integrated circuit (LPI2C)
modules with FIFO support and low power
availability
• 1× CAN module (MSCAN), with 5 Rx buffers and 3
Tx buffers
• Up to 50 MHz DC external square wave input clock
• System clock generator (SCG)
• Real time counter (RTC)
Operating Characteristics
• Voltage range: 2.7 to 5.5 V
• Ambient temperature range: –40 to 105 °C
Human-machine interface (HMI)
• Supports up to 32 interrupt request (IRQ) sources
• Up to 42 GPIO pins with interrupt functionality
• Touch sensing input (TSI) module
Related Resources
Type
Description
Resource
Fact Sheet
The Fact Sheet gives overview of the product key features and its uses. KE1xZ Family Fact Sheet
Product Brief The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
KE1xZ64PB1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
KE1xZP48M48SF0RM 1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
This document:
KE1xZP48M48SF0
Chip Errata
The chip mask set Errata provides additional or corrective information for Kinetis_E_0N16X 1
a particular device mask set.
Package
drawing
Package dimensions are provided in package drawings.
48-LQFP: 98ASH00962A
44-LQFP: 98ASS23225W
40-QFN: 98ASA01371D
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
2
Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020
NXP Semiconductors
Kinetis KE1xZ64 Sub-Family
Arm® Cortex® -M0+
System
Memories and Memory Interfaces
Clocks
OSC
Core
Program
flash
RAM
TRGMUX
WDOG
EWM
FIRC
SIRC
LPFLL
Debug
interfaces
MMDVSQ
Interrupt
controller
LPO
Security
Communication Interfaces
Human-Machine
Interface (HMI)
Analog
Timers
and Integrity
LPI 2C
x1
FlexTimer
6ch x1
2ch x1
12-bit ADC
GPIO
CRC
upto 42
x1
LPUART
x3
CMP x1
(with 8-bit DAC)
High drive
I/O (6 pins)
PDB x1
LPSPI
x1
Digital filters
(port E)
PMC
LPIT, 2ch
LPTMR
SRTC
PWT
TSI, 25ch
msCAN x1
Figure 1. Functional block diagram
Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020
3
NXP Semiconductors
Table of Contents
1 Ordering information............................................................... 5
5.1.3
5.1.4
Typical-value conditions....................................32
2 Overview................................................................................. 5
2.1 System features...............................................................6
Relationship between ratings and operating
requirements..................................................... 32
Guidelines for ratings and operating
2.1.1
2.1.2
2.1.3
2.1.4
2.1.5
2.1.6
2.1.7
2.1.8
2.1.9
ARM Cortex-M0+ core...................................... 6
NVIC..................................................................7
AWIC.................................................................7
Memory............................................................. 8
Reset and boot..................................................8
Clock options.....................................................9
Security............................................................. 10
Power management..........................................10
Debug controller................................................12
5.1.5
requirements..................................................... 33
5.2 Ratings............................................................................ 33
5.2.1
5.2.2
5.2.3
5.2.4
Thermal handling ratings...................................33
Moisture handling ratings..................................34
ESD handling ratings........................................ 34
Voltage and current operating ratings...............34
5.3 General............................................................................35
5.3.1
5.3.2
5.3.3
Nonswitching electrical specifications...............35
Switching specifications.................................... 48
Thermal specifications...................................... 51
2.2 Peripheral features.......................................................... 12
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.2.6
2.2.7
2.2.8
2.2.9
FTM...................................................................12
ADC...................................................................13
CMP.................................................................. 14
RTC...................................................................14
LPIT...................................................................15
PDB...................................................................15
LPTMR..............................................................15
CRC.................................................................. 16
LPUART............................................................16
5.4 Peripheral operating requirements and behaviors...........54
5.4.1
5.4.2
5.4.3
5.4.4
5.4.5
5.4.6
5.4.7
5.4.8
System modules................................................54
Clock interface modules....................................55
Memories and memory interfaces.....................60
Security and integrity modules..........................61
Analog...............................................................61
Communication interfaces.................................68
Human-machine interfaces (HMI)..................... 72
Debug modules.................................................73
2.2.10 LPSPI................................................................17
2.2.11 LPI2C................................................................ 17
2.2.12 Modular/Scalable Controller Area Network
6 Design considerations.............................................................74
6.1 Hardware design considerations..................................... 74
(MSCAN)...........................................................18
6.1.1
6.1.2
6.1.3
6.1.4
6.1.5
Printed circuit board recommendations.............74
Power delivery system...................................... 75
Analog design................................................... 75
Digital design.....................................................76
Crystal oscillator................................................78
2.2.13 Port control and GPIO.......................................18
3 Memory map........................................................................... 20
4 Pinouts.................................................................................... 20
4.1 KE1xZ64 Signal Multiplexing and Pin Assignments........ 20
4.2 Port control and interrupt summary................................. 22
4.3 Module Signal Description Tables................................... 23
4.4 Pinout diagram................................................................ 27
4.5 Package dimensions....................................................... 30
5 Electrical characteristics..........................................................31
5.1 Terminology and guidelines.............................................31
6.2 Software considerations.................................................. 80
7 Part identification.....................................................................80
7.1 Description.......................................................................80
7.2 Format............................................................................. 80
7.3 Fields............................................................................... 81
7.4 Example...........................................................................81
8 Revision history.......................................................................81
5.1.1
5.1.2
Definitions......................................................... 31
Examples.......................................................... 31
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Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020
NXP Semiconductors
Ordering information
1 Ordering information
The following chips are available for ordering.
Table 1. Ordering information
Product
Memory
Package
IO and ADC channel
HMI
TSI
Commu
nication
Part number
Flash
SRAM
(KB)
Pin
Packag
e
GPIOs
GPIOs
(INT/
ADC
channel
s
CAN
(KB)
count
HD)1
MKE16Z64VLF4
MKE16Z64VLD4
MKE15Z64VLF4
MKE15Z64VLD4
MKE14Z64VLF4
MKE14Z64VLD4
MKE16Z32VLF4
MKE16Z32VLD4
MKE15Z32VLF4
MKE15Z32VLD4
MKE14Z32VLF4
MKE14Z32VLD4
MKE15Z64VFP4
MKE14Z64VFP4
MKE15Z32VFP4
MKE14Z32VFP4
64
64
64
64
64
64
32
32
32
32
32
32
64
64
32
32
8
8
8
8
8
8
4
4
4
4
4
4
8
8
4
4
48
44
48
44
48
44
48
44
48
44
48
44
40
40
40
40
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
LQFP
QFN
42
38
42
38
42
38
42
38
42
38
42
38
36
36
36
36
42/6
38/6
42/6
38/6
42/6
38/6
42/6
38/6
42/6
38/6
42/6
38/6
36/4
36/4
36/4
36/4
12
12
12
12
12
12
12
12
12
12
12
12
11
11
11
11
Yes
Yes
Yes
Yes
No
Yes
Yes
No
No
No
No
Yes
Yes
No
No
No
No
No
No
No
No
No
Yes
Yes
Yes
Yes
No
No
Yes
No
QFN
QFN
Yes
No
QFN
1. INT: interrupt pin numbers; HD: high drive pin numbers
2 Overview
The following figure shows the system diagram of this device.
Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020
5
NXP Semiconductors
Overview
Slave
Master
M0
Cortex M0+
IOPORT
unified bus
for core
Flash
upto 64 KB
FMC
Debug
(SWD)
CM0+ core
S0
S1
NVIC
SRAM
upto 8 KB
various
peripheral
blocks
S2
MUX
System Clock Generator (SCG)
Fast IRC
Slow IRC
SOSC
LPFLL
Clock
Source
LPO
Figure 2. System diagram
The crossbar switch connects bus masters and slaves using a crossbar switch structure.
This structure allows up to four bus masters to access different bus slaves
simultaneously, while providing arbitration among the bus masters when they access
the same slave.
2.1 System features
The following sections describe the high-level system features.
6
Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020
NXP Semiconductors
Overview
2.1.1 ARM Cortex-M0+ core
The enhanced ARM Cortex M0+ is the member of the Cortex-M Series of processors
targeting microcontroller cores focused on very cost sensitive, low power
applications. It has a single 32-bit AMBA AHB-Lite interface and includes an NVIC
component. It also has hardware debug functionality including support for simple
program trace capability. The processor supports the ARMv6-M instruction set
(Thumb) architecture including all but three 16-bit Thumb opcodes (52 total) plus
seven 32-bit instructions. It is upward compatible with other Cortex-M profile
processors.
2.1.2 NVIC
The Nested Vectored Interrupt Controller supports nested interrupts and 4 priority
levels for interrupts. In the NVIC, each source in the IPR registers contains 2 bits. It
also differs in number of interrupt sources and supports 32 interrupt vectors.
The Cortex-M family uses a number of methods to improve interrupt latency to up to
15 clock cycles for Cortex-M0+. It also can be used to wake the MCU core from Wait
and VLPW modes.
2.1.3 AWIC
The asynchronous wake-up interrupt controller (AWIC) is used to detect
asynchronous wake-up events in Stop mode and signal to clock control logic to
resume system clocking. After clock restarts, the NVIC observes the pending interrupt
and performs the normal interrupt or event processing. The AWIC can be used to
wake MCU core from Partial Stop, Stop and VLPS modes.
Wake-up sources for this SoC are listed as below:
Table 2. AWIC Stop and VLPS Wake-up Sources
Wake-up source
Available system resets
Pin interrupts
ADCx
Description
RESET pin, WDOG , loss of clock(LOC) reset and loss of lock (LOL) reset
Port Control Module - Any enabled pin interrupt is capable of waking the system
ADCx is optional functional with clock source from SIRC or OSC
Functional in Stop/VLPS modes with clock source from SIRC or OSC
Functional in Stop/VLPS modes with clock source from SIRC or OSC
Functional in Stop/VLPS modes with clock source from SIRC or OSC
CMPx
LPI2C
LPUART
Table continues on the next page...
Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020
7
NXP Semiconductors
Overview
Table 2. AWIC Stop and VLPS Wake-up Sources (continued)
Wake-up source
LPSPI
LPIT
Description
Functional in Stop/VLPS modes with clock source from SIRC or OSC
Functional in Stop/VLPS modes with clock source from SIRC or OSC
Functional in Stop/VLPS modes
LPTMR
RTC
Functional in Stop/VLPS modes
SCG
Functional in Stop mode (Only SIRC)
CAN stop wakeup
CAN
TSI
Touch sense wakeup
NMI
Non-maskable interrupt
2.1.4 Memory
This device has the following features:
• Upto 64 KB of embedded program flash memory.
• Upto 8 KB of embedded RAM accessible (read/write) at CPU clock speed with 0
wait states.
• The program flash memory contains a 16-byte flash configuration field that stores
default protection settings and security information. The page size of program flash
is 1 KB.
The protection setting can protect 32 regions of the program flash memory from
unintended erase or program operations.
The security circuitry prevents unauthorized access to RAM or flash contents from
debug port.
2.1.5 Reset and boot
The following table lists all the reset sources supported by this device.
NOTE
In the following table, Y means the specific module, except
for the registers, bits or conditions mentioned in the footnote,
is reset by the corresponding Reset source. N means the
specific module is not reset by the corresponding Reset
source.
8
Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020
NXP Semiconductors
Overview
Table 3. Reset source
Reset
Descriptions
Modules
sources
PMC SIM SMC RCM
Reset WDO SCG RTC LPTM Other
pin is
G
R
s
negated
POR reset
Power-on reset (POR)
Y
Y1
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
N
Y
Y
Y
Y
System
resets
Low-voltage detect
(LVD)
External pin reset
(RESET)
Y1
Y1
Y1
Y2
Y2
Y2
Y3
Y3
Y3
Y4
Y4
Y4
Y
Y
Y
Y5
Y5
Y5
Y6
Y6
Y6
N
N
N
N
N
N
Y
Y
Y
Watchdog (WDOG)
reset
Multipurpose clock
generator loss of clock
(LOC) reset
Multipurpose clock
generator loss of lock
(LOL) reset
Stop mode acknowledge Y1
error (SACKERR)
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y
Y
Y5
Y5
Y6
Y6
N
N
N
N
Y
Y
Software reset (SW)
Y1
Y1
Y1
Y1
Y2
Y2
Y2
Y2
Y3
Y3
Y3
Y3
Y4
Y4
Y4
Y4
Y
Y
Y
Y
Y5
Y5
Y5
Y5
Y6
Y6
Y6
Y6
N
N
N
N
N
N
N
N
Y
Y
Y
Y
Lockup reset (LOCKUP)
MDM DAP system reset
Debug reset Debug reset
1. Except PMC_LVDSC1[LVDV] and PMC_LVDSC2[LVWV]
2. Except SIM_SOPT1
3. Except SMC_PMPROT, SMC_PMCTRL_RUM, SMC_PMCTRL_STOPM, SMC_STOPCTRL, SMC_PMSTAT
4. Except RCM_RPC, RCM_MR, RCM_FM, RCM_SRIE, RCM_SRS, RCM_SSRS
5. Except WDOG_CS[TST]
6. Except SCG_CSR and SCG_FIRCSTAT
This device supports booting from:
• internal flash
2.1.6 Clock options
The SCG module controls which clock source is used to derive the system clocks. The
clock generation logic divides the selected clock source into a variety of clock
domains, including the clocks for the system bus masters, system bus slaves, and flash
memory . The clock generation logic also implements module-specific clock gating to
allow granular shutoff of modules.
Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020
9
NXP Semiconductors
Overview
The following figure is a high level block diagram of the clock generation. For more
details on the clock operation and configuration, see the Clocking chapter in the
Reference Manual.
00
01
10
PWT
11
TCLK0
00
01
SIM_CHIPCTL[PWTCLKSEL]
TCLK1
TCLK2
10
11
FTMx
SIM_FTMOPT0[FTMxCLKSEL]
SCG
SCG_LPFLLTCFG[TRIMSRC]
Core
RAM
GPIOC
48MHz
Fast
IRC
01
00
0101
LPFLL
TRIMDIV
(SCG_LFLLTCFG)
10
11
0011
0010
default start up
DIVCORE
CORE_CLK/SYS_CLK
PDB
8MHz/2MHz
Slow
IRC
PCC
0001
Other
SYS_CLK
PCC_xxx[CGC]
BUS_CLK/FLASH_CLK
CRC
ACMPx
TSI
SCG_xCCR[SCS]
(x=R, V, H)
DIVSLOW
BUSOUT
FLL_CLK
FLLDIV2_CLK
FLLDIV2
Flash
Peripheral
Registers
SIRC_CLK
FIRC_CLK
SIRCDIV2_CLK
FIRCDIV2_CLK
ADCx
SIRCDIV2
LPIT
LPI2Cx
LPUARTx
LPSPIx
Async clock
FIRCDIV2
SCG_SOSCCFG[EREFS]
0
SOSCDIV2_CLK
SOSC_CLK
SOSCDIV2
EXTAL
System
OSC
1
PCC_xxx[PCS]
Other 0000 0001 0011 0010 0101
SCG_CLKOUTCNFG
[CLKOUTSEL]
XTAL
SCG_SOSCCSR
[SOSCERCLKEN]
OSC
SCG CLKOUT
00
WDOG
01
10
CLKOUTDIV
CLKOUT
11
SIM_CHIPCTL[CLKOUTSEL]
LPO_CLK
RTC_CLKIN
LPTMR
EWM
RTC
1kHz
LPO128K
1
÷128
PMC
00
01
10
11
32kHz
RTC_CLKIN
0
RTC_CLKOUT
÷4
PORT Control
RTC_CR[LPOS]
SIM_CHIPCTL[RTC32KCLKSEL]
MSCAN
Figure 3. Clocking block diagram
2.1.7 Security
Security state can be enabled via programming flash configure field (0x40e). After
enabling device security, the SWD port cannot access the memory resources of the
MCU.
External interface
Security
Unsecure
SWD port
Can't access memory source by SWD
interface
the debugger can write to the Flash
Mass Erase in Progress field of the
MDM-AP Control register to trigger a
mass erase (Erase All Blocks)
command
10
Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020
NXP Semiconductors
Overview
2.1.8 Power management
The Power Management Controller (PMC) expands upon ARM’s operational modes
of Run, Sleep, and Deep Sleep, to provide multiple configurable modes. These modes
can be used to optimize current consumption for a wide range of applications. The
WFI or WFE instruction invokes a Wait or a Stop mode, depending on the current
configuration. For more information on ARM’s operational modes, See the ARM®
Cortex® User Guide.
The PMC provides Normal Run (RUN), and Very Low Power Run (VLPR)
configurations in ARM’s Run operation mode. In these modes, the MCU core is
active and can access all peripherals. The difference between the modes is the
maximum clock frequency of the system and therefore the power consumption. The
configuration that matches the power versus performance requirements of the
application can be selected.
The PMC provides Wait (Wait) and Very Low Power Wait (VLPW) configurations in
ARM’s Sleep operation mode. In these modes, even though the MCU core is inactive,
all of the peripherals can be enabled and operate as programmed. The difference
between the modes is the maximum clock frequency of the system and therefore the
power consumption.
The PMC provides Stop (Stop), Very Low Power Stop (VLPS) configurations in
ARM’s Deep Sleep operational mode. In these modes, the MCU core and most of the
peripherals are disabled. Depending on the requirements of the application, different
portions of the analog, logic, and memory can be retained or disabled to conserve
power.
The Nested Vectored Interrupt Controller (NVIC), the Asynchronous Wake-up
Interrupt Controller (AWIC) are used to wake up the MCU from low power states.
The NVIC is used to wake up the MCU core from WAIT and VLPW modes. The
AWIC is used to wake up the MCU core from STOP and VLPS modes.
For additional information regarding operational modes, power management, the
NVIC, AWIC, please refer to the Reference Manual.
The following table provides information about the state of the peripherals in the
various operational modes and the modules that can wake MCU from low power
modes.
Table 5. Peripherals states in different operational modes
Core mode
Device mode
Descriptions
Run mode
Table continues on the next page...
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11
NXP Semiconductors
Overview
Table 5. Peripherals states in different operational modes (continued)
Core mode
Device mode
Descriptions
Run
In Run mode, all device modules are operational.
Very Low Power Run
In VLPR mode, all device modules are operational at a reduced frequency
except the Low Voltage Detect (LVD) monitor, which is disabled.
Sleep mode
Deep sleep
Wait
In Wait mode, all peripheral modules are operational. The MCU core is
placed into Sleep mode.
Very Low Power Wait
In VLPW mode, all peripheral modules are operational at a reduced
frequency except the Low Voltage Detect (LVD) monitor, which is disabled.
The MCU core is placed into Sleep mode.
Stop
In Stop mode, most peripheral clocks are disabled and placed in a static
state. Stop mode retains all registers and SRAMs while maintaining Low
Voltage Detection protection. In Stop mode, the ADC, CMP, LPTMR, RTC,
and pin interrupts are operational. The NVIC is disabled, but the AWIC can
be used to wake up from an interrupt.
Very Low Power Stop
In VLPS mode, the contents of the SRAM are retained. The CMP (low
speed), ADC, OSC, RTC, LPTMR, LPIT, FlexIO, LPUART, LPI2C,LPSPI,
and DMA are operational, LVD and NVIC are disabled, AWIC is used to
wake up from interrupt.
NOTE
When the MCU is in HSRUN or VLP mode, user cannot write
FlexRAM (EEPROM), and cannot launch an FTFE command
including flash programming/erasing.
2.1.9 Debug controller
This device has extensive debug capabilities including run control and tracing
capabilities. The standard ARM debug port supports SWD interface.
2.2 Peripheral features
The following sections describe the features of each peripherals of the chip.
2.2.1 FTM
This device contains two FlexTimer modules.
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NXP Semiconductors
Overview
The FlexTimer module (FTM) is a two-to-eight channel timer that supports input
capture, output compare, and the generation of PWM signals to control electric motor
and power management applications. The FTM time reference is a 16-bit counter that
can be used as an unsigned or signed counter.
Several key enhancements of this module are made:
• Signed up counter
• Deadtime insertion hardware
• Fault control inputs
• Enhanced triggering functionality
• Initialization and polarity control
2.2.2 ADC
This device contains one 12-bit SAR ADC modules. The ADC module supports
hardware triggers from FTM, LPTMR, PIT, RTC, external trigger pin and CMP
output. It supports wakeup of MCU in low power mode when using internal clock
source or external crystal clock.
ADC module has the following features:
• Linear successive approximation algorithm with up to 12-bit resolution
• Up to 12 single-ended external analog inputs
• Support 12-bit, 10-bit, and 8-bit single-ended output modes
• Single or continuous conversion
• Configurable sample time and conversion speed/power
• Input clock selectable from up to four sources
• Operation in low-power modes for lower noise
• Selectable hardware conversion trigger
• Automatic compare with interrupt for less-than, greater-than or equal-to, within
range, or out-of-range, programmable value
• Temperature sensor
• Hardware average function
• Selectable Voltage reference: from external or alternate
• Self-Calibration mode
2.2.2.1 Temperature sensor
This device contains one temperature sensor internally connected to the input channel
of AD26, see ADC electrical characteristics for details of the linearity factor.
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NXP Semiconductors
Overview
The sensor must be calibrated to gain good accuracy, so as to provide good linearity,
see also AN3031 for more detailed application information of the temperature sensor.
2.2.3 CMP
There are one analog comparators on this device.
• Each CMP has its own independent 8-bit DAC.
• Each CMP supports up to 6 analog inputs from external pins.
• Each CMP is able to convert an internal reference from the bandgap.
• Each CMP supports the round-robin sampling scheme. In summary, this allow the
CMP to operate independently in VLPS and Stop modes, whilst being triggered
periodically to sample up to 8 inputs. Only if an input changes state is a full wakeup
generated.
The CMP has the following features:
• Inputs may range from rail to rail
• Programmable hysteresis control
• Selectable interrupt on rising-edge, falling-edge, or both rising and falling edges of
the comparator output
• Selectable inversion on comparator output
• Capability to produce a wide range of outputs such as sampled, windowed, or
digitally filtered
• External hysteresis can be used at the same time that the output filter is used for
internal functions
• Two software selectable performance levels: Shorter propagation delay at the
expense of higher power, and Low power with longer propagation delay
• Functional in all power modes available on this MCU
• The window and filter functions are not available in STOP mode
• Integrated 8-bit DAC with selectable supply reference source and can be power
down to conserve power
2.2.4 RTC
The RTC is an always powered-on block that remains active in all low power modes.
RTC is reset on power-on reset, and a software reset bit in RTC can also initialize all
RTC registers.
The RTC module has the following features
• 32-bit seconds counter with roll-over protection and 32-bit alarm
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Overview
• 16-bit prescaler with compensation that can correct errors between 0.12 ppm and
3906 ppm
• Register write protection with register lock mechanism
• 1 Hz square wave or second pulse output with optional interrupt
2.2.5 LPIT
The Low Power Periodic Interrupt Timer (LPIT) is a multi-channel timer module
generating independent pre-trigger and trigger outputs. These timer channels can
operate individually or can be chained together. The LPIT can operate in low power
modes if configured to do so. The pre-trigger and trigger outputs can be used to
trigger other modules on the device.
2.2.6 PDB
The Programmable Delay Block (PDB) provides controllable delays from either an
internal or an external trigger, or a programmable interval tick, to the hardware trigger
inputs of ADCs and/or generates the interval triggers to DACs, so that the precise
timing between ADC conversions and/or DAC updates can be achieved. The PDB can
optionally provide pulse outputs (Pulse-Out's) that are used as the sample window in
the CMP block.
The PDB module has the following capabilities:
• trigger input sources and one software trigger source
• 1 DAC refresh trigger output, for this device
• configurable PDB channels for ADC hardware trigger
• 1 pulse output, for this device
2.2.7 LPTMR
The low-power timer (LPTMR) can be configured to operate as a time counter with
optional prescaler, or as a pulse counter with optional glitch filter, across all power
modes, including the low-leakage modes. It can also continue operating through most
system reset events, allowing it to be used as a time of day counter.
The LPTMR module has the following features:
• 16-bit time counter or pulse counter with compare
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NXP Semiconductors
Overview
• Optional interrupt can generate asynchronous wakeup from any low-power
mode
• Hardware trigger output
• Counter supports free-running mode or reset on compare
• Configurable clock source for prescaler/glitch filter
• Configurable input source for pulse counter
2.2.8 CRC
This device contains one cyclic redundancy check (CRC) module which can generate
16/32-bit CRC code for error detection.
The CRC module provides a programmable polynomial, WAS, and other parameters
required to implement a 16-bit or 32-bit CRC standard.
The CRC module has the following features:
• Hardware CRC generator circuit using a 16-bit or 32-bit programmable shift
register
• Programmable initial seed value and polynomial
• Option to transpose input data or output data (the CRC result) bitwise or bytewise.
• Option for inversion of final CRC result
• 32-bit CPU register programming interface
2.2.9 LPUART
This product contains three Low-Power UART modules, and can work in Stop and
VLPS modes. The module also supports 4× to 32× data oversampling rate to meet
different applications.
The LPUART module has the following features:
• Programmable baud rates (13-bit modulo divider) with configurable oversampling
ratio from 4× to 32×
• Transmit and receive baud rate can operate asynchronous to the bus clock and can
be configured independently of the bus clock frequency, support operation in Stop
mode
• Interrupt, or polled operation
• Hardware parity generation and checking
• Programmable 8-bit, 9-bit or 10-bit character length
• Programmable 1-bit or 2-bit stop bits
• Three receiver wakeup methods
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Overview
• Idle line wakeup
• Address mark wakeup
• Receive data match
• Automatic address matching to reduce ISR overhead:
• Address mark matching
• Idle line address matching
• Address match start, address match end
• Optional 13-bit break character generation / 11-bit break character detection
• Configurable idle length detection supporting 1, 2, 4, 8, 16, 32, 64 or 128 idle
characters
• Selectable transmitter output and receiver input polarity
2.2.10 LPSPI
This device contains one LPSPI modules. The LPSPI is a low power Serial Peripheral
Interface (SPI) module that supports an efficient interface to an SPI bus as a master
and/or a slave. The LPSPI can continue operating in stop modes provided an
appropriate clock is available and is designed for low CPU overhead with DMA
offloading of FIFO register accesses.
The LPSPI modules have the following features:
• Command/transmit FIFO of 4 words
• Receive FIFO of 4 words
• Host request input can be used to control the start time of an SPI bus transfer
2.2.11 LPI2C
This device contains one LPI2C modules. The LPI2C is a low power Inter-Integrated
Circuit (I2C) module that supports an efficient interface to an I2C bus as a master
and/or a slave. The LPI2C can continue operating in stop modes provided an
appropriate clock is available and is designed for low CPU overhead with DMA
offloading of FIFO register accesses. The LPI2C implements logic support for
standard-mode, fast-mode, fast-mode plus and ultra-fast modes of operation. The
LPI2C module also complies with the System Management Bus (SMBus)
Specification, version 2.
The LPI2C modules have the following features:
• Standard, Fast, Fast+ and Ultra Fast modes are supported
• HS-mode supported in slave mode
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Overview
• Multi-master support including synchronization and arbitration
• Clock stretching
• General call, 7-bit and 10-bit addressing
• Software reset, START byte and Device ID require software support
• For master mode:
• command/transmit FIFO of 4 words
• receive FIFO of 4 words
• For slave mode:
• separate I2C slave registers to minimize software overhead due to master/slave
switching
• support for 7-bit or 10-bit addressing, address range, SMBus alert and general
call address
• transmit/receive data register supporting interrupt requests
2.2.12 Modular/Scalable Controller Area Network (MSCAN)
This device contains one CAN module. It uses the MSCAN mudule which is a
communication controller implementing the CAN 2.0A/B protocol as defined in the
Bosch specification dated September 1991.
Its 5 Rx buffers and 3 Tx buffers are adaptable to target CAN applications.
The MSCAN module has the following features :
• Implementation of the CAN protocol Version 2.0 A/B
• Standard and extended data frames
• 0-to-8 bytes data length
• Programmable bit rate up to 1 Mbit/s
• Support for remote frames
• Individual Rx Mask Registers per Message Buffer
• Internal timer for time-stamping of received and transmitted messages
• Listen-only mode capability
• Programmable loopback mode supporting self-test operation
• Programmable transmission priority scheme: lowest ID, lowest buffer number, or
highest priority
• Low power modes, with programmable wakeup on bus activity
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Overview
2.2.13 Port control and GPIO
The Port Control and Interrupt (PORT) module provides support for port control,
digital filtering, and external interrupt functions. The GPIO data direction and output
data registers control the direction and output data of each pin when the pin is
configured for the GPIO function. The GPIO input data register displays the logic
value on each pin when the pin is configured for any digital function, provided the
corresponding Port Control and Interrupt module for that pin is enabled.
The following figure shows the basic I/O pad structure. Pseudo open-drain pins have
the p-channel output driver disabled when configured for open-drain operation. None
of the I/O pins, including open-drain and pseudo open-drain pins, are allowed to go
above VDD.
Digital input
IBE=1 whenever
IFE
MUX≠000
IBE
ESD
Bus
VDD
RPULL
PE
PS
Analog input
DSE
Digital output
Figure 4. I/O simplified block diagram
The PORT module has the following features:
• all PIN support interrupt enable
• Configurable edge (rising, falling, or both) or level sensitive interrupt type
• Support DMA request
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Memory map
• Asynchronous wake-up in low-power modes
• Configurable pullup, pulldown, and pull-disable on select pins
• Configurable high and low drive strength on selected pins
• Configurable passive filter on selected pins
• Individual mux control field supporting analog or pin disabled, GPIO, and up to
chip-specific digital functions
• Pad configuration fields are functional in all digital pin muxing modes.
The GPIO module has the following features:
• Port Data Input register visible in all digital pin-multiplexing modes
• Port Data Output register with corresponding set/clear/toggle registers
• Port Data Direction register
• GPIO support single-cycle access via fast GPIO.
3 Memory map
This device contains various memories and memory-mapped peripherals which are
located in a 4 GB memory space. For more details of the system memory and peripheral
locations, see the Memory Map chapter in the Reference Manual.
4 Pinouts
4.1 KE1xZ64 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
48
44
40
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP QFN
—
—
—
—
1
—
—
—
—
1
5
6
PTE5
TSI0_CH0
TSI0_CH1
TSI0_CH16
TSI0_CH15
TSI0_CH5
TSI0_CH0
TSI0_CH1
TSI0_CH16
TSI0_CH15
TSI0_CH5
PTE5
TCLK2
EWM_IN
PTE4
PTC7
PTC6
PTD1
PTE4
PTC7
PTC6
PTD1
BUSOUT
EWM_OUT_b
32
33
1
LPUART1_TX
LPUART1_RX
FTM0_CH3
TRGMUX_
OUT2
2
2
2
PTD0
TSI0_CH4
TSI0_CH4
PTD0
FTM0_CH2
TRGMUX_
OUT1
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Pinouts
48
44
40
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP QFN
3
—
3
PTE11
TSI0_CH3
TSI0_CH3
PTE11
PWT_IN1
LPTMR0_
ALT1
4
5
—
3
4
—
—
7
PTE10
PTE5
PTE4
VDD
TSI0_CH2
TSI0_CH0
TSI0_CH1
VDD
TSI0_CH2
TSI0_CH0
TSI0_CH1
VDD
PTE10
PTE5
PTE4
CLKOUT
TCLK2
CAN0_TX
CAN0_RX
EWM_IN
6
4
BUSOUT
EWM_OUT_b
7
5
8
6
7
VDDA
VREFH
VDDA
VDDA
9
7
7
VREFH
VREFH
10
8
—
VSS/
VSS/
VSS/
VREFL
VREFL
VREFL
11
12
13
9
8
9
PTB7
PTB6
PTE3
EXTAL
EXTAL
PTB7
PTB6
PTE3
LPI2C0_SCL
LPI2C0_SDA
FTM0_FLT0
10
11
XTAL
XTAL
—
TSI0_CH24
TSI0_CH24
LPUART2_
RTS
14
15
16
17
18
—
12
13
14
15
10
11
12
13
14
PTE8
PTB5
PTB4
PTC3
PTC2
ACMP0_IN3/
TSI0_CH11
ACMP0_IN3/
TSI0_CH11
PTE8
PTB5
PTB4
PTC3
PTC2
TSI0_CH9
TSI0_CH9
FTM0_CH5
FTM0_CH4
FTM0_CH3
FTM0_CH2
LPSPI0_
PCS1
TRGMUX_IN0
TRGMUX_IN1
TSI0_CH8
TSI0_CH8
LPSPI0_
SOUT
ADC0_SE11/
ACMP0_IN4
ADC0_SE11/
ACMP0_IN4
ADC0_SE10/
ACMP0_IN5
ADC0_SE10/
ACMP0_IN5
19
20
21
16
17
18
15
16
17
PTD7
PTD6
PTD5
TSI0_CH10
TSI0_CH7
TSI0_CH6
TSI0_CH10
TSI0_CH7
TSI0_CH6
PTD7
PTD6
PTD5
LPUART2_TX
LPUART2_RX
LPTMR0_
ALT2
PWT_IN2
LPUART2_
CTS
22
23
24
25
26
27
28
29
19
20
21
22
23
24
25
26
18
19
20
22
23
24
25
—
PTC1
PTC0
PTB3
PTB2
PTB1
PTB0
PTA7
PTA6
ADC0_SE9/
TSI0_CH23
ADC0_SE9/
TSI0_CH23
PTC1
PTC0
PTB3
PTB2
PTB1
PTB0
PTA7
PTA6
FTM0_CH1
FTM0_CH0
FTM1_CH1
FTM1_CH0
ADC0_SE8/
TSI0_CH22
ADC0_SE8/
TSI0_CH22
ADC0_SE7/
TSI0_CH21
ADC0_SE7/
TSI0_CH21
LPSPI0_SIN
LPSPI0_SCK
FTM1_QD_
PHA
TRGMUX_IN2
TRGMUX_IN3
ADC0_SE6/
TSI0_CH20
ADC0_SE6/
TSI0_CH20
FTM1_QD_
PHB
ADC0_SE5
ADC0_SE4
ADC0_SE3
ADC0_SE2
ADC0_SE5
ADC0_SE4
ADC0_SE3
ADC0_SE2
LPUART0_TX LPSPI0_
SOUT
TCLK0
LPUART0_RX LPSPI0_
PCS0
LPTMR0_
ALT3
PWT_IN3
FTM0_FLT2
LPSPI0_
PCS3
RTC_CLKIN
LPUART1_
RTS
FTM0_FLT1
LPUART1_
CTS
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Pinouts
48
44
40
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP QFN
30
27
21,
40
VSS
VSS
VSS
and
EP
31
32
33
34
35
36
37
28
29
30
31
32
33
34
26
—
27
—
28
29
30
VDD
VDD
VDD
PTD4
PTD3
PTD2
PTA3
PTA2
PTA1
DISABLED
NMI_b
PTD4
FTM0_FLT3
FTM1_CH1
PTD3
PTD2
PTA3
PTA2
PTA1
NMI_b
DISABLED
DISABLED
DISABLED
LPI2C0_SCL
LPI2C0_SDA
EWM_IN
LPUART0_TX
LPUART0_RX
EWM_OUT_b
ADC0_SE1/
ACMP0_IN1/
TSI0_CH18
ADC0_SE1/
ACMP0_IN1/
TSI0_CH18
LPI2C0_
SDAS
FTM1_QD_
PHA
LPUART0_
RTS
TRGMUX_
OUT0
38
35
31
PTA0
ADC0_SE0/
ACMP0_IN0/
TSI0_CH17
ADC0_SE0/
ACMP0_IN0/
TSI0_CH17
PTA0
LPI2C0_
SCLS
LPUART0_
CTS
TRGMUX_
OUT3
39
40
41
36
37
—
—
—
—
PTC7
PTC6
PTE6
TSI0_CH16
TSI0_CH15
DISABLED
TSI0_CH16
TSI0_CH15
PTC7
PTC6
PTE6
LPUART1_TX
LPUART1_RX
CAN0_TX
CAN0_RX
LPSPI0_
PCS2
LPUART1_
RTS
42
43
38
39
—
PTE2
PTE1
TSI0_CH19
TSI0_CH14
TSI0_CH19
TSI0_CH14
PTE2
PTE1
LPSPI0_
SOUT
LPTMR0_
ALT3
PWT_IN3
LPUART1_
CTS
34
LPSPI0_SIN
LPI2C0_
HREQ
44
45
40
41
35
36
PTE0
PTC5
TSI0_CH13
TSI0_CH12
TSI0_CH13
TSI0_CH12
PTE0
PTC5
LPSPI0_SCK
TCLK1
RTC_
CLKOUT
46
42
37
PTC4
SWD_CLK
ACMP0_IN2
PTC4
FTM1_CH0
RTC_
CLKOUT
EWM_IN
FTM1_QD_
PHB
SWD_CLK
47
48
43
44
38
39
PTA5
PTA4
RESET_b
SWD_DIO
PTA5
PTA4
TCLK1
RESET_b
SWD_DIO
ACMP0_OUT
EWM_OUT_b
4.2 Port control and interrupt summary
The following table provides more information regarding the Port Control and Interrupt
configurations.
Table 6. Ports summary
Feature
Port A
Port B
Yes
Port C
Port D
Port E
Yes
Pull select control Yes
Yes
Yes
Pull select at reset PTA4/PTA5=Pull
up, Others=No
No
PTC4=Pull down, PTD3=Pull up,
Others=No Others=No
No
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Pinouts
Table 6. Ports summary (continued)
Feature
Port A
Port B
Yes
Port C
Port D
Port E
Yes
Pull enable control Yes
Yes
Yes
Pull enable at reset PTA4/
Disabled
PTC4=Enabled;
Others=Disabled
PTD3=Enabled;
Others=Disabled
Disabled
PTA5=Enabled;
Others=Disabled
Passive filter
enable control
PTA5=Yes;
Others=No
No
No
PTD3=Yes;
Others=No
No
Passive filter
enable at reset
PTA5=Enabled;
Others=Disabled
Disabled
Disabled
Disabled
Disabled
Open drain enable I2C and UART
I2C and UART
Tx=Enabled;
I2C and UART
Tx=Enabled;
I2C and UART
Tx=Enabled;
I2C and UART
Tx=Enabled;
control
Tx=Enabled;
Others=Disabled
Others=Disabled
Others=Disabled
Others=Disabled
Others=Disabled
Open drain enable Disabled
at reset
Disabled
PTB4/PTB5 only
Disabled
Yes
Disabled
No
Disabled
PTD0/PTD1 only
Disabled
Yes
Disabled
Drive strength
enable control
No
PTE0/PTE1 only
Disabled
Drive strength
enable at reset
Disabled
Disabled
Yes
Pin mux control Yes
Yes
Pin mux at reset PTA4/PTA5=ALT7; ALT0
Others=ALT0
PTC4=ALT7;
Others=ALT0
PTD3=ALT7;
Others=ALT0
ALT0
Lock bit
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Interrupt and DMA Yes
request
Digital glitch filter No
No
No
No
Yes
4.3 Module Signal Description Tables
The following sections correlate the chip-level signal name with the signal name used
in the module's chapter. They also briefly describe the signal function and direction.
4.3.1 Core Modules
Table 7. SWD Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
SWD_CLK
SWD_DIO
SWD_CLK
SWD_DIO
Serial Wire Clock
Serial Wire Data
I
I/O
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4.3.2 System Modules
Table 8. System Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
NMI_b
—
Non-maskable interrupt NOTE: Driving the NMI signal low forces a
non-maskable interrupt, if the NMI function is selected on the
corresponding pin.
I
RESET_b
VDD
—
—
—
Reset bidirectional signal
MCU power
I/O
I
I
VSS
MCU ground
Table 9. EWM Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
EWM_IN
EWM_in
EWM input for safety status of external safety circuits. The polarity
of EWM_IN is programmable using the EWM_CTRL[ASSIN] bit.
The default polarity is active-low.
I
EWM_OUT_b
EWM_out
EWM reset out signal
O
4.3.3 Clock Modules
Table 10. OSC (in SCG) Signal Descriptions
Chip
signal
name
Module signal name
Description
I/O
EXTAL
XTAL
EXTAL
XTAL
External clock/Oscillator input
Oscillator output
I
O
4.3.4 Analog
Table 11. ADC0 Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
ADC0_SE[11:0]
AD[11:0]
VREFSH
Single-Ended Analog Channel Inputs
Voltage Reference Select High
I
I
VREFH
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Pinouts
I/O
Table 11. ADC0 Signal Descriptions (continued)
Chip signal name
Module signal
name
Description
VREFL
VDDA
VREFSL
VDDA
Voltage Reference Select Low
Analog Power Supply
I
I
Table 12. ACMP0 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
IN[5:0]
CMPO
ACMP0_IN[5:0]
ACMP0_OUT
Analog voltage inputs
Comparator output
I
O
4.3.5 Timer Modules
Table 13. LPTMR0 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
LPTMR0_ALT[3:1]
LPTMR_ALTn
Pulse Counter Input pin
I
Table 14. RTC Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
RTC_CLKOUT
RTC_CLKOUT
1 Hz square-wave output or 32 kHz clock
O
Table 15. FTM0 Signal Descriptions
Chip signal name Module signal name Description
I/O
FTM0_CH[5:0]
FTM0_FLT[3:0]
TCLK[2:0]
CHn
FTM channel (n), where n can be 5-0
Fault input (j), where j can be 3-0
I/O
FAULTj
EXTCLK
I
I
External clock. FTM external clock can be selected to drive the
FTM counter.
Table 16. FTM1 Signal Descriptions
Chip signal name Module signal name Description
I/O
I/O
I
FTM1_CH[1:0]
CHn
PHA
FTM channel (n), where n can be 1-0
FTM1_QD_PHA
Quadrature decoder phase A input. Input pin associated with
quadrature decoder phase A.
Table continues on the next page...
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Table 16. FTM1 Signal Descriptions (continued)
FTM1_QD_PHB
PHB
Quadrature decoder phase B input. Input pin associated with
quadrature decoder phase B.
I
4.3.6 Communication Interfaces
Table 17. CANn Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
CAN Rx
CAN Tx
CANn_RX
CANn_TX
CAN Receive Pin
CAN Transmit Pin
I
O
Table 18. LPSPIn Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
SOUT
SIN
LPSPIn_SOUT
LPSPIn_SIN
Serial Data Out
Serial Data In
O
I
LPSPIn_SCK
SCK
Serial Clock
I/O
I/O
LPSPIn_PCS[3:0]
PCS[3:0]
Peripheral Chip Select 0-3
Table 19. LPI2Cn Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
LPI2Cn_SCL
LPI2Cn_SDA
LPI2Cn_HREQ
SCL
Bidirectional serial clock line of the I2C system.
Bidirectional serial data line of the I2C system.
I/O
I/O
I
SDA
HREQ
Host request, can initiate an LPI2C master transfer if asserted and
the I2C bus is idle.
LPI2Cn_SCLS
LPI2Cn_SDAS
SCLS
SDAS
Secondary I2C clock line.
Secondary I2C data line.
I/O
I/O
Table 20. LPUARTn Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
LPUARTn_TX
LPUARTn_RX
LPUARTn_CTS
LPUARTn_RTS
LPUART_TXD
LPUART_RXD
LPUART_CTS
LPUART_RTS
Transmit data
Receive data
Clear to send
Request to send
I/O
I
I
O
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Pinouts
4.3.7 Human-Machine Interfaces (HMI)
Table 21. GPIO Signal Descriptions
Chip signal name
Module signal
name
Description
I/O
PTA[7:0]
PTB[7:0]
PTC[7:0]
PTD[7:0]
PTE[11:10],
PTE[8],
PORTA7–PORTA0 General-purpose input/output
PORTB7–PORTB0 General-purpose input/output
PORTC7–PORTC0 General-purpose input/output
PORTD7–PORTD0 General-purpose input/output
I/O
I/O
I/O
I/O
I/O
PORTE11–
PORTE10
General-purpose input/output
PORTE8
PTE[6:0]
PORTE6–PORTE0
Table 22. TSI0 Signal Descriptions
Chip signal name
Module signal
Description
I/O
name
TSI0_CH[24:0]
TSI[24:0]
TSI sensing pins or GPIO pins
I/O
4.4 Pinout diagram
The following figure shows the pinout diagram for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see the previous table of Pin Assignments.
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Pinouts
PTA2
PTA3
PTD2
PTD3
PTD4
VDD
36
35
34
33
32
31
30
29
28
27
26
25
PTD1
PTD0
1
2
PTE11
PTE10
PTE5
3
4
5
PTE4
6
VDD
VSS
7
VDDA
PTA6
PTA7
PTB0
PTB1
PTB2
8
VREFH
VSS/VREFL
PTB7
9
10
11
12
PTB6
Figure 5. 48 LQFP Pinout Diagram
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Pinouts
PTA2
PTA3
PTD2
PTD3
PTD4
VDD
33
32
31
30
29
28
27
26
25
PTD1
PTD0
1
2
PTE5
3
PTE4
4
VDD
5
VDDA
6
VSS
VREFH
VSS/VREFL
PTB7
7
PTA6
PTA7
8
9
PTB6
10
11
PTB0
PTB1
24
23
PTE3
Figure 6. 44 LQFP Pinout Diagram
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Pinouts
PTA1
PTA2
PTA3
PTD3
VDD
30
29
28
27
26
25
24
23
22
21
PTD1
PTD0
1
2
PTE11
3
PTE10
4
PTE5
5
PTE4
PTA7
PTB0
PTB1
PTB2
VSS
6
VDD VDDA VREFH
PTB7
7
Exposed Pad (EP)
VSS
8
PTB6
9
PTE8
10
Figure 7. 40 QFN Pinout Diagram
4.5 Package dimensions
The following hyperlinks (package drawings) show the dimensions of the package
options for the devices supported by this document.
• 48-LQFP: 98ASH00962A
• 44-LQFP: 98ASS23225W
• 40-QFN: 98ASA01371D
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Electrical characteristics
5 Electrical characteristics
5.1 Terminology and guidelines
5.1.1 Definitions
Key terms are defined in the following table:
Term
Definition
Rating
A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior
A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value
A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor
guaranteed.
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Electrical characteristics
5.1.2 Examples
Operating rating:
EXAMPLE
EXAMPLE
Operating requirement:
Operating behavior that includes a typical value:
5.1.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
Supply voltage
Value
Unit
TA
25
°C
V
VDD
5.0
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Electrical characteristics
5.1.4 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
5.1.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
5.2 Ratings
5.2.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
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Electrical characteristics
5.2.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
5.2.3 ESD handling ratings
Symbol
VHBM
Description
Min.
Max.
Unit
Notes
Electrostatic discharge voltage, human body model
− 6000
6000
V
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
All pins except the corner pins
Corner pins only
− 500
− 750
− 100
500
750
100
V
V
ILAT
Latch-up current at ambient temperature upper limit
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
5.2.4 Voltage and current operating ratings
NOTE
Functional operating conditions appear in the "DC electrical
specifications". Absolute maximum ratings are stress ratings
only, and functional operation at the maximum values is not
guaranteed. Stress beyond the listed maximum values may
affect device reliability or cause permanent damage to the
device.
Table 23. Voltage and current operating ratings
Symbol
VDD
Description
Min.
–0.3
—
Max.
Unit
V
Supply voltage
5.8 1
IDD
Digital supply current
mA
Table continues on the next page...
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Electrical characteristics
Table 23. Voltage and current operating ratings (continued)
Symbol
VIO
Description
Min.
VSS – 0.3
–25
Max.
VDD + 0.3
25
Unit
V
IO pin input voltage
ID
Instantaneous maximum current single pin limit (applies to
all port pins)
mA
VDDA
Analog supply voltage
VDD – 0.1
VDD + 0.1
V
1. 60s lifetime - No restrictions, i.e. the part can switch.
10 hours lifetime - Device in reset, i.e. the part cannot switch.
5.3 General
5.3.1 Nonswitching electrical specifications
5.3.1.1 Voltage and current operating requirements
Table 24. Voltage and current operating requirements
Symbol Description
Min.
2.7
Max.
5.5
Unit
V
Notes
VDD
Supply voltage
VDDA
Analog supply voltage
VDD-to-VDDA differential voltage
2.7
5.5
V
VDD
–
– 0.1
0.1
V
VDDA
VSS
VSSA
–
VSS-to-VSSA differential voltage
DC injection current — single pin
– 0.1
0.1
V
IICIO
VIN < VSS - 0.3 V (Negative current
injection)
− 3
—
—
mA
mA
1
VIN > VDD + 0.3 V (Positive current
injection)
+ 3
IICcont
Contiguous pin DC injection current —
regional limit, includes sum of negative
injection currents or sum of positive
injection currents of 16 contiguous pins
− 25
VDD
+ 25
VDD
mA
V
VODPU Open drain pullup voltage level
2
1. All pins are internally clamped to VSS and VDD through ESD protection diodes. If VIN is less than VSS – 0.3V or greater
than VDD + 0.3V, a current limiting resistor is required. The negative DC injection current limiting resistor is calculated
as R=(VSS – 0.3V–VIN)/|IICIO|. The positive injection current limiting resistor is calculated as R=[VIN–(VDD + 0.3V)]/|
IICIO|. The actual resistor values should be an order of magnitude higher to tolerate transient voltages.
2. Open drain outputs must be pulled to VDD
.
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Electrical characteristics
5.3.1.2 DC electrical specifications at 3.3 V Range and 5.0 V Range
Table 25. DC electrical specifications
Symbol
Parameter
Value
Typ
3.3
Unit
Notes
Min
Max
VDD
I/O Supply Voltage 1
2.7
4
V
@ VDD = 3.3 V
@ VDD = 5.0 V
4
—
—
5.5
V
V
Vih
Input Buffer High Voltage
@ VDD = 3.3 V
0.7 × VDD
VDD + 0.3
@ VDD = 5.0 V
0.65 × VDD
VSS − 0.3
—
—
VDD + 0.3
0.3 × VDD
V
V
Vil
Input Buffer Low Voltage
@ VDD = 3.3 V
@ VDD = 5.0 V
VSS − 0.3
0.06 × VDD
2.8
—
—
—
0.35 × VDD
V
V
Vhys
Input Buffer Hysteresis
—
—
Ioh_5
Normal drive I/O current source capability
measured when pad = (VDD − 0.8 V)
mA
@ VDD = 3.3 V
@ VDD = 5.0 V
4.8
2.4
—
—
—
—
mA
mA
Iol_5
Ioh_20
Iol_20
Normal drive I/O current sink capability
measured when pad = 0.8 V
@ VDD = 3.3 V
@ VDD = 5.0 V
4.4
—
—
—
—
mA
mA
High drive I/O current source capability
measured when pad = (VDD − 0.8 V), 2
10.8
@ VDD = 3.3 V
@ VDD = 5.0 V
18.5
10.1
—
—
—
—
mA 3
mA
High drive I/O current sink capability measured
when pad = 0.8 V4
@ VDD = 3.3 V
@ VDD = 5.0 V
18.5
—
—
—
—
mA 3
nA
I_leak
VOH
Hi-Z (Off state) leakage current (per pin)
Output high voltage
300
5, 6
7
Normal drive pad (2.7 V ≤ VDD ≤ 4.0 V, IOH = −
2.8 mA)
VDD – 0.8
VDD – 0.8
VDD – 0.8
VDD – 0.8
—
—
—
—
—
—
—
—
V
V
Normal drive pad (4.0 V ≤ VDD ≤ 5.5 V, IOH = −
4.8 mA)
High drive pad (2.7 V ≤ VDD ≤ 4.0 V, IOH = −
10.8 mA)
—
V
High drive pad (4.0 V ≤ VDD ≤ 5.5 V, IOH = −
18.5 mA)
—
V
IOHT
VOL
Output high current total for all ports
Output low voltage
100
mA
7
Table continues on the next page...
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Electrical characteristics
Table 25. DC electrical specifications (continued)
Symbol
Parameter
Value
Typ
—
Unit
Notes
Min
Max
Normal drive pad (2.7 V ≤ VDD ≤ 4.0 V, IOH = −
2.8 mA)
—
0.8
V
V
Normal drive pad (4.0 V ≤ VDD ≤ 5.5 V, IOH = −
4.8 mA)
—
—
—
—
—
—
—
—
0.8
0.8
0.8
100
High drive pad (2.7 V ≤ VDD ≤ 4.0 V, IOH = −
10.8 mA)
V
High drive pad (4.0 V ≤ VDD ≤ 5.5 V, IOH = −
18.5 mA)
V
IOLT
IIN
Output low current total for all ports
mA
Input leakage current (per pin) for full temperature range
@ VDD = 3.3 V
8, 7
All pins other than high drive port pins
High drive port pins
—
—
0.002
0.004
0.5
0.5
μA
μA
Input leakage current (per pin) for full temperature range
@ VDD = 5.5 V
All pins other than high drive port pins
High drive port pins
Internal pull-up resistors
@ VDD = 3.3 V
—
—
20
0.005
0.010
—
0.5
0.5
65
μA
μA
kΩ
RPU
9
@ VDD = 5.0 V
20
20
—
—
50
65
kΩ
kΩ
RPD
Internal pull-down resistors
@ VDD = 3.3 V
10
@ VDD = 5.0 V
20
—
50
kΩ
1. Max power supply ramp rate is 500 V/ms.
2. The value given is measured at high drive strength mode. For value at low drive strength mode see the Ioh_5 value
given above.
3. The 20 mA I/O pin is capable of switching a 50 pF load at up to 40 MHz.
4. The value given is measured at high drive strength mode. For value at low drive strength mode see the Iol_5 value
given above.
5. Refers to the current that leaks into the core when the pad is in Hi-Z (Off state).
6. Maximum pin leakage current at the ambient temperature upper limit.
7. PTD0, PTD1, PTB4, PTB5, PTE0 and PTE1 I/O have both high drive and normal drive capability selected by the
associated Portx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
8. Refers to the pin leakage on the GPIOs when they are OFF.
9. Measured at VDD supply voltage = VDD min and input V = VSS
10. Measured at VDD supply voltage = VDD min and input V = VDD
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Electrical characteristics
5.3.1.3 Voltage regulator electrical characteristics
VDD
48 LQFP /
VDDA
VDD
VSS
44 LQFP
VREFH
Package
VREFL / VSS
Figure 8. Pinout decoupling
Table 26. Voltage regulator electrical characteristics
Symbol
Description
Min.
—
Typ.
100
100
Max.
—
Unit
nF
, 1, 2
CREF
ADC reference high decoupling capacitance
Recommended decoupling capacitance
2, 3
CDEC
—
—
nF
1. For improved ADC performance it is recommended to use 1 nF X7R/C0G and 10 nF X7R ceramics in parallel.
2. The capacitors should be placed as close as possible to the VREFH/VREFL pins or corresponding VDD/VSS pins.
3. The requirement and value of of CDEC will be decided by the device application requirement.
5.3.1.4 LVR, LVD and POR operating requirements
Table 27. VDD supply LVR, LVD and POR operating requirements
Symbol
VPOR
Description
Min.
1.1
Typ.
1.6
Max.
2.0
Unit
V
Notes
Rising and Falling VDD POR detect voltage
VLVRX
LVRX falling threshold (RUN and STOP
modes)
2.53
2.58
2.64
V
LVRX hysteresis
—
45
—
mV
V
1
VLVRX_HYST
VLVRX_LP
LVRX falling threshold (VLPS/VLPR
modes)
1.97
2.12
2.44
VLVRX_LP_HYST LVRX hysteresis (VLPS/VLPR modes)
—
2.8
—
40
2.88
50
—
3
mV
V
VLVD
Falling low-voltage detect threshold
LVD hysteresis
—
mV
1
1
VLVD_HYST
VLVW
VLVW_HYST
VBG
Falling low-voltage warning threshold
LVW hysteresis
4.19
0.97
4.31
68
4.5
V
mV
V
Bandgap voltage reference
1.00
1.03
1. Rising threshold is the sum of falling threshold and hysteresis voltage.
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Electrical characteristics
5.3.1.5 Power mode transition operating behaviors
Table 28. Power mode transition operating behaviors
Description
System Clock
Core, Bus, Flash
frequency (MHz)
Min.
Typ. (μs)1 Max. (μs)2
STOP→RUN
FIRC
FLL
48, 24, 24
—
—
—
—
—
—
—
—
—
—
—
—
—
7.41
13.4
16.5
13.4
16.9
15
STOP→RUN
VLPS→RUN
VLPS→RUN
RUN→VLPR
VLPR→RUN
VLPR→RUN
WAIT→RUN
WAIT→RUN
VLPW→VLPR
VLPS→VLPR
VLPW→RUN
48, 24, 24
10.9
7.41
10.4
14.3
23.5
27
FIRC
FLL
48, 24, 24
48, 24, 24
FLL→SIRC
SIRC→FIRC
SIRC→FLL
FIRC
48, 24, 24→4, 1, 1
4, 1, 1→48, 24, 24
4, 1, 1→48, 24, 24
48, 24, 24
37.3
36
0.620
0.632
20.7
19.8
97.4
88.2
0.760
0.775
28
FLL
48, 24, 24
SIRC
4, 1, 1
SIRC
4, 1, 1
26
FIRC (reset value)
FIRC (reset value)
48, 24, 24 (reset value)
48, 24, 24 (reset value)
109
101
3
tPOR
1. Typical value is the average of values tested at Temperature=25 ℃ and VDD=3.3 V.
2. Max value is mean+6×sigma of tested values at the worst case of ambient temperature range and VDD 2.7 V to 5.5 V.
3. After a POR event, the amount of time from the point VDD reaches the reference voltage 2.7 V to execution of the first
instruction, across the operating temperature range of the chip.
5.3.1.6 Power consumption
The following table shows the power consumption targets for the device in various
modes of operations.
NOTE
The maximum values stated in the following table represent
characterized results equivalent to the mean plus three times
the standard deviation (mean + 3 sigma).
Table 29. Power consumption operating behaviors (48 LQFP and 44 LQFP)
Mode
Symbol
Clock
Configur
ation
Description
Temperat Min
ure
Typ
Max1
Uni
t
RUN
IDD_RUN
LPFLL
Running CoreMark in Flash in Compute 25 ℃
—
—
8.09
8.23
mA
Operation mode.
105 ℃
8.37
8.51
Core@48MHz, bus @24MHz, flash
@24MHz, VDD=5V
LPFLL
Running CoreMark in Flash all
peripheral clock disabled.
25 ℃
—
8.76
8.90
Table continues on the next page...
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Electrical characteristics
Table 29. Power consumption operating behaviors (48 LQFP and 44 LQFP) (continued)
Mode
Symbol
Clock
Configur
ation
Description
Temperat Min
ure
Typ
Max1
Uni
t
Core@48MHz, bus @24MHz, flash
@24MHz, VDD=5V
105 ℃
—
9.04
9.18
LPFLL
Running CoreMark in Flash, all
peripheral clock enabled.
25 ℃
—
—
9.76
9.90
105 ℃
10.06
10.20
Core@48MHz, bus@24MHz, flash
@24MHz, VDD=5V
LPFLL
Running While(1) loop in Flash, all
peripheral clock disabled.
25 ℃
—
—
6.65
6.91
6.79
7.05
105 ℃
Core@48MHz, bus@24MHz, flash
@24MHz, VDD=5V
LPFLL
Running While(1) loop in Flash all
peripheral clock enabled.
25 ℃
—
—
7.66
7.94
7.80
8.08
105 ℃
Core@48MHz , bus@24MHz, flash
@24MHz, VDD=5V
IRC48M
IRC48M
IRC48M
IRC48M
IRC8M
IRC8M
IRC8M
Running CoreMark in Flash in Compute 25 ℃
—
—
7.8
7.94
8.11
Operation mode.
105 ℃
7.97
Core@48MHz, bus @24MHz, flash
@24MHz, VDD=5V
Running CoreMark in Flash all
peripheral clock disabled.
25 ℃
—
—
8.46
8.64
8.60
8.78
105 ℃
Core@48MHz, bus @24MHz, flash
@24MHz, VDD=5V
Running CoreMark in Flash, all
peripheral clock enabled.
25 ℃
—
—
9.47
9.64
9.61
9.78
105 ℃
Core@48MHz, bus@24MHz, flash
@24MHz, VDD=5V
Running While(1) loop in Flash, all
peripheral clock disabled.
25 ℃
—
—
6.35
6.55
6.49
6.69
105 ℃
Core@48MHz, bus@24MHz, flash
@24MHz, VDD=5V
VLPR
IDD_VLPR
Very Low Power Run Core Mark in
Flash in Compute Operation mode.
25 ℃
25 ℃
25 ℃
—
—
—
1480
1580
1510
1522
1622
1552
μA
Core@4MHz, bus @1MHz, flash
@1MHz, VDD=5V
Very Low Power Run Core Mark in
Flash all peripheral clock disabled.
Core@4MHz, bus @1MHz, flash
@1MHz, VDD=5V
Very Low Power Run Core Mark in
Flash all peripheral clock enabled.
Core@4MHz, bus @1MHz, flash
@1MHz, VDD=5V
Table continues on the next page...
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Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020
Electrical characteristics
Table 29. Power consumption operating behaviors (48 LQFP and 44 LQFP) (continued)
Mode
Symbol
Clock
Configur
ation
Description
Temperat Min
ure
Typ
Max1
Uni
t
IRC8M
IRC8M
IRC2M
IRC2M
Very Low Power Run While(1) loop in
Flash all peripheral clock disabled.
25 ℃
25 ℃
25 ℃
25 ℃
—
—
—
—
701
743
Core@4MHz, bus @1MHz, flash
@1MHz, VDD=5V
Very Low Power Run While(1) loop in
Flash all peripheral clock enabled.
765
571
609
807
613
651
Core@4MHz, bus @1MHz, flash
@1MHz, VDD=5V
Very Low Power Run While(1) loop in
Flash all peripheral clock disabled.
Core@2MHz, bus @1MHz, flash
@1MHz, VDD=5V
Very Low Power Run While(1) loop in
Flash all peripheral clock enabled.
Core@2MHz, bus @1MHz, flash
@1MHz, VDD=5V
WAIT
IDD_WAIT
LPFLL
core disabled, system@48MHz, bus
@24MHz, flash disabled (flash doze
enabled), VDD=5 V, all peripheral
clocks disabled
25 ℃
25 ℃
25 ℃
25 ℃
—
—
—
—
—
4.77
4.46
609
525
23
4.87
4.56
644
560
25
mA
IRC48M
core disabled, system@48 MHz, bus
@24MHz, flash disabled (flash doze
enabled), VDD=5 V, all peripheral
clocks disabled
VLPW
IDD_VLPW IRC8M
Very Low Power Wait current, core
disabled system@4MHz, bus and
flash@1MHz, all peripheral clocks
disabled, VDD=5V
μA
IRC2M
Very Low Power Wait current, core
disabled system@2MHz, bus and
flash@1MHz, all peripheral clocks
disabled, VDD=5V
STOP
STOP
IDD_STOP
-
-
Stop mode current, VDD=5V, bias
enabled 2, clock bias enabled , 3
25 ℃ and
below
μA
μA
50 ℃
85 ℃
105 ℃
—
—
—
—
25
36
52
20
27
39
57
22
IDD_STOP
Stop mode current, VDD=5V, bias
enabled 2, clock bias disabled , 3
25 ℃ and
below
50 ℃
85 ℃
105 ℃
—
—
—
22
33
48
25
41
61
Table continues on the next page...
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41
NXP Semiconductors
Electrical characteristics
Table 29. Power consumption operating behaviors (48 LQFP and 44 LQFP) (continued)
Mode
Symbol
Clock
Configur
ation
Description
Temperat Min
ure
Typ
Max1
Uni
t
VLPS
IDD_VLPS
-
-
Very Low Power Stop current, VDD=5V, 25 ℃ and
—
23
25
μA
bias enabled 2, clock bias enabled , 3
below
50 ℃
85 ℃
105 ℃
—
—
—
—
25
36
50
20
27
39
55
22
VLPS
IDD_VLPS
Very Low Power Stop current, VDD=5V, 25 ℃ and
μA
bias enabled 2, clock bias disabled , 3
below
50 ℃
85 ℃
105 ℃
—
—
—
22
33
48
25
41
61
1. These values are based on characterization but not covered by test limits in production.
2. PMC_REGSC[BIASDIS] is the control bit to enable or disable bias under STOP/VLPS mode.
3. PMC_REGSC[CLKBIASDIS] is the control bit to enable or disable clockbias under STOP/VLPS mode.
Table 30. Power consumption operating behaviors (40 QFN)
Mode
Symbol
Clock
Configura
tion
Description
Temperat Min
ure
Typ
Max1 Unit
RUN
IDD_RUN
LPFLL
LPFLL
LPFLL
LPFLL
LPFLL
IRC48M
Running CoreMark in Flash in Compute 25 ℃
—
—
8.09
8.33
8.62
mA
Operation mode.
105 ℃
8.37
Core@48MHz, bus @24MHz, flash
@24MHz, VDD=5V
Running CoreMark in Flash all peripheral 25 ℃
—
—
8.76
9.04
9.02
9.31
clock disabled.
105 ℃
Core@48MHz, bus @24MHz, flash
@24MHz, VDD=5V
Running CoreMark in Flash, all
peripheral clock enabled.
25 ℃
—
—
9.76
10.05
10.36
105 ℃
10.06
Core@48MHz, bus@24MHz, flash
@24MHz, VDD=5V
Running While(1) loop in Flash, all
peripheral clock disabled.
25 ℃
—
—
6.65
6.91
6.85
7.12
105 ℃
Core@48MHz, bus@24MHz, flash
@24MHz, VDD=5V
Running While(1) loop in Flash all
peripheral clock enabled.
25 ℃
—
—
7.66
7.94
7.89
8.18
105 ℃
Core@48MHz , bus@24MHz, flash
@24MHz, VDD=5V
Running CoreMark in Flash in Compute 25 ℃
—
—
7.8
8.03
8.21
Operation mode.
105 ℃
7.97
Table continues on the next page...
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NXP Semiconductors
Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020
Electrical characteristics
Table 30. Power consumption operating behaviors (40 QFN) (continued)
Mode
Symbol
Clock
Configura
tion
Description
Temperat Min
ure
Typ
Max1 Unit
Core@48MHz, bus @24MHz, flash
@24MHz, VDD=5V
IRC48M
IRC48M
IRC48M
IRC8M
IRC8M
IRC8M
IRC8M
IRC8M
IRC2M
IRC2M
Running CoreMark in Flash all peripheral 25 ℃
—
—
8.46
8.71
clock disabled.
105 ℃
8.64
8.90
Core@48MHz, bus @24MHz, flash
@24MHz, VDD=5V
Running CoreMark in Flash, all
peripheral clock enabled.
25 ℃
—
—
9.47
9.64
9.75
9.93
105 ℃
Core@48MHz, bus@24MHz, flash
@24MHz, VDD=5V
Running While(1) loop in Flash, all
peripheral clock disabled.
25 ℃
—
—
6.35
6.55
6.54
6.75
105 ℃
Core@48MHz, bus@24MHz, flash
@24MHz, VDD=5V
VLPR
IDD_VLPR
Very Low Power Run Core Mark in Flash 25 ℃
in Compute Operation mode.
—
—
—
—
—
—
—
1480
1580
1510
701
1670
1783
1704
791
μA
Core@4MHz, bus @1MHz, flash
@1MHz, VDD=5V
Very Low Power Run Core Mark in Flash 25 ℃
all peripheral clock disabled.
Core@4MHz, bus @1MHz, flash
@1MHz, VDD=5V
Very Low Power Run Core Mark in Flash 25 ℃
all peripheral clock enabled.
Core@4MHz, bus @1MHz, flash
@1MHz, VDD=5V
Very Low Power Run While(1) loop in
Flash all peripheral clock disabled.
25 ℃
25 ℃
25 ℃
25 ℃
Core@4MHz, bus @1MHz, flash
@1MHz, VDD=5V
Very Low Power Run While(1) loop in
Flash all peripheral clock enabled.
765
863
Core@4MHz, bus @1MHz, flash
@1MHz, VDD=5V
Very Low Power Run While(1) loop in
Flash all peripheral clock disabled.
571
644
Core@2MHz, bus @1MHz, flash
@1MHz, VDD=5V
Very Low Power Run While(1) loop in
Flash all peripheral clock enabled.
609
687
Core@2MHz, bus @1MHz, flash
@1MHz, VDD=5V
Table continues on the next page...
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43
NXP Semiconductors
Electrical characteristics
Table 30. Power consumption operating behaviors (40 QFN) (continued)
Mode
Symbol
Clock
Configura
tion
Description
Temperat Min
ure
Typ
Max1 Unit
WAIT
IDD_WAIT
LPFLL
IRC48M
IRC8M
IRC2M
-
core disabled, system@48MHz, bus
@24MHz, flash disabled (flash doze
enabled), VDD=5 V, all peripheral clocks
disabled
25 ℃
25 ℃
25 ℃
25 ℃
—
—
—
—
—
4.77
5.37
mA
core disabled, system@48 MHz, bus
@24MHz, flash disabled (flash doze
enabled), VDD=5 V, all peripheral clocks
disabled
4.46
609
525
23
5.02
747
644
31
VLPW
IDD_VLPW
Very Low Power Wait current, core
disabled system@4MHz, bus and
flash@1MHz, all peripheral clocks
disabled, VDD=5V
μA
Very Low Power Wait current, core
disabled system@2MHz, bus and
flash@1MHz, all peripheral clocks
disabled, VDD=5V
STOP
STOP
VLPS
VLPS
IDD_STOP
IDD_STOP
IDD_VLPS
IDD_VLPS
Stop mode current, VDD=5V, bias
enabled 2, clock bias enabled , 3
25 ℃ and
below
μA
μA
μA
μA
50 ℃
85 ℃
105 ℃
—
—
—
—
25
36
52
20
51
74
103
28
-
-
-
Stop mode current, VDD=5V, bias
enabled 2, clock bias disabled , 3
25 ℃ and
below
50 ℃
85 ℃
105 ℃
—
—
—
—
22
33
48
23
46
69
100
31
Very Low Power Stop current, VDD=5V, 25 ℃ and
bias enabled 2, clock bias enabled , 3
below
50 ℃
85 ℃
105 ℃
—
—
—
—
25
36
50
20
51
74
102
27
Very Low Power Stop current, VDD=5V, 25 ℃ and
bias enabled 2, clock bias disabled , 3
below
50 ℃
85 ℃
105 ℃
—
—
—
22
33
48
46
68
100
1. These values are based on characterization but not covered by test limits in production.
2. PMC_REGSC[BIASDIS] is the control bit to enable or disable bias under STOP/VLPS mode.
3. PMC_REGSC[CLKBIASDIS] is the control bit to enable or disable clockbias under STOP/VLPS mode.
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Electrical characteristics
NOTE
CoreMark benchmark compiled using IAR 8.30 with
optimization level high, optimized for balanced.
5.3.1.6.1 Low power mode peripheral current adder — typical value
Symbol
Description
Typical
ILPTMR
LPTMR peripheral adder measured by placing the device in VLPS
mode with LPTMR enabled using LPO. Includes LPO power
consumption.
366 nA
ICMP
CMP peripheral adder measured by placing the device in VLPS mode
with CMP enabled using the 8-bit DAC and a single external input for
compare. 8-bit DAC enabled with half VDDA voltage, low speed mode.
Includes 8-bit DAC power consumption.
16 μA
IRTC
RTC peripheral adder measured by placing the device in VLPS mode
with external 32 kHz crystal enabled by means of the RTC_CR[OSCE]
bit and the RTC counter enabled. Includes EXTAL32 (32 kHz external
crystal) power consumption.
312 nA
ILPUART
LPUART peripheral adder measured by placing the device in VLPS
mode with selected clock source waiting for RX data at 115200 baud
rate. Includes selected clock source power consumption. (SIRC 8 MHz)
79 μA
45 μA
IFTM
FTM peripheral adder measured by placing the device in VLPW mode
with selected clock source, outputting the edge aligned PWM of 100 Hz
frequency.
IADC
ADC peripheral adder combining the measured values at VDD and
VDDA by placing the device in VLPS mode. ADC is configured for low
power mode using SIRC clock source, 8-bit resolution and continuous
conversions.
484 μA
ILPI2C
LPI2C peripheral adder measured by placing the device in VLPS mode
with selected clock source sending START and Slave address, waiting
for RX data. Includes the DMA power consumption.
179 μA
18 μA
ILPIT
LPIT peripheral adder measured by placing the device in VLPS mode
with internal SIRC 8 MHz enabled in Stop mode. Includes selected
clock source power consumption.
ILPSPI
IMSCAN
ITSI
LPSPI peripheral adder measured by placing the device in VLPS mode
with selected clock source, output data on SOUT pin with SCK 500
kbit/s. Includes the DMA power consumption.
565 μA
2354 μA
784 μA
MSCAN peripheral adder measured by placing the device in RUN
mode, CAN baud rate = 125 kbps, loopback mode: MSCAN receives
the frame sent by itself continuously.
TSI self-cap mode:
TSI peripheral adder measured by placing the device in RUN mode,
continuous TSI self-cap mode scan with 11.6 kHz switching clock.
TSI mutual-cap mode:
899 μA
TSI peripheral adder measured by placing the device in RUN mode,
continuous TSI mutual-cap mode scan with 37.22 kHz switching clock.
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NXP Semiconductors
Electrical characteristics
5.3.1.6.2 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• SCG in SOSC for both Run and VLPR modes
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Figure 9. Run mode supply current vs. core frequency
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NXP Semiconductors
Electrical characteristics
Figure 10. VLPR mode supply current vs. core frequency
5.3.1.7 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components, and MCU software
operation play a significant role in the EMC performance. The system designer can
consult the following applications notes, available on http://www.nxp.com for advice
and guidance specifically targeted at optimizing EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
• AN2764: Improving the Transient Immunity Performance of Microcontroller-
Based Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCU-
Based Systems
5.3.1.7.1 EMC radiated emissions operating behaviors
EMC measurements to IC-level IEC standards are available from NXP on request.
Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020
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NXP Semiconductors
Electrical characteristics
5.3.1.7.2 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions.
1. Go to http://www.nxp.com.
2. Perform a keyword search for “EMC design”.
3. Select the "Documents" category and find the application notes.
5.3.1.8 Capacitance attributes
Table 31. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
pF
Input capacitance: analog pins
Input capacitance: digital pins
7
7
CIN_D
—
pF
NOTE
Please refer to External Oscillator electrical specifications for
EXTAL/XTAL pins.
5.3.2 Switching specifications
5.3.2.1 Device clock specifications
Table 32. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
Normal run mode
fSYS
fBUS
fFLASH
fLPTMR
System and core clock
Bus clock
—
—
—
—
48
24
25
48
MHz
MHz
MHz
MHz
Flash clock
LPTMR clock
VLPR / VLPW mode1
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
—
4
1
MHz
MHz
MHz
MHz
MHz
fFLASH
fERCLK
fLPTMR
Flash clock
1
External reference clock
LPTMR clock
16
13
1. The frequency limitations in VLPR / VLPW mode here override any frequency specification listed in the timing
specification for any other module.
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Electrical characteristics
5.3.2.2 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 11. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Normal drive strength
5.3.2.3 General AC specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and timers.
Table 33. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1, 2
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
50
—
—
ns
3
4
GPIO pin interrupt pulse width (digital glitch filter
disabled, passive filter disabled) — Asynchronous
path
ns
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses
may or may not be recognized. In Stop and VLPS modes, the synchronizer is bypassed so shorter pulses can be
recognized in that case.
2. The greater of synchronous and asynchronous timing must be met.
3. These pins have a passive filter enabled on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
4. These pins do not have a passive filter on the inputs. This is the shortest pulse width that is guaranteed to be
recognized.
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Electrical characteristics
5.3.2.4 AC specifications at 3.3 V range
Table 34. Functional pad AC specifications
Characteristic
Symbol
Min
Typ
Max
Unit
I/O Supply Voltage
Vdd 1
2.7
4
V
1. Max power supply ramp rate is 500 V/ms.
Name
Prop Delay (ns) 1
Rise/Fall Edge (ns) 2
Min Max
Drive Load (pF)
Max
17.5
28
Normal drive I/O pad
High drive I/O pad
CMOS Input 3
5
9
17
32
17
33
3
25
50
25
50
0.5
19
5
26
9
4
1.2
1. Propagation delay measured from 50ꢀ of core side input to 50ꢀ of the output.
2. Edges measured using 20ꢀ and 80ꢀ of the VDD supply.
3. Input slope = 2 ns.
NOTE
All measurements were taken accounting for 150 mV drop
across VDD and VSS.
5.3.2.5 AC specifications at 5 V range
Table 35. Functional pad AC specifications
Characteristic
Symbol
Min
Typ
Max
5.5
Unit
I/O Supply Voltage
Vdd 1
4
V
1. Max power supply ramp rate is 500 V/ms.
Name
Prop Delay (ns) 1
Rise/Fall Edge (ns) 2
Min Max
Drive Load (pF)
Max
12
18
13
19
3
Normal drive I/O pad
High drive I/O pad
CMOS Input 3
3.6
8
10
17
10
19
2.8
25
50
25
50
0.5
3.6
8
1.2
1. As measured from 50ꢀ of core side input to 50ꢀ of the output.
2. Edges measured using 20ꢀ and 80ꢀ of the VDD supply.
3. Input slope = 2 ns.
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Electrical characteristics
NOTE
All measurements were taken accounting for 150 mV drop
across VDD and VSS.
5.3.3 Thermal specifications
5.3.3.1 Thermal operating requirements
Table 36. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Notes
Die junction temperature
Ambient temperature
TA
105
°C
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed maximum TJ. The simplest method to
determine TJ is: TJ = TA + RΘJA × chip power dissipation.
5.3.3.2 Thermal attributes
5.3.3.2.1 Description
The tables in the following sections describe the thermal characteristics of the device.
NOTE
Junction temperature is a function of die size, on-chip power
dissipation, package thermal resistance, mounting side
(board) temperature, ambient temperature, air flow, power
dissipation or other components on the board, and board
thermal resistance.
5.3.3.2.2 Thermal characteristics for the 44-pin LQFP package
Table 37. Thermal characteristics for the 44-pin LQFP package
Rating
Conditions
Symbol
Value
Unit
Thermal resistance, Junction to Ambient
(Natural Convection)1, 2
Single layer board (1s)
RθJA
74
°C/W
Thermal resistance, Junction to Ambient
(Natural Convection)1, 2
Four layer board (2s2p)
Single layer board (1s)
RθJA
52
61
°C/W
°C/W
Thermal resistance, Junction to Ambient
(@200 ft/min)1, 3
RθJMA
Table continues on the next page...
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Electrical characteristics
Table 37. Thermal characteristics for the 44-pin LQFP package (continued)
Rating
Conditions
Symbol
Value
Unit
Thermal resistance, Junction to Ambient
(@200 ft/min)1, 3
Four layer board (2s2p)
RθJMA
45
°C/W
Thermal resistance, Junction to Board4
Thermal resistance, Junction to Case 5
Thermal resistance, Junction to Package Top6
—
—
RθJB
RθJC
ψJT
32
19
5
°C/W
°C/W
°C/W
Natural Convection
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for
1s or 2s2p board, respectively.
3. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s
or 2s2p board, respectively.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
5.3.3.2.3 Thermal characteristics for the 48-pin LQFP package
Table 38. Thermal characteristics for the 48-pin LQFP package
Rating
Conditions
Symbol
Value
Unit
Thermal resistance, Junction to Ambient
(Natural Convection)1, 2
Single layer board (1s)
RθJA
79
°C/W
Thermal resistance, Junction to Ambient
(Natural Convection)1, 2
Four layer board (2s2p)
Single layer board (1s)
Four layer board (2s2p)
RθJA
RθJMA
RθJMA
55
66
49
°C/W
°C/W
°C/W
Thermal resistance, Junction to Ambient
(@200 ft/min)1, 3
Thermal resistance, Junction to Ambient
(@200 ft/min)1, 3
Thermal resistance, Junction to Board4
Thermal resistance, Junction to Case 5
Thermal resistance, Junction to Package Top6
—
—
RθJB
RθJC
ψJT
33
23
6
°C/W
°C/W
°C/W
Natural Convection
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for
1s or 2s2p board, respectively.
3. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for 1s
or 2s2p board, respectively.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
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Electrical characteristics
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2.
5.3.3.2.4 Thermal characteristics for the 40-pin QFN package
Table 39. Thermal characteristics for the 40-pin QFN package
Rating
Board Type 1
Symbol
RθJA
Value
28.6
Unit
Junction to Ambient
Thermal Resistance 2
JESD51-9, 2s2p
℃/W
Junction-to-Top of
Package Thermal
Characterization
Parameter 2
JESD51-9, 2s2p
JESD51-9
ΨJT
0.2
℃/W
℃/W
Junction to Case
RθJC
1.6
Thermal Resistance 3
1. Thermal test board meets JEDEC specification for this package (JESD51-9).
2. Determined in accordance to JEDEC JESD51-2A natural convection environment. Thermal resistance data in this
report is solely for a thermal performance comparison of one package to another in a standardized specified
environment. It is not meant to predict the performance of a package in an application-specific environment.
3. Junction-to-Case thermal resistance determined using an isothermal cold plate. Case is defined as the bottom of the
packages (exposed pad).
5.3.3.2.5 General notes for specifications at maximum junction temperature
An estimation of the chip junction temperature, TJ, can be obtained from this
equation:
TJ = TA + (RθJA × PD)
where:
• TA = ambient temperature for the package (°C)
• RθJA = junction to ambient thermal resistance (°C/W)
• PD = power dissipation in the package (W)
The junction to ambient thermal resistance is an industry standard value that provides
a quick and easy estimation of thermal performance. Unfortunately, there are two
values in common usage: the value determined on a single layer board and the value
obtained on a board with two planes. For packages such as the PBGA, these values
can be different by a factor of two. Which value is closer to the application depends
on the power dissipated by other components on the board. The value obtained on a
single layer board is appropriate for the tightly packed printed circuit board. The value
obtained on the board with the internal planes is usually appropriate if the board has
low power dissipation and the components are well separated.
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When a heat sink is used, the thermal resistance is expressed in the following equation
as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal
resistance:
RθJA = RθJC + RθCA
where:
• RθJA = junction to ambient thermal resistance (°C/W)
• RθJC = junction to case thermal resistance (°C/W)
• RθCA = case to ambient thermal resistance (°C/W)
RθJC is device related and cannot be influenced by the user. The user controls the
thermal environment to change the case to ambient thermal resistance, RθCA. For
instance, the user can change the size of the heat sink, the air flow around the device,
the interface material, the mounting arrangement on printed circuit board, or change the
thermal dissipation on the printed circuit board surrounding the device.
To determine the junction temperature of the device in the application when heat sinks
are not used, the Thermal Characterization Parameter (ΨJT) can be used to determine
the junction temperature with a measurement of the temperature at the top center of the
package case using this equation:
TJ = TT + (ΨJT × PD)
where:
• TT = thermocouple temperature on top of the package (°C)
• ΨJT = thermal characterization parameter (°C/W)
• PD = power dissipation in the package (W)
The thermal characterization parameter is measured per JESD51-2 specification using a
40 gauge type T thermocouple epoxied to the top center of the package case. The
thermocouple should be positioned so that the thermocouple junction rests on the
package. A small amount of epoxy is placed over the thermocouple junction and over
about 1 mm of wire extending from the junction. The thermocouple wire is placed flat
against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
5.4 Peripheral operating requirements and behaviors
54
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5.4.1 System modules
There are no specifications necessary for the device's system modules.
5.4.2 Clock interface modules
5.4.2.1 Oscillator electrical specifications
5.4.2.1.1 External Oscillator electrical specifications
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Single input buffer
(EXTAL WAVE)
ref_clk
mux
Differential input comparator
(HG/LP mode)
Peak detector
LP mode
Driver
(HG/LP mode)
Pull down resistor (OFF)
ESD PAD
300 ohms
ESD PAD
40 ohms
XTAL pin
EXTAL pin
1
Series resistor for current
limitation
1M ohms Feedback Resistor
Crystal or resonator
C1
C2
NOTE:
1. 1M Feedback resistor is needed only for HG mode.
Figure 12. Oscillator connections scheme (OSC)
NOTE
Data values in the following "External Oscillator electrical
specifications" tables are from simulation.
Table 40. External Oscillator electrical specifications (OSC)
Symbol
VDD
Description
Min.
Typ.
Max.
Unit Notes
Supply voltage
2.7
—
5.5
V
IDDOSC
Supply current — low-gain mode (low-power mode) (HGO=0)
1
4 MHz
8 MHz
—
200
300
—
—
µA
µA
—
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Table 40. External Oscillator electrical specifications (OSC)
(continued)
Symbol
Description
Min.
—
Typ.
1.2
1.6
2
Max.
—
Unit Notes
16 MHz
mA
mA
mA
mA
1
24 MHz
—
—
32 MHz
—
—
40 MHz
—
2.6
—
IDDOSC
Supply current — high-gain mode (HGO=1)
32 kHz
—
—
—
—
—
—
—
25
1
—
—
—
—
—
—
—
µA
4 MHz
mA
mA
mA
mA
mA
mA
8 MHz
1.2
3.5
5
16 MHz
24 MHz
32 MHz
5.5
6
40 MHz
gmXOSC
Fast external crystal oscillator transconductance
32 kHz, Low Frequency Range, High Gain (32 kHz)
Medium Frequency Range (4-8 MHz)
High Frequency Range (8-40 MHz)
Input high voltage — EXTAL pin in external clock mode
Input low voltage — EXTAL pin in external clock mode
EXTAL load capacitance
15
2.2
16
—
—
45
9.7
37
µA / V
mA / V
mA / V
VIH
VIL
C1
C2
RF
1.75
VSS
—
—
—
—
—
VDD
1.20
—
V
V
2
XTAL load capacitance
—
—
2
Feedback resistor
3
Low-frequency, high-gain mode (32 kHz)
—
—
10
—
—
—
MΩ
MΩ
Medium/high-frequency, low-gain mode (low-power
mode) (4-8 MHz, 8-40 MHz)
Medium/high-frequency, high-gain mode (4-8 MHz,
8-40 MHz)
—
1
—
MΩ
RS
Series resistor
Low-frequency, high-gain mode (32 kHz)
—
—
200
0
—
—
kΩ
kΩ
Medium/high-frequency, low-gain mode (low-power
mode) (4-8 MHz, 8-40 MHz)
Medium/high-frequency, high-gain mode (4-8 MHz,
8-40 MHz)
—
0
—
kΩ
Vpp
Peak-to-peak amplitude of oscillation (oscillator mode)
Low-frequency, high-gain mode
4
—
—
—
3.3
1.0
3.3
—
—
—
V
V
V
Medium/high-frequency, low-gain mode
Medium/high-frequency, high-gain mode
1. Measured at VDD = 5 V, Temperature = 25 °C. The current consumption is according to the crystal or resonator,
loading capacitance.
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2. C1 and C2 must be provided by external capacitors and their load capacitance depends on the crystal or resonator
manufacturers' recommendation. Please check the crystal datasheet for the recommended values. And also consider
the parasitic capacitance of package and board.
3. When low power mode is selected, RF is integrated and must not be attached externally.
4. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
5.4.2.1.2 External Oscillator frequency specifications
Table 41. External Oscillator frequency specifications (OSC)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fosc_lo
fosc_me
fosc_hi
Oscillator crystal or resonator frequency — Low
Frequency, High Gain Mode
32
—
40
kHz
Oscillator crystal or resonator frequency —
Medium Frequency
4
8
—
—
8
MHz
Oscillator crystal or resonator frequency — High
Frequency
40
tdc_extal Input clock duty cycle (external clock mode)
fec_extal Input clock frequency (external clock mode)
40
—
—
50
—
60
50
—
ꢀ
MHz
ms
tcst
Crystal startup time — 32 kHz Low Frequency,
High-Gain Mode
500
1
Crystal startup time — 8 MHz Medium
Frequency, Low-Power Mode
—
—
—
—
1.5
2.5
2
—
—
—
—
Crystal startup time — 8 MHz Medium
Frequency, High-Gain Mode
Crystal startup time — 40 MHz High Frequency,
Low-Power Mode
Crystal startup time — 40 MHz High Frequency,
High-Gain Mode
2.5
1. The start-up measured after 4096 cycles. Proper PC board layout procedures must be followed to achieve
specifications.
5.4.2.2 System Clock Generation (SCG) specifications
5.4.2.2.1 Fast internal RC Oscillator (FIRC) electrical specifications
Table 42. Fast internal RC Oscillator electrical specifications
Symbol
Parameter
Value
Typ.
Unit
Min.
Max.
FFIRC
Fast internal reference frequency
—
—
MHz
48
400
—
IVDD
Supply current
—
500
µA
FUntrimmed IRC frequency (untrimmed)
FIRC
×
FIRC
×
MHz
(1-0.3)
(1+0.3)
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Electrical characteristics
Table 42. Fast internal RC Oscillator electrical specifications
(continued)
Symbol
Parameter
Value
Typ.
Unit
Min.
Max.
ΔFOL
Open loop total deviation of IRC frequency over voltage and
temperature1
Regulator enable
Startup time
—
—
0.5
—
1
3
ꢀFFIRC
µs2
TStartup
TJIT
Period jitter (RMS)
35
150
ps
1. The limit is respected across process, voltage and full temperature range.
2. Startup time is defined as the time between clock enablement and clock availability for system use.
NOTE
Fast internal RC Oscillator is compliant with CAN and LIN
standards.
5.4.2.2.2 Slow internal RC oscillator (SIRC) electrical specifications
Table 43. Slow internal RC oscillator (SIRC) electrical specifications
Symbol
Parameter
Value
Typ.
2
Unit
Min.
Max.
FSIRC
Slow internal reference frequency
—
—
MHz
8
IVDD
FUntrimmed
ΔFOL
Supply current
—
—
23
—
—
µA
IRC frequency (untrimmed)
—
MHz
Open loop total deviation of IRC frequency over
voltage and temperature1
Regulator enable
Startup time
—
—
—
6
3
ꢀFSIRC
µs2
TStartup
—
1. The limit is respected across process, voltage and full temperature range.
2. Startup time is defined as the time between clock enablement and clock availability for system use.
5.4.2.2.3 Low Power Oscillator (LPO) electrical specifications
Table 44. Low Power Oscillator (LPO) electrical specifications
Symbol
FLPO
Parameter
Internal low power oscillator frequency
Current consumption
Min.
113
1
Typ.
128
3
Max.
139
7
Unit
kHz
µA
ILPO
Tstartup
Startup Time
—
—
20
µs
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5.4.2.2.4 LPFLL electrical specifications
Table 45. LPFLL electrical specifications
Symbol
Iavg
Parameter
Min.
Typ.
240
3.6
—
Max.
Unit
μA
μs
Power consumption
Start-up time
Tstart
ΔFol
Frequency accuracy over temperature and voltage
in open loop after process trimmed
–10
–1 1
10
ꢀ
ΔFcl
Frequency accuracy in closed loop
—
1 1
ꢀ
1. ΔFcl is dependent on reference clock accuracy. For example, if locked to crystal oscillator, ΔFcl is typically limited by
trimming ability of the module itself; if locked to other clock source which has 3ꢀ accuracy, then ΔFcl can only be 3ꢀ.
5.4.3 Memories and memory interfaces
5.4.3.1 Flash memory module (FTFA) electrical specifications
This section describes the electrical characteristics of the flash memory module
(FTFA).
5.4.3.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 46. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
13
Max.
18
Unit
μs
Notes
thvpgm4
Longword Program high-voltage time
—
1
thversscr Sector Erase high-voltage time
—
113
452
ms
ms
thversall
Erase All high-voltage time
—
52
1
1. Maximum time based on expectations at cycling end-of-life.
5.4.3.1.2 Flash timing specifications — commands
Table 47. Flash command timing specifications
Symbol Description
Min.
—
Typ.
—
Max.
60
Unit
μs
Notes
trd1sec1k Read 1s Section execution time (flash sector)
1
1
tpgmchk
trdrsrc
Program Check execution time
Read Resource execution time
Program Longword execution time
—
—
45
μs
—
—
30
μs
1
tpgm4
—
65
145
μs
—
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Electrical characteristics
Table 47. Flash command timing specifications (continued)
Symbol Description
tersscr Erase Flash Sector execution time
trd1all
Min.
—
Typ.
14
—
Max.
114
0.9
25
Unit
ms
ms
μs
Notes
2
1
Read 1s All Blocks execution time
Read Once execution time
—
trdonce
—
—
1
tpgmonce Program Once execution time
—
65
70
—
—
μs
—
2
tersall
tvfykey
tersallu
Erase All Blocks execution time
—
575
30
ms
μs
Verify Backdoor Access Key execution time
Erase All Blocks Unsecure execution time
—
1
—
70
575
ms
2
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
5.4.3.1.3 Flash high voltage current behaviors
Table 48. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
5.4.3.1.4 Reliability specifications
Table 49. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
—
—
2
20
100
50 K
10 K
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
5.4.4 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
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5.4.5 Analog
5.4.5.1 ADC electrical specifications
5.4.5.1.1 12-bit ADC operating conditions
Table 50. 12-bit ADC operating conditions
Symbol Description
Conditions
Absolute
Min.
2.7
Typ.1
Max.
5.5
Unit
V
Notes
VDDA
Supply voltage
Supply voltage
—
ΔVDDA
Delta to VDD
-100
0
+100
mV
2
2
3
3
(VDD – VDDA
)
ΔVSSA
Ground voltage
Delta to VSS (VSS
-100
2.5
0
+100
mV
V
– VSSA
)
VREFH
ADC reference voltage high
VDDA
VDDA +
100m
VREFL
VADIN
RS
ADC reference voltage low
Input voltage
− 100
VREFL
—
0
100
VREFH
5
mV
V
—
—
0.5
Source impedendance
fADCK < 4 MHz
kΩ
kΩ
RSW1
Channel Selection Switch
Impedance
—
1.2
RAD
CP1
CP2
CS
Sampling Switch Impedance
Pin Capacitance
—
—
—
—
2
2
3
5
—
5
kΩ
pF
Analog Bus Capacitance
Sampling capacitance
—
4
pF
5
pF
fADCK
ADC conversion clock
frequency
40
48
MHz
4, 5
7
Crate
ADC conversion rate
No ADC
20
—
1200
Ksps
hardware
averaging6
Continuous
conversions
enabled,
subsequent
conversion time
1. Typical values assume VDDA = 5 V, Temp = 25 °C, fADCK = 40 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
VSSA
.
4. Clock and compare cycle need to be set according the guidelines in the block guide.
5. ADC conversion will become less reliable above maximum frequency.
6. When using ADC hardware averaging, refer to the device Reference Manual to determine the most appropriate setting
for AVGS.
7. Max ADC conversion rate of 1200 Ksps is with 10-bit mode
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Figure 13. ADC input impedance equivalency diagram
5.4.5.1.2 12-bit ADC electrical characteristics
NOTE
All the parameters in the table are given assuming system
clock as the clocking source for ADC.
NOTE
For ADC signals adjacent to VDD/VSS or the XTAL pins
some degradation in the ADC performance may be
observed.
NOTE
All values guarantee the performance of the ADC for the
multiple ADC input channel pins. When using the ADC to
monitor the internal analogue parameters, please assume
minor degradation.
Table 51. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
Typ.2
Max. 3
Unit
Notes
IDDA_ADC Supply current at 2.7
to 5.5 V
470
515 μA @
5 V
560
μA
4
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Table 51. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max. 3
Unit
Notes
Sample Time
275
—
Refer to
the
ns
device's
Reference
Manual
TUE
DNL
INL
Total unadjusted error
at 2.7 to 5.5 V
—
—
—
—
—
—
—
—
4.5
0.8
1.4
–2
6.11
1.07
3.54
-3.60
-4.24
0.5
LSB5
LSB5
LSB5
LSB5
LSB5
LSB5
bits
6
Differential non-
linearity at 2.7 to 5.5 V
6
Integral non-linearity at
2.7 to 5.5 V
6
6
EFS
Full-scale error at 2.7
to 5.5 V
VADIN = VDDA
EZS
Zero-scale error at 2.7
to 5.5 V
–2.7
—
EQ
Quantization error at
2.7 to 5.5 V
ENOB
Effective number of
bits at 2.7 to 5.5 V
11.3
70
—
7
Signal-to-noise plus
See ENOB
—
SINAD = 6.02 ×
ENOB + 1.76
SINAD distortion at 2.7 to 5.5
V
dB
EIL
Input leakage error at
2.7 to 5.5 V
IIn × RAS
mV
IIn = leakage
current (refer to
the MCU's
voltage and
current operating
ratings)
VTEMP_S Temp sensor slope at Across the full
1.492
730
1.564
740.5
1.636
751
mV/°C
mV
8, 9
2.7 to 5.5 V
temperature
range of the
device
VTEMP25 Temp sensor voltage 25 °C
at 2.7 to 5.5 V
8, 9
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 5.0 V, Temp = 25 °C, fADCK = 48 MHz unless otherwise stated.
3. These values are based on characterization but not covered by test limits in production.
4. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
5. 1 LSB = (VREFH - VREFL)/2N
6. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = ꢀ1, AVGS = ꢀ11)
7. Input data is 100 Hz sine wave. ADC conversion clock < 40 MHz.
8. ADC conversion clock < 3 MHz
9. The sensor must be calibrated to gain good accuracy, so as to provide good linearity, see also AN3031 for more detailed
application information of the temperature sensor.
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5.4.5.2 CMP with 8-bit DAC electrical specifications
Table 52. Comparator with 8-bit DAC electrical specifications
Symbol
VDD
Description
Min.
Typ. 1
Max.
Unit
V
Supply voltage
2.7
—
5.5
IDDHS
Supply current, High-speed mode2
within ambient temperature range
Supply current, Low-speed mode2
within ambient temperature range
Analog input voltage
μA
—
145
200
IDDLS
μA
—
0
5
10
VAIN
VAIO
0 - VDDX
VDDX
V
Analog input offset voltage, High-speed mode
within ambient temperature range
Analog input offset voltage, Low-speed mode
within ambient temperature range
Propagation delay, High-speed mode3
within ambient temperature range
Propagation delay, Low-speed mode3
within ambient temperature range
Propagation delay, High-speed mode4
within ambient temperature range
Propagation delay, Low-speed mode4
within ambient temperature range
Initialization delay, High-speed mode 3
within ambient temperature range
Initialization delay, Low-speed mode3
within ambient temperature range
mV
-25
-40
—
—
—
—
—
—
—
1
4
25
40
200
2
VAIO
tDHSB
tDLSB
tDHSS
tDLSS
tIDHS
mV
ns
30
0.5
70
1
µs
ns
400
5
µs
μs
1.5
10
0
3
tIDLS
μs
30
—
VHYST0
Analog comparator hysteresis, Hyst0 (VAIO
within ambient temperature range
)
mV
mV
VHYST1
Analog comparator hysteresis, Hyst1, High-speed
mode
within ambient temperature range
—
—
—
—
16
11
32
22
53
30
90
53
Analog comparator hysteresis, Hyst1, Low-speed
mode
within ambient temperature range
VHYST2
Analog comparator hysteresis, Hyst2, High-speed
mode
mV
mV
within ambient temperature range
Analog comparator hysteresis, Hyst2, Low-speed
mode
within ambient temperature range
VHYST3
Analog comparator hysteresis, Hyst3, High-speed
mode
Table continues on the next page...
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Table 52. Comparator with 8-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ. 1
Max.
Unit
within ambient temperature range
—
48
133
Analog comparator hysteresis, Hyst3, Low-speed
mode
within ambient temperature range
8-bit DAC current adder (enabled)
8-bit DAC integral non-linearity
8-bit DAC differential non-linearity
—
—
33
10
—
—
80
16
IDAC8b
INL
μA
LSB5
–0.6
–0.5
0.5
0.5
DNL
LSB
1. Typical values assumed at VDDA = 5.0 V, Temp = 25 ℃, unless otherwise stated.
2. Difference at input > 200mV
3. Applied (100 mV + Hyst) around switch point
4. Applied (30 mV + 2 × Hyst) around switch point
5. 1 LSB = Vreference/256
Figure 14. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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Figure 15. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
Figure 16. Typical hysteresis vs. Vin level (VDD = 5 V, PMODE = 0)
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Figure 17. Typical hysteresis vs. Vin level (VDD = 5 V, PMODE = 1)
5.4.6 Communication interfaces
5.4.6.1 LPUART electrical specifications
Refer to General AC specifications for LPUART specifications.
5.4.6.2 LPSPI electrical specifications
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus
with master and slave operations. Many of the transfer attributes are programmable.
The following tables provide timing characteristics for classic LPSPI timing modes.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as
well as input signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins.
Table 53. LPSPI master mode timing
Num.
Symbol Description
fSPSCK Frequency of SPSCK
tSPSCK
Min.
Max.
Unit
Hz
Note
1
2
fperiph/2048
2 x tperiph
fperiph/2
1
2
SPSCK period
2048 x
tperiph
ns
3
4
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
—
—
Table continues on the next page...
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Electrical characteristics
Table 53. LPSPI master mode timing (continued)
Num.
Symbol Description
Min.
Max.
Unit
Note
5
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
1024 x
tperiph
ns
—
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
18
0
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
15
8
tv
—
0
9
tHO
tRI
—
10
—
tperiph - 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. fperiph is LPSPI peripheral functional clock. On this device, the max value of fSPSCK should not exceed 25 MHz.
2. tperiph = 1/fperiph
NOTE
High drive pin should be used for fast bit rate.
1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. LPSPI master mode timing (CPHA = 0)
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Electrical characteristics
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
LSB IN
MSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER MSB OUT
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 19. LPSPI master mode timing (CPHA = 1)
Table 54. LPSPI slave mode timing
Num.
1
Symbol Description
Min.
Max.
Unit
Hz
Note
1
fSPSCK
tSPSCK
tLead
Frequency of SPSCK
SPSCK period
0
fperiph/2
2
2 x tperiph
—
—
ns
2
3
Enable lead time
Enable lag time
1
tperiph
tperiph
ns
—
—
—
—
—
3
4
tLag
1
—
5
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
—
6
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
2.5
3.5
—
—
—
0
—
ns
7
—
ns
8
tperiph
tperiph
31
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
—
ns
—
tperiph - 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. fperiph is LPSPI peripheral functional clock. On this device, the max value of fSPSCK should not exceed 25 MHz.
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
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Electrical characteristics
SS
(INPUT)
2
12
12
13
13
4
SPSCK
(CPOL=0)
(INPUT)
5
5
3
SPSCK
(CPOL=1)
(INPUT)
9
8
10
11
11
see
note
SEE
NOTE
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
6
MOSI
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
Figure 20. LPSPI slave mode timing (CPHA = 0)
SS
(INPUT)
4
2
12
12
13
13
3
SPSCK
(CPOL=0)
(INPUT)
5
5
SPSCK
(CPOL=1)
(INPUT)
11
9
10
SLAVE MSB OUT
see
note
MISO
(OUTPUT)
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
8
6
7
MOSI
(INPUT)
MSB IN
Figure 21. LPSPI slave mode timing (CPHA = 1)
5.4.6.3 LPI2C
Table 55. LPI2C specifications
Symbol Description
Min.
Max.
100
Unit
Notes
fSCL
SCL clock frequency
Standard mode (Sm)
Fast mode (Fm)
0
0
0
0
0
kHz
1, 2, 3
400
Fast mode Plus (Fm+)
Ultra Fast mode (UFm)
High speed mode (Hs-mode)
1000
5000
3400
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Electrical characteristics
1. Hs-mode is only supported in slave mode.
2. The maximum SCL clock frequency in Fast mode with maximum bus loading (400pF) can only be achieved with
appropriate pull-up devices on the bus when using the high or normal drive pins across the full voltage range . The
maximum SCL clock frequency in Fast mode Plus can support maximum bus loading (400pF) with appropriate pull-up
devices when using the high drive pins. The maximum SCL clock frequency in Ultra Fast mode can support maximum
bus loading (400pF) when using the high drive pins. The maximum SCL clock frequency for slave in High speed mode
can support maximum bus loading (400pF) with appropriate pull-up devices when using the high drive pins. For more
information on the required pull-up devices, see I2C Bus Specification.
3. See the section "General switching specifications".
5.4.6.4 Modular/Scalable Controller Area Network (MSCAN)
Table 56. MSCAN Timing Parameters
Characteristic
Baud Rate
Symbol
BRCAN
Min
—
—
5
Max
1
Unit
Mbit/s
µs
CAN Wakeup dominant pulse filtered
CAN Wakeup dominant pulse pass
TWAKEUP
TWAKEUP
1.5
—
µs
CAN_RX
CAN receive
data pin
T
WAKEUP
(Input)
Figure 22. Bus Wake-up Detection
5.4.7 Human-machine interfaces (HMI)
5.4.7.1 Touch sensing input (TSI) electrical specifications
Table 57. TSI electrical specifications
Symbol
Description
Value
Typ
Unit
Min
Max
IDD_EN
Power
consumption in
operation mode
—
500
600
µA
nA
IDD_DIS
Power
—
20
355
consumption in
disable mode
VBG
VPRE
CI
Internal bandgap
reference voltage
—
—
—
1.21
1.51
90
—
—
—
V
V
Internal bias
voltage
Internal integration
capacitance
pF
Table continues on the next page...
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Electrical characteristics
Table 57. TSI electrical specifications (continued)
Symbol
Description
Value
Typ
16
Unit
Min
Max
FCLK
Internal main clock
frequency
—
—
MHz
5.4.8 Debug modules
5.4.8.1 SWD electricals
Table 58. SWD full voltage range electricals
Symbol
VDDA
S1
Description
Min.
Max.
5.5
25
—
Unit
V
Operating voltage
2.7
0
SWD_CLK frequency of operation
SWD_CLK cycle period
MHz
ns
S2
1/S1
15
—
S3
SWD_CLK clock pulse width
—
ns
S4
SWD_CLK rise and fall times
3
ns
S9
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
8
—
ns
S10
S11
S12
1.4
—
—
ns
25
—
ns
5
ns
S2
S4
S3
S3
SWD_CLK (input)
S4
Figure 23. Serial wire clock input timing
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Design considerations
SWD_CLK
S9
S10
Input data valid
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
S11
Output data valid
S12
S11
Output data valid
Figure 24. Serial wire data timing
6 Design considerations
6.1 Hardware design considerations
This device contains protective circuitry to guard against damage due to high static
voltage or electric fields. However, take normal precautions to avoid application of any
voltages higher than maximum-rated voltages to this high-impedance circuit.
6.1.1 Printed circuit board recommendations
• Place connectors or cables on one edge of the board and do not place digital circuits
between connectors.
• Drivers and filters for I/O functions must be placed as close to the connectors as
possible. Connect TVS devices at the connector to a good ground. Connect filter
capacitors at the connector to a good ground. Consider to add ferrite bead or
inductor to some sensitive lines.
• Physically isolate analog circuits from digital circuits if possible.
74
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NXP Semiconductors
Design considerations
• Place input filter capacitors as close to the MCU as possible.
• For best EMC performance, route signals as transmission lines; use a ground
plane directly under LQFP packages; and solder the exposed pad (EP) to ground
directly under QFN packages.
6.1.2 Power delivery system
Consider the following items in the power delivery system:
• Use a plane for ground.
• Use a plane for MCU VDD supply if possible.
• Always route ground first, as a plane or continuous surface, and never as
sequential segments.
• Always route the power net as star topology, and make each power trace loop as
minimum as possible.
• Route power next, as a plane or traces that are parallel to ground traces.
• Place bulk capacitance, 10 μF or more, at the entrance of the power plane.
• Place bypass capacitors for MCU power domain as close as possible to each
VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.
• The minimum bypass requirement is to place 0.1 μF capacitors positioned as near
as possible to the package supply pins.
6.1.3 Analog design
Each ADC input must have an RC filter as shown in the following figure. The
maximum value of R must be RAS max if fast sampling and high resolution are
required. The value of C must be chosen to ensure that the RC time constant is very
small compared to the sample period.
MCU
1
2
Input signal
ADCx
R
C
Figure 25. RC circuit for ADC input
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NXP Semiconductors
Design considerations
High voltage measurement circuits require voltage division, current limiting, and over-
voltage protection as shown the following figure. The voltage divider formed by R1 –
R4 must yield a voltage less than or equal to VREFH. The current must be limited to
less than the injection current limit. External clamp diodes can be added here to protect
against transient over-voltages.
MCU
R1
R2
R3
VDD
1
1
1
2
2
2
R5
1
2
ADCx
High voltage input
R4
1
2
C
BAT54SW
Figure 26. High voltage measurement with an ADC input
NOTE
For more details of ADC related usage, refer to AN5250:
How to Increase the Analog-to-Digital Converter Accuracy in
an Application.
6.1.4 Digital design
Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V).
CAUTION
Do not provide power to I/O pins prior to VDD, especially the
RESET_b pin.
• RESET_b pin
The RESET_b pin is a pseudo open-drain I/O pin that has an internal pullup
resistor. An external RC circuit is recommended to filter noise as shown in the
following figure. The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the
recommended capacitance value is 0.1 μF. The RESET_b pin also has a selectable
digital filter to reject spurious noise.
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Design considerations
VDD
MCU
10k
RESET_b
RESET_b
0.1uF
Figure 27. Reset circuit
When an external supervisor chip is connected to the RESET_b pin, a series
resistor must be used to avoid damaging the supervisor chip or the RESET_b pin,
as shown in the following figure. The series resistor value (RS below) must be in
the range of 100 Ω to 1 kΩ depending on the external reset chip drive strength.
The supervisor chip must have an active high, open-drain output.
VDD
Supervisor Chip
MCU
10k
1
2
OUT
RESET_b
RS
Active high,
open drain
0.1uF
Figure 28. Reset signal connection to external reset chip
• NMI pin
Do not add a pull-down resistor or capacitor on the NMI_b pin, because a low
level on this pin will trigger non-maskable interrupt. When this pin is enabled as
the NMI function, an external pull-up resistor (10 kΩ) as shown in the following
figure is recommended for robustness.
If the NMI_b pin is used as an I/O pin, the non-maskable interrupt handler is
required to disable the NMI function by remapping to another function. The NMI
function is disabled by programming the FOPT[NMI_DIS] bit to zero.
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NXP Semiconductors
Design considerations
VDD
MCU
10k
NMI_b
Figure 29. NMI pin biasing
• Debug interface
This MCU uses the standard ARM SWD interface protocol as shown in the
following figure. While pull-up or pull-down resistors are not required (SWD_DIO
has an internal pull-up and SWD_CLK has an internal pull-down), external 10 kΩ
pull resistors are recommended for system robustness. The RESET_b pin
recommendations mentioned above must also be considered.
VDD
10k
VDD
J1
SWD_DIO
SWD_CLK
1
3
5
7
9
2
4
6
8
RESET_b
10k
10
0.1uF
HDR_5X2
Figure 30. SWD debug interface
• Unused pin
Unused GPIO pins must be left floating (no electrical connections) with the MUX
field of the pin’s PORTx_PCRn register equal to 0:0:0. This disables the digital
input path to the MCU.
78
NXP Semiconductors
Kinetis KE1xZ with up to 64 KB Flash, Rev. 3, 06/2020
Design considerations
6.1.5 Crystal oscillator
When using an external crystal or ceramic resonator as the frequency reference for the
MCU clock system, refer to the following table and diagrams.
The feedback resistor, RF, is incorporated internally with the low power oscillators.
An external feedback is required when using high gain (HGO=1) mode.
The series resistor, RS, is required in high gain (HGO=1) mode when the crystal or
resonator frequency is below 2 MHz. Otherwise, the low power oscillator (HGO=0)
must not have any series resistance; and the high frequency, high gain oscillator with a
frequency above 2 MHz does not require any series resistance.
Table 59. External crystal/resonator connections
Oscillator mode
Low frequency (32.768 kHz), high gain
High frequency (1-32 MHz), low power
High frequency (1-32 MHz), high gain
Oscillator mode
Diagram 3
Diagram 2
Diagram 3
OSCILLATOR
EXTAL
OSCILLATOR
XTAL
EXTAL
XTAL
1
2
1
3
CRYSTAL
Cx
Cy
RESONATOR
Figure 31. Crystal connection – Diagram 2
OSCILLATOR
EXTAL
OSCILLATOR
EXTAL
XTAL
XTAL
1
2
1
2
RF
RF
RS
RS
1
2
1
3
CRYSTAL
Cx
Cy
RESONATOR
Figure 32. Crystal connection – Diagram 3
NOTE
For PCB layout, the user could consider to add the guard
ring to the crystal oscillator circuit.
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NXP Semiconductors
Part identification
6.2 Software considerations
All Kinetis MCUs are supported by comprehensive NXP and third-party hardware and
software enablement solutions, which can reduce development costs and time to market.
Featured software and tools are listed below. Visit http://www.nxp.com/kinetis/sw for
more information and supporting collateral.
Evaluation and Prototyping Hardware
• Freedom Development Platform: http://www.nxp.com/freedom
IDEs for Kinetis MCUs
• MCUXpresso IDE: https://www.nxp.com/support/developer-resources/software-
development-tools/mcuxpresso-software-and-tools/mcuxpresso-integrated-
development-environment-ide:MCUXpresso-IDE
• Partner IDEs: http://www.nxp.com/kide
Run-time Software
• MCUXpresso Software Development Kit (SDK): https://www.nxp.com/support/
developer-resources/software-development-tools/mcuxpresso-software-and-tools/
mcuxpresso-software-development-kit-sdk:MCUXpresso-SDK
For all other partner-developed software and tools, visit http://www.nxp.com/partners.
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q KE## A FFF R T PP CC N
80
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Revision history
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 60. Part number fields description
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
KE##
A
Kinetis family
Key attribute
• KE16, KE15, KE14
• Z = Cortex-M0+
FFF
Program flash memory size
• 32 = 32 KB
• 64 = 64 KB
R
Silicon revision
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
PP
• LD = 44 LQFP (10 mm x 10 mm)
• LF = 48 LQFP (7 mm x 7 mm)
• FP = 40 QFN (5 mm x 5 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 4 = 48 MHz
• R = Tape and reel
• (Blank) = Trays
7.4 Example
This is an example part number:
MKE16Z64VLF4
8 Revision history
The following table provides a revision history for this document.
Table 61. Revision history
Rev. No.
Date
Substantial Changes
2
3
01/2019
06/2020
Initial public release.
40-QFN new package is added. Related sections (Ordering information, Pinout, Package,
Power consumption, Thermal characteristics, etc.) are updated.
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81
NXP Semiconductors
Information in this document is provided solely to enable system and software implementers to use
NXP products. There are no express or implied copyright licenses granted hereunder to design or
fabricate any integrated circuits based on the information in this document. NXP reserves the right to
make changes without further notice to any products herein.
How to Reach Us:
Home Page:
nxp.com
Web Support:
nxp.com/support
NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any
particular purpose, nor does NXP assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without limitation
consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets
and/or specifications can and do vary in different applications, and actual performance may vary over
time. All operating parameters, including "typicals," must be validated for each customer application
by customer's technical experts. NXP does not convey any license under its patent rights nor the
rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be
found at the following address: nxp.com/SalesTermsandConditions.
While NXP has implemented advanced security features, all products may be subject to unidentified
vulnerabilities. Customers are responsible for the design and operation of their applications and
products to reduce the effect of these vulnerabilities on customer's applications and products, and
NXP accepts no liability for any vulnerability that is discovered. Customers should implement
appropriate design and operating safeguards to minimize the risks associated with their applications
and products.
NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER WORLD, COOLFLUX,
EMBRACE, GREENCHIP, HITAG, I2C BUS, ICODE, JCOP, LIFE VIBES, MIFARE, MIFARE
CLASSIC, MIFARE DESFire, MIFARE PLUS, MIFARE FLEX, MANTIS, MIFARE ULTRALIGHT,
MIFARE4MOBILE, MIGLO, NTAG, ROADLINK, SMARTLX, SMARTMX, STARPLUG, TOPFET,
TRENCHMOS, UCODE, Freescale, the Freescale logo, AltiVec, C‑5, CodeTEST, CodeWarrior,
ColdFire, ColdFire+, C‑Ware, the Energy Efficient Solutions logo, Kinetis, Layerscape, MagniV,
mobileGT, PEG, PowerQUICC, Processor Expert, QorIQ, QorIQ Qonverge, Ready Play, SafeAssure,
the SafeAssure logo, StarCore, Symphony, VortiQa, Vybrid, Airfast, BeeKit, BeeStack, CoreNet,
Flexis, MXC, Platform in a Package, QUICC Engine, SMARTMOS, Tower, TurboLink, UMEMS, eIQ,
Immersiv3D, EdgeLock, and EdgeScale are trademarks of NXP B.V. All other product or service
names are the property of their respective owners. AMBA, Arm, Arm7, Arm7TDMI, Arm9, Arm11,
Artisan, big.LITTLE, Cordio, CoreLink, CoreSight, Cortex, DesignStart, DynamIQ, Jazelle, Keil, Mali,
Mbed, Mbed Enabled, NEON, POP, RealView, SecurCore, Socrates, Thumb, TrustZone, ULINK,
ULINK2, ULINK-ME, ULINK-PLUS, ULINKpro, µVision, Versatile are trademarks or registered
trademarks of Arm Limited (or its subsidiaries) in the US and/or elsewhere. The related technology
may be protected by any or all of patents, copyrights, designs and trade secrets. All rights reserved.
Oracle and Java are registered trademarks of Oracle and/or its affiliates. The Power Architecture and
Power.org word marks and the Power and Power.org logos and related marks are trademarks and
service marks licensed by Power.org.
© 2018–2020 NXP B.V.
Document Number KE1xZP48M48SF0
Revision 3, 06/2020
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