MKL02Z16VFG4 [NXP]
Kinetis KL02 32 KB Flash;
| 型号： | MKL02Z16VFG4 |
| 厂家： | 
NXP |
| 描述： | Kinetis KL02 32 KB Flash |
| 文件： | 总48页 (文件大小：997K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NXP Semiconductors
Data Sheet: Technical Data
Document Number: KL02P32M48SF0
Rev. 5 08/2017
Kinetis KL02 32 KB Flash
MKL02ZxxVFG4
MKL02ZxxVFK4
MKL02ZxxVFM4
48 MHz Cortex-M0+ Based Microcontroller
Designed with efficiency in mind. Features a size efficient, ultra-
small package, energy efficient ARM Cortex-M0+ 32-bit
performance. Shares the comprehensive enablement and
scalability of the Kinetis family.
16-pin QFN (FG)
24-pin QFN (FK)
3 x 3 x 0.65 Pitch 0.5
4 x 4 x 1 Pitch 0.5 mm
mm
This product offers:
• Run power consumption down to 36 μA/MHz in very low
power run mode
• Static power consumption down to 2 μA with full state
retention and 4 μs wakeup
• Ultra-efficient Cortex-M0+ processor running up to 48 MHz
with industry leading throughput
• Memory option is up to 32 KB flash and 4 KB RAM
• Energy-saving architecture is optimized for low power with
90nm TFS technology, clock and power gating techniques,
and zero wait state flash memory controller
32-pin QFN (FM)
5 x 5 x 1 Pitch 0.5 mm
Performance
• 48 MHz ARM® Cortex®-M0+ core
Human-machine interface
• Up to 28 general-purpose input/output (GPIO)
Memories and memory interfaces
• Up to 32 KB program flash memory
• Up to 4 KB SRAM
Communication interfaces
• One 8-bit SPI module
• One low power UART module
• Two I2C module
System peripherals
• Nine low-power modes to provide power optimization
based on application requirements
• COP Software watchdog
• SWD debug interface and Micro Trace Buffer
• Bit Manipulation Engine
Analog Modules
• 12-bit SAR ADC
• Analog comparator (CMP) containing a 6-bit DAC
and programmable reference input
Timers
Clocks
• Two 2-channel Timer/PWM modules
• 16-bit low-power timer (LPTMR)
• 32 kHz to 40 kHz crystal oscillator
• Multi-purpose clock source
• 1 kHz LPO clock
Security and integrity modules
• 80-bit unique identification number per chip
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Ordering Information 1
Part Number
Memory
Maximum number of I\O's
Flash (KB)
SRAM (KB)
MKL02Z8VFG4
MKL02Z16VFG4
MKL02Z32VFG4
MKL02Z16VFK4
MKL02Z32VFK4
MKL02Z16VFM4
MKL02Z32VFM4
8
1
2
4
2
4
2
4
14
14
14
22
22
28
28
16
32
16
32
16
32
1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search.
Related Resources
Type
Description
Resource
Solution Advisor
Selector Guide The NXP Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Product Brief
The Product Brief contains concise overview/summary information to KL0XPB1
enable quick evaluation of a device for design suitability.
Reference
Manual
The Reference Manual contains a comprehensive description of the KL02P32M48SF0RM1
structure and function (operation) of a device.
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
KL02P32M48SF01
Chip Errata
The chip mask set Errata provides additional or corrective
information for a particular device mask set.
KINETIS_L_xN33H2
Package
drawing
Package dimensions are provided in package drawings.
QFN 16-pin: 98ASA00525D1
QFN 24-pin: 98ASA00474D1
QFN 32-pin: 98ASA00473D1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
2. To find the associated resource, go to http://www.nxp.com and perform a search using this term with the “x” replaced by
the revision of the device you are using.
Figure 1 shows the functional modules in the chip.
2
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NXP Semiconductors
Kinetis KL02 Family
System
Clocks
Memories and
Memory Interfaces
ARM Cortex-M0+
Core
Internal
watchdog
Frequency-
locked loop
Debug
interfaces
Program
flash
Low
BME
frequency
oscillator
Interrupt
RAM
controller
Internal
reference
clocks
MTB
Security
and Integrity
Analog
Communication Human-Machine
Timers
Interfaces
Interface (HMI)
Internal
watchdog
Timers
2x2ch
12-bit ADC
x1
GPIOs
with
I2C
x2
interrupt
Analog
comparator
x1
Low Power
Timer
Low power
UART
x1
6-bit DAC
SPI
x1
Figure 1. Functional block diagram
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NXP Semiconductors
Table of Contents
1
2
Ratings..................................................................................5
3.6 Analog............................................................................24
3.6.1 ADC electrical specifications............................. 24
3.6.2 CMP and 6-bit DAC electrical specifications..... 27
3.7 Timers............................................................................29
3.8 Communication interfaces............................................. 29
3.8.1 SPI switching specifications.............................. 29
3.8.2 Inter-Integrated Circuit Interface (I2C) timing.... 33
3.8.3 UART.................................................................35
Dimensions........................................................................... 35
4.1 Obtaining package dimensions......................................35
Pinout....................................................................................36
5.1 KL02 signal multiplexing and pin assignments..............36
5.2 KL02 pinouts..................................................................37
Ordering parts....................................................................... 40
6.1 Determining valid orderable parts..................................40
Part identification...................................................................40
7.1 Description.....................................................................40
7.2 Format........................................................................... 41
7.3 Fields............................................................................. 41
7.4 Example.........................................................................41
Small package marking.........................................................42
Terminology and guidelines.................................................. 42
9.1 Definition: Operating requirement..................................42
9.2 Definition: Operating behavior....................................... 43
9.3 Definition: Attribute........................................................ 43
9.4 Definition: Rating........................................................... 43
9.5 Result of exceeding a rating.......................................... 44
9.6 Relationship between ratings and operating
1.1 Thermal handling ratings............................................... 5
1.2 Moisture handling ratings...............................................5
1.3 ESD handling ratings.....................................................5
1.4 Voltage and current operating ratings............................5
General................................................................................. 6
2.1 AC electrical characteristics...........................................6
2.2 Nonswitching electrical specifications............................6
2.2.1 Voltage and current operating requirements..... 7
2.2.2 LVD and POR operating requirements..............7
2.2.3 Voltage and current operating behaviors...........8
2.2.4 Power mode transition operating behaviors...... 9
2.2.5 Power consumption operating behaviors.......... 10
2.2.6 EMC radiated emissions operating behaviors... 15
2.2.7 EMC Radiated Emissions Web Search
4
5
6
7
Procedure boilerplate........................................ 16
2.2.8 Capacitance attributes.......................................16
2.3 Switching specifications.................................................16
2.3.1 Device clock specifications................................16
2.3.2 General switching specifications....................... 17
2.4 Thermal specifications...................................................17
2.4.1 Thermal operating requirements....................... 17
2.4.2 Thermal attributes..............................................17
Peripheral operating requirements and behaviors................ 18
3.1 Core modules................................................................ 18
3.1.1 SWD electricals ................................................ 18
3.2 System modules............................................................ 20
3.3 Clock modules............................................................... 20
3.3.1 MCG specifications............................................20
3.3.2 Oscillator electrical specifications......................21
3.4 Memories and memory interfaces................................. 22
3.4.1 Flash electrical specifications............................ 22
3.5 Security and integrity modules.......................................24
8
9
3
requirements..................................................................44
9.7 Guidelines for ratings and operating requirements........45
9.8 Definition: Typical value.................................................45
9.9 Typical value conditions.................................................46
10 Revision history.....................................................................47
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NXP Semiconductors
Ratings
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
Symbol
VHBM
Description
Min.
–2000
–500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
ILAT
Latch-up current at ambient temperature of 105 °C
–100
+100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
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NXP Semiconductors
General
1.4 Voltage and current operating ratings
Table 4. Voltage and current operating ratings
Symbol
VDD
IDD
Description
Min.
–0.3
—
Max.
3.8
Unit
V
Digital supply voltage
Digital supply current
IO pin input voltage
120
mA
V
VIO
–0.3
–25
VDD + 0.3
25
ID
Instantaneous maximum current single pin limit (applies to
all port pins)
mA
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume the output
pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
2.2 Nonswitching electrical specifications
6
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NXP Semiconductors
General
2.2.1 Voltage and current operating requirements
Table 5. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
1.71
–0.1
–0.1
Max.
3.6
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
3.6
V
—
—
—
—
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
0.1
V
0.1
V
VIH
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
—
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICIO
Input hysteresis
0.06 × VDD
–3
—
—
V
—
1
IO pin negative DC injection current—single pin
• VIN < VSS–0.3V
mA
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
—
–25
—
mA
• Negative current injection
VODPU
VRAM
Open drain pullup voltage level
VDD
1.2
VDD
—
V
V
2
VDD voltage required to retain RAM
—
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD
.
2.2.2 LVD and POR operating requirements
Table 6. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
—
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48
2.56
2.64
V
—
Low-voltage warning thresholds — high range
1
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NXP Semiconductors
General
Table 6. VDD supply LVD and POR operating requirements (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VLVW1H
VLVW2H
VLVW3H
VLVW4H
• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11)
2.62
2.70
2.78
V
2.72
2.82
2.92
2.80
2.90
3.00
2.88
2.98
3.08
V
V
V
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
60
—
mV
V
—
—
1
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV = 00)
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
—
1.80
1.90
2.00
2.10
40
1.86
1.96
2.06
2.16
—
V
V
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
V
• Level 4 falling (LVWV = 11)
V
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
mV
—
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
—
—
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 7. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
VOH
Output high voltage — Normal drive pad (except
RESET)
1, 2
VDD – 0.5
VDD – 0.5
—
—
V
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –2.5 mA
VOH
Output high voltage — High drive pad (except
RESET)
1, 2
VDD – 0.5
VDD – 0.5
—
—
V
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –10 mA
IOHT
VOL
Output high current total for all ports
Output low voltage — Normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
—
100
mA
—
1
—
—
0.5
0.5
V
V
Table continues on the next page...
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NXP Semiconductors
General
Table 7. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
Notes
VOL
Output low voltage — High drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
1
—
—
—
—
0.5
0.5
100
1
V
V
IOLT
IIN
Output low current total for all ports
mA
μA
—
3
Input leakage current (per pin) for full temperature
range
IIN
IIN
Input leakage current (per pin) at 25 °C
—
—
0.025
41
μA
μA
3
3
Input leakage current (total all pins) for full
temperature range
IOZ
Hi-Z (off-state) leakage current (per pin)
Internal pullup resistors
—
1
μA
kΩ
—
4
RPU
20
50
1. PTA12, PTA13, PTB0 and PTB1 I/O have both high drive and normal drive capability selected by the associated
PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
3. Measured at VDD = 3.6 V
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• FEI clock mode
POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system
frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.
Table 8. Power mode transition operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
tPOR
After a POR event, amount of time from the
—
—
300
μs
1
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
• VLLS0 → RUN
—
95
115
μs
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NXP Semiconductors
General
Table 8. Power mode transition operating behaviors (continued)
Symbol Description
• VLLS1 → RUN
Min.
Typ.
Max.
Unit
—
93
115
μs
• VLLS3 → RUN
• VLPS → RUN
• STOP → RUN
—
—
—
42
4
53
4.4
4.4
μs
μs
μs
4
1. Normal boot (FTFA_FOPT[LPBOOT]=11).
2.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
Table 9. Power consumption operating behaviors
Symbol
IDDA
Description
Temp.
—
Typ.
—
Max
See note
4
Unit
mA
mA
Note
Analog supply current
1
2
IDD_RUNCO
Run mode current in compute operation -
48 MHz core / 24 MHz flash / bus clock
disabled, code of while(1) loop executing
from flash, at 3.0 V
—
3.6
IDD_RUN
Run mode current - 48 MHz core / 24 MHz
bus and flash, all peripheral clocks
disabled, code executing from flash, at 3.0
V
—
4.3
4.6
mA
2
2, 3
2
IDD_RUN
Run mode current - 48 MHz core / 24 MHz
bus and flash, all peripheral clocks
enabled, code executing from flash, at 3.0
V
at 25 °C
4.8
5
5
mA
mA
at 125 °C
5.2
IDD_WAIT
IDD_WAIT
IDD_PSTOP2
Wait mode current - core disabled / 48 MHz
system / 24 MHz bus / flash disabled (flash
doze enabled), all peripheral clocks
disabled, at 3.0 V
—
—
—
2.3
1.8
1.3
2.6
2.1
1.5
mA
mA
mA
Wait mode current - core disabled / 24 MHz
system / 24 MHz bus / flash disabled (flash
doze enabled), all peripheral clocks
disabled, at 3.0 V
2
Stop mode current with partial stop 2
clocking option - core and system
disabled / 10.5 MHz bus, at 3.0 V
2
Table continues on the next page...
10
NXP Semiconductors
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
General
Table 9. Power consumption operating behaviors (continued)
Symbol
Description
Temp.
Typ.
Max
Unit
Note
IDD_VLPRCO
Very low power run mode current in
compute operation - 4 MHz core / 0.8 MHz
flash / bus clock disabled, code executing
from flash, at 3.0 V
—
145
198
µA
4
IDD_VLPR
IDD_VLPR
IDD_VLPW
IDD_STOP
Very low power run mode current - 4 MHz
core / 0.8 MHz bus and flash, all peripheral
clocks disabled, code executing from flash,
at 3.0 V
—
—
—
165
185
86
217
237
141
µA
µA
µA
4
3, 4
4
Very low power run mode current - 4 MHz
core / 0.8 MHz bus and flash, all peripheral
clocks enabled, code executing from flash,
at 3.0 V
Very low power wait mode current - core
disabled / 4 MHz system / 0.8 MHz bus /
flash disabled (flash doze enabled), all
peripheral clocks disabled, at 3.0 V
Stop mode current at 3.0 V
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C
230
238
268
301
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
—
259
307
290
352
341
437
IDD_VLPS
IDD_VLLS3
IDD_VLLS1
IDD_VLLS0
Very-low-power stop mode current at 3.0 V
2.3
4.28
8.29
17.63
33.55
64.75
1.33
2.12
3.57
6.45
13.59
0.69
1.04
2.02
4.05
9.42
0.4
—
—
—
—
4.75
10.1
20.23
40.54
1.12
1.59
2.81
5.26
10.82
0.58
0.9
Very low-leakage stop mode 3 current at
3.0 V
Very low-leakage stop mode 1 current at
3.0 V
1.68
3.51
7.89
0.3
Very low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 0) at 3.0 V
0.62
1.38
3.16
7.44
0.75
1.71
3.71
8.98
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NXP Semiconductors
General
Table 9. Power consumption operating behaviors (continued)
Symbol
IDD_VLLS0
Description
Temp.
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C
Typ.
0.12
0.44
1.21
3.01
7.34
Max
0.23
0.58
1.55
3.57
8.89
Unit
µA
µA
µA
µA
µA
Note
Very low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 1) at 3.0 V
5
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. MCG configured for FEI mode.
3. Incremental current consumption from peripheral activity is not included.
4. MCG configured for BLPI mode.
5. No brownout.
Table 10. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz
4 MHz internal reference clock (IRC) adder.
Measured by entering STOP or VLPS mode
with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
IIREFSTEN32KHz
32 kHz internal reference clock (IRC) adder.
Measured by entering STOP mode with the
32 kHz IRC enabled.
52
52
52
52
52
52
µA
nA
IEREFSTEN32KHz
External 32 kHz crystal clock
adder by means of the
OSC0_CR[EREFSTEN and
EREFSTEN] bits. Measured
by entering all modes with the
crystal enabled.
VLLS1
VLLS3
VLPS
440
440
510
510
490
490
560
560
540
540
560
560
560
560
560
560
570
570
610
610
580
580
680
680
STOP
ICMP
CMP peripheral adder measured by placing
the device in VLLS1 mode with CMP enabled
using the 6-bit DAC and a single external
input for compare. Includes 6-bit DAC power
consumption.
22
22
22
22
22
22
µA
µA
IUART
UART peripheral adder
measured by placing the
device in STOP or VLPS
mode with selected clock
source waiting for RX data at
115200 baud rate. Includes
selected clock source power
consumption.
MCGIRCLK
(4 MHz
internal
reference
clock)
66
66
66
66
66
66
ITPM
TPM peripheral adder
MCGIRCLK
(4 MHz
internal
reference
clock)
86
86
86
86
86
86
µA
measured by placing the
device in STOP or VLPS
mode with selected clock
source configured for output
compare generating 100 Hz
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12
NXP Semiconductors
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
General
Table 10. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
clock signal. No load is
placed on the I/O generating
the clock signal. Includes
selected clock source and I/O
switching currents.
OSCERCLK
(4 MHz
external
crystal)
235
256
265
274
280
287
IBG
Bandgap adder when BGEN bit is set and
device is placed in VLPx, or VLLSx mode.
45
45
45
45
45
45
µA
µA
IADC
ADC peripheral adder combining the
366
366
366
366
366
366
measured values at VDD and VDDA by placing
the device in STOP or VLPS mode. ADC is
configured for low power mode using the
internal clock and continuous conversions.
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE for run mode, and BLPE for VLPR mode
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
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NXP Semiconductors
General
Run Mode Current VS Core Frequency
Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE
7.00E-03
6.00E-03
5.00E-03
4.00E-03
3.00E-03
2.00E-03
1.00E-03
000.00E+00
All Peripheral CLK Gates
All Off
All On
CLK Ratio
'1-1
1
'1-1
2
'1-1
3
'1-1
4
'1-1
6
'1-1
12
'1-1
24
'1-2
48
Flash-Core
Core Freq (MHz)
Figure 3. Run mode supply current vs. core frequency
14
NXP Semiconductors
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
General
VLPR Mode Current VS Core Frequency
Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = BLPE
350.00E-06
300.00E-06
250.00E-06
200.00E-06
150.00E-06
100.00E-06
50.00E-06
All Peripheral CLK Gates
All Off
All On
000.00E+00
CLK Ratio
'1-1
'1-2
'1-2
'1-4
Flash-Core
1
2
4
Core Freq (MHz)
Figure 4. VLPR mode current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 11. EMC radiated emissions operating behaviors for 32-pin QFN package
Symbol
Description
Frequency
band
Typ.
Unit
Notes
(MHz)
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC level
0.15–50
50–150
7
6
4
4
N
dBμV
dBμV
dBμV
dBμV
—
1, 2
VRE3
150–500
500–1000
0.15–1000
VRE4
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions,
150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits -
Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM
Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic
application code. The reported emission level is the value of the maximum measured emission, rounded up to the next
whole number, from among the measured orientations in each frequency range.
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
15
NXP Semiconductors
General
2. VDD = 3.3 V, TA = 25 °C, fOSC = 32.768 kHz (crystal), fSYS = 48 MHz, fBUS = 24 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 EMC Radiated Emissions Web Search Procedure boilerplate
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for "EMC design"
2.2.8 Capacitance attributes
Table 12. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN
Input capacitance
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 13. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Normal run mode
fSYS
fBUS
fFLASH
fLPTMR
System and core clock
Bus clock
—
—
—
—
48
24
24
24
MHz
MHz
MHz
MHz
Flash clock
LPTMR clock
VLPR and VLPS modes1
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
—
—
—
4
MHz
MHz
MHz
MHz
kHz
1
1
fFLASH
fLPTMR
fERCLK
Flash clock
LPTMR clock2
24
External reference clock
32.768
16
fLPTMR_ERCLK LPTMR external reference clock
fTPM TPM asynchronous clock
MHz
MHz
8
Table continues on the next page...
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NXP Semiconductors
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
General
Table 13. Device clock specifications (continued)
Symbol
Description
UART0 asynchronous clock
Min.
Max.
Unit
fUART0
—
8
MHz
1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
2.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 14. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter disabled)
— Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
Port rise and fall time
16
—
—
ns
ns
2
3
36
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 15. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Notes
Die junction temperature
Ambient temperature
TA
105
°C
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + θJA × chip power dissipation.
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NXP Semiconductors
Peripheral operating requirements and behaviors
2.4.2 Thermal attributes
Table 16. Thermal attributes
Board type
Symbol
Description
16 QFN 24 QFN 32 QFN
Unit
Notes
Single-layer (1S)
RθJA
Thermal resistance, junction to
ambient (natural convection)
141
114
101
°C/W
1
Four-layer (2s2p)
RθJA
Thermal resistance, junction to
ambient (natural convection)
55
42
35
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Single-layer (1S)
RθJMA Thermal resistance, junction to
ambient (200 ft./min. air speed)
120
49
96
84
Four-layer (2s2p)
RθJMA Thermal resistance, junction to
ambient (200 ft./min. air speed)
36
30
—
—
—
RθJB
RθJC
ΨJT
Thermal resistance, junction to
board
27
19
15
2
3
4
Thermal resistance, junction to
case
20
3.4
15
3.4
11
Thermal characterization
parameter, junction to package
top outside center (natural
convection)
23
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 17. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
J1
SWD_CLK frequency of operation
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NXP Semiconductors
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Peripheral operating requirements and behaviors
Table 17. SWD full voltage range electricals (continued)
Symbol
Description
• Serial wire debug
Min.
Max.
25
Unit
0
MHz
J2
J3
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
1/J1
—
ns
20
—
ns
J4
J9
SWD_CLK rise and fall times
—
10
0
3
ns
ns
ns
ns
ns
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
—
32
—
J10
J11
J12
—
5
J2
J4
J3
J3
SWD_CLK (input)
J4
Figure 5. Serial wire clock input timing
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
J9
J10
Input data valid
J11
Output data valid
J12
J11
Output data valid
Figure 6. Serial wire data timing
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NXP Semiconductors
Peripheral operating requirements and behaviors
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 18. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
—
39.0625
0.6
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using C3[SCTRIM] and C4[SCFTRIM]
0.3
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
+0.5/-0.7
0.4
3
%fdco
%fdco
1, 2
1, 2
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70 °C
1.5
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25 °C
—
—
4
—
3
MHz
Δfintf_ft
Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
+1/-2
%fintf_ft
2
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
—
—
5
MHz
kHz
kHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
FLL
ffll_ref
fdco
FLL reference frequency range
31.25
20
—
39.0625
25
kHz
DCO output
Low range (DRS = 00)
20.97
MHz
3, 4
5, 6
frequency range
640 × ffll_ref
Mid range (DRS = 01)
1280 × ffll_ref
40
—
41.94
23.99
48
—
MHz
MHz
fdco_t_DMX3 DCO output
Low range (DRS = 00)
frequency
2
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NXP Semiconductors
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Peripheral operating requirements and behaviors
Table 18. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
732 × ffll_ref
Mid range (DRS = 01)
1464 × ffll_ref
—
47.97
—
MHz
Jcyc_fll
FLL period jitter
• fVCO = 48 MHz
—
—
180
—
—
1
ps
7
8
tfll_acquire FLL target frequency acquisition time
ms
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft
.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature must be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
3.3.2 Oscillator electrical specifications
3.3.2.1 Oscillator DC electrical specifications
Table 19. Oscillator DC electrical specifications
Symbol Description
VDD Supply voltage
Min.
Typ.
Max.
Unit
Notes
1.71
—
3.6
V
IDDOSC Supply current — low-power mode (HGO=0)
• 32 kHz
1
—
500
—
nA
μA
IDDOSC Supply current — high gain mode (HGO=1)
• 32 kHz
1
—
25
—
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
10
—
—
—
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
Table continues on the next page...
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21
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 19. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Series resistor — low-frequency, high-gain
—
200
—
kΩ
mode (HGO=1)
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
—
0.6
—
—
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using either the integrated capacitors or by using external components.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2 Oscillator frequency specifications
Table 20. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low
frequency mode (MCG_C2[RANGE]=00)
tdc_extal Input clock duty cycle (external clock mode)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
40
—
50
60
—
%
tcst
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
ms
1, 2
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
ms
1. Proper PC board layout procedures must be followed to achieve specifications.
2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
22
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
NXP Semiconductors
Peripheral operating requirements and behaviors
3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 21. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
13
Max.
18
Unit
μs
Notes
thvpgm4 Longword Program high-voltage time
thversscr Sector Erase high-voltage time
—
1
—
113
452
ms
ms
thversall
Erase All high-voltage time
—
52
1
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 22. Flash command timing specifications
Symbol Description
Min.
—
—
—
—
—
—
—
—
—
—
Typ.
—
Max.
60
Unit
μs
Notes
trd1sec1k Read 1s Section execution time (flash sector)
tpgmchk Program Check execution time
1
1
—
45
μs
trdrsrc
tpgm4
tersscr
trd1all
trdonce
Read Resource execution time
Program Longword execution time
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
30
μs
1
65
14
—
145
114
0.5
25
μs
—
2
ms
ms
μs
—
1
—
tpgmonce Program Once execution time
65
61
—
—
μs
—
2
tersall
Erase All Blocks execution time
500
30
ms
μs
tvfykey
Verify Backdoor Access Key execution time
1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3 Flash high voltage current behaviors
Table 23. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
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23
NXP Semiconductors
Peripheral operating requirements and behaviors
3.4.1.4 Reliability specifications
Table 24. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
—
—
2
20
100
50 K
10 K
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C.
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
All ADC channels meet the 12-bit single-ended accuracy specifications.
3.6.1.1 12-bit ADC operating conditions
Table 25. 12-bit ADC operating conditions
Symbol Description
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
VDDA
ΔVDDA
ΔVSSA
VREFH
Supply voltage
Supply voltage
Absolute
—
—
2
Delta to VDD (VDD – VDDA
)
0
+100
+100
VDDA
mV
mV
V
Ground voltage Delta to VSS (VSS – VSSA
)
0
2
ADC reference
voltage high
VDDA
3
VREFL
ADC reference
voltage low
VSSA
VSSA
VSSA
V
3
VADIN
CADIN
Input voltage
VREFL
—
—
4
VREFH
5
V
—
—
Input
capacitance
• 8-bit / 10-bit / 12-bit
modes
pF
RADIN
Input series
resistance
—
2
5
kΩ
—
Table continues on the next page...
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NXP Semiconductors
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
Peripheral operating requirements and behaviors
Table 25. 12-bit ADC operating conditions (continued)
Symbol Description
Conditions
12-bit modes
fADCK < 4 MHz
Min.
Typ.1
Max.
Unit
kΩ
Notes
RAS
Analog source
resistance
4
—
—
5
(external)
fADCK
Crate
ADC conversion ≤ 12-bit mode
clock frequency
1.0
—
18.0
MHz
5
6
ADC conversion ≤ 12-bit modes
rate
No ADC hardware averaging
20.000
—
818.330
Ksps
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied
to VSSA
.
4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 7. ADC input impedance equivalency diagram
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25
NXP Semiconductors
Peripheral operating requirements and behaviors
3.6.1.2 12-bit ADC electrical characteristics
Table 26. 12-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
6.1
7.3
9.5
Unit
mA
Notes
IDDA_ADC Supply current
—
3
ADC
asynchronous
clock source
• ADLPC = 1, ADHSC =
0
2.4
4.0
5.2
6.2
MHz
MHz
MHz
MHz
tADACK =
1/fADACK
2.4
• ADLPC = 1, ADHSC =
1
3.0
fADACK
4.4
• ADLPC = 0, ADHSC =
0
• ADLPC = 0, ADHSC =
1
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit modes
• <12-bit modes
• 12-bit modes
• <12-bit modes
—
—
—
—
0.7
0.2
1.0
0.5
–1.1 to
+1.9
–0.3 to 0.5
INL
Integral non-
linearity
–2.7 to
+1.9
LSB4
5
–0.7 to
+0.5
EFS
Full-scale error
• 12-bit modes
• <12-bit modes
• 12-bit modes
—
—
—
–4
–1.4
—
–5.4
–1.8
0.5
LSB4
VADIN
VDDA
=
5
EQ
EIL
Quantization
error
LSB4
mV
Input leakage
error
IIn × RAS
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
Across the full temperature
range of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
6
VTEMP25 Temp sensor
voltage
25 °C
6
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
26
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
NXP Semiconductors
Peripheral operating requirements and behaviors
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. ADC conversion clock < 3 MHz
Typical ADC 12-bit Single Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
11.9
11.8
11.7
11.6
11.5
11.4
11.3
11.2
11.1
11
10.9
10.8
10.7
10.6
10.5
10.4
10.3
Hardware Averaging Disabled
Averaging of 8 samples
10.2
10.1
10
Averaging of 32 samples
0
2
4
6
8
10
12
14
16
18
20
22
ADC Clock Frequency (MHz)
Figure 8. Typical ENOB vs. ADC_CLK for 12-bit single-ended mode
3.6.2 CMP and 6-bit DAC electrical specifications
Table 27. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
Supply current, High-speed mode (EN=1,
PMODE=1)
—
200
μA
IDDLS
VAIN
VAIO
VH
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
VSS – 0.3
—
—
—
—
20
VDD
20
μA
V
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
mV
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
• CR0[HYSTCTR] = 01
10
20
30
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
Output high
Output low
VDD – 0.5
—
—
—
—
V
V
0.5
Table continues on the next page...
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
27
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 27. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
tDHS
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
50
200
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
80
250
600
ns
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
—
—
—
7
40
—
μs
μA
LSB3
IDAC6b
INL
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
0.06
HYSTCTR
Setting
0.05
0.04
0.03
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
28
NXP Semiconductors
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
3.8.1 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master
and slave operations. Many of the transfer attributes are programmable. The following
tables provide timing characteristics for classic SPI timing modes. See the SPI chapter
of the chip's Reference Manual for information about the modified transfer formats
used for communicating with slower peripheral devices.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted,
as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
29
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 28. SPI master mode timing on slew rate disabled pads
Num.
Symbol Description
Min.
Max.
Unit
Hz
Note
1
2
fop
Frequency of operation
fperiph/2048
2 x tperiph
fperiph/2
1
2
tSPSCK
SPSCK period
2048 x
tperiph
ns
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph – 30
1024 x
tperiph
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
20
0
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
12
8
tv
—
0
9
tHO
tRI
—
10
—
tperiph – 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. For SPI0, fperiph is the bus clock (fBUS).
2. tperiph = 1/fperiph
Table 29. SPI master mode timing on slew rate enabled pads
Num.
Symbol Description
Min.
Max.
Unit
Hz
Note
1
2
fop
Frequency of operation
fperiph/2048
2 x tperiph
fperiph/2
1
2
tSPSCK
SPSCK period
2048 x
tperiph
ns
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph – 30
1024 x
tperiph
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
96
0
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
52
8
tv
—
0
9
tHO
tRI
—
10
—
tperiph – 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
36
ns
—
Fall time output
1. For SPI0, fperiph is the bus clock (fBUS).
2. tperiph = 1/fperiph
30
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
NXP Semiconductors
Peripheral operating requirements and behaviors
1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 11. SPI master mode timing (CPHA = 0)
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
LSB IN
MSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER MSB OUT
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 12. SPI master mode timing (CPHA = 1)
Table 30. SPI slave mode timing on slew rate disabled pads
Num.
Symbol Description
Min.
Max.
fperiph/4
—
Unit
Hz
Note
1
1
2
3
fop
Frequency of operation
0
4 x tperiph
1
tSPSCK
tLead
SPSCK period
ns
2
Enable lead time
—
tperiph
—
Table continues on the next page...
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
31
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 30. SPI slave mode timing on slew rate disabled pads (continued)
Num.
4
Symbol Description
tLag Enable lag time
tWSPSCK Clock (SPSCK) high or low time
Min.
Max.
—
Unit
tperiph
ns
Note
—
—
—
—
3
1
5
tperiph – 30
—
6
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
3
7
—
ns
7
—
ns
8
23
23
—
0
tperiph
tperiph
25.7
—
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
ns
—
tperiph – 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. For SPI0, fperiph is the bus clock (fBUS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
Table 31. SPI slave mode timing on slew rate enabled pads
Num.
1
Symbol Description
Min.
Max.
fperiph/4
—
Unit
Note
fop
tSPSCK
tLead
tLag
Frequency of operation
0
Hz
ns
1
2
SPSCK period
Enable lead time
Enable lag time
4 x tperiph
2
3
1
—
tperiph
tperiph
ns
—
—
—
—
—
3
4
1
—
5
tWSPSCK Clock (SPSCK) high or low time
tperiph – 30
—
6
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
2
7
—
ns
7
—
ns
8
—
—
—
0
tperiph
tperiph
122
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
—
ns
—
tperiph – 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
36
ns
—
Fall time output
1. For SPI0, fperiph is the bus clock (fBUS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
32
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
NXP Semiconductors
Peripheral operating requirements and behaviors
SS
(INPUT)
2
12
12
13
13
4
SPSCK
(CPOL=0)
(INPUT)
5
5
3
SPSCK
(CPOL=1)
(INPUT)
9
8
10
11
11
see
note
SEE
NOTE
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
6
MOSI
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
NOTE: Not defined
Figure 13. SPI slave mode timing (CPHA = 0)
SS
(INPUT)
4
2
12
12
13
13
3
SPSCK
(CPOL=0)
(INPUT)
5
5
SPSCK
(CPOL=1)
(INPUT)
11
9
10
SLAVE MSB OUT
see
note
MISO
(OUTPUT)
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
8
6
7
MOSI
(INPUT)
MSB IN
NOTE: Not defined
Figure 14. SPI slave mode timing (CPHA = 1)
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
33
NXP Semiconductors
Peripheral operating requirements and behaviors
3.8.2 Inter-Integrated Circuit Interface (I2C) timing
Table 32. I2C timing
Characteristic
Symbol
Standard Mode
Minimum Maximum
1001
Fast Mode
Unit
Minimum
Maximum
4002
SCL Clock Frequency
fSCL
0
0
kHz
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.25
0.6
—
—
—
µs
µs
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
0.6
Data hold time for I2C bus devices
tHD; DAT
tSU; DAT
tr
03
2506
—
3.454
—
05
1004, 7
20 +0.1Cb
20 +0.1Cb
0.6
0.93
—
µs
ns
ns
ns
µs
µs
Data set-up time
8
7
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
1000
300
—
300
300
—
tf
—
tSU; STO
tBUF
4
Bus free time between STOP and
START condition
4.7
—
1.3
—
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The PTB3 and PTB4 pins can support only the Standard mode.
2. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can be achieved only when using the
normal drive pins and VDD ≥ 2.7 V.
3. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
4. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
5. Input signal Slew = 10 ns and Output Load = 50 pF
6. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
7. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU;
DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
8. Cb = total capacitance of the one bus line in pF.
Table 33. I 2C 1Mbit/s timing
Characteristic
Symbol
fSCL
Minimum
Maximum
Unit
MHz
µs
SCL Clock Frequency
0
11
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA
0.26
—
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
0.5
0.26
0.26
0
—
—
—
—
µs
µs
µs
µs
Set-up time for a repeated START condition
Data hold time for I2C bus devices
tSU; STA
tHD; DAT
Table continues on the next page...
34
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
NXP Semiconductors
Dimensions
Table 33. I 2C 1Mbit/s timing (continued)
Characteristic
Data set-up time
Symbol
Minimum
50
Maximum
Unit
ns
tSU; DAT
—
120
120
—
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
Bus free time between STOP and START condition
tr
tf
20 +0.1Cb
ns
2
20 +0.1Cb
ns
tSU; STO
tBUF
tSP
0.26
0.5
0
µs
—
µs
Pulse width of spikes that must be suppressed by
the input filter
50
ns
1. The maximum SCL clock frequency of 1 Mbit/s can support 200 pF bus loading when using the normal drive pins and
VDD ≥ 2.7 V.
2. Cb = total capacitance of the one bus line in pF.
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tSU; STO
HD; STA
S
SR
P
S
tHD; DAT
tHIGH
Figure 15. Timing definition for devices on the I2C bus
3.8.3 UART
See General switching specifications.
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
35
NXP Semiconductors
Pinout
If you want the drawing for this package
Then use this document number
98ASA00525D
16-pin QFN
24-pin QFN
32-pin QFN
98ASA00474D
98ASA00473D
5 Pinout
5.1 KL02 signal multiplexing and pin assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
NOTE
PTB3 and PTB4 are true open drain pins. To use these pins as
outputs, you must use an external pullup resistor to make
them output correct values when using I2C, GPIO, and
UART0.
32
24
16
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
QFN
QFN
QFN
1
1
—
PTB6/
DISABLED
PTB6/
TPM1_CH1
TPM_CLKIN1
IRQ_2/
IRQ_2/
LPTMR0_ALT3
LPTMR0_ALT3
2
2
—
PTB7/
IRQ_3
DISABLED
PTB7/
IRQ_3
TPM1_CH0
3
4
3
3
1
1
VDD
VDD
VDD
VREFH
VREFL
VSS
VREFH
VREFH
VREFL
VSS
5
4
2
VREFL
6
4
2
VSS
7
5
3
PTA3
PTA4
PTA5
PTA6
PTB8
PTB9
PTB10
PTB11
EXTAL0
EXTAL0
XTAL0
PTA3
PTA4
PTA5
PTA6
PTB8
PTB9
PTB10
PTB11
I2C0_SCL
I2C0_SDA
TPM0_CH1
TPM0_CH0
I2C1_SDA
I2C1_SCL
SPI0_SS_b
SPI0_MISO
8
6
4
XTAL0
9
7
5
DISABLED
DISABLED
ADC0_SE11
ADC0_SE10
ADC0_SE9
ADC0_SE8
ADC0_SE7
10
11
12
13
14
15
8
6
—
—
9
—
—
—
—
7
ADC0_SE11
ADC0_SE10
ADC0_SE9
ADC0_SE8
ADC0_SE7
TPM0_CH1
TPM0_CH0
SPI0_MISO
10
11
PTA7/
IRQ_4
PTA7/
IRQ_4
SPI0_MOSI
36
NXP Semiconductors
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
Pinout
32
24
16
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
QFN
QFN
QFN
16
17
18
12
13
14
8
9
PTB0/
IRQ_5
ADC0_SE6
ADC0_SE6
PTB0/
IRQ_5
EXTRG_IN
SPI0_SCK
PTB1/
IRQ_6
ADC0_SE5/
CMP0_IN3
ADC0_SE5/
CMP0_IN3
PTB1/
IRQ_6
UART0_TX
UART0_RX
UART0_RX
UART0_TX
10
PTB2/
IRQ_7
ADC0_SE4
ADC0_SE4
PTB2/
IRQ_7
19
20
21
15
16
—
—
—
—
PTA8
PTA9
ADC0_SE3
ADC0_SE2
DISABLED
ADC0_SE3
ADC0_SE2
PTA8
PTA9
I2C1_SCL
I2C1_SDA
PTA10/
IRQ_8
PTA10/
IRQ_8
22
23
24
25
26
—
17
18
19
20
—
11
12
13
—
PTA11/
IRQ_9
DISABLED
DISABLED
DISABLED
NMI_b
PTA11/
IRQ_9
PTB3/
IRQ_10
PTB3/
IRQ_10
I2C0_SCL
I2C0_SDA
TPM1_CH1
TPM1_CH0
UART0_TX
UART0_RX
NMI_b
PTB4/
IRQ_11
PTB4/
IRQ_11
PTB5/
IRQ_12
ADC0_SE1/
CMP0_IN1
PTB5/
IRQ_12
PTA12/
IRQ_13/
ADC0_SE0/
CMP0_IN0
ADC0_SE0/
CMP0_IN0
PTA12/
IRQ_13/
TPM_CLKIN0
LPTMR0_ALT2
LPTMR0_ALT2
27
28
29
30
—
—
21
22
—
—
—
14
PTA13
PTB12
PTB13
DISABLED
DISABLED
ADC0_SE13
SWD_CLK
PTA13
PTB12
ADC0_SE13
PTB13
TPM1_CH1
TPM1_CH0
PTA0/
IRQ_0
ADC0_SE12/
CMP0_IN2
PTA0/
IRQ_0
SWD_CLK
RESET_b
31
32
23
24
15
16
PTA1/
IRQ_1/
LPTMR0_ALT1
RESET_b
SWD_DIO
PTA1/
IRQ_1/
LPTMR0_ALT1
TPM_CLKIN0
CMP0_OUT
PTA2
PTA2
SWD_DIO
5.2 KL02 pinouts
The following figures show the pinout diagrams for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see KL02 signal multiplexing and pin assignments.
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NXP Semiconductors
Pinout
PTB4/IRQ_11
PTB3/IRQ_10
PTA11/IRQ_9
PTA10/IRQ_8
PTA9
PTB6/IRQ_2/LPTMR0_ALT3
24
23
22
21
20
19
1
2
3
4
5
6
7
8
PTB7/IRQ_3
VDD
VREFH
VREFL
VSS
PTA8
PTA3
PTB2/IRQ_7
PTB1/IRQ_6
18
17
PTA4
Figure 16. KL02 32-pin QFN pinout diagram
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NXP Semiconductors
Pinout
PTB4/IRQ_11
PTB3/IRQ_10
PTA9
PTB6/IRQ_2/LPTMR0_ALT3
18
17
16
15
14
13
1
2
3
4
5
6
PTB7/IRQ_3
VDD VREFH
VREFL VSS
PTA3
PTA8
PTB2/IRQ_7
PTB1/IRQ_6
PTA4
Figure 17. KL02 24-pin QFN pinout diagram
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NXP Semiconductors
Ordering parts
VDD VREFH
VREFL VSS
PTA3
1
2
3
4
12
11
10
9
PTB4/IRQ_11
PTB3/IRQ_10
PTB2/IRQ_7
PTB1/IRQ_6
PTA4
Figure 18. KL02 16-pin QFN pinout diagram
6 Ordering parts
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the Web. To determine the orderable part
numbers for this device, go to nxp.com and perform a part number search for the
following device numbers: PKL02 and MKL02
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
40
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NXP Semiconductors
Part identification
7.2 Format
Part numbers for this device have the following format:
Q KL## A FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 34. Part number fields descriptions
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
KL##
A
Kinetis family
Key attribute
• KL02
• Z = Cortex-M0+
FFF
Program flash memory size
• 8 = 8 KB
• 16 = 16 KB
• 32 = 32 KB
R
Silicon revision
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
PP
• FG = 16 QFN (3 mm x 3 mm)
• FK = 24 QFN (4 mm x 4 mm)
• FM = 32 QFN (5 mm x 5 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 4 = 48 MHz
• R = Tape and reel
• (Blank) = Trays
7.4 Example
This is an example part number:
MKL02Z8VFG4
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NXP Semiconductors
Small package marking
8 Small package marking
In order to save space, small package devices use special marking on the chip.
Q FS FF (TP)
Table 35. Small package marking
Field
Description
Values
Q
Qualification status
• M = M
• P = P
FS
FF
Kinetis family and CPU frequency
Program flash memory size
• (0)2T = KL02, 48 MHz of CPU
• 3 = 8 KB
• 4 = 16 KB
• 5 = 32 KB
TP
Temperature range (°C) and package
• V = –40 to 105, 24 or 32 QFN
• blank = –40 to 105, 16 QFN
For example:
M2T4 = MKL02Z16VFG4
M02T4V = MKL02Z16VFK4
9 Terminology and guidelines
9.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation and
possibly decreasing the useful life of the chip.
9.1.1 Example
This is an example of an operating requirement:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
42
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NXP Semiconductors
Terminology and guidelines
9.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of
values for a technical characteristic that are guaranteed during operation if you meet
the operating requirements and any other specified conditions.
9.2.1 Example
This is an example of an operating behavior:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
9.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that
are guaranteed, regardless of whether you meet the operating requirements.
9.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
9.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if
exceeded, may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
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NXP Semiconductors
Terminology and guidelines
9.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
9.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
44
NXP Semiconductors
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
Terminology and guidelines
9.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
9.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
9.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
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NXP Semiconductors
Terminology and guidelines
9.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
9.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
9.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
46
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NXP Semiconductors
Revision history
Table 36. Typical value conditions
Symbol
TA
Description
Value
25
Unit
°C
Ambient temperature
3.3 V supply voltage
VDD
3.3
V
10 Revision history
The following table provides a revision history for this document.
Table 37. Revision history
Rev. No.
Date
Substantial Changes
2
05/2013
07/2013
Public release.
2.1
Removed the specification on OSCERCLK (4 MHz external crystal)
because KL02 does not support it.
3
3/2014
• Updated the front page and restructured the chapters
• Added a note to the ILAT in the ESD handling ratings
• Updated table title in the Voltage and current operating ratings
• Updated Voltage and current operating requirements
• Updated footnote to the VOH in the Voltage and current operating
behaviors
• Updated Power mode transition operating behaviors
• Updated Capacitance attributes
• Updated the Device clock specifications
• Added Inter-Integrated Circuit Interface (I2C) timing
4
5
08/2014
08/2017
• Updated related source and added block diagram in the front
page
• Updated Power consumption operating behaviors
• Updated tSU and tv in Table 28, tSU, tdis, tv in Table 30
• Updated the note in KL02 signal multiplexing and pin
assignments
• Added a note in the Thermal operating requirements
• Added I2C 1 Mbit/s timing table and a footnote to the fSCL of the
I2C timing table in the Inter-Integrated Circuit Interface (I2C)
timing.
Kinetis KL02 32 KB Flash, Rev. 5 08/2017
47
NXP Semiconductors
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based
on the information in this document. NXP reserves the right to make changes
without further notice to any products herein.
How to Reach Us:
Home Page:
nxp.com
Web Support:
nxp.com/support
NXP makes no warranty, representation, or guarantee regarding the suitability of
its products for any particular purpose, nor does NXP assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in NXP data sheets and/or
specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be
validated for each customer application by customerʼs technical experts. NXP
does not convey any license under its patent rights nor the rights of others. NXP
sells products pursuant to standard terms and conditions of sale, which can be
found at the following address: nxp.com/SalesTermsandConditions. .
NXP, the NXP logo, Freescale, Freescale logo, Energy Efficient Solutions logo,
and Kinetis are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. &
Tm. Off. All other product or service names are the property of their respective
owners. ARM and Cortex are registered trademarks of ARM Limited (or its
subsidiaries) in the EU and/or elsewhere. All rights reserved.
© 2012-2017 NXP B.V.
Document Number KL02P32M48SF0
Revision 5 08/2017
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