MKL13Z64VFM4 [NXP]
Kinetis KL13 Microcontroller;型号: | MKL13Z64VFM4 |
厂家: | NXP |
描述: | Kinetis KL13 Microcontroller 微控制器 |
文件: | 总71页 (文件大小:1539K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Data Sheet: Technical Data
KL13P80M48SF3
Rev. 2, 03/2015
Kinetis KL13 Microcontroller
MKL13Z32Vxx4
MKL13Z64Vxx4
48 MHz ARM® Cortex®-M0+ and 64 KB Flash
The KL13 series is optimized for cost-sensitive and battery-
powered applications requiring low-power general purpose
connectivity. The product offers:
64 LQFP
80 LQFP
10x10 mm P 0.5 mm 12x12 mm P 0.5 mm
• Embedded ROM with boot loader for flexible program
upgrade
• High accuracy internal voltage and clock reference
• FlexIO to support any standard and customized serial
peripheral emulation
• Hardware CRC module
• Down to 60uA/MHz in very low power run mode and
1.83uA in deep sleep mode (RAM + RTC retained)
48 QFN
7x7 mm P 0.5 mm
32 QFN
5x5 mm P 0.5 mm
Core Processor
Peripherals
• ARM® Cortex®-M0+ core up to 48 MHz
• One UART module supporting ISO7816, operating
up to 1.5 Mbit/s
Memories
• Two low-power UART modules supporting
asynchronous operation in low-power modes
• Two I2C modules and I2C0 supporting up to 1
Mbit/s
• Two 16-bit SPI modules supporting up to 24 Mbit/s
• One FlexIO module supporting emulation of
additional UART, IrDA, SPI, I2C, PWM and other
serial modules, etc.
• One 16-bit 818 ksps ADC module with high
accuracy internal voltage reference (Vref) and up to
20 channels
• High-speed analog comparator containing a 6-bit
DAC for programmable reference input
• One 12-bit DAC
• 32/64 KB program flash memory
• 4/8 KB SRAM
• 8 KB ROM with build-in bootloader
• 32-byte backup register
System
• 4-channel asynchronous DMA controller
• Watchdog
• Low-leakage wakeup unit
• Two-pin Serial Wire Debug (SWD) programming and
debug interface
• Micro Trace Buffer
• Bit manipulation engine
• Interrupt controller
• 1.2 V internal voltage reference
Clocks
Timers
• 48 MHz high accuracy (up to 0.5%) internal reference
clock
• One 6-channel Timer/PWM module
• Two 2-channel Timer/PWM modules
• One low-power timer
• Periodic interrupt timer
• Real time clock
• 8MHz/2MHz high accuracy (up to 3%) internal
reference clock
• 1KHz reference clock active under all low-power
modes (except VLLS0)
• 32–40KHz and 3–32MHz crystal oscillator
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2014–2015 Freescale
Semiconductor, Inc. All rights reserved.
Operating Characteristics
Security and Integrity
• 80-bit unique identification number per chip
• Advanced flash security
• Hardware CRC module
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range: –40 to 105 °C
I/O
Packages
• Up to 70 general-purpose input/output pins (GPIO)
and 4 high-drive pad
• 80 LQFP 12mm x 12mm, 0.5mm pitch, 1.6mm
thickness
• 64 LQFP 10mm x 10mm, 0.5mm pitch, 1.6mm
thickness
• 64 MAPBGA 5mm x 5mm, 0.5mm pitch, 1.23mm
thickness (Package Your Way)
• 48 QFN 7mm x 7mm, 0.5mm pitch, 0.65mm thickness
(Package Your Way)
Low Power
• Down to 60uA/MHz in very low power run mode
• Down to 1.83uA in VLLS3 mode (RAM + RTC
retained)
• Six flexible static modes
• 32 QFN 5mm x 5mm, 0.5mm pitch, 0.65mm thickness
(Package Your Way)
Ordering Information
Product
Marking (Line1/
Memory
Package
IO and ADC channel
Part number
Flash
SRAM
(KB)
Pin
Package
GPIOs
GPIOs
ADC
Line2)
(KB)
count
(INT/HD)1 channels
(SE/DP)
MKL13Z32VFM4
MKL13Z64VFM4
MKL13Z32VFT4
MKL13Z64VFT4
MKL13Z32VLH4
MKL13Z64VLH4
MKL13Z32VMP4
MKL13Z64VMP4
MKL13Z32VLK4
MKL13Z64VLK4
TBD
TBD
32
64
32
64
32
64
32
64
32
64
4
8
4
8
4
8
4
8
4
8
32
32
48
48
64
64
64
64
80
80
QFN
QFN
28
28
40
40
54
54
54
54
70
70
28/4
28/4
40/4
40/4
54/4
54/4
54/4
54/4
70/4
70/4
11/2
11/2
18/3
18/3
20/4
20/4
20/4
20/4
20/4
20/4
TBD
QFN
TBD
QFN
MKL13Z32/VLH4
MKL13Z64/VLH4
TBD
LQFP
LQFP
MAPBGA
MAPBGA
LQFP
LQFP
TBD
MKL13Z32VLK4
MKL13Z64VLK4
1. INT: interrupt pin numbers; HD: high drive pin numbers
NOTE
The 32 QFN, 48 QFN, and 64 MAPBGA packages supporting MKLx3ZxxVFT4,
MKLx3ZxxVFM4, and MKLx3ZxxVMP4 part numbers for this product are not yet
available. However, these packages are included in Package Your Way program for
Kinetis MCUs. Visit freescale.com/KPYW for more details.
Related Resources
Description
Type
Selector
Guide
Resource
The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Solution Advisor
Product Brief The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
KL1xPB1
Table continues on the next page...
2
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Related Resources (continued)
Description
Type
Resource
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
KL13P80M48SF3RM1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
This document.
Chip Errata
The chip mask set Errata provides additional or corrective information for KINETIS_L_0N01P1
a particular device mask set.
Package
drawing
Package dimensions are provided in package drawings.
• 64-LQFP: 98ASS23234W1
• 64 MAPBGA:
98ASA00420D1
• 48 QFN: 98ASA00616D1
• 80 LQFP: 98ASS23174W1
• 32 QFN: 98ASA00615D1
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
3
Freescale Semiconductor, Inc.
Table of Contents
1
2
Ratings..................................................................................5
5
Communication interfaces.....................................................40
1.1 Thermal handling ratings.............................................5
1.2 Moisture handling ratings............................................ 5
1.3 ESD handling ratings...................................................5
1.4 Voltage and current operating ratings......................... 5
General................................................................................. 6
2.1 AC electrical characteristics........................................ 6
2.2 Nonswitching electrical specifications......................... 6
2.2.1 Voltage and current operating requirements... 7
2.2.2 LVD and POR operating requirements............7
2.2.3 Voltage and current operating behaviors.........8
2.2.4 Power mode transition operating behaviors.... 9
2.2.5 Power consumption operating behaviors........ 10
2.2.6 EMC performance........................................... 20
2.2.7 Capacitance attributes.....................................21
2.3 Switching specifications...............................................21
2.3.1 Device clock specifications..............................21
2.3.2 General switching specifications..................... 21
2.4 Thermal specifications.................................................22
2.4.1 Thermal operating requirements..................... 22
2.4.2 Thermal attributes............................................22
Peripheral operating requirements and behaviors................ 23
3.1 Core modules.............................................................. 23
3.1.1 SWD electricals .............................................. 23
3.2 System modules..........................................................25
3.3 Clock modules.............................................................25
3.3.1 MCG-Lite specifications...................................25
3.3.2 Oscillator electrical specifications....................25
3.4 Memories and memory interfaces............................... 28
3.4.1 Flash electrical specifications..........................28
3.5 Security and integrity modules.................................... 29
3.6 Analog......................................................................... 29
3.6.1 ADC electrical specifications........................... 29
3.6.2 Voltage reference electrical specifications...... 34
3.6.3 CMP and 6-bit DAC electrical specifications... 35
3.6.4 12-bit DAC electrical characteristics................37
Timers................................................................................... 40
5.1 SPI switching specifications........................................ 40
5.2 I2C...............................................................................45
5.2.1 Inter-Integrated Circuit Interface (I2C) timing.. 45
5.3 UART...........................................................................47
Design considerations...........................................................47
6.1 Hardware design considerations................................. 47
6.1.1 Printed circuit board recommendations...........47
6.1.2 Power delivery system.....................................47
6.1.3 Analog design..................................................48
6.1.4 Digital design...................................................49
6.1.5 Crystal oscillator.............................................. 52
6.2 Software considerations.............................................. 53
Dimensions........................................................................... 54
7.1 Obtaining package dimensions................................... 54
Pinouts and Packaging......................................................... 55
8.1 KL13 Signal Multiplexing and Pin Assignments.......... 55
8.2 KL13 Family Pinouts....................................................58
Ordering parts....................................................................... 63
9.1 Determining valid orderable parts................................63
6
7
8
9
10 Part identification...................................................................63
10.1 Description...................................................................63
10.2 Format......................................................................... 64
10.3 Fields...........................................................................64
10.4 Example.......................................................................64
11 Terminology and guidelines.................................................. 65
11.1 Definition: Operating requirement................................65
11.2 Definition: Operating behavior.....................................65
11.3 Definition: Attribute...................................................... 65
11.4 Definition: Rating......................................................... 66
11.5 Result of exceeding a rating........................................66
11.6 Relationship between ratings and operating
3
requirements................................................................67
11.7 Guidelines for ratings and operating requirements......67
11.8 Definition: Typical value...............................................68
11.9 Typical value conditions.............................................. 69
12 Revision History.................................................................... 69
4
4
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Ratings
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
Symbol
VHBM
Description
Min.
–2000
–500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
ILAT
Latch-up current at ambient temperature of 105 °C
–100
+100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
5
Freescale Semiconductor, Inc.
General
1.4 Voltage and current operating ratings
Table 4. Voltage and current operating ratings
Symbol
VDD
IDD
Description
Min.
–0.3
—
Max.
3.8
Unit
V
Digital supply voltage
Digital supply current
IO pin input voltage
120
mA
V
VIO
–0.3
–25
VDD + 0.3
25
ID
Instantaneous maximum current single pin limit (applies to
all port pins)
mA
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 1. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
2.2 Nonswitching electrical specifications
6
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
General
2.2.1 Voltage and current operating requirements
Table 5. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
1.71
–0.1
–0.1
Max.
3.6
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
0.1
V
0.1
V
VIH
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICIO
Input hysteresis
0.06 × VDD
-3
—
—
V
IO pin negative DC injection current — single pin
• VIN < VSS-0.3V
1
mA
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
-25
—
mA
• Negative current injection
VODPU
VSRAM
Open drain pullup voltage level
VDD
1.2
VDD
—
V
V
2
VDD voltage required to retain SRAM
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD
.
2.2.2 LVD and POR operating requirements
Table 6. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
—
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48
2.56
2.64
V
—
Low-voltage warning thresholds — high range
1
Table continues on the next page...
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
7
Freescale Semiconductor, Inc.
General
Table 6. VDD supply LVD and POR operating requirements (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VLVW1H
VLVW2H
VLVW3H
VLVW4H
• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11)
2.62
2.70
2.78
V
2.72
2.82
2.92
2.80
2.90
3.00
2.88
2.98
3.08
V
V
V
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
60
—
mV
V
—
—
1
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV = 00)
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
—
1.80
1.90
2.00
2.10
40
1.86
1.96
2.06
2.16
—
V
V
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
V
• Level 4 falling (LVWV = 11)
V
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
mV
—
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
—
—
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 7. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
VOH
Output high voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1.5 mA
1
VDD – 0.5
VDD – 0.5
—
—
V
V
VOH
Output high voltage — high drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –18 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –6 mA
1
VDD – 0.5
VDD – 0.5
—
—
V
V
IOHT
VOL
Output high current total for all ports
Output low voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 1.5 mA
—
100
mA
1
1
—
—
0.5
0.5
V
V
VOL
Output low voltage — high drive pad
Table continues on the next page...
8
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
General
Notes
Table 7. Voltage and current operating behaviors (continued)
Symbol
Description
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 18 mA
Min.
Max.
Unit
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 6 mA
—
0.5
V
IOLT
IIN
Output low current total for all ports
—
—
100
1
mA
μA
Input leakage current (per pin) for full temperature
range
2
IIN
IIN
Input leakage current (per pin) at 25 °C
—
—
0.025
80
μA
μA
2
2
Input leakage current (total all pins) for full
temperature range
IOZ
Hi-Z (off-state) leakage current (per pin)
Internal pullup resistors
—
1
μA
kΩ
RPU
20
50
3
1. PTB0, PTB1, PTC3, and PTD7 I/O have both high drive and normal drive capability selected by the associated
PORTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. Measured at VDD = 3.6 V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• HIRC clock mode
Table 8. Power mode transition operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tPOR After a POR event, amount of time from the
—
—
300
μs
1
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS3 → RUN
• LLS → RUN
—
—
—
—
152
152
93
166
166
104
8
μs
μs
μs
μs
7.5
Table continues on the next page...
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
9
Freescale Semiconductor, Inc.
General
Table 8. Power mode transition operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
• VLPS → RUN
—
7.5
8
8
μs
• STOP → RUN
—
7.5
μs
1. Normal boot (FTFA_FOPT[LPBOOT]=11)
2.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
NOTE
The while (1) test is executed with flash cache enabled.
Table 9. Power consumption operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
2
IDD_RUNCO Running CoreMark in flash in compute operation
mode—48M HIRC mode, 48 MHz core / 24 MHz
flash, VDD = 3.0 V
—
—
4.74
4.9
4.93
5.10
mA
mA
mA
• at 25 °C
• at 105 °C
IDD_RUNCO Running While(1) loop in flash in compute
operation mode—48M HIRC mode, 48 MHz
core / 24 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
3.27
3.42
3.43
3.59
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable
48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
2
—
—
5.63
5.79
5.86
6.02
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in flash all peripheral clock disable,
24 MHz core/12 MHz flash, VDD = 3.0 V
2,
—
—
3.47
3.63
3.61
3.78
• at 25 °C
mA
• at 105 °C
Table continues on the next page...
10
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
General
Table 9. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock disable
12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
2
—
—
2.37
2.53
2.56
2.73
mA
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
CoreMark in Flash all peripheral clock enable 48
MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
2
—
—
6.91
7.07
7.19
7.35
mA
mA
mA
mA
mA
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in flash all peripheral clock
disable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
4.14
4.3
4.31
4.47
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, running
While(1) loop in Flash all peripheral clock
disable, 24 MHz core/12 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
2.7
2.92
3.09
2.86
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock
disable, 12 MHz core/6 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
1.99
2.14
2.15
2.31
• at 105 °C
IDD_RUN Run mode current—48M HIRC mode, Running
While(1) loop in Flash all peripheral clock
enable, 48 MHz core/24 MHz flash, VDD = 3.0 V
• at 25 °C
—
—
5.39
5.56
5.61
5.78
• at 105 °C
IDD_VLPRCO Very Low Power Run Core Mark in Flash in
Compute Operation mode: Core@4MHz, Flash
@1MHz, VDD = 3.0 V
—
—
—
739
339
152
827.68
406.8
197.6
μA
μA
μA
• at 25 °C
IDD_VLPRCO Very-low-power-run While(1) loop in SRAM in
compute operation mode— 8 MHz LIRC mode,
4 MHz core / 1 MHz flash, VDD = 3.0 V
• at 25 °C
IDD_VLPRCO Very-low-power run While(1) loop in SRAM in
compute operation mode:—2 MHz LIRC mode,
2 MHz core / 0.5 MHz flash, VDD = 3.0 V
• at 25 °C
IDD_VLPR Very-low-power run mode current— 2 MHz
LIRC mode, While(1) loop in flash all peripheral
Table continues on the next page...
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
11
Freescale Semiconductor, Inc.
General
Table 9. Power consumption operating behaviors (continued)
Symbol Description
clock disable, 2 MHz core / 0.5 MHz flash, VDD
= 3.0 V
• at 25 °C
Min.
Typ.
Max.
Unit
Notes
—
119
178.5
μA
IDD_VLPR Very-low-power run mode current— 2 MHz
LIRC mode, While(1) loop in flash all peripheral
clock disable, 125 kHz core / 31.25 kHz flash,
VDD = 3.0 V
—
—
—
—
—
—
—
—
—
41
277
343
375
441
45
89.39
360.1
425.32
450
μA
μA
μA
μA
μA
μA
mA
mA
μA
• at 25 °C
IDD_VLPR Very-low-power run mode current— 8 MHz
LIRC mode, While(1) loop in flash all peripheral
clock disable, 4 MHz core / 1 MHz flash, VDD
=
3.0 V
• at 25 °C
IDD_VLPR Very-low-power run mode current— 8 MHz
LIRC mode, While(1) loop in flash all peripheral
clock enable, 4 MHz core / 1 MHz flash, VDD
=
3.0 V
• at 25 °C
IDD_VLPR Very-low-power run mode current— 8 MHz
LIRC mode, While(1) loop in SRAM in all
peripheral clock disable, 4 MHz core / 1 MHz
flash, VDD = 3.0 V
• at 25 °C
IDD_VLPR Very-low-power run mode current— 8 MHz
LIRC mode, While(1) loop in SRAM all
peripheral clock enable, 4 MHz core / 1 MHz
flash, VDD = 3.0 V
529.2
103.5
2.50
• at 25 °C
IDD_VLPR Very-low-power run mode current—2 MHz LIRC
mode, While(1) loop in SRAM all peripheral
clock disable, 125 kHz core / 31.25 kHz flash,
VDD = 3.0 V
• at 25 °C
IDD_WAIT Wait mode current—core disabled, 48 MHz
system/24 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
• at 25 °C
2.14
1.41
193
IDD_WAIT Wait mode current—core disabled, 24 MHz
system/12 MHz bus, flash disabled (flash doze
enabled), all peripheral clocks disabled,
MCG_Lite under HIRC mode, VDD = 3.0 V
• at 25 °C
1.62
IDD_VLPW Very-low-power wait mode current, core
disabled, 4 MHz system/ 1 MHz bus and flash,
all peripheral clocks disabled, VDD = 3.0 V
• at 25 °C
239.023
Table continues on the next page...
12
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
General
Notes
Table 9. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
124.8
78
Unit
IDD_VLPW Very-low-power wait mode current, core
disabled, 2 MHz system/ 0.5 MHz bus and flash,
all peripheral clocks disabled, VDD = 3.0 V
• at 25 °C
—
78
μA
IDD_VLPW Very-low-power wait mode current, core
disabled, 125 kHz system/ 31.25 kHz bus and
flash, all peripheral clocks disabled, VDD = 3.0 V
• at 25 °C
—
39
μA
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
12 MHz bus and flash, VDD = 3.0 V
• at 25 °C
—
1.72
1.1
2.06
1.32
mA
mA
IDD_PSTOP2 Partial Stop 2, core and system clock disabled,
flash doze enabled, 12 MHz bus, VDD = 3.0 V
• at 25 °C
—
IDD_STOP Stop mode current at 3.0 V
• at 25 °C and below
—
—
—
—
161
178.2
181.17
229.72
302.01
• at 50 °C
• at 85 °C
• at 105 °C
171.9
206.8
255.9
μA
μA
IDD_VLPS Very-low-power stop mode current at 3.0 V
• at 25 °C and below
—
—
—
—
2.20
4.57
3.80
8.03
• at 50 °C
• at 85 °C
• at 105 °C
18.02
39.60
31.98
65.80
IDD_VLPS Very-low-power stop mode current at 1.8 V
• at 25 °C and below
—
—
—
—
2.13
4.42
3.80
7.94
• at 50 °C
• at 85 °C
• at 105 °C
17.53
38.55
31.58
65.18
μA
μA
IDD_LLS Low-leakage stop mode current, all peripheral
disable, at 3.0 V
• at 25 °C and below
—
—
—
—
—
1.63
2.42
4.22
7.16
15.34
2.25
3.55
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
7.08
10.22
22.69
IDD_LLS Low-leakage stop mode current with RTC
current, at 3.0 V
μA
—
2.3
2.99
• at 25 °C and below
Table continues on the next page...
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
13
Freescale Semiconductor, Inc.
General
Table 9. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
—
3.12
4.50
—
—
—
4.96
7.93
7.71
10.75
22.99
16.02
IDD_LLS Low-leakage stop mode current with RTC
current, at 1.8 V
3
μA
—
—
—
—
—
2.03
2.81
4.53
7.31
14.93
2.55
3.95
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
7.30
10.25
22.72
IDD_VLLS3 Very-low-leakage stop mode 3 current, all
peripheral disable, at 3.0 V
μA
μA
μA
—
—
—
—
—
1.16
1.72
3.04
5.21
11.33
1.65
2.65
5.70
7.79
17.63
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC
current, at 3.0 V
3
—
—
—
—
—
1.83
2.43
3.78
5.98
12.02
2.35
3.39
5.95
8.14
17.89
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current with RTC
current, at 1.8 V
3
—
—
—
—
—
1.58
2.13
3.37
5.4
1.98
3.17
5.80
7.83
16.86
• at 25 °C and below
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
10.99
IDD_VLLS1 Very-low-leakage stop mode 1 current all
peripheral disabled at 3.0 V
—
—
—
—
0.62
0.99
1.88
3.41
1.06
1.43
2.65
4.53
• at 25 °C and below
• at 50°C
• at 70°C
μA
Table continues on the next page...
14
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
General
Notes
3
Table 9. Power consumption operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
• at 85°C
—
7.89
9.99
• at 105 °C
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 3.0 V
—
—
—
—
—
1.31
1.7
1.52
2.04
3.20
4.69
10.46
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C
2.6
μA
4.14
8.51
IDD_VLLS1 Very-low-leakage stop mode 1 current RTC
enabled at 1.8 V
3
—
—
—
—
—
1.06
1.39
2.18
3.54
7.43
1.35
1.73
2.83
4.60
9.97
• at 25 °C and below
• at 50°C
• at 70°C
• at 85°C
• at 105 °C
μA
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled (SMC_STOPCTRL[PORPO]
= 0) at 3.0 V
—
—
—
—
—
278
578
385
• at 25 °C and below
1013
2015
3617
9900
nA
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
1530
3070
7550
IDD_VLLS0 Very-low-leakage stop mode 0 current all
peripheral disabled (SMC_STOPCTRL[PORPO]
= 1) at 3 V
—
—
—
—
—
95
218
653
• at 25 °C and below
412
nA
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
1350
2900
7380
1683
3428
9785
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. MCG_Lite configured for HIRC mode. CoreMark benchmark compiled using IAR 7.20 with optimization level high,
optimized for balanced.
3. RTC uses external 32 kHz crystal as clock source, and the current includes ERCLK32K power consumption.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
15
Freescale Semiconductor, Inc.
General
Table 10. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIRC8MHz
8 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 8 MHz IRC enabled,
MCG_SC[FCRDIV]=000b,
85
87
88
88
89
90
µA
MCG_MC[LIRC_DIV2]=000b.
IIRC2MHz
2 MHz internal reference clock (IRC)
adder. Measured by entering STOP
mode with the 2 MHz IRC enabled,
MCG_SC[FCRDIV]=000b,
28
28
28
28
28
28
µA
µA
MCG_MC[LIRC_DIV2]=000b.
IEREFSTEN4MHz
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS
mode with the crystal enabled.
206
224
230
238
245
253
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of setting the
OSC0_CR[EREFSTEN and
EREFSTEN] bits to 1 and
SIM_SOPT1[OSC32KSEL] to 01.
Measured by entering all modes with
the crystal enabled.
• VLLS1
440
440
490
510
510
490
490
490
560
560
540
540
540
560
560
560
560
560
560
560
570
570
570
610
610
580
580
680
680
680
• VLLS3
• LLS
• VLPS
• STOP
nA
ILPTMR
LPTMR peripheral adder measured by
placing the device in VLLS1 mode with
LPTMR enabled using LPO.
30
30
30
85
100
200
nA
µA
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare.
16
16
16
16
16
16
Includes 6-bit DAC power consumption.
IRTC
RTC peripheral adder measured by
placing the device in VLLS1 mode with
external 32 kHz crystal enabled by
means of the RTC_CR[OSCE] bit and
the RTC ALARM set for 1 minute.
Includes ERCLK32K (32 kHz external
crystal) power consumption.
582
627
638
662
682
760
nA
IUART
UART peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source waiting
for RX data at 115200 baud rate.
Table continues on the next page...
16
Freescale Semiconductor, Inc.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
General
Table 10. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
Includes selected clock source power
consumption.
105
34
110
34
110
34
111
34
112
34
114
34
µA
• IRC8M (8 MHz internal reference
clock)
• IRC2M (2 MHz internal reference
clock)
ITPM
TPM peripheral adder measured by
placing the device in STOP or VLPS
mode with selected clock source
configured for output compare
generating 100 Hz clock signal. No load
is placed on the I/O generating the clock
signal. Includes selected clock source
and I/O switching currents.
130
40
130
40
130
40
130
40
130
40
130
40
µA
• IRC8M (8 MHz internal reference
clock)
• IRC2M (2 MHz internal reference
clock)
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPx or VLLSx
mode.
45
45
45
45
45
45
µA
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS
mode. ADC is configured for low power
mode using the internal clock and
continuous conversions.
320
320
320
320
320
320
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG-Lite in HIRC for run mode, and LIRC for VLPR mode
• No GPIOs toggled
• Code execution from flash
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
17
Freescale Semiconductor, Inc.
General
Figure 2. Run mode supply current vs. core frequency
18
Freescale Semiconductor, Inc.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
General
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
19
Freescale Semiconductor, Inc.
General
Figure 3. VLPR mode current vs. core frequency
2.2.6 EMC performance
Electromagnetic compatibility (EMC) performance is highly dependent on the
environment in which the MCU resides. Board design and layout, circuit topology
choices, location and characteristics of external components, and MCU software
operation play a significant role in the EMC performance. The system designer can
consult the following Freescale applications notes, available on freescale.com for
advice and guidance specifically targeted at optimizing EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
• AN2764: Improving the Transient Immunity Performance of Microcontroller-
Based Applications
20
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
General
• AN1259: System Design and Layout Techniques for Noise Reduction in MCU-
Based Systems
• KL-QRUG (Kinetis L-series Quick Reference).
2.2.7 Capacitance attributes
Table 11. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN
Input capacitance
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 12. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Normal run mode
fSYS
fBUS
fFLASH
fLPTMR
System and core clock
Bus clock
—
—
—
—
48
24
24
24
MHz
MHz
MHz
MHz
Flash clock
LPTMR clock
VLPR and VLPS modes1
fSYS
fBUS
fFLASH
fLPTMR
System and core clock
Bus clock
—
—
—
—
—
—
4
1
MHz
MHz
MHz
MHz
MHz
MHz
Flash clock
LPTMR clock2
1
24
16
16
fLPTMR_ERCLK LPTMR external reference clock
fosc_hi_2
Oscillator crystal or resonator frequency — high frequency
mode (high range) (MCG_C2[RANGE]=1x)
fTPM
TPM asynchronous clock
—
—
8
8
MHz
MHz
fLPUART0/1 LPUART0/1 asynchronous clock
1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
21
Freescale Semiconductor, Inc.
General
2.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 13. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) —
Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
Port rise and fall time
16
—
—
ns
ns
2
3
36
1. The synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 14. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Notes
Die junction temperature
Ambient temperature
TA
105
°C
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + θJA × chip power dissipation.
2.4.2 Thermal attributes
NOTE
The 48 QFN, 32 QFN, and 64 MAPBGA packages for this
product are not yet available. However, these packages are
included in Package Your Way program for Kinetis MCUs.
Visit freescale.com/KPYW for more details.
22
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 15. Thermal attributes
Board type
Symbol
Description
64 LQFP 80 LQFP
Unit
Notes
Single-layer (1S)
RθJA
Thermal resistance, junction to
ambient (natural convection)
71
53
60
46
35
21
5
58
43
47
37
26
15
3
°C/W
1, 2
Four-layer (2s2p)
RθJA
RθJMA
RθJMA
RθJB
Thermal resistance, junction to
ambient (natural convection)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 3
1, 3,
4
Single-layer (1S)
Thermal resistance, junction to
ambient (200 ft./min. air speed)
Four-layer (2s2p)
Thermal resistance, junction to
ambient (200 ft./min. air speed)
—
—
—
Thermal resistance, junction to
board
RθJC
ΨJT
Thermal resistance, junction to
case
5
Thermal characterization
6
parameter, junction to package top
outside center (natural convection)
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
thermal resistance.
2. Per JEDEC JESD51-2 with natural convection for horizontally oriented board. Board meets JESD51-9 specification for
1s or 2s2p board, respectively.
3. Per JEDEC JESD51-6 with forced convection for horizontally oriented board. Board meets JESD51-9 specification for
1s or 2s2p board, respectively.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is
written as Psi-JT.
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 16. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
J1
SWD_CLK frequency of operation
Table continues on the next page...
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
23
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 16. SWD full voltage range electricals (continued)
Symbol
Description
• Serial wire debug
Min.
Max.
Unit
0
25
MHz
J2
J3
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
1/J1
—
ns
20
—
ns
J4
J9
SWD_CLK rise and fall times
—
10
0
3
ns
ns
ns
ns
ns
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
—
32
—
J10
J11
J12
—
5
J2
J4
J3
J3
SWD_CLK (input)
J4
Figure 4. Serial wire clock input timing
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
J9
J10
Input data valid
J11
Output data valid
J12
J11
Output data valid
Figure 5. Serial wire data timing
24
Freescale Semiconductor, Inc.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Peripheral operating requirements and behaviors
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG-Lite specifications
Table 17. IRC48M specifications
Symbol
IDD48M
firc48m
Description
Min.
—
Typ.
400
48
Max.
500
—
Unit
μA
Notes
Supply current
Internal reference frequency
—
MHz
Δfirc48m_ol_lv Open loop total deviation of IRC48M frequency at
low voltage (VDD=1.71V-1.89V) over temperature
—
0.5
1.5
%firc48m
Δfirc48m_ol_hv Open loop total deviation of IRC48M frequency at
high voltage (VDD=1.89V-3.6V) over temperature
—
—
—
0.5
35
2
1.0
150
3
%firc48m
ps
Jcyc_irc48m Period Jitter (RMS)
tirc48mst
Startup time
μs
Table 18. IRC8M/2M specification
Symbol
IDD_2M
Description
Min.
—
Typ.
14
30
2
Max.
17
Unit
µA
Notes
Supply current in 2 MHz mode
Supply current in 8 MHz mode
Output frequency
—
—
—
—
—
—
—
—
IDD_8M
—
35
µA
fIRC_2M
fIRC_8M
fIRC_T_2M
fIRC_T_8M
Tsu_2M
—
—
MHz
MHz
Output frequency
—
8
—
Output frequency range (trimmed)
Output frequency range (trimmed)
Startup time
—
—
—
—
—
3
%fIRC
%fIRC
µs
—
3
—
12.5
12.5
Tsu_8M
Startup time
—
µs
3.3.2 Oscillator electrical specifications
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
25
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.3.2.1 Oscillator DC electrical specifications
Table 19. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
25
400
500
2.5
3
—
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
4
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain
mode (HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Table continues on the next page...
26
Freescale Semiconductor, Inc.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Peripheral operating requirements and behaviors
Table 19. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Peak-to-peak amplitude of oscillation (oscillator
—
VDD
—
V
mode) — low-frequency, high-gain mode
(HGO=1)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
—
—
0.6
—
—
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2 Oscillator frequency specifications
Table 20. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
fosc_hi_1 Oscillator crystal or resonator frequency —
high-frequency mode (low range)
3
8
—
—
8
MHz
MHz
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency —
high frequency mode (high range)
(MCG_C2[RANGE]=1x)
32
fec_extal Input clock frequency (external clock mode)
tdc_extal Input clock duty cycle (external clock mode)
—
40
—
—
50
48
60
—
MHz
%
tcst
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
1, 2
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
1. Proper PC board layout procedures must be followed to achieve specifications.
2. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
27
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 21. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
13
Max.
18
Unit
μs
Notes
thvpgm4
Longword Program high-voltage time
—
1
thversscr Sector Erase high-voltage time
—
113
452
ms
ms
thversall
Erase All high-voltage time
—
52
1
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 22. Flash command timing specifications
Symbol Description
Min.
—
—
—
—
—
—
—
—
—
—
—
Typ.
—
Max.
60
Unit
μs
Notes
trd1sec1k Read 1s Section execution time (flash sector)
1
1
tpgmchk
trdrsrc
tpgm4
Program Check execution time
Read Resource execution time
Program Longword execution time
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
45
μs
—
30
μs
1
65
14
—
145
114
0.9
25
μs
—
2
tersscr
trd1all
ms
ms
μs
1
trdonce
—
1
tpgmonce Program Once execution time
65
70
—
—
μs
—
2
tersall
tvfykey
tersallu
Erase All Blocks execution time
575
30
ms
μs
Verify Backdoor Access Key execution time
Erase All Blocks Unsecure execution time
1
70
575
ms
2
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
28
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.4.1.3 Flash high voltage current behaviors
Table 23. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
2.5
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
3.4.1.4 Reliability specifications
Table 24. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
—
—
2
20
100
50 K
10 K
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
Using differential inputs can achieve better system accuracy than using single-end
inputs.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
29
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.6.1.1 16-bit ADC operating conditions
Table 25. 16-bit ADC operating conditions
Symbol Description
Conditions
Min.
1.71
Typ.1
Max.
3.6
Unit
V
Notes
VDDA
ΔVDDA
ΔVSSA
VADIN
Supply voltage
Supply voltage
Absolute
—
—
2
Delta to VDD (VDD – VDDA
)
-100
0
+100
+100
mV
mV
V
Ground voltage Delta to VSS (VSS – VSSA
)
-100
0
2
Input voltage
• 16-bit differential mode
• All other modes
• 16-bit mode
VREFL
—
31/32 *
VREFH
—
VREFL
—
VREFH
CADIN
Input
—
—
8
4
10
5
pF
—
capacitance
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input series
resistance
—
—
2
5
5
kΩ
kΩ
—
3
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
fADCK
fADCK
Crate
ADC conversion ≤ 13-bit mode
clock frequency
1.0
2.0
—
—
18.0
12.0
MHz
MHz
4
4
5
ADC conversion 16-bit mode
clock frequency
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
20.000
37.037
—
—
818.330
461.467
Ksps
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
5
rate
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
30
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 6. ADC input impedance equivalency diagram
3.6.1.2 16-bit ADC electrical characteristics
Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
6.1
7.3
9.5
Unit
mA
Notes
IDDA_ADC Supply current
—
3
ADC
asynchronous
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
2.4
4.0
5.2
6.2
MHz
MHz
MHz
MHz
tADACK =
1/fADACK
2.4
clock source
fADACK
3.0
4.4
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total
unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
2.5
1.4
6.8
2.1
LSB4
LSB4
5
5
Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
0.7
0.2
–1.1 to
+1.9
–0.3 to
0.5
INL
Integral non-
linearity
• 12-bit modes
—
0.9
–2.7 to
+1.9
LSB4
5
Table continues on the next page...
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
31
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
—
0.4
• <12-bit modes
–0.7 to
+0.5
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• 16-bit modes
• ≤13-bit modes
—
—
—
—
–4
–1.4
–1 to 0
—
–5.4
–1.8
—
LSB4
LSB4
VADIN
VDDA
=
5
Quantization
error
0.5
ENOB Effective
number of bits
16-bit differential mode
• Avg = 32
6
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg = 4
16-bit single-ended mode
• Avg = 32
12.2
11.4
13.9
13.1
—
—
bits
bits
• Avg = 4
Signal-to-noise See ENOB
plus distortion
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic 16-bit differential mode
7
7
distortion
—
—
–94
–85
—
—
dB
dB
• Avg = 32
16-bit single-ended mode
• Avg = 32
SFDR Spurious free
dynamic range
16-bit differential mode
• Avg = 32
82
78
95
90
—
—
dB
dB
16-bit single-ended mode
• Avg = 32
EIL
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Temp sensor
slope
Across the full temperature range
of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
8
VTEMP25 Temp sensor
voltage
25 °C
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
32
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
12.30
12.00
Averaging of 8 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 7. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
12.75
12.50
12.25
12.00
11.75
11.50
11.25
11.00
Averaging of 4 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 8. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
33
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.6.2 Voltage reference electrical specifications
Table 27. VREF full-range operating requirements
Symbol
VDDA
TA
Description
Supply voltage
Temperature
Min.
Max.
Unit
V
Notes
—
3.6
Operating temperature
range of the device
°C
—
CL
Output load capacitance
100
nF
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature range
of the device.
Table 28 is tested under the condition of setting VREF_TRM[CHOPEN],
VREF_SC[REGEN] and VREF_SC[ICOMPEN] bits to 1.
Table 28. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.1915
1.195
1.1977
V
1
nominal VDDA and temperature=25C
Voltage reference output — factory trim
Voltage reference output — user trim
Voltage reference trim step
Vout
Vout
1.1584
1.193
—
—
—
0.5
2
1.2376
1.197
—
V
V
1
1
1
1
Vstep
Vtdrift
mV
mV
Temperature drift (Vmax -Vmin across the full
temperature range: 0 to 70°C)
—
15
Ibg
Ilp
Bandgap only current
—
—
—
—
—
—
80
360
1
µA
uA
mA
µV
1
1
Low-power buffer current
High-power buffer current
Ihp
1
ΔVLOAD Load regulation
• current = 1.0 mA
1, 2
—
200
—
Tstup
Buffer startup time
—
—
—
—
100
35
µs
—
—
Tchop_osc_st Internal bandgap start-up delay with chop
ms
oscillator enabled
up
Vvdrift
Voltage drift (Vmax -Vmin across the full voltage
range)
—
2
—
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
34
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 29. VREF limited-range operating requirements
Symbol
Description
Temperature
Min.
Max.
50
Unit
Notes
TA
0
°C
—
Table 30. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim
1.173
1.225
V
—
3.6.3 CMP and 6-bit DAC electrical specifications
Table 31. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
VDD – 0.5
—
—
—
50
250
—
7
—
0.5
200
600
40
V
V
Output low
Propagation delay, high-speed mode (EN=1, PMODE=1)
Propagation delay, low-speed mode (EN=1, PMODE=0)
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
20
ns
tDLS
80
ns
—
μs
IDAC6b
INL
—
—
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
35
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
0.08
0.07
0.06
0.05
0.04
0.03
HYSTCTR
Setting
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
36
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.4 12-bit DAC electrical characteristics
3.6.4.1 12-bit DAC operating requirements
Table 32. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
CL
Desciption
Min.
Max.
3.6
3.6
100
1
Unit
V
Notes
Supply voltage
Reference voltage
Output load capacitance
Output load current
1.13
—
V
1
2
pF
mA
IL
—
1. The DAC reference can be selected to be VDDA or VREFH
.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
37
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.6.4.2 12-bit DAC operating behaviors
Table 33. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
250
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
100
15
900
200
30
μA
μs
μs
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-speed
mode
0.7
1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
—
—
—
—
—
—
100
mV
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
VDACR
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR > 2
V
Differential non-linearity error — VDACR
VREF_OUT
=
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
Rop
SR
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance (load = 3 kΩ)
Slew rate -80h→ F7Fh→ 80h
3.7
—
μV/C
%FSR/C
Ω
6
0.000421
—
—
250
V/μs
• High power (SPHP
)
1.2
1.7
—
—
• Low power (SPLP
3dB bandwidth
)
0.05
0.12
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
38
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
8
6
4
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 11. Typical INL error vs. digital code
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
39
Freescale Semiconductor, Inc.
Timers
1.499
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
85
25
105
125
-40
Temperature °C
Figure 12. Offset at half scale vs. temperature
4 Timers
See General switching specifications.
5 Communication interfaces
40
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Communication interfaces
5.1 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master
and slave operations. Many of the transfer attributes are programmable. The following
tables provide timing characteristics for classic SPI timing modes. See the SPI chapter
of the chip's Reference Manual for information about the modified transfer formats
used for communicating with slower peripheral devices.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted,
as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 34. SPI master mode timing on slew rate disabled pads
Num.
Symbol Description
Min.
Max.
Unit
Hz
Note
1
2
fop
Frequency of operation
fperiph/2048
2 x tperiph
fperiph/2
1
2
tSPSCK
SPSCK period
2048 x
tperiph
ns
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
1024 x
tperiph
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
18
0
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
15
8
tv
—
0
9
tHO
tRI
—
10
—
tperiph - 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
Table 35. SPI master mode timing on slew rate enabled pads
Num.
Symbol Description
Min.
Max.
Unit
Hz
Note
1
2
fop
Frequency of operation
fperiph/2048
2 x tperiph
fperiph/2
1
2
tSPSCK
SPSCK period
2048 x
tperiph
ns
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
1024 x
tperiph
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
96
0
—
—
ns
ns
—
—
Table continues on the next page...
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
41
Freescale Semiconductor, Inc.
Communication interfaces
Table 35. SPI master mode timing on slew rate enabled pads (continued)
Num.
Symbol Description
Min.
—
Max.
83
Unit
ns
Note
—
8
9
tv
Data valid (after SPSCK edge)
tHO
tRI
Data hold time (outputs)
Rise time input
0
—
ns
—
10
—
tperiph - 25
ns
—
tFI
Fall time input
11
tRO
tFO
Rise time output
Fall time output
—
36
ns
—
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 13. SPI master mode timing (CPHA = 0)
42
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Communication interfaces
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
LSB IN
MSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER MSB OUT
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 14. SPI master mode timing (CPHA = 1)
Table 36. SPI slave mode timing on slew rate disabled pads
Num.
1
Symbol Description
Min.
Max.
fperiph/4
—
Unit
Hz
Note
1
fop
tSPSCK
tLead
tLag
Frequency of operation
0
2
SPSCK period
Enable lead time
Enable lag time
4 x tperiph
ns
2
3
1
—
tperiph
tperiph
ns
—
—
—
—
—
3
4
1
—
5
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
—
6
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
2.5
3.5
—
—
—
0
—
ns
7
—
ns
8
tperiph
tperiph
31
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
—
ns
—
tperiph - 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
43
Freescale Semiconductor, Inc.
Communication interfaces
Table 37. SPI slave mode timing on slew rate enabled pads
Num.
1
Symbol Description
Min.
Max.
fperiph/4
—
Unit
Hz
Note
1
fop
tSPSCK
tLead
tLag
Frequency of operation
0
2
SPSCK period
Enable lead time
Enable lag time
4 x tperiph
ns
2
3
1
—
tperiph
tperiph
ns
—
—
—
—
—
3
4
1
—
5
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
—
6
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
2
7
—
ns
7
—
ns
8
—
—
—
0
tperiph
tperiph
130
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
—
ns
—
tperiph - 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
36
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
SS
(INPUT)
2
12
12
13
13
4
SPSCK
(CPOL=0)
(INPUT)
5
5
3
SPSCK
(CPOL=1)
(INPUT)
9
8
10
11
11
see
note
SEE
NOTE
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
6
MOSI
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
NOTE: Not defined
Figure 15. SPI slave mode timing (CPHA = 0)
44
Freescale Semiconductor, Inc.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Communication interfaces
SS
(INPUT)
4
2
12
12
13
13
3
SPSCK
(CPOL=0)
(INPUT)
5
5
SPSCK
(CPOL=1)
(INPUT)
11
9
10
SLAVE MSB OUT
see
note
MISO
(OUTPUT)
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
8
6
7
MOSI
(INPUT)
MSB IN
NOTE: Not defined
Figure 16. SPI slave mode timing (CPHA = 1)
5.2 I2C
5.2.1 Inter-Integrated Circuit Interface (I2C) timing
Table 38. I2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency
fSCL
0
4
100
—
0
4001
kHz
µs
Hold time (repeated) START condition. tHD; STA
After this period, the first clock pulse is
generated.
0.6
—
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.25
0.6
—
—
—
µs
µs
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
0.6
Data hold time for I2C bus devices
tHD; DAT
tSU; DAT
tr
02
2505
—
3.453
—
04
1003, 6
20 +0.1Cb
20 +0.1Cb
0.6
0.92
—
µs
ns
ns
ns
µs
µs
Data set-up time
7
6
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
1000
300
—
300
300
—
tf
—
tSU; STO
tBUF
4
Bus free time between STOP and
START condition
4.7
—
1.3
—
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
45
Freescale Semiconductor, Inc.
Communication interfaces
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only be achieved when using the
High drive pins across the full voltage range and when using the Normal drive pins and VDD ≥ 2.7 V.
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU;
DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
7. Cb = total capacitance of the one bus line in pF.
To achieve 1MHz I2C clock rates, consider the following recommendations:
• To counter the effects of clock stretching, the I2C baud Rate select bits can be
configured for faster than desired baud rate.
• Use high drive pad and DSE bit should be set in PORTx_PCRn register.
• Minimize loading on the I2C SDA and SCL pins to ensure fastest rise times for the
SCL line to avoid clock stretching.
• Use smaller pull up resistors on SDA and SCL to reduce the RC time constant.
Table 39. I 2C 1Mbit/s timing
Characteristic
Symbol
fSCL
Minimum
Maximum
Unit
MHz
µs
SCL Clock Frequency
0
11
Hold time (repeated) START condition. After this
period, the first clock pulse is generated.
tHD; STA
0.26
—
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
0.5
0.26
—
—
µs
µs
µs
µs
ns
ns
ns
µs
µs
ns
Set-up time for a repeated START condition
Data hold time for I2C bus devices
Data set-up time
tSU; STA
tHD; DAT
tSU; DAT
tr
0.26
—
0
—
50
—
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
20 +0.1Cb
120
120
—
2
tf
20 +0.1Cb
tSU; STO
tBUF
0.26
0.5
0
Bus free time between STOP and START condition
—
Pulse width of spikes that must be suppressed by
the input filter
tSP
50
1. The maximum SCL Clock Frequency of 1Mbit/s can support maximum bus loading when using the High drive pins
across the full voltage range.
2. Cb = total capacitance of the one bus line in pF.
46
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Design considerations
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tSU; STO
HD; STA
S
SR
P
S
tHD; DAT
tHIGH
Figure 17. Timing definition for devices on the I2C bus
5.3 UART
See General switching specifications.
6 Design considerations
6.1 Hardware design considerations
This device contains protective circuitry to guard against damage due to high static
voltage or electric fields. However, take normal precautions to avoid application of
any voltages higher than maximum-rated voltages to this high-impedance circuit.
6.1.1 Printed circuit board recommendations
• Place connectors or cables on one edge of the board and do not place digital
circuits between connectors.
• Drivers and filters for I/O functions should be placed as close to the connectors as
possible. Connect TVS devices at the connector to a good ground. Connect filter
capacitors at the connector to a good ground.
• Physically isolate analog circuits from digital circuits if possible.
• Place input filter capacitors as close to the MCU as possible.
• For best EMC performance, route signals as transmission lines; use a ground
plane directly under LQFP packages; and solder the exposed pad (EP) to ground
directly under QFN packages.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
47
Freescale Semiconductor, Inc.
Design considerations
6.1.2 Power delivery system
Consider the following items in the power delivery system:
• Use a plane for ground.
• Use a plane for MCU VDD supply if possible.
• Always route ground first, as a plane or continuous surface, and never as sequential
segments.
• Route power next, as a plane or traces that are parallel to ground traces.
• Place bulk capacitance, 10uF or more, at the entrance of the power plane.
• Place bypass capacitors for MCU power domain as close as possible to each
VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.
• The minimum bypass requirement is to place 0.1 μF capacitors positioned as near
as possible to the package supply pins.
• Take special care to minimize noise levels on the VREFH/VREFL inputs. An
option is to use the internal reference voltage (output 1.2V typically) as the ADC
reference.
NOTE
The internal reference voltage output (VREFO) is bonded to
the VREFH pin on some packages and to PTE30 on other
packages. When the VREFO output is used, a 0.1uF capacitor
is required as a filter. Do not connect any other supply voltage
to the pin that has VREFO activated.
6.1.3 Analog design
Each ADC input must have an RC filter as shown in the following figure. The
maximum value of R must be RAS max if fast sampling and high resolution are
required. The value of C must be chosen to ensure that the RC time constant is very
small compared to the sample period.
MCU
1
2
Input signal
ADCx
R
C
Figure 18. RC circuit for ADC input
48
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Design considerations
High voltage measurement circuits require voltage division, current limiting, and
over-voltage protection as shown the following figure. The voltage divider formed by
R1 – R4 must yield a voltage less than or equal to VREFH. The current must be
limited to less than the injection current limit. Since the ADC pins do not have diodes
to VDD, external clamp diodes must be included to protect against transient over-
voltages.
MCU
R1
R2
R3
VDD
1
1
1
2
2
2
R5
1
2
ADCx
High voltage input
R4
1
2
C
BAT54SW
Figure 19. High voltage measurement with an ADC input
6.1.4 Digital design
Ensure that all I/O pins cannot get pulled above VDD (max I/O spec is VDD+0.3V).
CAUTION
Do not provide power to I/O pins prior to VDD, especially
the RESET_b pin.
• RESET_b pin
The RESET_b pin is an open-drain I/O pin that has an internal pullup resistor. An
external RC circuit is recommended to filter noise as shown in the following
figure. The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the
recommended capacitance value is 0.1 μF. The RESET_b pin also has a selectable
digital filter to reject spurious noise.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
49
Freescale Semiconductor, Inc.
Design considerations
VDD
MCU
10k
RESET_b
RESET_b
0.1uF
Figure 20. Reset circuit
When an external supervisor chip is connected to the RESET_b pin, a series
resistor should be used to avoid damaging the supervisor chip or the RESET_b pin,
as shown in Figure 55. The series resistor value (RS below) should be in the range
of 100Ω to 1kΩ depending on the external reset chip drive strength. The supervisor
chip must have an active high, open-drain output.
VDD
Supervisor Chip
MCU
10k
1
2
OUT
RESET_b
RS
Active high,
open drain
0.1uF
Figure 21. Reset signal connection to external reset chip
• NMI pin
Because a low level on the NMI_b pin will trigger the Non-maskable interrupt, it is
not recommended to add a pull-down resistor or capacitor on this pin. When this
pin is enabled as the NMI function an external pull-up resistor (10k) as shown in
the following figure is recommended for robustness.
If the NMI_b pin is used as an I/O pin the Non-maskable interrupt handler is
required to disable the NMI function by remapping to another function. The NMI
function is disabled by programming the FOPT[NMI_DIS] bit to zero.
50
Freescale Semiconductor, Inc.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Design considerations
VDD
MCU
10k
NMI_b
Figure 22. NMI pin biasing
• Debug interface
This MCU uses the standard ARM SWD interface protocol as shown in the
following figure. While pull-up or pull-down resistors are not required
(SWD_DIO has an internal pull-up and SWD_CLK has an internal pull-down),
external 10kΩ pull resistors are recommended for system robustness. Please note
the RESET_b pin recommendations mentioned above.
VDD
10k
VDD
J1
SWD_DIO
SWD_CLK
1
3
5
7
9
2
4
6
8
RESET_b
10k
10
0.1uF
HDR_5X2
Figure 23. SWD debug interface
• Low leakage stop mode wakeup
Select low leakage wakeup pins (LLWU_Px) to wake the MCU from one of the
low leakage stop modes (LLS/VLLSx). Please refer to the signal multiplexing
table for pin selection.
• Unused pin
Unused GPIO pins should be left floating (no electrical connections) with the
MUX field of the pin’s PORTx_PCRn register equal to 0:0:0. This disables the
digital input path to the MCU.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
51
Freescale Semiconductor, Inc.
Design considerations
6.1.5 Crystal oscillator
When using an external crystal or ceramic resonator as the frequency reference for the
MCU clock system, refer to the following table and diagrams.
The feedback resistor, RF, is incorporated internally with the low power oscillators. An
external feedback is required when using high gain (HGO=1) mode.
The series resistor, RS, is required in high gain (HGO=1) mode when the crystal or
resonator frequency is below 2MHz. Otherwise, the low power oscillator (HGO=0)
must not have any series resistance; and the high frequency, high gain oscillator with a
frequency above 2MHz does not require any series resistance.
Internal load capacitors (Cx, Cy) are provided in the low frequency (32.786kHz) mode.
Use the SCxP bits in the OSC0_CR register to adjust the load capacitance for the
crystal. Typically, values of 10pf to 16pF are sufficient for 32.768kHz crystals that have
a 12.5pF CL specification. The internal load capacitor selection must not be used for
high frequency crystals and resonators.
Table 40. External crystal/resonator connections
Oscillator mode
Low frequency (32.768kHz), low power
Low frequency (32.768kHz), high gain
High frequency (1-32MHz), low power
High frequency (1-32MHz), high gain
Oscillator mode
Diagram 1
Diagram 2, Diagram 4
Diagram 3
Diagram 4
OSCILLATOR
EXTAL
XTAL
1
2
CRYSTAL
Figure 24. Crystal connection – Diagram 1
52
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Design considerations
OSCILLATOR
EXTAL
XTAL
1
2
RF
RS
1
2
CRYSTAL
Figure 25. Crystal connection – Diagram 2
OSCILLATOR
EXTAL
OSCILLATOR
EXTAL
XTAL
XTAL
1
2
1
3
CRYSTAL
Cx
Cy
RESONATOR
Figure 26. Crystal connection – Diagram 3
OSCILLATOR
EXTAL
OSCILLATOR
EXTAL
XTAL
XTAL
1
2
1
2
RF
RF
RS
RS
1
2
1
3
CRYSTAL
Cx
Cy
RESONATOR
Figure 27. Crystal connection – Diagram 4
6.2 Software considerations
All Kinetis MCUs are supported by comprehensive Freescale and third-party
hardware and software enablement solutions, which can reduce development costs and
time to market. Featured software and tools are listed below. Visit http://
www.freescale.com/kinetis/sw for more information and supporting collateral.
Evaluation and Prototyping Hardware
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
53
Freescale Semiconductor, Inc.
Dimensions
• Freescale Freedom Development Platform: http://www.freescale.com/freedom
• Tower System Development Platform: http://www.freescale.com/tower
IDEs for Kinetis MCUs
• Kinetis Design Studio IDE: http://www.freescale.com/kds
• Partner IDEs: http://www.freescale.com/kide
Development Tools
• PEG Graphics Software: http://www.freescale.com/peg
• Processor Expert Software and Embedded Components: http://www.freescale.com/
processorexpert )
Run-time Software
• Kinetis SDK: http://www.freescale.com/ksdk
• Kinetis Bootloader: http://www.freescale.com/kboot
• ARM mbed Development Platform: http://www.freescale.com/mbed
• MQX RTOS: http://www.freescale.com/mqx
For all other partner-developed software and tools, visit http://www.freescale.com/
partners.
7 Dimensions
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
32-pin QFN
Then use this document number
98ASA00615D
48-pin QFN
98ASA00616D
98ASS23234W
98ASA00420D
98ASS23174W
64-pin LQFP
64-pin MAPBGA
80-pin LQFP
54
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Pinouts and Packaging
8 Pinouts and Packaging
8.1 KL13 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
NOTE
The 32 QFN, 48 QFN, and 64 MAPBGA packages for this
product are not yet available. However, these packages are
included in Package Your Way program for Kinetis MCUs.
Visit freescale.com/KPYW for more details.
80
64
48
64
32
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP QFN
MAP
BGA
QFN
—
1
—
1
—
—
C5
A1
—
1
NC
NC
NC
PTE0
DISABLED
PTE0/
CLKOUT32
K
SPI1_MISO LPUART1_
TX
RTC_
CLKOUT
CMP0_OUT I2C1_SDA
SPI1_MISO I2C1_SCL
2
2
—
B1
2
PTE1
DISABLED
PTE1
SPI1_MOSI LPUART1_
RX
3
4
5
6
7
8
9
—
—
—
—
3
—
—
—
—
1
—
—
—
—
—
C4
E1
—
—
—
—
—
—
3
PTE2
PTE3
PTE4
PTE5
VDD
DISABLED
DISABLED
DISABLED
DISABLED
VDD
PTE2
PTE3
PTE4
PTE5
SPI1_SCK
SPI1_MISO
SPI1_PCS0
SPI1_MOSI
VDD
VSS
4
2
VSS
VSS
5
3
PTE16
ADC0_DP1/ ADC0_DP1/ PTE16
SPI0_PCS0 UART2_TX
TPM_
FXIO0_D0
ADC0_SE1
ADC0_SE1
CLKIN0
10
6
4
D1
4
PTE17
ADC0_
DM1/
ADC0_
DM1/
PTE17
SPI0_SCK
UART2_RX TPM_
LPTMR0_
ALT3
FXIO0_D1
CLKIN1
ADC0_
SE5a
ADC0_
SE5a
11
12
7
8
5
6
E2
D2
5
6
PTE18
PTE19
ADC0_DP2/ ADC0_DP2/ PTE18
SPI0_MOSI
SPI0_MISO
I2C0_SDA
I2C0_SCL
SPI0_MISO FXIO0_D2
SPI0_MOSI FXIO0_D3
ADC0_SE2
ADC0_SE2
ADC0_
DM2/
ADC0_
DM2/
PTE19
ADC0_
SE6a
ADC0_
SE6a
13
9
7
G1
—
PTE20
ADC0_DP0/ ADC0_DP0/ PTE20
ADC0_SE0 ADC0_SE0
TPM1_CH0 LPUART0_
TX
FXIO0_D4
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
55
Freescale Semiconductor, Inc.
Pinouts and Packaging
80
64
48
64
32
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP QFN
MAP
BGA
QFN
14
10
8
F1
—
PTE21
ADC0_
DM0/
ADC0_
DM0/
PTE21
TPM1_CH1 LPUART0_
RX
FXIO0_D5
ADC0_
SE4a
ADC0_
SE4a
15
16
11
12
—
—
G2
F2
—
—
PTE22
PTE23
ADC0_DP3/ ADC0_DP3/ PTE22
TPM2_CH0 UART2_TX
TPM2_CH1 UART2_RX
FXIO0_D6
FXIO0_D7
ADC0_SE3
ADC0_SE3
ADC0_
DM3/
ADC0_
DM3/
PTE23
ADC0_
SE7a
ADC0_
SE7a
17
18
18
13
14
14
9
F4
G4
G4
7
VDDA
VDDA
VDDA
10
10
—
—
VREFH
VREFO
VREFH
VREFH
VREFH
VREFO
(1,2V
reference,
bond to
VREFH)
19
20
21
15
16
17
11
12
13
G3
F3
H1
—
8
VREFL
VSSA
VREFL
VSSA
VREFL
VSSA
—
PTE29
CMP0_IN5/
ADC0_
SE4b
CMP0_IN5/
ADC0_
SE4b
PTE29
PTE30
TPM0_CH2 TPM_
CLKIN0
22
18
14
H2
9
PTE30
DAC0_
OUT/
DAC0_
OUT/
TPM0_CH3 TPM_
CLKIN1
LPUART1_
TX
LPTMR0_
ALT1
ADC0_
SE23/
ADC0_
SE23/
CMP0_IN4
CMP0_IN4
23
24
25
26
27
19
20
21
22
23
—
15
16
17
18
H3
H4
H5
D3
D4
—
—
—
10
11
PTE31
PTE24
PTE25
PTA0
DISABLED
DISABLED
DISABLED
SWD_CLK
DISABLED
PTE31
PTE24
PTE25
PTA0
TPM0_CH4
TPM0_CH0
TPM0_CH1
TPM0_CH5
TPM2_CH0
I2C0_SCL
I2C0_SDA
SWD_CLK
PTA1
PTA1
LPUART0_
RX
28
24
19
E5
12
PTA2
DISABLED
PTA2
LPUART0_
TX
TPM2_CH1
29
30
31
32
33
34
25
26
27
28
29
—
20
21
—
—
—
—
D5
G5
F5
H6
G6
—
13
14
—
—
—
—
PTA3
SWD_DIO
NMI_b
PTA3
I2C1_SCL
I2C1_SDA
TPM0_CH0
TPM0_CH1
TPM0_CH2
TPM1_CH0
TPM1_CH1
SWD_DIO
NMI_b
PTA4
PTA4
PTA5
DISABLED
DISABLED
DISABLED
DISABLED
PTA5
PTA12
PTA13
PTA14
PTA12
PTA13
PTA14
SPI0_PCS0 LPUART0_
TX
35
36
—
—
—
—
—
—
—
—
PTA15
PTA16
DISABLED
DISABLED
PTA15
PTA16
SPI0_SCK
LPUART0_
RX
SPI0_MOSI
SPI0_MISO
56
Freescale Semiconductor, Inc.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Pinouts and Packaging
80
64
48
64
32
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP QFN
MAP
BGA
QFN
37
38
39
40
—
30
31
32
—
22
23
24
—
G7
H7
H8
—
15
16
17
PTA17
VDD
DISABLED
VDD
PTA17
SPI0_MISO
SPI0_MOSI
VDD
VSS
VSS
VSS
PTA18
EXTAL0
EXTAL0
PTA18
PTA19
PTA20
LPUART1_
RX
TPM_
CLKIN0
41
33
25
G8
18
PTA19
PTA20
XTAL0
XTAL0
LPUART1_
TX
TPM_
CLKIN1
LPTMR0_
ALT1
42
43
34
35
26
27
F8
F7
19
20
RESET_b
RESET_b
PTB0/
LLWU_P5
ADC0_SE8
ADC0_SE8
ADC0_SE9
PTB0/
LLWU_P5
I2C0_SCL
TPM1_CH0 SPI1_MOSI SPI1_MISO
44
45
36
37
28
29
F6
E7
21
—
PTB1
PTB2
ADC0_SE9
PTB1
PTB2
I2C0_SDA
I2C0_SCL
TPM1_CH1 SPI1_MISO SPI1_MOSI
TPM2_CH0
ADC0_
SE12
ADC0_
SE12
46
38
30
E8
—
PTB3
ADC0_
SE13
ADC0_
SE13
PTB3
I2C0_SDA
TPM2_CH1
47
48
49
50
51
—
—
—
—
39
—
—
—
—
31
—
—
—
—
E6
—
—
—
—
—
PTB8
PTB8
SPI1_PCS0 EXTRG_IN
SPI1_SCK
PTB9
PTB9
PTB10
PTB11
PTB16
PTB10
PTB11
PTB16
SPI1_PCS0
SPI1_SCK
SPI1_MOSI LPUART0_
RX
TPM_
CLKIN0
SPI1_MISO
SPI1_MOSI
52
40
32
D7
—
PTB17
PTB17
SPI1_MISO LPUART0_
TX
TPM_
CLKIN1
53
54
55
41
42
43
—
—
33
D6
C7
D8
—
—
—
PTB18
PTB19
PTC0
PTB18
PTB19
PTC0
TPM2_CH0
TPM2_CH1
EXTRG_IN
ADC0_
SE14
ADC0_
SE14
CMP0_OUT
56
44
34
C6
22
PTC1/
LLWU_P6/
RTC_CLKIN
ADC0_
SE15
ADC0_
SE15
PTC1/
LLWU_P6/
RTC_CLKIN
I2C1_SCL
I2C1_SDA
TPM0_CH0
TPM0_CH1
57
58
45
46
35
36
B7
C8
23
24
PTC2
ADC0_
SE11
ADC0_
SE11
PTC2
PTC3/
LLWU_P7
PTC3/
LLWU_P7
SPI1_SCK
LPUART1_
RX
TPM0_CH2 CLKOUT
59
60
61
47
48
49
—
—
37
E3
E4
B8
—
—
25
VSS
VDD
VSS
VDD
VSS
VDD
PTC4/
LLWU_P8
PTC4/
LLWU_P8
SPI0_PCS0 LPUART1_
TX
TPM0_CH3 SPI1_PCS0
62
63
64
50
51
52
38
39
40
A8
A7
B6
26
27
28
PTC5/
LLWU_P9
PTC5/
LLWU_P9
SPI0_SCK
LPTMR0_
ALT2
CMP0_OUT
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN1
CMP0_IN0
CMP0_IN1
PTC6/
LLWU_P10
SPI0_MOSI EXTRG_IN
SPI0_MISO
SPI0_MOSI
PTC7
PTC7
SPI0_MISO
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
57
Freescale Semiconductor, Inc.
Pinouts and Packaging
80
64
48
64
32
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP QFN
MAP
BGA
QFN
65
66
67
68
69
53
54
55
56
—
—
—
—
—
—
A6
B5
B4
A5
—
—
—
—
—
—
PTC8
CMP0_IN2
CMP0_IN3
CMP0_IN2
CMP0_IN3
PTC8
I2C0_SCL
I2C0_SDA
I2C1_SCL
I2C1_SDA
TPM0_CH4
TPM0_CH5
PTC9
PTC9
PTC10
PTC11
PTC12
PTC10
PTC11
PTC12
TPM_
CLKIN0
70
—
—
—
—
PTC13
PTC13
TPM_
CLKIN1
71
72
73
74
—
—
57
58
—
—
41
42
—
—
—
—
—
—
PTC16
PTC17
PTD0
PTC16
PTC17
PTD0
C3
A4
SPI0_PCS0
SPI0_SCK
TPM0_CH0
TPM0_CH1
FXIO0_D0
FXIO0_D1
PTD1
ADC0_
SE5b
ADC0_
SE5b
PTD1
75
76
77
59
60
61
43
44
45
C2
B3
A3
—
—
29
PTD2
PTD3
PTD2
PTD3
SPI0_MOSI UART2_RX TPM0_CH2 SPI0_MISO FXIO0_D2
SPI0_MISO UART2_TX TPM0_CH3 SPI0_MOSI FXIO0_D3
SPI1_PCS0 UART2_RX TPM0_CH4
PTD4/
LLWU_P14
PTD4/
LLWU_P14
FXIO0_D4
FXIO0_D5
78
79
80
62
63
64
46
47
48
C1
B2
A2
30
31
32
PTD5
ADC0_
SE6b
ADC0_
SE6b
PTD5
SPI1_SCK
UART2_TX
TPM0_CH5
I2C1_SDA
I2C1_SCL
PTD6/
LLWU_P15
ADC0_
SE7b
ADC0_
SE7b
PTD6/
LLWU_P15
SPI1_MOSI LPUART0_
RX
SPI1_MISO FXIO0_D6
SPI1_MOSI FXIO0_D7
PTD7
PTD7
SPI1_MISO LPUART0_
TX
8.2 KL13 Family Pinouts
Figure below shows the 64 LQFP pinouts:
NOTE
The 32 QFN, 48 QFN, and 64 MAPBGA packages for this
product are not yet available. However, these packages are
included in Package Your Way program for Kinetis MCUs.
Visit freescale.com/KPYW for more details.
58
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Pinouts and Packaging
PTE0
PTE1
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
2
VSS
VDD
3
PTC3/LLWU_P7
VSS
4
PTC2
PTE16
5
PTC1/LLWU_P6/RTC_CLKIN
PTE17
6
PTC0
PTE18
7
PTB19
PTB18
PTB17
PTB16
PTB3
PTE19
8
PTE20
9
PTE21
10
11
12
13
14
15
16
PTE22
PTE23
PTB2
VDDA
PTB1
VREFH/VREFO
VREFL
VSSA
PTB0/LLWU_P5
PTA20
PTA19
Figure 28. 64 LQFP Pinout diagram
Figure below shows the 80 LQFP pinouts:
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
59
Freescale Semiconductor, Inc.
Pinouts and Packaging
1
PTE0
PTE1
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
VDD
2
VSS
3
PTE2
PTC3/LLWU_P7
4
PTE3
PTC2
5
PTE4
PTC1/LLWU_P6/RTC_CLKIN
6
PTE5
PTC0
7
VDD
PTB19
PTB18
PTB17
PTB16
PTB11
PTB10
PTB9
8
VSS
9
PTE16
PTE17
PTE18
PTE19
PTE20
PTE21
PTE22
PTE23
VDDA
10
11
12
13
14
15
16
17
18
19
20
PTB8
PTB3
PTB2
PTB1
VREFH/VREFO
VREFL
VSSA
PTB0/LLWU_P5
PTA20
PTA19
Figure 29. 80 LQFP Pinout diagram
Figure below shows the 64 MAPBGA pinouts:
60
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Pinouts and Packaging
1
2
3
4
5
6
7
8
PTD4/
LLWU_P14
PTC6/
LLWU_P10 LLWU_P9
PTC5/
A
B
C
D
E
F
PTE0
PTD7
PTD1
PTC11
PTC8
A
B
C
D
E
F
PTD6/
LLWU_P15
PTE1
PTD5
PTD3
PTD0
PTA0
VSS
PTC10
VSS
PTC9
NC
PTC7
PTC2
PTB19
PTB17
PTB2
PTC4/
LLWU_P8
PTC1/
LLWU_P6/
RTC_CLKIN
PTC3/
LLWU_P7
PTD2
PTE19
PTE18
PTE23
PTE22
PTE17
PTE16
PTE21
PTE20
PTA1
VDD
PTA3
PTA2
PTA5
PTA4
PTB18
PTB16
PTB1
PTC0
PTB3
PTB0/
LLWU_P5
VSSA
VREFL
VDDA
PTA20
PTA19
G
H
VREFH/
VREFO
PTA13
VDD
G
H
PTE29
1
PTE30
2
PTE31
3
PTE24
4
PTE25
5
PTA12
6
VSS
7
PTA18
8
Figure 30. 64 MAPBGA Pinout diagram
Figure below shows the 48 QFN pinouts:
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
61
Freescale Semiconductor, Inc.
Pinouts and Packaging
PTC3/LLWU_P7
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VSS
1
2
PTC2
PTC1/LLWU_P6/RTC_CLKIN
PTE16
3
PTC0
PTE17
4
PTB17
PTB16
PTB3
PTE18
5
PTE19
6
PTE20
7
PTE21
PTB2
8
VDDA
PTB1
9
VREFH/VREFO
VREFL
PTB0/LLWU_P5
PTA20
10
11
12
VSSA
PTA19
Figure 31. 48 QFN Pinout diagram
Figure below shows the 32 QFN pinouts:
62
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Ordering parts
PTC3/LLWU_P7
PTE0
PTE1
24
23
22
21
20
19
1
2
3
4
5
6
7
8
PTC2
PTC1/LLWU_P6/RTC_CLKIN
PTE16
PTE17
PTE18
PTE19
VDDA
VSSA
PTB1
PTB0/LLWU_P5
PTA20
PTA19
18
17
PTA18
Figure 32. 32 QFN Pinout diagram
9 Ordering parts
9.1 Determining valid orderable parts
Valid orderable part numbers are provided on the Web. To determine the orderable
part numbers for this device, go to freescale.com and perform a part number search for
the following device numbers:
10 Part identification
10.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
63
Freescale Semiconductor, Inc.
Part identification
10.2 Format
Part numbers for this device have the following format:
Q KL## A FFF R T PP CC N
10.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 41. Part number fields description
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
KL##
A
Kinetis family
Key attribute
• KL13
• Z = Cortex-M0+
FFF
Program flash memory size
• 32 = 32 KB
• 64 = 64 KB
R
Silicon revision
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
PP
• FM = 32 QFN (5 mm x 5 mm) 1
• FT = 48 QFN (7 mm x 7 mm)1,
• LH = 64 LQFP (10 mm x 10 mm)
• MP = 64 MAPBGA (5 mm x 5 mm)1
• LK = 80 LQFP (12 mm x 12 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 4 = 48 MHz
• R = Tape and reel
1. This package for this product is not yet available. However, it is included in Package Your Way program for Kinetis
MCUs. Visit freescale.com/KPYW for more details.
10.4 Example
This is an example part number:
MKL13Z32VLH4
64
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Terminology and guidelines
11 Terminology and guidelines
11.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation
and possibly decreasing the useful life of the chip.
11.1.1 Example
This is an example of an operating requirement:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
11.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of
values for a technical characteristic that are guaranteed during operation if you meet
the operating requirements and any other specified conditions.
11.2.1 Example
This is an example of an operating behavior:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
65
Freescale Semiconductor, Inc.
Terminology and guidelines
11.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
11.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
11.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
11.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
66
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Terminology and guidelines
11.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
11.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
11.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
67
Freescale Semiconductor, Inc.
Terminology and guidelines
11.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
11.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
11.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
68
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Revision History
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
TJ
150 °C
105 °C
25 °C
–40 °C
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
11.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Table 42. Typical value conditions
Symbol
TA
Description
Value
25
Unit
°C
Ambient temperature
3.3 V supply voltage
VDD
3.3
V
12 Revision History
The following table provides a revision history for this document.
Table 43. Revision History
Rev. No.
Date
Substantial Changes
1
01 February
2015
• Added new topic "Electrical Design Considerations" as Section 6.
• Added a note in Table 14 - Thermal operating requirements.
• Footnote 1 in Table 9 was moved in the beginning of the table as text.
Table continues on the next page...
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
69
Freescale Semiconductor, Inc.
Revision History
Table 43. Revision History (continued)
Rev. No.
Date
Substantial Changes
2
18 March
2015
• Updated the features and completed the ordering information.
• Removed thickness dimension from package diagrams.
• Updated Table 7. Voltage and current operating behaviors.
• Specified correct max. value for IIN parameter.
• Updated Table 8. Power mode transition operating behaviors with Typ. and Max.
values.
• Updated Table 9. Power consumption operating behaviors with Typ. and Max.
values.
• Updated Table 10. Low power mode peripheral adders — typical value.
• Updated EMC Performance information in section 2.2.6.
• Updated Table 17. IRC48M specification and Table 18. IRC8M/2M specification.
• Updated Typ. values of TUE and INL parameters in Table 26. 16-bit ADC
characteristics.
• Updated Table 28. VREF full-range operating behaviors.
• Removed Ac(Aging coefficient) row.
• Added Tchop_osc_stup parameter.
• Updated typical value of the Vout parameter.
• Added tables: "I2C timing" and "I2C 1Mbit/s timing" under section - I2C.
• Updated Section 6 - Design Considerations.
70
Kinetis KL13 Microcontroller, Rev.2, 03/2015.
Freescale Semiconductor, Inc.
Information in this document is provided solely to enable system and
software implementers to use Freescale products. There are no express
or implied copyright licenses granted hereunder to design or fabricate
any integrated circuits based on the information in this document.
Freescale reserves the right to make changes without further notice to
any products herein.
How to Reach Us:
Home Page:
freescale.com
Web Support:
freescale.com/support
Freescale makes no warranty, representation, or guarantee regarding
the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages.
“Typical” parameters that may be provided in Freescale data sheets
and/or specifications can and do vary in different applications, and
actual performance may vary over time. All operating parameters,
including “typicals,” must be validated for each customer application by
customer's technical experts. Freescale does not convey any license
under its patent rights nor the rights of others. Freescale sells products
pursuant to standard terms and conditions of sale, which can be found
at the following address: freescale.com/SalesTermsandConditions.
Freescale, Freescale logo, Energy Efficient Solutions logo, and Kinetis
are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm.
Off. All other product or service names are the property of their
respective owners. ARM and Cortex are registered trademarks of ARM
Limited (or its subsidiaries) in the EU and/or elsewhere. All rights
reserved.
©2014-2015 Freescale Semiconductor, Inc.
Document Number KL13P80M48SF3
Revision 2, 03/2015
相关型号:
©2020 ICPDF网 联系我们和版权申明