MKL16Z32VLH4 [NXP]
Kinetis L 32-bit MCU, ARM Cortex-M0+ core, 32KB Flash, 48MHz, QFP 64;
| 型号： | MKL16Z32VLH4 |
| 厂家： | 
NXP |
| 描述： | Kinetis L 32-bit MCU, ARM Cortex-M0+ core, 32KB Flash, 48MHz, QFP 64 时钟 输入元件 外围集成电路 |
| 文件： | 总58页 (文件大小：1284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
Data Sheet: Technical Data
Document Number: KL16P64M48SF5
Rev 5 08/2014
Kinetis KL16 Sub-Family
MKL16ZxxxVFM4
MKL16ZxxxVFT4
MKL16ZxxxVLH4
48 MHz Cortex-M0+ Based Microcontroller
Designed with efficiency in mind. Compatible with all other
Kinetis L families as well as Kinetis K1x family. General purpose
MCU featuring market leading ultra low-power to provide
developers an appropriate entry-level 32-bit solution.
This product offers:
32-pin QFN (FM)
5 x 5 x 1 Pitch 0.5 mm 7 x 7 x 1 Pitch 0.5 mm
48-pin QFN (FT)
• Run power consumption down to 40 μA/MHz in very low
power run mode
• Static power consumption down to 2 μA with full state
retention and 4.5 μs wakeup
• Ultra-efficient Cortex-M0+ processor running up to 48 MHz
with industry leading throughput
• Memory option is up to 128 KB flash and 16 KB RAM
• Energy-saving architecture is optimized for low power with
90nm TFS technology, clock and power gating techniques,
and zero wait state flash memory controller
64-pin LQFP (LH)
10 x 10 x 1.4 Pitch 0.5 mm
Performance
• 48 MHz ARM® Cortex®-M0+ core
Human-machine interface
• Low-power hardware touch sensor interface (TSI)
• Up to 54 general-purpose input/output (GPIO)
Memories and memory interfaces
• Up to 128 KB program flash memory
• Up to 16 KB SRAM
Communication interfaces
• Two 16-bit SPI modules
• I2S (SAI) module
System peripherals
• One low power UART module
• Two UART modules
• Two I2C module
• Nine low-power modes to provide power optimization
based on application requirements
• COP Software watchdog
• 4-channel DMA controller, supporting up to 63 request Analog Modules
sources
• Low-leakage wakeup unit
• SWD debug interface and Micro Trace Buffer
• Bit Manipulation Engine
• 16-bit SAR ADC
• 12-bit DAC
• Analog comparator (CMP) containing a 6-bit DAC
and programmable reference input
Clocks
Timers
• 32 kHz to 40 kHz or 3 MHz to 32 MHz crystal oscillator
• Multi-purpose clock source
• Six channel Timer/PWM (TPM)
• Two 2-channel Timer/PWM modules
• Periodic interrupt timers
• 16-bit low-power timer (LPTMR)
• Real time clock
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range (ambient): -40 to 105°C
Security and integrity modules
• 80-bit unique identification number per chip
Freescale reserves the right to change the detail specifications as may be required to
permit improvements in the design of its products. © 2013–2014 Freescale
Semiconductor, Inc. All rights reserved.
Ordering Information 1
Memory
Part Number
Maximum number of I\O's
Flash (KB)
SRAM (KB)
MKL16Z32VFM4
32
64
4
8
28
28
28
40
40
40
54
54
54
MKL16Z64VFM4
MKL16Z128VFM4
MKL16Z32VFT4
MKL16Z64VFT4
MKL16Z128VFT4
MKL16Z32VLH4
MKL16Z64VLH4
MKL16Z128VLH4
128
32
16
4
64
8
128
32
16
4
64
8
128
16
1. To confirm current availability of ordererable part numbers, go to http://www.freescale.com and perform a part number
search.
Related Resources
Type
Description
Resource
Solution Advisor
Selector Guide The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Reference
Manual
The Reference Manual contains a comprehensive description of the KL16P64M48SF5RM1
structure and function (operation) of a device.
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
KL16P64M48SF51
Chip Errata
The chip mask set Errata provides additional or corrective
information for a particular device mask set.
KINETIS_L_xN15J 2
Package
drawing
Package dimensions are provided in package drawings.
QFN 32-pin: 98ASA00473D1
QFN 48-pin: 98ASA00466D1
LQFP 64-pin: 98ASS23234W1
1. To find the associated resource, go to http://www.freescale.com and perform a search using this term.
2. To find the associated resource, go to http://www.freescale.com and perform a search using this term with the “x”
replaced by the revision of the device you are using.
2
Kinetis KL16 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
Table of Contents
1 Ratings..................................................................................4
3.6.2 CMP and 6-bit DAC electrical specifications......29
3.6.3 12-bit DAC electrical characteristics.................. 31
3.7 Timers............................................................................34
3.8 Communication interfaces............................................. 34
3.8.1 SPI switching specifications...............................34
3.8.2 Inter-Integrated Circuit Interface (I2C) timing.....39
3.8.3 UART................................................................. 40
3.8.4 I2S/SAI switching specifications........................ 40
3.9 Human-machine interfaces (HMI)..................................44
3.9.1 TSI electrical specifications................................44
4 Dimensions........................................................................... 45
4.1 Obtaining package dimensions......................................45
5 Pinout....................................................................................45
5.1 KL16 Signal Multiplexing and Pin Assignments.............45
5.2 KL16 pinouts..................................................................48
6 Ordering parts....................................................................... 51
6.1 Determining valid orderable parts..................................51
7 Part identification...................................................................51
7.1 Description.....................................................................52
7.2 Format........................................................................... 52
7.3 Fields............................................................................. 52
7.4 Example.........................................................................52
8 Terminology and guidelines.................................................. 53
8.1 Definition: Operating requirement..................................53
8.2 Definition: Operating behavior....................................... 53
8.3 Definition: Attribute........................................................ 53
8.4 Definition: Rating........................................................... 54
8.5 Result of exceeding a rating.......................................... 54
8.6 Relationship between ratings and operating
1.1 Thermal handling ratings............................................... 4
1.2 Moisture handling ratings...............................................4
1.3 ESD handling ratings..................................................... 4
1.4 Voltage and current operating ratings............................4
2 General................................................................................. 5
2.1 AC electrical characteristics...........................................5
2.2 Nonswitching electrical specifications............................5
2.2.1 Voltage and current operating requirements......6
2.2.2 LVD and POR operating requirements.............. 6
2.2.3 Voltage and current operating behaviors...........7
2.2.4 Power mode transition operating behaviors.......8
2.2.5 Power consumption operating behaviors...........9
2.2.6 EMC radiated emissions operating behaviors... 14
2.2.7 Designing with radiated emissions in mind........15
2.2.8 Capacitance attributes....................................... 15
2.3 Switching specifications.................................................15
2.3.1 Device clock specifications................................ 15
2.3.2 General switching specifications........................16
2.4 Thermal specifications................................................... 16
2.4.1 Thermal operating requirements........................16
2.4.2 Thermal attributes..............................................17
3 Peripheral operating requirements and behaviors................ 17
3.1 Core modules................................................................ 17
3.1.1 SWD electricals .................................................17
3.2 System modules............................................................ 19
3.3 Clock modules............................................................... 19
3.3.1 MCG specifications............................................19
3.3.2 Oscillator electrical specifications...................... 21
3.4 Memories and memory interfaces................................. 23
3.4.1 Flash electrical specifications............................ 23
3.5 Security and integrity modules.......................................24
3.6 Analog............................................................................24
3.6.1 ADC electrical specifications..............................24
requirements..................................................................54
8.7 Guidelines for ratings and operating requirements........55
8.8 Definition: Typical value.................................................55
8.9 Typical value conditions.................................................56
9 Revision history.....................................................................57
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Ratings
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
Symbol
VHBM
Description
Min.
–2000
–500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
ILAT
Latch-up current at ambient temperature of 105 °C
–100
+100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
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General
1.4 Voltage and current operating ratings
Table 4. Voltage and current operating ratings
Symbol
VDD
IDD
Description
Min.
–0.3
—
Max.
3.8
Unit
Digital supply voltage
Digital supply current
IO pin input voltage
V
mA
V
120
VIO
–0.3
–25
VDD + 0.3
25
ID
Instantaneous maximum current single pin limit (applies to
all port pins)
mA
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 1. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume the output
pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
2.2 Nonswitching electrical specifications
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General
2.2.1 Voltage and current operating requirements
Table 5. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
1.71
–0.1
–0.1
Max.
3.6
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
0.1
V
0.1
V
VIH
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICIO
Input hysteresis
0.06 × VDD
-3
—
—
V
IO pin negative DC injection current — single pin
• VIN < VSS-0.3V
1
mA
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
-25
—
mA
• Negative current injection
VODPU
VRAM
Open drain pullup voltage level
VDD
1.2
VDD
—
V
V
2
VDD voltage required to retain RAM
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD
.
2.2.2 LVD and POR operating requirements
Table 6. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
—
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48
2.56
2.64
V
—
Low-voltage warning thresholds — high range
1
Table continues on the next page...
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General
Notes
Table 6. VDD supply LVD and POR operating requirements (continued)
Symbol Description
Min.
Typ.
Max.
Unit
VLVW1H
VLVW2H
VLVW3H
VLVW4H
• Level 1 falling (LVWV = 00)
2.62
2.70
2.78
V
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
• Level 4 falling (LVWV = 11)
2.72
2.82
2.92
2.80
2.90
3.00
2.88
2.98
3.08
V
V
V
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
60
—
mV
V
—
—
1
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV = 00)
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
—
1.80
1.90
2.00
2.10
40
1.86
1.96
2.06
2.16
—
V
V
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
V
• Level 4 falling (LVWV = 11)
V
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
mV
—
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
—
—
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 7. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
VOH
Output high voltage — Normal drive pad (except
RESET_b)
1, 2
VDD – 0.5
VDD – 0.5
—
—
V
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -2.5 mA
VOH
Output high voltage — High drive pad (except
RESET_b)
1, 2
VDD – 0.5
VDD – 0.5
—
—
V
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -10 mA
IOHT
VOL
Output high current total for all ports
Output low voltage — Normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
—
100
mA
1
—
—
0.5
0.5
V
V
Table continues on the next page...
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General
Table 7. Voltage and current operating behaviors (continued)
Symbol
Description
Min.
Max.
Unit
Notes
VOL
Output low voltage — High drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
1
—
—
0.5
0.5
V
V
IOLT
IIN
Output low current total for all ports
—
—
100
1
mA
μA
Input leakage current (per pin) for full temperature
range
3
IIN
IIN
Input leakage current (per pin) at 25 °C
—
—
0.025
65
μA
μA
3
3
Input leakage current (total all pins) for full
temperature range
IOZ
Hi-Z (off-state) leakage current (per pin)
Internal pullup resistors
—
1
μA
kΩ
RPU
20
50
4
1. PTB0, PTB1, PTD6, and PTD7 I/O have both high drive and normal drive capability selected by the associated
PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. The reset pin only contains an active pull down device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
3. Measured at VDD = 3.6 V
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• FEI clock mode
POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system
frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.
Table 8. Power mode transition operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tPOR After a POR event, amount of time from the
—
—
300
μs
1
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
• VLLS0 → RUN
—
106
120
μs
Table continues on the next page...
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General
Notes
Table 8. Power mode transition operating behaviors (continued)
Symbol Description
• VLLS1 → RUN
Min.
Typ.
Max.
Unit
—
105
117
μs
• VLLS3 → RUN
• LLS → RUN
—
—
—
—
47
4.5
4.5
4.5
54
5.0
5.0
5.0
μs
μs
μs
μs
• VLPS → RUN
• STOP → RUN
1. Normal boot (FTFA_FOPT[LPBOOT]=11).
2.2.5 Power consumption operating behaviors
The maximum values stated in the following table represent characterized results
equivalent to the mean plus three times the standard deviation (mean + 3 sigma).
Table 9. Power consumption operating behaviors
Symbol
IDDA
Description
Temp.
—
Typ.
—
Max
See note
—
Unit
mA
mA
Note
Analog supply current
1
2
IDD_RUNCO_ CM
Run mode current in compute
operation - 48 MHz core / 24 MHz
flash/ bus disabled, LPTMR running
using 4 MHz internal reference clock,
CoreMark® benchmark code
—
6.1
executing from flash, at 3.0 V
IDD_RUNCO
Run mode current in compute
operation - 48 MHz core / 24 MHz
flash / bus clock disabled, code of
while(1) loop executing from flash, at
3.0 V
—
—
3.8
4.6
4.4
5.2
mA
mA
3
IDD_RUN
Run mode current - 48 MHz core / 24
MHz bus and flash, all peripheral
clocks disabled, code executing from
flash, at 3.0 V
3
IDD_RUN
Run mode current - 48 MHz core / 24 at 25 °C
6.0
6.2
6.2
6.2
6.4
6.5
mA
mA
mA
3, 4
MHz bus and flash, all peripheral
clocks enabled, code executing from
at 70 °C
at 125 °C
flash, at 3.0 V
Table continues on the next page...
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General
Table 9. Power consumption operating behaviors (continued)
Symbol
IDD_WAIT
Description
Temp.
Typ.
Max
Unit
Note
Wait mode current - core disabled / 48
MHz system / 24 MHz bus / flash
disabled (flash doze enabled), all
peripheral clocks disabled, at 3.0 V
—
2.7
3.2
mA
3
IDD_WAIT
Wait mode current - core disabled / 24
MHz system / 24 MHz bus / flash
disabled (flash doze enabled), all
peripheral clocks disabled, at 3.0 V
—
2.1
2.6
mA
3
IDD_PSTOP2
Stop mode current with partial stop 2
clocking option - core and system
disabled / 10.5 MHz bus, at 3.0 V
—
—
1.5
2.0
—
mA
µA
3
5
IDD_VLPRCO _CM
Very-low-power run mode current in
compute operation - 4 MHz core / 0.8
MHz flash / bus clock disabled,
732
LPTMR running with 4 MHz internal
reference clock, CoreMark benchmark
code executing from flash, at 3.0 V
IDD_VLPRCO
IDD_VLPR
IDD_VLPR
IDD_VLPW
Very low power run mode current in
compute operation - 4 MHz core / 0.8
MHz flash / bus clock disabled, code
executing from flash, at 3.0 V
—
—
—
—
161
185
255
110
329
352
421
281
µA
µA
µA
µA
6
6
Very low power run mode current - 4
MHz core / 0.8 MHz bus and flash, all
peripheral clocks disabled, code
executing from flash, at 3.0 V
Very low power run mode current - 4
MHz core / 0.8 MHz bus and flash, all
peripheral clocks enabled, code
executing from flash, at 3.0 V
4, 6
6
Very low power wait mode current -
core disabled / 4 MHz system / 0.8
MHz bus / flash disabled (flash doze
enabled), all peripheral clocks
disabled, at 3.0 V
IDD_STOP
IDD_VLPS
IDD_LLS
Stop mode current at 3.0 V
at 25 °C
at 50 °C
at 70 °C
at 85 °C
at 105 °C
305
317
326
344
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
—
—
—
337
380
364
428
429
553
Very-low-power stop mode current at at 25 °C
3.0 V
2.69
5.54
11.80
21.13
45.85
1.98
3.13
4.14
9.80
21.94
39.13
85.45
2.65
4.35
at 50 °C
at 70 °C
at 85 °C
at 105 °C
Low leakage stop mode current at 3.0 at 25 °C
V
at 50 °C
Table continues on the next page...
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General
Note
Table 9. Power consumption operating behaviors (continued)
Symbol
Description
Temp.
Typ.
5.65
9.58
20.52
1.46
2.29
4.10
6.93
14.80
0.71
1.10
2.09
3.80
8.84
0.40
0.80
1.79
3.50
8.54
0.23
0.61
1.59
3.30
8.36
Max
8.34
14.29
31.74
2.06
3.22
5.90
10.02
22.12
1.20
1.71
3.03
5.42
12.98
0.88
1.40
2.72
5.10
12.63
0.69
1.19
2.50
4.89
12.41
Unit
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
at 70 °C
at 85 °C
at 105 °C
IDD_VLLS3
Very low-leakage stop mode 3 current at 25 °C
—
—
—
7
at 3.0 V
at 50 °C
at 70 °C
at 85 °C
at 105 °C
IDD_VLLS1
IDD_VLLS0
IDD_VLLS0
Very low-leakage stop mode 1 current at 25 °C
at 3.0V
at 50 °C
at 70 °C
at 85 °C
at 105 °C
Very low-leakage stop mode 0 current at 25 °C
(SMC_STOPCTRL[PORPO] = 0) at
3.0 V
at 50 °C
at 70 °C
at 85 °C
at 105 °C
Very low-leakage stop mode 0 current at 25 °C
(SMC_STOPCTRL[PORPO] = 1) at
3.0 V
at 50 °C
at 70 °C
at 85 °C
at 105 °C
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.
See each module's specification for its supply current.
2. MCG configured for PEE mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized
for balanced.
3. MCG configured for FEI mode.
4. Incremental current consumption from peripheral activity is not included.
5. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 6.40 with optimization level high, optimized
for balanced.
6. MCG configured for BLPI mode.
7. No brownout.
Table 10. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz
4 MHz internal reference clock (IRC) adder.
Measured by entering STOP or VLPS mode
with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
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Freescale Semiconductor, Inc.
General
Table 10. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN32KHz
IEREFSTEN4MHz
IEREFSTEN32KHz
32 kHz internal reference clock (IRC) adder.
Measured by entering STOP mode with the
32 kHz IRC enabled.
52
52
52
52
52
52
µA
External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS mode
with the crystal enabled.
206
228
237
245
251
258
µA
nA
External 32 kHz crystal clock
adder by means of the
OSC0_CR[EREFSTEN and
EREFSTEN] bits. Measured
by entering all modes with
the crystal enabled.
VLLS1
VLLS3
LLS
440
440
490
510
510
22
490
490
490
560
560
22
540
540
540
560
560
22
560
560
560
560
560
22
570
570
570
610
610
22
580
580
680
680
680
22
VLPS
STOP
ICMP
CMP peripheral adder measured by placing
the device in VLLS1 mode with CMP
enabled using the 6-bit DAC and a single
external input for compare. Includes 6-bit
DAC power consumption.
µA
nA
IRTC
RTC peripheral adder measured by placing
the device in VLLS1 mode with external 32
kHz crystal enabled by means of the
RTC_CR[OSCE] bit and the RTC ALARM
set for 1 minute. Includes ERCLK32K (32
kHz external crystal) power consumption.
432
66
357
66
388
66
475
66
532
66
810
66
IUART
UART peripheral adder
measured by placing the
device in STOP or VLPS
mode with selected clock
source waiting for RX data at
115200 baud rate. Includes
selected clock source power
consumption.
MCGIRCLK
(4 MHz
internal
reference
clock)
µA
OSCERCLK 214
(4 MHz
external
237
86
246
86
254
86
260
86
268
86
crystal)
ITPM
TPM peripheral adder
MCGIRCLK
(4 MHz
internal
reference
clock)
86
µA
measured by placing the
device in STOP or VLPS
mode with selected clock
source configured for output
compare generating 100 Hz
clock signal. No load is
placed on the I/O generating
the clock signal. Includes
selected clock source and
I/O switching currents.
OSCERCLK 235
(4 MHz
external
256
265
274
280
287
crystal)
IBG
Bandgap adder when BGEN bit is set and
device is placed in VLPx, LLS, or VLLSx
mode.
45
45
45
45
45
45
µA
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
366
366
366
366
366
366
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Freescale Semiconductor, Inc.
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General
Unit
Table 10. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
50 70
-40
25
85
105
placing the device in STOP or VLPS mode.
ADC is configured for low power mode using
the internal clock and continuous
conversions.
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE for run mode, and BLPE for VLPR mode
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
Run Mode Current VS Core Frequency
Temperature = 25, VDD = 3, CACHE = Enable, Code Residence = Flash, Clocking Mode = FBE
7.00E-03
6.00E-03
5.00E-03
4.00E-03
All Peripheral CLK Gates
All Off
All On
3.00E-03
2.00E-03
1.00E-03
000.00E+00
CLK Ratio
'1-2
'1-1
1
'1-1
2
'1-1
3
'1-1
4
'1-1
6
'1-1
12
'1-1
24
Flash-Core
48
Core Freq (MHz)
Figure 2. Run mode supply current vs. core frequency
Kinetis KL16 Sub-Family, Rev5 08/2014.
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Freescale Semiconductor, Inc.
General
400.00E-06
350.00E-06
300.00E-06
250.00E-06
200.00E-06
150.00E-06
100.00E-06
50.00E-06
All Off
All On
000.00E+00
CLK Ratio
Flash-Core
Core Freq (MHz)
1
2
4
Figure 3. VLPR mode current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 11. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band
Typ.
Unit
Notes
(MHz)
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC level
0.15–50
50–150
16
18
11
13
M
dBμV
dBμV
dBμV
dBμV
—
1, 2
VRE3
150–500
500–1000
0.15–1000
VRE4
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
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Freescale Semiconductor, Inc.
General
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 8 MHz (crystal), fSYS = 48 MHz, fBUS = 24 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.freescale.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 12. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN
Input capacitance
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 13. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Normal run mode
fSYS
fBUS
fFLASH
fLPTMR
System and core clock
Bus clock
—
—
—
—
48
24
24
24
MHz
MHz
MHz
MHz
Flash clock
LPTMR clock
VLPR and VLPS modes1
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
—
4
1
MHz
MHz
MHz
MHz
MHz
fFLASH
fLPTMR
fERCLK
Flash clock
LPTMR clock2
1
24
16
External reference clock
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Freescale Semiconductor, Inc.
General
Table 13. Device clock specifications (continued)
Symbol
Description
Min.
—
Max.
Unit
MHz
MHz
fLPTMR_ERCLK LPTMR external reference clock
16
16
fosc_hi_2
Oscillator crystal or resonator frequency — high frequency
—
mode (high range) (MCG_C2[RANGE]=1x)
fTPM
TPM asynchronous clock
—
—
8
8
MHz
MHz
fUART0
UART0 asynchronous clock
1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS was entered from RUN
or from VLPR.
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
2.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO and
UART signals.
Table 14. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) —
Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
Port rise and fall time
16
—
—
ns
ns
2
3
36
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. 75 pF load
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 15. Thermal operating requirements
Symbol
TJ
Description
Min.
Max.
125
Unit
°C
Die junction temperature
Ambient temperature
–40
–40
TA
105
°C
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Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors
2.4.2 Thermal attributes
Table 16. Thermal attributes
Board type
Symbol
Description
64 LQFP 48 QFN 32 QFN
Unit
Notes
Single-layer (1S)
RθJA
Thermal resistance, junction to
ambient (natural convection)
71
53
59
46
35
21
6
83
30
68
24
12
2.3
5
98
34
82
28
13
2.3
8
°C/W
1
Four-layer (2s2p)
RθJA
Thermal resistance, junction to
ambient (natural convection)
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Single-layer (1S)
RθJMA Thermal resistance, junction to
ambient (200 ft./min. air speed)
Four-layer (2s2p)
RθJMA Thermal resistance, junction to
ambient (200 ft./min. air speed)
—
—
—
RθJB
RθJC
ΨJT
Thermal resistance, junction to
board
2
3
4
Thermal resistance, junction to
case
Thermal characterization
parameter, junction to package
top outside center (natural
convection)
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test
Method Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material
between the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 17. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
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Peripheral operating requirements and behaviors
Table 17. SWD full voltage range electricals (continued)
Symbol
Description
Min.
Max.
Unit
J1
SWD_CLK frequency of operation
• Serial wire debug
0
25
—
MHz
ns
J2
J3
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
1/J1
20
—
ns
J4
J9
SWD_CLK rise and fall times
—
10
0
3
ns
ns
ns
ns
ns
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
—
32
—
J10
J11
J12
—
5
J2
J4
J3
J3
SWD_CLK (input)
J4
Figure 4. Serial wire clock input timing
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
J9
J10
Input data valid
J11
Output data valid
J12
J11
Output data valid
Figure 5. Serial wire data timing
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Freescale Semiconductor, Inc.
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Peripheral operating requirements and behaviors
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 18. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
—
39.0625
0.6
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using C3[SCTRIM] and C4[SCFTRIM]
0.3
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
+0.5/-0.7
0.4
3
%fdco
%fdco
1, 2
1, 2
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70 °C
1.5
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25 °C
—
—
4
—
3
MHz
Δfintf_ft
Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
+1/-2
%fintf_ft
2
fintf_t
Internal reference frequency (fast clock) —
user trimmed at nominal VDD and 25 °C
3
—
—
—
5
MHz
kHz
kHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
FLL
ffll_ref
fdco
FLL reference frequency range
31.25
20
—
39.0625
25
kHz
DCO output
Low range (DRS = 00)
20.97
MHz
3, 4
5, 6
frequency range
640 × ffll_ref
Mid range (DRS = 01)
1280 × ffll_ref
40
—
41.94
23.99
48
—
MHz
MHz
fdco_t_DMX3 DCO output
Low range (DRS = 00)
frequency
2
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 18. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
732 × ffll_ref
Mid range (DRS = 01)
1464 × ffll_ref
—
47.97
—
MHz
Jcyc_fll
FLL period jitter
• fVCO = 48 MHz
—
—
180
—
—
1
ps
7
8
tfll_acquire FLL target frequency acquisition time
ms
PLL
fvco
Ipll
VCO operating frequency
48.0
—
—
100
—
MHz
µA
PLL operating current
9
9
1060
• PLL at 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 48)
=
=
Ipll
PLL operating current
—
600
—
—
µA
• PLL at 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref
2 MHz, VDIV multiplier = 24)
fpll_ref
PLL reference frequency range
PLL period jitter (RMS)
• fvco = 48 MHz
2.0
4.0
MHz
Jcyc_pll
10
10
—
—
120
50
—
—
ps
ps
• fvco = 100 MHz
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
• fvco = 48 MHz
—
—
1350
600
—
—
ps
ps
• fvco = 100 MHz
Dlock
Dunl
Lock entry frequency tolerance
Lock exit frequency tolerance
Lock detector detection time
1.49
4.47
—
—
—
—
2.98
5.97
150 × 10-6
+ 1075(1/
%
%
s
tpll_lock
11
fpll_ref
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft
.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency deviation
(Δfdco_t) over voltage and temperature must be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
9. Excludes any oscillator currents that are also consuming power while PLL is in operation.
10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics
of each PCB and results will vary.
11. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
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Peripheral operating requirements and behaviors
3.3.2 Oscillator electrical specifications
3.3.2.1 Oscillator DC electrical specifications
Table 19. Oscillator DC electrical specifications
Symbol Description
VDD Supply voltage
Min.
Typ.
Max.
Unit
Notes
1.71
—
3.6
V
IDDOSC Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
IDDOSC Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
—
—
25
400
500
2.5
3
—
—
—
—
—
—
μA
μA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
μA
mA
mA
mA
• 24 MHz
• 32 MHz
4
Cx
Cy
RF
EXTAL load capacitance
XTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-
power mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain
mode (HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 19. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
—
0
—
kΩ
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
—
—
—
—
0.6
VDD
0.6
—
—
—
—
V
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
3.3.2.2 Oscillator frequency specifications
Table 20. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
fosc_hi_1 Oscillator crystal or resonator frequency — high-
frequency mode (low range)
3
8
—
—
8
MHz
MHz
(MCG_C2[RANGE]=01)
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency mode (high range)
32
(MCG_C2[RANGE]=1x)
fec_extal Input clock frequency (external clock mode)
tdc_extal Input clock duty cycle (external clock mode)
—
40
—
—
50
48
60
—
MHz
%
1, 2
3, 4
tcst
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), low-power mode
(HGO=0)
Crystal startup time — 8 MHz high-frequency
(MCG_C2[RANGE]=01), high-gain mode
(HGO=1)
—
1
—
ms
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Freescale Semiconductor, Inc.
Kinetis KL16 Sub-Family, Rev5 08/2014.
Peripheral operating requirements and behaviors
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps
are active and do not include command overhead.
Table 21. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
13
Max.
18
Unit
μs
Notes
thvpgm4 Longword Program high-voltage time
thversscr Sector Erase high-voltage time
—
1
—
113
452
ms
ms
thversall
Erase All high-voltage time
—
52
1
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 22. Flash command timing specifications
Symbol Description
Min.
—
—
—
—
—
—
—
—
—
—
Typ.
—
Max.
60
Unit
μs
Notes
trd1sec1k Read 1s Section execution time (flash sector)
tpgmchk Program Check execution time
1
1
—
45
μs
trdrsrc
tpgm4
tersscr
trd1all
trdonce
Read Resource execution time
Program Longword execution time
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
30
μs
1
65
14
—
145
114
1.8
25
μs
—
2
ms
ms
μs
—
1
—
tpgmonce Program Once execution time
65
88
—
—
μs
—
2
tersall
Erase All Blocks execution time
650
30
ms
μs
tvfykey
Verify Backdoor Access Key execution time
1
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Peripheral operating requirements and behaviors
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3 Flash high voltage current behaviors
Table 23. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
3.4.1.4 Reliability specifications
Table 24. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
—
—
2
20
100
50 K
10 K
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ Tj ≤ 125 °C.
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
The 16-bit accuracy specifications listed in Table 25 and Table 26 are achievable on the
differential pins ADCx_DP0, ADCx_DM0.
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications.
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Peripheral operating requirements and behaviors
3.6.1.1 16-bit ADC operating conditions
Table 25. 16-bit ADC operating conditions
Symbol Description
VDDA Supply voltage
ΔVDDA Supply voltage
Conditions
Min.
1.71
-100
-100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
Absolute
—
—
2
Delta to VDD (VDD – VDDA
)
0
+100
+100
VDDA
mV
mV
V
ΔVSSA
Ground voltage Delta to VSS (VSS – VSSA
)
0
2
VREFH
ADC reference
voltage high
VDDA
3
VREFL
VADIN
ADC reference
voltage low
VSSA
VSSA
VSSA
V
V
3
Input voltage
• 16-bit differential mode
• All other modes
• 16-bit mode
VREFL
VREFL
—
—
31/32 *
VREFH
—
VREFH
CADIN
Input
capacitance
—
—
8
4
10
5
pF
—
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input series
resistance
—
—
2
5
5
kΩ
kΩ
—
4
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
—
fADCK
fADCK
Crate
ADC conversion ≤ 13-bit mode
clock frequency
1.0
2.0
—
—
18.0
12.0
MHz
MHz
5
5
6
ADC conversion 16-bit mode
clock frequency
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
20.000
37.037
—
—
818.330
461.467
Ksps
Ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
6
rate
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied
to VSSA
.
4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS/CAS time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
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Peripheral operating requirements and behaviors
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 6. ADC input impedance equivalency diagram
3.6.1.2 16-bit ADC electrical characteristics
Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
6.1
7.3
9.5
Unit
mA
Notes
IDDA_ADC Supply current
—
3
ADC
asynchronous
clock source
• ADLPC = 1, ADHSC =
0
2.4
4.0
5.2
6.2
MHz
MHz
MHz
MHz
tADACK
=
1/fADACK
2.4
• ADLPC = 1, ADHSC =
1
3.0
fADACK
4.4
• ADLPC = 0, ADHSC =
0
• ADLPC = 0, ADHSC =
1
Sample Time
See Reference Manual chapter for sample times
TUE
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
5
1.4
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
DNL
Differential non-
linearity
• 12-bit modes
—
0.7
–1.1 to
+1.9
LSB4
5
• <12-bit modes
• 12-bit modes
• <12-bit modes
—
—
—
0.2
1.0
0.5
–0.3 to 0.5
INL
Integral non-
linearity
–2.7 to
+1.9
LSB4
5
–0.7 to
+0.5
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• 16-bit modes
• ≤13-bit modes
—
—
—
—
–4
–1.4
–1 to 0
—
–5.4
–1.8
—
LSB4
LSB4
VADIN
VDDA
=
5
Quantization
error
0.5
ENOB
Effective number 16-bit differential mode
6
12.8
11.9
14.5
13.8
—
—
bits
bits
of bits
• Avg = 32
• Avg = 4
12.2
11.4
13.9
13.1
—
—
bits
bits
16-bit single-ended mode
• Avg = 32
• Avg = 4
Signal-to-noise
plus distortion
See ENOB
SINAD
THD
6.02 × ENOB + 1.76
dB
Total harmonic
distortion
16-bit differential mode
• Avg = 32
7
7
—
—
-94
-85
—
—
dB
dB
16-bit single-ended mode
• Avg = 32
SFDR
Spurious free
dynamic range
16-bit differential mode
• Avg = 32
82
78
95
90
—
—
dB
dB
16-bit single-ended mode
• Avg = 32
EIL
Input leakage
error
IIn × RAS
mV
IIn =
leakage
current
(refer to
the MCU's
voltage
and
current
operating
ratings)
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 26. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
Temp sensor
slope
Across the full temperature
range of the device
1.55
1.62
1.69
mV/°C
8
VTEMP25 Temp sensor
voltage
25 °C
706
716
726
mV
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
12.30
12.00
Averaging of 8 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 7. Typical ENOB vs. ADC_CLK for 16-bit differential mode
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Peripheral operating requirements and behaviors
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
12.75
12.50
12.25
12.00
11.75
11.50
11.25
11.00
Averaging of 4 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 8. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
3.6.2 CMP and 6-bit DAC electrical specifications
Table 27. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
Supply current, High-speed mode (EN=1,
PMODE=1)
—
200
μA
IDDLS
VAIN
VAIO
VH
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
VSS – 0.3
—
—
—
—
20
VDD
20
μA
V
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
mV
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
• CR0[HYSTCTR] = 01
10
20
30
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
Output low
VDD – 0.5
—
—
50
—
0.5
200
V
V
—
Propagation delay, high-speed mode (EN=1,
PMODE=1)
20
ns
tDLS
Propagation delay, low-speed mode (EN=1,
PMODE=0)
Analog comparator initialization delay2
80
—
250
—
600
40
ns
μs
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 27. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
IDAC6b
INL
Description
Min.
—
Typ.
7
Max.
—
Unit
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
6-bit DAC differential non-linearity
μA
–0.5
–0.3
—
0.5
0.3
LSB3
LSB
DNL
—
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
0.08
0.07
0.06
HYSTCTR
Setting
0.05
0.04
0.03
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 9. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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Peripheral operating requirements and behaviors
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
3.6.3.1 12-bit DAC operating requirements
Table 28. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
CL
Desciption
Min.
1.71
1.13
—
Max.
3.6
3.6
100
1
Unit
V
Notes
Supply voltage
Reference voltage
Output load capacitance
Output load current
V
1
2
pF
mA
IL
—
1. The DAC reference can be selected to be VDDA or VREFH.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC
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Peripheral operating requirements and behaviors
3.6.3.2 12-bit DAC operating behaviors
Table 29. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
250
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
100
15
900
200
30
μA
μs
μs
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-speed
mode
0.7
1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
—
—
—
—
—
—
100
mV
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
VDACR
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR > 2
V
Differential non-linearity error — VDACR
VREF_OUT
=
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
Rop
SR
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance (load = 3 kΩ)
Slew rate -80h→ F7Fh→ 80h
3.7
—
μV/C
%FSR/C
Ω
6
0.000421
—
—
250
V/μs
• High power (SPHP
)
1.2
1.7
—
—
• Low power (SPLP
3dB bandwidth
)
0.05
0.12
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC set
to 0x800, temperature range is across the full range of the device
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Peripheral operating requirements and behaviors
8
6
4
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 11. Typical INL error vs. digital code
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Peripheral operating requirements and behaviors
1.499
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
85
25
105
125
-40
Temperature °C
Figure 12. Offset at half scale vs. temperature
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
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Peripheral operating requirements and behaviors
3.8.1 SPI switching specifications
The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master
and slave operations. Many of the transfer attributes are programmable. The following
tables provide timing characteristics for classic SPI timing modes. See the SPI chapter
of the chip's Reference Manual for information about the modified transfer formats
used for communicating with slower peripheral devices.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted,
as well as input signal transitions of 3 ns and a 30 pF maximum load on all SPI pins.
Table 30. SPI master mode timing on slew rate disabled pads
Num.
Symbol Description
Min.
Max.
Unit
Hz
Note
1
2
fop
Frequency of operation
fperiph/2048
2 x tperiph
fperiph/2
1
2
tSPSCK
SPSCK period
2048 x
tperiph
ns
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
1024 x
tperiph
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
18
0
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
15
8
tv
—
0
9
tHO
tRI
—
10
—
tperiph - 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
Table 31. SPI master mode timing on slew rate enabled pads
Num.
Symbol Description
Min.
Max.
Unit
Hz
Note
1
2
fop
Frequency of operation
fperiph/2048
2 x tperiph
fperiph/2
1
2
tSPSCK
SPSCK period
2048 x
tperiph
ns
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
1024 x
tperiph
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
96
0
—
—
ns
ns
—
—
Table continues on the next page...
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Peripheral operating requirements and behaviors
Table 31. SPI master mode timing on slew rate enabled pads (continued)
Num.
Symbol Description
Min.
—
Max.
52
Unit
ns
Note
—
8
9
tv
Data valid (after SPSCK edge)
tHO
tRI
Data hold time (outputs)
Rise time input
0
—
ns
—
10
—
tperiph - 25
ns
—
tFI
Fall time input
11
tRO
tFO
Rise time output
Fall time output
—
36
ns
—
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 13. SPI master mode timing (CPHA = 0)
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Peripheral operating requirements and behaviors
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
LSB IN
MSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER MSB OUT
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 14. SPI master mode timing (CPHA = 1)
Table 32. SPI slave mode timing on slew rate disabled pads
Num.
1
Symbol Description
Min.
Max.
fperiph/4
—
Unit
Hz
Note
1
fop
tSPSCK
tLead
tLag
Frequency of operation
0
2
SPSCK period
Enable lead time
Enable lag time
4 x tperiph
ns
2
3
1
—
tperiph
tperiph
ns
—
—
—
—
—
3
4
1
—
5
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
—
6
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
2.5
3.5
—
—
—
0
—
ns
7
—
ns
8
tperiph
tperiph
31
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
—
ns
—
tperiph - 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
Kinetis KL16 Sub-Family, Rev5 08/2014.
37
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 33. SPI slave mode timing on slew rate enabled pads
Num.
1
Symbol Description
Min.
Max.
fperiph/4
—
Unit
Hz
Note
1
fop
tSPSCK
tLead
tLag
Frequency of operation
0
2
SPSCK period
Enable lead time
Enable lag time
4 x tperiph
ns
2
3
1
—
tperiph
tperiph
ns
—
—
—
—
—
3
4
1
—
5
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
—
6
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
2
7
—
ns
7
—
ns
8
—
—
—
0
tperiph
tperiph
122
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
—
ns
—
tperiph - 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
36
ns
—
Fall time output
1. For SPI0 fperiph is the bus clock (fBUS). For SPI1 fperiph is the system clock (fSYS).
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
SS
(INPUT)
2
12
12
13
13
4
SPSCK
(CPOL=0)
(INPUT)
5
5
3
SPSCK
(CPOL=1)
(INPUT)
9
8
10
11
11
see
note
SEE
NOTE
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
6
MOSI
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
NOTE: Not defined
Figure 15. SPI slave mode timing (CPHA = 0)
38
Freescale Semiconductor, Inc.
Kinetis KL16 Sub-Family, Rev5 08/2014.
Peripheral operating requirements and behaviors
SS
(INPUT)
4
2
12
12
13
3
SPSCK
(CPOL=0)
(INPUT)
5
5
13
SPSCK
(CPOL=1)
(INPUT)
11
9
10
SLAVE MSB OUT
see
note
MISO
(OUTPUT)
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
8
6
7
MOSI
(INPUT)
MSB IN
LSB IN
NOTE: Not defined
Figure 16. SPI slave mode timing (CPHA = 1)
3.8.2 Inter-Integrated Circuit Interface (I2C) timing
Table 34. I2C timing
Characteristic
Symbol
Standard Mode
Fast Mode
Unit
Minimum Maximum Minimum Maximum
SCL Clock Frequency
fSCL
0
4
100
—
0
4001
—
kHz
µs
Hold time (repeated) START condition. tHD; STA
After this period, the first clock pulse is
generated.
0.6
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.3
0.6
0.6
—
—
—
µs
µs
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
Data hold time for I2C bus devices
tHD; DAT
tSU; DAT
tr
02
2505
—
3.453
—
04
1003, 6
20 +0.1Cb
20 +0.1Cb
0.6
0.92
—
µs
ns
ns
ns
µs
µs
Data set-up time
7
6
Rise time of SDA and SCL signals
Fall time of SDA and SCL signals
Set-up time for STOP condition
1000
300
—
300
300
—
tf
—
tSU; STO
tBUF
4
Bus free time between STOP and
START condition
4.7
—
1.3
—
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The maximum SCL Clock Frequency in Fast mode with maximum bus loading can only achieved when using the High
drive pins (see Voltage and current operating behaviors) or when using the Normal drive pins and VDD ≥ 2.7 V
Kinetis KL16 Sub-Family, Rev5 08/2014.
39
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
2. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
3. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
4. Input signal Slew = 10 ns and Output Load = 50 pF
5. Set-up time in slave-transmitter mode is 1 IPBus clock period, if the TX FIFO is empty.
6. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such
a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax + tSU;
DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is released.
7. Cb = total capacitance of the one bus line in pF.
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tSU; STO
HD; STA
S
SR
P
S
tHD; DAT
tHIGH
Figure 17. Timing definition for fast and standard mode devices on the I2C bus
3.8.3 UART
See General switching specifications.
3.8.4 I2S/SAI switching specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks are
driven) and slave mode (clocks are input). All timing is given for noninverted serial
clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame sync
(TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame sync
have been inverted, all the timing remains valid by inverting the bit clock signal
(BCLK) and/or the frame sync (FS) signal shown in the following figures.
40
Kinetis KL16 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
3.8.4.1 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 35. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
40
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK (as an input) pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
45%
80
55%
—
MCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
55%
15.5
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
19
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
26
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 18. I2S/SAI timing — master modes
Kinetis KL16 Sub-Family, Rev5 08/2014.
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Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 36. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
80
3.6
—
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
ns
S12
S13
S14
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
10
2
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
0
33
—
—
—
28
ns
ns
ns
ns
ns
10
2
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 19. I2S/SAI timing — slave modes
3.8.4.2 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
42
Kinetis KL16 Sub-Family, Rev5 08/2014.
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 37. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes
(full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
62.5
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
45%
250
55%
—
MCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
55%
45
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
45
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S4
S5
S7
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S8
I2S_TXD
I2S_RXD
S9
S10
Figure 20. I2S/SAI timing — master modes
Table 38. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full
voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
1.71
250
3.6
—
V
S11
ns
Table continues on the next page...
Kinetis KL16 Sub-Family, Rev5 08/2014.
43
Freescale Semiconductor, Inc.
Peripheral operating requirements and behaviors
Table 38. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
(continued)
Num.
S12
Characteristic
Min.
Max.
55%
Unit
MCLK period
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
(input)
S13
S14
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
S15
S16
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
—
0
ns
ns
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output
invalid
—
S17
S18
S19
I2S_RXD setup before I2S_RX_BCLK
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
30
—
—
—
72
ns
ns
ns
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 21. I2S/SAI timing — slave modes
3.9 Human-machine interfaces (HMI)
3.9.1 TSI electrical specifications
Table 39. TSI electrical specifications
Symbol
Description
Min.
Typ.
Max.
Unit
TSI_RUNF
Fixed power consumption in run mode
—
100
—
µA
Table continues on the next page...
44
Freescale Semiconductor, Inc.
Kinetis KL16 Sub-Family, Rev5 08/2014.
Dimensions
Table 39. TSI electrical specifications (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
TSI_RUNV
Variable power consumption in run mode
(depends on oscillator's current selection)
1.0
—
128
µA
TSI_EN
TSI_DIS
Power consumption in enable mode
Power consumption in disable mode
TSI analog enable time
—
—
100
1.2
66
—
—
µA
µA
µs
pF
V
TSI_TEN
—
—
TSI_CREF
TSI_DVOLT
TSI reference capacitor
—
1.0
—
—
Voltage variation of VP & VM around nominal
values
0.19
1.03
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to freescale.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
32-pin QFN
Then use this document number
98ASA00473D
48-pin QFN
64-pin LQFP
98ASA00466D
98ASS23234W
5 Pinout
5.1 KL16 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is
responsible for selecting which ALT functionality is available on each pin.
Kinetis KL16 Sub-Family, Rev5 08/2014.
45
Freescale Semiconductor, Inc.
Pinout
64
48
32
QFN
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
UART1_TX
UART1_RX
ALT4
ALT5
ALT6
I2C1_SDA
I2C1_SCL
ALT7
LQFP QFN
1
—
1
PTE0
DISABLED
PTE0
SPI1_MISO
SPI1_MOSI
RTC_
CLKOUT
CMP0_OUT
SPI1_MISO
2
3
4
5
—
1
2
—
—
3
PTE1
VDD
DISABLED
VDD
PTE1
VDD
2
VSS
VSS
VSS
3
PTE16
ADC0_DP1/
ADC0_SE1
ADC0_DP1/
ADC0_SE1
PTE16
PTE17
PTE18
PTE19
PTE20
PTE21
PTE22
PTE23
SPI0_PCS0
SPI0_SCK
SPI0_MOSI
SPI0_MISO
UART2_TX
UART2_RX
TPM_CLKIN0
TPM_CLKIN1
I2C0_SDA
6
7
4
5
4
5
PTE17
PTE18
PTE19
PTE20
PTE21
PTE22
PTE23
ADC0_DM1/
ADC0_SE5a
ADC0_DM1/
ADC0_SE5a
LPTMR0_
ALT3
ADC0_DP2/
ADC0_SE2
ADC0_DP2/
ADC0_SE2
SPI0_MISO
SPI0_MOSI
8
6
6
ADC0_DM2/
ADC0_SE6a
ADC0_DM2/
ADC0_SE6a
I2C0_SCL
9
7
—
—
—
—
ADC0_DP0/
ADC0_SE0
ADC0_DP0/
ADC0_SE0
TPM1_CH0
TPM1_CH1
TPM2_CH0
TPM2_CH1
UART0_TX
UART0_RX
UART2_TX
UART2_RX
10
11
12
8
ADC0_DM0/
ADC0_SE4a
ADC0_DM0/
ADC0_SE4a
—
—
ADC0_DP3/
ADC0_SE3
ADC0_DP3/
ADC0_SE3
ADC0_DM3/
ADC0_SE7a
ADC0_DM3/
ADC0_SE7a
13
14
15
16
17
9
7
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
VDDA
VREFH
VREFL
VSSA
10
11
12
13
—
—
8
—
PTE29
CMP0_IN5/
ADC0_SE4b
CMP0_IN5/
ADC0_SE4b
PTE29
PTE30
TPM0_CH2
TPM0_CH3
TPM_CLKIN0
TPM_CLKIN1
18
14
9
PTE30
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
DAC0_OUT/
ADC0_SE23/
CMP0_IN4
19
20
21
22
23
24
25
26
27
—
15
16
17
18
19
20
21
—
—
—
—
10
11
12
13
14
—
PTE31
PTE24
PTE25
PTA0
PTA1
PTA2
PTA3
PTA4
PTA5
DISABLED
DISABLED
DISABLED
SWD_CLK
DISABLED
DISABLED
SWD_DIO
NMI_b
PTE31
PTE24
PTE25
PTA0
PTA1
PTA2
PTA3
PTA4
PTA5
TPM0_CH4
TPM0_CH0
TPM0_CH1
TPM0_CH5
TPM2_CH0
TPM2_CH1
TPM0_CH0
TPM0_CH1
TPM0_CH2
I2C0_SCL
I2C0_SDA
TSI0_CH1
TSI0_CH2
TSI0_CH3
TSI0_CH4
TSI0_CH5
SWD_CLK
UART0_RX
UART0_TX
I2C1_SCL
I2C1_SDA
SWD_DIO
NMI_b
DISABLED
I2S0_TX_
BCLK
28
29
30
—
—
22
—
—
15
PTA12
PTA13
VDD
DISABLED
DISABLED
VDD
PTA12
PTA13
TPM1_CH0
TPM1_CH1
I2S0_TXD0
I2S0_TX_FS
VDD
46
Freescale Semiconductor, Inc.
Kinetis KL16 Sub-Family, Rev5 08/2014.
Pinout
64
48
32
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP QFN
QFN
31
32
33
23
24
25
16
17
18
VSS
VSS
VSS
PTA18
PTA19
EXTAL0
XTAL0
EXTAL0
XTAL0
PTA18
UART1_RX
UART1_TX
TPM_CLKIN0
TPM_CLKIN1
PTA19
LPTMR0_
ALT1
34
35
26
27
19
20
PTA20
RESET_b
PTA20
RESET_b
PTB0/
LLWU_P5
ADC0_SE8/
TSI0_CH0
ADC0_SE8/
TSI0_CH0
PTB0/
LLWU_P5
I2C0_SCL
I2C0_SDA
I2C0_SCL
I2C0_SDA
TPM1_CH0
TPM1_CH1
TPM2_CH0
TPM2_CH1
36
37
38
28
29
30
21
—
—
PTB1
PTB2
PTB3
ADC0_SE9/
TSI0_CH6
ADC0_SE9/
TSI0_CH6
PTB1
PTB2
PTB3
ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
ADC0_SE13/
TSI0_CH8
ADC0_SE13/
TSI0_CH8
39
40
41
31
32
—
—
—
—
PTB16
PTB17
PTB18
TSI0_CH9
TSI0_CH10
TSI0_CH11
TSI0_CH9
TSI0_CH10
TSI0_CH11
PTB16
PTB17
PTB18
SPI1_MOSI
SPI1_MISO
UART0_RX
UART0_TX
TPM2_CH0
TPM_CLKIN0 SPI1_MISO
TPM_CLKIN1 SPI1_MOSI
I2S0_TX_
BCLK
42
43
—
—
—
PTB19
PTC0
TSI0_CH12
TSI0_CH12
PTB19
PTC0
TPM2_CH1
EXTRG_IN
I2S0_TX_FS
CMP0_OUT
33
ADC0_SE14/
TSI0_CH13
ADC0_SE14/
TSI0_CH13
I2S0_TXD0
I2S0_TXD0
44
34
22
PTC1/
LLWU_P6/
RTC_CLKIN
ADC0_SE15/
TSI0_CH14
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6/
RTC_CLKIN
I2C1_SCL
I2C1_SDA
TPM0_CH0
TPM0_CH1
45
46
35
36
23
24
PTC2
ADC0_SE11/
TSI0_CH15
ADC0_SE11/
TSI0_CH15
PTC2
I2S0_TX_FS
PTC3/
LLWU_P7
DISABLED
PTC3/
LLWU_P7
UART1_RX
UART1_TX
TPM0_CH2
CLKOUT
I2S0_TX_
BCLK
47
48
49
—
—
37
—
—
25
VSS
VDD
VSS
VSS
VDD
VDD
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0
SPI0_SCK
SPI0_MOSI
TPM0_CH3
I2S0_RXD0
I2S0_MCLK
50
51
38
39
26
27
PTC5/
LLWU_P9
DISABLED
CMP0_IN0
PTC5/
LLWU_P9
LPTMR0_
ALT2
CMP0_OUT
I2S0_MCLK
PTC6/
LLWU_P10
CMP0_IN0
PTC6/
LLWU_P10
EXTRG_IN
I2S0_RX_
BCLK
SPI0_MISO
SPI0_MOSI
52
53
54
40
—
—
28
—
—
PTC7
PTC8
PTC9
CMP0_IN1
CMP0_IN2
CMP0_IN3
CMP0_IN1
CMP0_IN2
CMP0_IN3
PTC7
PTC8
PTC9
SPI0_MISO
I2C0_SCL
I2C0_SDA
I2S0_RX_FS
I2S0_MCLK
TPM0_CH4
TPM0_CH5
I2S0_RX_
BCLK
55
56
57
58
59
—
—
41
42
43
—
—
—
—
—
PTC10
PTC11
PTD0
PTD1
PTD2
DISABLED
DISABLED
DISABLED
ADC0_SE5b
DISABLED
PTC10
PTC11
PTD0
PTD1
PTD2
I2C1_SCL
I2C1_SDA
SPI0_PCS0
SPI0_SCK
SPI0_MOSI
I2S0_RX_FS
I2S0_RXD0
TPM0_CH0
TPM0_CH1
TPM0_CH2
ADC0_SE5b
UART2_RX
SPI0_MISO
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Freescale Semiconductor, Inc.
Pinout
64
48
32
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP QFN
QFN
60
61
44
45
—
PTD3
DISABLED
DISABLED
PTD3
SPI0_MISO
SPI1_PCS0
UART2_TX
UART2_RX
TPM0_CH3
TPM0_CH4
SPI0_MOSI
29
PTD4/
PTD4/
LLWU_P14
LLWU_P14
62
63
46
47
30
31
PTD5
ADC0_SE6b
ADC0_SE7b
ADC0_SE6b
ADC0_SE7b
PTD5
SPI1_SCK
UART2_TX
UART0_RX
TPM0_CH5
PTD6/
LLWU_P15
PTD6/
LLWU_P15
SPI1_MOSI
SPI1_MISO
SPI1_MOSI
64
48
32
PTD7
DISABLED
PTD7
SPI1_MISO
UART0_TX
5.2 KL16 pinouts
The following figures show the pinout diagrams for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see KL16 Signal Multiplexing and Pin Assignments.
48
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Pinout
PTE0
PTE1
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
2
VSS
VDD
3
PTC3/LLWU_P7
PTC2
VSS
4
PTE16
PTE17
PTE18
PTE19
PTE20
PTE21
PTE22
PTE23
VDDA
VREFH
VREFL
VSSA
5
PTC1/LLWU_P6/RTC_CLKIN
6
PTC0
7
PTB19
PTB18
PTB17
PTB16
PTB3
8
9
10
11
12
13
14
15
16
PTB2
PTB1
PTB0/LLWU_P5
PTA20
PTA19
Figure 22. KL16 64-pin LQFP pinout diagram
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Freescale Semiconductor, Inc.
Pinout
PTC3/LLWU_P7
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VSS
1
2
PTC2
PTC1/LLWU_P6/RTC_CLKIN
PTE16
PTE17
PTE18
PTE19
PTE20
PTE21
VDDA
VREFH
VREFL
VSSA
3
PTC0
4
PTB17
PTB16
PTB3
5
6
7
PTB2
8
PTB1
9
PTB0/LLWU_P5
PTA20
10
11
12
PTA19
Figure 23. KL16 48-pin QFN pinout diagram
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Ordering parts
PTC3/LLWU_P7
PTC2
PTE0
PTE1
24
23
22
21
20
19
1
2
3
4
5
6
7
8
PTC1/LLWU_P6/RTC_CLKIN
PTE16
PTE17
PTE18
PTE19
VDDA
VSSA
PTB1
PTB0/LLWU_P5
PTA20
PTA19
18
17
PTA18
Figure 24. KL16 32-pin QFN pinout diagram
6 Ordering parts
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable
part numbers for this device, go to freescale.com and perform a part number search
for the following device numbers: PKL16 and MKL16
7 Part identification
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Freescale Semiconductor, Inc.
Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q KL## A FFF R T PP CC N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
KL##
A
Kinetis family
Key attribute
• KL16
• Z = Cortex-M0+
FFF
Program flash memory size
• 32 = 32 KB
• 64 = 64 KB
• 128 = 128 KB
R
Silicon revision
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
PP
• FM = 32 QFN (5 mm x 5 mm)
• FT = 48 QFN (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 4 = 48 MHz
• R = Tape and reel
7.4 Example
This is an example part number:
MKL16Z128VFM4
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Terminology and guidelines
8 Terminology and guidelines
8.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation
and possibly decreasing the useful life of the chip.
8.1.1 Example
This is an example of an operating requirement:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
8.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of
values for a technical characteristic that are guaranteed during operation if you meet
the operating requirements and any other specified conditions.
8.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that
are guaranteed, regardless of whether you meet the operating requirements.
8.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
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Terminology and guidelines
8.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
8.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
8.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
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Freescale Semiconductor, Inc.
Kinetis KL16 Sub-Family, Rev5 08/2014.
Terminology and guidelines
8.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
8.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
8.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
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Freescale Semiconductor, Inc.
Terminology and guidelines
8.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
8.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
5000
4500
4000
TJ
3500
150 °C
3000
105 °C
2500
25 °C
2000
–40 °C
1500
1000
500
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
8.9 Typical value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
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Revision history
Table 40. Typical value conditions
Symbol
TA
Description
Value
25
Unit
°C
Ambient temperature
3.3 V supply voltage
VDD
3.3
V
9 Revision history
The following table provides a revision history for this document.
Table 41. Revision history
Rev. No.
Date
3/2014
5/2014
Substantial Changes
3
4
• Updated the front page and restructured the chapters
• Updated Power consumption operating behaviors
• Updated Definition: Operating behavior
5
08/2014
• Updated related source in the front page
• Updated Power consumption operating behaviors
Kinetis KL16 Sub-Family, Rev5 08/2014.
57
Freescale Semiconductor, Inc.
Information in this document is provided solely to enable system and
software implementers to use Freescale products. There are no express
or implied copyright licenses granted hereunder to design or fabricate
any integrated circuits based on the information in this document.
Freescale reserves the right to make changes without further notice to
any products herein.
How to Reach Us:
Home Page:
freescale.com
Web Support:
freescale.com/support
Freescale makes no warranty, representation, or guarantee regarding
the suitability of its products for any particular purpose, nor does
Freescale assume any liability arising out of the application or use of
any product or circuit, and specifically disclaims any and all liability,
including without limitation consequential or incidental damages.
“Typical” parameters that may be provided in Freescale data sheets
and/or specifications can and do vary in different applications, and
actual performance may vary over time. All operating parameters,
including “typicals,” must be validated for each customer application by
customer's technical experts. Freescale does not convey any license
under its patent rights nor the rights of others. Freescale sells products
pursuant to standard terms and conditions of sale, which can be found
at the following address: freescale.com/SalesTermsandConditions.
Freescale, Freescale logo, Energy Efficient Solutions logo, and Kinetis
are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm.
Off. All other product or service names are the property of their
respective owners. ARM and Cortex are registered trademarks of ARM
Limited (or its subsidiaries) in the EU and/or elsewhere. All rights
reserved.
© 2012-2014 Freescale Semiconductor, Inc.
Document Number KL16P64M48SF5
Revision 5 08/2014
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