MKL28Z512VDC72 [NXP]
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM;
| 型号： | MKL28Z512VDC72 |
| 厂家： | 
NXP |
| 描述： | Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM 静态存储器 |
| 文件： | 总83页 (文件大小：1216K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NXP Semiconductors
Data Sheet: Technical Data
MKL28Z512Vxx7
Rev. 3, 09/2020
Kinetis KL28Zxxx with 512 KB
MKL28Z512Vxx7
Flash and 128 KB SRAM
72 MHz Cortex-M0+ based Microcontroller
Supports ultra low power Arm based microcontroller with crystal-
less USB feature, large flash and RAM, evolutionary low-power
peripherals and security features. This is an ideal solution for
Sensor Hub applications, Bluetooth, Wi-Fi connectivity, Smart
Energy, Internet of Things, and Edge and Concentrator. This
device offers:
121 XFBGA
8 x 8 x 0.43 mm Pitch 14 x 14 x 1.4 mm Pitch
0.65 mm 0.5 mm
100 LQFP
• 128KB SRAM for data processing and connectivity stack
• Ultra low dynamic and static power consumption with smart
peripherals for low power applications
• Advanced LPI2C and LPSPI supporting asynchronous
DMA master data transition
• FlexIO for flexible and high performance interfaces
• Crypto acceleration with AES/DES/3DES/MD5/SHA and TRNG
• USB FS 2.0 device operation without need of external crystal
Core
• Arm® Cortex®-M0+ cores up to 72 MHz in Normal
mode and 96 MHz in High Speed mode
Communication interfaces
• Three 16-bit Low Power Serial Peripheral Interface
(LPSPI) modules
• One EMVSIM module supporting EMV version 4.3,
ISO7816
• Three LPUART modules
• Three LPI2C modules supporting up to 5 Mbit/s
• One SAI module supporting I2S
• One FlexIO module emulating UART, SPI, I2S,
camera interface, and Motorola 68K/Intel 8080 bus
• USB FS 2.0 device operation without need of
external crystal
Memories
• Up to 512 KB program flash memory
• 128 KB SRAM
• 32 KB ROM with built-in bootloader
System peripherals
• 8-channel DMA controller
• Independent clocked Watchdog
• Low-leakage wakeup unit
• SWD debug interface and Micro Trace Buffer
• Bit Manipulation Engine
• Memory Mapped Divide and Square Root module
(MMDDVSQ)
• Cyclic Redundancy Check (CRC) module
• Nested Vector Interrupt Controller (NVIC) supports 32
interrupt vectors
• Additional peripheral interrupt support via Interrupt
Multiplexer (INTMUX)
Analog Modules
• 16-bit, 24-channel SAR ADC with internal voltage
reference
• Two High-speed analog comparators each
containing a 6-bit DAC and programmable reference
input
• One 12-bit DAC
• 1.2 V and 2.1 V voltage references (Vref)
Timers
Clocks
• One 6-channel Timer/PWM module
• Two 2-channel Timer/PWM modules
• Two low-power timers
• System Clock Generator module that includes the
following clock sources:
• 48 to 60 MHz high accuracy fast internal
reference clock (FIRC)
• Two periodic interrupt timers
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• 32–40 kHz, or 3–32 MHz crystal oscillator
• 1 kHz LPO clock
• Secure Real time clock
• 56-bit software time stamp timer at 1 MHz
• 8/2 MHz slow internal reference clock (SIRC)
• Peripheral Clock Control (PCC) module that
supports asynchronous clocking and clock divide
options for peripherals.
Security and integrity modules
• 80-bit unique identification number per chip
• MMCAU supports acceleration of the DES, 3DES,
AES, MD5, SHA-1, and SHA-256 algorithms
• True Random Number Generator (TRNG)
Human-machine interface
• General-purpose input/output up to 97
• Low-power hardware touch sensor interface (TSI)
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Temperature range: –40 to 105 °C
NOTE
The 121-pin packages for this product is not yet available. However, it is included in a
Package Your Way program for Kinetis MCUs. Visit nxp.com/KPYW for more
details.
Ordering Information 1
Part Number
Memory
Package
IO and ADC channels
GPIOs ADC
Flash (KB)
SRAM (KB)
Pin count
Package
GPIOs
(INT/HD)
channels
(SE/DP)
MKL28Z512V
LL7
512
512
128
128
100
121
LQFP
82
97
82/8
27/4
MKL28Z512V
DC72
XFBGA
97/8
27/4
1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number search.
2. Package Your Way.
Related Resources
Type
Selector
Guide
Description
Resource
Solution Advisor
The NXP Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
Product Brief The Product Brief contains concise overview/summary information to
enable quick evaluation of a device for design suitability.
KL2XPB1
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
MKL28ZRM1
MKL28Z512Vxx71
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
Chip Errata
The chip mask set Errata provides additional or corrective information for KINETIS_L_1N52N1
a particular device mask set.
Package
drawing
Package dimensions are provided in package drawings.
• 121-XFBGA:
98ASA00595D1
• 100-LQFP:
98ASS23308W1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
2
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
WDOG
Reset
Timer
Timer
Timer
Timer
SPI
UART
Clocks/
Oscillators
SMC
XTAL
OSC
ANALOG
Temp
SCG
TSTMR
0
TPM
2
LPTMR LPTMR WDOG LPSPI
LPUART
2
PMC
CRC
1
0
0
2
ADC
Inputs
TSI0
TSI
ADC0
DAC0
CMP0
CMP1
FIRC
PLL
SIRC
Monitor
PCC
LPI2C
2
I2C
DAC
Outputs
VREF
LPO1K
LLWU
0
LPIT
0
SCG
SRTC
RCM
SIM
TRG
MUX
SAI0
Audio
GPIO
Reference
Inputs
RGPIO
DMA0
8-channel
USB
MCM
s2
s1
MSCM
USBVREG
DMA
Requests
CAU
DMAMux
•
•
•
m1
0
Core
SRAM
128KB
DVSQ
IO Port
Cortex-M0+
Platform
AXBS
m0
MTB
DWT
CTI
Cortex-M0+
ROM
32KB
s0
s3
System
Interrupts
m2
SYSTICK NVIC
SWD
SWD-DP
FTFA
DBG
CTI
MPU
AWIC
MDM-AP
AHB-AP0
FLASH 0
256KB
FMC
FLASH 1
256KB
M0+ DBG
AIPS1
AHB
EMVSIM
EMVSIM
TPM
0/1
TRNG
Timer
SPI
USB
SRAM
LPSPI
0/1
PortA
PortB
PortC
Port A
Port B
Port C
PCC
LPUART
0/1
UART
I2C
AIPS0
TRG
MUX
LPI2C
0/1
FlexIO
8/16-bit
Parallel I/F
FlexIO0
PortD
PortE
Port D
Port E
1x
USB
USB0
LEGEND:
Synchronizer
Bus Components
Platform Domain
CM0+ Platform
Analog Domain
AHB32
S
AIPS0 IPBUS
AIPS1 IPBUS
Core Memory-
Mapped Module
DAP Reference
sec
exsc
Memory protection
Gaskets
Other Module such
as test/analog
Figure 1. KL28Z block diagram
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
3
NXP Semiconductors
Table of Contents
1
2
Ratings..................................................................................5
3.8 Communication interfaces............................................. 43
3.8.1 EMV SIM specifications.....................................43
3.8.2 USB electrical specifications............................. 48
3.8.3 USB VREG electrical specifications.................. 49
3.8.4 LPSPI switching specifications.......................... 49
3.8.5 LPI2C.................................................................54
3.8.6 LPUART............................................................ 54
3.8.7 I2S/SAI switching specifications........................ 55
3.9 Human-machine interfaces (HMI)..................................59
3.9.1 TSI electrical specifications............................... 59
Dimensions........................................................................... 59
4.1 Obtaining package dimensions......................................59
Pinouts and Packaging......................................................... 60
5.1 KL28Z Signal Multiplexing and Pin Assignments.......... 60
5.2 KL28Z Pinouts............................................................... 65
Ordering parts....................................................................... 67
6.1 Determining valid orderable parts..................................67
Design considerations...........................................................68
7.1 Hardware design considerations................................... 68
7.1.1 Printed circuit board recommendations............. 68
7.1.2 Power delivery system.......................................68
7.1.3 Analog design....................................................69
7.1.4 Digital design.....................................................70
7.1.5 Crystal oscillator................................................ 74
7.2 Software considerations................................................ 75
Part identification...................................................................76
8.1 Description.....................................................................76
8.2 Format........................................................................... 76
8.3 Fields............................................................................. 76
8.4 Example.........................................................................77
Terminology and guidelines.................................................. 77
9.1 Definitions......................................................................77
9.2 Examples.......................................................................78
9.3 Typical-value conditions................................................ 78
9.4 Relationship between ratings and operating
1.1 Thermal handling ratings............................................... 5
1.2 Moisture handling ratings...............................................5
1.3 ESD handling ratings.....................................................5
1.4 Voltage and current operating ratings............................5
General................................................................................. 6
2.1 AC electrical characteristics...........................................6
2.2 Nonswitching electrical specifications............................7
2.2.1 Voltage and current operating requirements..... 7
2.2.2 LVD, HVD, and POR operating requirements... 7
2.2.3 Voltage and current operating behaviors...........8
2.2.4 Power mode transition operating behaviors...... 9
2.2.5 Power consumption operating behaviors.......... 10
2.2.6 EMC radiated emissions operating behaviors... 19
2.2.7 Designing with radiated emissions in mind........20
2.2.8 Capacitance attributes.......................................20
2.3 Switching specifications.................................................20
2.3.1 Device clock specifications................................20
2.3.2 General switching specifications....................... 21
2.4 Thermal specifications...................................................23
2.4.1 Thermal operating requirements....................... 23
2.4.2 Thermal attributes..............................................23
Peripheral operating requirements and behaviors................ 24
3.1 Core modules................................................................ 24
3.1.1 SWD electricals ................................................ 24
3.2 System modules............................................................ 26
3.3 Clock modules............................................................... 26
3.3.1 System Clock Generation (SCG) specifications26
3.3.2 Oscillator electrical specifications......................28
3.4 Memories and memory interfaces................................. 30
3.4.1 Flash electrical specifications............................ 30
3.5 Security and integrity modules.......................................32
3.6 Analog............................................................................32
3.6.1 ADC electrical specifications............................. 32
3.6.2 Voltage reference electrical specifications........ 36
3.6.3 CMP and 6-bit DAC electrical specifications..... 38
3.6.4 12-bit DAC electrical characteristics..................40
3.7 Timers............................................................................43
4
5
6
7
3
8
9
requirements..................................................................79
9.5 Guidelines for ratings and operating requirements........79
10 Revision History.................................................................... 80
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Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
Ratings
1 Ratings
1.1 Thermal handling ratings
Table 1. Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Table 2. Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Table 3. ESD handling ratings
Symbol
VHBM
Description
Min.
–2000
–500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
ILAT
Latch-up current at ambient temperature of 105 °C
–100
+100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
5
NXP Semiconductors
General
1.4 Voltage and current operating ratings
Table 4. Voltage and current operating ratings
Symbol
VDD
IDD
Description
Min.
–0.3
—
Max.
3.8
Unit
V
Digital supply voltage
Digital supply current
IO pin input voltage
120
mA
V
VIO
–0.3
–25
VDD + 0.3
25
ID
Instantaneous maximum current single pin limit (applies to
all port pins)
mA
VDDA
Analog supply voltage
USB_DP input voltage
USB_DM input voltage
USB regulator input
VDD – 0.3
–0.3
VDD + 0.3
3.63
V
V
V
V
VUSB_DP
VUSB_DM
VREGIN
–0.3
3.63
–0.3
6.0
2 General
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
6
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
General
2.2 Nonswitching electrical specifications
2.2.1 Voltage and current operating requirements
Table 5. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
1.71
–0.1
–0.1
Max.
3.6
Unit
V
Notes
Supply voltage
VDDA
Analog supply voltage
3.6
V
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
0.1
V
0.1
V
VIH
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.71 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.71 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICIO
Input hysteresis
0.06 × VDD
-5
—
—
V
IO pin negative DC injection current — single pin
• VIN < VSS-0.3V
1
mA
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
-25
—
mA
• Negative current injection
VODPU
VRAM
Open drain pullup voltage level
VDD
1.2
VDD
—
V
V
2
VDD voltage required to retain RAM
1. All I/O pins are internally clamped to VSS through a ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS-0.3 V) is observed, then there is no need to provide current limiting resistors at the pads. If
this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
2. Open drain outputs must be pulled to VDD
.
2.2.2 LVD, HVD, and POR operating requirements
Table 6. VDD supply LVD, HVD, and POR operating requirements
Symbol Description
VPOR Falling VDD POR detect voltage
Min.
Typ.
Max.
Unit
Notes
0.8
1.1
1.5
V
—
Table continues on the next page...
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
7
NXP Semiconductors
General
Table 6. VDD supply LVD, HVD, and POR operating requirements (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VLVDH
Falling low-voltage detect threshold — high
range (LVDV = 01)
2.48
2.56
2.64
V
—
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV = 00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
—
2.70
2.80
2.90
3.00
60
2.78
2.88
2.98
3.08
—
V
V
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
V
• Level 4 falling (LVWV = 11)
V
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
mV
—
—
1
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
V
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV = 00)
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
—
1.80
1.90
2.00
2.10
40
1.86
1.96
2.06
2.16
—
V
V
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
V
• Level 4 falling (LVWV = 11)
V
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
mV
—
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
—
—
Internal low power oscillator period — factory
trimmed
1000
1100
μs
VHVDL
VHVDH
VHYSH
High voltage detect threshold — low range
(HVDV=0) — Rising
3.4
3.35
3.65
3.6
—
3.5
3.45
3.75
3.7
50
3.6
3.55
3.85
3.8
—
V
V
2
High voltage detect threshold — low range
(HVDV=0) — Falling
High voltage detect threshold — high range
(HVDV=1) — Rising
2
High voltage detect threshold — high range
(HVDV=1) — Falling
High voltage detect hysteresis — low range
(HVDV=0)
mV
—
High voltage detect hysteresis — high range
(HVDV=1)
—
50
—
1. Rising thresholds are falling threshold + hysteresis voltage
2. The selection of high voltage detect trip voltage is controlled by PMC_HVDSC1[HVDV].
8
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
General
2.2.3 Voltage and current operating behaviors
Table 7. Voltage and current operating behaviors
Symbol Description
VOH Output high voltage — Normal drive pad
Min.
Typ.
Max.
Unit
Notes
1
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –2.5 mA
VDD – 0.5
VDD – 0.5
—
—
V
V
VOH
Output high voltage — High drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –10 mA
1
VDD – 0.5
VDD – 0.5
—
—
—
V
V
IOHT
VOL
Output high current total for all ports
Output low voltage — Normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
100
mA
1
1
—
—
0.5
0.5
V
V
VOL
Output low voltage — High drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
—
—
—
—
0.5
0.5
100
1
V
V
IOLT
IIN
Output low current total for all ports
mA
μA
Input leakage current (per pin) for full
temperature range
2
IIN
IIN
Input leakage current (per pin) at 25 °C
—
—
0.025
41
μA
μA
2
2
Input leakage current (total all pins) for full
temperature range
IOZ
Hi-Z (off-state) leakage current (per pin)
Internal pullup resistors
—
1
μA
kΩ
RPU
20
50
3
1. PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6 and PTD7 I/O have both high drive and normal drive capability
selected by the associated PORTx_PCRn[DSE] control bit. All other GPIOs are normal drive only. PTD4, PTD5,
PTD6, PTD7, PTE20, PTE21, PTE22, and PTE23 are also fast pins.
2. Measured at VDD = 3.6 V
3. Measured at VDD supply voltage = VDD min and Vinput = VSS
2.2.4 Power mode transition operating behaviors
All specifications in the following table assume this clock configuration in Run mode:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• SCG configured in FIRC mode; peripheral functional clocks from
FIRCDIV3_CLK and USB clock from FIRCDIV1_CLK
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
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NXP Semiconductors
General
Table 8. Power mode transition operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the
point VDD reaches 1.8 V to execution of the first
instruction across the operating temperature
range of the chip.
—
—
300
μs
1
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• LLS3 → RUN
• LLS2 → RUN
• VLPS → RUN
• STOP → RUN
—
—
—
—
—
—
—
—
188
188
125
125
5.5
5.5
5.5
5.5
193
193
130
130
6.1
6.1
6.1
6.1
μs
μs
μs
μs
μs
μs
μs
μs
1. Normal boot (FTFA_FOPT[LPBOOT]=11).
2.2.5 Power consumption operating behaviors
NOTE
The values in the following table are based on
characterization data with a few samples.
NOTE
The actual power consumption measured in the related
condition, with certain peripherals running, is the sum of
related low power current consumption of the device listed in
Table 9 and the related low power mode peripheral adders in
Table 10.
10
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
General
NOTE
The maximum values represent characterized results
equivalent to the mean plus three times the standard
deviation (mean + 3σ).
Table 9. Power consumption operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDDA
Analog supply current
—
—
See note
mA
1
2
IDD_HSRUN High speed run mode current at 96
MHz - all peripheral clocks disabled,
code executing from flash, while(1)
loop
—
—
12.6
12.8
17.4
17.6
mA
mA
• at 1.8 V
• at 3.0 V
IDD_HSRUN High speed run mode current at 96
MHz - all peripheral clocks enabled,
code executing from flash, while(1)
loop
3
—
—
15.5
15.7
20.4
20.6
mA
mA
• at 1.8 V
• at 3.0 V
IDD_RUN
IDD_RUN
IDD_RUN
IDD_RUN
Run mode current at 72 MHz - all
peripheral clocks disabled, code
executing from flash, while(1) loop
4
5
6
7
• at 1.8 V
• at 3.0 V
—
—
9.4
9.6
13.6
13.8
mA
mA
Run mode current at 48 Mhz - all
peripheral clocks disabled, code
executing from flash, while(1) loop
—
—
7.3
7.4
11.4
11.5
mA
mA
• at 1.8 V
• at 3.0 V
Run mode current at 72 MHz - all
peripheral clocks enabled, code
executing from flash, while(1) loop
—
—
11.6
11.7
15.9
16.0
mA
mA
• at 1.8 V
• at 3.0 V
Run mode current at 48 Mhz - all
peripheral clocks enabled, code
executing from flash, while(1) loop
—
—
8.9
9.1
13.1
13.3
mA
mA
• at 1.8 V
• at 3.0 V
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Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
11
NXP Semiconductors
General
Table 9. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
IDD_WAIT
IDD_WAIT
IDD_VLPR
IDD_VLPR
IDD_VLPR
IDD_VLPR
Wait mode high frequency current at 72
MHz, at 3.0 V - all peripheral clocks
disabled, while(1) loop
—
7.0
9.0
mA
4
Wait mode current at 3.0 V at 48 Mhz
— all peripheral clocks disabled,
while(1) loop
—
—
—
—
—
—
—
5.7
10.4
mA
μA
μA
μA
μA
μA
μA
5
8
Very-low-power run mode current at
3.0 V — all peripheral clocks enabled
at 4 MHz, while(1) loop
483.7
557.6
400.3
415.2
285.9
415.6
1011.7
1720.2
926.5
Very-low-power run mode current at
3.0 V — all peripheral clocks enabled
at 8 MHz, while(1) loop
9
Very-low-power run mode current at
3.0 V — all peripheral clocks disabled
at 4 MHz, while(1) loop
10
11
10
11
Very-low-power run mode current at
3.0 V — all peripheral clocks disabled
at 8 MHz, while(1) loop
941.1
IDD_VLPW Very-low-power wait mode current at
3.0 V — all peripheral clocks disabled
at 4 MHz, while(1) loop
1145.6
1498.7
IDD_VLPW Very-low-power wait mode current at
3.0 V — all peripheral clocks disabled
at 8 MHz, while(1) loop
IDD_STOP Stop mode current at 3.0 V
• -40 to 25 °C
—
—
—
—
—
264.5
287.0
325.3
374.7
496.7
320.5
356.1
445.4
590.8
952.3
μA
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
IDD_VLPS
Very-low-power stop mode current at
3.0 V
—
—
—
—
—
4.2
16.4
35.9
μA
• -40 to 25 °C
11.0
24.0
44.0
93.4
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
84.5
156.2
300.2
IDD_LLS2
Low-leakage stop mode 2 current at
3.0 V
—
—
—
—
2.7
4.7
5.4
μA
• -40 to 25 °C
10.6
22.7
49.0
• at 50 °C
• at 70 °C
8.6
14.7
Table continues on the next page...
12
NXP Semiconductors
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
General
Table 9. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
• at 85 °C
—
30.4
88.6
• at 105 °C
IDD_LLS3
Low-leakage stop mode 3 current at
3.0 V
—
—
—
—
—
3.0
5.9
5.9
14.5
32.0
65.2
122.0
μA
• -40 to 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
11.4
19.7
40.9
IDD_VLLS3 Very-low-leakage stop mode 3 current
at 3.0 V
—
—
—
—
—
2.2
4.6
5.1
μA
• -40 to 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
10.9
24.4
44.8
91.0
9.0
15.9
33.1
IDD_VLLS2 Very-low-leakage stop mode 2 current
at 3.0 V
—
—
—
—
—
1.8
3.3
3.4
6.8
μA
• -40 to 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
6.1
14.5
26.4
54.4
10.4
21.6
IDD_VLLS1 Very-low-leakage stop mode 1 current
at 3.0V
—
—
—
—
—
0.65
1.1
2.1
3.6
8.5
0.88
1.6
μA
• -40 to 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
3.3
21.0
32.2
IDD_VLLS0 Very-low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 0) at 3.0
V
—
—
—
—
—
372.0
768.6
1734
3291
8025
598
1331
nA
• -40 to 25 °C
• at 50 °C
• at 70 °C
3038
20575
27560
Table continues on the next page...
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
13
NXP Semiconductors
General
Table 9. Power consumption operating behaviors (continued)
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
• at 85 °C
• at 105 °C
IDD_VLLS0 Very-low-leakage stop mode 0 current
12
(SMC_STOPCTRL[PORPO] = 1) at 3.0
V
—
—
—
—
—
94.1
480.9
1416
2970
7642
311
1024
nA
• -40 to 25 °C
• at 50 °C
• at 70 °C
• at 85 °C
• at 105 °C
2760
19574
27325
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 96 MHz core and system clock (DIVCORE_CLK), 24 MHz bus/slow clock(DIVSLOW_CLK), and 24 MHz flash clock.
SCG configured as System PLL mode (SCG_HCCR[SCS]=0110), PLL clock source is SOSC from external 8 MHz
crystal. All peripheral functional clocks disabled by clearing all xxDIV3, xxDIV2, and xxDIV1 in SCG_SOSCDIV and
SCG_SPLLDIV registers. FIRC and SIRC disabled by clearing SCG_FIRCCSR[FIRCEN] and SCG_SIRCCSR[SIRCEN].
3. 96 MHz core and system clock (DIVCORE_CLK), 24 MHz bus/slow clock(DIVSLOW_CLK), and 24 MHz flash clock.
SCG configured as System PLL mode (SCG_HCCR[SCS]=0110), PLL clock source is SOSC from external 8 MHz
crystal. All peripheral functional clocks except USB = 24 MHz from SPLLDIV3_CLK. USB functional clock = 48 MHz
from SPLLDIV1_CLK. FIRC and SIRC disabled by clearing SCG_FIRCCSR[FIRCEN] and SCG_SIRCCSR[SIRCEN].
4. 72 MHz core and system clock (DIVCORE_CLK), 24 MHz bus/slow clock(DIVSLOW_CLK), and 24 MHz flash clock.
SCG configured as System PLL mode (SCG_RCCR[SCS]=0110), PLL clock source is SOSC from external 8 MHz
crystal. All peripheral functional clocks disabled by clearing all xxDIV3, xxDIV2, and xxDIV1 in SCG_SOSCDIV and
SCG_SPLLDIV registers. FIRC and SIRC disabled by clearing SCG_FIRCCSR[FIRCEN] and SCG_SIRCCSR[SIRCEN].
5. 48 MHz core and system clock (DIVCORE_CLK), 24 MHz bus/slow clock(DIVSLOW_CLK), and 24 MHz flash clock.
SCG configured as FIRC 48 MHz mode (SCG_RCCR[SCS]=0011). All peripheral functional clocks disabled by clearing
all xxDIV3, xxDIV2, and xxDIV1 in SCG_FIRCDIV register. PLL, SOSC, and SIRC disabled by clearing
SCG_SPLLCSR[SPLLEN], SCG_SOSCCSR[SOSCEN], and SCG_SIRCCSR[SIRCEN].
6. 72 MHz core and system clock (DIVCORE_CLK), 24 MHz bus/slow clock(DIVSLOW_CLK), and 24 MHz flash clock.
SCG configured as System PLL mode (SCG_RCCR[SCS]=0110), PLL clock source is SOSC from external 8 MHz
crystal. All peripheral functional clocks except USB = 24 MHz from SPLLDIV3_CLK. USB functional clock = 48 MHz
from SPLLDIV1_CLK. FIRC and SIRC disabled by clearing SCG_FIRCCSR[FIRCEN] and SCG_SIRCCSR[SIRCEN].
7. 48 MHz core and system clock (DIVCORE_CLK), 24 MHz bus/slow clock(DIVSLOW_CLK), and 24 MHz flash clock.
SCG configured as FIRC 48 MHz mode (SCG_RCCR[SCS]=0011). All peripheral functional clocks except USB = 24
MHz from FIRCDIV3_CLK. USB functional clock = 48 MHz from FIRCDIV1_CLK. PLL, SOSC, and SIRC disabled by
clearing SCG_SPLLCSR[SPLLEN], SCG_SOSCCSR[SOSCEN], and SCG_SIRCCSR[SIRCEN].
8. 4 MHz core and system clock (DIVCORE_CLK), 1 MHz bus/slow clock(DIVSLOW_CLK), and 1 MHz flash clock. SCG
configured as SIRC 8 MHz mode (SCG_VCCR[SCS]=0010). All peripheral functional clocks except USB = 1M Hz from
SIRCDIV3_CLK. USB clock disabled. PLL, SOSC, and FIRC disabled by clearing SCG_SPLLCSR[SPLLEN],
SCG_SOSCCSR[SOSCEN], and SCG_FIRCCSR[FIRCEN].
9. 8 MHz core and system clock (DIVCORE_CLK), 1 MHz bus/slow clock(DIVSLOW_CLK), and 1 MHz flash clock. SCG
configured as SIRC 8 MHz mode (SCG_VCCR[SCS]=0010). All peripheral functional clocks except USB = 1M Hz from
SIRCDIV3_CLK. USB clock disabled. PLL, SOSC, and FIRC disabled by clearing SCG_SPLLCSR[SPLLEN],
SCG_SOSCCSR[SOSCEN], and SCG_FIRCCSR[FIRCEN].
10. 4 MHz core and system clock (DIVCORE_CLK), 1 MHz bus/slow clock(DIVSLOW_CLK), and 1 MHz flash clock. SCG
configured as SIRC 8 MHz mode (SCG_VCCR[SCS]=0010). All peripheral functional clocks disabled by clearing all
xxDIV3, xxDIV2, and xxDIV1 in SCG_SIRCDIV register. PLL, SOSC, and FIRC disabled by clearing
SCG_SPLLCSR[SPLLEN], SCG_SOSCCSR[SOSCEN], and SCG_FIRCCSR[FIRCEN].
11. 8 MHz core and system clock (DIVCORE_CLK), 1 MHz bus/slow clock(DIVSLOW_CLK), and 1 MHz flash clock. SCG
configured as SIRC 8 MHz mode (SCG_VCCR[SCS]=0010). All peripheral functional clocks disabled by clearing all
14
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
General
xxDIV3, xxDIV2, and xxDIV1 in SCG_SIRCDIV register. PLL, SOSC, and FIRC disabled by clearing
SCG_SPLLCSR[SPLLEN], SCG_SOSCCSR[SOSCEN], and SCG_FIRCCSR[FIRCEN].
12. No brownout
Table 10. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IEREFSTEN8MHz
External 8 MHz crystal clock adder with 402.9 462.1 477.5
System OSC. Measured by entering
VLPS mode with the crystal enabled
(SCG_SOSCCFG[RANGE] = 10,
492
506.2 530.4
uA
SCG_SOSCCFG[HGO] = 0,
SCG_SOSCCFG[EREFS] = 1, and
SC2P/SC4P/SC8P = 0).
IEREFSTEN32KHz
External 32 kHz crystal clock adder
with System OSC by means of
SCG_SOSCCFG[RANGE] = 01,
SCG_SOSCCFG[HGO] = 0,
SCG_SOSCCFG[EREFS] = 1, and
SC2P/SC4P/SC8P = 0. Measured by
entering all the following modes with
the crystal enabled:
• VLLS1
nA
373.9 539.2 612.3 644.9 523.7 1000
568.4 552.6 650.8 757.9 995.6 1400
582.8 565.0 615.5 797.1 968.5 1700
472.4 635.2 776.9 425.6 1500 2800
528.0 534.1 636.6 9600 20300 40900
• VLLS3
• LLS3
• VLPS
• STOP
ILPTMR
LPTMR peripheral adder measured by 151.0
placing the device in VLLS1 mode with
LPTMR enabled using LPO clock.
7.7
21.8
19.9
7.6
174.0 31.0
nA
µA
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and
a single external input for compare.
Includes 6-bit DAC power
18.8
19.6
20.0
20.4
20.5
consumption.
IRTC
RTC peripheral adder measured by
placing the device in VLLS1 mode and
the RTC ALARM set for 1 minute.
Includes selected clock source power
consumption.
• OSC32KCLK (32KHz external
crystal)
• LPO (internal 1K Hz Low Power
Oscillator)
116.0 1400 1400 1500 1500 120.0
35.0 1400 1400 1600 1400 120.0
nA
ILPUART
LPUART peripheral adder measured
by placing the device in STOP mode
with selected clock source waiting for
RX data at 115200 baud rate. Includes
Table continues on the next page...
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
15
NXP Semiconductors
General
Table 10. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
selected clock source power
consumption.
85.7
89.4
87.3
88.4
85.3
86.6
µA
41.2
43.5
38.7
36.8
39.6
37.0
• Slow IRC clock from SCG (8
MHz internal reference clock)
• OSCERCLK (8 MHz external
crystal)
ILPSPI
LPSPI peripheral adder measured by
placing the device in VLPS mode with
selected clock source, LPSPI is
configured as master mode with bit
rate of 4 Mbps. Includes selected clock
source power consumption.
69.4
66.7
65.9
66.1
65.8
66.0
µA
µA
• Slow IRC clock from SCG (8
MHz internal reference clock)
• OSCERCLK (8 MHz external
crystal)
431.9 489.9 503.5 518.6 533.0 557.0
ITPM
TPM peripheral adder measured by
placing the device in STOP mode with
selected clock source configured for
output compare generating 100 Hz
clock signal. No load is placed on the
I/O generating the clock signal.
Includes selected clock source and I/O
switching currents.
80.7
35.5
84.2
37.2
84.2
37.3
84.4
37.1
84.8
37.7
86.3
37.7
• Slow IRC clock from SCG (8
MHz internal reference clock)
• OSCERCLK (8 MHz external
crystal)
ILPI2C
LPI2C peripheral adder measured by
placing the device in VLPS mode with
selected clock source, LPI2C is
configured as master, and bit rate is
400 Kbps. Includes selected clock
source power consumption.
• Slow IRC clock from SCG (8
MHz internal reference clock)
• OSCERCLK (8 MHz external
crystal)
µA
69.7
66.7
66.9
67.6
68.2
68.2
582.9 597.9 610.8 623.8 637.0 660.2
IBG
Bandgap adder when BGEN bit is set
and device is placed in VLPS mode.
• Bandgap buffer disabled
µA
µA
96.8
95.4
96.4
98.2
98.2
98.5
137.5 129.6 133.0 135.5 136.9 139.6
372.9 380.5 384.0 388.3 392.2 394.6
• Bandgap buffer enabled
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP mode.
ADC is configured for low power mode
using the ADC asynchronous clock
(ADACK) and continuous conversions.
Table continues on the next page...
16
NXP Semiconductors
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
General
Table 10. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IWDOG
WDOG peripheral adder measured by
placing the device in STOP mode,
WDOG is configured to time out at 1
second. Includes selected clock source
power consumption.
µA
68.8
11.2
56.0
68.5
10.1
57.1
69.2
10.1
58.6
69.9
10.2
58.5
71.7
10.5
58.6
72.6
10.7
60.0
• Slow IRC clock from SCG (8
MHz internal reference clock)
• OSCERCLK (8 MHz external
crystal)
• LPO (internal 1 kHz Lower
Power Oscillator)
ISIRC_8MHz
SIRC adder when SIRC is configured
to 8 MHz. Measured by entering VLPS
mode with 8 MHz IRC enabled, and
SIRCDIV1, SIRCDIV2, SIRCDIV3
=000.
67.2
22.3
63.0
21.2
63.3
21.4
63.2
21.5
63.3
21.7
63.6
21.4
µA
µA
ISIRC_2MHz
SIRC adder when SIRC is configured
to 2 MHz. Measured by entering STOP
or VLPS mode with 2 MHz IRC
enabled, and SIRCDIV1, SIRCDIV2,
SIRCDIV3 =000.
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• SCG is configured as SPLL mode with SOSC as the clock source for RUN mode
current measurement, and as SIRC mode for VLPR mode current measurement
• USB regulator disabled
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
• For the ALLON curve, all peripheral clocks are enabled as specified in notes of
Power consumption operating behaviors.
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
17
NXP Semiconductors
General
Figure 3. Run mode supply current vs. core frequency
18
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
General
Figure 4. VLPR mode supply current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
Table 11. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band
Typ.
Unit
Notes
(MHz)
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC level
0.15–50
50–150
18
21
21
24
L
dBμV
dBμV
dBμV
dBμV
—
1, 2
VRE3
150–500
500–1000
0.15–1000
VRE4
VRE_IEC
2, 3
1. Determined according to IEC Standard 61967-2 (and SAE J1752/3), Integrated Circuits - Measurement of
Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
19
NXP Semiconductors
General
2. VDD = 3.3 V, VREGIN= 5V, TA = 25 °C, fOSC = 8 MHz (crystal), fSYS_CORE = 96 MHz, fBUS = 24 MHz
3. IEC/SAE level maximum: L≤24dB mV
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 12. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN
Input capacitance
—
7
pF
2.3 Switching specifications
2.3.1 Device clock specifications
Table 13. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Run mode1
Normal run mode
fSYS
System and core clock (DIVCORE_CLK)
—
—
96
72
MHz High speed run
mode
MHz Normal speed run
mode
—
—
8
MHz VLPR mode
fBUS
Bus clock/Slow clock (DIVSLOW_CLK)
Flash clock
24
MHz High speed run
mode and Normal
speed run mode
—
—
1
MHz VLPR mode
fFLASH
24
MHz High speed run
mode and Normal
speed run mode
—
—
—
1
1
1
MHz VLPR mode
KHz All modes
KHz All modes
fLLWU
fRCM
LLWU clock
RCM clock
Table continues on the next page...
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
20
NXP Semiconductors
General
Table 13. Device clock specifications (continued)
Symbol
Description
Min.
Max.
Unit
Run mode1
fWDOG, fTSI WDOG clock, TSI clock
—
24
MHz High speed run
mode and Normal
speed run mode
—
—
1
242
MHz VLPR mode
fADC
ADC clock
MHz High speed run
mode and Normal
speed run mode
—
—
—
—
—
8
32.768
1
MHz VLPR mode
KHz All modes
MHz All modes
MHz All modes
fRTC
fTSTMR
RTC clock
TSTMR clock
LPTMR clock
fLPTMR
24
fTPM, fLPIT
,
TPM clock, LPIT clock, LPSPI clock, LPI2C clock,
LPUART clock, EMVSIM clock, SAI clock, FlexIO
clock
96
MHz High speed run
mode
fLPSPI, fLPI2C
fLPUART
fEMVSIM, fSAI
fFLEXIO
,
,
—
72
MHz Normal speed run
mode
,
—
—
8
MHz VLPR mode
fUSB
USB clock
48
MHz High speed run
mode and Normal
speed run mode
—
—
0
MHz VLPR mode
fERCLK
External reference clock
48
MHz High speed run
mode and Normal
speed run mode
16
32
MHz VLPR mode
fosc_hi_2
Oscillator crystal or resonator frequency — high
frequency mode (high range)
(SCG_SOSCCFG[RANGE]=11)
—
MHz High speed run
mode and Normal
speed run mode
—
—
16
96
MHz VLPR mode
fCAU, fGPIO
CAU clock, GPIO clock
MHz High speed run
mode
—
—
72
8
MHz Normal speed run
mode
MHz VLPR mode
1. Normal run mode, High speed run mode, and VLPR mode.
2. See ADC electrical specifications
2.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO, LPI2C,
and LPUART signals.
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
21
NXP Semiconductors
General
Table 14. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter disabled) —
Synchronous path
1.5
—
Bus clock
cycles
1
GPIO pin interrupt pulse width (digital glitch filter disabled,
analog filter enabled) — Asynchronous path
100
50
—
—
—
—
ns
ns
ns
ns
GPIO pin interrupt pulse width (digital glitch filter disabled,
analog filter disabled) — Asynchronous path
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
16
2
2
GPIO pin interrupt pulse width — Asynchronous path
Port rise/fall time
Normal drive pins
3
• 2.7 ≤ VDD ≤ 3.6 V
• Fast slew rate
—
—
3
ns
10.5
• Slow slew rate
• 1.71 ≤ VDD ≤ 2.7 V
• Fast slew rate
—
—
4
17
• Slow slew rate
High drive pins
4
Normal/low drive enabled
• 2.7 ≤ VDD ≤ 3.6 V
• Fast slew rate
—
—
2.5
ns
10.5
• Slow slew rate
• 1.71 ≤ VDD ≤ 2.7 V
• Fast slew rate
—
—
4
17
• Slow slew rate
High drive enabled
• 2.7 ≤ VDD ≤ 3.6 V
• Fast slew rate
—
—
2
11
• Slow slew rate
• 1.71 ≤ VDD ≤ 2.7 V
• Fast slew rate
—
—
2.5
17
• Slow slew rate
Normal drive fast pins
5
• 2.7 ≤ VDD ≤ 3.6 V
• Fast slew rate
—
—
0.5
10
ns
• Slow slew rate
• 1.71 ≤ VDD ≤ 2.7 V
• Fast slew rate
—
—
0.75
19
• Slow slew rate
High drive fast pins
6
Normal/low drive enabled
• 2.7 ≤ VDD ≤ 3.6 V
—
0.5
ns
22
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
General
Notes
Table 14. General switching specifications
Description
• Fast slew rate
Min.
Max.
Unit
—
11
• Slow slew rate
• 1.71 ≤ VDD ≤ 2.7 V
• Fast slew rate
—
—
1
19
• Slow slew rate
High drive enabled
• 2.7 ≤ VDD ≤ 3.6 V
• Fast slew rate
—
—
2
13
• Slow slew rate
• 1.71 ≤ VDD ≤ 2.7 V
• Fast slew rate
—
—
4
21
• Slow slew rate
1. The synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. For high drive pins with high drive enabled, load is 75pF; other pins load (normal/low drive) is 25pF. Fast slew rate is
enabled by clearing PORTx_PCRn[SRE].
4. High drive pins are PTB0,PTB1, PTC3, and PTC4. High drive capability is enabled by setting PORTx_PCRn[DSE].
5. Normal drive fast pins are PTE20, PTE21, PTE22, and PTE23.
6. High drive fast pins are PTD4, PTD5, PTD6, and PTD7. High drive capability is enabled by setting
PORTx_PCRn[DSE].
NOTE
Only PTA4, PTA20, and PTB19 pins have analog/passive
filter.
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 15. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Notes
Die junction temperature
Ambient temperature
TA
105
°C
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
23
NXP Semiconductors
Peripheral operating requirements and behaviors
2.4.2 Thermal attributes
Table 16. Thermal attributes
Board type
Single-layer (1S)
Four-layer (2s2p)
Single-layer (1S)
Four-layer (2s2p)
—
Symbol
RθJA
Description
100 LQFP
121
XFBGA
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Notes
Thermal resistance, junction to
ambient (natural convection)
64
51
54
45
37
19
4
94
57
81
53
40
30
8
1
RθJA
Thermal resistance, junction to
ambient (natural convection)
RθJMA
RθJMA
RθJB
Thermal resistance, junction to
ambient (200 ft./min. air speed)
Thermal resistance, junction to
ambient (200 ft./min. air speed)
Thermal resistance, junction to
board
2
3
4
—
RθJC
Thermal resistance, junction to
case
—
ΨJT
Thermal characterization
parameter, junction to package top
outside center (natural convection)
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD electricals
Table 17. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
J1
SWD_CLK frequency of operation
Table continues on the next page...
24
NXP Semiconductors
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
Peripheral operating requirements and behaviors
Table 17. SWD full voltage range electricals (continued)
Symbol
Description
• Serial wire debug
Min.
Max.
25
Unit
0
MHz
J2
J3
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
1/J1
—
ns
20
—
ns
J4
J9
SWD_CLK rise and fall times
—
10
0
3
ns
ns
ns
ns
ns
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
—
32
—
J10
J11
J12
—
5
J2
J4
J3
J3
SWD_CLK (input)
J4
Figure 5. Serial wire clock input timing
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
J9
J10
Input data valid
J11
Output data valid
J12
J11
Output data valid
Figure 6. Serial wire data timing
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
25
NXP Semiconductors
System Clock Generation (SCG) specifications
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 System Clock Generation (SCG) specifications
3.3.1.1 Fast IRC (FIRC) specifications
Table 18. Fast IRC (FIRC) specifications
Symbol
Description
Min.
1.71
—
Typ.
Max.
3.6
Unit
V
Notes
Vdd_firc
Supply voltage
—
Ffirc_target IRC target frequency (nominal)
Trim range = 00
—
MHz
1
48
52
56
60
Trim range = 01
Trim range = 10
Trim range = 11
Δffirc_ol_lv Open loop total deviation of FIRC frequency at low
voltage (VDD=1.71V-1.89V) over full temperature
• Regulator disable
2
—
—
—
0.5
0.5
0.5
1.5
1.5
1.5
%Ffirc_targe
t
(SCG_FIRCCSR[FIRCREGOFF]=1)
• Regulator enable
(SCG_FIRCCSR[FIRCREGOFF]=0)
Δffirc_ol_hv Open loop total deviation of FIRC frequency at high
2, 3
voltage (VDD=1.89V-3.6V) over full temperature
%Ffirc_targe
Regulator enable
(SCG_FIRCCSR[FIRCREGOFF]=0)
t
Δffirc_cl
Fine Trim Resolution
—
0.1
%Ffirc_targe
t
Jcyc_firc
Tst_firc
Idd_firc
Period Jitter (RMS)
Startup time
—
—
35
2
150
3
ps
μs
4
Current consumption:
• 48 MHz
—
—
—
—
350
360
380
400
400
420
460
500
μA
• 52 MHz
• 56 MHz
• 60 MHz
1. FIRC trim range is programmable via SCG_FIRCCFG[RANGE].
26
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
System Clock Generation (SCG) specifications
2. For temperatures -40 to 85 °C, the maximum value is 1%, characterized on a few samples of different slots. This
value is not guaranteed by production.
3. Closed loop operation of the FIRC is only usable for USB device operation; it is not usable for USB host operation. It is
enabled by configuring for USB Device, selecting FIRC as USB clock source, and enabling the clock recover function
(USBn_CLK_RECOVER_CTRL[CLOCK_RECOVER_EN]=1, SCG_FIRCCSR[FIRCREGOFF]=0).
4. FIRC startup time is defined as the time between clock enablement and clock availability for system use.
3.3.1.2 Slow IRC (SIRC) specifications
Table 19. Slow IRC specifications
Symbol
Description
Min.
—
Typ.
14
25
2
Max.
17
Unit
μA
Notes
IDD_sirc2M Supply current in 2 MHz mode
IDD_sirc8M Supply current in 8 MHz mode
—
35
μA
fsirc
Output frequency
—
—
MHz
1
2
—
8
—
Δfsirc
Total deviation of trimmed frequency over voltage
and temperature
%fsirc
—
—
—
—
3
4
• 0 to 105 °C
• -40 to 0 °C
Δfsirc_t
Total deviation of trimmed frequency over
temperature @VDD=3.3V
2
3
—
—
—
—
3
%fsirc
Tsu_sirc
Jcyc_sirc
Startup time
12.5
μs
ps
Period jitter (RMS)
• fsirc = 2 MHz
• fsirc = 8 Mhz
—
—
350
100
—
—
1. Selection of output frequency for Slow IRC between 2 MHz and 8 MHz is controlled by SCG_ SIRCCFG[RANGE].
2. Maximum deviation occurs at cold temperature (-40 °C) and hot temperature (105 °C).
3. This specification was obtained using a NXP developed PCB. Jitter is dependent on the noise characteristics of each
PCB and results will vary.
3.3.1.3 System PLL specifications
Table 20. System PLL Specifications
Symbol
fpll_ref
Description
Min.
8
Typ.
—
Max.
16
Unit
MHz
MHz
MHz
Notes
PLL reference frequency range
VCO output frequency
PLL output frequency
fvcoclk_2x
fvcoclk
Ipll
180
90
—
288
144
—
PLL operating current — VCO @ 180 MHz (f osc_hi_2
= 10 MHz , f pll_ref = 10 MHz ,VDIV multiplier = 18)
1
2
—
1.1
—
mA
ps
PLL operating current — VCO @ 288 MHz (f osc_hi_2
= 32 MHz , f pll_ref = 8 MHz ,VDIV multiplier = 36)
—
—
2.0
—
—
Jcyc_pll
PLL period jitter (RMS)
120
Table continues on the next page...
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
27
NXP Semiconductors
System Clock Generation (SCG) specifications
Table 20. System PLL Specifications
(continued)
Symbol
Description
• fvco = 180 MHz
• fvco = 288 MHz
Min.
Typ.
Max.
Unit
Notes
—
80
—
Jacc_pll
PLL accumilated jitter over 1 μs (RMS)
• fvco = 180 MHz
2
—
—
600
300
—
—
—
ps
• fvco = 288 MHz
Dunl
Lock exit frequency tolerance
Lock detector detection time
4.47
—
5.97
150 × 10-6
%
s
tpll_lock
—
3
+ 1075(1/
f pll_ref
)
1. Excludes any oscillator currents that are also consuming power while PLL is in operation.
2. This specification was obtained using an NXP developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
3. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled to PLL enabled. If a crystal/resonator is being used as the reference, this specification assumes it is already
running.
3.3.2 Oscillator electrical specifications
3.3.2.1 Oscillator DC electrical specifications
Table 21. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
—
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
• 24 MHz
• 32 MHz
1.5
IDDOSC
Supply current — high gain mode (HGO=1)
1
• 32 kHz
—
—
—
—
25
400
500
2.5
—
—
—
—
μA
μA
μA
mA
• 4 MHz
• 8 MHz (RANGE=01)
• 16 MHz
Table continues on the next page...
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
28
NXP Semiconductors
System Clock Generation (SCG) specifications
Table 21. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
• 24 MHz
—
3
—
mA
• 32 MHz
—
4
—
mA
Cx
Cy
RF
EXTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
XTAL load capacitance
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain
mode (HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
1.0
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
29
NXP Semiconductors
System Clock Generation (SCG) specifications
3.3.2.2 Oscillator frequency specifications
Table 22. Oscillator frequency specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fosc_lo Oscillator crystal or resonator frequency — low-
32
—
40
kHz
frequency range
(SCG_SOSCCFG[RANGE]=01)
fosc_hi_1 Oscillator crystal or resonator frequency —
medium frequency range
1
8
—
—
8
MHz
MHz
(SCG_SOSCCFG[RANGE]=10)
fosc_hi_2 Oscillator crystal or resonator frequency — high
frequency range
32
(SCG_SOSCCFG[RANGE]=11)
fec_extal Input clock frequency (external clock mode)
tdc_extal Input clock duty cycle (external clock mode)
—
40
—
—
50
48
60
—
MHz
%
1, 2
tcst
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
750
ms
3, 4, 5
Crystal startup time — 32 kHz low-frequency,
high-gain mode (HGO=1)
—
—
250
0.6
—
—
ms
ms
Crystal startup time — 8 MHz medium
frequency (SCG_SOSCCFG[RANGE]=11), low-
power mode (HGO=0)
Crystal startup time — 8 MHz medium
frequency (SCG_SOSCCFG[RANGE]=10),
high-gain mode (HGO=1)
—
1
—
ms
1. Other frequency limits may apply when external clock is being used as a reference for the PLL.
2. When transitioning to system PLL mode, restrict the frequency of the input clock so that, when it is divided by PREDIV, it
remains within the limits of the PLL reference input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the SCG_SOSCCSR[SOSCVLD]
being set.
5. Crystal startup time is dependent on external crystal and/or resonator and loading capacitance as well as series
resistance.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
30
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
System Clock Generation (SCG) specifications
Table 23. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
13
Max.
18
Unit
μs
Notes
thvpgm4 Longword Program high-voltage time
thversscr Sector Erase high-voltage time
thversblk128k Erase Block high-voltage time for 128 KB
—
1
—
113
452
904
ms
ms
ms
—
52
1
thversall
Erase All high-voltage time
—
104
1
1. Maximum time based on expectations at cycling end-of-life.
3.4.1.2 Flash timing specifications — commands
Table 24. Flash command timing specifications
Symbol Description
Read 1s Block execution time
• 128 KB program flash
Min.
Typ.
Max.
Unit
Notes
1
trd1blk128k
—
—
1.7
ms
trd1sec1k Read 1s Section execution time (flash sector)
tpgmchk Program Check execution time
—
—
—
—
—
—
—
65
60
45
μs
μs
μs
μs
1
1
trdrsrc
tpgm4
Read Resource execution time
Program Longword execution time
Erase Flash Block execution time
• 128 KB program flash
30
1
145
—
2
tersblk128k
—
88
600
ms
tersscr
trd1all
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
—
—
—
—
—
14
—
114
1.8
25
ms
ms
μs
2
1
trdonce
—
1
tpgmonce Program Once execution time
65
175
—
—
μs
—
2
tersall
Erase All Blocks execution time
1300
30
ms
μs
tvfykey
Verify Backdoor Access Key execution time
1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3 Flash high voltage current behaviors
Table 25. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
31
NXP Semiconductors
ADC electrical specifications
3.4.1.4 Reliability specifications
Table 26. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
—
—
2
20
100
50 K
10 K
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 ADC electrical specifications
3.6.1.1 16-bit ADC operating conditions
Table 27. 16-bit ADC operating conditions
Symbol Description
Conditions
Min.
1.71
Typ.1
Max.
3.6
Unit
V
Notes
VDDA
ΔVDDA
ΔVSSA
VADIN
Supply voltage
Supply voltage
Absolute
—
—
2
Delta to VDD (VDD – VDDA
)
-100
0
+100
+100
mV
mV
V
Ground voltage Delta to VSS (VSS – VSSA
)
-100
0
2
Input voltage
• 16-bit differential mode
• All other modes
• 16-bit mode
VREFL
—
31/32 ×
VREFH
—
VREFL
—
VREFH
CADIN
Input
—
—
8
4
10
5
pF
—
capacitance
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input series
resistance
—
2
5
kΩ
kΩ
—
Analog source
resistance
16-bit modes
• fADCK > 8 MHz
3, 4
—
—
0.5
Table continues on the next page...
32
NXP Semiconductors
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
ADC electrical specifications
Table 27. 16-bit ADC operating conditions (continued)
Symbol Description
Conditions
• fADCK = 4–8 MHz
Min.
Typ.1
Max.
Unit
Notes
—
—
1
kΩ
• fADCK < 4 MHz
—
—
2
kΩ
13-bit / 12-bit modes
• fADCK > 16 MHz
• fADCK > 8 MHz
• fADCK = 4–8 MHz
• fADCK < 4 MHz
—
—
—
—
—
—
—
—
0.5
1
kΩ
kΩ
kΩ
kΩ
2
5
11-bit / 10-bit modes
• fADCK > 8 MHz
• fADCK = 4–8 MHz
• fADCK < 4MHz
—
—
—
—
—
—
2
5
kΩ
kΩ
kΩ
10
9-bit / 8-bit modes
• fADCK > 8 MHz
• fADCK < 8 MHz
—
—
5
kΩ
—
—
—
—
10
kΩ
fADCK
ADC conversion ≤ 13-bit mode
1.0
2.0
24.0
12.0
MHz
MHz
5
6
clock frequency
16-bit mode
Crate
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
20.000
37.037
—
1200
ksps
ksps
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
6
rate
No ADC hardware averaging
—
461.467
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
2. DC potential difference.
3. Assumes ADLSMP=0
4. This resistance is external to the MCU. To achieve the best results, the analog source resistance must be kept as low
as possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The
RAS * CAS time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
33
NXP Semiconductors
ADC electrical specifications
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
ZAS
ADC SAR
ENGINE
RAS
RADIN
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 7. ADC input impedance equivalency diagram
3.6.1.2 16-bit ADC electrical characteristics
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
6.1
7.3
9.5
Unit
mA
Notes
IDDA_ADC Supply current
—
3
ADC asynchronous
clock source
• ADLPC = 1, ADHSC = 0
• ADLPC = 1, ADHSC = 1
• ADLPC = 0, ADHSC = 0
• ADLPC = 0, ADHSC = 1
2.4
4.0
5.2
6.2
MHz
MHz
MHz
MHz
tADACK = 1/
fADACK
2.4
fADACK
3.0
4.4
Sample Time
See Reference Manual chapter for sample times
TUE
DNL
Total unadjusted
error
• 12-bit modes
• <12-bit modes
—
—
4
6.8
2.1
LSB4
LSB4
5
5
1.4
Differential non-
linearity
• 12-bit modes
• <12-bit modes
—
—
0.7
0.2
–1.1 to
+1.9
–0.3 to
0.5
INL
Integral non-linearity
• 12-bit modes
• <12-bit modes
—
—
1.0
0.5
–2.7 to
+1.9
LSB4
5
Table continues on the next page...
34
NXP Semiconductors
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
ADC electrical specifications
Table 28. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
–0.7 to
+0.5
5
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• 16-bit modes
• ≤13-bit modes
—
—
—
—
–4
–1.4
–1 to 0
—
–5.4
–1.8
—
LSB4
LSB4
VADIN = VDDA
Quantization error
0.5
ENOB Effective number of 16-bit differential mode
6
bits
12.8
11.9
14.5
13.8
—
—
bits
bits
• Avg = 32
• Avg = 4
16-bit single-ended mode
• Avg = 32
12.2
11.4
13.9
13.1
—
—
bits
bits
dB
• Avg = 4
Signal-to-noise plus See ENOB
SINAD
6.02 × ENOB + 1.76
distortion
THD
Total harmonic
distortion
16-bit differential mode
• Avg = 32
7
7
dB
dB
—
-94
-85
—
16-bit single-ended mode
• Avg = 32
—
—
SFDR Spurious free
dynamic range
16-bit differential mode
• Avg = 32
—
—
dB
dB
82
78
95
90
16-bit single-ended mode
• Avg = 32
EIL
Input leakage error
IIn × RAS
mV
IIn = leakage
current
(refer to the
MCU's voltage
and current
operating
ratings)
Temp sensor slope Across the full temperature
range of the device
1.55
706
1.62
716
1.69
726
mV/°C
mV
8
VTEMP25 Temp sensor voltage 25 °C
8
1. All accuracy numbers assume the ADC is calibrated with VREFH = VDDA
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with
1 MHz ADC conversion clock speed.
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
35
NXP Semiconductors
ADC electrical specifications
4. 1 LSB = (VREFH - VREFL)/2N
5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)
6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
8. ADC conversion clock < 3 MHz
Typical ADC 16-bit Differential ENOB vs ADC Clock
100Hz, 90% FS Sine Input
15.00
14.70
14.40
14.10
13.80
13.50
13.20
12.90
12.60
Hardware Averaging Disabled
Averaging of 4 samples
Averaging of 8 samples
Averaging of 32 samples
12.30
12.00
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 8. Typical ENOB vs. ADC_CLK for 16-bit differential mode
Typical ADC 16-bit Single-Ended ENOB vs ADC Clock
100Hz, 90% FS Sine Input
14.00
13.75
13.50
13.25
13.00
12.75
12.50
12.25
12.00
11.75
11.50
11.25
11.00
Averaging of 4 samples
Averaging of 32 samples
1
2
3
4
5
6
7
8
9
10
11
12
ADC Clock Frequency (MHz)
Figure 9. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode
3.6.2 Voltage reference electrical specifications
36
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
ADC electrical specifications
Table 29. VREF full-range operating requirements
Symbol
Description
Min.
Max.
3.6
Unit
V
Notes
—
VDDA
Supply voltage for 1.2V output
Supply voltage for 2.1V output
Temperature
2.4
3.6
V
—
TA
CL
Operating temperature
range of the device
°C
—
Output load capacitance
100
nF
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/-25% of the nominal specified CL value over the operating temperature
range of the device.
Table 30. VREF full-range operating behaviors
Symbol Description
Min.
1.190
2.092
1.188
2.087
—
Typ.
1.195
2.1
Max.
1.2
Unit
V
Notes
Vout Voltage reference output with factory trim at
1
nominal VDDA and temperature=25°C
2.108
1.202
2.113
—
V
Vout
Voltage reference 1.2 V output— factory trim
Voltage reference 2.1 V output — factory trim
Voltage reference trim step for 1.2 V output
Voltage reference trim step for 2.1 V output
Aging coefficient
1.195
2.1
V
1
1
V
Vstep
0.5
mV
mV
uV/yr
µA
µA
µA
mV
µs
1
—
1.5
—
1
Ac
Ibg
Ilp
—
—
400
80
—
1
Bandgap only current
—
60
Low-power buffer current
—
180
480
0.2
360
960
—
1
Ihp
High-power buffer current
—
1
ΔVLOAD Load regulation — current is 1.0 mA
—
1, 2
—
1
Tstup
Buffer startup time
—
—
100
2
Vvdrift
Voltage drift for 1.2 V output (Vmax -Vmin
across the full voltage range)
—
0.5
mV
Voltage drift for 2.1 V output (Vmax -Vmin
across the full voltage range)
—
—
—
0.9
2
3.5
15
26
mV
mV
mV
Vtdrift
Temperature drift for 1.2 V output (Vmax -Vmin
across the full temperature range)
3
Temperature drift for 2.1 V output (Vmax -Vmin
across the full temperature range)
3.5
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register for Vout
selection of 1.2 V or 2.1 V.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
3. To get best performance of VREF temperature drift, VREF_SC[ICOMPEN] must be set.
Table 31. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
50
°C
—
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
37
NXP Semiconductors
ADC electrical specifications
Table 32. VREF limited-range operating behaviors
Symbol
Vout
Description
Min.
1.173
2.088
Max.
1.225
2.115
Unit
V
Notes
—
Voltage reference output 1.2 V with factory trim
Voltage reference output 2.1 V with factory trim
Vout
V
—
3.6.3 CMP and 6-bit DAC electrical specifications
Table 33. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, high-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
VDD – 0.5
—
—
—
50
250
—
7
—
0.5
200
600
40
V
V
Output low
Propagation delay, high-speed mode (EN=1, PMODE=1)
Propagation delay, low-speed mode (EN=1, PMODE=0)
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
20
ns
tDLS
80
ns
—
μs
IDAC6b
INL
—
—
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
38
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
ADC electrical specifications
0.08
0.07
0.06
0.05
0.04
0.03
HYSTCTR
Setting
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 10. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
39
NXP Semiconductors
ADC electrical specifications
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 11. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.4 12-bit DAC electrical characteristics
3.6.4.1 12-bit DAC operating requirements
Table 34. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
CL
Desciption
Min.
Max.
3.6
3.6
100
1
Unit
V
Notes
Supply voltage
Reference voltage
Output load capacitance
Output load current
1.13
—
V
1
2
pF
mA
IL
—
1. The DAC reference can be selected to be VDDA or VREFH
.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
40
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
ADC electrical specifications
3.6.4.2 12-bit DAC operating behaviors
Table 35. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
250
μA
P
IDDA_DACH Supply current — high-speed mode
—
—
—
—
—
100
15
900
200
30
μA
μs
μs
μs
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
1
1
1
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08) — low-power mode and high-
speed mode
0.7
1
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
—
—
—
—
—
—
100
mV
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
VDACR
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR > 2
V
Differential non-linearity error — VDACR
VREF_OUT
=
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
Rop
SR
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance (load = 3 kΩ)
Slew rate -80h→ F7Fh→ 80h
3.7
—
μV/C
%FSR/C
Ω
6
0.000421
—
—
250
V/μs
• High power (SPHP
)
1.2
1.7
—
—
• Low power (SPLP
3dB bandwidth
)
0.05
0.12
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC
set to 0x800, temperature range is across the full range of the device
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
41
NXP Semiconductors
ADC electrical specifications
8
6
4
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 12. Typical INL error vs. digital code
42
NXP Semiconductors
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
ADC electrical specifications
1.499
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
85
25
105
125
-40
Temperature °C
Figure 13. Offset at half scale vs. temperature
3.7 Timers
See General switching specifications.
3.8 Communication interfaces
3.8.1 EMV SIM specifications
Each EMV SIM module interface consists of a total of five pins.
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
43
NXP Semiconductors
ADC electrical specifications
The interface is designed to be used with synchronous Smart cards, meaning the EMV
SIM module provides the clock used by the Smart card. The clock frequency is
typically 372 times the Tx/Rx data rate.
There is no timing relationship between the clock and the data. The clock that the EMV
SIM module provides to the Smart card is used by the Smart card to recover the clock
from the data in the same manner as standard UART data exchanges. All five signals of
the EMV SIM module are asynchronous with each other.
There are no required timing relationships between signals in normal mode. The smart
card is initiated by the interface device; the Smart card responds with Answer to Reset.
Although the EMV SIM interface has no defined requirements, the ISO/IEC 7816
defines reset and power-down sequences (for detailed information see ISO/IEC 7816).
SI10
EMVSIMn_PD
EMVSIMn_RST
SI7
EMVSIMn_CLK
SI8
EMVSIMn_IO
SI9
EMVSIMn_VCCEN
Figure 14. EMV SIM Clock Timing Diagram
44
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
ADC electrical specifications
The following table defines the general timing requirements for the EMV SIM
interface.
Table 36. Timing Specifications, High Drive Strength
ID
Parameter
Symbol
Min
Max
Unit
MHz
SI EMV SIM clock frequency (EMVSIMn_CLK)1
1
SI EMV SIM clock rise time (EMVSIMn_CLK)2
2
SI EMV SIM clock fall time (EMVSIMn_CLK)2
3
Sfreq
Srise
Sfall
1
5
—
—
20
—
—
0.08 × (1/Sfreq)
ns
ns
ns
μs
μs
0.08 × (1/Sfreq)
SI EMV SIM input transition time (EMVSIMn_IO,
4
Si EMV SIM I/O rise time / fall time (EMVSIMn_IO)3
5
Si EMV SIM RST rise time / fall time (EMVSIMn_RST)4 Tr/Tf
6
Stran
Tr/Tf
25
EMVSIMn_PD)
0.8
0.8
1. 50% duty cycle clock,
2. With C = 50 pF
3. With Cin = 30 pF, Cout = 30 pF,
4. With Cin = 30 pF,
3.8.1.1 EMV SIM Reset Sequences
Smart cards may have internal reset, or active low reset. The following subset
describes the reset sequences in these two cases.
3.8.1.1.1 Smart Cards with Internal Reset
Following figure shows the reset sequence for Smart cards with internal reset. The
reset sequence comprises the following steps:
• After power-up, the clock signal is enabled on EMVSIMn_CLK (time T0)
• After 200 clock cycles, EMVSIMn_IO must be asserted.
• The card must send a response on EMVSIMn_IO acknowledging the reset
between 400–40000 clock cycles after T0.
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
45
NXP Semiconductors
ADC electrical specifications
EMVSIMn_VCCEN
EMVSIMn_CLK
EMVSIMn_IO
RESPONSE
1
2
T0
Figure 15. Internal Reset Card Reset Sequence
The following table defines the general timing requirements for the SIM interface.
Table 37. Timing Specifications, Internal Reset Card Reset Sequence
Ref
Min
Max
Units
1
—
200
EMVSIMx_CLK
clock cycles
2
400
40,000
EMVSIMx_CLK
clock cycles
3.8.1.1.2 Smart Cards with Active Low Reset
Following figure shows the reset sequence for Smart cards with active low reset. The
reset sequence comprises the following steps::
• After power-up, the clock signal is enabled on EMVSIMn_CLK (time T0)
• After 200 clock cycles, EMVSIMn_IO must be asserted.
• EMVSIMn_RST must remain low for at least 40,000 clock cycles after T0 (no
response is to be received on RX during those 40,000 clock cycles)
• EMVSIMn_RST is asserted (at time T1)
• EMVSIMn_RST must remain asserted for at least 40,000 clock cycles after T1, and
a response must be received on EMVSIMn_IO between 400 and 40,000 clock
cycles after T1.
46
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
ADC electrical specifications
EMVSIMn_VCCEN
EMVSIMn_RST
EMVSIMn_CLK
EMVSIMn_IO
RESPONSE
2
1
3
3
T0
T1
Figure 16. Active-Low-Reset Smart Card Reset Sequence
The following table defines the general timing requirements for the EMVSIM
interface..
Table 38. Timing Specifications, Internal Reset Card Reset Sequence
Ref No
Min
—
Max
200
Units
1
2
3
EMVSIMx_CLK clock cycles
EMVSIMx_CLK clock cycles
EMVSIMx_CLK clock cycles
400
40,000
—
40,000
3.8.1.2 EMVSIM Power-Down Sequence
Following figure shows the EMV SIM interface power-down AC timing
diagram.Table 39 table shows the timing requirements for parameters (SI7–SI10)
shown in the figure. The power-down sequence for the EMV SIM interface is as
follows:
• EMVSIMn_SIMPD port detects the removal of the Smart Card
• EMVSIMn_RST is negated
• EMVSIMn_CLK is negated
• EMVSIM_IO is negated
• EMVSIMx_VCCENy is negated
Each of the above steps requires one OSC32KCLK period (usually 32 kHz, also
known as rtcclk in below figure). Power-down may be initiated by a Smart card
removal detection; or it may be launched by the processor.
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
47
NXP Semiconductors
ADC electrical specifications
SI10
EMVSIMn_PD
EMVSIMn_RST
SI7
EMVSIMn_CLK
EMVSIMn_IO
SI8
SI9
EMVSIMn_VCCEN
Figure 17. Smart Card Interface Power Down AC Timing
Table 39. Timing Requirements for Power-down Sequence
Ref No
Parameter
Symbol
Min
Max
Units
SI7
EMVSIM reset to SIM clock stop
Srst2clk
0.9 × 1/
Frtcclk1
1.1 × 1/Frtcclk
μs
SI8
SI9
EMVSIM reset to SIM Tx data
low
Srst2dat 1.8 × 1/Frtcclk 2.2 × 1/Frtcclk
Srst2ven 2.7 × 1/Frtcclk 3.3 × 1/Frtcclk
Spd2rst 0.9 × 1/Frtcclk 1.1 × 1/Frtcclk
μs
μs
μs
EMVSIM reset to SIM voltage
enable low
SI10
EMVSIM presence detect to SIM
reset low
1. Frtcclk is OSC32KCLK, and this clock must be enabled during the power down sequence.
NOTE
Same timing is also followed when auto power down is
initiated. See Reference Manual for reference.
48
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
ADC electrical specifications
3.8.2 USB electrical specifications
The USB electricals for the USB On-the-Go module conform to the standards
documented by the Universal Serial Bus Implementers Forum. For the most up-to-
date standards, visit usb.org.
NOTE
The Fast IRC do not meet the USB jitter specifications for
certification for Host mode operation.
3.8.3 USB VREG electrical specifications
Table 40. USB VREG electrical specifications
Symbol Description
Min.
2.7
—
Typ.1
Max.
5.5
Unit
V
Notes
VREGIN Input supply voltage
—
IDDon
IDDstby
IDDoff
Quiescent current — Run mode, load current
equal zero, input supply (VREGIN) > 3.6 V
125
186
μA
Quiescent current — Standby mode, load
current equal zero
—
1.1
10
μA
Quiescent current — Shutdown mode
—
—
650
—
—
4
nA
μA
• VREGIN = 5.0 V and temperature=25 °C
• Across operating voltage and
temperature
ILOADrun Maximum load current — Run mode
ILOADstby Maximum load current — Standby mode
—
—
—
—
120
1
mA
mA
VReg33out Regulator output voltage — Input supply
(VREGIN) > 3.6 V
• Run mode
3
3.3
2.8
—
3.6
3.6
3.6
V
V
V
• Standby mode
2.1
2.1
VReg33out Regulator output voltage — Input supply
(VREGIN) < 3.6 V, pass-through mode
2
COUT
ESR
External output capacitor
1.76
1
2.2
—
8.16
100
μF
External output capacitor equivalent series
resistance
mΩ
ILIM
Short circuit current
—
290
—
mA
1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.
2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to ILoad
.
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
49
NXP Semiconductors
ADC electrical specifications
3.8.4 LPSPI switching specifications
The Low Power Serial Peripheral Interface (LPSPI) provides a synchronous serial bus
with master and slave operations. Many of the transfer attributes are programmable.
The following tables provide timing characteristics for classic SPI timing modes.
All timing is shown with respect to 20% VDD and 80% VDD thresholds, unless noted, as
well as input signal transitions of 3 ns and a 30 pF maximum load on all LPSPI pins.
NOTE
• Slew rate disabled pads are those pins with
PORTx_PCRn[SRE] bit cleared. Slew rate enabled pads
are those pins with PORTx_PCRn[SRE] bit set.
• To achieve high bit rate, it is recommended to use fast
pins (PTE20, PTE21, PTE22, PTE23, PTD4, PTD5,
PTD6, and PTD7) and/or high drive pins (PTC3, PTC4,
PTD4, PTD5, PTD6, and PTD7).
Table 41. LPSPI master mode timing on slew rate disabled pads
Num.
Symbol Description
Min.
Max.
Unit
Hz
Note
1
2
fop
Frequency of operation
fperiph/2048
2 x tperiph
fperiph/2
1
2
tSPSCK
SPSCK period
2048 x
tperiph
ns
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
1024 x
tperiph
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
18
0
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
15
8
tv
—
0
9
tHO
tRI
—
10
—
tperiph - 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. fperiph is the LPSPI peripheral functional clock.
2. tperiph = 1/fperiph
Table 42. LPSPI master mode timing on slew rate enabled pads
Num.
Symbol Description
fop Frequency of operation
Min.
Max.
Unit
Note
1
fperiph/2048
fperiph/2
Hz
1
Table continues on the next page...
50
NXP Semiconductors
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
ADC electrical specifications
Table 42. LPSPI master mode timing on slew rate enabled pads (continued)
Num.
Symbol Description
Min.
Max.
Unit
Note
2
tSPSCK
SPSCK period
2 x tperiph
2048 x
tperiph
ns
2
3
4
5
tLead
tLag
Enable lead time
Enable lag time
1/2
1/2
—
—
tSPSCK
tSPSCK
ns
—
—
—
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
1024 x
tperiph
6
7
tSU
tHI
Data setup time (inputs)
Data hold time (inputs)
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
96
0
—
ns
ns
ns
ns
ns
—
—
—
—
—
—
52
8
tv
—
0
9
tHO
tRI
—
10
—
tperiph - 25
tFI
Fall time input
11
tRO
tFO
Rise time output
—
36
ns
—
Fall time output
1. fperiph is the LPSPI peripheral functional clock
2. tperiph = 1/fperiph
1
SS
(OUTPUT)
3
2
10
10
11
11
4
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
8
MSB IN
LSB IN
9
MOSI
(OUTPUT)
2
BIT 6 . . . 1
MSB OUT
LSB OUT
1. If configured as an output.
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 18. LPSPI master mode timing (CPHA = 0)
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
51
NXP Semiconductors
ADC electrical specifications
1
SS
(OUTPUT)
2
10
10
11
11
4
3
SPSCK
(CPOL=0)
(OUTPUT)
5
5
SPSCK
(CPOL=1)
(OUTPUT)
6
7
MISO
(INPUT)
2
BIT 6 . . . 1
LSB IN
MSB IN
9
8
MOSI
(OUTPUT)
2
PORT DATA
BIT 6 . . . 1
MASTER MSB OUT
PORT DATA
MASTER LSB OUT
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 19. LPSPI master mode timing (CPHA = 1)
Table 43. LPSPI slave mode timing on slew rate disabled pads
Num.
1
Symbol Description
Min.
Max.
fperiph/4
—
Unit
Hz
Note
1
fop
tSPSCK
tLead
tLag
Frequency of operation
0
2
SPSCK period
Enable lead time
Enable lag time
4 x tperiph
ns
2
3
1
—
tperiph
tperiph
ns
—
—
—
—
—
3
4
1
—
5
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
—
6
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
2.5
3.5
—
—
—
0
—
ns
7
—
ns
8
tperiph
tperiph
31
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
—
ns
—
tperiph - 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
25
ns
—
Fall time output
1. fperiph is the LPSPI peripheral functional clock
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
52
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
ADC electrical specifications
Table 44. LPSPI slave mode timing on slew rate enabled pads
Num.
1
Symbol Description
Min.
Max.
fperiph/4
—
Unit
Hz
Note
1
fop
tSPSCK
tLead
tLag
Frequency of operation
0
2
SPSCK period
Enable lead time
Enable lag time
4 x tperiph
ns
2
3
1
—
tperiph
tperiph
ns
—
—
—
—
—
3
4
1
—
5
tWSPSCK Clock (SPSCK) high or low time
tperiph - 30
—
6
tSU
tHI
ta
Data setup time (inputs)
Data hold time (inputs)
Slave access time
2
7
—
ns
7
—
ns
8
—
—
—
0
tperiph
tperiph
122
ns
9
tdis
tv
Slave MISO disable time
Data valid (after SPSCK edge)
Data hold time (outputs)
Rise time input
ns
4
10
11
12
ns
—
—
—
tHO
tRI
tFI
—
ns
—
tperiph - 25
ns
Fall time input
13
tRO
tFO
Rise time output
—
36
ns
—
Fall time output
1. fperiph is the LPSPI peripheral functional clock
2. tperiph = 1/fperiph
3. Time to data active from high-impedance state
4. Hold time to high-impedance state
SS
(INPUT)
2
12
12
13
4
SPSCK
(CPOL=0)
(INPUT)
5
5
3
13
11
SPSCK
(CPOL=1)
(INPUT)
9
8
10
11
see
note
SEE
NOTE
MISO
(OUTPUT)
BIT 6 . . . 1
SLAVE MSB
7
SLAVE LSB OUT
6
MOSI
(INPUT)
LSB IN
MSB IN
BIT 6 . . . 1
NOTE: Not defined
Figure 20. LPSPI slave mode timing (CPHA = 0)
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
53
NXP Semiconductors
ADC electrical specifications
SS
(INPUT)
4
2
12
12
13
13
3
SPSCK
(CPOL=0)
(INPUT)
5
5
SPSCK
(CPOL=1)
(INPUT)
11
9
10
SLAVE MSB OUT
see
note
MISO
(OUTPUT)
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
8
6
7
MOSI
(INPUT)
MSB IN
NOTE: Not defined
Figure 21. LPSPI slave mode timing (CPHA = 1)
3.8.5 LPI2C
Table 45. LPI2C specifications
Symbol Description
Min.
Max.
100
Unit
Notes
1
fSCL
SCL clock frequency
Standard mode (Sm)
Fast mode (Fm)
0
0
0
0
0
kHz
400
1, 2
1, 3
1, 4
1, 5
Fast mode Plus (Fm+)
Ultra Fast mode (UFm)
High speed mode (Hs-mode)
1000
5000
3400
1. See General switching specifications, measured at room temperature.
2. Measured with the maximum bus loading of 400pF at 3.3V VDD with pull-up Rp = 580Ω on normal drive pins or 350Ω on
high drive pins, and at 1.8V VDD with Rp = 880Ω. For all other cases, select appropriate Rp per I2C Bus Specification
and the pin drive capability.
3. Fm+ is only supported on high drive pin with high drive enabled. It is measured with the maximum bus loading of 400pF
at 3.3V VDD with Rp = 350Ω. For all other cases, select appropriate Rp per I2C Bus Specification and the pin drive
capability.
4. UFm is only supported on high drive pin with high drive enabled and push-pull output only mode. It is measured at 3.3V
VDD with the maximum bus loading of 400pF. For 1.8V VDD, the maximum speed is 4Mbps.
5. Hs-mode is only supported in slave mode and on the high drive pins with high drive enabled.
3.8.6 LPUART
See General switching specifications.
54
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
ADC electrical specifications
3.8.7 I2S/SAI switching specifications
This section provides the AC timing for the I2S/SAI module in master mode (clocks
are driven) and slave mode (clocks are input). All timing is given for noninverted
serial clock polarity (TCR2[BCP] is 0, RCR2[BCP] is 0) and a noninverted frame
sync (TCR4[FSP] is 0, RCR4[FSP] is 0). If the polarity of the clock and/or the frame
sync have been inverted, all the timing remains valid by inverting the bit clock signal
(BCLK) and/or the frame sync (FS) signal shown in the following figures.
3.8.7.1 Normal Run, Wait and Stop mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in Normal Run, Wait and Stop modes.
Table 46. I2S/SAI master mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
40
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK (as an input) pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
45%
80
55%
—
MCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
55%
15.5
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
0
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
0
19
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
26
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
55
NXP Semiconductors
ADC electrical specifications
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S5
S4
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 22. I2S/SAI timing — master modes
Table 47. I2S/SAI slave mode timing
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
80
3.6
—
V
S11
S12
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
S13
S14
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
10
2
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
0
33
—
—
—
28
ns
ns
ns
ns
ns
10
2
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
56
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
ADC electrical specifications
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 23. I2S/SAI timing — slave modes
3.8.7.2 VLPR, VLPW, and VLPS mode performance over the full
operating voltage range
This section provides the operating performance over the full operating voltage for the
device in VLPR, VLPW, and VLPS modes.
Table 48. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
62.5
3.6
—
V
S1
S2
S3
S4
S5
I2S_MCLK cycle time
ns
I2S_MCLK pulse width high/low
I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)
45%
250
55%
—
MCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%
55%
45
BCLK period
ns
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output valid
—
S6
I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/
I2S_RX_FS output invalid
—
ns
S7
S8
S9
I2S_TX_BCLK to I2S_TXD valid
I2S_TX_BCLK to I2S_TXD invalid
—
45
—
—
ns
ns
ns
I2S_RXD/I2S_RX_FS input setup before
I2S_RX_BCLK
S10
I2S_RXD/I2S_RX_FS input hold after
I2S_RX_BCLK
0
—
ns
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
57
NXP Semiconductors
ADC electrical specifications
S1
S2
S2
I2S_MCLK (output)
S3
S4
I2S_TX_BCLK/
I2S_RX_BCLK (output)
S5
S4
S6
I2S_TX_FS/
I2S_RX_FS (output)
S10
S9
I2S_TX_FS/
I2S_RX_FS (input)
S7
S8
S7
S8
I2S_TXD
S9
S10
I2S_RXD
Figure 24. I2S/SAI timing — master modes
Table 49. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)
Num.
Characteristic
Min.
Max.
Unit
Operating voltage
1.71
250
3.6
—
V
S11
I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)
ns
S12
S13
S14
I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low
(input)
45%
55%
MCLK period
I2S_TX_FS/I2S_RX_FS input setup before
I2S_TX_BCLK/I2S_RX_BCLK
30
—
ns
ns
I2S_TX_FS/I2S_RX_FS input hold after
I2S_TX_BCLK/I2S_RX_BCLK
—
S15
S16
S17
S18
S19
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid
I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid
I2S_RXD setup before I2S_RX_BCLK
—
0
ns
ns
ns
ns
ns
—
—
—
72
30
I2S_RXD hold after I2S_RX_BCLK
I2S_TX_FS input assertion to I2S_TXD output valid1
—
1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear
58
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
Dimensions
S11
S12
I2S_TX_BCLK/
I2S_RX_BCLK (input)
S12
S15
S15
S16
I2S_TX_FS/
I2S_RX_FS (output)
S13
S14
I2S_TX_FS/
I2S_RX_FS (input)
S15
S19
S16
S16
I2S_TXD
I2S_RXD
S17
S18
Figure 25. I2S/SAI timing — slave modes
3.9 Human-machine interfaces (HMI)
3.9.1 TSI electrical specifications
Table 50. TSI electrical specifications
Symbol
TSI_RUNF
TSI_RUNV
Description
Min.
—
Typ.
100
—
Max.
Unit
µA
Fixed power consumption in run mode
—
Variable power consumption in run mode
(depends on oscillator's current selection)
1.0
128
µA
TSI_EN
TSI_DIS
Power consumption in enable mode
Power consumption in disable mode
TSI analog enable time
—
—
100
1.2
66
—
—
µA
µA
µs
pF
V
TSI_TEN
—
—
TSI_CREF
TSI_DVOLT
TSI reference capacitor
—
1.0
—
—
Voltage variation of VP & VM around nominal
values
0.19
1.03
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
59
NXP Semiconductors
Pinouts and Packaging
To find a package drawing, go to nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
100-pin LQFP
Then use this document number
98ASS23308W
98ASA00595D
121-pin XFBGA
5 Pinouts and Packaging
5.1 KL28Z Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT function is available on each pin.
NOTE
The 121-pin XFBGA package for this product is not yet
available. However, it is included in a Package Your Way
program for Kinetis MCUs. Visit nxp.com/KPYW for more
details.
NOTE
• A pull-up resistor (typically 4.7 KΩ) must be connected to
the EMVSIM0_IO pin if this pin is configured as EMV
SIM function.
• PTB0/1, PTC3/4, PTD4/5/6/7 have both high drive and
normal/low drive capability. PTD4, PTD5, PTD6, PTD7,
PTE20, PTE21, PTE22, PTE23 are also fast pins. When a
high bit rate is required on the communication interface
pins, it is recommended to use fast pins. In case of high
bus loading, the high drive strength of high drive pins
must be enabled by setting the corresponding
PORTx_PCRn[DSE] bit.
• RESET_b pin is open drain with internal pullup device
and passive analog filter when configured as RESET pin
(default state after POR). When this pin is configured to
other shared functions, the passive analog filter is
disabled.
60
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
Pinouts and Packaging
• NMI0_b pin has pullup device enabled and passive
analog filter disabled after POR.
• SWD_DIO pin has pullup device enabled after POR.
SWD_CLK has pulldown device enabled after POR.
121
XFB
GA
100
LQFP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
E4
E3
E2
F4
H7
1
2
3
4
5
PTE0
ADC0_SE16
ADC0_SE17
ADC0_SE18
ADC0_SE19
DISABLED
ADC0_SE16
ADC0_SE17
ADC0_SE18
ADC0_SE19
PTE0/
RTC_CLKOUT
LPSPI1_SIN
LPUART1_TX
LPUART1_RX
CMP0_OUT
LPI2C1_SDA
LPI2C1_SCL
LPI2C1_SDAS
LPI2C1_SCLS
PTE1/
LLWU_P0
PTE1/
LLWU_P0
LPSPI1_
SOUT
PTE2/
LLWU_P1
PTE2/
LLWU_P1
LPSPI1_SCK
LPSPI1_SIN
LPSPI1_PCS0
LPUART1_
CTS_b
PTE3
PTE3
LPUART1_
RTS_b
PTE4/
PTE4/
LLWU_P2
LLWU_P2
G4
F3
6
7
PTE5
DISABLED
DISABLED
PTE5
LPSPI1_PCS1
LPSPI1_PCS2
PTE6/
LLWU_P16
PTE6/
LLWU_P16
I2S0_MCLK
USB_SOF_
OUT
E6
G7
L6
8
VDD
VDD
VDD
9
VSS
VSS
VSS
—
10
11
12
13
14
VSS
VSS
VSS
F1
F2
G1
G2
H1
USB0_DP
USB0_DM
VOUT33
VREGIN
PTE16
USB0_DP
USB0_DM
VOUT33
VREGIN
USB0_DP
USB0_DM
VOUT33
VREGIN
ADC0_DP1/
ADC0_SE1
ADC0_DP1/
ADC0_SE1
PTE16
LPSPI0_PCS0 LPUART2_TX
TPM0_CLKIN
LPSPI1_PCS3 FXIO0_D0
H2
15
PTE17/
LLWU_P19
ADC0_DM1/
ADC0_SE5a
ADC0_DM1/
ADC0_SE5a
PTE17/
LLWU_P19
LPSPI0_SCK
LPUART2_RX TPM1_CLKIN
LPTMR0_
ALT3/
FXIO0_D1
LPTMR1_
ALT3
J1
J2
K1
K2
L1
L2
F5
16
17
18
19
20
21
22
PTE18/
LLWU_P20
ADC0_DP2/
ADC0_SE2
ADC0_DP2/
ADC0_SE2
PTE18/
LLWU_P20
LPSPI0_
SOUT
LPUART2_
CTS_b
LPI2C0_SDA
LPI2C0_SCL
LPUART0_TX
LPUART0_RX
LPUART2_TX
LPUART2_RX
FXIO0_D2
FXIO0_D3
FXIO0_D4
FXIO0_D5
FXIO0_D6
FXIO0_D7
PTE19
PTE20
PTE21
PTE22
PTE23
VDDA
ADC0_DM2/
ADC0_SE6a
ADC0_DM2/
ADC0_SE6a
PTE19
PTE20
PTE21
PTE22
PTE23
LPSPI0_SIN
LPUART2_
RTS_b
ADC0_DP0/
ADC0_SE0
ADC0_DP0/
ADC0_SE0
LPSPI2_SCK
TPM1_CH0
TPM1_CH1
TPM2_CH0
ADC0_DM0/
ADC0_SE4a
ADC0_DM0/
ADC0_SE4a
LPSPI2_
SOUT
ADC0_DP3/
ADC0_SE3
ADC0_DP3/
ADC0_SE3
LPSPI2_SIN
ADC0_DM3/
ADC0_SE7a
ADC0_DM3/
ADC0_SE7a
LPSPI2_PCS0 TPM2_CH1
VDDA
VDDA
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
61
NXP Semiconductors
Pinouts and Packaging
121
XFB
GA
100
LQFP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
G5
23
VREFH/
VREFH/
VREFH/
VREF_OUT
VREF_OUT
VREF_OUT
G6
F6
L3
24
25
26
VREFL
VREFL
VREFL
VSSA
VSSA
VSSA
PTE29
CMP1_IN5/
CMP0_IN5/
ADC0_SE4b
CMP1_IN5/
CMP0_IN5/
ADC0_SE4b
PTE29
EMVSIM0_
CLK
TPM0_CH2
TPM0_CH3
TPM0_CLKIN
TPM1_CLKIN
K5
27
PTE30
PTE31
DAC0_OUT/
CMP1_IN3/
ADC0_SE23/
CMP0_IN4
DAC0_OUT/
CMP1_IN3/
ADC0_SE23/
CMP0_IN4
PTE30
PTE31
EMVSIM0_
RST
L4
28
DISABLED
EMVSIM0_
VCCEN
TPM0_CH4
TPM2_CLKIN
LPI2C0_
HREQ
L5
K6
H5
J5
29
30
31
32
VSS
VSS
VSS
VDD
VDD
VDD
PTE24
ADC0_SE20
ADC0_SE21
ADC0_SE20
ADC0_SE21
PTE24
EMVSIM0_IO
TPM0_CH0
LPI2C0_SCL
LPI2C0_SDA
PTE25/
PTE25/
EMVSIM0_PD TPM0_CH1
LLWU_P21
LLWU_P21
H6
J6
33
34
PTE26
PTA0
DISABLED
SWD_CLK
PTE26/
RTC_CLKOUT
TPM0_CH5
LPI2C0_SCLS
LPI2C0_SDAS
USB_CLKIN
SWD_CLK
TSI0_CH1
PTA0
LPUART0_
CTS_b
TPM0_CH5
H8
J7
35
36
37
PTA1
PTA2
PTA3
DISABLED
DISABLED
SWD_DIO
TSI0_CH2
TSI0_CH3
TSI0_CH4
PTA1
PTA2
PTA3
LPUART0_RX TPM2_CH0
LPUART0_TX
LPI2C1_SCL
TPM2_CH1
TPM0_CH0
H9
LPUART0_
RTS_b
SWD_DIO
NMI0_b
J8
38
39
PTA4/
LLWU_P3
DISABLED
DISABLED
TSI0_CH5
PTA4/
LLWU_P3
LPI2C1_SDA
USB_CLKIN
TPM0_CH1
TPM0_CH2
K7
PTA5
PTA5
LPI2C2_
HREQ
I2S0_TX_
BCLK
E5
G3
K3
H4
J9
—
—
40
41
—
VDD
VSS
VDD
VDD
VSS
VSS
PTA6
PTA7
DISABLED
DISABLED
DISABLED
PTA6
PTA7
TPM0_CH3
LPSPI0_PCS3 TPM0_CH4
LPSPI0_PCS2 TPM2_CH0
LPI2C2_SDAS
LPI2C2_SCLS
PTA10/
PTA10/
LLWU_P22
LLWU_P22
J4
—
PTA11/
DISABLED
PTA11/
LPSPI0_PCS1 TPM2_CH1
LPI2C2_SDA
LLWU_P23
LLWU_P23
K8
L8
42
43
PTA12
DISABLED
DISABLED
PTA12
TPM1_CH0
TPM1_CH1
LPI2C2_SCL
LPI2C2_SDA
I2S0_TXD0
PTA13/
PTA13/
I2S0_TX_FS
LLWU_P4
LLWU_P4
K9
L9
44
45
PTA14
PTA15
DISABLED
DISABLED
PTA14
PTA15
LPSPI0_PCS0 LPUART0_TX
LPI2C2_SCL
I2S0_RX_
BCLK
I2S0_TXD0
LPSPI0_SCK
LPUART0_RX
I2S0_RXD0
62
NXP Semiconductors
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
Pinouts and Packaging
121
XFB
GA
100
LQFP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
J10
46
47
PTA16
DISABLED
PTA16
LPSPI0_
SOUT
LPUART0_
CTS_b
I2S0_RX_FS
I2S0_MCLK
I2S0_RXD0
H10
PTA17
ADC0_SE22
ADC0_SE22
PTA17
LPSPI0_SIN
LPUART0_
RTS_b
L10
K10
L11
K11
48
49
50
51
VDD
VDD
VDD
VSS
VSS
VSS
PTA18
PTA19
EXTAL0
XTAL0
EXTAL0
XTAL0
PTA18
PTA19
LPUART1_RX TPM0_CLKIN
LPUART1_TX
TPM1_CLKIN
LPTMR0_
ALT1/
LPTMR1_
ALT1
J11
H11
G11
52
—
53
PTA20
PTA29
RESET_b
PTA20
PTA29
LPI2C0_SCLS
LPI2C0_SDAS
LPI2C0_SCL
TPM2_CLKIN
RESET_b
DISABLED
PTB0/
LLWU_P5
ADC0_SE8/
TSI0_CH0
ADC0_SE8/
TSI0_CH0
PTB0/
LLWU_P5
TPM1_CH0
TPM1_CH1
TPM2_CH0
TPM2_CH1
FXIO0_D8
FXIO0_D9
FXIO0_D10
FXIO0_D11
G10
G9
54
55
56
PTB1
PTB2
PTB3
ADC0_SE9/
TSI0_CH6
ADC0_SE9/
TSI0_CH6
PTB1
PTB2
PTB3
LPI2C0_SDA
LPI2C0_SCL
LPI2C0_SDA
ADC0_SE12/
TSI0_CH7
ADC0_SE12/
TSI0_CH7
LPUART0_
RTS_b
G8
ADC0_SE13/
TSI0_CH8
ADC0_SE13/
TSI0_CH8
LPSPI1_PCS3 LPUART0_
CTS_b
F11
E11
D11
E10
D10
C10
B10
—
57
58
59
60
61
62
PTB6
PTB7
PTB8
PTB9
PTB10
PTB11
PTB16
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
TSI0_CH9
PTB6
PTB7
PTB8
PTB9
PTB10
PTB11
PTB16
LPSPI1_PCS2
LPSPI1_PCS1
LPSPI1_PCS0
LPSPI1_SCK
LPSPI1_PCS0
LPSPI1_SCK
FXIO0_D12
FXIO0_D13
FXIO0_D14
FXIO0_D15
TPM2_CLKIN
TSI0_CH9
LPSPI1_
SOUT
LPUART0_RX TPM0_CLKIN
LPSPI2_PCS3 FXIO0_D16
E9
D9
63
64
PTB17
PTB18
TSI0_CH10
TSI0_CH11
TSI0_CH10
TSI0_CH11
PTB17
PTB18
LPSPI1_SIN
LPUART0_TX
TPM2_CH0
TPM1_CLKIN
LPSPI2_PCS2 FXIO0_D17
I2S0_TX_
BCLK
LPI2C1_
HREQ
FXIO0_D18
C9
F10
F9
65
66
67
68
PTB19
PTB20
PTB21
PTB22
TSI0_CH12
DISABLED
DISABLED
DISABLED
TSI0_CH12
PTB19
PTB20
PTB21
PTB22
TPM2_CH1
I2S0_TX_FS
LPSPI2_PCS1 FXIO0_D19
CMP0_OUT
LPSPI2_PCS0
LPSPI2_SCK
CMP1_OUT
F8
LPSPI2_
SOUT
E8
B9
69
70
PTB23
PTC0
DISABLED
PTB23
PTC0
LPSPI2_SIN
ADC0_SE14/
TSI0_CH13
ADC0_SE14/
TSI0_CH13
LPSPI2_PCS1
USB_SOF_
OUT
CMP0_OUT
I2S0_TXD0
I2S0_TXD0
D8
71
PTC1/
LLWU_P6
ADC0_SE15/
TSI0_CH14
ADC0_SE15/
TSI0_CH14
PTC1/
LLWU_P6
LPI2C1_SCL
LPUART1_
RTS_b
TPM0_CH0
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
63
NXP Semiconductors
Pinouts and Packaging
121
XFB
GA
100
LQFP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
C8
72
73
PTC2
ADC0_SE11/
CMP1_IN0/
TSI0_CH15
ADC0_SE11/
CMP1_IN0/
TSI0_CH15
PTC2
LPI2C1_SDA
LPUART1_
CTS_b
TPM0_CH1
I2S0_TX_FS
B8
PTC3/
LLWU_P7
CMP1_IN1
CMP1_IN1
PTC3/
LLWU_P7
LPSPI0_PCS1 LPUART1_RX TPM0_CH2
CLKOUT
I2S0_TX_
BCLK
F7
E7
74
75
—
—
76
VSS
VSS
VSS
VDD
VDD
VDD
B11
C11
A8
PTC22
PTC23
DISABLED
DISABLED
DISABLED
PTC22
PTC23
LPSPI0_PCS3
LPSPI0_PCS2
PTC4/
PTC4/
LLWU_P8
LPSPI0_PCS0 LPUART1_TX
TPM0_CH3
I2S0_RXD0
I2S0_MCLK
CMP1_OUT
CMP0_OUT
LLWU_P8
D7
77
PTC5/
DISABLED
PTC5/
LLWU_P9
LPSPI0_SCK
LPTMR0_
ALT2/
LLWU_P9
LPTMR1_
ALT2
C7
B7
78
79
PTC6/
LLWU_P10
CMP0_IN0
CMP0_IN1
CMP0_IN0
CMP0_IN1
PTC6/
LLWU_P10
LPSPI0_
SOUT
I2S0_RX_
BCLK
I2S0_MCLK
FXIO0_D20
PTC7
PTC7
LPSPI0_SIN
USB_SOF_
OUT
I2S0_RX_FS
A7
D6
80
81
PTC8
PTC9
CMP0_IN2
CMP0_IN3
CMP0_IN2
CMP0_IN3
PTC8
PTC9
LPI2C0_SCL
LPI2C0_SDA
TPM0_CH4
TPM0_CH5
I2S0_MCLK
FXIO0_D21
FXIO0_D22
I2S0_RX_
BCLK
C6
C5
82
83
PTC10
DISABLED
DISABLED
PTC10
LPI2C1_SCL
LPI2C1_SDA
I2S0_RX_FS
I2S0_RXD0
FXIO0_D23
PTC11/
PTC11/
LLWU_P11
LLWU_P11
B6
A6
A5
84
85
86
PTC12
PTC13
PTC14
DISABLED
DISABLED
DISABLED
PTC12
PTC13
PTC14
LPI2C1_SCLS
LPI2C1_SDAS
TPM0_CLKIN
TPM1_CLKIN
EMVSIM0_
CLK
B5
87
PTC15
DISABLED
PTC15
EMVSIM0_
RST
A11
—
88
89
90
VSS
VSS
VSS
VDD
VDD
VDD
D5
PTC16
DISABLED
PTC16
EMVSIM0_
VCCEN
C4
B4
A4
D4
91
92
—
93
PTC17
PTC18
PTC19
DISABLED
DISABLED
DISABLED
DISABLED
PTC17
PTC18
PTC19
EMVSIM0_IO
LPSPI0_PCS3
EMVSIM0_PD LPSPI0_PCS2
LPSPI0_PCS1
PTD0/
LLWU_P12
PTD0/
LLWU_P12
LPSPI0_PCS0 LPUART2_
RTS_b
TPM0_CH0
TPM0_CH1
FXIO0_D0
FXIO0_D1
FXIO0_D2
D3
C3
94
95
PTD1
ADC0_SE5b
DISABLED
ADC0_SE5b
PTD1
LPSPI0_SCK
LPUART2_
CTS_b
PTD2/
LLWU_P13
PTD2/
LLWU_P13
LPSPI0_
SOUT
LPUART2_RX TPM0_CH2
64
NXP Semiconductors
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
Pinouts and Packaging
121
XFB
GA
100
LQFP
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
B3
A3
96
97
PTD3
DISABLED
DISABLED
PTD3
LPSPI0_SIN
LPUART2_TX
TPM0_CH3
FXIO0_D3
FXIO0_D4
PTD4/
LLWU_P14
PTD4/
LLWU_P14
LPSPI1_PCS0 LPUART2_RX TPM0_CH4
LPUART0_
RTS_b
A2
B2
98
99
PTD5
ADC0_SE6b
ADC0_SE7b
ADC0_SE6b
ADC0_SE7b
PTD5
LPSPI1_SCK
LPUART2_TX
LPUART0_RX
TPM0_CH5
LPUART0_
CTS_b
FXIO0_D5
FXIO0_D6
PTD6/
LLWU_P15
PTD6/
LLWU_P15
LPSPI1_
SOUT
A1
100
—
PTD7
DISABLED
DISABLED
PTD7
LPSPI1_SIN
LPI2C0_SCL
LPUART0_TX
LPSPI1_PCS1
FXIO0_D7
A10
PTD8/
PTD8/
FXIO0_D24
LLWU_P24
LLWU_P24
A9
B1
C2
—
—
—
PTD9
DISABLED
DISABLED
DISABLED
PTD9
LPI2C0_SDA
LPSPI2_PCS3
FXIO0_D25
FXIO0_D26
FXIO0_D27
PTD10
PTD10
LPSPI2_PCS2 LPI2C0_SCLS
LPSPI2_PCS0 LPI2C0_SDAS
PTD11/
PTD11/
LLWU_P25
LLWU_P25
C1
D2
—
—
PTD12
PTD13
DISABLED
DISABLED
PTD12
PTD13
LPSPI2_SCK
FXIO0_D28
FXIO0_D29
LPSPI2_
SOUT
D1
E1
J3
—
—
—
—
—
—
PTD14
PTD15
NC
DISABLED
DISABLED
NC
PTD14
PTD15
LPSPI2_SIN
FXIO0_D30
FXIO0_D31
LPSPI2_PCS1
NC
NC
NC
NC
H3
K4
L7
NC
NC
NC
NC
NC
NC
5.2 KL28Z Pinouts
The below figure shows the pinout diagram for the devices supported by this
document. Many signals may be multiplexed onto a single pin. To determine what
signals can be used on which pin, see the previous section.
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
65
NXP Semiconductors
Pinouts and Packaging
1
2
3
4
5
6
7
8
9
10
11
PTD4/
LLWU_P14
PTC4/
LLWU_P8
PTD8/
LLWU_P24
A
B
C
D
E
F
G
H
J
PTD7
PTD10
PTD12
PTD14
PTD15
PTD5
PTC19
PTC14
PTC13
PTC8
PTD9
VSS
A
B
C
D
E
F
G
H
J
PTD6/
LLWU_P15
PTC3/
LLWU_P7
PTD3
PTC18
PTC17
PTC15
PTC12
PTC10
PTC9
VDD
PTC7
PTC0
PTB19
PTB18
PTB17
PTB21
PTB2
PTB16
PTB11
PTB10
PTB9
PTC22
PTC23
PTB8
PTB7
PTB6
PTD11/
PTD2/
LLWU_P25 LLWU_P13
PTC11/
LLWU_P11
PTC6/
LLWU_P10
PTC2
PTD0/
LLWU_P12
PTC5/
PTC1/
LLWU_P9 LLWU_P6
PTD13
PTD1
PTC16
VDD
PTE2/
PTE1/
PTE0
PTE3
PTE5
VDD
VSS
VSS
PTB23
PTB22
PTB3
LLWU_P1 LLWU_P0
PTE6/
USB0_DP USB0_DM
VDDA
VSSA
VREFL
PTE26
PTA0
PTB20
PTB1
LLWU_P16
VREFH/
VREF_OUT
PTB0/
LLWU_P5
VOUT33
PTE16
VREGIN
VSS
PTE17/
LLWU_P19
PTE4/
LLWU_P2
NC
NC
PTA7
PTE24
PTA1
PTA3
PTA17
PTA16
VSS
PTA29
PTA20
PTA19
PTE18/
LLWU_P20
PTA11/
LLWU_P23 LLWU_P21
PTE25/
PTA4/
LLWU_P3 LLWU_P22
PTA10/
PTE19
PTE21
PTA2
PTA5
K
L
PTE20
PTA6
NC
PTE30
VDD
PTA12
PTA14
K
L
PTA13/
LLWU_P4
PTE22
1
PTE23
2
PTE29
3
PTE31
4
VSS
5
VSS
6
NC
7
PTA15
9
VDD
10
PTA18
11
8
Figure 26. 121 XFBGA Pinout Diagram
66
NXP Semiconductors
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
Ordering parts
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PTE0
PTE1/LLWU_P0
PTE2/LLWU_P1
PTE3
VDD
2
VSS
3
PTC3/LLWU_P7
PTC2
4
5
PTC1/LLWU_P6
PTC0
PTE4/LLWU_P2
PTE5
6
7
PTB23
PTB22
PTB21
PTB20
PTB19
PTB18
PTB17
PTB16
PTB11
PTE6/LLWU_P16
VDD
8
9
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
USB0_DP
USB0_DM
VOUT33
VREGIN
PTE16
PTE17/LLWU_P19
PTE18/LLWU_P20
PTE19
PTB10
PTB9
PTB8
PTE20
PTB7
PTE21
PTB3
PTE22
PTB2
PTE23
PTB1
VDDA
PTB0/LLWU_P5
PTA20
VREFH/VREF_OUT
VREFL
PTA19
VSSA
Figure 27. 100 LQFP Pinout Diagram
6 Ordering parts
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
67
NXP Semiconductors
Design considerations
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to nxp.com and perform a part number search for the
following device numbers: PKL28Z and MKL28Z
7 Design considerations
7.1 Hardware design considerations
This device contains protective circuitry to guard against damage due to high static
voltage or electric fields. However, take normal precautions to avoid application of any
voltages higher than maximum-rated voltages to this high-impedance circuit.
7.1.1 Printed circuit board recommendations
• Place connectors or cables on one edge of the board and do not place digital circuits
between connectors.
• Drivers and filters for I/O functions must be placed as close to the connectors as
possible. Connect TVS devices at the connector to a good ground. Connect filter
capacitors at the connector to a good ground.
• Physically isolate analog circuits from digital circuits if possible.
• Place input filter capacitors as close to the MCU as possible.
• For best EMC performance, route signals as transmission lines; use a ground plane
directly under LQFP/MAPBGA packages.
7.1.2 Power delivery system
Consider the following items in the power delivery system:
• Use a plane for ground.
• Use a plane for MCU VDD supply if possible.
• Always route ground first, as a plane or continuous surface, and never as sequential
segments.
• Route power next, as a plane or traces that are parallel to ground traces.
• Place bulk capacitance, 10 μF or more, at the entrance of the power plane.
• Place bypass capacitors for MCU power domain as close as possible to each
VDD/VSS pair, including VDDA/VSSA and VREFH/VREFL.
68
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
NXP Semiconductors
Design considerations
• The minimum bypass requirement is to place 0.1 μF capacitors positioned as near
as possible to the package supply pins.
• The VREG_IN voltage range is 2.7 V to 5.5 V. Typically, 5.0V is applied here. If
USB module is used, this pin must be powered to make the USB transceiver also
powered. It is recommended to include a filter circuit with one bulk capacitor (no
less than 2.2 μF) and one 0.1 μF capacitor to VREG_IN at this pin to improve
USB performance. Total capacitors on VBUS should be less than 10 μF.
• Take special care to minimize noise levels on the VREFH/VREFL inputs. An
option is to use the internal reference voltage (output 1.2 V or 2.1 V typically) as
the ADC reference.
NOTE
The internal reference voltage output (VREF_OUT) is
bonded to the VREFH pin. When the VREF_OUT output is
used, a 0.1 μF capacitor is required as a filter. Do not
connect any other supply voltage to the pin that has
VREF_OUT activated.
7.1.3 Analog design
Each ADC input must have an RC filter as shown in the following figure. The
maximum value of R must be smaller than RAS max if high resolution is required.
The value of C must be chosen to ensure that the RC time constant is very small
compared to the sample period. See AN4373: Cookbook for SAR ADC
Measurements for how to select proper RC values.
MCU
1
2
Input signal
ADCx
R
C
Figure 28. RC circuit for ADC input
High voltage measurement circuits require voltage division, current limiting, and
overvoltage protection as shown the following figure. The voltage divider formed by
R1 – R4 must yield a voltage less than or equal to VREFH. Typically, VREFH is
connected to VDDA. The current must be limited to less than the negative injection
current limit. Since the ADC pins do not have diodes to VDD, external clamp diodes
must be included to protect against transient over-voltages.
Kinetis KL28Zxxx with 512 KB Flash and 128 KB SRAM, Rev. 3, 09/2020
69
NXP Semiconductors
Design considerations
MCU
R1
R2
R3
VDD
1
1
1
2
2
2
R5
1
2
ADCx
High voltage input
R4
1
2
C
BAT54SW
Figure 29. High voltage measurement with an ADC input
7.1.4 Digital design
Ensure that all I/O pins cannot get pulled above VDD (Max I/O is VDD+0.3V).
CAUTION
Do not provide power to I/O pins prior to VDD, especially the
RESET_b pin.
• High drive pins
PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6 and PTD7 I/O have both high
drive and normal drive capability selected by the associated PTx_PCRn[DSE]
control bit. All other GPIOs are normal drive only. When in high drive mode, the
sink/source current for a high drive pin can reach 20 mA. However, the total
current flowing into the MCU VDD must not exceed maximum limit of IDD.
• Fast pins
PTE20, PTE21, PTE22, PTE23, PTD4, PTD5, PTD6, PTD7 can support fast slew
rate of 0.5 ns and are used for high speed communications. It is set/cleared by
PTx_PCRn[SRE].
• Default I/O state
Most of digital pins are disabled (in high impedance state) after power up, so a pull-
up/down is needed to a determined level for some applications. Please refer to the
Signal Multiplexing and Pin Assignments chapter to know the default IO state for a
dedicate pin.
• RESET_b pin
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Design considerations
The RESET_b pin is an open-drain I/O pin that has an internal pullup resistor. An
external RC circuit is recommended to filter noise as shown in the following
figure. The resistor value must be in the range of 4.7 kΩ to 10 kΩ; the
recommended capacitance value is 0.1 μF. The RESET_b pin also has a selectable
digital filter to reject spurious noise.
VDD
MCU
10k
RESET_b
RESET_b
0.1uF
Figure 30. Reset circuit
When an external supervisor chip is connected to the RESET_b pin, a series
resistor must be used to avoid damaging the supervisor chip or the RESET_b pin,
as shown in the following figure. The series resistor value (RS below) must be in
the range of 100 Ω to 1 kΩ depending on the external reset chip drive strength.
The supervisor chip must have an active high, open-drain output.
VDD
Supervisor Chip
MCU
10k
1
2
OUT
RESET_b
RS
Active high,
open drain
0.1uF
Figure 31. Reset signal connection to external reset chip
• NMI pin
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Design considerations
Do not add a pull-down resistor or capacitor on the NMI_b pin, because a low level
on this pin will trigger non-maskable interrupt. When this pin is enabled as the NMI
function, an external pull-up resistor (10 kΩ) as shown in the following figure is
recommended for robustness.
If the NMI_b pin is used as an I/O pin, use the following two ways to disable NMI
function:
a. Define NMI interrupt handler in which NMI pin function is remapped to other
pin mux function
b. Disable NMI function by programming flash configuration byte at 0x40d for
FOPT, change FOPT[NMI_DIS] bit to zero. It will not take effect until next
reset.
VDD
MCU
10k
NMI_b
Figure 32. NMI pin biasing
• Debug interface
This MCU uses the standard Arm SWD interface protocol as shown in the
following figure. While pull-up or pull-down resistors are not required (SWD_DIO
has an internal pull-up and SWD_CLK has an internal pull-down), external 10 kΩ
pull resistors are recommended for system robustness. The RESET_b pin
recommendations mentioned above must also be considered.
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Design considerations
VDD
10k
VDD
J1
SWD_DIO
SWD_CLK
1
3
5
7
9
2
4
6
8
RESET_b
10k
10
0.1uF
HDR_5X2
Figure 33. SWD debug interface
• Low leakage stop mode wakeup
Select low leakage wakeup pins (LLWU_Px) to wake the MCU from one of the
low leakage stop modes (LLS/VLLSx). See KL28 Signal Multiplexing and Pin
Assignments chapter for pin selection.
• Unused pin
Unused GPIO pins must be left floating (no electrical connections) with the MUX
field of the pin’s PORTx_PCRn register equal to 000. This disables the digital
input path to the MCU.
If the USB module is not used, leave the USB data pins (USB0_DP, USB0_DM)
floating.
• EMVSIM
When using EMVSIM, a typical 4.7 KΩ pull up resistor should be added on the
EMVSIM_IO pin.
P3V3
R103
4.7K
EMVSIM HEADER
JP1
1
2
3
EMVSIM_CLK
PTC14
EMVSIM_RST
EMVSIM_VCCEN
EMVSIM_IO
4
5
6
7
PTC15
PTC16
PTC17
PTC18
EMVSIM_PD
HDR TH 1X7
GND
Figure 34. EMVSIM interface
• Pull up resistor for getting correct power consumption result
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Design considerations
Connect the pull up resistor to VDD_MCU for the pins like RESET and NMI. For
other pull up resistor, do not use VDD_MCU.
7.1.5 Crystal oscillator
When using an external crystal or ceramic resonator as the frequency reference for the
MCU clock system, refer to the following table and diagrams.
The feedback resistor, RF, is incorporated internally with the low power oscillators. An
external feedback is required when using high gain (HGO=1) mode. In harsh EMC
environment, it is recommended to use high gain mode. For low frequency (32 to 40
kHz), switching between high gain and low power is not supported.
The series resistor, RS, is used to limit current to external crystal or resonator to avoid
overdrive, and is required in high gain (HGO=1) mode when the crystal or resonator
frequency is below 2 MHz. The low power oscillator (HGO=0) must not have any
series resistor RS.
Internal load capacitors (Cx, Cy) are provided in the low frequency (32.786kHz) mode.
Use the SCxP bits in the SCG_SOSCCFG register to adjust the load capacitance for the
crystal. Typically, values of 10 pf to 16 pF are sufficient for 32.768 kHz crystals that
have a 12.5 pF CL specification. The internal load capacitor selection must not be used
for high frequency crystals and resonators. See crystal or resonator manufacturer's
recommendation for parameters about load capacitance and RF.
Table 51. External crystal/resonator connections
Oscillator mode
Diagram
Low frequency (32 kHz-40 kHz), low power
Low frequency (32 kHz-40 kHz), high gain
High/Medium frequency (1-32 MHz), low power
High/Medium frequency (1-32MHz), high gain
Diagram 1
Diagram 2, Diagram 4
Diagram 3
Diagram 4
OSCILLATOR
EXTAL
XTAL
1
2
CRYSTAL
Figure 35. Crystal connection – Diagram 1
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Design considerations
OSCILLATOR
EXTAL
XTAL
1
2
RF
RS
1
2
CRYSTAL
Figure 36. Crystal connection – Diagram 2
OSCILLATOR
EXTAL
OSCILLATOR
EXTAL
XTAL
XTAL
1
2
1
3
CRYSTAL
Cx
Cy
RESONATOR
Figure 37. Crystal connection – Diagram 3
OSCILLATOR
EXTAL
OSCILLATOR
EXTAL
XTAL
XTAL
1
2
1
2
RF
RF
RS
RS
1
2
1
3
CRYSTAL
Cx
Cy
RESONATOR
Figure 38. Crystal connection – Diagram 4
7.2 Software considerations
All Kinetis MCUs are supported by comprehensive NXP and third-party hardware and
software enablement solutions, which can reduce development costs and time to
market. Featured software and tools are listed below. Visit http://www.nxp.com/
kinetis/sw for more information and supporting collateral.
Evaluation and Prototyping Hardware
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Part identification
• NXP Freedom Development Platform: http://www.nxp.com/freedom
• Tower System Development Platform: http://www.nxp.com/tower
IDEs for Kinetis MCUs
• Kinetis Design Studio IDE: http://www.nxp.com/kds
• Partner IDEs: http://www.nxp.com/kide
Development Tools
• PEG Graphics Software: http://www.nxp.com/peg
• Processor Expert Software and Embedded Components: http://www.nxp.com/
processorexpert )
Run-time Software
• Kinetis SDK: http://www.nxp.com/ksdk
• Kinetis Bootloader: http://www.nxp.com/kboot
• Arm mbed Development Platform: http://www.nxp.com/mbed
• MQX RTOS: http://www.nxp.com/mqx
For all other partner-developed software and tools, visit http://www.nxp.com/partners.
8 Part identification
8.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
8.2 Format
Part numbers for this device have the following format:
Q KL## A FFF R T PP CC N
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Terminology and guidelines
8.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 52. Part number fields descriptions
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
KL##
A
Kinetis family
Key attribute
• KL28
FFF
Program flash memory size
• 256 = 256 KB
• 512 = 512 KB
R
Silicon revision
• (Blank) = Main
• A = Revision after main
T
Temperature range (°C)
Package identifier
• V = –40 to 105
PP
• LL = 100 LQFP (14 mm x 14 mm)
• DC = 121XFBGA (8mm x 8mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 7 = 72 MHz
• R = Tape and reel
• (Blank) = Trays
8.4 Example
This is an example part number:
MKL28Z512VDC7
MKL28Z512VLL7
9 Terminology and guidelines
9.1 Definitions
Key terms are defined in the following table:
Term
Definition
Rating
A minimum or maximum value of a technical characteristic that, if exceeded, may cause
permanent chip failure:
Table continues on the next page...
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Terminology and guidelines
Term
Definition
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
NOTE: The likelihood of permanent chip failure increases rapidly as soon as a characteristic
begins to exceed one of its operating ratings.
Operating requirement A specified value or range of values for a technical characteristic that you must guarantee during
operation to avoid incorrect operation and possibly decreasing the useful life of the chip
Operating behavior
A specified value or range of values for a technical characteristic that are guaranteed during
operation if you meet the operating requirements and any other specified conditions
Typical value
A specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Is representative of that characteristic during operation when you meet the typical-value
conditions or other specified conditions
NOTE: Typical values are provided as design guidelines and are neither tested nor
guaranteed.
9.2 Examples
Operating rating:
EXAMPLE
EXAMPLE
Operating requirement:
Operating behavior that includes a typical value:
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Terminology and guidelines
9.3 Typical-value conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
Supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
9.4 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
9.5 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
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Revision History
10 Revision History
The following table provides a revision history for this document.
Table 53. Revision History
Rev. No.
Date
Substantial Changes
0
1
08/2015
10/2015
Initial release
• Removed "Ready Play module (RPM)" from the features list
• Added "96 MHz high speed mode" to the features list under "Core"
• Updated the values in the following sections:
• Voltage and current operating requirements
• Power mode transition operating behaviors
• EMC radiated emissions operating behaviors
• General switching specifications
• Oscillator frequency specifications
• 16-bit ADC operating conditions
• LPSPI switching specifications
• LPI2C specifications
• Created new table for topic "Power consumption operating behaviors"
• Updated the pinouts
• Updated the "Terminology and guidelines" section to a new format
2
04/2016
• Removed 64-pin package information and marked 121-pin package information as
"Package Your Way"
• Updated the values in Power mode transition operating behaviors
• Updated values and resolved TBDs in Power consumption operating behaviors
• In section Diagram: Typical IDD_RUN operating behavior :
• Added "For the ALLON curve, all peripheral clocks are enabled as specified in
notes of Table 9."
• Updated figures
• Updated table in Slow IRC (SIRC) specifications
• Removed section "Specification Test Methods"
• In table VREF full-range operating behaviors, removed the user trim values and
updated the factory trim values
2.1
3
06/2016
09/2020
• In table Table 10 Low power mode peripheral adders — typical value, removed
IUSB_Alive
• In section Fast IRC (FIRC) specifications :
• In the Open loop total deviation of FIRC frequency at low voltage
(VDD=1.71V-1.89V) over full temperature specification, maximum regulator
disable value updated to 1.5.
• In the Open loop total deviation of FIRC frequency at high voltage
(VDD=1.89V-3.6V) over full temperature specification, maximum value updated
to 1.5.
• Added footnote stating "For temperatures -40 to 85 °C, the maximum value is
1%, characterized on a few samples of different slots. This value is not
guaranteed by production.".
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Date of release: September, 2020
Document identifier: MKL28Z512Vxx7
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