MKM33Z64CLL5_技术文档

Document Number: MKMxxZxxCxx5

Rev. 7, 01/2014

Freescale Semiconductor

Data Sheet: Technical Data

MKMxxZxxCxx5

KM Family

Supports the following:

MKM14Z64CHH5, MKM14Z128CHH5,

MKM33Z64CLH5, MKM33Z128CLH5,

MKM33Z64CLL5, MKM33Z128CLL5,

MKM34Z128CLL5

Features

Security and integrity modules

– Hardware programmable CRC module to support

fast cyclic redundancy checks

– Hardware random-number generator

– 128-bit unique identification (ID) number per chip

•

Operating Characteristics

•

– Voltage range: 1.71 V to 3.6 V (when Analog Front

End (AFE) is not used)

– Voltage range: 2.7 V to 3.6 V (when Analog Front

End (AFE) is used)

– iRTC battery supply voltage range: 1.71 to 3.6 V

– Flash write voltage range: 1.71 to 3.6 V

– Temperature range (ambient): -40°C to 85°C

Human-machine interface

– Segment LCD controller supporting up to 36

frontplanes and 8 backplanes or 40 frontplanes and 4

backplanes

Performance

– General-purpose input/output which can acts as

Rapid GPIO (single cycle access)

•

– Up to 50 MHz ARM Cortex-M0+ core delivering

0.95 Dhrystone MIPS per MHz

Analog modules

– 16-bit SAR ADC

– 24-bit Analog Front End comprising of 24-bit Sigma

Delta ADCs (after averaging)

•

Memories and memory interfaces

– 128/64 KB program flash memory. There is no

FlexMemory on these devices

– 16 KB of single access RAM

– Programmable Gain Amplifier (PGA with gains

upto 32)

– Two analog comparators (CMP) containing a 6-bit

DAC and programmable reference input

– 1.2V Voltage reference

Clocks

•

– 1 to 32 MHz crystal oscillator

– 32 kHz crystal oscillator

– Multi-purpose clock generator

Timers

•

System peripherals

– 4 channel Quad Timer with 16-bit counters

– Periodic interrupt timers

– 16-bit low-power timer

– Independent Real Time Clock with calendaring and

compensation

– Multiple low-power modes to provide power

optimization based on application requirements

– Memory protection unit with multi-master

protection

– 4-channel DMA controller, supporting up to 64

request sources

Communication interfaces

– One SPI module with FIFO support (supports 5V

AMR operation)

– External watchdog monitor

– Robust watchdog monitor

– Low-leakage wakeup unit

– Asynchronous wakeup unit

– Peripheral Crossbar (allows internal signals to be

connected to other on-chip modules)

– One SPI module without FIFO (no AMR operation)

– Two I2C modules with SMBus support

– Two UART modules with ISO7816 support and

Two UART without ISO 7816 support

– Any one SCI can be used for IrDA operation. 5V

AMR support on one SCI.

Freescale reserves the right to change the detail specifications as may be

required to permit improvements in the design of its products.

KM Family Data Sheet, Rev. 7, 01/2014.

2

Freescale Semiconductor, Inc.

Table of Contents

1 Ordering parts...........................................................................4

5.3 Switching specifications.....................................................18

5.3.1 Device clock specifications...................................18

5.3.2 General switching specifications...........................18

5.4 Thermal specifications.......................................................19

5.4.1 Thermal operating requirements...........................19

5.4.2 Thermal attributes.................................................19

6 Peripheral operating requirements and behaviors....................20

6.1 Core modules....................................................................21

6.1.1 Single Wire Debug (SWD)....................................21

6.1.2 Analog Front End (AFE)........................................21

6.2 Clock modules...................................................................22

6.2.1 MCG specifications...............................................22

6.2.2 Oscillator electrical specifications.........................24

6.2.3 32 kHz oscillator electrical characteristics.............27

6.3 Memories and memory interfaces.....................................28

6.3.1 Flash electrical specifications................................28

6.4 Analog...............................................................................29

6.4.1 ADC electrical specifications.................................29

6.4.2 CMP and 6-bit DAC electrical specifications.........33

6.4.3 Voltage reference electrical specifications............35

6.4.4 AFE electrical specifications.................................36

6.5 Timers................................................................................40

6.6 Communication interfaces.................................................40

6.6.1 I2C switching specifications..................................40

6.6.2 UART switching specifications..............................40

6.6.3 SPI switching specifications..................................40

6.7 Human-Machine Interfaces (HMI).....................................43

6.7.1 LCD electrical characteristics................................43

7 Dimensions...............................................................................44

7.1 Obtaining package dimensions.........................................45

8 Pinout........................................................................................45

8.1 KM Signal multiplexing and pin assignments....................45

8.2 KM Family Pinouts.............................................................48

9 Revision History........................................................................51

1.1 Determining valid order-able parts....................................4

2 Part identification......................................................................4

2.1 Description.........................................................................4

2.2 Format...............................................................................4

2.3 Fields.................................................................................4

2.4 Example............................................................................5

3 Terminology and guidelines......................................................5

3.1 Definition: Operating requirement......................................5

3.2 Definition: Operating behavior...........................................6

3.3 Definition: Attribute............................................................6

3.4 Definition: Rating...............................................................7

3.5 Result of exceeding a rating..............................................7

3.6 Relationship between ratings and operating

requirements......................................................................7

3.7 Guidelines for ratings and operating requirements............8

3.8 Definition: Typical value.....................................................8

3.9 Typical value conditions....................................................9

4 Ratings......................................................................................10

4.1 Thermal handling ratings...................................................10

4.2 Moisture handling ratings..................................................10

4.3 ESD handling ratings.........................................................10

4.4 Voltage and current operating ratings...............................11

5 General.....................................................................................11

5.1 AC electrical characteristics..............................................11

5.2 Nonswitching electrical specifications...............................11

5.2.1 Voltage and current operating requirements.........11

5.2.2 LVD and POR operating requirements.................12

5.2.3 Voltage and current operating behaviors..............13

5.2.4 Power mode transition operating behaviors..........14

5.2.5 Power consumption operating behaviors..............15

5.2.6 EMC radiated emissions operating behaviors.......17

5.2.7 Designing with radiated emissions in mind...........17

5.2.8 Capacitance attributes..........................................18

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

3

Ordering parts

1 Ordering parts

1.1 Determining valid order-able parts

Valid order-able part numbers are provided on the web. To determine the order-able part

numbers for this device, go to freescale.com and perform a part number search for the

following device numbers:

• MKM13Z64CHH5

• MKM14Z64CHH5

• MKM14Z128CHH5

• MKM32Z64CLH5

• MKM33Z64CLH5

• MKM33Z128CLH5

• MKM32Z64CLL5

• MKM33Z64CLL5

• MKM33Z128CLL5

• MKM34Z128CLL5

• MKM38Z128CLL5

2 Part identification

2.1 Description

Part numbers for the chip have fields that identify the specific part. You can use the

values of these fields to determine the specific part you have received.

2.2 Format

Part numbers for this device have the following format:

Q K M S R FFF T PP CC N

KM Family Data Sheet, Rev. 7, 01/2014.

4

Freescale Semiconductor, Inc.

Terminology and guidelines

2.3 Fields

Following table lists the possible values for each field in the part number (not all

combinations are valid):

Field

Description

Values

Q

Qualification status

• M = Fully qualified, general market flow

• P = Pre-qualification (Proto)

K

Main family

Sub family

• K = Kinetis

M

• M1 = Metering only (No LCD support)

• M3 = Metering with LCD support

S

Number of Sigma Delta (SD) ADC

• 2 = 1 SD ADC with PGA and 1 SD ADC

• 3 = 2 SD ADC with PGA and 1 SD ADC

• 4 = 2 SD ADC with PGA and 2 SD ADC

• 8 = Same as '4'.

R

Silicon revision

• Z = Initial

• (Blank) = Main

• A = Revision after main

FFF

Program flash memory size

• 64 = 64 KB

• 128 = 128 KB

T

Temperature range (°C)

Package identifier

• C = –40 to 85

PP

• HH = 44 LGA (5 mm x 5 mm)

• LH = 64 LQFP (10 mm x 10 mm)

• LL = 100 LQFP (14 mm x 14 mm)

CC

N

Maximum CPU frequency (MHz)

Packaging type

• 5 = 50 MHz

• R = Tape and reel

• (Blank) = Trays

2.4 Example

This is an example part number:

• MKM34Z128CLL5

3 Terminology and guidelines

3.1 Definition: Operating requirement

An operating requirement is a specified value or range of values for a technical

characteristic that you must guarantee during operation to avoid incorrect operation and

possibly decreasing the useful life of the chip.

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

5

Terminology and guidelines

3.1.1 Example

This is an example of an operating requirement:

Symbol

Description

Min.

Max.

Unit

V_DD

1.0 V core supply

voltage

0.9

1.1

V

3.2 Definition: Operating behavior

An operating behavior is a specified value or range of values for a technical

characteristic that are guaranteed during operation if you meet the operating requirements

and any other specified conditions.

3.2.1 Example

This is an example of an operating behavior:

Symbol

Description

Min.

Max.

Unit

I_WP

Digital I/O weak pullup/ 10

pulldown current

130

µA

3.3 Definition: Attribute

An attribute is a specified value or range of values for a technical characteristic that are

guaranteed, regardless of whether you meet the operating requirements.

3.3.1 Example

This is an example of an attribute:

Symbol

Description

Min.

Max.

Unit

CIN_D

Input capacitance:

digital pins

—

7

pF

KM Family Data Sheet, Rev. 7, 01/2014.

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Freescale Semiconductor, Inc.

Terminology and guidelines

3.4 Definition: Rating

A rating is a minimum or maximum value of a technical characteristic that, if exceeded,

may cause permanent chip failure:

• Operating ratings apply during operation of the chip.

• Handling ratings apply when the chip is not powered.

3.4.1 Example

This is an example of an operating rating:

Symbol

Description

Min.

Max.

Unit

V_DD

1.0 V core supply

voltage

–0.3

1.2

V

3.5 Result of exceeding a rating

40

30

The likelihood of permanent chip failure increases rapidly as

soon as a characteristic begins to exceed one of its operating ratings.

20

10

0

Operating rating

Measured characteristic

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

7

Terminology and guidelines

3.6 Relationship between ratings and operating requirements

Fatal range

Degraded operating range

Normal operating range

Degraded operating range

Fatal range

Expected permanent failure

- No permanent failure

- Possible decreased life

- Possible incorrect operation

- No permanent failure

- Correct operation

- No permanent failure

- Possible decreased life

- Possible incorrect operation

Expected permanent failure

–∞

∞

Operating (power on)

Fatal range

Handling range

Fatal range

Expected permanent failure

No permanent failure

Expected permanent failure

–∞

∞

Handling (power off)

3.7 Guidelines for ratings and operating requirements

Follow these guidelines for ratings and operating requirements:

• Never exceed any of the chip’s ratings.

• During normal operation, don’t exceed any of the chip’s operating requirements.

• If you must exceed an operating requirement at times other than during normal

operation (for example, during power sequencing), limit the duration as much as

possible.

3.8 Definition: Typical value

A typical value is a specified value for a technical characteristic that:

• Lies within the range of values specified by the operating behavior

• Given the typical manufacturing process, is representative of that characteristic

during operation when you meet the typical-value conditions or other specified

conditions

Typical values are provided as design guidelines and are neither tested nor guaranteed.

KM Family Data Sheet, Rev. 7, 01/2014.

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Freescale Semiconductor, Inc.

Terminology and guidelines

3.8.1 Example 1

This is an example of an operating behavior that includes a typical value:

Symbol

Description

Min.

Typ.

Max.

Unit

I_WP

Digital I/O weak

pullup/pulldown

current

10

70

130

µA

3.8.2 Example 2

This is an example of a chart that shows typical values for various voltage and

temperature conditions:

5000

4500

4000

T_J

3500

150 °C

3000

105 °C

2500

25 °C

2000

–40 °C

1500

1000

500

0

0.90

0.95

1.00

1.05

1.10

V_DD(V)

3.9 Typical value conditions

Typical values assume you meet the following conditions (or other conditions as

specified):

Symbol

Description

Ambient temperature

3.3 V supply voltage

Value

Unit

T_A

25

°C

V

V_DD

3.3

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

9

Ratings

4 Ratings

4.1 Thermal handling ratings

Symbol

T_STG

Description

Min.

–55

—

Max.

150

Unit

°C

Notes

Storage temperature

Solder temperature, lead-free

1

2

T_SDR

260

°C

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

4.2 Moisture handling ratings

Symbol

Description

Min.

Max.

Unit

Notes

MSL

Moisture sensitivity level

—

3

—

1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

4.3 ESD handling ratings

Symbol

Description

Min.

Max.

Unit

Notes

V_HBM

Electrostatic discharge voltage, human body model (All

pins except RESET pin)

-4000

+4000

V

1

Electrostatic discharge voltage, human body model

(RESET pin only)

-2500

-750

+2500

+750

V

1

2

3

V_CDM

Electrostatic discharge voltage, charged-device model

(for corner pins)

V_CDM

V_PESD

I_LAT

Electrostatic discharge voltage, charged-device model

Powered ESD voltage

-500

-6000

-100

+500

+6000

+100

V

Latch-up current at ambient temperature of 105°C

mA

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human Body

Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

KM Family Data Sheet, Rev. 7, 01/2014.

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Freescale Semiconductor, Inc.

General

4.4 Voltage and current operating ratings

Symbol

V_DD

Description

Min.

–0.3

–25

Max.

3.6

Unit

Digital supply voltage

V

V_DIO

Digital input voltage (except RESET, EXTAL, and XTAL)

V_DD+ 0.3

V_BAT+ 0.3

V_DD+ 0.3

25

V_DTamper

V_AIO

Tamper input voltage

Analog¹, RESET, EXTAL, and XTAL input voltage

V

I_D

Instantaneous maximum current single pin limit (applies to all

port pins)

mA

V_DDA

V_BAT

Analog supply voltage

V_DD– 0.3

–0.3

V_DD+ 0.3

3.6

V

RTC battery supply voltage

1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

5 General

5.1 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%

point, and rise and fall times are measured at the 20% and 80% points, as shown in the

following figure.

Figure 1. Input signal measurement reference

5.2 Nonswitching electrical specifications

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

11

General

5.2.1 Voltage and current operating requirements

Table 1. Voltage and current operating requirements

Symbol

Description

Min.

2.7

Max.

3.6

0.1

3.6

Unit

V

Notes

V_DD

Supply voltage when AFE is operational

Supply voltage when AFE is NOT operational

Analog supply voltage

1.71

2.7

V

V_DDA

V

V_DD– V_DDAV_DD-to-V_DDAdifferential voltage

V_SS– V_SSAV_SS-to-V_SSAdifferential voltage

–0.1

1.71

V

V_BAT

V_IH

RTC battery supply voltage

Input high voltage

V

1

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.7 V ≤ V_DD≤ 2.7 V

0.7 × V_DD

—

V

0.75 × V_DD

V_IL

Input low voltage

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.7 V ≤ V_DD≤ 2.7 V

—

0.35 × V_DD

0.3 × V_DD

V

V_HYS

I_ICDIO

Input hysteresis

0.06 × V_DD

-5

—

V

Digital pin negative DC injection current — single pin

• V_IN< V_SS-0.3V

mA

I_ICAIO

Analog², EXTAL, and XTAL pin DC injection current —

single pin

mA

-3

—

• V_IN< V_SS-0.3V (Negative current injection)

• V_IN> V_DD+0.3V (Positive current injection)

—

+3

I_ICcont

Contiguous pin DC injection current —regional limit,

includes sum of negative injection currents or sum of

positive injection currents of 16 contiguous pins

-25

—

mA

V

• Negative current injection

• Positive current injection

+25

V_RFVBAT

V_BATvoltage required to retain the VBAT register file

V_{POR_VBAT}

—

1. V_BATalways needs to be there for the chip to be operational.

2. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

5.2.2 LVD and POR operating requirements

Table 2. V_DDsupply LVD and POR operating requirements

Symbol Description

Min.

0.8

Typ.

1.1

Max.

1.5

Unit

V

Notes

V_POR

Falling VDD POR detect voltage

V_LVDH

Falling low-voltage detect threshold — high

range (LVDV=01)

2.48

2.56

2.64

V

Table continues on the next page...

KM Family Data Sheet, Rev. 7, 01/2014.

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General

Table 2. V_DDsupply LVD and POR operating requirements (continued)

Symbol Description

Low-voltage warning thresholds — high range

Min.

Typ.

Max.

Unit

Notes

1

V_LVW1H

V_LVW2H

V_LVW3H

V_LVW4H

• Level 1 falling (LVWV=00)

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

2.62

2.72

2.82

2.92

2.70

2.80

2.90

3.00

2.78

2.88

2.98

3.08

V

V_HYSH

V_LVDL

Low-voltage inhibit reset/recover hysteresis —

high range

—

80

—

mV

V

Falling low-voltage detect threshold — low range

(LVDV=00)

1.54

1.60

1.66

Low-voltage warning thresholds — low range

• Level 1 falling (LVWV=00)

1

V_LVW1L

V_LVW2L

V_LVW3L

V_LVW4L

1.74

1.84

1.94

2.04

1.80

1.90

2.00

2.10

1.86

1.96

2.06

2.16

V

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

V_HYSL

Low-voltage inhibit reset/recover hysteresis —

low range

—

60

—

mV

V_BG

t_LPO

Bandgap voltage reference

0.97

900

1.00

1.03

V

Internal low power oscillator period — factory

trimmed

1000

1100

μs

1. Rising threshold is the sum of falling threshold and hysteresis voltage

Table 3. VBAT power operating requirements

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_{POR_VBAT}Falling VBAT supply POR detect voltage

0.8

1.1

1.5

V

5.2.3 Voltage and current operating behaviors

Table 4. Voltage and current operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

V_OH

Output high voltage — high-drive strength

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= 20 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OH= 10 mA

V_DD– 0.5

—

V

Output high voltage — low-drive strength

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= 5 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OH= 2.5 mA

V_DD– 0.5

—

V

I_OHT

Output high current total for all ports

—

100

mA

Table continues on the next page...

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

13

General

Table 4. Voltage and current operating behaviors (continued)

Symbol

Description

Min.

Max.

Unit

Notes

V_OL

Output low voltage — high-drive strength

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 20 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OL= 10 mA

—

0.5

V

Output low voltage — low-drive strength

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 5 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OL= 2.5 mA

—

0.5

V

I_OLT

I_OZ

Output low current total for all ports

Hi-Z (off-state) leakage current (per pin)

Internal pullup resistors

—

30

100

1

mA

μA

kΩ

R_PU

R_PD

60

1,

2

Internal pulldown resistors

1. Measured at Vinput = V_SS

2. Measured at Vinput = V_DD

5.2.4 Power mode transition operating behaviors

All specifications except t_POR, and VLLSx→RUN recovery times in the following table

assume this clock configuration:

• CPU and system clocks = 50 MHz

• Bus clock = 25 MHz

• Flash clock = 25 MHz

• Temp: -40 °C, 25 °C, and 85 °C

• V_DD: 1.71 V, 3.3 V, and 3.6 V

Table 5. Power mode transition operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

t_POR

After a POR event, amount of time from the point V_DD

reaches 1.71 V to execute the first instruction across

the operating temperature range of the chip.

563

659

μs

1

—

372

273

5.0

μs

• VLLS0 → RUN

• VLLS1 → RUN

• VLLS2 → RUN

• VLLS3 → RUN

• VLPS → RUN

Table continues on the next page...

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General

Notes

Table 5. Power mode transition operating behaviors (continued)

Symbol

Description

Min.

Max.

Unit

—

5.0

μs

• STOP → RUN

1. Normal boot (FTFA_OPT[LPBOOT]=1)

5.2.5 Power consumption operating behaviors

Table 6. Power consumption operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_DDA

Analog supply current

—

See note

mA

1

2

I_{DD_RUN}Run mode current — all peripheral clocks

disabled, code executing from flash

• @ 3.0 V

—

6.17

6.39

6.93

7.1

6.7

8.3

mA

• 25 °C

• -40 °C

• 105 °C

I_{DD_RUN}Run mode current — all peripheral clocks

enabled, code executing from flash

2

• @ 3.0 V

—

8.24

8.26

9.00

10.4

9.8

mA

• 25 °C

• -40 °C

• 105 °C

11.5

I_{DD_WAIT}Wait mode high frequency current at 3.0 V— all

2

peripheral clocks disabled and Flash is not in

low-power

• 25 °C

—

3.95

4.65

4.4

6

mA

• -40 °C

• 105 °C

I_{DD_WAIT}Wait mode high frequency current at 3.0 V— all

2, 3

peripheral clocks disabled and Flash disabled

(put in low-power)

• 25 °C

—

3.81

4.4

4.2

5.8

mA

• -40 °C

• 105 °C

I_{DD_VLPR}Very-low-power run mode current at 3.0 V — all

4

5

peripheral clocks disabled

• 25 °C

—

248.8

245.30

535.40

500

470

μA

• -40 °C

• 105 °C

1800

I_{DD_VLPR}Very-low-power run mode current at 3.0 V — all

peripheral clocks enabled

• 25 °C

—

343.4

336.62

626.18

530

500

μA

• -40 °C

• 105 °C

2000

Table continues on the next page...

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

15

General

Table 6. Power consumption operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_{DD_VLPW}Very-low-power wait mode current at 3.0 V — all

6

peripheral clocks disabled

• 25 °C

—

162

350

330

μA

158.50

446.94

• -40 °C

• 105 °C

1700

I_{DD_STOP}Stop mode current at 3.0 V

• 25 °C

• -40 °C

• 105 °C

—

311.90

364

730

700

μA

645.13

2250

I_{DD_VLPS}Very-low-power stop mode current at 3.0 V

• 25 °C

• -40 °C

• 105 °C

—

8.56

1.98

1.24

0.89

0.35

0.472

0.3

46

44

μA

1500

I_{DD_VLLS3}Very low-leakage stop mode 3 current at 3.0 V

• 25 °C

• -40 °C

• 105 °C

—

3.5

3.3

85

μA

I_{DD_VLLS2}Very low-leakage stop mode 2 current at 3.0 V

• 25 °C

• -40 °C

• 105 °C

—

2.6

2.5

μA

59.5

I_{DD_VLLS1}Very low-leakage stop mode 1 current at 3.0 V

• 25 °C

• -40 °C

• 105 °C

—

1.7

1.6

μA

38.8

I_{DD_VLLS0}Very low-leakage stop mode 0 current at 3.0 V

with POR detect circuit disabled

—

0.67

0.64

38

μA

• 25 °C

• -40 °C

• 105 °C

I_{DD_VLLS0}Very low-leakage stop mode 0 current at 3.0 V

with POR detect circuit enabled

—

0.76

0.72

38.4

μA

• 25 °C

• -40 °C

• 105 °C

I_{DD_VBAT}Average current with RTC and 32 kHz disabled

at 3.0 V and VDD is OFF

• 25 °C

—

1

μA

0.95

15

• -40 °C

• 105 °C

Table continues on the next page...

KM Family Data Sheet, Rev. 7, 01/2014.

16

Freescale Semiconductor, Inc.

General

Table 6. Power consumption operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_{DD_VBAT}Average current when VDD is OFF and LFSR

and Tamper clocks set to 2 Hz.

8, 9

• @ 3.0 V

• 25 °C

—

1.3 ⁷

3

μA

2.5

16

• -40 °C

• 105 °C

1. See AFE specification for IDDA.

2. 50 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FBE mode. All peripheral

clocks disabled.

3. Should be reduced by 500 μA.

4. 2 MHz core, system, bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.

Code executing while (1) loop from flash.

5. 2 MHz core, system and bus clock, and 1MHz flash clock. MCG configured for BLPE mode. All peripheral clocks enabled

but peripherals are not in active operation. Code executing while (1) loop from flash.

6. 2 MHz core, system and bus clock, and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks disabled.

No flash accesses; some activity on DMA & RAM assumed.

7. Current consumption will vary with number of CPU accesses done and is dependent on the frequency of the accesses and

frequency of bus clock. Number of CPU accesses should be optimized to get optimal current value.

8. Includes 32 kHz oscillator current and RTC operation.

9. An external power switch for VBAT should be present on board to have better battery life and keep VBAT pin powered in

all conditions. There is no internal power switch in RTC.

5.2.6 EMC radiated emissions operating behaviors

Table 7. EMC radiated emissions operating behaviors

Symbol

Description

Frequency

band (MHz)

Typ.

Unit

Notes

V_RE1

V_RE2

Radiated emissions voltage, band 1

Radiated emissions voltage, band 2

Radiated emissions voltage, band 3

Radiated emissions voltage, band 4

IEC level

0.15–50

50–150

14

16

12

5

dBμV

—

1, 2

V_RE3

150–500

500–1000

0.15–1000

V_RE4

V_{RE_IEC}

M

2, 3

1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150

kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement of

Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and Wideband

TEM Cell Method. Measurements were made while the microcontroller was running basic application code. The reported

emission level is the value of the maximum measured emission, rounded up to the next whole number, from among the

measured orientations in each frequency range.

2. V_DD= 3.3 V, T_A= 25 °C, f_OSC= 10 MHz (crystal), f_SYS= 50 MHz, f_BUS= 25 MHz

3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and Wideband

TEM Cell Method

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

17

General

5.2.7 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions:

1. Go to www.freescale.com.

2. Perform a keyword search for “EMC design.”

5.2.8 Capacitance attributes

Table 8. Capacitance attributes

Symbol

C_{IN_A}

Description

Min.

—

Max.

Unit

pF

Input capacitance: analog pins

Input capacitance: digital pins

Input capacitance: fast digital pins

7

9

C_{IN_D}

—

pF

C_{IN_D_io60}

—

pF

5.3 Switching specifications

5.3.1 Device clock specifications

Table 9. Device clock specifications

Symbol

Description

Min.

Max.

Unit

Notes

Normal run mode

f_SYS

f_BUS

f_FLASH

f_AFE

System and core clock

Bus clock

50

25

6.5

MHz

Flash clock

AFE Modulator clock

VLPR mode¹

f_SYS

f_BUS

f_FLASH

f_AFE

System and core clock

Bus clock

2

1

MHz

Flash clock

AFE Modulator clock²

1

1.6

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for any

other module.

2. AFE working in low-power mode.

KM Family Data Sheet, Rev. 7, 01/2014.

18

Freescale Semiconductor, Inc.

General

5.3.2 General switching specifications

These general purpose specifications apply to all signals configured for GPIO, UART,

and I²C signals.

Table 10. General switching specifications

Symbol

Description

Min.

Max.

Unit

Notes

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

1.5

—

Bus clock

cycles

1

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Asynchronous path

16

—

ns

2

External reset pulse width (digital glitch filter disabled)

100

ns

2

3

Port rise and fall time—Low (All pins) and high drive

(only PTC2) strength

• Slew disabled

—

8

5

ns

• 1.71 ≤ V_DD≤ 2.7 V

• 2.7 ≤ V_DD≤ 3.6 V

• Slew enabled

—

27

16

ns

• 1.71 ≤ V_DD≤ 2.7 V

• 2.7 ≤ V_DD≤ 3.6 V

1. The greater synchronous and asynchronous timing must be met.

2. This is the shortest pulse that is guaranteed to be recognized.

3. Only PTC2 has high drive capability and load is 75 pF, other pins load (low drive) is 25 pF.

5.4 Thermal specifications

5.4.1 Thermal operating requirements

Table 11. Thermal operating requirements

Symbol

T_J

Description

Min.

–40

Max.

105

85

Unit

°C

Die junction temperature

Ambient temperature

T_A

°C

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

19

Peripheral operating requirements and behaviors

5.4.2 Thermal attributes

Board type

Symbol

Description

100 LQFP

44 LGA

Unit

Notes

Single-layer

(1s)

R_θJA

Thermal

resistance,

junction to

63

95

°C/W

1

ambient (natural

convection)

Four-layer

(2s2p)

R_θJA

Thermal

resistance,

junction to

ambient (natural

convection)

50

53

44

36

50

79

45

35

°C/W

1

2

Single-layer

(1s)

R_θJMA

R_θJB

Thermal

resistance,

junction to

ambient (200 ft./

min. air speed)

Four-layer

(2s2p)

Thermal

resistance,

junction to

ambient (200 ft./

min. air speed)

—

Thermal

resistance,

junction to

board

—

R_θJC

Thermal

resistance,

junction to case

18

3

28

4

°C/W

3

4

Ψ_JT

Thermal

characterization

parameter,

junction to

package top

outside center

(natural

convection)

1.

Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method

Environmental Conditions—Forced Convection (Moving Air).

2.

3.

Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board.

Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

temperature used for the case temperature. The value includes the thermal resistance of the interface material

between the top of the package and the cold plate.

4.

Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

6 Peripheral operating requirements and behaviors

KM Family Data Sheet, Rev. 7, 01/2014.

20

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

6.1 Core modules

6.1.1 Single Wire Debug (SWD)

Table 12. SWD switching characteristics at 2.7 V (2.7-3.6 V)

Symbol

SWD CLK

Description

Value

Unit

Notes

Frequency of SWD

operation

20

MHz

1

Inputs, tSUI

inputs,tHI

Data setup time

Data hold time

5

ns

1

0

after clock edge, tDVO Data valid Time

tHO Data Valid Hold

32

0

1. Input transition assumed =1 ns. Output transition assumed = 50 pf.

Table 13. Switching characteristics at 1.7 V (1.7-3.6 V)

Symbol

SWD CLK

Description

Value

Unit

Notes

Frequency of SWD

operation

18

MHz

Inputs, tSUI

inputs,tHI

Data setup time

Data hold time

4.7

0

ns

after clock edge, tDVO Data valid Time

tHO Data Valid Hold

49.4

0

2

1. Frequency of SWD clock (18 Mhz) is applicable only in case the input setup time of the device outside is not more than

6.15 ns, else the frequency of SWD clock would need to be lowered.

6.1.2 Analog Front End (AFE)

AFE switching characteristics at (2.7 V-3.6 V)

Case1: Clock is coming In and Data is also coming In (XBAR ports timed with respect to

the XBAR ports timed with respect to AFE clock defined at pad ptb[7] and pte[3])

Table 14. AFE switching characteristics (2.7 V-3.6 V)

Symbol

AFE CLK

Description

Value

Unit

Notes

Frequency of operation 10

MHz

ns

1

Inputs, tSUI

inputs,tHI

Data setup time

Data hold time

5

0

ns

1. Input Transition: 1ns. Output Load: 50 pf.

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

21

Peripheral operating requirements and behaviors

Case 2: Clock is going Out and Data is coming In (XBAR ports timed with respect to

generated clock defined at the XBAR out ports)

Table 15. AFE switching characteristics (2.7V-3.6V)

Symbol

AFE CLK

Description

Value

Unit

Notes

Frequency of operation 6.2

MHz

ns

Inputs, tSUI

inputs,tHI

Data setup time

Data hold time

36

0

ns

AFE switching characteristics at (1.7 V-3.6 V)

Case1: Clock is coming In and Data is also coming In ( XBAR ports timed with respect

to AFE clock defined at pad ptb[7] and pte[3])

Table 16. AFE switching characteristics (1.7 V-3.6 V)

Symbol

AFE CLK

Description

Value

Unit

Notes

Frequency of operation 10

MHz

ns

Inputs, tSUI

inputs,tHI

Data setup time

Data hold time

5.1

0

ns

Case 2: Clock is going Out and Data is coming In ( XBAR ports timed with respect to

generated clock defined at XBAR out ports)

Table 17. AFE switching characteristics (1.7 V-3.6 V)

Symbol

AFE CLK

Description

Value

Unit

Notes

Frequency of operation 6.2

MHz

ns

Inputs, tSUI

inputs,tHI

Data setup time

Data hold time

54

0

ns

6.2 Clock modules

6.2.1 MCG specifications

Table 18. MCG specifications

Symbol Description

f_{ints_ft}Internal reference frequency (slow clock) —

factory trimmed at nominal VDD and 25 °C

Min.

Typ.

Max.

Unit

Notes

—

32.768

—

kHz

Table continues on the next page...

KM Family Data Sheet, Rev. 7, 01/2014.

22

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 18. MCG specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

Δf_{ints_t}

Total deviation of internal reference frequency

(slow clock) over voltage and temperature

—

4

15

%

f_{ints_t}

Internal reference frequency (slow clock) — user

trimmed

31.25

—

33.4234

0.6

kHz

Δ_{fdco_res_t}Resolution of trimmed average DCO output

frequency at fixed voltage and temperature —

using SCTRIM and SCFTRIM

0.3

%f_dco

1

Δf_{dco_t}

Total deviation of trimmed average DCO output

frequency over voltage and temperature

—

%f_dco

1

Δf_{dco_t}

Total deviation of trimmed average DCO output

frequency over fixed voltage and temperature

range of 0–70°C

f_{intf_ft}

Δf_{intf_t}

f_{intf_t}

Internal reference frequency (fast clock) —

factory trimmed at nominal VDD and 25°C

4

MHz

%

Total deviation of internal reference frequency

(fast clock) over voltage and temperature

—

3

10

—

15

5

Internal reference frequency (fast clock) — user

trimmed at nominal VDD and 25 °C

MHz

kHz

f_{loc_low}

f_{loc_high}

Loss of external clock minimum frequency —

RANGE = 00

(3/5) x

f_{ints_t}

—

Loss of external clock minimum frequency —

RANGE = 01, 10, or 11

(16/5) x

f_{ints_t}

—

FLL

f_dco

DCO output

frequency range

Low-range (DRS=00)

640 × f_{ints_t}

20

40

60

80

—

20.97

41.94

62.91

83.89

23.99

47.97

71.99

95.98

22

45

67

90

—

MHz

2, 3

Mid-range (DRS=01)

1280 × f_{ints_t}

Mid-high range (DRS=10)

1920 × f_{ints_t}

High-range (DRS=11)

2560 × f_{ints_t}

f_{dco_t_DMX32}DCO output

frequency

Low-range (DRS=00)

732 × f_{ints_t}

4, 5, 6

Mid-range (DRS=01)

1464 × f_{ints_t}

Mid-high range (DRS=10)

2197 × f_{ints_t}

High-range (DRS=11)

2929 × f_{ints_t}

J_{cyc_fll}

FLL period jitter

—

70

—

140

1

ps

7

8

t_{fll_acquire}FLL target frequency acquisition time

ms

PLL

Table continues on the next page...

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

23

Peripheral operating requirements and behaviors

Table 18. MCG specifications (continued)

Symbol Description

f_vcoVCO operating frequency

Min.

Typ.

Max.

Unit

Notes

11.71875

12.288

14.648437

5

MHz

I_pll

PLL operating current

• IO 3.3 V current

9

—

300

100

—

39.0625

700

µA

kHz

ps

• Max core voltage current

f_{pll_ref}

PLL reference frequency range

PLL period jitter (RMS)

• f_vco= 12 MHz

31.25

32.768

J_{cyc_pll}

10

D_lock

D_unl

Lock entry frequency tolerance

Lock exit frequency tolerance

Lock detector detection time

1.49

4.47

—

2.98

5.97

150 × 10^-6

+ 1075(1/

%

s

11

12

t_{pll_lock}

f_{pll_ref}

)

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock

mode).

2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.

3. Chip max freq is 50 MHz, so Mid-range with DRS = 10 and High-range of DCO cannot be used and should not be

configured.

4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.

5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.

6. Chip max freq is 50 MHz, so Mid-range with DRS = 10 and High-range of DCO cannot be used and should not be

configured.

7. This specification is based on standard deviation (RMS) of period or frequency.

8. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,

DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,

FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

9. Excludes any oscillator currents that are also consuming power while PLL is in operation.

10. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of

each PCB and results will vary.

11. Will be updated later

12. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL disabled

(BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this specification assumes

it is already running.

6.2.2 Oscillator electrical specifications

6.2.2.1 Oscillator DC electrical specifications

Table 19. Oscillator DC electrical specifications

Symbol Description

V_DDSupply voltage

Min.

Typ.

Max.

Unit

Notes

1.71

—

3.6

V

Table continues on the next page...

KM Family Data Sheet, Rev. 7, 01/2014.

24

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 19. Oscillator DC electrical specifications (continued)

Symbol Description

I_DDOSCSupply current — low-power mode (HGO=0)

Min.

Typ.

Max.

Unit

Notes

1

• 32 kHz

—

500

200

300

950

1.2

—

nA

μA

mA

• 1 MHz

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

• 24 MHz

• 32 MHz

1.5

I_DDOSC

Supply current — high-gain mode (HGO=1)

1

• 32 kHz

—

25

300

400

500

2.5

3

—

μA

• 1 MHz

• 4 MHz

μA

• 8 MHz (RANGE=01)

• 16 MHz

μA

mA

• 24 MHz

• 32 MHz

4

C_x

C_y

EXTAL load capacitance

XTAL load capacitance

Capacitance of EXTAL

—

2, 3

247

ff

• Die level (100 LQFP)

• Package level (100 LQFP)

0.495

pF

Capacitance of XTAL

—

265

ff

• Die level (100 LQFP)

• Package level (100 LQFP)

0.495

pF

R_F

Feedback resistor — low-frequency, low-power

mode (HGO=0)

—

10

—

1

—

MΩ

2, 4

Feedback resistor — low-frequency, high-gain

mode (HGO=1)

Feedback resistor — high-frequency, low-power

mode (HGO=0)

Feedback resistor — high-frequency, high-gain

mode (HGO=1)

Table continues on the next page...

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

25

Peripheral operating requirements and behaviors

Table 19. Oscillator DC electrical specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

R_SSeries resistor — low-frequency, low-power

—

kΩ

mode (HGO=0)

Series resistor — low-frequency, high-gain mode

(HGO=1)

—

200

—

kΩ

Series resistor — high-frequency, low-power

mode (HGO=0)

Series resistor — high-frequency, high-gain

mode (HGO=1)

• 1 MHz resonator

• 2 MHz resonator

• 4 MHz resonator

• 8 MHz resonator

• 16 MHz resonator

• 20 MHz resonator

• 32 MHz resonator

—

6.6

3.3

0

—

kΩ

V

0

5

V_pp

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, low-power mode

(HGO=0)

0.6

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, high-gain mode

(HGO=1)

—

V_DD

0.6

—

V

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, low-power mode

(HGO=0)

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, high-gain mode

(HGO=1)

V_DD

1. V_DD=3.3 V, Temperature =25 °C

2. See crystal or resonator manufacturer's recommendation

3. C_xand C_ycan be provided by using either integrated capacitors or external components.

4. When low-power mode is selected, R_Fis integrated and must not be attached externally.

5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to any

other device.

6.2.2.2 Oscillator frequency specifications

Table 20. Oscillator frequency specifications

Symbol Description

f_{osc_lo}Oscillator crystal or resonator frequency — low-

frequency mode (MCG_C2[RANGE]=00)

Min.

Typ.

Max.

Unit

Notes

32

—

40

kHz

f_{osc_hi_1}Oscillator crystal or resonator frequency — high-

frequency mode (low range)

1

—

8

MHz

(MCG_C2[RANGE]=01)

Table continues on the next page...

KM Family Data Sheet, Rev. 7, 01/2014.

26

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 20. Oscillator frequency specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

f_{osc_hi_2}Oscillator crystal or resonator frequency — high

frequency mode (high range)

8

—

32

MHz

(MCG_C2[RANGE]=1x)

f_{ec_extal}

t_{dc_extal}

t_cst

Input clock frequency (external clock mode)

Input clock duty cycle (external clock mode)

—

40

—

48

60

—

MHz

%

1, 2

3, 4

50

Crystal startup time — 32 kHz low-frequency,

low-power mode (HGO=0)

ms

Crystal startup time — 32 kHz low-frequency,

high-gain mode (HGO=1)

—

ms

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), low-power mode

(HGO=0)

0.6

1

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), high-gain mode

(HGO=1)

—

ms

1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.

2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

3. Proper PC board layout procedures must be followed to achieve specifications.

4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S register

being set.

6.2.3 32 kHz oscillator electrical characteristics

6.2.3.1 32 kHz oscillator DC electrical specifications

Table 21. 32kHz oscillator DC electrical specifications

Symbol

V_BAT

R_F

Description

Min.

1.71

—

Typ.

—

Max.

3.6

—

Unit

V

Supply voltage

Internal feedback resistor

Parasitical capacitance of EXTAL32 and XTAL32

Peak-to-peak amplitude of oscillation

100

5

MΩ

pF

V

C_para

—

7

1

V_pp

—

0.6

—

1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to

required oscillator components and must not be connected to any other devices.

6.2.3.2 32 kHz oscillator frequency specifications

Table 22. 32 kHz oscillator frequency specifications

Symbol Description

f_{osc_lo}Oscillator crystal

Min.

Typ.

Max.

Unit

Notes

—

32.768

—

kHz

Table continues on the next page...

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

27

Peripheral operating requirements and behaviors

Table 22. 32 kHz oscillator frequency specifications (continued)

Symbol Description

Min.

—

Typ.

1000

—

Max.

—

Unit

ms

Notes

1

t_start

Crystal start-up time

v_{ec_extal32}Externally provided input clock amplitude

700

V_BAT

mV

2 , 3

1. Proper PC board layout procedures must be followed to achieve specifications.

2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input. The

oscillator remains enabled and XTAL32 must be left unconnected.

3. The parameter specified is a peak-to-peak value and V_IHand V_ILspecifications do not apply. The voltage of the applied

clock must be within the range of V_SSto V_BAT

.

NOTE

The 32 kHz oscillator works in low power mode by default and

cannot be moved into high power/gain mode.

6.3 Memories and memory interfaces

6.3.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

6.3.1.1 Flash timing specifications — program and erase

The following specifications represent the amount of time the internal charge pumps are

active and do not include command overhead.

Table 23. NVM program/erase timing specifications

Symbol Description

Min.

—

Typ.

7.5

13

Max.

18

Unit

μs

Notes

t_hvpgm4

Longword Program high-voltage time

t_hversscrSector Erase high-voltage time

—

113

452

ms

1

t_hversall

Erase All high-voltage time

—

52

1. Maximum time based on expectations at cycling end-of-life.

6.3.1.2 Flash timing specifications — commands

Table 24. Flash command timing specifications

Symbol Description

Min.

—

Typ.

—

Max.

60

Unit

μs

Notes

t_rd1sec1kRead 1s Section execution time (flash sector)

1

t_pgmchk

t_rdrsrc

Program Check execution time

Read Resource execution time

—

45

μs

—

30

μs

Table continues on the next page...

KM Family Data Sheet, Rev. 7, 01/2014.

28

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 24. Flash command timing specifications (continued)

Symbol Description

Min.

—

Typ.

65

14

—

Max.

145

114

1.8

25

Unit

μs

Notes

t_pgm4

t_ersscr

t_rd1all

Program Longword execution time

Erase Flash Sector execution time

Read 1s All Blocks execution time

Read Once execution time

—

ms

μs

2

1

—

t_rdonce

—

t_pgmonceProgram Once execution time

—

65

88

—

μs

t_ersall

Erase All Blocks execution time

—

650

30

ms

μs

2

1

t_vfykey

Verify Backdoor Access Key execution time

—

1. Assumes 25 MHz flash clock frequency.

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

6.3.1.3 Flash high voltage current behaviors

Table 25. Flash high voltage current behaviors

Symbol

Description

Min.

Typ.

Max.

Unit

I_{DD_PGM}

Average current adder during high voltage

flash programming operation

—

2.5

6.0

mA

I_{DD_ERS}

Average current adder during high voltage

flash erase operation

—

1.5

4.0

mA

6.3.1.4 Reliability specifications

Table 26. NVM reliability specifications

Symbol Description

Min.

Program Flash

Typ.¹

Max.

Unit

Notes

t_nvmretp10kData retention after up to 10 K cycles

t_nvmretp1kData retention after up to 1 K cycles

n_nvmcycpCycling endurance

5

50

—

years

cycles

20

100

50 K

10 K

2

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a constant

25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in Engineering

Bulletin EB619.

2. Cycling endurance represents number of program/erase cycles at -40 °C ≤ T_j≤ 125 °C.

6.4 Analog

6.4.1 ADC electrical specifications

All ADC channels meet the 12-bit single-ended accuracy specifications.

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

29

Peripheral operating requirements and behaviors

6.4.1.1 16-bit ADC operating conditions

Table 27. 16-bit ADC operating conditions

Symbol Description

Conditions

Min.

1.71

-100

1.13

Typ.¹

Max.

3.6

Unit

V

Notes

V_DDA

ΔV_DDA

ΔV_SSA

V_REFH

Supply voltage

Ground voltage

Absolute

—

Delta to V_DD(V_DD– V_DDA

)

0

+100

V_DDA

mV

V

2

Delta to V_SS(V_SS– V_SSA

)

0

ADC reference

voltage high

V_DDA

V_REFL

ADC reference

voltage low

V_SSA

V

V_ADIN

C_ADIN

Input voltage

V_REFL

—

8

V_REFH

10

V

Input capacitance

• 16-bit mode

pF

• 8-bit / 10-bit / 12-bit

modes

—

4

5

R_ADIN

R_AS

Input series

resistance

—

2

5

kΩ

Analog source

resistance

(external)

12-bit modes

f_ADCK< 4 MHz

3

—

f_ADCK

C_rate

ADC conversion ≤ 12-bit mode

clock frequency

1.0

2.0

—

18.0

12.0

MHz

4

5

ADC conversion 16-bit mode

clock frequency

ADC conversion ≤ 12-bit modes

rate

No ADC hardware averaging

20.000

37.037

—

818.330

461.467

Ksps

Continuous conversions

enabled, subsequent

conversion time

C_rate

ADC conversion 16-bit mode

5

rate

No ADC hardware averaging

Continuous conversions

enabled, subsequent

conversion time

1. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

2. DC potential difference.

3. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The R_AS/C_AS

time constant should be kept to < 1 ns.

4. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.

5. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

KM Family Data Sheet, Rev. 7, 01/2014.

30

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

SIMPLIFIED

INPUT PIN EQUIVALENT

CIRCUIT

Z_ADIN

SIMPLIFIED

CHANNEL SELECT

Pad

Z_AS

leakage

due to

input

CIRCUIT

ADC SAR

ENGINE

R_AS

R_ADIN

protection

V_ADIN

C_AS

V_AS

R_ADIN

INPUT PIN

R_ADIN

C_ADIN

Figure 2. ADC input impedance equivalency diagram

6.4.1.2 16-bit ADC electrical characteristics

Table 28. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA

)

Symbol Description

Conditions¹.

Min.

0.215

1.2

Typ.²

Max.

1.7

3.9

6.1

7.3

9.5

Unit

Notes

I_{DDA_ADC}Supply current

—

mA

3

ADC

asynchronous

• ADLPC = 1, ADHSC = 0

• ADLPC = 1, ADHSC = 1

• ADLPC = 0, ADHSC = 0

• ADLPC = 0, ADHSC = 1

2.4

4.0

5.2

6.2

t_ADACK= 1/

f_ADACK

MHz

2.4

clock source

f_ADACK

3.0

4.4

Sample Time

See Reference Manual chapter for sample times

TUE

DNL

Total unadjusted

error

• 12-bit modes

• <12-bit modes

—

4

6.8

2.1

LSB⁴

5

1.4

Differential non-

linearity

• 12-bit modes

—

0.7

–1.1 to

+1.9

–0.3 to 0.5

• <12-bit modes

• 12-bit modes

—

0.2

1.0

INL

Integral non-

linearity

–2.7 to

+1.9

LSB⁴

5

–0.7 to

+0.5

• <12-bit modes

—

0.5

Table continues on the next page...

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

31

Peripheral operating requirements and behaviors

Table 28. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA) (continued)

Symbol Description

Conditions¹.

Min.

—

Typ.²

Max.

–5.4

–1.8

—

Unit

Notes

E_FS

E_Q

Full-scale error

• 12-bit modes

• <12-bit modes

• 16-bit modes

• 12-bit modes

–4

LSB⁴

V_ADIN

V_DDA

=

5

—

–1.4

–1 to 0

—

Quantization

error

—

LSB⁴

—

0.5

ENOB

Effective number 16-bit single-ended mode

6

of bits

• Avg = 32

12.8

11.9

14.5

13.8

—

bits

• Avg = 4

12.2

11.4

13.9

13.1

—

bits

Signal-to-noise

plus distortion

See ENOB

SINAD

THD

6.02 × ENOB + 1.76

dB

Total harmonic

distortion

16-bit single-ended mode

• Avg = 32

7

—

82

78

-94

-85

95

—

dB

SFDR

Spurious free

dynamic range

16-bit single-ended mode

• Avg = 32

90

dB

E_IL

Input leakage

error

I_In× R_AS

mV

I_In=

leakage

current

(refer to

the MCU's

voltage

and current

operating

ratings)

Temp sensor

slope

Across the full temperature

range of the device

1.55

706

1.62

716

1.69

726

mV/°C

mV

8

V_TEMP25Temp sensor

voltage

25 °C

8

1. All accuracy numbers assume the ADC is calibrated with V_REFH= V_DDA

2. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 2.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low

power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1

MHz ADC conversion clock speed.

4. 1 LSB = (V_REFH- V_REFL)/2^N

5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)

6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.

7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.

KM Family Data Sheet, Rev. 7, 01/2014.

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Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

8. ADC conversion clock < 3 MHz

Figure 3. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

6.4.2 CMP and 6-bit DAC electrical specifications

Table 29. Comparator and 6-bit DAC electrical specifications

Symbol

V_DD

Description

Min.

1.71

—

Typ.

—

Max.

3.6

Unit

V

Supply voltage

I_DDHS

I_DDLS

V_AIN

Supply current, High-speed mode (EN=1, PMODE=1)

Supply current, low-speed mode (EN=1, PMODE=0)

Analog input voltage

—

200

20

μA

V

—

V_SS– 0.3

—

V_DD

20

V_AIO

Analog input offset voltage

Analog comparator hysteresis¹

• CR0[HYSTCTR] = 00

—

mV

V_H

—

5

—

mV

• CR0[HYSTCTR] = 01

10

20

30

• CR0[HYSTCTR] = 10

• CR0[HYSTCTR] = 11

V_CMPOh

V_CMPOl

t_DHS

Output high

Output low

V_DD– 0.5

—

50

—

0.5

200

V

—

Propagation delay, high-speed mode (EN=1,

PMODE=1)

20

ns

Table continues on the next page...

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

33

Peripheral operating requirements and behaviors

Table 29. Comparator and 6-bit DAC electrical specifications (continued)

Symbol

Description

Min.

Typ.

Max.

Unit

t_DLS

Propagation delay, low-speed mode (EN=1,

PMODE=0)

80

250

600

ns

Analog comparator initialization delay²

6-bit DAC current adder (enabled)

6-bit DAC integral non-linearity

—

7

40

—

μs

μA

LSB³

I_DAC6b

INL

–0.5

–0.3

—

0.5

0.3

DNL

6-bit DAC differential non-linearity

LSB

1. Typical hysteresis is measured with input voltage range limited to 0.6 to V_DD–0.6 V.

2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and

CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.

3. 1 LSB = V_reference/64

0.08

0.07

0.06

0.05

0.04

0.03

0.02

0.01

0

HYSTCTR

Setting

00

01

10

11

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vinlevel (V)

Figure 4. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

KM Family Data Sheet, Rev. 7, 01/2014.

34

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

0.18

0.16

0.14

0.12

0.1

HYSTCTR

Setting

00

01

10

11

0.08

0.06

0.04

0.02

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vinlevel (V)

Figure 5. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

6.4.3 Voltage reference electrical specifications

Table 30. 1.2 VREF full-range operating requirements

Symbol

V_DDA

T_A

Description

Min.

1.71¹

−40

Max.

3.6

Unit

V

Notes

Supply voltage

Temperature

85

°C

nF

C_L

Output load capacitance

100

2, 3

1. AFE is enabled.

2. C_Lmust be connected between VREFH and VREFL.

3. The load capacitance should not exceed +/-25% of the nominal specified C_Lvalue over the operating temperature range of

the device.

Table 31. VREF full-range operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

VREFH Voltage reference output with factory trim at

nominal V_DDAand temperature = 25 °C

1.1915

1.2

1.2027

V

VREFH Voltage reference output with — factory trim

1.1584

—

1.2376

V

Table continues on the next page...

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

35

Peripheral operating requirements and behaviors

Table 31. VREF full-range operating behaviors (continued)

Symbol Description

Min.

1.178

0.38

—

Typ.

—

Max.

1.202

0.42

—

Unit

V

Notes

VREFH Voltage reference output — user trim

VREFL Voltage reference output

0.4

0.5

5

V

V_step

V_tdrift

Voltage reference trim step

mV

Temperature drift (Vmax - Vmin across the full

temperature range)

—

1

Ac

I_bg

Aging coefficient

—

400

80

uV/yr

µA

Bandgap only current

Low-power buffer current

High-power buffer current

VREF buffer current

2

I_lp

0.19

0.5

1

µA

I_hp

mA

mV

2

I_LOAD

3

ΔV_LOADLoad regulation

• current = + 1.0 mA

2, 4

—

2

5

—

• current = - 1.0 mA

T_stup

Buffer startup time

—

20

—

ms

V_vdrift

Voltage drift (Vmax -Vmin across the full voltage

range)

0.5

mV

2

1. For temp range -40 °C to 105 °C, this value is 15 mV

2. See the chip's Reference Manual for the appropriate settings of VREF Status and Control register.

3. See the chip's Reference Manual for the appropriate settings of SIM Miscellaneous Control Register.

4. Load regulation voltage is the difference between VREFH voltage with no load vs. voltage with defined load.

Table 32. VREF limited-range operating requirements

Symbol

Description

Min.

Max.

Unit

Notes

T_A

Temperature

0

50

°C

Table 33. VREF limited-range operating behaviours

Symbol

Description

Min.

Max.

Unit

Notes

VREFH

Voltage reference

output with factory

trim

1.173

1.225

V

VREFL

Voltage reference

output

0.38

0.42

V

6.4.4 AFE electrical specifications

KM Family Data Sheet, Rev. 7, 01/2014.

36

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

6.4.4.1 ΣΔ ADC + PGA specifications

Table 34. ΣΔ ADC + PGA specifications

Symbo Description

l

Conditions

Min

Typ¹

Max

Unit

Notes

f_Nyq

Input bandwidth

Normal Mode

1.5

0.8

kHz

Low-Power Mode

1.5

0

V_CMInput Common Mode

Reference

V

VIN_diffDifferential input range

Gain = 1 (PGA ON/OFF)²

Gain = 2

+/- 500

+/- 250

+/- 125

+/- 62

mV

dB

Gain = 4

Gain = 8

Gain = 16

+/- 31

Gain = 32

+/- 15

SNR Signal to Noise Ratio

Normal Mode

90

92

• f_IN=50Hz; gain=01, common

mode=0V, V_pp=1000mV (full

range diff.)

88

82

90

86

• f_IN=50Hz; gain=02, common

mode=0V, V_pp= 500mV

(differential ended )

• f_IN=50Hz; gain=04, common

mode=0V, V_pp= 250mV

(differential ended )

• f_IN=50Hz; gain=08, common

mode=0V, V_pp= 125mV

(differential ended )

• f_IN=50Hz; gain=16, common

mode=0V, V_pp= 62mV

(differential ended )

76

70

82

78

• f_IN=50Hz; gain=32, common

mode=0V, V_pp= 31mV

(differential ended )

64

74

Low-Power Mode

dB

82

76

82

78

• f_IN=50Hz; gain=01, common

mode=0V, V_pp=1000mV (full

range diff.)

• f_IN=50Hz; gain=02, common

mode=0V, V_pp= 500mV

(differential ended )

• f_IN=50Hz; gain=04, common

mode=0V, V_pp= 250mV

(differential ended )

• f_IN=50Hz; gain=08, common

mode=0V, V_pp= 125mV

(differential ended )

70

64

74

70

• f_IN=50Hz; gain=16, common

mode=0V, V_pp= 62mV

(differential ended )

• f_IN=50Hz; gain=32, common

mode=0V, V_pp= 31mV

(differential ended )

58

52

66

62

Table continues on the next page...

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

37

Peripheral operating requirements and behaviors

Table 34. ΣΔ ADC + PGA specifications (continued)

Symbo Description

l

Conditions

Min

Typ¹

Max

Unit

Notes

SINAD Signal-to-Noise + Distortion Normal Mode

Ratio

dB

78

• f_IN=50Hz; gain=01, common

mode=0V, V_pp=500mV

(differential ended )

Low-Power Mode

dB

74

• f_IN=50Hz; gain=01, common

mode=0V, V_pp=500mV

(differential ended )

CMMR Common Mode Rejection

Ratio

• f_IN=50Hz; gain=01, common

mode=0V, Vid=100 mV

• f_IN=50Hz; gain=32, common

mode=0V, V_id=100 mV

70

E_offsetOffset Error

Gain=01, V_pp=1000 mV (full range

diff.)

+/- 5

mV

ΔOffset Offset Temperature Drift³

Temp

Gain=01, V_pp=1000mV (full range

diff.)

+/- 25 ppm/^oC

+/- 75 ppm/^oC

ΔGain_TeGain Temperate Drift - Gain

• Gain=01, V_pp=500mV

(differential ended )

• Gain=32, V_pp=15mV

(differential ended )

error caused by

mp

temperature drifts⁴

PSRR_AAC Power Supply Rejection Gain=01, VCC = 3V 100mV, f_IN

=

60

dB

Ratio

50 Hz

C

XT

Crosstalk (with the input of Gain=01, V_id= 500 mV, f_IN= 50 Hz

-100

dB

the affected channel

grounded)

f_MCLKModulator Clock Frequency Normal Mode

0.03

6.5

1.6

2.6

MHz

mA

Range

Low-Power Mode

I_{DDA_PG}Current consumption by

PGA (each channel)

Normal Mode (f_MCLK= 6.144 MHz,

OSR= 2048)

5

A

0

Low-Power Mode (f_MCLK= 0.768MHz,

OSR= 256)

I_{DDA_AD}Current Consumption by

ADC (each chanel)

Normal Mode (f_MCLK= 6.144 MHz,

OSR= 2048)

1.4

0.5

mA

C

Low-Power Mode (f_MCLK= 0.768MHz,

OSR= 256)

1. Typical values assume VDDA = 3.0 V, Temp = 25°C, f_MCLK= 6.144 MHz, OSR = 2048 for Normal mode and f_MCLK= 768

kHz, OSR = 256 for Low-Power Mode unless otherwise stated. Typical values are for reference only and are not tested in

production.

2. The full-scale input range in single-ended mode is 0.5Vpp

3. Represents combined offset temperature drift of the PGA, SD ADC and Internal 1.2 VREF blocks; Defined by shorting both

differential inputs to ground.

4. Represents combined gain temperature drift of the PGA, SD ADC and Internal 1.2 VREF blocks.

5. PGA is disabled in low-power modes.

KM Family Data Sheet, Rev. 7, 01/2014.

38

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

6.4.4.2 ΣΔ ADC Standalone specifications

Table 35. ΣΔ ADC standalone specifications

Symbo Description

l

Conditions

Min

Typ¹

Max

Unit

Notes

f_Nyq

Input bandwidth

Normal Mode

1.5

0.8

kHz

Low-Power Mode

1.5

0

1.5

V_CMInput Common Mode

Reference

V

VIN_diffInput range

Differential

+/- 500

+/- 250

mV

dB

Single Ended

Normal Mode

SNR Signal to Noise Ratio

88

76

90

78

• f_IN=50Hz; common mode=0V,

V_pp= 500mV (differential

ended )

• f_IN=50Hz; common mode=0V,

V_pp= 500mV (full range se.)

Low-Power Mode

• f_IN=50Hz; common mode=0V,

V_pp=500mV (diff.)

• f_IN=50Hz; common mode=0V,

V_pp=500mV (full range se.)

ΔGain_TeGain Temperate Drift - Gain

• Gain bypassed Vpp = 500 mV

(differential)

• PGA bypassed Vpp = 500 mV

(differential), VCM = 0 V

55

30

ppm/^oC

error caused by

mp

temperature drifts ²

ΔOffset Offset Temperate Drift -

• Gain bypassed Vpp = 500 mV

(differential), VCM = 0 V

ppm/^oC

dB

Offset error caused by

Temp

temperature drifts ³

SINAD Signal-to-Noise + Distortion Normal Mode

Ratio

80

74

• f_IN=50Hz; common mode=0V,

V_pp= 500mV (diff.)

• f_IN=50Hz; common mode=0V,

V_pp= 500mV (full range se.)

Low-Power Mode

• f_IN=50Hz; common mode=0V,

V_pp=500mV (diff.)

• f_IN=50Hz; common mode=0V,

V_pp=500mV (full range se.)

CMMR Common Mode Rejection

Ratio

• f_IN=50Hz; common mode=0V,

V_id=100 mV

90

60

dB

PSRR_AAC Power Supply Rejection Gain=01, VCC = 3V 100mV, f_IN

=

Ratio

50 Hz

C

XT

Crosstalk

Gain=01, V_id= 500 mV, f_IN= 50 Hz

-100

6.5

dB

f_MCLKModulator Clock Frequency Normal Mode

0.03

MHz

Range

Low-Power Mode

1.6

I_{DDA_AD}Current Consumption by

ADC (each channel)

Normal Mode (f_MCLK= 6.144 MHz,

OSR= 2048)

1.4

mA

C

0.5

Low-Power Mode (f_MCLK= 0.768MHz,

OSR= 256)

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

39

Peripheral operating requirements and behaviors

1. Typical values assume VDDA = 3.0 V, Temp = 25°C, f_MCLK= 6.144 MHz, OSR = 2048 for Normal mode and f_MCLK= 768

kHz, OSR = 256 for Low-Power Mode unless otherwise stated. Typical values are for reference only and are not tested in

production.

2. Represent combined gain temperature drift of the SD ADC, and Internal 1.2 VREF blocks.

3. Represent combined offset temperature drift of the SD ADC, and Internal 1.2 VREF blocks; Defined by shorting both

differential inputs to ground.

6.4.4.3 External modulator interface

The external modulator interface on this device comprises of a Clock signal and 1-bit

data signal. Depending on the modulator device being used the interface works as

follows:

• Clock supplied to external modulator which drives data on rising edge and the KM

device captures it on falling edge or next rising edge.

• Clock and data are supplied by external modulator and KM device can sample it on

falling edge or next rising edge.

Depending on control bit in AFE, the sampling edge is changed.

6.5 Timers

See General switching specifications.

6.6 Communication interfaces

6.6.1 I2C switching specifications

See General switching specifications.

6.6.2 UART switching specifications

See General switching specifications.

KM Family Data Sheet, Rev. 7, 01/2014.

40

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

6.6.3 SPI switching specifications

The Serial Peripheral Interface (SPI) provides a synchronous serial bus with master and

slave operations. Many of the transfer attributes are programmable. The following table

provides some reference values to be met on SoC.

Table 36. SPI switching characteristics at 2.7 V ( 2.7 - 3.6)

Description

Frequency of operation (F_sys

Min.

—

Max.

Unit

Notes

)

50

MHz

1

3

SCK frequency

• Master

2

12.5

—

MHz

Mhz

—

• Slave

SCK Duty Cycle

50%

Data Setup Time (inputs, tSUI)

ns

25

3

• Master

• Slave

Input Data Hold Time (inputs, tHI)

ns

0

1

• Master

• Slave

Data hold time (outputs, tHO)

• Master

0

• Slave

Data Valid Out Time (after SCK edge, tDVO)

13

28

• Master

• Slave

Rise time input

• Master

1

• Slave

Fall time input

• Master

1

• Slave

Rise time output

• Master

8.9

• Slave

Fall time output

• Master

7.8

• Slave

1. SPI modules will work on core clock.

2. F_sys/(Max Divider Value from registers)

3. F_SYS/2 in Master mode and F_SYS/4 in Slave mode. F_SYS/4 in Master as well as Slave Modes, where F_SYS=50Mhz

NOTE

The values assumed for input transition and output load are:

Input transition = 1 ns Output load = 50 pF

Table 37. SPI switching characteristics at 1.7 V ( 1.7 - 3.6)

Description

Min.

Max.

Unit

Notes

Frequency of operation (F_sys

)

—

50

MHz

Table continues on the next page...

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

41

Peripheral operating requirements and behaviors

Table 37. SPI switching characteristics at 1.7 V ( 1.7 - 3.6) (continued)

Description

Min.

Max.

Unit

Notes

SCK frequency

• Master

9

MHz

Mhz

—

• Slave

SCK Duty Cycle

50%

—

Data Setup Time (inputs, tSUI)

ns

42

• Master

• Slave

3.5

Input Data Hold Time (inputs, tHI)

ns

0

1

• Master

• Slave

Data hold time (outputs, tHO)

• Master

-3

0

• Slave

Data Valid Out Time (tDVO)

• Master

1

16

44

• Slave

Rise time input

• Master

1

• Slave

Fall time input

• Master

1

• Slave

Rise time output

• Master

14.4

• Slave

Fall time output

• Master

12.4

• Slave

1. SCK frequency of 9 Mhz is applicable only in the case that the input setup time of the device outside is not more than 11.5

ns, else the frequency would need to be lowered.

The following table represents SPI Switching specification in OD cells

Table 38. SPI switching characteristics at 1.7 V ( 1.7 - 3.6)

Description

Min.

Max.

Unit

Notes

Data Setup Time (inputs, tSUI)

ns

51

4

• Master

• Slave

Input Data Hold Time (inputs, tHI)

ns

0

1

• Master

• Slave

Data hold time (outputs, tHO)

• Master

-15

0

• Slave

Data Valid Out Time (tDVO)

• Master

61

93

• Slave

Table continues on the next page...

KM Family Data Sheet, Rev. 7, 01/2014.

42

Freescale Semiconductor, Inc.

Peripheral operating requirements and behaviors

Table 38. SPI switching characteristics at 1.7 V ( 1.7 - 3.6) (continued)

Description

Min.

Max.

Unit

Notes

Rise time input

• Master

ns

1

• Slave

Fall time input

• Master

ns

1

• Slave

Rise time output

• Master

30.4

• Slave

Fall time output

• Master

33.5

29.0

• Slave

Table 39. SPI switching characteristics at 2.7 V ( 2.7 - 3.6)

Description

Min.

Max.

Unit

Notes

Data Setup Time (inputs, tSUI)

ns

29

4

• Master

• Slave

Input Data Hold Time (inputs, tHI)

ns

0

1

• Master

• Slave

Data hold time (outputs, tHO)

• Master

0

• Slave

Data Valid Out Time (after SCK edge, tDVO)

49

• Master

• Slave

Rise time input

• Master

1

• Slave

Fall time input

• Master

1

• Slave

Rise time output

• Master

17.3

• Slave

Fall time output

• Master

16.6

16.0

• Slave

6.7 Human-Machine Interfaces (HMI)

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

43

Dimensions

6.7.1 LCD electrical characteristics

Table 40. LCD electricals

Symbol Description

f_FrameLCD frame frequency

C_LCDLCD charge pump capacitance — nominal value

C_BYLCDLCD bypass capacitance — nominal value

Min.

28

—

Typ.

30

Max.

58

Unit

Hz

nF

Notes

100

2000

—

1

2

3

—

nF

C_Glass

V_IREG

LCD glass capacitance

V_IREG

—

8000

pF

• HREFSEL=0, RVTRIM=1111

• HREFSEL=0, RVTRIM=1000

• HREFSEL=0, RVTRIM=0000

—

1.11

1.01

0.91

—

V

Δ_RTRIM

I_VIREG

I_RBIAS

V_IREGTRIM resolution

—

1

3.0

—

% V_IREG

µA

V_IREGcurrent adder — RVEN = 1

RBIAS current adder

4

—

15

3

—

µA

• LADJ = 10 or 11 — High load (LCD glass

capacitance ≤ 8000 pF)

• LADJ = 00 or 01 — Low load (LCD glass

capacitance ≤ 2000 pF)

VLL2

VLL3

VLL2 voltage

• HREFSEL = 0

2.0 − 5%

3.0 − 5%

2.0

3.0

—

V

VLL3 voltage

1. The actual value used could vary with tolerance.

2. For highest glass capacitance values, LCD_GCR[LADJ] should be configured as specified in the LCD Controller chapter

within the device's reference manual.

3. V_IREGmaximum should never be externally driven to any level other than V_DD- 0.15 V.

4. 2000 pF load LCD, 32 Hz frame frequency.

NOTE

KM family devices have a 1/3 bias controller that works with a

1/3 bias LCD glass. To avoid ghosting, the LCD OFF threshold

should be greater than VLL1 level. If the LCD glass has an

OFF threshold less than VLL1 level, use the internal VREG

mode and generate VLL1 internally using RVTRIM option.

This can reduce VLL1 level to allow for a lower OFF threshold

LCD glass.

7 Dimensions

KM Family Data Sheet, Rev. 7, 01/2014.

44

Freescale Semiconductor, Inc.

Pinout

7.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

To find a package drawing, go to freescale.com and perform a keyword search for the

drawing’s document number:

If you want the drawing for this package

44-pin LGA

Then use this document number

98ASA00239D

64-pin LQFP

100-pin LQFP

98ASS23234W

98ASS23308W

8 Pinout

NOTE

VSS also connects to flag on 44 LGA.

8.1 KM Signal multiplexing and pin assignments

100

64

44

DEFAULT

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

QFP

LGA

1

2

1

2

—

1

Disabled

LCD23

PTA0

PTA1

PTA2

PTA3

PTA4

PTA5

PTA6

PTA7

PTB0

Disabled

NMI_B

LCD24

LCD25

LCD26

LCD27

LCD28

LCD29

LCD30

LCD31

VDD

3

4

—

4

5

LLWU_P15

CMP0OUT

XBAR_IN0

XBAR_OUT0

NMI_B

6

5

2

Disabled

VDD

7

6

3

LLWU_P14

8

7

4

9

—

8

—

5

10

11

12

13

14

15

16

17

9

6

VSS

—

Disabled

LCD32

LCD33

LCD34

LCD35

LCD36

PTB1

PTB2

PTB3

PTB4

PTB5

PTB6

LCD37/

CMP1P0

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

45

Pinout

100

64

44

DEFAULT

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

QFP

LGA

18

19

20

10

11

12

—

Disabled

LCD38

PTB7

PTC0

PTC1

AFE_CLK

Disabled

LCD39

UART3_RTS

UART3_CTS

XBAR_IN1

LCD40/

CMP1P1

21

22

13

14

—

Disabled

LCD41

PTC2

PTC3

UART3_TxD

UART3_RxD

XBAR_OUT1

LLWU_P13

LCD42/

CMP0P3

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

—

15

16

17

18

—

19

20

21

22

23

24

25

26

27

28

—

7

Disabled

VBAT

LCD43

PTC4

VBAT

8

XTAL32K

EXTAL32K

VSS

XTAL32K

EXTAL32K

VSS

9

10

—

11

12

13

14

15

16

17

18

19

20

TAMPER2

TAMPER1

TAMPER0

VDDA

TAMPER2

TAMPER1

TAMPER0

VDDA

VSSA

SDADP0

SDADM0

SDADP1

SDADM1

VREFH

SDADP0

SDADM0

SDADP1

SDADM1

VREFH

VREFL

SDADP2/

CMP1P2

SDADP2/

CMP1P2

40

29

21

SDADM2/

CMP1P3

SDADM2/

CMP1P3

41

42

30

—

22

24

VREF

SDADP3/

CMP1P4

SDADP3/

CMP1P4

43

—

23

SDADM3/

CMP1P5

SDADM3/

CMP1P5

44

45

46

47

48

49

50

51

52

53

54

—

31

32

33

34

—

Disabled

AD0

PTC5

PTC6

PTC7

PTD0

PTD1

PTD2

PTD3

PTD4

PTD5

PTD6

PTD7

UART0_RTS

UART0_CTS

UART0_TxD

UART0_RxD

UART1_TxD

UART1_RxD

UART1_CTS

UART1_RTS

LPTMR2

LLWU_P12

TMR_1

AD1

AD2

XBAR_OUT2

XBAR_IN2

SPI0_SS_B

SPI0_SCK

SPI0_MOSI

SPI0_MISO

TMR_0

CMP0P0

LLWU_P11

XBAR_OUT3

XBAR_IN3

TMR_3

CMP0P1

LLWU_P10

AD3

LLWU_P9

AD4

UART3_CTS

UART3_RTS

UART3_RxD

AD5

LPTMR1

CMP1OUT

XBAR_IN4

LLWU_P8

LLWU_P7

CMP0P4

I2C0_SCL

KM Family Data Sheet, Rev. 7, 01/2014.

46

Freescale Semiconductor, Inc.

Pinout

100

64

44

DEFAULT

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

QFP

LGA

55

56

57

58

59

60

61

62

63

64

65

66

67

68

—

35

—

36

—

37

—

38

39

40

41

—

25

26

27

28

29

30

31

—

32

33

—

34

Disabled

PTE0

PTE1

PTE2

PTE3

I2C0_SDA

XBAR_OUT4

UART3_TxD

CLKOUT

RESET_B

EXTAL1

XTAL1

RESET_B

EXTAL1

EWM_IN

XBAR_IN6

AFE_CLK

I2C1_SDA

I2C1_SCL

XTAL1

EWM_OUT

VSS

SAR_VSSA

SAR_VDDA

VDD

SAR_VSSA

SAR_VDDA

VDD

Disabled

SWD_IO

SWD_CLK

Disabled

PTE4

PTE5

PTE6

PTE7

PTF0

PTF1

LPTMR0

UART2_CTS

UART2_RTS

UART2_RxD

UART2_TxD

TMR_2

EWM_IN

TMR_3

EWM_OUT

LLWU_P5

LLWU_P6

CMP0P2

AD6

XBAR_IN5

XBAR_OUT5

RTCCLKOUT

TMR_0

SWD_IO

SWD_CLK

AD7

CMP0OUT

LCD0/

AD8

XBAR_OUT6

69

42

35

Disabled

LCD1/

AD9

PTF2

CMP1OUT

RTCCLKOUT

70

71

72

73

74

75

76

43

44

45

46

47

48

49

—

36

Disabled

LCD2

LCD3

LCD4

LCD5

LCD6

LCD7

PTF3

PTF4

PTF5

PTF6

PTF7

PTG0

PTG1

SPI1_SS_B

SPI1_SCK

SPI1_MISO

SPI1_MOSI

TMR_2

LPTMR1

LPTMR0

I2C1_SCL

I2C1_SDA

CLKOUT

LPTMR2

LPTMR0

UART0_RxD

UART0_TxD

LLWU_P4

LLWU_P3

TMR_1

LCD8/

AD10

LLWU_P2

77

50

37

Disabled

LCD9/

AD11

PTG2

SPI0_SS_B

LLWU_P1

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

51

52

53

54

—

55

56

38

39

40

—

41

42

43

44

Disabled

LCD10

LCD11

LCD12

LCD13

LCD14

LCD15

LCD16

LCD17

LCD18

LCD19

LCD20

PTG3

PTG4

PTG5

PTG6

PTG7

PTH0

PTH1

PTH2

PTH3

PTH4

PTH5

PTH6

PTH7

PTI0

SPI0_SCK

SPI0_MOSI

SPI0_MISO

LLWU_P0

I2C0_SCL

I2C0_SDA

LPTMR1

LPTMR2

UART1_CTS

UART1_RTS

UART1_RxD

UART1_TxD

SPI1_SS_B

SPI1_SCK

XBAR_IN8

XBAR_OUT8

XBAR_IN7

XBAR_OUT7

SPI1_MISO

SPI1_MOSI

CMP0P5

SPI1_MOSI

SPI1_MISO

PTI1

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

47

Pinout

100

64

44

DEFAULT

ALT0

ALT1

ALT2

ALT3

ALT4

ALT5

ALT6

ALT7

QFP

LGA

93

94

95

96

97

98

99

100

57

58

59

60

61

62

63

64

—

Disabled

LCD21

PTI2

PTI3

Disabled

VSS

LCD22

VSS

VLL3

VLL2

VLL1

VCAP2

VCAP1

VCAP2

VCAP1

8.2 KM Family Pinouts

8.2.1 100-pin LQFP

The following figure represents the KM 100 LQFP pinouts:

KM Family Data Sheet, Rev. 7, 01/2014.

48

Freescale Semiconductor, Inc.

Pinout

1

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

PTA0/LCD23

PTA1/LCD24

PTG0/TMR_1/LPTMR2/LCD7

2

PTF7/TMR_2/CLKOUT/LCD6

3

PTA2/LCD25

PTF6/SPI1_MOSI/I2C1_SDA/LLWU_P3/LCD5

PTF5/SPI1_MISO/I2C1_SCL/LLWU_P4/LCD4

PTF4/SPI1_SCK/LPTMR0/UART0_TxD/LCD3

PTF3/SPI1_SS_B/LPTMR1/UART0_RxD/LCD2

PTF2/CMP1OUT/RTCCLKOUT/LCD1/AD9

PTF1/TMR_0/XBAR_OUT6/LCD0/AD8

PTF0/RTCCLKOUT/TMR_2/CMP0OUT/AD7

4

PTA3/LCD26

5

NMI_B/PTA4/LLWU_P15/LCD27

PTA5/CMP0OUT/LCD28

PTA6/XBAR_IN0/LLWU_P14/LCD29

PTA7/XBAR_OUT0/LCD30

PTB0/LCD31

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

SWD_CLK/PTE7/XBAR_OUT5/UART2_TxD/AD6

SWD_IO/PTE6/XBAR_IN5/UART2_RxD/LLWU_P5/CMP0P2

PTE5/TMR_3/UART2_RTS/EWM_OUT/LLWU_P6

PTE4/LPTMR0/UART2_CTS/EWM_IN

VDD

VSS

PTB1/LCD32

PTB2/LCD33

PTB3/LCD34

SAR_VDDA

PTB4/LCD35

SAR_VSSA

PTB5/LCD36

VSS

PTB6/LCD37/CMP1P0

PTB7/AFE_CLK/LCD38

PTC0/UART3_RTS/XBAR_IN1/LCD39

PTC1/UART3_CTS/LCD40/CMP1P1

PTC2/UART3_TxD/XBAR_OUT1/LCD41

PTC3/UART3_RxD/LLWU_P13/LCD42/CMP0P3

PTC4/LCD43

PTE3/EWM_OUT/AFE_CLK/I2C1_SCL/XTAL1

PTE2/EWM_IN/XBAR_IN6/I2C1_SDA/EXTAL1

RESET_B/PTE1

PTE0/I2C0_SDA/XBAR_OUT4/UART3_TxD/CLKOUT

PTD7/I2C0_SCL/XBAR_IN4/UART3_RxD/LLWU_P7/CMP0P4

PTD6/LPTMR1/CMP1OUT/UART3_RTS/LLWU_P8/AD5

PTD5/LPTMR2/TMR_0/UART3_CTS/AD4

PTD4/UART1_RTS/SPI0_MISO/LLWU_P9/AD3

VBAT

XTAL32K

Figure 6. 100-pin LQFP Pinout Diagram

8.2.2 64-pin LQFP

The following figure represents 64-pin LQFP pinouts:

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

49

Pinout

PTA0/LCD23

PTA1/LCD24

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

PTG0/TMR_1/LPTMR2/LCD7

2

PTF7/TMR_2/CLKOUT/LCD6

PTA2/LCD25

3

PTF6/SPI1_MOSI/I2C1_SDA/LLWU_P3/LCD5

PTF5/SPI1_MISO/I2C1_SCL/LLWU_P4/LCD4

PTF4/SPI1_SCK/LPTMR0/UART0_TxD/LCD3

PTF3/SPI1_SS_B/LPTMR1/UART0_RxD/LCD2

PTF2/CMP1OUT/RTCCLKOUT/LCD1/AD9

PTF1/TMR_0/XBAR_OUT6/LCD0/AD8

PTF0/RTCCLKOUT/TMR_2/CMP0OUT/AD7

SWD_CLK/PTE7/XBAR_OUT5/UART2_TxD/AD6

SWD_IO/PTE6/XBAR_IN5/UART2_RxD/LLWU_P5/CMP0P2

VDD

NMI_B/PTA4/LLWU_P15/LCD27

PTA5/CMP0OUT/LCD28

PTA6/XBAR_IN0/LLWU_P14/LCD29

PTA7/XBAR_OUT0/LCD30

VDD

4

5

6

7

8

VSS

9

PTB7/AFE_CLK/LCD38

10

11

12

13

14

15

16

PTC0/UART3_RTS/XBAR_IN1/LCD39

PTC1/UART3_CTS/LCD40/CMP1P1

PTC2/UART3_TxD/XBAR_OUT1/LCD41

PTC3/UART3_RxD/LLWU_P13/LCD42/CMP0P3

VBAT

VSS

RESET_B/PTE1

PTD4/UART1_RTS/SPI0_MISO/LLWU_P9/AD3

PTD3/UART1_CTS/SPI0_MOSI

XTAL32K

Figure 7. 64-pin LQFP Pinout Diagram

8.2.3 44-pin LGA

The following figure represents44-pin LGA pinouts:

KM Family Data Sheet, Rev. 7, 01/2014.

50

Freescale Semiconductor, Inc.

Revision History

SWD_CLK/PTE7/XBAR_OUT5/UART2_TxD/AD6

33

32

31

30

29

28

27

26

25

NMI_B/PTA4/LLWU_P15

1

2

SWD_IO/PTE6/XBAR_IN5/UART2_RxD/LLWU_P5/CMP0P2

PTA5/CMP0OUT

VDD

PTA6/XBAR_IN0/LLWU_P14

3

SAR_VDDA

PTA7/XBAR_OUT0

VDD

4

SAR_VSSA

5

VSS

6

PTE3/EWM_OUT/AFE_CLK/I2C1_SCL/XTAL1

PTE2/EWM_IN/XBAR_IN6/I2C1_SDA/EXTAL1

RESET_B/PTE1

VBAT

7

XTAL32K

EXTAL32K

VSS

8

9

10

11

SDADP3/CMP1P4

SDADM3/CMP1P5

24

23

TAMPER0

Figure 8. 44-pin LGA Pinout Diagram

NOTE

VSS also connects to flag on 44 LGA.

9 Revision History

The following table provides a revision history for this document.

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

51

Revision History

Table 41. Revision History

Rev. No.

Rev1

Date

Substantial Changes

10/2012

01/2013

Initial release

Rev2

Updated part numbers

Updated Table: Power mode transition operating behaviors

Updated Table: Power consumption operating behaviors. Included readings for

temperature - 40 °C, 25 °C, and 85 °C

Updated AFE Modulator clock maximum value in table “Device clock

specifications”

Updated Table: General switching specifications

Updated Table: Thermal operating requirements

Updated Table: SWD switching specifications

Added Table: AFE (Analog Frontend ) Switching characteristics

Updated Table: Oscillator DC electrical specifications

Updated Table: ΣΔ ADC + PGA specifications

Under section SPI switching specification,

• Table SPI timing renamed to SPI switching characteristics at 2.7 V ( 2.7 -

3.6)

• Modified row: “Data Hold Time (inputs, tHI)” to “Input Data Hold Time

(inputs, tHI)”

• Modified row: “Data valid time (after SCK edge, tDVO)” to “Data Valid Out

Time (after SCK edge, tDVO)”

Added table: SPI Switching characteristics at 1.7V (1.7 - 3.6V)

NOTE added to KM Signal Multiplexing and Pin Assignments topic

Updated orderable part numbers

Rev3

04/2013

Updated Table: ESD handling ratings

• Add new row: Electrostatic discharge voltage, charged-device mode

Updated Table: Voltage and current operating behaviors

Updated Table: Power consumption operating behaviors

Updated "Inputs, tSUI" row in Table: SWD switching characteristics at 2.7 V (2.7 -

3.6 V)

Updated "Inputs, tSUI" row in Table: AFE switching characteristics (1.7 V - 3.6 V)

Updated "Supply voltage" minimum value in table: Voltage reference electrical

specifications

Added table: OD cells in SPI Switching specification

Updated Table: VREF full-range operating behaviors

Updated Table: ΣΔ ADC + PGA specifications

Updated Table: ADC standalone specifications

Table continues on the next page...

KM Family Data Sheet, Rev. 7, 01/2014.

52

Freescale Semiconductor, Inc.

Revision History

Table 41. Revision History (continued)

Rev. No.

Date

Substantial Changes

Rev4

07/2013

Editorial changes through out the document.

Values of table "Power mode transition operating behaviors" updated.

In table "Power consumption operating behaviors":

• Row I_{DD_RUN}value updated

• Row I_{DD_WAIT}value updated

• Row I_{DD_VLPR}value updated

• Row I_{DD_VLPW}value updated

• Row I_{DD_STOP}value updated

• Row I_{DD_VLPS}value updated

• Row I_{DD_VLLS3}value updated

• Row I_{DD_VLLS2}value updated

• Row I_{DD_VLLS1}value updated

• Row I_{DD_VLLS0}value updated

• Row I_{DD_VBAT}value updated

• New row "I_{DD_VLLS0}with POR enabled" added.

Values of table "General switching specifications" updated.

In table "VREF full-range operating behaviors":

• Row V_tdrift: value updated and footnote added.

In table "LCD electricals":

• Row I_RBIAS: values updated.

Rev5

Rev6

10/2013

11/2013

Table: Obtaining package dimensions updated

Updated Section Fields:

• Row: Temperature range values updated.

Updated Table: Power consumption operating behaviors

Rev7

1/2014

• Table: Power consumption operating behaviors

• All rows with temperature 110 °C updated to 105 °C

• Footnote 9 updated: An external power switch for VBAT should be

present on board to have better battery life and keep VBAT pin

powered in all conditions. There is no internal power switch in RTC.

• Row I_{DD_VLPR}: Minimum value updated

• Row I_{DD_VLLS1}: Typ value updated

• Row I_{DD_VLLS0}with POR circuit disabled: Typ value updated

• Row I_{DD_VLLS0}with POR circuit enabled: Typ value updated

• Table: EMC radiated emissions operating behaviors

• All TBD updated

• Footnote 2: f_oscvalue updated to 10 MHz

• Table: ADC + PGA specifications

• Row CMMR: V_idvalue updated

• Table: ADC standalone specifications

• Row CMMR: V_idvalue updated

KM Family Data Sheet, Rev. 7, 01/2014.

Freescale Semiconductor, Inc.

53

Information in this document is provided solely to enable system and

software implementers to use Freescale products. There are no express

or implied copyright licenses granted hereunder to design or fabricate

any integrated circuits based on the information in this document.

Freescale reserves the right to make changes without further notice to

any products herein.

How to Reach Us:

Home Page:

freescale.com

Web Support:

freescale.com/support

Freescale makes no warranty, representation, or guarantee regarding

the suitability of its products for any particular purpose, nor does

Freescale assume any liability arising out of the application or use of

any product or circuit, and specifically disclaims any and all liability,

including without limitation consequential or incidental damages.

“Typical” parameters that may be provided in Freescale data sheets

and/or specifications can and do vary in different applications, and

actual performance may vary over time. All operating parameters,

including “typicals,” must be validated for each customer application by

customer's technical experts. Freescale does not convey any license

under its patent rights nor the rights of others. Freescale sells products

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at the following address: freescale.com/SalesTermsandConditions.

Freescale, the Freescale logo, and Kinetis are trademarks of Freescale

Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product or

service names are the property of their respective owners. ARM and

Cortex are the registered trademarks of ARM Limited.

Document Number MKMxxZxxCxx5

Revision 7, 01/2014


型号：	MKM33Z64CLL5
厂家：	NXP
描述：	Security and integrity modules
文件：	总54页 (文件大小：1813K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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