MKV46F256VLH16 [NXP]
168 MHz ARM Cortex-M4 core based Microcontroller with FPU;
| 型号： | MKV46F256VLH16 |
| 厂家： | 
NXP |
| 描述： | 168 MHz ARM Cortex-M4 core based Microcontroller with FPU 微控制器 |
| 文件： | 总63页 (文件大小：773K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NXP Semiconductors
Data Sheet: Technical Data
KV4XP100M168
Rev. 3, 06/2016
KV4x Data Sheet
MKV46FxxxVLy16
MKV44FxxxVLy16
MKV42FxxxVLy16
168 MHz ARM Cortex-M4 core based Microcontroller with
FPU
The Kinetis KV4x MCU family is a member of the Kinetis V
series and provides a high-performance solution for motor
control and Digital Power Conversion. Built upon the ARM®
Cortex®-M4 core operating at up to 168 MHz with DSP and
floating point unit, features include; dual 12-bit analog-to-digital
converters with 240ns conversion time, up to 30 PWM channels
for support of multi-motor systems, eFlexPWM module with 312
ps resolution for digital power conversion applications,
programmable delay block, memory protection unit, dual
FlexCAN modules and 64 to 256 KB of flash memory. KV4x
MCUs are offered in 48LQFP, 64LQFP, and 100LQFP
packages. All Kinetis V series MCUs are supported by a
comprehensive enablement suite from NXP and third-party
resources including reference designs, software libraries and
100 LQFP
64 LQFP
14 x 14 x 1.4 Pitch 0.5 10 x 10 x 1.4 Pitch 0.5
mm
mm
48 LQFP
7 x 7 x 1.4 Pitch 0.5 mm
motor configuration tools. KV4x MCUs are enabled to support Kinetis Motor Suite (KMS), a bundled hardware
and software solution that enables rapid configuration of BLDC and PMSM motor drive systems.
Core
• ARM® Cortex®-M4 core up to 168 MHz with single
precision Floating Point Unit (FPU)
Communication interfaces
• Two Universal Asynchronous Receiver/Transmitter
(UART) / FlexSCI modules with programmable 8- or
9-bit data format
Memories
• One 16-bit SPI module
• Up to 256 KB of program flash memory
• Up to 32 KB of RAM
• One I2C module
• Two FlexCAN modules
System peripherals
Analog Modules
• 16-channel DMA controller
• Low-leakage wakeup unit
• SWD interface and Micro Trace buffer
• Advanced independent clocked watchdog
• Two 12-bit cyclic ADCs
• Four analog comparator (CMP) containing a 6-bit
DAC and programmable reference input
• One 12-bit DAC
Clocks
Timers
• 32 to 40 kHz or 3 to 32 MHz crystal oscillator
• Multipurpose clock generator (MCG) with frequency-
locked loop and phase-locked loop referencing either
internal or external reference clock
• One eFlexPWM with 4 sub-modules, providing 12
PWM outputs
• Two 8-channel FlexTimers (FTM0 and FTM3)
• One 2-channel FlexTimers (FTM1)
• Four Periodic interrupt timers (PIT)
• Two Programmable Delay Blocks (PDB)
• Quadrature Encoder/Decoder (ENC)
• Ratio of timer input clock frequency vs. core
frequency is 1:2 when core frequency is 168 Mhz,
and 1:1 when core frequency is less than or equal to
100 Mhz
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Temperature range: –40 to 105 °C
Human-machine interface
• General-purpose input/output
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Kinetis Motor Suite
Security and integrity modules
• Hardware CRC module to support fast cyclic
redundancy checks
• Supports velocity and position control of BLDC and
PMSM motors
• Implements Field Orient Control (FOC) using Back
EMF to improve motor efficiency
• External Watchdog Monitor (EWM)
• Utilizes SpinTAC control theory that improves overall
system performance and reliability
NOTE
The 48-pin LQFP package for this product is not yet available. However, it is included
in a Package Your Way program for Kinetis MCUs. Visit nxp.com/KPYW for more
details.
Orderable part numbers summary1
NXP part
number
CPU Pin
Total SRA
ADC
eFlexPWM PW
M
Flex Timers
DA FlexCAN
coun flash
M
memo (KB)
ry
C
ADC ADC PW
PW
MX
FTM FTM FTM
CA CA
freq
t
Nan
o-
A
B
MA
0
3
1
N0 N1
uenc
y
(MHz
)
PW
MB
(KB)
Edg
e
MKV46F256VLL 168
16
100
64
256
256
128
128
256
256
128
128
128
64
32
32
24
24
32
32
24
24
24
16
16
32
32
24
18ch 20ch 1x8ch 1x4ch Yes 1x8ch 1x8ch 1x2ch
13ch 16ch 1x8ch Yes 1x8ch 1x8ch 1x2ch
18ch 20ch 1x8ch 1x4ch Yes 1x8ch 1x8ch 1x2ch
13ch 16ch 1x8ch Yes 1x8ch 1x8ch 1x2ch
18ch 20ch 1x8ch 1x4ch Yes
13ch 16ch 1x8ch Yes
18ch 20ch 1x8ch 1x4ch Yes
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
MKV46F256VLH 168
16
—
MKV46F128VLL 168
16
100
64
1
1
MKV46F128VLH 168
16
—
1
1
MKV44F256VLL 168
16
100
64
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
1
1
MKV44F256VLH 168
16
—
1
1
MKV44F128VLL 168
16
100
64
1
1
MKV44F128VLH 168
16
13ch 16ch 1x8ch
11ch 10ch 1x8ch
13ch 16ch 1x8ch
11ch 10ch 1x8ch
—
—
—
—
—
—
—
Yes
Yes
Yes
Yes
—
1
1
MKV44F128VLF 168
162
48
1
—
1
MKV44F64VLH1 168
6
64
1
MKV44F64VLF1 168
62
48
64
1
—
1
MKV42F256VLL 168
16
100
64
256
256
128
18ch 20ch
13ch 16ch
18ch 20ch
—
—
—
1x8ch 1x8ch 1x2ch
1x8ch 1x8ch 1x2ch
1x8ch 1x8ch 1x2ch
—
—
—
MKV42F256VLH 168
16
—
1
MKV42F128VLL 168
16
100
—
1
Table continues on the next page...
2
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
Orderable part numbers summary1 (continued)
NXP part
number
CPU Pin
Total SRA
ADC
eFlexPWM PW
M
Flex Timers
DA FlexCAN
coun flash
M
memo (KB)
ry
C
ADC ADC PW
PW
MX
FTM FTM FTM
CA CA
freq
t
Nan
o-
A
B
MA
0
3
1
N0 N1
uenc
y
(MHz
)
PW
MB
(KB)
Edg
e
MKV42F128VLH 168
16
64
48
64
48
128
128
64
24
24
16
16
13ch 16ch
11ch 10ch
13ch 16ch
11ch 10ch
—
—
—
—
—
—
—
—
—
—
—
—
1x8ch 1x8ch 1x2ch
1x8ch 1x8ch 1x2ch
1x8ch 1x8ch 1x2ch
1x8ch 1x8ch 1x2ch
—
—
—
—
1
1
1
1
1
—
1
MKV42F128VLF 168
162
MKV42F64VLH1 168
6
MKV42F64VLF1 168
62
64
—
1. To confirm current availability of ordererable part numbers, go to http://www.nxp.com and perform a part number
search.
2. Package Your Way.
Related Resources
Type
Selector
Description
Resource
Solution Advisor
The Solution Advisor is a web-based tool that features interactive
application wizards and a dynamic product selector.
Guide
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
KV4XP100M168RM1
KV4XP100M1681
Kinetis_V_1N72K1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
Chip Errata
The chip mask set Errata provides additional or corrective information
for a particular device mask set.
KMS User
Guide
The KMS User Guide provides a comprehensive description of the
features and functions of the Kinetis Motor Suite solution.
Kinetis Motor Suite User’s
Guide (KMS100UG)1
KMS API
Reference
Manual
The KMS API reference manual provides a comprehensive description Kinetis Motor Suite API
of the API of the Kinetis Motor Suite function blocks.
Reference Manual
(KMS100RM)1
Package
drawing
Package dimensions are provided in package drawings.
• LQFP 100-pin:
98ASS23308W1
• LQFP 64-pin:
98ASS23234W1
• LQFP 48-pin:
98ASH00962A1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
KV4x Data Sheet, Rev. 3, 06/2016
3
NXP Semiconductors
MCG
32 kHz
RC
8 MHz
RC
JTAG/SWD
ARM Cortex M4
32-bit CPU
16-ch
DMA
PLL
100-240 MHz
168 MHz
SPFPU
MCM
Osc
Low range: 32 kHz
High range: 4-20 MHz
Crossbar switch (AXBS-Lite)
GPIO
Up to 70
32
FMC
128
RCM
SIM
PMC
Peripheral bridge
P-Flash
Up to 256 KB
eFlexPWM
8ch + 4ch
12 bit ADC
(4.1 MSPS)
FlexTimer
8ch + 8ch +2ch
12 bit ADC
(4.1 MSPS)
XBARA
2 x PDB
4 x HSCMP
with 6bit DAC
1x 12 bit
DAC
XBARB
4 - ch PIT
nano-edge
WDOG
CRC
ENC
EWM
SRAM
I2C
SMBUS
FlexCAN
x2
LPTMR
AOI
Up to 32 KB
FlexSCI
SPI
IRQ
FlexSCI
Figure 1. KV4x block diagram
4
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
Table of Contents
1 Ratings..................................................................................6
3.6.2 CMP and 6-bit DAC electrical specifications....34
3.6.3 12-bit DAC electrical characteristics................ 36
3.7 Timers..........................................................................39
3.8 Enhanced NanoEdge PWM characteristics.................39
3.9 Communication interfaces........................................... 40
3.9.1 SPI (DSPI) switching specifications (limited
1.1 Thermal handling ratings............................................. 6
1.2 Moisture handling ratings.............................................6
1.3 ESD handling ratings...................................................6
1.4 Voltage and current operating ratings..........................6
1.5 Absolute Maximum Ratings.........................................7
2 General................................................................................. 8
2.1 AC electrical characteristics.........................................8
2.2 Nonswitching electrical specifications..........................9
2.2.1 Recommended Operating Conditions..............9
2.2.2 LVD and POR operating requirements............ 10
2.2.3 Voltage and current operating behaviors.........10
2.2.4 Power mode transition operating behaviors.... 11
2.2.5 Power consumption operating behaviors.........12
2.2.6 EMC radiated emissions operating behaviors. 17
2.2.7 Designing with radiated emissions in mind......18
2.2.8 Capacitance attributes..................................... 18
2.3 Switching specifications...............................................18
2.3.1 Typical device clock specifications.................. 18
2.3.2 General switching specifications......................19
2.4 Thermal specifications.................................................20
2.4.1 Thermal operating requirements......................20
2.4.2 Thermal attributes............................................20
3 Peripheral operating requirements and behaviors................ 21
3.1 Core modules.............................................................. 21
3.1.1 SWD Electricals .............................................. 21
3.1.2 Debug trace timing specifications.................... 22
3.1.3 JTAG electricals...............................................23
3.2 System modules.......................................................... 26
3.3 Clock modules............................................................. 26
3.3.1 MCG specifications..........................................26
3.3.2 Oscillator electrical specifications.................... 28
3.4 Memories and memory interfaces............................... 30
3.4.1 Flash electrical specifications.......................... 30
3.5 Security and integrity modules.....................................31
3.6 Analog..........................................................................32
3.6.1 12-bit cyclic Analog-to-Digital Converter
voltage range)..................................................40
3.9.2 SPI (DSPI) switching specifications (full
voltage range)..................................................44
3.9.3 I2C................................................................... 47
3.9.4 UART............................................................... 47
3.10 Kinetis Motor Suite (KMS)........................................... 47
4 Dimensions........................................................................... 48
4.1 Obtaining package dimensions....................................48
5 Pinout....................................................................................48
5.1 KV4x Signal Multiplexing and Pin Assignments.......... 48
5.2 Pinout diagrams...........................................................52
6 Ordering parts....................................................................... 55
6.1 Determining valid orderable parts................................55
7 Part identification...................................................................56
7.1 Description...................................................................56
7.2 Format......................................................................... 56
7.3 Fields........................................................................... 56
7.4 Example.......................................................................57
8 Terminology and guidelines.................................................. 57
8.1 Definition: Operating requirement................................57
8.2 Definition: Operating behavior..................................... 57
8.3 Definition: Attribute...................................................... 58
8.4 Definition: Rating......................................................... 58
8.5 Result of exceeding a rating........................................ 59
8.6 Relationship between ratings and operating
requirements................................................................59
8.7 Guidelines for ratings and operating requirements......59
8.8 Definition: Typical value...............................................60
8.9 Typical Value Conditions............................................. 61
9 Revision history.....................................................................61
(ADC) parameters............................................32
KV4x Data Sheet, Rev. 3, 06/2016
5
NXP Semiconductors
Ratings
1 Ratings
1.1 Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.2 Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
1.3 ESD handling ratings
Symbol
VHBM
Description
Min.
-2000
-500
Max.
+2000
+500
Unit
V
Notes
Electrostatic discharge voltage, human-body model
1
2
VCDM
Electrostatic discharge voltage, charged-device
model
V
ILAT
Latch-up current at ambient temperature of 105 °C
-100
+100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-up Test.
1.4 Voltage and current operating ratings
6
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
Ratings
Symbol
VDD
Description
Min.
–0.3
—
Max.
3.8
Unit
Digital supply voltage
V
mA
V
IDD
Digital supply current
120
VDD + 0.31
VIO
Digital pin input voltage (except open drain pins)
Open drain pins (PTC6 and PTC7)
–0.3
–0.3
–25
5.5
V
ID
Instantaneous maximum current single pin limit (applies to
all port pins)
25
mA
VDDA
Analog supply voltage
VDD – 0.3
VDD + 0.3
V
1. Maximum value of VIO (except open drain pins) must be 3.8 V.
1.5 Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the
maxima is not guaranteed. Stress beyond the limits specified in Table 1 may affect
device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
Table 1. Absolute Maximum Ratings (VSS = 0 V, VSSA = 0 V)
Symbol
VDD
Description
Supply Voltage Range
Notes1
Min
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.3
-0.4
-0.3
—
Max
4.0
Unit
V
VDDA
VREFHx
VREFLx
ΔVDD
ΔVSS
VIN
Analog Supply Voltage Range
4.0
V
ADC High Voltage Reference
4.0
V
ADC Low Voltage Reference
0.3
V
Voltage difference VDD to VDDA
Voltage difference VSS to VSSA
Digital Input Voltage Range
0.3
V
0.3
V
Pin Groups 1, 2
Pin Group 4
4.0
V
VOSC
VINA
Oscillator Input Voltage Range
Analog Input Voltage Range
4.0
V
Pin Group 3
4.0
V
IIC
Input clamp current, per pin (VIN < 0)
Output clamp current, per pin (VO < 0)2
Output Voltage Range (Normal Push-Pull mode)
Output Voltage Range (Open Drain mode)
DAC Output Voltage Range
-20.0
-20.0
4.0
mA
mA
V
IOC
—
VOUT
VOUTOD
VOUT_DAC
TA
Pin Group 1
Pin Group 2
Pin Group 5
-0.3
-0.3
-0.3
-40
5.5
V
4.0
V
Ambient Temperature Industrial
Storage Temperature Range (Extended Industrial)
105
150
°C
°C
TSTG
-55
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET, PORTC6, and PORTC7
• Pin Group 3: ADC and Comparator Analog Inputs
KV4x Data Sheet, Rev. 3, 06/2016
7
NXP Semiconductors
General
• Pin Group 4: XTAL, EXTAL
• Pin Group 5: DAC analog output
2. Continuous clamp current per pin is -2.0 mA
2 General
Electromagnetic compatibility (EMC) performance depends on the environment in
which the MCU resides. Board design and layout, circuit topology choices, location,
characteristics of external components, and MCU software operation play a significant
role in EMC performance.
See the following applications notes available on nxp.com for guidelines on optimizing
EMC performance.
• AN2321: Designing for Board Level Electromagnetic Compatibility
• AN1050: Designing for Electromagnetic Compatibility (EMC) with HCMOS
Microcontrollers
• AN1263: Designing for Electromagnetic Compatibility with Single-Chip
Microcontrollers
• AN2764: Improving the Transient Immunity Performance of Microcontroller-Based
Applications
• AN1259: System Design and Layout Techniques for Noise Reduction in MCU-
Based Systems
2.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 2. Input signal measurement reference
8
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
General
All digital I/O switching characteristics, unless otherwise specified, assume:
1. output pins
• have CL=30pF loads,
• are slew rate disabled, and
• are normal drive strength
2.2 Nonswitching electrical specifications
2.2.1 Recommended Operating Conditions
This section includes information about recommended operating conditions.
NOTE
Recommended VDD ramp rate is between 1 ms and 200 ms.
Table 2. Recommended Operating Conditions (VREFLx=0V, VSSA=0V, VSS=0V)
Symbol
VDD
Description
Notes1
Min
1.71
2.7
Typ
Max
3.6
Unit
V
Supply Voltage Digital
2, 3
VDDA
Supply voltage (analog)
2, 3
3.0
3.6
V
VREFHx
ΔVDD
ΔVSS
ADC (Cyclic) Reference Voltage High
Voltage difference VDD to VDDA
Voltage difference VSS to VSSA
Device Clock Frequency
2.7
VDDA
0.1
V
-0.1
-0.1
0
0
V
0.1
V
F_MCGO
UT
0.04
0
168
168
MHz
•
using internal RC oscillator
using external clock source
•
VIH
Input Voltage High (digital inputs)
Input Voltage Low (digital inputs)
Oscillator Input Voltage High
Pin Groups 1, 2 0.7 x VDD
Pin Groups 1, 2
3.6
V
V
V
VIL
0.35 x VDD
VDD + 0.3
VIHOSC
Pin Group 4
2.0
-0.3
-40
XTAL driven by an external clock source
Oscillator Input Voltage Low
VILOSC
Cout
TA
Pin Group 4
Pin Group 5
0.8
1
V
DAC Output Current Drive Strength
Ambient Operating Temperature
mA
°C
105
1. Default Mode
• Pin Group 1: GPIO, TDI, TDO, TMS, TCK
• Pin Group 2: RESET
• Pin Group 3: ADC and Comparator Analog Inputs
• Pin Group 4: XTAL, EXTAL
• Pin Group 5: DAC analog output
• Pin Group 6: PTB0, PTB1, PTD4, PTD5, PTD6, PTD7, PTC3, and PTC4. have high output current capability
• Pin Group 7: PTC6 and PTC7 are true open drain pins and have no P-chanl transistor. A external pull-up
resistor is required when these pins are outputs.
KV4x Data Sheet, Rev. 3, 06/2016
9
NXP Semiconductors
General
2. If the ADC is enabled, minimum VDD is 2.7 V and minimum VDDA is 2.7 V. ADCA and ADCB are not guaranteed to
operate below 2.7 V. All other analog modules besides the ADC and Nano-edge will operate down to 1.71 V.
3. If the Nano-edge is enabled, minimum VDD is 3.0 V and minimum VDDA is 3.0 V. Nano-edge is not guaranteed to operate
below 3.0 V. All other analog modules besides the ADC and Nano-edge will operate down to 1.71 V.
2.2.2 LVD and POR operating requirements
Table 3. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VLVDH
Falling low-voltage detect threshold — high
range (LVDV=01)
2.48
2.56
2.64
V
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV=00)
1
VLVW1H
VLVW2H
VLVW3H
VLVW4H
2.62
2.72
2.82
2.92
2.70
2.80
2.90
3.00
2.78
2.88
2.98
3.08
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
—
80
—
mV
V
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV=00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
1.80
1.90
2.00
2.10
1.86
1.96
2.06
2.16
V
V
V
V
• Level 2 falling (LVWV=01)
• Level 3 falling (LVWV=10)
• Level 4 falling (LVWV=11)
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
—
60
—
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low power oscillator period — factory
trimmed
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
2.2.3 Voltage and current operating behaviors
Table 4. Voltage and current operating behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
VOH
Output high voltage — normal drive pad
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
Table continues on the next page...
10
NXP Semiconductors
KV4x Data Sheet, Rev. 3, 06/2016
General
Notes
1
Table 4. Voltage and current operating behaviors (continued)
Symbol
Description
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -10mA
Min.
Typ.
Max.
Unit
• 1.71 V ≤VDD ≤ 2.7 V, IOH = -5mA
Output high voltage — High drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = -20mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = -10mA
VDD – 0.5
VDD – 0.5
—
—
—
—
V
V
IOHT
VOL
Output high current total for all ports
Output low voltage — open drain pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = 3 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = 1 mA
—
—
100
mA
2
—
—
—
—
0.5
0.5
V
V
VOL
Output low voltage — normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 10 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 5 mA
—
—
—
—
0.5
0.5
V
V
Output low voltage — high drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
1
3
—
—
—
—
0.5
0.5
V
V
IOLT
IIN
Output low current total for all ports
—
—
—
100
0.5
mA
µA
Input leakage current, analog and digital
0.002
pins
• VSS ≤ VIN ≤ VDD
RPU
RPD
Internal pullup resistors(except
RTC_WAKEUP pins)
20
20
—
—
50
50
kΩ
kΩ
4
5
Internal pulldown resistors
1. High drive pads are PTB0, PTB1, PTC3, PTC4, PTD4, PTD5, PTD6 and PTD7.
2. Open drain pads are PTC6 and PTC7.
3. Measured at VDD=3.6V
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
5. Measured at VDD supply voltage = VDD min and Vinput = VDD
2.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 100 MHz
• Bus and flash clock = 25 MHz
• FEI clock mode
KV4x Data Sheet, Rev. 3, 06/2016
11
NXP Semiconductors
General
Table 5. Power mode transition operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the
point VDD reaches 1.71 V to execution of the
first instruction across the operating temperature
range of the chip.
—
—
300
μs
• VLLS0 → RUN
• VLLS1 → RUN
• VLLS2 → RUN
• VLLS3 → RUN
• VLPS → RUN
• STOP → RUN
—
—
—
—
—
—
—
—
—
—
—
—
173
172
96
μs
μs
μs
μs
μs
μs
96
5.4
5.4
2.2.5 Power consumption operating behaviors
NOTE
The maximum values represent characterized results
equivalent to the mean plus three times the standard deviation
(mean+3σ)
Table 6. Power consumption operating behaviors (All IDDs are Target values)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash, excludes
IDDA
Core frequency
of 25 MHz.
• @ 1.8V
• @ 3.0V
—
—
6.8
6.9
17.2
17.4
mA
mA
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash, excludes
IDDA
Core frequency
of 50 MHz.
• @ 1.8V
• @ 3.0V
—
9.9
19.7
mA
Table continues on the next page...
12
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
General
Table 6. Power consumption operating behaviors (All IDDs are Target values) (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
—
10.0
19.8
mA
IDD_RUN Run mode current — all peripheral clocks
disabled, code executing from flash, excludes
IDDA
Core frequency
of 100 MHz.
—
—
17.0
17.2
25.9
26.1
mA
mA
• @ 1.8V
• @ 3.0V
IDD_HSRUN Run mode current — all peripheral clocks
disabled, code executing from flash, excludes
IDDA
Core frequency
of 168 MHz.
—
—
26.3
26.5
45.3
45.5
mA
mA
• @ 1.8V
• @ 3.0V
IDD_HSRUN Run mode current — all peripheral clocks
enabled, code executing from flash,excludes
IDDA
Core frequency
of 168 MHz.
Nanoedge
module at 84
MHz.
• @ 3.0V
• @ 25°C
• @ 105°C
—
—
34.0
39.0
45.5
53.2
mA
mA
IDD_WAIT Wait mode high frequency current at 3.0 V —
all peripheral clocks disabled
—
—
—
—
8.9
—
—
—
—
mA
mA
mA
mA
IDD_VLPR Very-low-power run mode current at 3.0 V —
all peripheral clocks disabled
0.58
0.83
0.34
Core frequency
of 4 Mhz.
IDD_VLPR Very-low-power run mode current at 3.0 V —
all peripheral clocks enabled
Core frequency
of 4 Mhz.
IDD_VLPW Very-low-power wait mode current at 3.0 V —
all peripheral clocks disabled
Bus frequency
of 2 MHz.
IDD_STOP Stop mode current at 3.0 V
• @ –40 to 25°C
—
—
—
0.43
1.16
3.05
2.03
4.27
mA
mA
mA
• @ 70°C
10.13
• @ 105°C
IDD_VLPS Very-low-power stop mode current at 3.0 V
—
—
—
58
218
1340
2870
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
280
924
• @ 105°C
IDD_VLLS3 Very low-leakage stop mode 3 current at 3.0 V
—
—
—
2.8
9.6
5.3
35.1
134.8
μA
μA
μA
• @ –40 to 25°C
• @ 70°C
37.4
• @ 105°C
IDD_VLLS2 Very low-leakage stop mode 2 current at 3.0 V
Table continues on the next page...
KV4x Data Sheet, Rev. 3, 06/2016
13
NXP Semiconductors
General
Table 6. Power consumption operating behaviors (All IDDs are Target values) (continued)
Symbol Description
• @ –40 to 25°C
Min.
Typ.
Max.
Unit
Notes
—
2.7
3.3
μA
• @ 70°C
—
—
6.6
12.2
50.5
μA
μA
• @ 105°C
25.9
IDD_VLLS1 Very low-leakage stop mode 1 current at 3.0 V
—
—
—
740
2.5
1200
10.6
26.5
nA
μA
μA
• @ –40 to 25°C
• @ 70°C
11.1
• @ 105°C
IDD_VLLS0B Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit enabled
• @ –40 to 25°C
• @ 70°C
—
—
—
420
1.9
832
9.4
nA
μA
μA
• @ 105°C
10.8
26.3
IDD_VLLS0A Very low-leakage stop mode 0 current at 3.0 V
with POR detect circuit disabled
• @ –40 to 25°C
• @ 70°C
—
—
—
200
1.8
599
10.5
26.3
nA
μA
μA
• @ 105°C
10.8
Table 7. Low power mode peripheral adders — typical value
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
IIREFSTEN4MHz 4 MHz internal reference clock (IRC) adder.
Measured by entering STOP or VLPS mode
with 4 MHz IRC enabled.
56
56
56
56
56
56
µA
µA
uA
IIREFSTEN32KHz 32 kHz internal reference clock (IRC) adder.
Measured by entering STOP mode with the
32 kHz IRC enabled.
52
52
52
52
52
52
IEREFSTEN4MHz External 4 MHz crystal clock adder.
Measured by entering STOP or VLPS mode
with the crystal enabled.
206
228
237
245
251
258
IEREFSTEN32KHz External 32 kHz crystal clock adder by
means of the OSC0_CR[EREFSTEN and
EREFSTEN] bits. Measured by entering all
modes with the crystal enabled.
nA
VLLS1
VLLS3
VLPS
440
440
510
490
490
560
540
540
560
560
560
560
570
570
610
580
580
680
STOP
Table continues on the next page...
14
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
General
Table 7. Low power mode peripheral adders — typical value (continued)
Symbol
Description
Temperature (°C)
Unit
-40
25
50
70
85
105
510
560
560
560
610
680
ICMP
CMP peripheral adder measured by placing
the device in VLLS1 mode with CMP
enabled using the 6-bit DAC and a single
external input for compare. Includes 6-bit
DAC power consumption.
22
22
22
22
22
22
µA
IUART
UART peripheral adder measured by placing
the device in STOP or VLPS mode with
selected clock source waiting for RX data at
115200 baud rate. Includes selected clock
source power consumption.
µA
µA
MCGIRCLK (4 MHz internal reference clock)
OSCERCLK (4 MHz external crystal)
66
214
45
66
234
45
66
246
45
66
254
45
66
260
45
66
268
45
IBG
Bandgap adder when BGEN bit is set and
device is placed in VLPx or VLLSx mode.
2.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
• MCG in FBE for run mode, and BLPE for VLPR mode
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
KV4x Data Sheet, Rev. 3, 06/2016
15
NXP Semiconductors
General
Figure 3. Run mode supply current vs. core frequency
16
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
General
VeryLow Power Run(VLPR) Current vsCore Frequency
Temp(C)=25,VDD=3.6V,CACHE=ENABLE,CodeResidence=Flash
1.00E-03
900.00E-06
800.00E-06
700.00E-06
600.00E-06
500.00E-06
400.00E-06
300.00E-06
200.00E-06
100.00E-06
000.00E+00
All Peripheral ClkGates
ALLOFF
ALLON
ClkRatio
Core-Bus-Flash
'1-1-2
'1-1-1
'1-2-4
'1-1-4
2
'1-1-2
'1-2-4
'1-1-4
CoreFreq(Mhz)
1
4
Figure 4. VLPR mode current vs. core frequency
2.2.6 EMC radiated emissions operating behaviors
NOTE
EMC measurements to IC-level IEC standards are available
from NXP on request.
Table 8. EMC radiated emissions operating behaviors
Symbol
Description
Frequency
band
Typ.
Unit
Notes
(MHz)
VRE1
VRE2
Radiated emissions voltage, band 1
Radiated emissions voltage, band 2
Radiated emissions voltage, band 3
Radiated emissions voltage, band 4
IEC level
0.15–50
50–150
20
18
14
8
dBμV
dBμV
dBμV
dBμV
—
1, 2
VRE3
150–500
500–1000
0.15–1000
VRE4
VRE_IEC
L
2, 3
KV4x Data Sheet, Rev. 3, 06/2016
17
NXP Semiconductors
General
1. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions, 150
kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits - Measurement
of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic application code.
The reported emission level is the value of the maximum measured emission, rounded up to the next whole number,
from among the measured orientations in each frequency range.
2. VDD = 3.3 V, TA = 25 °C, fOSC = 10 MHz (crystal), fSYS = 75 MHz, fBUS = 25 MHz
3. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and
Wideband TEM Cell Method
2.2.7 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com.
2. Perform a keyword search for “EMC design.”
2.2.8 Capacitance attributes
Table 9. Capacitance attributes
Symbol
CIN_A
Description
Min.
—
Max.
Unit
pF
Input capacitance: analog pins
Input capacitance: digital pins
7
7
CIN_D
—
pF
2.3 Switching specifications
2.3.1 Typical device clock specifications
Table 10. Typical device clock specifications
Symbol
Description
Min.
Max.
Unit
Notes
High Speed RUN mode
fSYS
fBUS
fFPCK
fNANO
System and core clock
Bus and Flash clock
Fast peripheral clock
Nano-edge clock
—
—
—
—
168
24
MHz
MHz
MHz
MHz
84
168
Normal run mode
fSYS
fBUS
System and core clock
Bus and Flash clock
—
—
100
25
MHz
MHz
Table continues on the next page...
18
NXP Semiconductors
KV4x Data Sheet, Rev. 3, 06/2016
General
Notes
Table 10. Typical device clock specifications (continued)
Symbol
fFPCK
Description
Min.
—
Max.
100
Unit
MHz
MHz
Fast peripheral clock
Nano-edge clock
fNANO
—
200
Low Speed RUN mode
fSYS
fBUS
fFPCK
fNANO
System and core clock
Bus and Flash clock
Fast peripheral clock
Nano-edge clock
—
—
—
—
50
25
MHz
MHz
MHz
MHz
100
200
NOTE
When NaneEdge circuit is enabled, the following clock set
must be followed:
1. NanoEdge clock source must be from the PLL output
2. NanoEdge clock must be 2x the fast peripheral clock
3. NanoEdge clock must in the range of 164 Mhz ~232
Mhz
2.3.2 General switching specifications
These general purpose specifications apply to all signals configured for GPIO, UART,
and I2C signals.
Table 11. General switching specifications
Symbol
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock
cycles
1
External RESET and NMI pin interrupt pulse width —
Asynchronous path
100
16
—
—
ns
2
GPIO pin interrupt pulse width — Asynchronous path
Port rise and fall time
Fast slew rate
ns
2
3
—
—
8
7
ns
ns
1.71≤ VDD ≤ 2.7 V
2.7 ≤ VDD ≤ 3.6 V
Port rise and fall time
Slow slew rate
—
—
25
15
ns
ns
1.71≤ VDD ≤ 2.7 V
2.7 ≤ VDD ≤ 3.6 V
KV4x Data Sheet, Rev. 3, 06/2016
19
NXP Semiconductors
General
1. The greater synchronous and asynchronous timing must be met.
2. This is the shortest pulse that is guaranteed to be recognized.
3. For high drive pins with high drive enabled, load is 75pF; other pins load (low drive) is 25pF.
2.4 Thermal specifications
2.4.1 Thermal operating requirements
Table 12. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Die junction temperature
Ambient temperature
TA
105
°C
2.4.2 Thermal attributes
Table 13. Thermal attributes
Board type
Single-layer (1S)
Four-layer (2s2p)
Single-layer (1S)
Four-layer (2s2p)
—
Symbol
RθJA
Description
100
LQFP
64 LQFP 48 LQFP
Unit
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Notes
Thermal resistance, junction to
ambient (natural convection)
62
49
52
43
35
17
3
64
46
52
39
28
15
2
71
47
58
41
24
18
2
1
RθJA
Thermal resistance, junction to
ambient (natural convection)
RθJMA Thermal resistance, junction to
ambient (200 ft./min. air speed)
RθJMA Thermal resistance, junction to
ambient (200 ft./min. air speed)
RθJB
RθJC
ΨJT
Thermal resistance, junction to
board
2
3
4
—
Thermal resistance, junction to
case
—
Thermal characterization
parameter, junction to package
top outside center (natural
convection)
1. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air), or EIA/JEDEC Standard JESD51-6, Integrated Circuit Thermal Test Method
Environmental Conditions—Forced Convection (Moving Air).
2. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental
Conditions—Junction-to-Board.
3. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate
temperature used for the case temperature. The value includes the thermal resistance of the interface material between
the top of the package and the cold plate.
20
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
4. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental
Conditions—Natural Convection (Still Air).
3 Peripheral operating requirements and behaviors
3.1 Core modules
3.1.1 SWD Electricals
Table 14. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
J1
SWD_CLK frequency of operation
• Serial wire debug
0
25
—
MHz
ns
J2
J3
SWD_CLK cycle period
SWD_CLK clock pulse width
• Serial wire debug
1/J1
20
—
ns
J4
J9
SWD_CLK rise and fall times
—
10
0
3
ns
ns
ns
ns
ns
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
—
32
—
J10
J11
J12
—
5
J2
J4
J3
J3
SWD_CLK (input)
J4
Figure 5. Serial wire clock input timing
KV4x Data Sheet, Rev. 3, 06/2016
21
NXP Semiconductors
Peripheral operating requirements and behaviors
SWD_CLK
SWD_DIO
J9
J10
Input data valid
J11
Output data valid
SWD_DIO
J12
SWD_DIO
J11
Output data valid
SWD_DIO
Figure 6. Serial wire data timing
3.1.2 Debug trace timing specifications
Table 15. Debug trace operating behaviors
Symbol
Tcyc
Twl
Description
Min.
Max.
Unit
MHz
ns
Clock period
Frequency dependent
Low pulse width
High pulse width
Clock and data rise time
Clock and data fall time
Data setup
2
2
—
—
3
Twh
Tr
ns
—
—
3
ns
Tf
3
ns
Ts
1.5
1.0
ns
Th
Data hold
2
ns
22
NXP Semiconductors
KV4x Data Sheet, Rev. 3, 06/2016
Peripheral operating requirements and behaviors
TRACECLK
T
r
T
f
T
T
wh
wl
T
cyc
Figure 7. TRACE_CLKOUT specifications
TRACE_CLKOUT
TRACE_D[3:0]
Ts
Th
Ts
Th
Figure 8. Trace data specifications
3.1.3 JTAG electricals
Table 16. JTAG limited voltage range electricals
Symbol
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
25
50
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
20
10
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
J4
J5
TCLK rise and fall times
—
20
2.0
—
—
8
3
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
—
—
28
25
—
—
J6
J7
J8
J9
J10
1
Table continues on the next page...
KV4x Data Sheet, Rev. 3, 06/2016
23
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 16. JTAG limited voltage range electricals (continued)
Symbol
J11
Description
Min.
—
Max.
19
Unit
ns
TCLK low to TDO data valid
TCLK low to TDO high-Z
TRST assert time
J12
—
17
ns
J13
100
8
—
ns
J14
TRST setup time (negation) to TCLK high
—
ns
Table 17. JTAG full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
J1
TCLK frequency of operation
• Boundary Scan
MHz
0
0
0
10
20
40
• JTAG and CJTAG
• Serial Wire Debug
J2
J3
TCLK cycle period
TCLK clock pulse width
• Boundary Scan
1/J1
—
ns
50
25
—
—
—
ns
ns
ns
• JTAG and CJTAG
• Serial Wire Debug
12.5
J4
J5
TCLK rise and fall times
—
20
2.0
—
—
8
3
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Boundary scan input data setup time to TCLK rise
Boundary scan input data hold time after TCLK rise
TCLK low to boundary scan output data valid
TCLK low to boundary scan output high-Z
TMS, TDI input data setup time to TCLK rise
TMS, TDI input data hold time after TCLK rise
TCLK low to TDO data valid
J6
—
J7
30.6
25
J8
J9
—
J10
J11
J12
J13
J14
1.0
—
—
100
8
—
19.0
17.0
—
TCLK low to TDO high-Z
TRST assert time
TRST setup time (negation) to TCLK high
—
J2
J4
J3
J3
TCLK (input)
J4
Figure 9. Test clock input timing
24
NXP Semiconductors
KV4x Data Sheet, Rev. 3, 06/2016
Peripheral operating requirements and behaviors
TCLK
J5
J6
Input data valid
Data inputs
Data outputs
Data outputs
Data outputs
J7
Output data valid
J8
J7
Output data valid
Figure 10. Boundary scan (JTAG) timing
TCLK
TDI/TMS
TDO
J9
J10
Input data valid
J11
Output data valid
J12
J11
TDO
Output data valid
TDO
Figure 11. Test Access Port timing
KV4x Data Sheet, Rev. 3, 06/2016
25
NXP Semiconductors
Peripheral operating requirements and behaviors
TCLK
J14
J13
TRST
Figure 12. TRST timing
3.2 System modules
There are no specifications necessary for the device's system modules.
3.3 Clock modules
3.3.1 MCG specifications
Table 18. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
—
39.0625
0.6
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM and SCFTRIM
0.3
%fdco
1
1
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using SCTRIM only
—
0.2
0.5
0.5
%fdco
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
2
1
%fdco
%fdco
1
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70°C
fintf_ft
fintf_t
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25°C
—
3
4
—
5
MHz
MHz
kHz
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
—
—
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
Table continues on the next page...
26
NXP Semiconductors
KV4x Data Sheet, Rev. 3, 06/2016
Peripheral operating requirements and behaviors
Table 18. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
—
—
kHz
FLL
ffll_ref
fdco
FLL reference frequency range
31.25
20
—
39.0625
25
kHz
DCO output
Low range (DRS=00)
20.97
MHz
2, 3
frequency range
640 × ffll_ref
Mid range (DRS=01)
1280 × ffll_ref
40
60
80
—
—
—
—
41.94
62.91
83.89
23.99
47.97
71.99
95.98
50
75
100
—
MHz
MHz
MHz
MHz
MHz
MHz
MHz
ps
Mid-high range (DRS=10)
1920 × ffll_ref
High range (DRS=11)
2560 × ffll_ref
fdco_t_DMX3 DCO output
Low range (DRS=00)
732 × ffll_ref
4, 5
frequency
2
Mid range (DRS=01)
1464 × ffll_ref
—
Mid-high range (DRS=10)
2197 × ffll_ref
—
High range (DRS=11)
2929 × ffll_ref
—
Jcyc_fll
FLL period jitter
—
—
180
150
—
—
• fDCO = 48 MHz
• fDCO = 98 MHz
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
6
PLL
fpll_ref
fvcoclk_2x VCO output frequency
fvcoclk PLL output frequency
fvcoclk_90 PLL quadrature output frequency
PLL reference frequency range
8
—
—
—
—
16
MHz
MHz
MHz
MHz
220
110
110
480
240
240
Ipll
PLL operating current
7
7
8
—
2.8
—
mA
• VCO @ 176 MHz (fosc_hi_1 = 32 MHz,
fpll_ref = 8 MHz, VDIV multiplier = 22)
Ipll
PLL operating current
—
4.7
—
mA
• VCO @ 360 MHz (fosc_hi_1 = 32 MHz,
fpll_ref = 8 MHz, VDIV multiplier = 45)
Jcyc_pll
PLL period jitter (RMS)
• fvco = 48 MHz
—
—
120
75
—
—
ps
ps
• fvco = 120 MHz
Jacc_pll
PLL accumulated jitter over 1µs (RMS)
8
Table continues on the next page...
KV4x Data Sheet, Rev. 3, 06/2016
27
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 18. MCG specifications (continued)
Symbol Description
• fvco = 48 MHz
Min.
Typ.
Max.
Unit
Notes
—
1350
—
ps
• fvco = 120 MHz
—
600
—
ps
Dunl
Lock exit frequency tolerance
Lock detector detection time
4.47
—
—
—
5.97
150 × 10-6
+ 1075(1/
%
s
tpll_lock
9
fpll_ref
)
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.
3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature should be considered.
4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.
5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
6. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
7. Excludes any oscillator currents that are also consuming power while PLL is in operation.
8. This specification was obtained using a NXP developed PCB. PLL jitter is dependent on the noise characteristics of
each PCB and results will vary.
9. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
3.3.2 Oscillator electrical specifications
3.3.2.1 Oscillator DC electrical specifications
Table 19. Oscillator DC electrical specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
VDD
Supply voltage
1.71
—
3.6
V
IDDOSC
Supply current — low-power mode (HGO=0)
1
• 32 kHz
• 4 MHz
• 8 MHz
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
—
—
—
500
200
300
950
1.2
—
—
—
—
—
—
nA
μA
μA
μA
mA
mA
1.5
IDDOSC
Supply current — high gain mode (HGO=1)
• 4 MHz
1
—
400
—
μA
Table continues on the next page...
28
NXP Semiconductors
KV4x Data Sheet, Rev. 3, 06/2016
Peripheral operating requirements and behaviors
Table 19. Oscillator DC electrical specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
• 8 MHz
—
500
—
μA
• 16 MHz
• 24 MHz
• 32 MHz
—
—
—
2.5
3
—
—
—
mA
mA
mA
4
Cx
Cy
RF
EXTAL load capacitance
—
—
—
—
—
—
—
—
—
2, 3
2, 3
2, 4
XTAL load capacitance
Feedback resistor — low-frequency, low-power
mode (HGO=0)
MΩ
MΩ
MΩ
MΩ
kΩ
Feedback resistor — low-frequency, high-gain
mode (HGO=1)
—
—
—
—
—
—
10
—
—
—
—
—
—
—
Feedback resistor — high-frequency, low-power
mode (HGO=0)
Feedback resistor — high-frequency, high-gain
mode (HGO=1)
1
RS
Series resistor — low-frequency, low-power
mode (HGO=0)
—
Series resistor — low-frequency, high-gain
mode (HGO=1)
200
—
kΩ
Series resistor — high-frequency, low-power
mode (HGO=0)
kΩ
Series resistor — high-frequency, high-gain
mode (HGO=1)
—
—
0
—
—
kΩ
V
5
Vpp
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, low-power mode
(HGO=0)
0.6
Peak-to-peak amplitude of oscillation (oscillator
mode) — low-frequency, high-gain mode
(HGO=1)
—
—
—
VDD
0.6
—
—
—
V
V
V
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, low-power mode
(HGO=0)
Peak-to-peak amplitude of oscillation (oscillator
mode) — high-frequency, high-gain mode
(HGO=1)
VDD
1. VDD=3.3 V, Temperature =25 °C
2. See crystal or resonator manufacturer's recommendation
3. Cx,Cy can be provided by using the integrated capacitors when the low frequency oscillator (RANGE = 00) is used. For
all other cases external capacitors must be used.
4. When low power mode is selected, RF is integrated and must not be attached externally.
5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to
any other devices.
KV4x Data Sheet, Rev. 3, 06/2016
29
NXP Semiconductors
Peripheral operating requirements and behaviors
3.3.2.2 Oscillator frequency specifications
Table 20. Oscillator frequency specifications
Symbol Description
fosc_lo Oscillator crystal or resonator frequency — low-
frequency mode (MCG_C2[RANGE]=00)
Min.
Typ.
Max.
Unit
Notes
32
—
40
kHz
fec_extal Input clock frequency (external clock mode)
tdc_extal Input clock duty cycle (external clock mode)
—
40
—
—
50
48
60
—
MHz
%
1, 2
3, 4
tcst
Crystal startup time — 32 kHz low-frequency,
low-power mode (HGO=0)
1000
ms
1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.
2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by
FRDIV, it remains within the limits of the DCO input clock frequency.
3. Proper PC board layout procedures must be followed to achieve specifications.
4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S
register being set.
NOTE
The 32 kHz oscillator works in low power mode by default
and cannot be moved into high power/gain mode.
3.4 Memories and memory interfaces
3.4.1 Flash electrical specifications
This section describes the electrical characteristics of the flash memory module.
3.4.1.1 Flash timing specifications — program and erase
The following specifications represent the amount of time the internal charge pumps are
active and do not include command overhead.
Table 21. NVM program/erase timing specifications
Symbol Description
Min.
—
Typ.
7.5
Max.
18
Unit
μs
Notes
thvpgm4
Longword Program high-voltage time
—
1
thversscr Sector Erase high-voltage time
—
13
113
1808
ms
ms
thversall
Erase All high-voltage time
—
208
1
1. Maximum time based on expectations at cycling end-of-life.
30
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
3.4.1.2 Flash timing specifications — commands
Table 22. Flash command timing specifications
Symbol Description
Min.
—
—
—
—
—
—
—
—
—
—
Typ.
—
Max.
60
Unit
μs
Notes
trd1sec4k Read 1s Section execution time (flash sector)
tpgmchk Program Check execution time
1
1
—
45
μs
trdrsrc
tpgm4
tersscr
trd1all
trdonce
Read Resource execution time
Program Longword execution time
Erase Flash Sector execution time
Read 1s All Blocks execution time
Read Once execution time
—
30
μs
1
65
14
—
145
114
0.9
25
μs
—
2
ms
ms
μs
1
—
1
tpgmonce Program Once execution time
65
280
—
—
μs
—
2
tersall
Erase All Blocks execution time
2100
30
ms
μs
tvfykey
Verify Backdoor Access Key execution time
1
1. Assumes 25 MHz flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
3.4.1.3 Flash high voltage current behaviors
Table 23. Flash high voltage current behaviors
Symbol
Description
Min.
Typ.
Max.
Unit
IDD_PGM
Average current adder during high voltage
flash programming operation
—
2.5
6.0
mA
IDD_ERS
Average current adder during high voltage
flash erase operation
—
1.5
4.0
mA
3.4.1.4 Reliability specifications
Table 24. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
—
—
2
20
100
50 K
10 K
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ Tj ≤ 125 °C.
KV4x Data Sheet, Rev. 3, 06/2016
31
NXP Semiconductors
Peripheral operating requirements and behaviors
3.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
3.6 Analog
3.6.1 12-bit cyclic Analog-to-Digital Converter (ADC) parameters
NOTE
The maximum values represent characterized results
equivalent to the mean plus three times the standard deviation
(mean+3σ).
Table 25. 12-bit ADC electrical specifications
Characteristic
Symbol
Min
Typ
Max
Unit
Recommended Operating Conditions
Supply Voltage1
Vrefh Supply Voltage, 2
VDDA
Vrefhx
fADCCLK
RAD
2.7
2.7
3.3
3.6
VDDA
25
V
V
ADC Conversion Clock3
0.6
MHz
V
Conversion Range
VREFL
VREFH
Input Voltage Range
VADIN
V
VREFL
VSSA
VREFH
VDDA
External Reference
Internal Reference
Timing and Power
Conversion Time
tADC
tADPU
IADRUN
6
ADC Clock Cycles
ADC Clock Cycles
mA
ADC Power-Up Time (from adc_pdn)
ADC RUN Current (per ADC block)
• at 600 kHz ADC Clock, LP mode
• ≤ 8.33 MHz ADC Clock, 00 mode
• ≤ 12.5 MHz ADC Clock, 01 mode
• ≤ 16.67 MHz ADC Clock, 10 mode
• ≤ 20 MHz ADC Clock, 11 mode
• ≤ 25 MHz ADC Clock
13
1
5.7
10.5
17.7
22.6
27.5
ADC Powerdown Current (adc_pdn enabled)
VREFH Current
IADPWRDWN
IVREFH
0.02
µA
µA
0.001
Accuracy (DC or Absolute)
Integral non-Linearity4
Differential non-Linearity4
INL
+/- 3
+/- 5
LSB5
LSB5
DNL
+/- 0.6
+/- 0.9
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32
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 25. 12-bit ADC electrical specifications (continued)
Characteristic
Monotonicity
Offset6
Symbol
Min
Typ
Max
Unit
VOFFSET
LSB4
+/- 25
+/- 20
• 1x gain mode
• 2x gain mode
• 4x gain mode
+50, -10
Gain Error
EGAIN
0.0002
—
%
AC Specifications7
Signal to Noise Ratio
Total Harmonic Distortion
Spurious Free Dynamic Range
Signal to Noise plus Distortion
Effective Number of Bits
ADC Inputs
SNR
THD
59
64
65
59
9.1
dB
dB
dB
dB
bits
SFDR
SINAD
ENOB
Input Leakage Current
Input Injection Current 8
Input Capacitance
IIN
IINJ
0
+/-2
+/-3
µA
mA
pF
CADI
4.8
Sampling Capacitor
1. If the ADC’s reference is from VDDA: When VDDA is below 2.7 V, then the ADC functions, but the ADC specifications
are not guaranteed.
2. When the input is at the Vrefl level, then the resulting output will be all zeros (hex 000), plus any error contribution due
to offset and gain error. When the input is at the Vrefh level, then the output will be all ones (hex FFF), minus any error
contribution due to offset and gain error.
3. ADC clock duty cycle min/max is 45/55% .
4. DNL and INL conversion accuracy is not guaranteed from VREFL to VREFL + 0025 and VREFH to VREFH-0025.
5. LSB = Least Significant Bit = 0.806 mV at 3.3 V VDDA, x1 Gain Setting
6. Offset over the conversion range of 0025 to 4070, with internal/external reference.
7. Measured when converting a 1 kHz input Full Scale sine wave.
8. The current that can be injected into or sourced from an unselected ADC input, without affecting the performance of
the ADC.
3.6.1.1 Equivalent circuit for ADC inputs
The following figure shows the ADC input circuit during sample and hold. S1 and S2
are always opened/closed at non-overlapping phases, and both S1 and S2 operate at
the ADC clock frequency. The following equation gives equivalent input impedance
when the input is selected.
1
100ohm+ 125ohm
+
-12
(ADC ClockRate) x 1.4x10
KV4x Data Sheet, Rev. 3, 06/2016
33
NXP Semiconductors
Peripheral operating requirements and behaviors
C1: Single Ended Mode
2XC1: Differential Mode
Channel Mux
equivalent resistance
100Ohms
S1
125 ESD
Resistor
Analog Input
C1
C1
S1
S1
S/H
1
2
S1
S2
S2
(VREFHx - VREFLx ) / 2
C1: Single Ended Mode
2XC1: Differential Mode
1. Parasitic capacitance due to package, pin-to-pin and pin-to-package base coupling =
1.8pF
2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal
routing = 2.04pF
3. Sampling capacitor at the sample and hold circuit. Capacitor C1 (4.8pF) is normally
disconnected from the input, and is only connected to the input at sampling time.
4. S1 and S2 switch phases are non-overlapping and operate at the ADC clock
frequency
S1
S2
Figure 13. Equivalent circuit for A/D loading
3.6.2 CMP and 6-bit DAC electrical specifications
Table 26. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
Supply current, high-speed mode (EN = 1, PMODE =
1)
—
200
μA
IDDLS
Supply current, low-speed mode (EN = 1, PMODE =
0)
—
—
20
μA
VAIN
VAIO
VH
Analog input voltage
VSS
—
—
—
VDD
20
V
Analog input offset voltage
Analog comparator hysteresis1
mV
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34
NXP Semiconductors
KV4x Data Sheet, Rev. 3, 06/2016
Peripheral operating requirements and behaviors
Table 26. Comparator and 6-bit DAC electrical specifications (continued)
Symbol
Description
• CR0[HYSTCTR] = 00
Min.
Typ.
Max.
Unit
—
5
—
mV
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
—
—
—
10
20
30
—
—
—
mV
mV
mV
VCMPOh
VCMPOl
tDHS
Output high
VDD – 0.5
—
—
50
—
0.5
200
V
V
Output low
—
Propagation delay, high-speed mode (EN = 1,
PMODE = 1)
20
ns
tDLS
Propagation delay, low-speed mode (EN = 1, PMODE
= 0)
80
250
600
ns
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
—
—
—
7
40
—
μs
μA
LSB3
IDAC6b
INL
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
LSB
1. Typical hysteresis is measured with input voltage range limited to 0.7 to VDD – 0.7 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (writes to
DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
CMP Hysteresis vs Vinn
90.00E-03
80.00E-03
70.00E-03
60.00E-03
HYSTCTR
50.00E-03
40.00E-03
30.00E-03
20.00E-03
10.00E-03
000.00E+00
Setting
0
1
2
3
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinn (V)
Figure 14. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
KV4x Data Sheet, Rev. 3, 06/2016
35
NXP Semiconductors
Peripheral operating requirements and behaviors
CMP Hysteresis vs Vinn
180.00E-03
160.00E-03
140.00E-03
120.00E-03
100.00E-03
80.00E-03
60.00E-03
40.00E-03
20.00E-03
000.00E+00
-20.00E-03
HYSTCTR
Setting
0
1
2
3
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vinn (V)
Figure 15. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
3.6.3 12-bit DAC electrical characteristics
3.6.3.1 12-bit DAC operating requirements
Table 27. 12-bit DAC operating requirements
Symbol
VDDA
VDACR
CL
Desciption
Min.
1.71
1.13
—
Max.
3.6
3.6
100
1
Unit
V
Notes
Supply voltage
Reference voltage
Output load capacitance
Output load current
V
1
2
pF
mA
IL
—
1. The DAC reference can be selected to be VDDA or VREFH
.
2. A small load capacitance (47 pF) can improve the bandwidth performance of the DAC.
3.6.3.2 12-bit DAC operating behaviors
Table 28. 12-bit DAC operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
IDDA_DACL Supply current — low-power mode
—
—
330
μA
μA
μs
P
IDDA_DACH Supply current — high-speed mode
—
—
—
1200
200
P
tDACLP Full-scale settling time (0x080 to 0xF7F) —
low-power mode
100
1
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36
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 28. 12-bit DAC operating behaviors (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tDACHP Full-scale settling time (0x080 to 0xF7F) —
high-power mode
—
15
30
μs
1
tCCDACLP Code-to-code settling time (0xBF8 to
0xC08)
—
μs
1
1
5
• High-speed mode
• Low speed mode
Vdacoutl DAC output voltage range low — high-
speed mode, no load, DAC set to 0x000
—
—
—
—
—
—
100
mV
mV
Vdacouth DAC output voltage range high — high-
speed mode, no load, DAC set to 0xFFF
VDACR
−100
VDACR
INL
DNL
DNL
Integral non-linearity error — high speed
mode
—
—
—
8
1
1
LSB
LSB
LSB
2
3
4
Differential non-linearity error — VDACR > 2
V
Differential non-linearity error — VDACR
VREF_OUT
=
VOFFSET Offset error
EG Gain error
PSRR Power supply rejection ratio, VDDA ≥ 2.4 V
—
—
60
—
—
—
0.4
0.1
0.8
0.6
90
%FSR
%FSR
dB
5
5
—
TCO
TGE
Rop
SR
Temperature coefficient offset voltage
Temperature coefficient gain error
Output resistance (load = 3 kΩ)
Slew rate -80h→ F7Fh→ 80h
3.7
—
μV/C
%FSR/C
Ω
6
0.000421
—
—
250
V/μs
• High power (SPHP
)
1.2
1.7
—
—
• Low power (SPLP
3dB bandwidth
)
0.05
0.12
BW
kHz
• High power (SPHP
• Low power (SPLP
)
550
40
—
—
—
—
)
1. Settling within 1 LSB
2. The INL is measured for 0 + 100 mV to VDACR −100 mV
3. The DNL is measured for 0 + 100 mV to VDACR −100 mV
4. The DNL is measured for 0 + 100 mV to VDACR −100 mV with VDDA > 2.4 V
5. Calculated by a best fit curve from VSS + 100 mV to VDACR − 100 mV
6. VDDA = 3.0 V, reference select set for VDDA (DACx_CO:DACRFS = 1), high power mode (DACx_C0:LPEN = 0), DAC
set to 0x800, temperature range is across the full range of the device
KV4x Data Sheet, Rev. 3, 06/2016
37
NXP Semiconductors
Peripheral operating requirements and behaviors
8
6
4
2
0
-2
-4
-6
-8
0
500
1000
1500
2000
2500
3000
3500
4000
Digital Code
Figure 16. Typical INL error vs. digital code
38
NXP Semiconductors
KV4x Data Sheet, Rev. 3, 06/2016
Peripheral operating requirements and behaviors
1.499
1.4985
1.498
1.4975
1.497
1.4965
1.496
55
85
25
105
125
-40
Temperature °C
Figure 17. Offset at half scale vs. temperature
3.7 Timers
See General switching specifications.
3.8 Enhanced NanoEdge PWM characteristics
Table 29. NanoEdge PWM timing parameters - 100 Mhz operating frequency
Characteristic
Symbol
Min.
Typ.
100
312
Max.
Unit
MHz
ps
PWM clock frequency
NanoEdge Placement (NEP) Step Size1, 2
KV4x Data Sheet, Rev. 3, 06/2016
pwmp
Table continues on the next page...
39
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 29. NanoEdge PWM timing parameters - 100 Mhz operating frequency (continued)
Characteristic
Symbol
Min.
Typ.
Max.
Unit
Delay for fault input activating to PWM output
deactivated
1
ns
Power-up Time3
tpu
25
μs
1. Reference 100 MHz in NanoEdge Placement mode.
2. Temperature and voltage variations do not affect NanoEdge Placement step size.
3. Powerdown to NanoEdge mode transition.
Table 30. NanoEdge PWM timing parameters - 84 Mhz operating frequency
Characteristic
Symbol
pwmp
tpu
Min.
Typ.
84
Max.
Unit
MHz
ps
PWM clock frequency
NanoEdge Placement (NEP) Step Size1, 2
Delay for fault input activating to PWM output deactivated
Power-up Time3
372
1
ns
30
μs
1. Reference 84 MHz in NanoEdge Placement mode.
2. Temperature and voltage variations do not affect NanoEdge Placement step size.
3. Powerdown to NanoEdge mode transition.
3.9 Communication interfaces
3.9.1 SPI (DSPI) switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. Refer to
the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
NOTE
Fast pads:
• SIN: PTE19
• SOUT: PTE18
• SCK: PTE17
• PCS: PTE16
Open drain pads:
40
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
• SIN: PTC7
• SOUT: PTC6
Table 31. Master mode DSPI timing for normal pads (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
25
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn to DSPI_SCK output valid
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
(tBUS x 2) −
2
—
ns
1
2
DS4
DSPI_SCK to DSPI_PCSn output hold
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
−2
17
0
8.5
—
—
—
ns
ns
ns
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Table 32. Master mode DSPI timing for fast pads (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
Unit
V
Notes
Operating voltage
Frequency of operation
—
37.5
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn to DSPI_SCK output valid
2 x tBUS
(tSCK/2) − 2 (tSCK/2) + 2
ns
(tBUS x 2) −
2
—
ns
1
2
DS4
DSPI_SCK to DSPI_PCSn output hold
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
−2
13
0
8.5
—
—
—
ns
ns
ns
ns
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Table 33. Master mode DSPI timing for open drain pads (limited voltage range)
Num
Description
Min.
Max.
Unit
Notes
Operating voltage
2.7
3.6
V
Table continues on the next page...
KV4x Data Sheet, Rev. 3, 06/2016
41
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 33. Master mode DSPI timing for open drain pads (limited voltage range) (continued)
Num
Description
Frequency of operation
Min.
—
Max.
25
Unit
MHz
ns
Notes
DS1
DS2
DS3
DSPI_SCK output cycle time
2 x tBUS
—
DSPI_SCK output high/low time
DSPI_PCSn to DSPI_SCK output valid
(tSCK/2) − 2 (tSCK/2) + 2
ns
(tBUS x 2) −
2
—
ns
1
2
DS4
DSPI_SCK to DSPI_PCSn output hold
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
−3
17
0
15.5
—
ns
ns
ns
ns
—
—
1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 18. DSPI classic SPI timing — master mode
Table 34. Slave mode DSPI timing for normal pads (limited voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
Frequency of operation
12.5
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
21
—
—
—
15
15
ns
ns
2
ns
7
ns
—
—
ns
ns
42
NXP Semiconductors
KV4x Data Sheet, Rev. 3, 06/2016
Peripheral operating requirements and behaviors
Table 35. Slave mode DSPI timing for fast pads (limited voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
Frequency of operation
25
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
17
—
—
—
11
11
ns
ns
2
ns
7
ns
—
—
ns
ns
Table 36. Slave mode DSPI timing for open drain pads (limited voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
2.7
3.6
Frequency of operation
12.5
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
28
—
—
—
22
22
ns
ns
2
ns
7
ns
—
—
ns
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 19. DSPI classic SPI timing — slave mode
KV4x Data Sheet, Rev. 3, 06/2016
43
NXP Semiconductors
Peripheral operating requirements and behaviors
3.9.2 SPI (DSPI) switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provides DSPI timing characteristics for classic SPI timing modes. Refer
to the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
NOTE
Fast pads:
• SIN: PTE19
• SOUT: PTE18
• SCK: PTE17
• PCS: PTE16
Open drain pads:
• SIN: PTC7
• SOUT: PTC6
Table 37. Master mode DSPI timing for normal pads (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
18.75
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
4 x tBUS
(tSCK/2) - 4 (tSCK/2) + 4
ns
(tBUS x 2) −
4
—
ns
2
3
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-7.8
24
0
10
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
44
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
Peripheral operating requirements and behaviors
Table 38. Master mode DSPI timing fast pads (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
25
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
4 x tBUS
—
(tSCK/2) - 4 (tSCK/2) + 4
ns
(tBUS x 2) −
4
—
ns
2
3
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-7.8
17
0
10
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
Table 39. Master mode DSPI timing open drain pads (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
18.75
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
4 x tBUS
(tSCK/2) - 4 (tSCK/2) + 4
ns
(tBUS x 2) −
4
—
ns
2
3
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
-7.8
24
0
26
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
KV4x Data Sheet, Rev. 3, 06/2016
45
NXP Semiconductors
Peripheral operating requirements and behaviors
DSPI_PCSn
DS1
DS3
DS2
DS4
DSPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
DSPI_SIN
DS5
DS6
First data
Data
Last data
DSPI_SOUT
Figure 20. DSPI classic SPI timing — master mode
Table 40. Slave mode DSPI timing for normal pads (full voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
Frequency of operation
—
12.5
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
27.5
—
ns
ns
2.5
7
—
ns
—
ns
—
—
22
22
ns
ns
Table 41. Slave mode DSPI timing for fast pads (full voltage range)
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
1.71
Frequency of operation
—
18.75
—
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBUS
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
20.5
—
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
ns
ns
2.5
7
—
ns
—
ns
—
—
15
ns
15
ns
46
NXP Semiconductors
KV4x Data Sheet, Rev. 3, 06/2016
Peripheral operating requirements and behaviors
Table 42. Slave mode DSPI timing for open drain pads (full voltage range)
Num
Description
Min.
Max.
3.6
Unit
V
Operating voltage
1.71
Frequency of operation
—
9.375
—
MHz
ns
DS9
DSPI_SCK input cycle time
8 x tBUS
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) - 4
(tSCK/2) + 4
43.5
—
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
ns
ns
2.5
7
—
ns
—
ns
—
—
38
ns
38
ns
DSPI_SS
DS10
DS9
DSPI_SCK
(CPOL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
DSPI_SOUT
Data
Data
DS13
First data
Last data
DSPI_SIN
Figure 21. DSPI classic SPI timing — slave mode
3.9.3 I2C
See General switching specifications.
3.9.4 UART
See General switching specifications.
3.10 Kinetis Motor Suite (KMS)
KV4x Data Sheet, Rev. 3, 06/2016
47
NXP Semiconductors
Dimensions
Kinetis Motor Suite is a bundled software solution that enables the rapid configuration
of motor drive systems, and accelerates development of the final motor drive
application.
Several members of the KV4x family are enabled with Kinetis Motor Suite. The
enabled devices can be identified within the orderable part numbers in KMS Orderable
part numbers summary . For more information,see Kinetis Motor Suite User's Guide
(KMS100UG) and Kinetis Motor Suite API Reference Manual (KMS100RM).
NOTE
To find the associated resource, go to http://www.nxp.com
and perform a search using the Document ID.
4 Dimensions
4.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to www.nxp.com and perform a keyword search for the
drawing’s document number:
If you want the drawing for this package
48-pin LQFP
Then use this document number
98ASH00962A
64-pin LQFP
100-pin LQFP
98ASS23234W
98ASS23308W
5 Pinout
5.1 KV4x Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
48
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
Pinout
100
64
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP LQFP
1
2
3
4
5
1
—
—
—
—
—
PTE0/
CLKOUT32K
ADCB_CH6f
ADCB_CH7f
ADCB_CH6g
ADCB_CH7g
DISABLED
ADCB_CH6f
ADCB_CH7f
ADCB_CH6g
ADCB_CH7g
PTE0/
CLKOUT32K
UART1_TX
UART1_RX
XBAR0_
OUT10
XBAR0_IN11
XBAR0_IN7
2
PTE1/
LLWU_P0
PTE1/
LLWU_P0
XBAR0_
OUT11
—
—
—
PTE2/
LLWU_P1
PTE2/
LLWU_P1
UART1_
CTS_b
PTE3
PTE3
UART1_
RTS_b
PTE4/
PTE4/
LLWU_P2
LLWU_P2
6
7
—
—
—
—
PTE5
DISABLED
DISABLED
PTE5
FTM3_CH0
FTM3_CH1
PTE6/
PTE6/
LLWU_P16
LLWU_P16
8
9
3
4
5
6
1
2
3
4
VDD
VDD
VDD
VSS
VSS
VSS
10
11
PTE16
ADCA_CH0
ADCA_CH1
ADCA_CH0
ADCA_CH1
PTE16
SPI0_PCS0
SPI0_SCK
UART1_TX
UART1_RX
FTM_CLKIN0
FTM_CLKIN1
FTM0_FLT3
PTE17/
PTE17/
LLWU_P19
LPTMR0_
ALT3
LLWU_P19
12
13
7
8
5
6
PTE18/
LLWU_P20
ADCB_CH0
ADCB_CH1
ADCB_CH0
ADCB_CH1
PTE18/
LLWU_P20
SPI0_SOUT
SPI0_SIN
UART1_
CTS_b
I2C0_SDA
I2C0_SCL
PTE19
PTE19
UART1_
RTS_b
CMP3_OUT
14
15
16
17
18
19
20
21
22
23
24
25
26
—
—
—
—
9
—
—
7
ADCA_CH6a
ADCA_CH7a
PTE20
ADCA_CH6a
ADCA_CH7a
ADCA_CH6b
ADCA_CH7b
ADCA_CH2
ADCA_CH3
ADCA_CH6c
ADCA_CH7c
VDDA
ADCA_CH6a
ADCA_CH7a
ADCA_CH6b
ADCA_CH7b
ADCA_CH2
ADCA_CH3
ADCA_CH6c
ADCA_CH7c
VDDA
PTE20
PTE21
FTM1_CH0
FTM1_CH1
UART0_TX
UART0_RX
8
PTE21
—
—
—
—
9
ADCA_CH2
ADCA_CH3
ADCA_CH6c
ADCA_CH7c
VDDA
10
11
12
13
14
15
16
17
10
11
12
13
VREFH
VREFH
VREFH
VREFL
VREFL
VREFL
VSSA
VSSA
VSSA
PTE29
ADCA_CH4/
CMP1_IN5/
CMP0_IN5
ADCA_CH4/
CMP1_IN5/
CMP0_IN5
PTE29
PTE30
FTM0_CH2
FTM0_CH3
FTM_CLKIN0
FTM_CLKIN1
27
28
29
18
19
—
14
—
—
PTE30
DAC0_OUT/
CMP1_IN3/
ADCA_CH5
DAC0_OUT/
CMP1_IN3/
ADCA_CH5
ADCA_CH6d/ ADCA_CH6d/ ADCA_CH6d/
CMP0_IN4/
CMP2_IN3
CMP0_IN4/
CMP2_IN3
CMP0_IN4/
CMP2_IN3
VSS
VSS
VSS
KV4x Data Sheet, Rev. 3, 06/2016
49
NXP Semiconductors
Pinout
100
64
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP LQFP
30
31
—
—
VDD
VDD
VDD
20
15
PTE24
ADCB_CH4
ADCB_CH5
DISABLED
ADCB_CH4
PTE24
CAN1_TX
CAN1_RX
FTM0_CH0
FTM0_CH1
XBAR0_IN2
XBAR0_IN3
I2C0_SCL
I2C0_SDA
EWM_OUT_b XBAR0_
OUT4
32
21
16
PTE25/
LLWU_P21
ADCB_CH5
PTE25/
LLWU_P21
EWM_IN
XBAR0_
OUT5
33
34
—
—
PTE26
PTA0
PTE26
PTA0
22
17
JTAG_TCLK/
SWD_CLK
UART0_
CTS_b/
UART0_
COL_b
FTM0_CH5
XBAR0_IN4
EWM_IN
JTAG_TCLK/
SWD_CLK
35
36
23
24
18
19
PTA1
PTA2
JTAG_TDI
PTA1
PTA2
UART0_RX
UART0_TX
FTM0_CH6
FTM0_CH7
CMP0_OUT
CMP1_OUT
FTM1_CH1
FTM1_CH0
JTAG_TDI
JTAG_TDO/
TRACE_
SWO
JTAG_TDO/
TRACE_
SWO
37
38
39
25
26
27
20
21
—
PTA3
JTAG_TMS/
SWD_DIO
PTA3
UART0_
RTS_b
FTM0_CH0
FTM0_CH1
FTM0_CH2
XBAR0_IN9
EWM_OUT_b FLEXPWMA_ JTAG_TMS/
A0 SWD_DIO
PTA4/
LLWU_P3
NMI_b
PTA4/
LLWU_P3
XBAR0_IN10
FTM0_FLT3
FLEXPWMA_ NMI_b
B0
PTA5
DISABLED
PTA5
CMP2_OUT
JTAG_TRST_
b
40
41
42
—
—
28
22
23
—
VDD
VDD
VDD
VSS
VSS
VSS
PTA12
CMP2_IN0
CMP2_IN0
PTA12
CAN0_TX
CAN0_RX
FTM1_CH0
FTM1_CH1
FTM1_QD_
PHA
43
29
—
PTA13/
LLWU_P4
CMP2_IN1
CMP2_IN1
PTA13/
LLWU_P4
FTM1_QD_
PHB
44
45
46
—
—
—
—
—
—
PTA14
PTA15
PTA16
CMP3_IN0
CMP3_IN1
CMP3_IN2
CMP3_IN0
CMP3_IN1
CMP3_IN2
PTA14
PTA15
PTA16
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
UART0_TX
UART0_RX
UART0_
CTS_b/
UART0_
COL_b
47
—
—
PTA17
ADCA_CH7e
ADCA_CH7e
PTA17
SPI0_SIN
UART0_
RTS_b
48
49
50
30
31
32
—
—
24
VDD
VDD
VDD
VSS
VSS
VSS
PTA18
EXTAL0
EXTAL0
PTA18
PTA19
XBAR0_IN7
XBAR0_IN8
FTM0_FLT2
FTM1_FLT0
FTM_CLKIN0 XBAR0_
OUT8
FTM3_CH2
51
33
25
PTA19
XTAL0
XTAL0
FTM_CLKIN1 XBAR0_
OUT9
LPTMR0_
ALT1
52
53
34
35
26
27
RESET_b
RESET_b
RESET_b
PTB0/
LLWU_P5
ADCB_CH2
ADCB_CH2
PTB0/
LLWU_P5
I2C0_SCL
I2C0_SDA
FTM1_CH0
FTM1_CH1
FTM1_QD_
PHA
UART0_RX
UART0_TX
54
36
28
PTB1
ADCB_CH3
ADCB_CH3
PTB1
FTM0_FLT2
EWM_IN
FTM1_QD_
PHB
50
NXP Semiconductors
KV4x Data Sheet, Rev. 3, 06/2016
Pinout
100
64
48
Pin Name
Default
ALT0
ALT1
ALT2
I2C0_SCL
I2C0_SDA
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP LQFP
55
56
37
38
29
30
PTB2
ADCA_CH6e/ ADCA_CH6e/ PTB2
CMP2_IN2 CMP2_IN2
UART0_
RTS_b
FTM0_FLT1
FTM0_FLT3
FTM0_FLT0
PTB3
ADCB_CH7e/ ADCB_CH7e/ PTB3
CMP3_IN5
UART0_
CTS_b/
UART0_
COL_b
CMP3_IN5
57
58
59
60
61
62
63
64
65
66
—
—
—
—
—
39
40
41
42
—
—
—
—
—
—
31
32
—
—
—
PTB9
DISABLED
ADCB_CH6a
ADCB_CH7a
VSS
PTB9
PTB10
PTB11
VSS
ADCB_CH6a
ADCB_CH7a
VSS
PTB10
PTB11
FTM0_FLT1
FTM0_FLT2
VDD
VDD
VDD
PTB16
PTB17
PTB18
PTB19
PTB20
DISABLED
DISABLED
DISABLED
DISABLED
DISABLED
PTB16
PTB17
PTB18
PTB19
PTB20
UART0_RX
UART0_TX
FTM_CLKIN2 CAN0_TX
FTM_CLKIN1 CAN0_RX
FTM3_CH2
EWM_IN
XBAR0_IN5
EWM_OUT_b
CAN0_TX
CAN0_RX
FTM3_CH3
FLEXPWMA_ CMP0_OUT
X0
67
68
69
70
71
72
73
—
—
—
43
44
45
46
—
—
—
33
34
35
36
PTB21
PTB22
PTB23
PTC0
DISABLED
DISABLED
DISABLED
ADCB_CH6b
ADCB_CH7b
PTB21
PTB22
PTB23
PTC0
FLEXPWMA_ CMP1_OUT
X1
FLEXPWMA_ CMP2_OUT
X2
SPI0_PCS5
FLEXPWMA_ CMP3_OUT
X3
ADCB_CH6b
ADCB_CH7b
SPI0_PCS4
SPI0_PCS3
SPI0_PCS2
SPI0_PCS1
PDB0_
EXTRG
FTM0_FLT1
SPI0_PCS0
PTC1/
LLWU_P6
PTC1/
LLWU_P6
UART1_
RTS_b
FTM0_CH0
FTM0_CH1
FTM0_CH2
FLEXPWMA_ XBAR0_IN11
A3
PTC2
ADCB_CH6c/ ADCB_CH6c/ PTC2
CMP1_IN0
UART1_
CTS_b
FLEXPWMA_ XBAR0_IN6
B3
CMP1_IN0
PTC3/
CMP1_IN1
CMP1_IN1
PTC3/
UART1_RX
CLKOUT
FTM3_FLT0
LLWU_P7
LLWU_P7
74
75
76
47
48
49
—
—
37
VSS
VDD
VSS
VSS
VDD
VDD
PTC4/
LLWU_P8
DISABLED
PTC4/
LLWU_P8
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
UART1_TX
FTM0_CH3
XBAR0_IN2
XBAR0_IN3
XBAR0_IN4
CMP1_OUT
CMP0_OUT
77
78
79
80
81
50
51
52
53
54
38
39
40
—
—
PTC5/
LLWU_P9
DISABLED
PTC5/
LLWU_P9
LPTMR0_
ALT2
FTM0_CH2
I2C0_SCL
I2C0_SDA
PTC6/
LLWU_P10
CMP2_IN4/
CMP0_IN0
CMP2_IN4/
CMP0_IN0
PTC6/
LLWU_P10
PDB0_
EXTRG
UART0_RX
UART0_TX
XBAR0_
OUT6
PTC7
PTC8
PTC9
CMP3_IN4/
CMP0_IN1
CMP3_IN4/
CMP0_IN1
PTC7
XBAR0_
OUT7
ADCB_CH7c/ ADCB_CH7c/ PTC8
CMP0_IN2 CMP0_IN2
FTM3_CH4
FTM3_CH5
ADCB_CH6d/ ADCB_CH6d/ PTC9
CMP0_IN3 CMP0_IN3
KV4x Data Sheet, Rev. 3, 06/2016
51
NXP Semiconductors
Pinout
100
64
48
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
LQFP LQFP LQFP
82
83
55
56
—
—
PTC10
ADCB_CH7d
ADCB_CH6e
ADCB_CH7d
ADCB_CH6e
PTC10
FTM3_CH6
FTM3_CH7
PTC11/
PTC11/
LLWU_P11
LLWU_P11
84
85
86
87
88
89
90
91
92
93
—
—
—
—
—
—
—
—
—
57
—
—
—
—
—
—
—
—
—
41
PTC12
PTC13
PTC14
PTC15
VSS
DISABLED
DISABLED
DISABLED
DISABLED
VSS
PTC12
PTC13
PTC14
PTC15
FTM_CLKIN0
FTM_CLKIN1
FTM3_FLT0
I2C0_SCL
I2C0_SDA
VSS
VDD
VDD
VDD
PTC16
PTC17
PTC18
DISABLED
DISABLED
DISABLED
DISABLED
PTC16
PTC17
PTC18
CAN1_RX
CAN1_TX
PTD0/
LLWU_P12
PTD0/
LLWU_P12
SPI0_PCS0
SPI0_SCK
SPI0_SOUT
SPI0_SIN
FTM3_CH0
FTM3_CH1
FTM3_CH2
FTM3_CH3
FTM0_CH4
FTM0_CH5
FTM0_CH0
FTM0_CH1
FTM0_CH2
FTM0_CH3
FLEXPWMA_
A0
94
95
96
97
98
58
59
60
61
62
42
43
44
45
46
PTD1
ADCA_CH7f
DISABLED
DISABLED
DISABLED
ADCA_CH6g
ADCA_CH7f
PTD1
FLEXPWMA_
B0
PTD2/
LLWU_P13
PTD2/
LLWU_P13
FLEXPWMA_ I2C0_SCL
A1
PTD3
PTD3
FLEXPWMA_ I2C0_SDA
B1
PTD4/
LLWU_P14
PTD4/
LLWU_P14
SPI0_PCS1
SPI0_PCS2
UART0_
RTS_b
FLEXPWMA_ EWM_IN
A2
SPI0_PCS0
PTD5
ADCA_CH6g
ADCA_CH7g
PTD5
UART0_
CTS_b/
UART0_
COL_b
FLEXPWMA_ EWM_OUT_b SPI0_SCK
B2
99
63
64
47
48
PTD6/
LLWU_P15
ADCA_CH7g
DISABLED
PTD6/
LLWU_P15
SPI0_PCS3
UART0_RX
FTM0_CH6
FTM0_CH7
FTM1_CH0
FTM1_CH1
FTM0_FLT0
FTM0_FLT1
SPI0_SOUT
SPI0_SIN
100
PTD7
PTD7
UART0_TX
5.2 Pinout diagrams
The following diagrams show pinouts for the packages. For each pin, the diagrams
show the default function. However, many signals may be multiplexed onto a single
pin.
52
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
Pinout
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
PTE0/CLKOUT32K
PTE1/LLWU_P0
PTE2/LLWU_P1
PTE3
VDD
VSS
2
3
PTC3/LLWU_P7
PTC2
4
5
PTC1/LLWU_P6
PTC0
PTE4/LLWU_P2
PTE5
6
7
PTB23
PTE6/LLWU_P16
VDD
8
PTB22
9
PTB21
VSS
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PTB20
PTE16
PTB19
PTE17/LLWU_P19
PTE18/LLWU_P20
PTE19
PTB18
PTB17
PTB16
ADCA_CH6a
ADCA_CH7a
PTE20
VDD
VSS
PTB11
PTE21
PTB10
ADCA_CH2
ADCA_CH3
ADCA_CH6c
ADCA_CH7c
VDDA
PTB9
PTB3
PTB2
PTB1
PTB0/LLWU_P5
RESET_b
PTA19
VREFH
VREFL
VSSA
Figure 22. 100-pin LQFP
KV4x Data Sheet, Rev. 3, 06/2016
53
NXP Semiconductors
Pinout
PTE0/CLKOUT32K
PTE1/LLWU_P0
VDD
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
VDD
2
VSS
3
PTC3/LLWU_P7
PTC2
VSS
4
PTE16
5
PTC1/LLWU_P6
PTC0
PTE17/LLWU_P19
PTE18/LLWU_P20
PTE19
6
7
PTB19
8
PTB18
ADCA_CH2
ADCA_CH3
ADCA_CH6c
ADCA_CH7c
VDDA
9
PTB17
10
11
12
13
14
15
16
PTB16
PTB3
PTB2
PTB1
VREFH
PTB0/LLWU_P5
RESET_b
PTA19
VREFL
VSSA
Figure 23. 64-pin LQFP
54
NXP Semiconductors
KV4x Data Sheet, Rev. 3, 06/2016
Ordering parts
PTC3/LLWU_P7
PTC2
36
35
34
33
32
31
30
29
28
27
26
25
VDD
VSS
1
2
PTC1/LLWU_P6
PTC0
PTE16
3
PTE17/LLWU_P19
PTE18/LLWU_P20
PTE19
4
PTB17
5
PTB16
6
PTE20
PTB3
7
PTE21
PTB2
8
VDDA
PTB1
9
VREFH
PTB0/LLWU_P5
RESET_b
PTA19
10
11
12
VREFL
VSSA
Figure 24. 48-pin LQFP
6 Ordering parts
KV4x Data Sheet, Rev. 3, 06/2016
55
NXP Semiconductors
Part identification
6.1 Determining valid orderable parts
Valid orderable part numbers are provided on the web. To determine the orderable part
numbers for this device, go to www.nxp.com and perform a part number search for the
MKV4x device numbers.
7 Part identification
7.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
7.2 Format
Part numbers for this device have the following format:
Q KV## A FFF T PP CC S N
7.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Field
Description
Values
Q
Qualification status
Kinetis family
• M = Fully qualified, general market flow
• P = Prequalification
KV##
• KV42
• KV44
• KV46
A
Key attribute
• F = Cortex-M4 w/ DSP and FPU
FFF
Program flash memory size
• 64 = 64 KB
• 128 = 128 KB
• 256 = 256 KB
T
Temperature range (°C)
Package identifier
• V = –40 to 105
PP
• LF = 48 LQFP (7 mm x 7 mm)
• LH = 64 LQFP (10 mm x 10 mm)
• LL = 100 LQFP (14 mm x 14 mm)
CC
Maximum CPU frequency (MHz)
• 16 = 168 MHz
Table continues on the next page...
56
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
Terminology and guidelines
Values
Field
Description
S
N
Software type
• P = KMS-PMSM and BLDC
• (Blank) = Not software enabled
Packaging type
• R = Tape and reel
• (Blank) = Trays
7.4 Example
This is an example part number:
MKV46F256VLL16
8 Terminology and guidelines
8.1 Definition: Operating requirement
An operating requirement is a specified value or range of values for a technical
characteristic that you must guarantee during operation to avoid incorrect operation
and possibly decreasing the useful life of the chip.
8.1.1 Example
This is an example of an operating requirement:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
0.9
1.1
V
8.2 Definition: Operating behavior
Unless otherwise specified, an operating behavior is a specified value or range of
values for a technical characteristic that are guaranteed during operation if you meet
the operating requirements and any other specified conditions.
KV4x Data Sheet, Rev. 3, 06/2016
57
NXP Semiconductors
Terminology and guidelines
8.2.1 Example
This is an example of an operating behavior:
Symbol
Description
Min.
Max.
Unit
IWP
Digital I/O weak pullup/ 10
pulldown current
130
µA
8.3 Definition: Attribute
An attribute is a specified value or range of values for a technical characteristic that are
guaranteed, regardless of whether you meet the operating requirements.
8.3.1 Example
This is an example of an attribute:
Symbol
Description
Min.
Max.
Unit
CIN_D
Input capacitance:
digital pins
—
7
pF
8.4 Definition: Rating
A rating is a minimum or maximum value of a technical characteristic that, if exceeded,
may cause permanent chip failure:
• Operating ratings apply during operation of the chip.
• Handling ratings apply when the chip is not powered.
8.4.1 Example
This is an example of an operating rating:
Symbol
Description
Min.
Max.
Unit
VDD
1.0 V core supply
voltage
–0.3
1.2
V
58
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
Terminology and guidelines
8.5 Result of exceeding a rating
40
30
The likelihood of permanent chip failure increases rapidly as
soon as a characteristic begins to exceed one of its operating ratings.
20
10
0
Operating rating
Measured characteristic
8.6 Relationship between ratings and operating requirements
Fatal range
Degraded operating range
Normal operating range
Degraded operating range
Fatal range
Expected permanent failure
- No permanent failure
- No permanent failure
- Correct operation
- No permanent failure
Expected permanent failure
- Possible decreased life
- Possible incorrect operation
- Possible decreased life
- Possible incorrect operation
–∞
∞
Operating (power on)
Fatal range
Handling range
Fatal range
Expected permanent failure
No permanent failure
Expected permanent failure
–∞
∞
Handling (power off)
8.7 Guidelines for ratings and operating requirements
Follow these guidelines for ratings and operating requirements:
• Never exceed any of the chip’s ratings.
KV4x Data Sheet, Rev. 3, 06/2016
59
NXP Semiconductors
Terminology and guidelines
• During normal operation, don’t exceed any of the chip’s operating requirements.
• If you must exceed an operating requirement at times other than during normal
operation (for example, during power sequencing), limit the duration as much as
possible.
8.8 Definition: Typical value
A typical value is a specified value for a technical characteristic that:
• Lies within the range of values specified by the operating behavior
• Given the typical manufacturing process, is representative of that characteristic
during operation when you meet the typical-value conditions or other specified
conditions
Typical values are provided as design guidelines and are neither tested nor guaranteed.
8.8.1 Example 1
This is an example of an operating behavior that includes a typical value:
Symbol
Description
Min.
Typ.
Max.
Unit
IWP
Digital I/O weak
pullup/pulldown
current
10
70
130
µA
8.8.2 Example 2
This is an example of a chart that shows typical values for various voltage and
temperature conditions:
60
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
Revision history
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
TJ
150 °C
105 °C
25 °C
–40 °C
0
0.90
0.95
1.00
1.05
1.10
VDD (V)
8.9 Typical Value Conditions
Typical values assume you meet the following conditions (or other conditions as
specified):
Symbol
Description
Ambient temperature
3.3 V supply voltage
Value
Unit
TA
25
°C
V
VDD
3.3
9 Revision history
The following table provides a revision history for this document.
Table 43. Revision history
Rev. No.
Date
7/2014
2/2015
Substantial Changes
0
1
Initial NDA release.
• Added information about 48 LQFP package in the following
sections:
• Ordering information
• Fields
Table continues on the next page...
KV4x Data Sheet, Rev. 3, 06/2016
61
NXP Semiconductors
Revision history
Rev. No.
Table 43. Revision history (continued)
Date
Substantial Changes
• Obtaining package dimensions
• Pinout
• In table "Power consumption operating behaviors", removed the
text "Maximum core fequency of 150 Mhz" from note for IDDA
.
• In table "Typical device clock specifications", removed information
about High Speed run mode.
2
8/2015
• Updated instances of operating frequency from 150 MHz to 168
Mhz
• Changed document number from "KV4XP100M150" to
"KV4XP100M168" due to the change in operating frequency
• Part numbers ending with "15" changed to ending with "16"
• Removed instances of MKV45, MKV43, and MKV40 part
numbers
• Updated MKV41 part numbers to MKV42
• Added part numbers MKV44F256VLL16 and MKV44F256VLH16
• Updated table "Orderable part numbers summary"
• In table Recommended Operating Conditions :
• Updated minimum digital supply voltage to 1.71 V
• Added footnote numbers 2 and 3
• Removed rows for IOH, IOL, NF, TR, and tFLRET
• Updated table Voltage and current operating behaviors
• Updated table Power mode transition operating behaviors
• Updated table Power consumption operating behaviors
• Updated table EMC radiated emissions operating behaviors
• Updated table Typical device clock specifications
• Updated table Thermal attributes
• Updated the PLL section of table MCG specifications
• Updated tersall value in table Flash timing specifications —
commands
• Added note to section 12-bit cyclic Analog-to-Digital Converter
(ADC) parameters
• Updated IDDA_DACL P and IDDA_DACH P values in table 12-bit DAC
operating behaviors
• Updated the pinouts
• Added section Enhanced NanoEdge PWM characteristics
3
06/2016
• Changed occurences of Freescale to NXP
• In the features list, added a section for "Kinetis Motor Suite"
• Added section Kinetis Motor Suite (KMS)
• In table 12-bit ADC electrical specifications, changed typical value
of ENOB from 9.5 to 9.1
62
KV4x Data Sheet, Rev. 3, 06/2016
NXP Semiconductors
Information in this document is provided solely to enable system and software
implementers to use NXP products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits based
on the information in this document. NXP reserves the right to make changes
without further notice to any products herein.
How to Reach Us:
Home Page:
nxp.com
Web Support:
nxp.com/support
NXP makes no warranty, representation, or guarantee regarding the suitability of
its products for any particular purpose, nor does NXP assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims
any and all liability, including without limitation consequential or incidental
damages. “Typical” parameters that may be provided in NXP data sheets and/or
specifications can and do vary in different applications, and actual performance
may vary over time. All operating parameters, including “typicals,” must be
validated for each customer application by customer's technical experts. NXP
does not convey any license under its patent rights nor the rights of others. NXP
sells products pursuant to standard terms and conditions of sale, which can be
found at the following address: nxp.com/SalesTermsandConditions.
NXP, the NXP logo, NXP SECURE CONNECTIONS FOR A SMARTER
WORLD, Freescale, the Freescale logo, and Kinetis are trademarks of NXP B.V.
All other product or service names are the property of their respective owners.
ARM, the ARM Powered logo, and Cortex are registered trademarks of ARM
Limited (or its subsidiaries) in the EU and/or elsewhere. All rights reserved.
©2014–2016 NXP B.V.
Document Number KV4XP100M168
Revision 3, 06/2016
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