MKW21D512VHA5_技术文档

NXP Semiconductors

MKW2xDxxx

Data Sheet: Technical Data

Rev. 2, 05/2016

MKW2xD Data Sheet

MKW2xDxxxVHA5

Supports MKW24D512V, MKW22D512V, MKW21D512V, and

MKW21D256V Products

The MKW2xD is a low power, compact integrated device

consisting of:

• A high-performance 2.4 GHz IEEE 802.15.4 compliant

radio transceiver

• A powerful ARM Cortex-M4 MCU system with connectivity

• Precision mixed signal analog peripherals

The MKW2xD family of devices are used to easily enable

connectivity based on the IEEE 802.15.4 Standard.

64 LQFP

8.0x8.0x0.91 mm P 0.5 mm

Core Processor and Memories

• 50 MHz Cortex-M4 CPU with DSP capabilities

• Up to 512 KB of flash memory

• Up to 64 KB of SRAM

Peripherals

• USB

• Cryptographic Acceleration

• 16-bit ADC

• 12-bit DAC

• Flexible timers

Typical Applications

• Smart Energy 1.x

• ZigBee Home Automation

• ZigBee Healthcare

• ZigBee RF4CE

Radio transceiver performance

• Up to –102 dBm receiver sensitivity

• +8 dBm maximum transmit output power

• Up to 58 dBm channel rejection

• Current consumption is minimized with peak

transmit current of 17 mA at 0 dBm output power,

and peak receive current of 15 mA in Low Power

Preamble Search mode.

• ZigBee Light Link

• Thread

• Home Area Networks consisting of

• Meters

• Gateways

• In-home displays

• Connected appliances

• Networked Building Control and Home Automations

with

Package and Operating Characteristics

• Packaged in an 8 x 8 mm LGA with 56 contacts

• Voltage range: 1.8 V to 3.6 V

• Ambient temperature range: –40°C to 105°C

• Lighting Control

• HVAC

• Security

NXP reserves the right to change the production detail specifications as may be

Ordering Information

Memory

Operatin

g Temp

Range

(T_A)

Device

Package

Description

Options

MKW21D256VHA5(R)

-40 to

105°C

8x8 LGA (R: tape

and reel)

32 KB

Additional FlexMemory with up to 64 KB FlexNVM and

SRAM, up to 4 KB FlexRAM. No USB.

256 KB

flash

MKW21D512VHA5(R)

MKW22D512VHA5(R)

MKW24D512VHA5(R)

-40 to

105°C

8x8 LGA (R: tape

and reel)

64 KB

Supports higher memory option and additional GPIO.

SRAM, No USB. No FlexNVM or FlexRAM.

512 KB

flash

-40 to

105°C

8x8 LGA (R: tape

and reel)

64 KB

SRAM, FlexRAM.

512 KB

Supports full speed USB 2.0. No FlexNVM or

flash

-40 to

105°C

8x8 LGA (R: tape

and reel)

64 KB

Supports Smart Energy 2.0 and full-speed USB 2.0.

SRAM, No FlexNVM or FlexRAM.

512 KB

flash

Related Resources

Type

Description

Resource

Product Selector

Selector

Guide

The Kinetis MCUs Product Selector is a web-based tool that features

interactive application wizards and a dynamic product selector.

Fact Sheet

The Fact Sheet gives overview of the product key features and its uses. KW2X Fact Sheet

Reference

Manual

The Reference Manual contains a comprehensive description of the

structure and function (operation) of a device.

MKW2xDRM¹

This document.

98ASA00393D¹

Data Sheet

The Data Sheet includes electrical characteristics and signal

connections.

Package

drawing

Package dimensions are provided in package drawings.

1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.

2

MKW2xD Data Sheet, Rev. 2, 05/2016

NXP Semiconductors

Table of Contents

1

2

Features.............................................................................. 4

7.3.1 Voltage and current operating requirements..26

7.3.2 LVD and POR operating requirements.......... 27

7.3.3 Voltage and current operating behaviors.......28

7.3.4 Power mode transition operating behaviors...28

7.3.5 Power consumption operating behaviors.......29

7.3.6 EMC radiated emissions operating

1.1 Block diagram............................................................ 4

1.2 Radio features............................................................4

1.3 Microcontroller features............................................. 5

Transceiver description....................................................... 8

2.1 Key specifications...................................................... 8

2.2 RF interface and usage..............................................9

2.2.1 Clock output feature.......................................9

2.3 Transceiver functions.................................................10

2.3.1 Receive..........................................................10

2.3.2 Transmit.........................................................10

2.3.3 Clear channel assessment (CCA), energy

behaviors....................................................... 33

7.3.7 Designing with radiated emissions in mind....34

7.3.8 Capacitance attributes................................... 34

7.4 Switching specifications.............................................34

7.4.1 Device clock specifications............................ 34

7.4.2 General switching specifications....................35

7.5 Thermal specifications............................................... 36

7.5.1 Thermal operating requirements....................36

7.5.2 Thermal attributes..........................................36

7.6 Peripheral operating requirements and behaviors.....37

7.6.1 Core modules.................................................37

7.6.2 System modules............................................ 40

7.6.3 Clock modules............................................... 40

7.6.4 Memories and memory interfaces..................45

7.6.5 Security and integrity modules.......................49

7.6.6 Analog............................................................50

7.6.7 Timers............................................................57

7.6.8 Communication interfaces............................. 57

Transceiver Electrical Characteristics................................. 66

8.1 DC electrical characteristics.......................................66

8.2 AC electrical characteristics.......................................67

8.3 SPI timing: R_SSEL_B to R_SCLK........................... 68

8.4 SPI timing: R_SCLK to R_MOSI and R_MISO..........69

Crystal oscillator reference frequency.................................69

9.1 Crystal oscillator design considerations.....................69

9.2 Crystal requirements..................................................69

detection (ED), and link quality indicator

(LQI)...............................................................11

2.3.4 Packet processor........................................... 12

2.3.5 Packet buffering.............................................13

2.4 Dual PAN ID...............................................................14

System and power management.........................................15

3.1 Modes of operation.................................................... 15

3.2 Power management...................................................15

Radio Peripherals................................................................16

4.1 Clock output (CLK_OUT)...........................................16

4.2 General-purpose input output (GPIO)........................16

4.3 Serial peripheral interface (SPI).................................18

4.3.1 Features.........................................................18

4.4 Antenna diversity....................................................... 19

4.5 RF Output Power Distribution.................................... 19

MKW2xD operating modes................................................. 20

5.1 Transceiver Transmit Current Distribution................. 21

MKW2xD electrical characteristics......................................22

6.1 Radio recommended operating conditions................ 22

6.2 Ratings.......................................................................23

6.2.1 Thermal handling ratings............................... 23

6.2.2 Moisture handling ratings...............................23

6.2.3 ESD handling ratings..................................... 23

6.2.4 Voltage and current operating ratings............24

MCU Electrical characteristics.............................................24

7.1 Maximum ratings........................................................24

7.2 AC electrical characteristics.......................................25

7.3 Nonswitching electrical specifications........................26

3

4

8

9

5

6

10 Pin diagrams and pin assignments..................................... 71

10.1 MKW21D256/MKW21D512 Pin Assignment............. 71

10.2 MKW22/24D512V Pin Assignment............................ 72

10.3 Pin assignments.........................................................72

11 Dimensions..........................................................................76

11.1 Obtaining package dimensions..................................76

12 Revision History.................................................................. 77

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MKW2xD Data Sheet, Rev. 2, 05/2016

3

NXP Semiconductors

Features

1 Features

This section provides a simplified block diagram and highlights the device features.

1.1 Block diagram

Core

RF Transceiver

System

Memories

Internal and

External

Watchdogs

Program Flash

(up to 512 KB)

TM –M

ARM Cortex

4

IEEE 802.15.4 2006

2.4 GHz

®

50 MHz

FlexNVM

64 KB

4 KB FlexRAM

MKW21D256 only

Dual

PAN ID

Debug

Interfaces

Antenna Diversity

DSP

DMA

SRAM

(up to 64 KB)

32 MHz

OSC

SPI

Interrupt Controller

Low‐Leakage

Wake‐up Unit

Timers

Clocks

Analog

Security

Communication Interfaces

and Integrity

FlexTimer

Phase‐Locked

Loop

Cyclic

Redundancy

Check (CRC)

16‐bit

ADC

USB On‐the‐Go

I2C

Programmable

Delay Block

(HS)

Frequency

Locked Loop

Tamper Detect

USB Device

UART

High‐Speed

Comparator

with 6‐bit

DAC

Periodic Interrupt

Timers

Charger Detect

(ISO 7816)

Low/High

Frequency

Oscillators

Cryptography

Authentication

Unit

(DCD)

Low‐Power

Timer

USB Voltage

Regulator

SPI

Internal

Reference

Clocks

Independent

Real‐Time

Clock (RTC)

Random Number

Generator

Standard Feature

Optional

Figure 1. MKW2xD simplified block diagram

1.2 Radio features

• Fully compliant 802.15.4 Standard transceiver supports 250 kbps data rate with O-

QPSK modulation in 5.0 MHz channels with direct sequence spread-spectrum

(DSSS) encode and decode

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MKW2xD Data Sheet, Rev. 2, 05/2016

NXP Semiconductors

Features

• Operates on one of 16 selectable channels in the 2.4 GHz frequency ISM band

• Programmable output power

• Supports 2.36 to 2.4 GHz Medical Band (MBAN) frequencies with same

modulation as IEEE 802.15.4

• Hardware acceleration for IEEE® 802.15.4 2006 packet processing

• Random number generator

• Support for dual PAN mode

• 32 MHz crystal reference oscillator with on board trim capability to supplement

external load capacitors

• Programmable frequency clock output (CLK_OUT)

• Control port for Antenna Diversity mode

• Clocks

• 32 MHz crystal oscillator

• Internal 1 kHz low power oscillator

• DC to 32 MHz external square wave input clock

• Small RF footprint

• Differential input/output port used with external balun

• Integrated transmit/receive switch

• Supports single ended and antenna diversity options

• Low external components count

• Supports external PA and LNA

1.3 Microcontroller features

• Core:

• ARM Cortex-M4 Core at 50 MHz (1.25 MIPS/MHz)

• Supports DSP instructions

MKW2xD Data Sheet, Rev. 2, 05/2016

5

NXP Semiconductors

Features

• Nested vectored interrupt controller (NVIC)

• Asynchronous wake-up interrupt controller (AWIC)

• Debug and trace capability

• 2-pin serial wire debug (SWD)

• IEEE 1149.1 Joint Test Action Group (JTAG)

• IEEE 1149.7 compact JTAG (cJTAG)

• Trace port interface unit (TPIU)

• Flash patch and breakpoint (FPB)

• Data watchpoint and trace (DWT)

• Instrumentation trace macrocell (ITM)

• Enhanced trace macrocell (ETM)

• System and power management:

• Software and hardware watchdog with external monitor pin

• DMA controller with 16 channels

• Low-leakage wake-up unit (LLWU)

• Power management controller with 10 different power modes

• Non-maskable interrupt (NMI)

• 128-bit unique identification (ID) number per chip

• Memories and memory interfaces:

• Up to 512 KB Program Flash

• Up to 64 KB of SRAM

• In MKW21D256, FlexMemory with up to 64 KB FlexNVM and up to 4 KB

FlexRAM can be partitioned.

• EEPROM has endurance of 10 million cycles over full voltage and temperature

range and read-while-write capability

• Flash security and protection features

• Serial flash programming interface (EzPort)

6

MKW2xD Data Sheet, Rev. 2, 05/2016

NXP Semiconductors

Features

• Clocks

• Multi-purpose clock generator

• PLL and FLL operation

• Internal reference clocks (32 kHz or 2 MHz)

• Three separate crystal oscillators

• 3 MHz to 32 MHz crystal oscillator for MCU

• 32 kHz to 40 kHz crystal oscillator for MCU or RTC

• 32 MHz crystal oscillator for Radio

• Internal 1 kHz low power oscillator

• DC to 50 MHz external square wave input clock

• Security and integrity

• Hardware CRC module to support fast cyclic redundancy checks

• Tamper detect and secure storage

• Hardware random-number generator

• Hardware encryption supporting DES, 3DES, AES, MD5, SHA-1, and

SHA-256 algorithms

• 128-bit unique identification (ID) number per chip

• Analog

• 16-bit SAR ADC

• High-speed Analog comparator (CMP) with 6-bit DAC

• Timers

• Up to 12 channels; 7 channels support external connections; 5 channels are

internal only

• Carrier modulator timer (CMT)

• Programmable delay block (PDB)

• 1x4ch programmable interrupt timer (PIT)

MKW2xD Data Sheet, Rev. 2, 05/2016

7

NXP Semiconductors

Transceiver description

• Low-power timer (LPT)

• FlexTimers that support general-purpose PWM for motor control functions

• Communications

• One SPI

• Two I²C with SMBUS support

• Three UARTs (w/ ISO7816, IrDA, and hardware flow control)

• One USB On-The-Go Full Speed

• Human-machine interface

• GPIO with pin interrupt support, DMA request capability, digital glitch filter,

and other pin control options

• Operating characteristics

• Voltage range 1.8 V - 3.6 V

• Flash memory programming down to 1.8 V

• Temperature range (TA) -40 to 105°C

2 Transceiver description

2.1 Key specifications

MKW2xD meets or exceeds all IEEE 802.15.4 performance specifications applicable to

2.4 GHz ISM and MBAN (Medical Band Area Network) bands. Key specifications for

MKW2xD are:

• ISM band:

• RF operating frequency: 2405 MHz to 2480 MHz (center frequency range)

• 5 MHz channel spacing

• MBAN band:

• RF operating frequency: 2360 MHz to 2400 MHz (center frequency range)

• MBAN channel page 9 is (2360 MHz-2390 MHz band)

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MKW2xD Data Sheet, Rev. 2, 05/2016

NXP Semiconductors

Transceiver description

• Fc = 2363.0 + 1.0 * k in MHz for k = 0, 1, 2, ...26

• MBAN channel page 10 is (2390 MHz-2400 MHz band)

• Fc = 2390.0 + 1.0 * k in MHz for k = 0, 1, 2, ...8

• IEEE 802.15.4 Standard 2.4 GHz modulation scheme

• Chip rate: 2000 kbps

• Data rate: 250 kbps

• Symbol rate: 62.5 kbps

• Modulation: OQPSK

• Receiver sensitivity: -102 dBm, typical (@1% PER for 20 byte payload packet)

• Differential bidirectional RF input/output port with integrated transmit/receive

switch

• Programmable output power from -35 dBm to +8 dBm.

2.2 RF interface and usage

The MKW2xD RF output ports are bidirectional (diplexed between receive/transmit

modes) and differential enabling interfaces with numerous off-chip devices such as a

balun. When using a balun, this device provides an interface to directly connect

between a single-ended antenna and the MKW2xD RF ports. In addition, MKW2xD

provides four output driver ports that can have both drive strength and slew rate

configured to control external peripheral devices. These signals designated as

ANT_A, ANT_B, RX_SWITCH, and TX_SWITCH when enabled are switched via

an internal hardware state machine. These ports provide control features for peripheral

devices such as:

• Antenna diversity modules

• External PAs

• External LNAs

• T/R switches

MKW2xD Data Sheet, Rev. 2, 05/2016

9

NXP Semiconductors

Transceiver functions

2.2.1 Clock output feature

The CLK_OUT digital output can be enabled to drive the system clock to the MCU.

This provides a highly accurate clock source based on the transceiver reference

oscillator. The clock is programmable over a wide range of frequencies divided down

from the reference 32 MHz (see Table 2). The CLK_OUT pin will be enabled upon

POR. The frequency CLK_OUT default to 4 MHz (32 MHz/8).

2.3 Transceiver functions

2.3.1 Receive

The receiver has the functionality to operate in either normal run state or low power run

state that can be considered as a partial power down mode. Low power run state can

save a considerable amount of current by duty-cycling some sections of the receiver

lineup during preamble search and is referred to as Low Power Preamble Search mode

(LPPS).

The radio receiver path is based upon a near zero IF (NZIF) architecture incorporating

front end amplification, one mixed signal down conversion to IF that is programmably

filtered, demodulated and digitally processed. The RF front end (FE) input port is

differential that shares the same off chip matching network with the transmit path.

2.3.2 Transmit

MKW2xD transmits OQPSK modulation having power and channel selection

adjustment per user application. After the channel of operation is determined, coarse

and fine tuning is executed within the Frac-N PLL to engage signal lock. After signal

lock is established, the modulated buffered signal is then routed to a multi-stage

amplifier for transmission. The differential signals at the output of the PA (RFOUTP,

RFOUTN) are converted as single ended (SE) signals with off chip components as

required.

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MKW2xD Data Sheet, Rev. 2, 05/2016

NXP Semiconductors

Transceiver functions

2.3.3 Clear channel assessment (CCA), energy detection (ED), and

link quality indicator (LQI)

The MKW2xD supports three clear channel assessment (CCA) modes of operation

including energy detection (ED) and link quality indicator (LQI). Functionality for

each of these modes is as follows.

2.3.3.1 CCA mode 1

CCA mode 1 has two functions:

• To estimate the energy in the received baseband signal. This energy is estimated

based on receiver signal strength indicator (RSSI).

• To determine whether the energy is greater than a set threshold.

The estimate of the energy can also be used as the Link Quality metric. In CCA Mode

1, the MKW2xD must warm up from Idle to Receive mode where RSSI averaging

takes place.

2.3.3.2 CCA mode 2

CCA mode 2 detects whether there is any 802.15.4 signal transmitting in the

frequency band that an 802.15.4 transmitter intends to transmit. From the definition of

CCA mode 2 in the 802.15.4 standard, the requirement is to detect an 802.15.4

complied signal. Whether the detected energy is strong or not is not important for

CCA mode 2.

2.3.3.3 CCA mode 3

CCA mode 3 as defined by 802.15.4 standard is implemented using a logical

combination of CCA mode 1 and CCA mode 2. Specifically, CCA mode 3 operates in

one of two operating modes:

• CCA mode 3 is asserted if both CCA mode 1 and CCA mode 2 are asserted.

• CCA mode 3 is asserted if either CCA mode 1 or CCA mode 2 is asserted.

This mode setting is available through a programmable register.

MKW2xD Data Sheet, Rev. 2, 05/2016

11

NXP Semiconductors

Transceiver functions

2.3.3.4 Energy detection (ED)

Energy detection (ED) is based on receiver signal strength indicator (RSSI) and

correlator output for the 802.15.4 standard. ED is an average value of signal strength.

The magnitude from this measurement is calculated from the digital RSSI value that is

averaged over a 128 μs duration.

2.3.3.5 Link quality indicator (LQI)

Link quality indicator (LQI) is based on receiver signal strength indicator (RSSI) or

correlator output for the 802.15.4 standard. In this mode, the RSSI measurement is done

during normal packet reception. LQI computations for the MKW2xD are based on

either digital RSSI or correlator peak values. This setting is executed through a register

bit where the final LQI value is available 64 μs after preamble is detected. If a

continuous update of LQI based on RSSI throughout the packet is desired, it can be read

in a separate 8-bit register by enabling continuous update in a register bit.

2.3.4 Packet processor

The MKW2xD packet processor performs sophisticated hardware filtering of the

incoming received packet to determine if the packet is both PHY- and MAC-compliant,

is addressed to this device, if the device is a PAN coordinator and whether a message is

pending for the sending device. The packet processor greatly reduces the packet

filtering burden on software allowing it to tend to higher-layer tasks with a lower

latency and smaller software footprint.

2.3.4.1 Features

• Aggressive packet filtering to enable long, uninterrupted MCU sleep periods

• Fully compliant with both 2003 and 2006 versions of the 802.15.4 wireless

standard

• Supports all frame types, including reserved types

• Supports all valid 802.15.4 frame lengths

• Enables auto-Tx acknowledge frames (no MCU intervention) by parsing of frame

control field and sequence number

• Supports all source and destination address modes, and also PAN ID compression

• Supports broadcast address for PAN ID and short address mode

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MKW2xD Data Sheet, Rev. 2, 05/2016

NXP Semiconductors

Transceiver functions

• Supports “promiscuous” mode, to receive all packets regardless of address- and

rules-checking

• Allows frame type-specific filtering (e.g., reject all but beacon frames)

• Supports SLOTTED and non-SLOTTED modes

• Includes special filtering rules for PAN coordinator devices

• Enables minimum-turnaround Tx-acknowledge frames for data-polling requests

by automatically determining message-pending status

• Assists MCU in locating pending messages in its indirect queue for data-polling

end devices

• Makes available to MCU detailed status of frames that fail address- or rules-

checking.

• Supports Dual PAN mode, allowing the device to exist on 2 PAN's

simultaneously

• Supports 2 IEEE addresses for the device

• Supports active promiscuous mode

2.3.5 Packet buffering

The packet buffer is a 128-byte random access memory (RAM) dedicated to the

storage of 802.15.4 packet contents for both TX and RX sequences. For TX

sequences, software stores the contents of the packet buffer starting with the frame

length byte at packet buffer address 0 followed by the packet contents at the

subsequent packet buffer addresses. For RX sequences the incoming packet's frame

length is stored in a register external to the packet buffer. Software will read this

register to determine the number of bytes of packet buffer to read. This facilitates

DMA transfer through the SPI. For receive packets, an LQI byte is stored at the byte

immediately following the last byte of the packet (frame length +1). Usage of the

packet buffer for RX and TX sequences is on a time-shared basis; receive packet data

will overwrite the contents of the packet buffer. Software can inhibit receive-packet

overwriting of the packet buffer contents by setting the PB_PROTECT bit. This will

block RX packet overwriting, but will not inhibit TX content loading of the packet

buffer via the SPI.

MKW2xD Data Sheet, Rev. 2, 05/2016

13

NXP Semiconductors

Transceiver functions

2.3.5.1 Features

• 128 byte buffer stores maximum length 802.15.4 packets

• Same buffer serves both TX and RX sequences

• The entire Packet Buffer can be uploaded or downloaded in a single SPI burst.

• Automatic address auto-incrementing for burst accesses

• Single-byte access mode supported.

• Entire packet buffer can be accessed in hibernate mode

• Under-run error interrupt supported

2.4 Dual PAN ID

In the past, radio transceivers designed for IEEE 802.15.4 applications allowed a device

to associate to one and only one PAN (Personal Area Network) at any given time. The

MKW2xD represents a high-performance SiP that includes hardware support for a

device to reside in two networks simultaneously. In optional Dual PAN mode, the

device alternates between the two (2) PANs under hardware or software control.

Hardware support for Dual PAN operation consists of two (2) sets of PAN and IEEE

addresses for the device, two (2) different channels (one for each PAN) and a

programmable timer to automatically switch PANs (including on-the-fly channel

changing) without software intervention. There are control bits to configure and enable

Dual PAN mode, and read only bits to monitor status in Dual PAN mode. A device can

be configured to be a PAN coordinator on either network, both networks or neither.

For the purpose of defining PAN in the context of Dual PAN mode, two (2) sets of

network parameters are maintained; PAN0 and PAN1. PAN0 and PAN1 will be used to

refer to the two (2) PANs where each parameter set uniquely identifies a PAN for Dual

PAN mode. These parameters are described in Table 1.

Table 1. PAN0 and PAN1 descriptions

PAN0

PAN1

Channel0 (PHY_INT0, PHY_FRAC0)

MacPANID0 (16-bit register)

MacShortAddrs0 (16-bit register)

MacLongAddrs0 (64-bit registers)

PANCORDNTR0 (1-bit register)

Channel1 (PHY_INT1, PHY_FRAC1)

MacPANID1 (16-bit register)

MacShortAddrs1 (16-bit register)

MacLongAddrs1 (64-bit registers)

PANCORDNTR1 (1-bit register)

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NXP Semiconductors

MKW2xD Data Sheet, Rev. 2, 05/2016

System and power management

During device initialization if Dual PAN mode is used, software will program both

parameter sets to configure the hardware for operation on two (2) networks.

3 System and power management

The MKW2xD is a low power device that also supports extensive system control and

power management modes to maximize battery life and provide system protection.

3.1 Modes of operation

The transceiver modes of operation include:

• Idle mode

• Doze mode

• Low power (LP) / hibernate mode

• Reset / powerdown mode

• Run mode

3.2 Power management

The MKW2xD power management is controlled through programming the modes of

operation. Different modes allow for different levels of power-down and RUN

operation. For the receiver, programmable power modes available are:

• Preamble search

• Preamble search sniff

• Low Power Preamble Search (LPPS)

• Fast Antenna Diversity (FAD) Preamble search

• Packet decoding

MKW2xD Data Sheet, Rev. 2, 05/2016

15

NXP Semiconductors

Radio Peripherals

4 Radio Peripherals

The MKW2xD provides a set of I/O pins useful for suppling a system clock to the

MCU, controlling external RF modules/circuitry, and GPIO.

4.1 Clock output (CLK_OUT)

MKW2xD integrates a programmable clock to source numerous frequencies for

connection with various MCUs. Package pin 39 can be used to provide this clock source

as required allowing the user to make adjustments per their application requirement.

The transceiver CLK_OUT pin is internally connected to the MCU EXTAL pin so that

no external connection is needed to drive the MCU clock.

Care must be taken that the clock output signal does not interfere with the reference

oscillator or the radio. Additional functionality this feature supports is:

• XTAL domain can be completely gated off (hibernate mode)

• SPI communication allowed in hibernate

Table 2. CLK_OUT

CLK_OUT_DIV [2:0]

CLK_OUT frequency

32 MHz¹

0

1

2

3

4

5

6

7

16 MHz¹

8 MHz¹

4 MHz

2 MHz

1 MHz

62.5 kHz

32.786 kHz

1. May require high drive strength for proper signal integrity.

There is an enable/disable bit for CLK_OUT. When disabling, the clock output will

optionally continue to run for 128 clock cycles after disablement. There is also be one

(1) bit available to adjust the CLK_OUT I/O pad drive strength.

16

MKW2xD Data Sheet, Rev. 2, 05/2016

NXP Semiconductors

Radio Peripherals

4.2 General-purpose input output (GPIO)

In addition to the MCU supported GPIOs, the radio supports 2 GPIO pins. All I/O

pins will have the same supply voltage and depending on the supply, can vary from

1.8 V up to 3.6 V. When the pin is configured as a general-purpose output or for

peripheral use, there will be specific settings required per use case. Pin configuration

will be executed by software to adjust input/output direction and drive strength,

capability. When the pin is configured as a general-purpose input or for peripheral

use, software (see Table 3) can enable a pull-up or pull-down device. Immediately

after reset, all pins are configured as high-impedance general-purpose inputs with

internal pull-up devices enabled.

Features for these pins include:

• Programmable output drive strength

• Programmable output slew rate

• Hi-Z mode

• Programmable as outputs or inputs (default)

Table 3. Pin configuration summary

Tolerance

Pin function configuration

Details

Units

Min.

—

2

Typ.

10

2

Max.

—

10

6

I/O buffer full drive mode¹

I/O buffer partial drive mode¹

I/O buffer high impedance²

No slew, full drive

Source or sink

Off state

Rise and fall time³

Rise and fall time

Full drive⁵

mA

nA

ns

—

4

No slew, partial drive

2

4

6

Slew, full drive

6

12

—

24

11

50

Slew, partial drive

6

Propagation delay⁴, no slew

Propagation delay, no slew

Propagation delay, slew

—

Partial drive⁶

Full drive

Partial drive

1. For this drive condition, the output voltage will not deviate more than 0.5 V from the rail reference VOH or VOL.

2. Leakage current applies for the full range of possible input voltage conditions.

3. Rise and fall time values in reference to 20% and 80%

4. Propagation Delay measured from/to 50% voltage point.

5. Full drive values provided are in reference to a 75 pF load.

6. Partial drive values provided are in reference to a 15 pF load.

MKW2xD Data Sheet, Rev. 2, 05/2016

17

NXP Semiconductors

Radio Peripherals

4.3 Serial peripheral interface (SPI)

The MKW2xD SiP uses a SPI interface allowing the MCU to communicate with the

radio's register set and packet buffer. The SPI is a slave-only interface; the MCU must

drive R_SSEL_B, R_SCLK and R_MOSI. Write and read access to both direct and

indirect registers is supported, and transfer length can be single-byte or bursts of

unlimited length. Write and read access to the Packet buffer can also be single-byte or a

burst mode of unlimited length.

The SPI interface is asynchronous to the rest of the IC. No relationship between

R_SCLK and MKW2xD's internal oscillator is assumed. And no relationship between

R_SCLK and the CLK_OUT pin is assumed. All synchronization of the SPI interface to

the IC takes place inside the SPI module. SPI synchronization takes place in both

directions; register writes and register reads. The SPI is capable of operation in all

power modes, except Reset. Operation in hibernate mode allows most transceiver

registers and the complete packet buffer to be accessed in the lowest-power operating

state enabling minimal power consumption, especially during the register-initialization

phase of the radio.

The SPI design features a compact, single-byte control word, reducing SPI access

latency to a minimum. Most SPI access types require only a single-byte control word,

with the address embedded in the control word. During control word transfer (the first

byte of any SPI access), the contents of the IRQSTS1 register (MKW2xD radio's

highest-priority status register) are always shifted out so that the MCU gets access to

IRQSTS1, with the minimum possible latency, on every SPI access.

4.3.1 Features

• 4-wire industry standard interface, supported by all MCUs

• SPI R_SCLK maximum frequency 16 MHz (for SPI write accesses)

• SPI R_SCLK maximum frequency 9 MHz (for SPI read accesses)

• Write and read access to all radio registers (direct and indirect)

• Write and read access to packet buffer

• SPI accesses can be single-byte or burst

• Automatic address auto-incrementing for burst accesses

18

MKW2xD Data Sheet, Rev. 2, 05/2016

NXP Semiconductors

Radio Peripherals

• The entire packet buffer can be uploaded or downloaded in a single SPI burst

• Entire packet buffer and most registers can be accessed in hibernate mode

• Built-in synchronization inside the SPI module to/from the rest of the radio

4.4 Antenna diversity

To improve the reliability of RF connectivity to long range applications, the antenna

diversity feature is supported without using the MCU through use of four dedicated

control pins (package pins 44, 45, 46, and 47).

Fast antenna diversity (FAD) mode supports this radio feature and, when enabled, will

allow the choice of selection between two antennas during the preamble phase. By

continually monitoring the received signal, the FAD block will select the first antenna

of which the received signal has a correlation factor above a predefined progammable

threshold. The FAD accomplishes the antenna selection by sequentially switching

between the two antennas testing for the presence of suitably strong s0 symbol where

the first antenna to reach this condition is then selected for the reception of the packet.

The antenna's are monitored for a period of 28 μs each. The antenna switching is

continued until 1.5 valid s0 symbols are detected. The demodulator then continues

with normal preamble search before declaring “Preamble Detect”.

4.5 RF Output Power Distribution

The following figure shows the linear region of the output and the typical power

distribution of the radio as a function of PA_PWR [4:0] range. The PA_PWR [4:0] is

the lower 5 bits of the PA_PWR 0x23 direct register and has a usable range of 3 to 31

decimal.

MKW2xD Data Sheet, Rev. 2, 05/2016

19

NXP Semiconductors

MKW2xD operating modes

Figure 2. MKW2xD transmit power vs. PA_PWR step

5 MKW2xD operating modes

For the discussion of this topic, the primary radio and MCU operating modes are

combined so that overall power consumption can then be derived. Depending on the

stop requirements of the user application, a variety of stop modes are available that

provide state retention, partial power down or full power down of certain logic and/or

memory. I/O states are held in all modes of operation. Both the radio and MCU's power

modes are described as follows.

The radio has 6 primary operating modes:

• Reset / power down

• Low power (LP) / hibernate

• Doze (low power with reference oscillator active)

20

MKW2xD Data Sheet, Rev. 2, 05/2016

NXP Semiconductors

MKW2xD operating modes

• Idle

• Receive

• Transmit

Table 4 lists and describes the transceivers power modes and consumption.

Table 4. Transceiver Power Modes

Current

Mode

Definition

consumption¹

Reset / All IC functions off, leakage only. RST asserted.

< 100 nA

powerdow

n

Low

Crystal reference oscillator off. (SPI is functional.)

< 1 μA

power /

hibernate

Doze²

Crystal reference oscillator on but CLK_OUT output available only if selected.

Crystal reference oscillator on with CLK_OUT output available only if selected.

500 μA³

(no CLK_OUT)

700 μA³

Idle

(no CLK_OUT)

< 19.5 mA ⁴

Receive Crystal reference oscillator on. Receiver on.

Transmit Crystal reference oscillator on. Transmitter on.

15 mA, LPPS

mode

< 18 mA ⁵

1. Conditions: VBAT and VBAT_2 = 2.7 V, nominal process @ 25°C

2. While in Doze mode, 4 MHz max frequency can be selected for CLK_OUT.

3. Typical

4. Signal sensitivity = -102 dBm

5. RF output = 0 dBm

The MCU has a variety of operating modes. For each run mode there is a

corresponding wait and stop mode. Wait modes are similar to ARM sleep modes. Stop

modes (VLPS, STOP) are similar to ARM sleep deep mode. The very low power run

(VLPR) operating mode can drastically reduce runtime power when the maximum bus

frequency is not required to handle the application needs.

The three primary modes of operation are run, wait and stop. The WFI instruction

invokes both wait and stop modes for the chip. The primary modes are augmented in a

number of ways to provide lower power based on application needs.

MKW2xD Data Sheet, Rev. 2, 05/2016

21

NXP Semiconductors

MKW2xD electrical characteristics

5.1 Transceiver Transmit Current Distribution

The following figure shows the relation between the transmit power generated by the

radio and its current consumption.

Figure 3. MKW2xD transmit power vs transmit current (Radio Only)

6 MKW2xD electrical characteristics

6.1 Radio recommended operating conditions

Table 5. Recommended operating conditions

Characteristic

Symbol

Min

1.8

Typ

2.7

—

Max

3.6

Unit

Vdc

GHz

°C

Power Supply Voltage (V_BAT= VDD_INT

Input Frequency

)

V_BAT, VDD_INT

fin

2.360

-40

2.480

105

Ambient Temperature Range

TA

25

Table continues on the next page...

22

MKW2xD Data Sheet, Rev. 2, 05/2016

NXP Semiconductors

Ratings

Table 5. Recommended operating conditions (continued)

Characteristic

Symbol

Min

Typ

Max

Unit

Logic Input Voltage Low

VIL

0

—

30%

V

VDDINT

Logic Input Voltage High

VIH

70%

—

VDDINT

V

VDDINT

SPI Clock Rate

RF Input Power

f_SPI

Pmax

fref

—

16.0

10

MHz

dBm

Crystal Reference Oscillator Frequency ( 40 ppm over

operating conditions to meet the 802.15.4 Standard.)

32 MHz only

6.2 Ratings

6.2.1 Thermal handling ratings

Symbol

T_STG

Description

Min.

Max.

150

Unit

°C

Notes

Storage temperature

Solder temperature, lead-free

–55

—

1

2

T_SDR

260

°C

1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.

2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

6.2.2 Moisture handling ratings

Symbol

Description

Min.

Max.

Unit

Notes

MSL

Moisture sensitivity level

—

3

—

1

1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic

Solid State Surface Mount Devices.

6.2.3 ESD handling ratings

Symbol

V_HBM

Description

Min.

-2000

-500

Max.

+2000

+500

Unit

V

Notes

Electrostatic discharge voltage, human body model

1

2

V_CDM

Electrostatic discharge voltage, charged-device

model

V

Table continues on the next page...

MKW2xD Data Sheet, Rev. 2, 05/2016

23

NXP Semiconductors

MCU Electrical characteristics

Symbol

Description

Min.

Max.

Unit

Notes

I_LAT

Latch-up current at ambient temperature of 105°C

-100

+100

mA

3

1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human

Body Model (HBM).

2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for

Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.

3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.

6.2.4 Voltage and current operating ratings

Symbol

V_DD

Description

Min.

–0.3

Max.

3.6

Unit

V

Digital supply voltage

I_DD

Digital supply current

—

155

mA

V

V_DIO

Digital input voltage (except RESET, EXTAL, and XTAL)

Analog¹, RESET, EXTAL, and XTAL input voltage

Maximum current single pin limit (applies to all digital pins)

Analog supply voltage

–0.3

V_DD+ 0.3

25

V_AIO

–0.3

V

I_D

–25

mA

V

V_DDA

V_DD– 0.3

–0.3

V_DD+ 0.3

3.63

V_{USB0_DP}

V_{USB0_DM}

USB0_DP input voltage

V

USB0_DM input voltage

–0.3

3.63

V

1. Analog pins are defined as pins that do not have an associated general purpose I/O port function.

7 MCU Electrical characteristics

7.1 Maximum ratings

Table 6. Maximum ratings

Requirement

Power Supply Voltage

Digital Input Voltage

RF Input Power

Description

Symbol

VBAT, VBAT2

Vin

Rating level

-0.3 to 3.6

Unit

Vdc

dBm

-0.3 to (VDDINT + 0.3)

+10

Pmax

Note: Maximum ratings are those values beyond which damage to the device may occur. Functional operation should be

restricted to the limits in the electrical characteristics or recommended operating conditions tables.

Human Body

Model

HBM

2000

200

Vdc

ESD¹

Machine Model

MM

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24

NXP Semiconductors

MKW2xD Data Sheet, Rev. 2, 05/2016

MCU Electrical characteristics

Table 6. Maximum ratings (continued)

Requirement

Description

Symbol

Rating level

Unit

Charged Device

Model

CDM

750

Vdc

Power Electro-

Static

Discharge /

Direct Contact

No damage / latch up to 4000

No soft failure / reset to 1000

Vdc

PESD

Power Electro-

Static

Discharge /

Indirect Contact

No damage / latch up to 6000

No soft failure / reset to 1000

EMC²

No damage / latch up to 5

No soft failure / reset to 5

No damage / latch up to 300

No soft failure / reset to 150

+125

Langer IC / EFT /

P201

Vdc

EFT (Electro

Magnetic Fast

Transient)

Langer IC / EFT /

P201

Junction Temperature

T_J

°C

Storage Temperature Range

T_stg

-65 to +165

1. Electrostatic discharge on all device pads meet this requirement

2. Electromagnetic compatibility for this product is low stress rating level

Note

Maximum ratings are those values beyond which damage to

the device may occur. Functional operation should be

restricted to the limits in the electrical characteristics or

recommended operating conditions tables.

7.2 AC electrical characteristics

Unless otherwise specified, propagation delays are measured from the 50% to the 50%

point, and rise and fall times are measured at the 20% and 80% points, as shown in the

following figure.

MKW2xD Data Sheet, Rev. 2, 05/2016

25

NXP Semiconductors

MCU Electrical characteristics

High

Low

V_IH

Midpoint1

80%

50%

20%

Input Signal

V_IL

Fall Time

Rise Time

The midpoint is V_IL+ (V_IH- V_IL) / 2

Figure 4. Input signal measurement reference

7.3 Nonswitching electrical specifications

7.3.1 Voltage and current operating requirements

Table 7. Voltage and current operating requirements

Symbol

V_DD

Description

Min.

1.8

Max.

3.6

0.1

3.6

Unit

V

Notes

Supply voltage

V_DDA

Analog supply voltage

1.8

V

V_DD– V_DDAV_DD-to-V_DDAdifferential voltage

V_SS– V_SSAV_SS-to-V_SSAdifferential voltage

–0.1

1.8

V

V_BAT

V_IH

RTC battery supply voltage

Input high voltage

V

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.7 V ≤ V_DD≤ 2.7 V

0.7 × V_DD

—

V

0.75 × V_DD

V_IL

Input low voltage

• 2.7 V ≤ V_DD≤ 3.6 V

• 1.7 V ≤ V_DD≤ 2.7 V

—

0.35 × V_DD

0.3 × V_DD

V

V_HYS

I_ICIO

Input hysteresis

0.06 × V_DD

—

V

I/O pin DC injection current — single pin

• V_IN< V_SS-0.3V (Negative current injection)

• V_IN> V_DD+0.3V (Positive current injection)

1

mA

-3

—

+3

I_ICcont

Contiguous pin DC injection current —regional limit,

includes sum of negative injection currents or sum of

positive injection currents of 16 contiguous pins

-25

—

mA

• Negative current injection

• Positive current injection

+25

Table continues on the next page...

26

NXP Semiconductors

MKW2xD Data Sheet, Rev. 2, 05/2016

MCU Electrical characteristics

Table 7. Voltage and current operating requirements (continued)

Symbol

Description

Min.

1.2

Max.

—

Unit

V

Notes

V_RAM

V_DDvoltage required to retain RAM

V_RFVBATV_BATvoltage required to retain the VBAT register file

V_{POR_VBAT}

—

V

1. All analog pins are internally clamped to V_SSand V_DDthrough ESD protection diodes. If V_INis less than V_{AIO_MIN}or

greater than V_{AIO_MAX}, a current limiting resistor is required. The negative DC injection current limiting resistor is

calculated as R=(V_{AIO_MIN}-V_IN)/|I_ICAIO|. The positive injection current limiting resistor is calculated as R=(V_IN-

V_{AIO_MAX})/|I_ICAIO|. Select the larger of these two calculated resistances if the pin is exposed to positive and negative

injection currents.

7.3.2 LVD and POR operating requirements

Table 8. V_DDsupply LVD and POR operating requirements

Symbol Description

Min.

0.8

Typ.

1.1

Max.

1.5

Unit

V

Notes

V_POR

Falling VDD POR detect voltage

V_LVDH

Falling low-voltage detect threshold — high

range (LVDV=01)

2.48

2.56

2.64

V

Low-voltage warning thresholds — high range

• Level 1 falling (LVWV=00)

1

V_LVW1H

V_LVW2H

V_LVW3H

V_LVW4H

2.62

2.72

2.82

2.92

2.70

2.80

2.90

3.00

2.78

2.88

2.98

3.08

V

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

V_HYSH

V_LVDL

Low-voltage inhibit reset/recover hysteresis —

high range

—

80

—

mV

V

Falling low-voltage detect threshold — low

range (LVDV=00)

1.54

1.60

1.66

Low-voltage warning thresholds — low range

• Level 1 falling (LVWV=00)

1

V_LVW1L

V_LVW2L

V_LVW3L

V_LVW4L

1.74

1.84

1.94

2.04

1.80

1.90

2.00

2.10

1.86

1.96

2.06

2.16

V

• Level 2 falling (LVWV=01)

• Level 3 falling (LVWV=10)

• Level 4 falling (LVWV=11)

V_HYSL

Low-voltage inhibit reset/recover hysteresis —

low range

—

60

—

mV

V_BG

t_LPO

Bandgap voltage reference

0.97

900

1.00

1.03

V

Internal low power oscillator period — factory

trimmed

1000

1100

μs

MKW2xD Data Sheet, Rev. 2, 05/2016

27

NXP Semiconductors

MCU Electrical characteristics

1. Rising threshold is the sum of falling threshold and hysteresis voltage

Table 9. VBAT power operating requirements

Symbol Description

Min.

Typ.

Max.

Unit

Notes

V_{POR_VBAT}Falling VBAT supply POR detect voltage

0.8

1.1

1.5

V

7.3.3 Voltage and current operating behaviors

Table 10. Voltage and current operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

V_OH

Output high voltage — high drive strength

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= - 9 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OH= -3 mA

V_DD– 0.5

—

V

Output high voltage — low drive strength

• 2.7 V ≤ V_DD≤ 3.6 V, I_OH= -2 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OH= -0.6 mA

V_DD– 0.5

—

V

I_OHT

V_OL

Output high current total for all ports

Output low voltage — high drive strength

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 9 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OL= 3 mA

—

100

mA

—

0.5

V

Output low voltage — low drive strength

• 2.7 V ≤ V_DD≤ 3.6 V, I_OL= 2 mA

• 1.71 V ≤ V_DD≤ 2.7 V, I_OL= 0.6 mA

—

0.5

V

I_OLT

I_IN

Output low current total for all ports

Input leakage current (per pin)

• @ full temperature range

• @ 25 °C

—

100

mA

—

1.0

0.1

μA

1

I_OZ

Hi-Z (off-state) leakage current (per pin)

Total Hi-Z (off-state) leakage current (all input pins)

Internal pullup resistors

—

22

1

4

μA

kΩ

R_PU

R_PD

50

2

3

Internal pulldown resistors

1. Tested by ganged leakage method

2. Measured at Vinput = V_SS

3. Measured at Vinput = V_DD

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NXP Semiconductors

MCU Electrical characteristics

7.3.4 Power mode transition operating behaviors

All specifications except t_POR, and VLLSx→RUN recovery times in the following

table assume this clock configuration:

• CPU and system clocks = 50 MHz

• Bus clock = 50 MHz

• Flash clock = 25 MHz

• MCG mode: FEI

Table 11. Power mode transition operating behaviors

Symbol

Description

Min.

Max.

Unit

Notes

t_POR

After a POR event, amount of time from the point

V_DDreaches 1.71 V to execution of the first

instruction across the operating temperature range

of the chip.

μs

1

—

300

1.7 V / (V_DD

slew rate)

• 1.71 V/(V_DDslew rate) ≤ 300 μs

• 1.71 V/(V_DDslew rate) > 300 μs

—

150

79

6

μs

• VLLS1 → RUN

• VLLS2 → RUN

• VLLS3 → RUN

• LLS → RUN

5.2

• VLPS → RUN

• STOP → RUN

1. Normal boot (FTFL_OPT[LPBOOT]=1)

7.3.5 Power consumption operating behaviors

Table 12. Power consumption operating behaviors

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_DDA

Analog supply current

—

See note

mA

1

2

I_{DD_RUN}Run mode current — all peripheral clocks

disabled, code executing from flash

• @ 1.8 V

• @ 3.0 V

—

12.98

12.93

14

mA

13.8

Table continues on the next page...

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29

NXP Semiconductors

MCU Electrical characteristics

Table 12. Power consumption operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

I_{DD_RUN}Run mode current — all peripheral clocks

enabled, code executing from flash

3, 4

• @ 1.8 V

• @ 3.0 V

• @ 25°C

• @ 125°C

—

17.04

19.3

mA

—

17.01

19.8

7.95

18.9

21.3

9.5

mA

I_{DD_WAIT}Wait mode high frequency current at 3.0 V —

all peripheral clocks disabled

2

5

I_{DD_WAIT}Wait mode reduced frequency current at 3.0 V

— all peripheral clocks disabled

—

5.88

7.4

mA

μA

I_{DD_STOP}Stop mode current at 3.0 V

• @ –40 to 25°C

• @ 50°C

320

360

410

610

754

436

489

620

1100

—

• @ 70°C

• @ 105°C

I_{DD_VLPR}Very-low-power run mode current at 3.0 V —

all peripheral clocks disabled

—

μA

6

7

8

I_{DD_VLPR}Very-low-power run mode current at 3.0 V —

all peripheral clocks enabled

1.1

—

mA

I_{DD_VLPW}Very-low-power wait mode current at 3.0 V

—

437

μA

I_{DD_VLPS}Very-low-power stop mode current at 3.0 V

7.33

14

24.2

32

• @ –40 to 25°C

• @ 50°C

• @ 70°C

• @ 105°C

28

48

110

280

I_{DD_LLS}Low leakage stop mode current at 3.0 V

—

μA

3.14

6.48

4.8

• @ –40 to 25°C

• @ 50°C

• @ 70°C

28.3

44.6

71.3

13.85

55.53

• @ 105°C

I_{DD_VLLS3}Very low-leakage stop mode 3 current at 3.0 V

—

2.19

4.35

3.4

• @ –40 to 25°C

• @ 50°C

• @ 70°C

4.35

24.6

45.3

8.92

• @ 105°C

35.33

I_{DD_VLLS2}Very low-leakage stop mode 2 current at 3.0 V

1.77

2.81

3.1

• @ –40 to 25°C

• @ 50°C

• @ 70°C

13.8

22.3

34.2

5.20

• @ 105°C

19.88

I_{DD_VLLS1}Very low-leakage stop mode 1 current at 3.0 V

• @ –40 to 25°C

—

1.03

1.8

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NXP Semiconductors

MCU Electrical characteristics

Table 12. Power consumption operating behaviors (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

• @ 50°C

• @ 70°C

• @ 105°C

1.92

7.5

4.03

15.9

28.7

17.43

I_{DD_VLLS0}Very low-leakage stop mode 0 current at 3.0 V

—

μA

0.543

1.36

1.1

with POR detect circuit enabled

• @ –40 to 25°C

• @ 50°C

7.58

14.3

24.1

3.39

• @ 70°C

• @ 105°C

16.52

I_{DD_VLLS0}Very low-leakage stop mode 0 current at 3.0 V

—

μA

0.359

1.03

0.95

6.8

with POR detect circuit disabled

• @ –40 to 25°C

• @ 50°C

2.87

15.4

25.3

• @ 70°C

• @ 105°C

15.20

I_{DD_VBAT}Average current when CPU is not accessing

9

0.91

1.1

1.5

4.3

1.1

1.35

1.85

5.7

RTC registers at 3.0 V

• @ –40 to 25°C

• @ 50°C

• @ 70°C

• @ 105°C

1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device.

See each module's specification for its supply current.

2. 50 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All

peripheral clocks disabled.

3. 50 MHz core and system clock, 25 MHz bus clock, and 25 MHz flash clock. MCG configured for FEI mode. All

peripheral clocks enabled, and peripherals are in active operation.

4. Max values are measured with CPU executing DSP instructions

5. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz flash clock. MCG configured for FEI mode.

6. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks

disabled. Code executing from flash.

7. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks

enabled but peripherals are not in active operation. Code executing from flash.

8. 4 MHz core, system, and bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All peripheral clocks

disabled.

9. Includes 32 kHz oscillator current and RTC operation.

7.3.5.1 Diagram: Typical IDD_RUN operating behavior

The following data was measured under these conditions:

• MCG in FBE mode

• No GPIOs toggled

• Code execution from flash with cache enabled

• For the ALLOFF curve, all peripheral clocks are disabled except FTFL

MKW2xD Data Sheet, Rev. 2, 05/2016

31

NXP Semiconductors

MCU Electrical characteristics

Figure 5. Run mode supply current vs. core frequency

32

MKW2xD Data Sheet, Rev. 2, 05/2016

NXP Semiconductors

MCU Electrical characteristics

Figure 6. VLPR mode supply current vs. core frequency

7.3.6 EMC radiated emissions operating behaviors

Table 13. EMC radiated emissions operating behaviors 1

Symbol

Description

Frequency

band

Typ.

Unit

Notes

(MHz)

V_RE1

V_RE2

Radiated emissions voltage, band 1

Radiated emissions voltage, band 2

Radiated emissions voltage, band 3

Radiated emissions voltage, band 4

IEC level

0.15–50

50–150

19

21

19

11

L

dBμV

—

2, 3

V_RE3

150–500

500–1000

0.15–1000

V_RE4

V_{RE_IEC}

3, 4

1. This data was collected on a MK20DN128VLH5 64pin LQFP device.

2. Determined according to IEC Standard 61967-1, Integrated Circuits - Measurement of Electromagnetic Emissions,

150 kHz to 1 GHz Part 1: General Conditions and Definitions and IEC Standard 61967-2, Integrated Circuits -

Measurement of Electromagnetic Emissions, 150 kHz to 1 GHz Part 2: Measurement of Radiated Emissions—TEM

Cell and Wideband TEM Cell Method. Measurements were made while the microcontroller was running basic

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NXP Semiconductors

MCU Electrical characteristics

application code. The reported emission level is the value of the maximum measured emission, rounded up to the next

whole number, from among the measured orientations in each frequency range.

3. V_DD= 3.3 V, T_A= 25 °C, f_OSC= 12 MHz (crystal), f_SYS= 48 MHz, f_BUS= 48MHz

4. Specified according to Annex D of IEC Standard 61967-2, Measurement of Radiated Emissions—TEM Cell and

Wideband TEM Cell Method

7.3.7 Designing with radiated emissions in mind

To find application notes that provide guidance on designing your system to minimize

interference from radiated emissions:

• Go to www.nxp.com.

• Perform a keyword search for “EMC design.”

7.3.8 Capacitance attributes

Table 14. Capacitance attributes

Symbol

C_{IN_A}

Description

Min.

—

Max.

Unit

pF

Input capacitance: analog pins

Input capacitance: digital pins

7

C_{IN_D}

—

pF

7.4 Switching specifications

7.4.1 Device clock specifications

Table 15. Device clock specifications

Symbol

Description

Min.

Max.

Unit

Notes

Normal run mode

f_SYS

System and core clock

—

50

—

MHz

System and core clock when Full Speed USB in

operation

20

f_BUS

Bus clock

—

50

25

MHz

f_FLASH

f_LPTMR

Flash clock

LPTMR clock

VLPR mode¹

f_SYS

f_BUS

System and core clock

Bus clock

—

4

MHz

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MCU Electrical characteristics

Table 15. Device clock specifications (continued)

Symbol

f_FLASH

Description

Min.

—

Max.

1

Unit

MHz

Notes

Flash clock

f_ERCLK

External reference clock

LPTMR clock

—

16

f_{LPTMR_pin}

—

25

f_{LPTMR_ERCLK}LPTMR external reference clock

—

16

f_{I2S_MCLK}

f_{I2S_BCLK}

I2S master clock

I2S bit clock

—

12.5

4

—

1. The frequency limitations in VLPR mode here override any frequency specification listed in the timing specification for

any other module.

7.4.2 General switching specifications

These general purpose specifications apply to all pins configured for:

• GPIO signaling

• Other peripheral module signaling not explicitly stated elsewhere

Table 16. General switching specifications

Symbol

Description

Min.

Max.

Unit

Notes

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

1.5

—

Bus clock

cycles

1, 2

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter enabled) — Asynchronous

path

100

50

—

ns

3

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter disabled) — Asynchronous

path

External reset pulse width (digital glitch filter

disabled)

100

3

4

Port rise and fall time (high drive strength)

• Slew disabled

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

—

13

7

ns

• Slew enabled

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

—

36

24

ns

Port rise and fall time (low drive strength)

• Slew disabled

5

—

12

6

ns

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MCU Electrical characteristics

Table 16. General switching specifications

Symbol

Description

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

• Slew enabled

Min.

Max.

Unit

Notes

—

36

24

ns

• 1.71 ≤ V_DD≤ 2.7V

• 2.7 ≤ V_DD≤ 3.6V

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may

or may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can

be recognized in that case.

2. The greater synchronous and asynchronous timing must be met.

3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and

VLLSx modes.

4. 75 pF load

5. 15 pF load

7.5 Thermal specifications

7.5.1 Thermal operating requirements

Table 17. Thermal operating requirements

Symbol

T_J

Description

Min.

–40

Max.

125

Unit

°C

Die junction temperature

Ambient temperature¹

T_A

105

°C

1. Maximum T_Acan be exceeded only if the user ensures that T_Jdoes not exceed maximum T_J. The simplest method to

determine T_Jis:

T_J= T_A+ R_θJAx chip power dissipation

7.5.2 Thermal attributes

Board type

Symbol

Description

80 LQFP

Unit

Notes

Single-layer (1s)

R_θJA

Thermal

resistance,

junction to ambient

(natural

convection)

50

35

°C/W

1, 2

1, 3

Four-layer (2s2p) R_θJA

Thermal

resistance,

junction to ambient

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MCU Electrical characteristics

Board type

Symbol

Description

80 LQFP

Unit

Notes

(natural

convection)

Single-layer (1s)

R_θJMA

Thermal

resistance,

junction to ambient

(200 ft./min. air

speed)

39

29

°C/W

1,3

Four-layer (2s2p) R_θJMA

Thermal

resistance,

junction to ambient

(200 ft./min. air

speed)

—

R_θJB

R_θJC

Ψ_JT

Thermal

resistance,

junction to board

19

8

°C/W

4

5

6

Thermal

resistance,

junction to case

Thermal

2

characterization

parameter,

junction to

package top

outside center

(natural

convection)

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

2. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air) with the single layer board horizontal. For the LQFP, the board meets the

JESD51-3 specification. For the MAPBGA, the board meets the JESD51-9 specification.

3. Determined according to JEDEC Standard JESD51-6, Integrated Circuits Thermal Test Method Environmental

Conditions—Forced Convection (Moving Air) with the board horizontal.

4. Determined according to JEDEC Standard JESD51-8, Integrated Circuit Thermal Test Method Environmental

Conditions—Junction-to-Board. Board temperature is measured on the top surface of the board near the package.

5. Determined according to Method 1012.1 of MIL-STD 883, Test Method Standard, Microcircuits, with the cold plate

temperature used for the case temperature. The value includes the thermal resistance of the interface material

between the top of the package and the cold plate.

6. Determined according to JEDEC Standard JESD51-2, Integrated Circuits Thermal Test Method Environmental

Conditions—Natural Convection (Still Air).

7.6 Peripheral operating requirements and behaviors

7.6.1 Core modules

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7.6.1.1 JTAG electricals

Table 18. JTAG limited voltage range electricals

Symbol

Description

Min.

Max.

Unit

V

Operating voltage

2.7

3.6

J1

TCLK frequency of operation

• Boundary Scan

MHz

0

10

25

50

• JTAG and CJTAG

• Serial Wire Debug

J2

J3

TCLK cycle period

TCLK clock pulse width

• Boundary Scan

1/J1

—

ns

50

20

10

—

ns

• JTAG and CJTAG

• Serial Wire Debug

J4

J5

TCLK rise and fall times

—

20

0

3

ns

Boundary scan input data setup time to TCLK rise

Boundary scan input data hold time after TCLK rise

TCLK low to boundary scan output data valid

TCLK low to boundary scan output high-Z

TMS, TDI input data setup time to TCLK rise

TMS, TDI input data hold time after TCLK rise

TCLK low to TDO data valid

—

25

—

17

—

J6

J7

—

8

J8

J9

J10

J11

J12

J13

J14

1

—

100

8

TCLK low to TDO high-Z

TRST assert time

TRST setup time (negation) to TCLK high

Table 19. JTAG full voltage range electricals

Symbol

Description

Min.

Max.

Unit

V

Operating voltage

1.8

3.6

J1

TCLK frequency of operation

• Boundary Scan

MHz

0

10

20

40

• JTAG and CJTAG

• Serial Wire Debug

J2

J3

TCLK cycle period

TCLK clock pulse width

• Boundary Scan

1/J1

—

ns

50

25

—

ns

• JTAG and CJTAG

• Serial Wire Debug

12.5

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Table 19. JTAG full voltage range electricals (continued)

Symbol

J4

Description

Min.

—

20

0

Max.

3

Unit

ns

TCLK rise and fall times

J5

Boundary scan input data setup time to TCLK rise

Boundary scan input data hold time after TCLK rise

TCLK low to boundary scan output data valid

TCLK low to boundary scan output high-Z

TMS, TDI input data setup time to TCLK rise

TMS, TDI input data hold time after TCLK rise

TCLK low to TDO data valid

—

J6

—

J7

—

8

25

J8

25

J9

—

J10

J11

J12

J13

J14

1.4

—

100

8

—

22.1

—

TCLK low to TDO high-Z

TRST assert time

TRST setup time (negation) to TCLK high

—

J2

J4

J3

TCLK (input)

J4

Figure 7. Test clock input timing

TCLK

J5

J6

Input data valid

Data inputs

Data outputs

J7

Output data valid

J8

J7

Output data valid

Figure 8. Boundary scan (JTAG) timing

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MCU Electrical characteristics

TCLK

TDI/TMS

TDO

J9

J10

Input data valid

J11

Output data valid

J12

J11

TDO

Output data valid

TDO

Figure 9. Test Access Port timing

TCLK

J14

J13

TRST

Figure 10. TRST timing

7.6.2 System modules

There are no specifications necessary for the device's system modules.

7.6.3 Clock modules

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MCU Electrical characteristics

7.6.3.1 MCG specifications

Table 20. MCG specifications

Symbol Description

Min.

Typ.

Max.

Unit

Notes

f_{ints_ft}Internal reference frequency (slow clock) —

—

32.768

—

kHz

factory trimmed at nominal VDD and 25 °C

f_{ints_t}

Internal reference frequency (slow clock) —

user trimmed

31.25

—

39.0625

0.6

kHz

Δ_{fdco_res_t}Resolution of trimmed average DCO output

frequency at fixed voltage and temperature —

using SCTRIM and SCFTRIM

0.3

%f_dco

1

Δf_{dco_res_t}Resolution of trimmed average DCO output

frequency at fixed voltage and temperature —

using SCTRIM only

—

0.2

0.5

%f_dco

Δf_{dco_t}

Total deviation of trimmed average DCO output

frequency over voltage and temperature

—

+0.5/-0.7

0.3

2

1

%f_dco

1, 2

Δf_{dco_t}

Total deviation of trimmed average DCO output

frequency over fixed voltage and temperature

range of 0–70°C

f_{intf_ft}

f_{intf_t}

Internal reference frequency (fast clock) —

factory trimmed at nominal VDD and 25°C

—

3

4

—

5

MHz

kHz

Internal reference frequency (fast clock) —

user trimmed at nominal VDD and 25 °C

—

f_{loc_low}

Loss of external clock minimum frequency —

RANGE = 00

(3/5) x

f_{ints_t}

—

f_{loc_high}Loss of external clock minimum frequency —

RANGE = 01, 10, or 11

(16/5) x

f_{ints_t}

FLL

f_{fll_ref}

f_dco

FLL reference frequency range

31.25

20

—

39.0625

25

kHz

DCO output

Low range (DRS=00)

20.97

MHz

3, 4

frequency range

640 × f_{fll_ref}

Mid range (DRS=01)

1280 × f_{fll_ref}

40

60

80

—

41.94

62.91

83.89

23.99

47.97

71.99

95.98

50

75

100

—

MHz

Mid-high range (DRS=10)

1920 × f_{fll_ref}

High range (DRS=11)

2560 × f_{fll_ref}

f_{dco_t_DMX3}DCO output

Low range (DRS=00)

732 × f_{fll_ref}

5,6

frequency

2

Mid range (DRS=01)

1464 × f_{fll_ref}

—

Mid-high range (DRS=10)

2197 × f_{fll_ref}

—

High range (DRS=11)

—

Table continues on the next page...

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MCU Electrical characteristics

Symbol Description

Table 20. MCG specifications (continued)

Min.

Typ.

Max.

Unit

Notes

2929 × f_{fll_ref}

J_{cyc_fll}

FLL period jitter

ps

—

180

150

—

• f_DCO= 48 MHz

• f_DCO= 98 MHz

t_{fll_acquire}FLL target frequency acquisition time

—

1

ms

7

PLL

f_vco

I_pll

VCO operating frequency

48.0

—

100

—

MHz

µA

PLL operating current

8

1200

• PLL @ 96 MHz (f_{osc_hi_1}= 8 MHz, f_{pll_ref}

= 2 MHz, VDIV multiplier = 48)

I_pll

PLL operating current

—

700

—

µA

• PLL @ 48 MHz (f_{osc_hi_1}= 8 MHz, f_{pll_ref}

= 2 MHz, VDIV multiplier = 24)

f_{pll_ref}

PLL reference frequency range

PLL period jitter (RMS)

• f_vco= 48 MHz

2.0

4.0

MHz

J_{cyc_pll}

9

—

120

75

—

ps

• f_vco= 100 MHz

J_{acc_pll}

PLL accumulated jitter over 1µs (RMS)

• f_vco= 48 MHz

—

1350

600

—

ps

• f_vco= 100 MHz

D_lock

D_unl

Lock entry frequency tolerance

Lock exit frequency tolerance

Lock detector detection time

1.49

4.47

—

2.98

5.97

150 × 10^-6

+ 1075(1/

%

s

t_{pll_lock}

10

f_{pll_ref}

)

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock

mode).

2. 2 V <= VDD <= 3.6 V.

3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.

4. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency

deviation (Δf_{dco_t}) over voltage and temperature should be considered.

5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.

6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.

7. This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,

DMX32 bit is changed, DRS bits are changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,

FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.

8. Excludes any oscillator currents that are also consuming power while PLL is in operation.

9. This specification was obtained using a Freescale developed PCB. PLL jitter is dependent on the noise characteristics of

each PCB and results will vary.

10. This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL

disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this

specification assumes it is already running.

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MCU Electrical characteristics

7.6.3.2 Oscillator electrical specifications

7.6.3.2.1 Oscillator DC electrical specifications

Table 21. Oscillator DC electrical specifications

Symbol Description

V_DDSupply voltage

Min.

Typ.

Max.

Unit

Notes

1.8

—

3.6

V

I_DDOSCSupply current — low-power mode (HGO=0)

1

• 32 kHz

—

500

200

300

950

1.2

—

nA

μA

mA

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

• 24 MHz

• 32 MHz

1.5

I_DDOSCSupply current — high-gain mode (HGO=1)

1

• 32 kHz

—

5

500

600

2.5

3

—

μA

• 4 MHz

• 8 MHz (RANGE=01)

• 16 MHz

μA

mA

• 24 MHz

• 32 MHz

4

C_x

C_y

R_F

EXTAL load capacitance

XTAL load capacitance

—

2, 3

2, 4

Feedback resistor — low-frequency, low-power

mode (HGO=0)

MΩ

kΩ

Feedback resistor — low-frequency, high-gain

mode (HGO=1)

—

10

—

Feedback resistor — high-frequency, low-

power mode (HGO=0)

Feedback resistor — high-frequency, high-gain

mode (HGO=1)

1

R_S

Series resistor — low-frequency, low-power

mode (HGO=0)

—

Series resistor — low-frequency, high-gain

mode (HGO=1)

200

—

kΩ

Series resistor — high-frequency, low-power

mode (HGO=0)

kΩ

Series resistor — high-frequency, high-gain

mode (HGO=1)

—

0

—

kΩ

Table continues on the next page...

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MCU Electrical characteristics

Table 21. Oscillator DC electrical specifications (continued)

Symbol Description

Min.

Typ.

Max.

Unit

Notes

5

V_pp

Peak-to-peak amplitude of oscillation (oscillator

—

0.6

—

V

mode) — low-frequency, low-power mode

(HGO=0)

Peak-to-peak amplitude of oscillation (oscillator

mode) — low-frequency, high-gain mode

(HGO=1)

—

V_DD

0.6

—

V

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, low-power mode

(HGO=0)

Peak-to-peak amplitude of oscillation (oscillator

mode) — high-frequency, high-gain mode

(HGO=1)

V_DD

1. V_DD=3.3 V, Temperature =25 °C

2. See crystal or resonator manufacturer's recommendation

3. C_xand C_ycan be provided by using either integrated capacitors or external components.

4. When low-power mode is selected, R_Fis integrated and must not be attached externally.

5. The EXTAL and XTAL pins should only be connected to required oscillator components and must not be connected to

any other device.

7.6.3.2.2 Oscillator frequency specifications

Table 22. Oscillator frequency specifications

Symbol Description

f_{osc_lo}Oscillator crystal or resonator frequency — low-

frequency mode (MCG_C2[RANGE]=00)

Min.

Typ.

Max.

Unit

Notes

32

—

40

kHz

f_{osc_hi_1}Oscillator crystal or resonator frequency — high-

frequency mode (low range)

3

8

—

8

MHz

(MCG_C2[RANGE]=01)

f_{osc_hi_2}Oscillator crystal or resonator frequency — high

frequency mode (high range)

32

(MCG_C2[RANGE]=1x)

f_{ec_extal}Input clock frequency (external clock mode)

t_{dc_extal}Input clock duty cycle (external clock mode)

—

40

—

50

60

—

MHz

%

1, 2

3, 4

t_cst

Crystal startup time — 32 kHz low-frequency,

low-power mode (HGO=0)

750

ms

Crystal startup time — 32 kHz low-frequency,

high-gain mode (HGO=1)

—

250

0.6

—

ms

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), low-power mode

(HGO=0)

Crystal startup time — 8 MHz high-frequency

(MCG_C2[RANGE]=01), high-gain mode

(HGO=1)

—

1

—

ms

1. Other frequency limits may apply when external clock is being used as a reference for the FLL or PLL.

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MCU Electrical characteristics

2. When transitioning from FEI or FBI to FBE mode, restrict the frequency of the input clock so that, when it is divided by

FRDIV, it remains within the limits of the DCO input clock frequency.

3. Proper PC board layout procedures must be followed to achieve specifications.

4. Crystal startup time is defined as the time between the oscillator being enabled and the OSCINIT bit in the MCG_S

register being set.

NOTE

The 32 kHz oscillator works in low power mode by default

and cannot be moved into high power/gain mode.

7.6.3.3 32 kHz oscillator electrical characteristics

7.6.3.3.1 32 kHz oscillator DC electrical specifications

Table 23. 32kHz oscillator DC electrical specifications

Symbol

V_BAT

R_F

Description

Min.

1.8

—

Typ.

—

Max.

3.6

—

Unit

V

Supply voltage

Internal feedback resistor

100

5

MΩ

pF

C_para

Parasitical capacitance of EXTAL32 and

XTAL32

—

7

1

V_pp

Peak-to-peak amplitude of oscillation

—

0.6

—

V

1. When a crystal is being used with the 32 kHz oscillator, the EXTAL32 and XTAL32 pins should only be connected to

required oscillator components and must not be connected to any other devices.

7.6.3.3.2 32 kHz oscillator frequency specifications

Table 24. 32 kHz oscillator frequency specifications

Symbol Description

Min.

—

Typ.

32.768

1000

—

Max.

—

Unit

kHz

ms

Notes

f_{osc_lo}

t_start

Oscillator crystal

Crystal start-up time

—

1

v_{ec_extal32}Externally provided input clock amplitude

700

V_BAT

mV

2, 3

1. Proper PC board layout procedures must be followed to achieve specifications.

2. This specification is for an externally supplied clock driven to EXTAL32 and does not apply to any other clock input.

The oscillator remains enabled and XTAL32 must be left unconnected.

3. The parameter specified is a peak-to-peak value and V_IHand V_ILspecifications do not apply. The voltage of the

applied clock must be within the range of V_SSto V_BAT

.

7.6.4 Memories and memory interfaces

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7.6.4.1 Flash electrical specifications

This section describes the electrical characteristics of the flash memory module.

7.6.4.1.1 Flash timing specifications — program and erase

The following specifications represent the amount of time the internal charge pumps are

active and do not include command overhead.

Table 25. NVM program/erase timing specifications

Symbol Description

Min.

—

Typ.

7.5

Max.

18

Unit

μs

Notes

t_hvpgm4

Longword Program high-voltage time

—

1

t_hversscrSector Erase high-voltage time

t_hversblk256kErase Block high-voltage time for 256 KB

—

13

113

904

ms

—

104

1

1. Maximum time based on expectations at cycling end-of-life.

7.6.4.1.2 Flash timing specifications — commands

Table 26. Flash command timing specifications

Symbol Description

Read 1s Block execution time

Min.

Typ.

Max.

Unit

Notes

1

t_rd1blk64k

• 64 KB data flash

—

0.9

1.7

ms

t_rd1blk256k

• 256 KB program flash

t_rd1sec2kRead 1s Section execution time (flash sector)

—

65

60

45

μs

1

t_pgmchk

t_rdrsrc

Program Check execution time

Read Resource execution time

Program Longword execution time

Erase Flash Block execution time

• 64 KB data flash

30

1

t_pgm4

145

—

2

t_ersblk64k

—

58

580

985

ms

t_ersblk256k

• 256 KB program flash

122

t_ersscr

Erase Flash Sector execution time

Program Section execution time

• 512 bytes flash

—

14

114

ms

2

—

t_pgmsec512

t_pgmsec1k

t_pgmsec2k

—

2.4

4.7

9.3

—

ms

• 1 KB flash

• 2 KB flash

t_rd1all

Read 1s All Blocks execution time

Read Once execution time

—

1.8

25

ms

μs

1

t_rdonce

Table continues on the next page...

46

NXP Semiconductors

MKW2xD Data Sheet, Rev. 2, 05/2016

MCU Electrical characteristics

Table 26. Flash command timing specifications (continued)

Symbol Description

Min.

—

Typ.

65

Max.

—

Unit

μs

Notes

t_pgmonceProgram Once execution time

—

2

t_ersall

Erase All Blocks execution time

Verify Backdoor Access Key execution time

Swap Control execution time

• control code 0x01

—

250

—

2000

30

ms

μs

t_vfykey

—

1

—

t_swapx01

t_swapx02

t_swapx04

t_swapx08

—

200

70

—

150

30

μs

• control code 0x02

• control code 0x04

• control code 0x08

Program Partition for EEPROM execution time

• 64 KB FlexNVM

—

t_pgmpart64k

—

138

—

ms

Set FlexRAM Function execution time:

• Control Code 0xFF

t_setramff

t_setram32k

t_setram64k

—

70

0.8

1.3

—

μs

ms

• 32 KB EEPROM backup

• 64 KB EEPROM backup

1.2

1.9

Byte-write to FlexRAM for EEPROM operation

t_eewr8bersByte-write to erased FlexRAM location

execution time

—

175

260

μs

3

Byte-write to FlexRAM execution time:

—

t_eewr8b32k

t_eewr8b64k

• 32 KB EEPROM backup

• 64 KB EEPROM backup

—

385

475

1800

2000

μs

Word-write to FlexRAM for EEPROM operation

t_eewr16bersWord-write to erased FlexRAM location

execution time

—

175

260

μs

—

Word-write to FlexRAM execution time:

t_eewr16b32k

t_eewr16b64k

• 32 KB EEPROM backup

• 64 KB EEPROM backup

—

385

475

1800

2000

μs

Longword-write to FlexRAM for EEPROM operation

t_eewr32bersLongword-write to erased FlexRAM location

execution time

—

360

540

μs

—

Longword-write to FlexRAM execution time:

t_eewr32b32k

t_eewr32b64k

• 32 KB EEPROM backup

• 64 KB EEPROM backup

—

630

810

2050

2250

μs

1. Assumes 25 MHz flash clock frequency.

2. Maximum times for erase parameters based on expectations at cycling end-of-life.

3. For byte-writes to an erased FlexRAM location, the aligned word containing the byte must be erased.

MKW2xD Data Sheet, Rev. 2, 05/2016

47

NXP Semiconductors

MCU Electrical characteristics

7.6.4.1.3 Flash high voltage current behaviors

Table 27. Flash high voltage current behaviors

Symbol

Description

Min.

Typ.

Max.

Unit

I_{DD_PGM}

Average current adder during high voltage

flash programming operation

—

2.5

6.0

mA

I_{DD_ERS}

Average current adder during high voltage

flash erase operation

—

1.5

4.0

mA

7.6.4.1.4 Reliability specifications

Table 28. NVM reliability specifications

Symbol Description

Min.

Program Flash

Typ.¹

Max.

Unit

Notes

t_nvmretp10kData retention after up to 10 K cycles

t_nvmretp1kData retention after up to 1 K cycles

n_nvmcycpCycling endurance

5

50

—

years

cycles

—

2

20

100

50 K

10 K

Data Flash

t_nvmretd10kData retention after up to 10 K cycles

t_nvmretd1kData retention after up to 1 K cycles

n_nvmcycdCycling endurance

5

50

—

years

cycles

—

2

20

10 K

100

50 K

FlexRAM as EEPROM

t_nvmretee100Data retention up to 100% of write endurance

t_nvmretee10Data retention up to 10% of write endurance

Write endurance

5

50

—

years

—

3

20

100

n_nvmwree16

n_nvmwree128

n_nvmwree512

n_nvmwree4k

• EEPROM backup to FlexRAM ratio = 16

• EEPROM backup to FlexRAM ratio = 128

• EEPROM backup to FlexRAM ratio = 512

35 K

315 K

1.27 M

10 M

175 K

1.6 M

6.4 M

50 M

—

writes

• EEPROM backup to FlexRAM ratio =

4096

1. Typical data retention values are based on measured response accelerated at high temperature and derated to a

constant 25 °C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in

Engineering Bulletin EB619.

2. Cycling endurance represents number of program/erase cycles at –40 °C ≤ T_j≤ °C.

3. Write endurance represents the number of writes to each FlexRAM location at –40 °C ≤Tj ≤ °C influenced by the cycling

endurance of the FlexNVM (same value as data flash) and the allocated EEPROM backup per subsystem. Minimum and

typical values assume all byte-writes to FlexRAM.

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MCU Electrical characteristics

7.6.4.2 EzPort switching specifications

Table 29. EzPort switching specifications

Num

Description

Min.

1.8

—

Max.

3.6

Unit

V

Operating voltage

EP1

EZP_CK frequency of operation (all commands except

READ)

f_SYS/2

MHz

EP1a

EP2

EP3

EP4

EP5

EP6

EP7

EP8

EP9

EZP_CK frequency of operation (READ command)

EZP_CS negation to next EZP_CS assertion

EZP_CS input valid to EZP_CK high (setup)

EZP_CK high to EZP_CS input invalid (hold)

EZP_D input valid to EZP_CK high (setup)

EZP_CK high to EZP_D input invalid (hold)

EZP_CK low to EZP_Q output valid

—

f_SYS/8

—

MHz

ns

2 x t_{EZP_CK}

5

—

ns

—

ns

2

—

ns

5

—

ns

—

0

ns

EZP_CK low to EZP_Q output invalid (hold)

EZP_CS negation to EZP_Q tri-state

—

ns

—

12

ns

EZP_CK

EP2

EP3

EP4

EZP_CS

EP9

EP8

EP7

EZP_Q (output)

EZP_D (input)

EP5

EP6

Figure 11. EzPort Timing Diagram

7.6.5 Security and integrity modules

MKW2xD Data Sheet, Rev. 2, 05/2016

49

NXP Semiconductors

MCU Electrical characteristics

7.6.5.1 DryIce Tamper Electrical Specifications

Information about security-related modules is not included in this document and is

available only after a nondisclosure agreement (NDA) has been signed. To request an

NDA, contact your local NXP sales representative.

7.6.6 Analog

7.6.6.1 ADC electrical specifications

The 16-bit accuracy specifications listed in Table 1 and Table 31 are achievable on the

differential pins ADCx_DP0, ADCx_DM0.

All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy

specifications.

7.6.6.1.1 16-bit ADC operating conditions

Table 30. 16-bit ADC operating conditions

Symbol Description

Conditions

Min.

1.8

Typ.¹

Max.

3.6

Unit

V

Notes

V_DDA

ΔV_DDA

ΔV_SSA

V_REFH

Supply voltage

Absolute

—

Delta to V_DD(V_DD– V_DDA

)

-100

V_DDA

0

+100

V_DDA

mV

V

2

3

Ground voltage Delta to V_SS(V_SS– V_SSA

)

0

ADC reference

voltage high

Absolute

V_DDA

V_REFL

V_ADIN

ADC reference

voltage low

Absolute

V_SSA

V

4

Input voltage

• 16-bit differential mode

• All other modes

• 16-bit mode

VREFL

—

31/32 *

VREFH

C_ADIN

Input

capacitance

—

8

4

10

5

pF

kΩ

• 8-bit / 10-bit / 12-bit

modes

R_ADIN

R_AS

Input series

resistance

—

2

5

Analog source

resistance

(external)

13-bit / 12-bit modes

f_ADCK< 4 MHz

5

6

—

5

kΩ

f_ADCK

ADC conversion ≤ 13-bit mode

clock frequency

1.0

18.0

MHz

Table continues on the next page...

50

NXP Semiconductors

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MCU Electrical characteristics

Table 30. 16-bit ADC operating conditions (continued)

Symbol Description

Conditions

Min.

Typ.¹

Max.

Unit

Notes

f_ADCK

ADC conversion 16-bit mode

clock frequency

2.0

—

12.0

MHz

6

C_rate

ADC conversion ≤ 13-bit modes

rate

7

No ADC hardware averaging

20.000

37.037

—

818.330

461.467

Ksps

Continuous conversions

enabled, subsequent

conversion time

C_rate

ADC conversion 16-bit mode

7

rate

No ADC hardware averaging

Continuous conversions

enabled, subsequent

conversion time

1. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 1.0 MHz, unless otherwise stated. Typical values are for

reference only, and are not tested in production.

2. DC potential difference.

3. V_REFHis internally tied to V_DDA

4. V_REFLis internally tied to V_SSA

.

5. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as

possible. The results in this data sheet were derived from a system that had < 8 Ω analog source resistance. The

R_AS/C_AStime constant should be kept to < 1 ns.

6. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.

7. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.

SIMPLIFIED

INPUT PIN EQUIVALENT

ZADIN

CIRCUIT

SIMPLIFIED

CHANNEL SELECT

CIRCUIT

Pad

ZAS

leakage

due to

input

ADC SAR

ENGINE

RAS

RADIN

protection

VADIN

CAS

VAS

RADIN

INPUT PIN

CADIN

Figure 12. ADC input impedance equivalency diagram

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MCU Electrical characteristics

7.6.6.1.2 16-bit ADC electrical characteristics

Table 31. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA

)

Symbol Description

Conditions¹

Min.

0.215

1.2

Typ.²

Max.

1.7

3.9

6.1

7.3

9.5

Unit

mA

Notes

I_{DDA_ADC}Supply current

—

3

ADC asynchronous

clock source

• ADLPC = 1, ADHSC = 0

• ADLPC = 1, ADHSC = 1

• ADLPC = 0, ADHSC = 0

• ADLPC = 0, ADHSC = 1

2.4

4.0

5.2

6.2

MHz

t_ADACK= 1/

f_ADACK

2.4

f_ADACK

3.0

4.4

Sample Time

See Reference Manual chapter for sample times

TUE

DNL

Total unadjusted

error

• 12-bit modes

• <12-bit modes

—

4

6.8

2.1

LSB⁴

5

1.4

Differential non-

linearity

• 12-bit modes

• <12-bit modes

—

0.7

0.2

–1.1 to

+1.9

–0.3 to

0.5

INL

Integral non-linearity

• 12-bit modes

• <12-bit modes

—

1.0

0.5

–2.7 to

+1.9

LSB⁴

5

–0.7 to

+0.5

5

E_FS

E_Q

Full-scale error

• 12-bit modes

• <12-bit modes

• 16-bit modes

• ≤13-bit modes

—

–4

–1.4

–1 to 0

—

–5.4

–1.8

—

LSB⁴

V_ADIN= V_DDA

Quantization error

0.5

ENOB Effective number of 16-bit differential mode

6

bits

12.8

11.9

14.5

13.8

—

bits

• Avg = 32

• Avg = 4

16-bit single-ended mode

• Avg = 32

12.2

11.4

13.9

13.1

—

bits

dB

• Avg = 4

Signal-to-noise plus See ENOB

SINAD

6.02 × ENOB + 1.76

distortion

THD

Total harmonic

distortion

16-bit differential mode

• Avg = 32

7

dB

—

-94

-85

—

16-bit single-ended mode

—

Table continues on the next page...

52

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MCU Electrical characteristics

Table 31. 16-bit ADC characteristics (V_REFH= V_DDA, V_REFL= V_SSA) (continued)

Symbol Description

Conditions¹

Min.

Typ.²

Max.

Unit

Notes

• Avg = 32

SFDR Spurious free

dynamic range

16-bit differential mode

• Avg = 32

7

—

dB

82

78

95

90

16-bit single-ended mode

• Avg = 32

E_IL

Input leakage error

I_In× R_AS

mV

I_In= leakage

current

(refer to the

MCU's voltage

and current

operating

ratings)

Temp sensor slope Across the full temperature

range of the device

1.55

706

1.62

716

1.69

726

mV/°C

mV

8

V_TEMP25Temp sensor voltage 25 °C

8

1. All accuracy numbers assume the ADC is calibrated with V_REFH= V_DDA

2. Typical values assume V_DDA= 3.0 V, Temp = 25 °C, f_ADCK= 2.0 MHz unless otherwise stated. Typical values are for

reference only and are not tested in production.

3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low

power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with

1 MHz ADC conversion clock speed.

4. 1 LSB = (V_REFH- V_REFL)/2^N

5. ADC conversion clock < 16 MHz, Max hardware averaging (AVGE = %1, AVGS = %11)

6. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.

7. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.

8. ADC conversion clock < 3 MHz

MKW2xD Data Sheet, Rev. 2, 05/2016

53

NXP Semiconductors

MCU Electrical characteristics

Typical ADC 16-bit Differential ENOB vs ADC Clock

100Hz, 90% FS Sine Input

15.00

14.70

14.40

14.10

13.80

13.50

13.20

12.90

12.60

Hardware Averaging Disabled

Averaging of 4 samples

Averaging of 8 samples

Averaging of 32 samples

12.30

12.00

1

2

3

4

5

6

7

8

9

10

11

12

ADC Clock Frequency (MHz)

Figure 13. Typical ENOB vs. ADC_CLK for 16-bit differential mode

Typical ADC 16-bit Single-Ended ENOB vs ADC Clock

100Hz, 90% FS Sine Input

14.00

13.75

13.50

13.25

13.00

12.75

12.50

12.25

12.00

11.75

11.50

11.25

Averaging of 4 samples

Averaging of 32 samples

11.00

1

2

3

4

5

6

7

8

9

10

11

12

ADC Clock Frequency (MHz)

Figure 14. Typical ENOB vs. ADC_CLK for 16-bit single-ended mode

7.6.6.2 CMP and 6-bit DAC electrical specifications

Table 32. Comparator and 6-bit DAC electrical specifications

Symbol

V_DD

Description

Min.

1.8

—

Typ.

—

Max.

3.6

Unit

V

Supply voltage

I_DDHS

Supply current, High-speed mode (EN=1, PMODE=1)

—

200

μA

Table continues on the next page...

54

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MCU Electrical characteristics

Table 32. Comparator and 6-bit DAC electrical specifications (continued)

Symbol

I_DDLS

V_AIN

Description

Min.

—

Typ.

—

Max.

20

Unit

μA

V

Supply current, low-speed mode (EN=1, PMODE=0)

Analog input voltage

V_SS– 0.3

—

V_DD

20

V_AIO

Analog input offset voltage

Analog comparator hysteresis¹

• CR0[HYSTCTR] = 00

—

mV

V_H

—

5

—

mV

• CR0[HYSTCTR] = 01

10

20

30

• CR0[HYSTCTR] = 10

• CR0[HYSTCTR] = 11

V_CMPOh

V_CMPOl

t_DHS

Output high

Output low

V_DD– 0.5

—

50

—

0.5

200

V

—

Propagation delay, high-speed mode (EN=1,

PMODE=1)

20

ns

t_DLS

Propagation delay, low-speed mode (EN=1,

PMODE=0)

80

250

600

ns

Analog comparator initialization delay²

6-bit DAC current adder (enabled)

6-bit DAC integral non-linearity

—

7

40

—

μs

μA

LSB³

I_DAC6b

INL

–0.5

–0.3

—

0.5

0.3

DNL

6-bit DAC differential non-linearity

LSB

1. Typical hysteresis is measured with input voltage range limited to 0.6 to V_DD–0.6 V.

2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to

CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and

CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.

3. 1 LSB = V_reference/64

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55

NXP Semiconductors

MCU Electrical characteristics

0.08

0.07

0.06

0.05

0.04

0.03

HYSTCTR

Setting

00

01

10

11

0.02

0.01

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 15. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)

56

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NXP Semiconductors

MCU Electrical characteristics

0.18

0.16

0.14

0.12

HYSTCTR

Setting

0.1

00

01

10

11

0.08

0.06

0.04

0.02

0

0.1

0.4

0.7

1

1.3

1.6

1.9

2.2

2.5

2.8

3.1

Vin level (V)

Figure 16. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)

7.6.7 Timers

See General switching specifications.

7.6.8 Communication interfaces

7.6.8.1 USB electrical specifications

The USB electricals for the USB On-the-Go module conform to the standards

documented by the Universal Serial Bus Implementers Forum. For the most up-to-

date standards, visit usb.org.

NOTE

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NXP Semiconductors

MCU Electrical characteristics

7.6.8.2 USB DCD electrical specifications

Table 33. USB0 DCD electrical specifications

Symbol

Description

Min.

0.5

Typ.

—

Max.

0.7

Unit

V

V_{DP_SRC}USB_DP source voltage (up to 250 μA)

V_LGC

Threshold voltage for logic high

USB_DP source current

0.8

—

2.0

V

I_{DP_SRC}

7

10

13

μA

kΩ

V

I_{DM_SINK}USB_DM sink current

50

100

—

150

24.8

0.4

R_{DM_DWN}D- pulldown resistance for data pin contact detect

V_{DAT_REF}Data detect voltage

14.25

0.25

0.33

7.6.8.3 VREG electrical specifications

Table 34. VREG electrical specifications

Symbol Description

Min.

2.7

—

Typ.¹

Max.

5.5

Unit

Notes

VREGIN Input supply voltage

—

V

I_DDon

I_DDstby

I_DDoff

Quiescent current — Run mode, load current

equal zero, input supply (VREGIN) > 3.6 V

125

186

μA

Quiescent current — Standby mode, load

current equal zero

—

1.27

30

μA

Quiescent current — Shutdown mode

—

650

—

4

nA

μA

• VREGIN = 5.0 V and temperature=25 °C

• Across operating voltage and temperature

I_LOADrunMaximum load current — Run mode

I_LOADstbyMaximum load current — Standby mode

—

120

1

mA

V_Reg33outRegulator output voltage — Input supply

(VREGIN) > 3.6 V

• Run mode

3

3.3

2.8

—

3.6

V

• Standby mode

2.1

V_Reg33outRegulator output voltage — Input supply

(VREGIN) < 3.6 V, pass-through mode

2

C_OUT

ESR

External output capacitor

1.76

1

2.2

—

8.16

100

μF

External output capacitor equivalent series

resistance

mΩ

I_LIM

Short circuit current

—

290

—

mA

1. Typical values assume VREGIN = 5.0 V, Temp = 25 °C unless otherwise stated.

2. Operating in pass-through mode: regulator output voltage equal to the input voltage minus a drop proportional to I_Load

.

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MCU Electrical characteristics

7.6.8.4 DSPI switching specifications (limited voltage range)

The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with

master and slave operations. Many of the transfer attributes are programmable. The

tables below provide DSPI timing characteristics for classic SPI timing modes. Refer

to the DSPI chapter of the Reference Manual for information on the modified transfer

formats used for communicating with slower peripheral devices.

Table 35. Master mode DSPI timing (limited voltage range)

Num

Description

Min.

2.7

Max.

3.6

25

Unit

V

Notes

Operating voltage

Frequency of operation

—

MHz

ns

DS1

DS2

DS3

DSPI_SCK output cycle time

DSPI_SCK output high/low time

DSPI_PCSn valid to DSPI_SCK delay

2 x t_BUS

—

(t_SCK/2) − 2 (t_SCK/2) + 2

ns

(t_BUSx 2) −

2

—

ns

1

2

DS4

DSPI_SCK to DSPI_PCSn invalid delay

(t_BUSx 2) −

2

—

ns

DS5

DS6

DS7

DS8

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

—

−2

15

0

8.5

—

ns

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].

2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

DSPI_PCSn

DS1

DS3

DS2

DS4

DSPI_SCK

(CPOL=0)

DS8

DS7

Data

Last data

First data

DSPI_SIN

DS5

DS6

First data

Data

Last data

DSPI_SOUT

Figure 17. DSPI classic SPI timing — master mode

Table 36. Slave mode DSPI timing (limited voltage range)

Num

Description

Min.

Max.

3.6

Unit

V

Operating voltage

2.7

Frequency of operation

12.5

MHz

Table continues on the next page...

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59

NXP Semiconductors

MCU Electrical characteristics

Table 36. Slave mode DSPI timing (limited voltage range) (continued)

Num

DS9

Description

DSPI_SCK input cycle time

Min.

Max.

Unit

ns

4 x t_BUS

—

DS10

DS11

DS12

DS13

DS14

DS15

DS16

DSPI_SCK input high/low time

(t_SCK/2) − 2

(t_SCK/2) + 2

DSPI_SCK to DSPI_SOUT valid

—

0

10

—

14

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

DSPI_SS active to DSPI_SOUT driven

DSPI_SS inactive to DSPI_SOUT not driven

2

7

—

DSPI_SS

DS10

DS9

DSPI_SCK

(CPOL=0)

DS15

DS12

DS16

DS11

First data

DS14

Last data

DSPI_SOUT

Data

DS13

First data

Last data

DSPI_SIN

Figure 18. DSPI classic SPI timing — slave mode

7.6.8.5 DSPI switching specifications (full voltage range)

The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with

master and slave operations. Many of the transfer attributes are programmable. The

tables below provides DSPI timing characteristics for classic SPI timing modes. Refer

to the DSPI chapter of the Reference Manual for information on the modified transfer

formats used for communicating with slower peripheral devices.

Table 37. Master mode DSPI timing (full voltage range)

Num

Description

Min.

1.8

Max.

3.6

Unit

V

Notes

Operating voltage

1

Frequency of operation

—

12.5

—

MHz

ns

DS1

DS2

DSPI_SCK output cycle time

DSPI_SCK output high/low time

4 x t_BUS

(t_SCK/2) - 4 (t_SCK/2)+ 4

Table continues on the next page...

ns

60

NXP Semiconductors

MKW2xD Data Sheet, Rev. 2, 05/2016

MCU Electrical characteristics

Table 37. Master mode DSPI timing (full voltage range) (continued)

Num

Description

Min.

Max.

Unit

Notes

DS3

DSPI_PCSn valid to DSPI_SCK delay

(t_BUSx 2) −

4

—

ns

2

DS4

DSPI_SCK to DSPI_PCSn invalid delay

(t_BUSx 2) −

4

—

ns

3

DS5

DS6

DS7

DS8

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

—

-4.5

20.5

0

10

—

ns

1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage

range the maximum frequency of operation is reduced.

2. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].

3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

DSPI_PCSn

DS1

DS3

DS2

DS4

DSPI_SCK

(CPOL=0)

DS8

DS7

Data

Last data

First data

DSPI_SIN

DS5

DS6

First data

Data

Last data

DSPI_SOUT

Figure 19. DSPI classic SPI timing — master mode

Table 38. Slave mode DSPI timing (full voltage range)

Num

Description

Min.

Max.

Unit

V

Operating voltage

1.8

3.6

Frequency of operation

—

6.25

MHz

ns

DS9

DSPI_SCK input cycle time

8 x t_BUS

—

DS10

DS11

DS12

DS13

DS14

DS15

DS16

DSPI_SCK input high/low time

(t_SCK/2) - 4

(t_SCK/2)+ 4

ns

DSPI_SCK to DSPI_SOUT valid

DSPI_SCK to DSPI_SOUT invalid

DSPI_SIN to DSPI_SCK input setup

DSPI_SCK to DSPI_SIN input hold

DSPI_SS active to DSPI_SOUT driven

DSPI_SS inactive to DSPI_SOUT not driven

—

0

20

—

19

ns

2

ns

7

ns

—

ns

MKW2xD Data Sheet, Rev. 2, 05/2016

61

NXP Semiconductors

MCU Electrical characteristics

DSPI_SS

DS10

DS9

DSPI_SCK

(CPOL=0)

DS15

DS12

DS16

DS11

First data

DS14

Last data

DSPI_SOUT

Data

DS13

First data

Last data

DSPI_SIN

Figure 20. DSPI classic SPI timing — slave mode

7.6.8.6 I²C

See General switching specifications.

7.6.8.7 UART

See General switching specifications.

7.6.8.8 Normal Run, Wait and Stop mode performance over the full

operating voltage range

This section provides the operating performance over the full operating voltage for the

device in Normal Run, Wait and Stop modes.

Due to a limited set of pin availability in the SiP, the I2S/SAI block is usable only for

receive mode and must be configured as a slave.

Table 39. I2S/SAI master mode timing

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

1.8

40

3.6

—

V

S1

S2

S3

S4

S5

I2S_MCLK cycle time

ns

I2S_MCLK (as an input) pulse width high/low

I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low

45%

80

55%

—

MCLK period

ns

45%

—

55%

15

BCLK period

ns

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output valid

S6

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output invalid

0

—

ns

Table continues on the next page...

62

MKW2xD Data Sheet, Rev. 2, 05/2016

NXP Semiconductors

MCU Electrical characteristics

Table 39. I2S/SAI master mode timing (continued)

Num.

Characteristic

I2S_TX_BCLK to I2S_TXD valid

I2S_TX_BCLK to I2S_TXD invalid

Min.

Max.

Unit

S7

S8

S9

—

0

15

—

ns

I2S_RXD/I2S_RX_FS input setup before

I2S_RX_BCLK

25

S10

I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK

0

—

ns

S1

S2

I2S_MCLK (output)

S3

S4

I2S_TX_BCLK/

I2S_RX_BCLK (output)

S4

S5

S7

S6

I2S_TX_FS/

I2S_RX_FS (output)

S10

S9

I2S_TX_FS/

I2S_RX_FS (input)

S7

S8

I2S_TXD

I2S_RXD

S9

S10

Figure 21. I2S/SAI timing — master modes

Table 40. I2S/SAI slave mode timing

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)

1.8

80

3.6

—

V

S11

S12

ns

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%

(input)

55%

MCLK period

S13

S14

I2S_TX_FS/I2S_RX_FS input setup before

I2S_TX_BCLK/I2S_RX_BCLK

10

—

ns

I2S_TX_FS/I2S_RX_FS input hold after

I2S_TX_BCLK/I2S_RX_BCLK

2

—

S15

S16

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid

—

0

29

—

ns

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output

invalid

S17

S18

S19

I2S_RXD setup before I2S_RX_BCLK

I2S_RXD hold after I2S_RX_BCLK

I2S_TX_FS input assertion to I2S_TXD output valid¹

10

2

—

21

ns

—

MKW2xD Data Sheet, Rev. 2, 05/2016

63

NXP Semiconductors

MCU Electrical characteristics

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

S11

S12

I2S_TX_BCLK/

I2S_RX_BCLK (input)

S12

S15

S16

I2S_TX_FS/

I2S_RX_FS (output)

S13

S14

I2S_TX_FS/

I2S_RX_FS (input)

S15

S19

S16

I2S_TXD

I2S_RXD

S17

S18

Figure 22. I2S/SAI timing — slave modes

7.6.8.9 VLPR, VLPW, and VLPS mode performance over the full

operating voltage range

This section provides the operating performance over the full operating voltage for the

device in VLPR, VLPW, and VLPS modes.

Due to a limited set of pin availability in the SiP, the I2S/SAI block is usable only for

receive mode and must be configured as a slave.

Table 41. I2S/SAI master mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

1.8

3.6

—

V

S1

S2

S3

S4

S5

I2S_MCLK cycle time

62.5

45%

250

45%

—

ns

I2S_MCLK pulse width high/low

55%

—

MCLK period

I2S_TX_BCLK/I2S_RX_BCLK cycle time (output)

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low

ns

55%

45

BCLK period

ns

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output valid

S6

I2S_TX_BCLK/I2S_RX_BCLK to I2S_TX_FS/

I2S_RX_FS output invalid

0

—

ns

S7

S8

S9

I2S_TX_BCLK to I2S_TXD valid

I2S_TX_BCLK to I2S_TXD invalid

—

0

45

—

ns

I2S_RXD/I2S_RX_FS input setup before

I2S_RX_BCLK

75

S10

I2S_RXD/I2S_RX_FS input hold after I2S_RX_BCLK

0

—

ns

64

MKW2xD Data Sheet, Rev. 2, 05/2016

NXP Semiconductors

MCU Electrical characteristics

S1

S2

I2S_MCLK (output)

S3

S4

I2S_TX_BCLK/

I2S_RX_BCLK (output)

S4

S5

S7

S6

I2S_TX_FS/

I2S_RX_FS (output)

S10

S9

I2S_TX_FS/

I2S_RX_FS (input)

S7

S8

I2S_TXD

I2S_RXD

S9

S10

Figure 23. I2S/SAI timing — master modes

Table 42. I2S/SAI slave mode timing in VLPR, VLPW, and VLPS modes (full voltage range)

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)

1.8

3.6

—

V

S11

250

ns

S12

S13

S14

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low 45%

(input)

55%

MCLK period

I2S_TX_FS/I2S_RX_FS input setup before

I2S_TX_BCLK/I2S_RX_BCLK

30

—

ns

I2S_TX_FS/I2S_RX_FS input hold after

I2S_TX_BCLK/I2S_RX_BCLK

2

—

S15

S16

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid

—

0

87

—

ns

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output

invalid

S17

S18

S19

I2S_RXD setup before I2S_RX_BCLK

I2S_RXD hold after I2S_RX_BCLK

I2S_TX_FS input assertion to I2S_TXD output valid¹

30

2

—

72

ns

—

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

MKW2xD Data Sheet, Rev. 2, 05/2016

65

NXP Semiconductors

Transceiver Electrical Characteristics

S11

S12

I2S_TX_BCLK/

I2S_RX_BCLK (input)

S12

S15

S16

I2S_TX_FS/

I2S_RX_FS (output)

S13

S14

I2S_TX_FS/

I2S_RX_FS (input)

S15

S19

S16

I2S_TXD

I2S_RXD

S17

S18

Figure 24. I2S/SAI timing — slave modes

8 Transceiver Electrical Characteristics

8.1 DC electrical characteristics

Table 43. DC electrical characteristics (V_BAT, V_BAT2= 2.7 V, T_A=25 °C, unless otherwise

noted)

Characteristic

Symbol

Min

Typ

Max

Unit

Power Supply Current (VBAT + VBAT2)

Reset / power down¹

Hibernate¹

I_leakage

I_CCH

I_CCD

I_CCI

—

<60

<1

<100

—

nA

μA

mA

Doze (No CLK_OUT)

500

700

17

—

Idle (No CLK_OUT)

—

Transmit mode (0 dBm nominal output power)

Receive mode (normal)

I_CCT

I_CCR

18

19

19.5

Receive mode (power preamble search)

Input current (VIN = 0 V or VDDINT) (All digital inputs)

Input low voltage (all digital inputs)

15 (LPPS)

I_IN

—

0

—

1

μA

V

V_IL

30%

V_DDINT

Input high voltage (all digital inputs)

V_IH

V_OH

V_OL

70%

V_DDINT

—

V_DDINT

V

Output high voltage (IOH = -1 mA) (all digital outputs)

Output low voltage (IOL = 1 mA) (all digital outputs)

80%

V_DDINT

0

20%

V_DDINT

1. To attain specified low power current, all GPIO and other digital IO must be handled properly.

66

MKW2xD Data Sheet, Rev. 2, 05/2016

NXP Semiconductors

Transceiver Electrical Characteristics

8.2 AC electrical characteristics

Table 44. Receiver AC electrical characteristics (V_BAT, V_DDINT= 2.7 V, T_A=25 °C, f_ref= 32 MHz

unless otherwise noted)

Characteristic

Symbol

Min

—

Typ

–99

–102

—

Max

Unit

dBm

Sensitivity for 1% packet error rate (PER) (–40 to +105 °C) SENSper

–97

Sensitivity for 1% packet error rate (PER) (+25 °C)

Saturation (maximum input level)

SENSper

—

SENSmax

–10

—

Channel rejection for dual port mode (1% PER and desired

signal –82 dBm)

+5 MHz (adjacent channel)

–5 MHz (adjacent channel)

+10 MHz (alternate channel)

–10 MHz (alternate channel)

>= 15 MHz

—

80

39

33

50

58

—

dB

—

dB

—

dB

—

dB

Frequency error tolerance

Symbol rate error tolerance

200

—

kHz

ppm

Table 45. Transmitter AC electrical characteristics (V_BAT, V_DDINT= 2.7 V, T_A=25 °C, f_ref= 32

MHz unless otherwise noted)

Characteristic

Symbol

Min

Typ

Max

Unit

Power spectral density¹, absolute limit from –40°C to

+105°C

–30

—

dBm

Power Spectral Density², Relative limit from –40°C to

+105°C

–20

—

dB

Nominal output power³

Maximum output power³

Error vector magnitude

Output power control range⁴

Over the air data rate

2nd harmonic⁵

Pout

EVM

–2

—

0

8

2

—

dBm

%

8

13

40

—

dB

250

<–50

—

kbps

dBm

<–40

3rd harmonic⁵

1. [f-fc] > 3.5 MHz, average spectral power is measured in 100 kHz resolution BW.

2. For the relative limit, the reference level is the highest reference power measured within 1 MHz of the carrier

frequency.

3. Measurement is at the package pin.

4. Measurement is at the package pin on the output of the Tx/Rx switch. It does not degrade more than 2 dB across

temperature and an additional 1 dB across all processes. Power adjustment will span nominally from –35 dBm to +8

dBm in 21 steps @ 2 dBm / step.

5. Measured with output power set to nominal (0 dBm) and temperature @ 25°C. Trap filter is needed.

MKW2xD Data Sheet, Rev. 2, 05/2016

67

NXP Semiconductors

Transceiver Electrical Characteristics

Characteristic

Table 46. RF port impedance

Symbol

Typ

Unit

RFIN Pins for internal T/R switch configuration, TX mode

Zin

Ohm

14.7 - j215

2.360 GHz

13.7 -

j18.7

2.420 GHz

2.480 GHz

13 - j16.3

RFIN Pins for internal or external T/R switch configuration, RX mode

Zin

Ohm

14 - j9.5

13 - j7.6

2.360 GHz

2.420 GHz

2.480 GHz

12.3 - j5.6

8.3 SPI timing: R_SSEL_B to R_SCLK

The following diagram describes timing constraints that must be guaranteed by the

system designer.

R_MOSI

R_SCLK

t

ASC

CSC

t

DT

CKH

CKL

Figure 25. SPI timing: R_SSEL_B to R_SCLK

t_CSC(CS-to-SCK delay): 31.25 ns

t_ASC(After SCK delay): 31.25 ns

t_DT(Minimum CS idle time): 62.5 ns

t_CKH(Minimum R_SCLK high time): 31.25 ns (for SPI writes); 55.55 ns (for SPI reads)

t_CKL(Minimum R_SCLK low time): 31.25 ns (for SPI writes); 55.55 ns (for SPI reads)

Note

The SPI master device deasserts R_SSEL_B only on byte

boundaries, and only after guaranteeing the t_ASCconstraint

shown above.

68

MKW2xD Data Sheet, Rev. 2, 05/2016

NXP Semiconductors

Crystal oscillator reference frequency

8.4 SPI timing: R_SCLK to R_MOSI and R_MISO

The following diagram describes timing constraints that must be guaranteed by the

system designer. These constraints apply to the Master SPI (R_MOSI), and are

guaranteed by the radio SPI (R_MISO).

R_SCLK

R_MOSI

R_MISO

t

DSU

t

DH

Figure 26. SPI timing: R_SCLK to R_MOSI and R_MISO

t_DSU(data-to-SCK setup): 10 ns

t_DH(SCK-to-data hold): 10 ns

9 Crystal oscillator reference frequency

This section provides application specific information regarding crystal oscillator

reference design and recommended crystal usage.

9.1 Crystal oscillator design considerations

The IEEE ® 802.15.4 Standard requires that frequency tolerance be kept within 40

ppm accuracy. This means that a total offset up to 80 ppm between transmitter and

receiver will still result in acceptable performance. The MKW2xD transceiver

provides on board crystal trim capacitors to assist in meeting this performance, while

the bulk of the crystal load capacitance is external.

MKW2xD Data Sheet, Rev. 2, 05/2016

69

NXP Semiconductors

Crystal oscillator reference frequency

9.2 Crystal requirements

The suggested crystal specification for the MKW2xD is shown in Table 47. A number

of the stated parameters are related to desired package, desired temperature range and

use of crystal capacitive load trimming.

Table 47. MKW2xD crystal specifications

Parameter

Value

32

Unit

MHz

ppm

Ω

Condition

Frequency

Frequency tolerance (cut tolerance)

Frequency stability (temperature)

Aging¹

10

at 25°C

25

Over desired temperature range

2

max

Equivalent series resistance

Load capacitance

60

5–9

<2

pF

Shunt capacitance

Mode of oscillation

pF

max

fundamental

1. A wider aging tolerance may be acceptable if application uses trimming at production final test.

70

MKW2xD Data Sheet, Rev. 2, 05/2016

NXP Semiconductors

Pin diagrams and pin assignments

10 Pin diagrams and pin assignments

10.1 MKW21D256/MKW21D512 Pin Assignment

56 55 54 53 52 51 50 49 48 47 46 45 44 43

EXTAL_32M

VBAT2_RF

RESET_B

1

2

3

4

42

41

40

GPIO1

GPIO2

57 58

59 60

61 62

63

PTA19/XTAL

PTC4/LLWU_P8

PTC5/LLWU_P9

PTC6/LLWU_P10

PTA18/EXTAL/CLK_OUT

VDD_MCU

39

GND flag

5

6

38

37

PTA4/LLWU_P3

7

PTC7

PTD1

36

PTA3

8

9

35

34

PTA2

PTD2/LLWU_P13

PTA1

GND flag

PTD3

10

33

PTA0

PTD4/LLWU_P14

11

12

32

31

VBAT_MCU

PTD5

EXTAL_32

PTD6/LLWU_P15

13

14

30

29

XTAL_32

PTD7

TAMPER0/RTC_WAKEUP_B

15 16 17 18 19 20 21 22 23 24 25 26 27 28

MKW2xD Data Sheet, Rev. 2, 05/2016

71

NXP Semiconductors

Pin diagrams and pin assignments

10.2 MKW22/24D512V Pin Assignment

56 55 54 53 52 51 50 49 48 47 46 45 44 43

EXTAL_32M

VBAT2_RF

RESET_B

1

2

3

4

42

41

40

GPIO1

GPIO2

57 58

59 60

61 62

63

PTA19/XTAL

PTC4/LLWU_P8

PTC5/LLWU_P9

PTC6/LLWU_P10

PTA18/EXTAL/CLK_OUT

VDD_MCU

39

GND flag

5

6

38

37

PTA4/LLWU_P3

7

PTC7

PTD1

36

PTA3

8

9

35

34

PTA2

PTD2/LLWU_P13

PTA1

GND flag

PTD3

10

33

PTA0

PTD4/LLWU_P14

11

12

32

31

VBAT_MCU

PTD5

EXTAL_32

PTD6/LLWU_P15

13

14

30

29

XTAL_32

PTD7

TAMPER0/RTC_WAKEUP_B

15 16 17 18 19 20 21 22 23 24 25 26 27 28

10.3 Pin assignments

Note

SPI1 (ALT2): SPI1 is dedicated to the radio and is not an

alternate MCU peripheral.

Table 48. Pin Assignments

MKW

22/24

D512

(USB)

MKW

21D25

6/512

Name

EZPO

RT

Default

ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7

1

EXTAL

_32M

EXTAL_32M

2

3

2

3

GPIO1

GPIO2

GPIO1

GPIO2

Table continues on the next page...

72

NXP Semiconductors

MKW2xD Data Sheet, Rev. 2, 05/2016

Pin diagrams and pin assignments

Table 48. Pin Assignments (continued)

MKW

22/24

D512

(USB)

MKW

21D25

6/512

Name

EZPO

RT

Default

ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7

4

5

6

7

8

9

4

5

6

7

8

9

PTC4/

LLWU_

P8

Disabled

PTC4/ SPI0_ UART1 FTM0_

CMP1_

OUT

LLWU_ PCS0

P8

_TX

CH3

PTC5/

LLWU_

P9

Disabled

CMP0_IN0

CMP0_IN1

ADC0_SE5b

Disabled

PTC5/ SPI0_ LPTM I2S0_R

LLWU_ SCK R0_AL XD0

CMP0_

OUT

P9

T2

PTC6/

LLWU_

P10

CMP0_ PTC6/ SPI0_ PDB0_ I2S0_R

IN0 LLWU_ SOUT EXTR X_BCL

I2S0_

MCLK

P10

G

K

PTC7

CMP0_ PTC7 SPI0_ USB_S I2S0_R

IN1

SIN

OF_O X_FS

UT

PTD1

ADC0_ PTD1 SPI0_ UART2

SE5b

SCK _CTS_

b

PTD2/

LLWU_

P13

PTD2/ SPI0_ UART2 I2C0_S

LLWU_ SOUT _RX

P13

CL

10

11

10

11

PTD3

Disabled

PTD3 SPI0_ UART2 I2C0_S

SIN _TX DA

PTD4/

LLWU_

P14

ADC0_SE21

ADC0_ PTD4/ SPI0_ UART0 FTM0_

SE21 LLWU_ PCS1 _RTS_ CH4

EWM_I

N

P14

b

12

PTD5

ADC0_SE6b

ADC0_ PTD5 SPI0_ UART0 FTM0_

EWM_

OUT_b

SE6b

PCS2 _CTS_ CH5

b/

UART0

_COL_

b

13

PTD6/

LLWU_

P15

ADC0_SE7b

ADC0_ PTD6/ SPI0_ UART0 FTM0_

FTM0_

FLT0

SE7b LLWU_ PCS3

P15

_RX

CH6

14

15

14

15

PTD7

ADC0_SE22

ADC0_SE10

ADC0_ PTD7 CMT_I UART0 FTM0_

SE22 RO _TX CH7

FTM0_

FLT1

PTE0

ADC0_ PTE0 SPI1_ UART1

SE10 PCS1 _TX

TRAC I2C1_S RTC_C

E_CLK

OUT

DA LKOUT

16

17

16

17

PTE1/

LLWU_

P0

DC0_SE11

ADC0_DP1

ADC0_ PTE1/ SPI1_ UART1

SE11 LLWU_ SOUT _RX

P0

TRAC I2C1_S SPI1_

E_D3

CL

SIN

PTE2/

LLWU_

P1

ADC0_ PTE2/ SPI1_ UART1

DP1 LLWU_ SCK _CTS_

TRAC

E_D2

P1

b

Table continues on the next page...

MKW2xD Data Sheet, Rev. 2, 05/2016

73

NXP Semiconductors

Pin diagrams and pin assignments

Table 48. Pin Assignments (continued)

MKW

22/24

D512

(USB)

MKW

21D25

6/512

Name

EZPO

RT

Default

ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7

18

19

20

18

PTE3

ADC0_DM1

ADC0_ PTE3 SPI1_ UART1

TRAC

E_D1

SPI1_

SOUT

DM1

SIN _RTS_

b

19

PTE4/

LLWU_

P2

Disabled

PTE4/ SPI1_

LLWU_ PCS0

P2

TRAC

E_D0

20

21

22

VDD_M

CU

VDD

PTE16

ADC0_SE4a

ADC0_SE5a

ADC0_ PTE16 SPI0_ UART2 FTM_C

SE4a PCS0 _TX LKIN0

FTM0_

FLT3

PTE17

ADC0_ PTE17 SPI0_ UART2 FTM_C

SE5a SCK _RX LKIN1

LPTM

R0_AL

T3

23

24

PTE18

PTE19

ADC0_SE6a

ADC0_SE7a

ADC0_ PTE18 SPI0_ UART2 I2C0_S

SE6a

SOUT _CTS_

b

DA

ADC0_ PTE19 SPI0_ UART2 I2C0_S

SE7a

SIN _RTS_

b

CL

21

22

23

24

USB0_

DP

USB0_DP

USB0_DM

VOUT33

VREGIN

USB0_

DP

USB0_

DM

USB0_

DM

VOUT3

3

VOUT3

3

VREGI

N

VREGI

N

25

26

25

26

VDDA

VREFH

VREF

H

27

28

29

27

28

29

VREFL

VSSA

VREFL

VSSA

VREFL

VSSA

TAMP

TAMPE

R0/

TAMPER0/

RTC_WAKEUP_B ER0/

RTC_

WAKE

UP_B

RTC_

WAKE

UP_B

30

31

32

30

31

32

XTAL3

2

XTAL32

EXTAL32

XTAL3

2

EXTAL

32

EXTAL

32

VBAT_

MCU

VBAT_MCU

VBAT_

MCU

Table continues on the next page...

74

NXP Semiconductors

MKW2xD Data Sheet, Rev. 2, 05/2016

Pin diagrams and pin assignments

Table 48. Pin Assignments (continued)

MKW

22/24

D512

(USB)

MKW

21D25

6/512

Name

EZPO

RT

Default

ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7

33

PTA0

JTAG_TCLK/

SWD_CLK/

EZP_CLK

PTA0 UART0 FTM0_

JTAG_ EZP_C

_CTS_ CH5

TCLK/

SWD_

CLK

LK

b/

UART0

_COL_

b

34

35

34

35

PTA1

PTA2

JTAG_TDI/

EZP_DI

PTA1 UART0 FTM0_

JTAG_ EZP_D

TDI

_RX

PTA2 UART0 FTM0_

_TX CH7

CH6

I

JTAG_TDO/

TRACE_SWO/

EZP_DO

JTAG_ EZP_D

TDO/

TRAC

E_SW

O

36

37

36

37

PTA3

JTAG_TMS/

SWD_DIO

PTA3 UART0 FTM0_

JTAG_

TMS/

SWD_

DIO

_RTS_ CH0

b

PTA4/ NMI_b/EZP_CS_b

LLWU_

P3

PTA4/

LLWU_

P3

FTM0_

CH1

NMI_b EZP_C

S_b

38

39

40

38

39

40

VDD2_

MCU

VDD

PTA18

EXTAL0

XTAL0

EXTAL PTA18

0

FTM0_ FTM_C

FLT2 LKIN0

PTA19

XTAL0 PTA19

FTM1_ FTM_C

FLT0 LKIN1

LPTM

R0_AL

T1

41

42

41

42

RESET

_b

RESET_b

VBAT2_RF

VDD_REGD

RESET

_b

VBAT2

_RF

43¹

43¹VDD_R

EGD

44

45

46

44

45

46

ANT_A

ANT_B

ANT_A

ANT_B

RX_S

RX_SWITCH

WITCH

47

48

49

47

48

49

TX_SW

ITCH

TX_SWITCH

VSSA_PA

RF_OUTP

GND_P

A

RF_OU

TP

Table continues on the next page...

MKW2xD Data Sheet, Rev. 2, 05/2016

75

NXP Semiconductors

Dimensions

MKW

Table 48. Pin Assignments (continued)

MKW

22/24

D512

(USB)

Name

EZPO

RT

21D25

6/512

Default

ALT0 ALT1 ALT2 ALT3 ALT4 ALT5 ALT6 ALT7

50

51

52¹

53¹

54¹

55

56

57

58

59

60

61

62

63

50

51

RF_OU

TN

RF_OUTN

VSSA_PA

VDD_PA

VDD_IF

GND_P

A

52¹VDD_P

A

53¹

VDD_I

F

54¹VDD_R

F

VDD_RF

VBAT

55

56

57

58

59

60

61

62

63

VBAT_

RF

XTAL_

32M

XTAL_32M

Factory Do not connect

test

Factory Do not connect

test

Factory Do not connect

test

Factory Do not connect

test

Factory Do not connect

test

Factory Do not connect

test

GND_P Connect to ground

A

1. This pin is used for external bypassing of an internal regulator. DO NOT connect to power.

11 Dimensions

11.1 Obtaining package dimensions

Package dimensions are provided in package drawings.

To find a package drawing, go to nxp.com and perform a keyword search for the

drawing’s document number:

76

MKW2xD Data Sheet, Rev. 2, 05/2016

NXP Semiconductors

Revision History

If you want the drawing for this package

63 MAPLGA

Then use this document number

98ASA00393D

12 Revision History

The following table provides a revision history for this document.

Table 49. Revision History

Rev. No.

Date

Substantial Changes

2

05/2016

• Updated features list and added pin package diagram on front

page.

• Added Related Resources table.

• Updated structure of section 4 and added section 4.5 "RF Output

Power Distribution".

• Added section 5.1 "Transceiver Transmit Current Distribution".

• Updated pin diagrams with correct pin assignments.

• Replaced MKW2x with MKW2xD through out.

MKW2xD Data Sheet, Rev. 2, 05/2016

77

NXP Semiconductors


型号：	MKW21D512VHA5
厂家：	NXP
描述：	The MKW2xD is a low power, compact integrated device
文件：	总78页 (文件大小：899K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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