MKW36Z512VFP4 [NXP]
An ultra low power, highly integrated Bluetooth® Low Energy 5.0 wireless microcontroller;型号: | MKW36Z512VFP4 |
厂家: | NXP |
描述: | An ultra low power, highly integrated Bluetooth® Low Energy 5.0 wireless microcontroller |
文件: | 总91页 (文件大小:1134K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
NXP Semiconductors
MKW36Z512
Data Sheet: Technical Data
Rev. 8, 05/2020
MKW36Z/35Z Data Sheet
MKW36Z512VHT4
MKW36Z512VFP4
MKW35Z512VHT4
An ultra low power, highly integrated Bluetooth® Low
Energy 5.0 wireless microcontroller
48 LQFN
40 "Wettable" HVQFN
7x7 mm Pitch 0.5 mm 6x6 mm Pitch 0.5 mm
Multi-Standard Radio
System peripherals
• 2.4 GHz Bluetooth Low Energy (Bluetooth LE) version
5.0 compliant supporting up to 8 simultaneous
hardware connections
• Nine MCU low-power modes to provide power
optimization based on application requirements
• DC-DC Converter supporting Buck and Bypass
operating modes
• Generic FSK modulation
• Data Rate: 250, 500 and 1000 kbps
• Modulations: GFSK BT = 0.3, 0.5, and 0.7;
FSK/MSK
• Direct memory access (DMA) Controller
• Computer operating properly (COP) watchdog
• Serial wire debug (SWD) Interface and Micro Trace
buffer
• Modulation Index: 0.32, 0.5, 0.7, and 1.0
Typical Receiver Sensitivity
(Bluetooth LE 1 Mbps) = –95 dBm
Typical Receiver Sensitivity
•
•
• Bit Manipulation Engine (BME)
Analog Modules
• 16-bit Analog-to-Digital Converter (ADC)
• 6-bit High Speed Analog Comparator (CMP)
• 1.2 V voltage reference (VREF)
(250 kbps GFSK-BT=0.5, h=0.5) = –99 dBm
• Programmable Transmitter Output Power:
–30 dBm to 5 dBm
• Low external component counts for low cost application
• On-chip balun with single ended bidirectional RF port
Timers
• 16-bit low-power timer (LPTMR)
• 3 Timer/PWM Modules(TPM): One 4 channel TPM
and two 2 channel TPMs
• Programmable Interrupt Timer (PIT)
• Real-Time Clock (RTC)
MCU and Memories
• 256 KB program flash memory plus 256 KB FlexNVM
on KW36Z
• 8 KB FlexRAM supporting EEPROM emulation on
KW36Z
• 512 KB program flash memory on KW35Z
• Up to 48 MHz Arm® Cortex®-M0+ core
• On-chip 64 KB SRAM
Communication interfaces
• 2 serial peripheral interface (SPI) modules
• 2 inter-integrated circuit (I2C) modules
• Low Power UART (LPUART) module with LIN
support (2x LPUART on KW36Z)
Low Power Consumption
• Carrier Modulator Timer (CMT)
• Transceiver current (DC-DC buck mode, 3.6 V supply)
• FlexCAN module (with CAN FD support up to 3.2
Mbps baudrate) on KW36Z
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
• Typical Rx Current: 6.3 mA
• Typical Tx current: 5.7 mA (0 dBm output)
• Low Power Mode (VLLS0) Current: 258 nA
Security
• AES-128 Hardware Accelerator (AESA)
• True Random Number Generator (TRNG)
• Advanced flash security on Program Flash
• 80-bit unique identification number per chip
• 40-bit unique media access control (MAC) sub-
address
Clocks
• 26 and 32 MHz supported for Bluetooth LE and
Generic FSK modes
• 32.768 kHz Crystal Oscillator
• LE Secure Connections
Operating Characteristics
• Voltage range: 1.71 V to 3.6 V
• Ambient temperature range: –40 to 105 °C
• Industrial Qualification
Human-machine interface
• General-purpose input/output
Orderable parts details
Top Line
Marking
CAN
FD
Device
Qualification
2nd UART with LIN FlexRAM
Package
MKW36Z512VHT4 (F)M36Z
MKW36Z512VFP4 M36Z9V4
MKW35Z512VHT4 (F)M35Z
Industrial
Y
Y
Y
Y
N
7X7 mm 48-pin
LQFN
Industrial
Industrial
Y
N
Y
N
6X6 mm 40-pin
"Wettable" HVQFN
7X7 mm 48-pin
LQFN
Related Resources
Description
Type
Resource
Product
Selector
The Product Selector lets you find the right Kinetis part for your design.
W-Series Product Selector
Fact Sheet
The Fact Sheet gives overview of the product key features and its uses. KW36-35-34 Fact Sheet
Reference
Manual
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
MKW36A512RM1
Data Sheet
The Data Sheet includes electrical characteristics and signal
connections.
This document.
Chip Errata
The chip mask set Errata provides additional or corrective information for KINETIS_W_1N41U1
a particular device mask set.
Package
drawing
Package dimensions are provided in package drawings.
• 40-pin "Wettable" HVQFN
(6x6): 98ASA01025D1
• 48-pin LQFN (7x7):
98ASA00694D1
1. To find the associated resource, go to http://www.nxp.com and perform a search using this term.
2
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
Table of Contents
1
2
Introduction......................................................................... 4
6.4.1 Thermal operating requirements......................45
6.4.2 Thermal attributes............................................ 46
6.5 Peripheral operating requirements and behaviors.......46
6.5.1 Core modules...................................................46
6.5.2 System modules.............................................. 47
6.5.3 Clock modules................................................. 48
6.5.4 Memories and memory interfaces....................52
6.5.5 Security and integrity modules.........................54
6.5.6 Analog..............................................................54
6.5.7 Timers.............................................................. 62
6.5.8 Communication interfaces................................62
6.5.9 Human-machine interfaces (HMI).................... 67
6.6 DC-DC Converter Operating Requirements................ 67
6.7 Ratings.........................................................................70
6.7.1 Thermal handling ratings................................. 70
6.7.2 Moisture handling ratings.................................70
6.7.3 ESD handling ratings....................................... 70
6.7.4 Voltage and current operating ratings..............71
Pin Diagrams and Pin Assignments....................................71
7.1 KW36Z Signal Multiplexing and Pin Assignments....... 71
7.2 KW36Z Pinouts............................................................74
7.3 KW35Z Signal Multiplexing and Pin Assignments....... 75
7.4 KW35Z Pinouts............................................................78
7.5 Module Signal Description Tables............................... 78
7.5.1 Core Modules...................................................79
7.5.2 Radio Modules................................................. 79
7.5.3 System Modules.............................................. 80
7.5.4 Clock Modules................................................. 81
7.5.5 Analog Modules............................................... 81
7.5.6 Timer Modules................................................. 82
7.5.7 Communication Interfaces............................... 83
7.5.8 Human-Machine Interfaces(HMI).....................85
Package Information........................................................... 85
8.1 Obtaining package dimensions....................................85
Part identification.................................................................85
9.1 Description...................................................................85
9.2 Format..........................................................................86
9.3 Fields........................................................................... 86
9.4 Example.......................................................................86
Feature Descriptions........................................................... 5
2.1 Block Diagram..............................................................5
2.2 Radio features..............................................................6
2.3 Microcontroller features............................................... 7
2.4 System features...........................................................8
2.5 Peripheral features.......................................................10
2.6 Security Features.........................................................14
Transceiver Description.......................................................16
3.1 Key Specifications........................................................16
3.2 Channel Map Frequency Plans ...................................16
3.2.1 Channel Plan for Bluetooth Low Energy.......... 16
3.2.2 Other Channel Plans .......................................18
3.3 Transceiver Functions..................................................18
Transceiver Electrical Characteristics................................. 19
4.1 Radio operating conditions.......................................... 19
4.2 Receiver Feature Summary.........................................19
4.3 Transmit and PLL Feature Summary...........................22
System and Power Management........................................ 26
5.1 Power Management.....................................................27
5.1.1 DC-DC Converter.............................................27
5.2 Modes of Operation..................................................... 27
5.2.1 Power modes................................................... 27
KW36Z/35Z Electrical Characteristics.................................30
6.1 AC electrical characteristics.........................................30
6.2 Nonswitching electrical specifications..........................30
6.2.1 Voltage and current operating requirements....30
6.2.2 LVD and POR operating requirements............ 31
6.2.3 Voltage and current operating behaviors......... 32
6.2.4 Power mode transition operating behaviors.....33
6.2.5 Power consumption operating behaviors.........34
6.2.6 Diagram: Typical IDD_RUN operating
3
4
5
7
6
behavior........................................................... 40
8
9
6.2.7 SoC Power Consumption.................................42
6.2.8 Designing with radiated emissions in mind...... 43
6.2.9 Capacitance attributes..................................... 43
6.3 Switching electrical specifications................................44
6.3.1 Device clock specifications.............................. 44
6.3.2 General switching specifications......................44
6.4 Thermal specifications................................................. 45
10 Revision History.................................................................. 87
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
3
NXP Semiconductors
Introduction
1 Introduction
The KW36Z/35Z wireless microcontrollers (MCU), which includes the KW36Z and
KW35Z families of devices, are highly integrated single-chip devices that enable
Bluetooth Low Energy (Bluetooth LE) and Generic FSK connectivity for industrial and
medical/healthcare embedded systems. The target applications center on wirelessly
bridging the embedded world with mobile devices to enhance the human interface
experience, share embedded data between devices and the cloud and enable wireless
firmware updates.
The KW36Z/35Z Wireless MCU integrates an Arm® Cortex®-M0+ CPU with up to
512 KB flash and 64 KB SRAM and a 2.4 GHz radio that supports Bluetooth LE 5.0
and Generic FSK modulations. The Bluetooth LE radio supports up to 8 simultaneous
connections in any master/slave combination. The Medical Body Area Network
(MBAN) frequencies from 2.36 to 2.4 GHz are also supported enabling wearable or
implantable wireless medical devices.
The KW36Z includes an integrated FlexCAN module enabling seamless integration
into an industrial CAN communication network, enabling communication with external
control and sensor monitoring devices over Bluetooth LE. The FlexCAN module can
support CAN’s flexible data-rate (CAN FD) protocol for increased bandwidth and
lower latency.
The KW36Z/35Z devices can be used as a "BlackBox" modem in order to add
Bluetooth LE or Generic FSK connectivity to an existing host MCU or MPU
(microprocessor), or may be used as a standalone smart wireless sensor with embedded
application where no host controller is required.
The RF circuit of the KW36Z/35Z is optimized to require very few external
components, achieving the smallest RF footprint possible on a printed circuit board.
Extremely long battery life is achieved through the efficiency of code execution in the
Cortex-M0+ CPU core and the multiple low power operating modes of the KW36Z/
35Z. For power critical applications, an integrated DC-DC converter enables operation
from a single coin cell or Li-ion battery with a significant reduction of peak receive and
transmit current consumption.
4
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
Feature Descriptions
2 Feature Descriptions
This section provides a simplified block diagram and highlights the KW36Z/35Z
features.
2.1 Block Diagram
Arm Cortex M0+ Core
32K Osc
32M Osc
IRC
MCG
DMA MUX
4ch DMA
Serial Wire Debug
DAP MDM
NVIC
WIC
4 MHz
DWT
MTB
IRC
32 kHz
FLL
IOPORT
Unified Bus
AHBLite
AHBLite
M2A
M0
Crossbar-Lite Switch (AXBS)
S2
S0
S1
SIM
ADC
BME
PIT
I2C x2
GPIO
Flash
Controller
64 KByte
SRAM
LTC(AESA)
TRNG
SMC
RCM
PMC
CMP
TPM x3
LPTMR
RTC
LPUART x2
SPI x2
Flash
AIPS-Lite
256 KB
FlexNVM
256 KB
FlexRAM
8 KB
Radio
IPS
APB
VREF
VDCDC_IN
IPS
DCDC
CMT
FlexCAN
Figure 1. KW36 Detailed Block Diagram
Arm Cortex M0+ Core
32K Osc
32M Osc
IRC
MCG
DMA MUX
4ch DMA
Serial Wire Debug
DAP MDM
NVIC
WIC
4 MHz
DWT
MTB
IRC
32 kHz
FLL
IOPORT
Unified Bus
AHBLite
AHBLite
M2A
M0
Crossbar-Lite Switch (AXBS)
S2
S0
S1
SIM
ADC
BME
PIT
I2C x2
GPIO
Flash
Controller
64 KByte
SRAM
SMC
RCM
PMC
CMP
TPM x3
LPTMR
RTC
LPUART
SPI x2
LTC(AESA)
TRNG
Flash
AIPS-Lite
512 KB
Prg Acc RAM
8 KB
Radio
IPS
VREF
APB
VDCDC_IN
DCDC
CMT
IPS
Figure 2. KW35 Detailed Block Diagram
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
5
NXP Semiconductors
Feature Descriptions
2.2 Radio features
Operating frequencies:
• 2.4 GHz ISM band (2400-2483.5 MHz)
• Medical Body Area Network (MBAN) 2360-2400 MHz
Supported standards:
• Bluetooth Low Energy Version 5.0 compliant radio
• Generic FSK modulation supporting data rates up to 1 Mbit/s
• Support for up to 8 simultaneous Bluetooth LE hardware connections in any
master, slave combination
• Bluetooth LE Application Profiles
Receiver performance:
• Receive sensitivity of up to –95 dBm for Bluetooth LE
• Receive sensitivity of up to –99 dBm for a 250 kbit/s GFSK mode with a
modulation index of 0.5. Receive sensitivity in Generic FSK modes depends on
mode selection and data rate.
Other features:
• Programmable transmit output power from –30 dBm to +5 dBm
• 26 MHz and 32 MHz crystals supported for Bluetooth LE and Generic FSK modes
• Bluetooth Low Energy version 5.0 Link Layer hardware with 1 Mbit/s PHY
support
• Hardware acceleration for Generic FSK packet processing
• Generic FSK modulation at 250, 500 and 1000 kbit/s
• Supports 8 simultaneous Bluetooth LE connections in any master/slave
combination
• Enhanced Bluetooth LE automatic deep sleep modes (DSM) supporting Slave
Latency
• Up to 26 devices supported by whitelist in hardware
• Up to 8 private resolvable addresses supported in hardware
• Supports DMA capture of IQ data with sampling rate of up to 2 MHz, when using a
32 MHz crystal
• Integrated on-chip balun
• Single ended bidirectional RF port shared by transmit and receive
• Low external component count
• Supports transceiver range extension using external PA and/or LNA
6
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
Feature Descriptions
2.3 Microcontroller features
Arm Cortex-M0+ CPU
• Up to 48 MHz CPU
• As compared to Cortex-M0, the Cortex-M0+ uses an optimized 2-stage pipeline
microarchitecture for reduced power consumption and improved architectural
performance (cycles per instruction)
• Supports up to 32 interrupt request sources
• Binary compatible instruction set architecture with the Cortex-M0 core
• Thumb instruction set combines high code density with 32-bit performance
• Serial Wire Debug (SWD) reduces the number of pins required for debugging
• Micro Trace Buffer (MTB) provides lightweight program trace capabilities using
system RAM as the destination memory
Nested Vectored Interrupt Controller (NVIC)
• 32 vectored interrupts, 4 programmable priority levels
• Includes a single non-maskable interrupt
Wake-up Interrupt Controller (WIC)
• Supports interrupt handling when system clocking is disabled in low-power
modes
• Takes over and emulates the NVIC behavior when correctly primed by the NVIC
on entry to very-deep-sleep
• A rudimentary interrupt masking system with no prioritization logic signals for
wake-up as soon as a non-masked interrupt is detected
Debug Controller
• Two-wire Serial Wire Debug (SWD) interface
• Hardware breakpoint unit for 2 code addresses
• Hardware watchpoint unit for 2 data items
• Micro Trace Buffer for program tracing
On-Chip Memory
• Up to 512 KB Flash
• KW36Z contains 256 KB program flash with ECC and 256 KB FlexNVM.
• KW35Z contains 512 KB program flash with ECC.
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
7
NXP Semiconductors
Feature Descriptions
• Flash implemented as two equal blocks each of 256 KB block. Code can
execute or read from one block while the other block is being erased or
programmed on KW35Z only.
• Firmware distribution protection. Program flash can be marked execute-only
on a per-sector (8 KB) basis to prevent firmware contents from being read by
third parties.
• 64 KB SRAM
• KW36Z contains 8 KB FlexRAM.
• KW35Z contains 8 KB program acceleration RAM.
• Security circuitry to prevent unauthorized access to RAM and flash contents
through the debugger
2.4 System features
Power Management Control Unit (PMC)
• Programmable power saving modes
• Available wake-up from power saving modes via internal and external sources
• Integrated Power-on Reset (POR)
• Integrated Low Voltage Detect (LVD) with reset (brownout) capability
• Selectable LVD trip points
• Programmable Low Voltage Warning (LVW) interrupt capability
• Individual peripheral clocks can be gated off to reduce current consumption
• Internal Buffered bandgap reference voltage
• Factory programmed trim for bandgap and LVD
• 1 kHz Low-power Oscillator (LPO)
DC-DC Converters
• Internal switched mode power supply supporting Buck and Bypass operating
modes
• Buck operation supports external voltage sources of 2.1 V to 3.6 V
• When DC-DC is not used, the device supports an external voltage range of 1.5 V to
3.6 V (1.5 - 3.6 V on VDD_RF1, VDD_RF2, VDD_RF3 and
VDD_1P5OUT_PMCIN pins. 1.71 - 3.6 V on VDD_0, VDD_1, and VDDA pins)
• An external inductor is required to support the Buck mode
Direct Memory Access (DMA) Controller
• All data movement via dual-address transfers: read from source, write to
destination
8
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
Feature Descriptions
• Programmable source and destination addresses and transfer size
• Support for enhanced addressing modes
• 4-channel implementation that performs complex data transfers with minimal
intervention from a host processor
• Internal data buffer, used as temporary storage to support 16- and 32-byte
transfers
• Connections to the crossbar switch for bus mastering the data movement
• Transfer Control Descriptor (TCD) organized to support two-deep, nested transfer
operations
• 32-byte TCD stored in local memory for each channel
• An inner data transfer loop defined by a minor byte transfer count
• An outer data transfer loop defined by a major iteration count
• Channel activation via one of three methods:
• Explicit software initiation
• Initiation via a channel-to-channel linking mechanism for continuous
transfers
• Peripheral-paced hardware requests, one per channel
• Fixed-priority and round-robin channel arbitration
• Channel completion reported via optional interrupt requests
• One interrupt per channel, optionally asserted at completion of major iteration
count
• Optional error terminations per channel and logically summed together to form
one error interrupt to the interrupt controller
• Optional support for scatter/gather DMA processing
• Support for complex data structures
DMA Channel Multiplexer (DMA MUX)
• 4 independently selectable DMA channel routers
• 2 periodic trigger sources available
• Each channel router can be assigned to 1 of the peripheral DMA sources
COP Watchdog Module
• Independent clock source input (independent from CPU/bus clock)
• Choice between two clock sources
• LPO oscillator
• Bus clock
System Clocks
• Both 26 MHz and 32 MHz crystal reference oscillator supported for Bluetooth LE
and Generic FSK modes
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
9
NXP Semiconductors
Feature Descriptions
• MCU can derive its clock either from the crystal reference oscillator or the
Frequency-locked Loop (FLL)1
• 32.768 kHz crystal reference oscillator used to maintain precise Bluetooth Low
Energy timing in low-power modes
• Multipurpose Clock Generator (MCG)
• Internal reference clocks — Can be used as a clock source for other on-chip
peripherals
• On-chip RC oscillator range of 31.25 kHz to 39.0625 kHz with 2% accuracy
across full temperature range
• On-chip 4 MHz oscillator with 5% accuracy across full temperature range
• Frequency-locked Loop (FLL) controlled by internal or external reference
• 20 MHz to 48 MHz FLL output
Unique Identifiers
• 80-bit Unique ID represents a unique identifier for each chip
• 40-bit unique Media Access Control (MAC) address, which can be used to build a
unique 48-bit Bluetooth Low Energy MAC address
2.5 Peripheral features
16-bit Analog-to-Digital Converter (ADC)
• Linear successive approximation algorithm with 16-bit resolution
• Output formatted in differential-ended 16-, 13-, 11-, and 9-bit mode
• Output formatted in single-ended 16-, 12-, 10-, and 8-bit mode
• Single or continuous conversion
• Configurable sample time and conversion speed/power
• Conversion rates in 16-bit mode with no averaging up to ~500Ksamples/sec
• Input clock selection
• Operation in low-power modes for lower noise operation
• Asynchronous clock source for lower noise operation
• Selectable asynchronous hardware conversion trigger
• Automatic compare with interrupt for less-than, or greater than, or equal to
programmable value
• Temperature sensor
• Battery voltage measurement
• Hardware average function
• Selectable voltage reverence
• Self-calibration mode
1. Clock options can have restrictions based on the chosen SoC configuration.
10
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
Feature Descriptions
High-Speed Analog Comparator (CMP)
• 6-bit DAC programmable reference generator output
• Up to eight selectable comparator inputs; each input can be compared with any
input by any polarity sequence
• Selectable interrupt on rising edge, falling edge, or either rising or falling edges of
comparator output
• Two performance modes:
• Shorter propagation delay at the expense of higher power
• Low-power, with longer propagation delay
• Operational in all MCU power modes except VLLS0 mode
Voltage Reference(VREF1)
• Programmable trim register with 0.5 mV steps, automatically loaded with factory
trimmed value upon reset
• Programmable buffer mode selection:
• Off
• Bandgap enabled/standby (output buffer disabled)
• High-power buffer mode (output buffer enabled)
• 1.2 V output at room temperature
• VREF_OUT output signal
Low-power Timer (LPTMR)
• One channel
• Operation as timer or pulse counter
• Selectable clock for prescaler/glitch filter
• 1 kHz internal LPO
• External low-power crystal oscillator
• Internal reference clock
• Configurable glitch filter or prescaler
• Interrupt generated on timer compare
• Hardware trigger generated on timer compare
• Functional in all power modes
Timer/PWM (TPM)
• TPM0: 4 channels, TPM1 and TPM2: 2 channels each
• Selectable source clock
• Programmable prescaler
• 16-bit counter supporting free-running or initial/final value, and counting is up or
up-down
• Input capture, output compare, and edge-aligned and center-aligned PWM modes
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
11
NXP Semiconductors
Feature Descriptions
• Input capture and output compare modes
• Generation of hardware triggers
• TPM1 and TPM2: Quadrature decoder with input filters
• Global time base mode shares single time base across multiple TPM instances
Programmable Interrupt Timer (PIT)
• Up to 2 interrupt timers for triggering ADC conversions
• 32-bit counter resolution
• Clocked by bus clock frequency
Real-Time Clock (RTC)
• 32-bit seconds counter with 32-bit alarm
• Can be invalidated on detection of tamper detect
• 16-bit prescaler with compensation
• Register write protection
• Hard Lock requires MCU POR to enable write access
• Soft lock requires POR or software reset to enable write/read access
• Capable of waking up the system from low-power modes
Inter-Integrated Circuit (I2C)
• Two channels
• Compatible with I2C bus standard and SMBus Specification Version 2 features
• Up to 400 kHz operation
• Multi-master operation
• Software programmable for one of 64 different serial clock frequencies
• Programmable slave address and glitch input filter
• Interrupt driven byte-by-byte data transfer
• Arbitration lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Bus busy detection broadcast and 10-bit address extension
• Address matching causes wake-up when processor is in low-power mode
LPUART
• One channel (2 channels on KW36Z)
• Full-duplex operation
• Standard mark/space Non-return-to-zero (NRZ) format
• 13-bit baud rate selection with fractional divide of 32
• Programmable 8-bit or 9-bit data format
• Programmable 1 or 2 stop bits
12
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
Feature Descriptions
• Separately enabled transmitter and receiver
• Programmable transmitter output polarity
• Programmable receive input polarity
• 13-bit break character option
• 11-bit break character detection option
• Two receiver wake-up methods:
• Idle line wake-up
• Address mark wake-up
• Address match feature in receiver to reduce address mark wake-up ISR overhead
• Interrupt or DMA driven operation
• Receiver framing error detection
• Hardware parity generation and checking
• Configurable oversampling ratio to support from 1/4 to 1/32 bit-time noise
detection
• Operation in low-power modes
• Hardware Flow Control RTS\CTS
• Functional in Stop/VLPS modes
• Break detect supporting LIN
Serial Peripheral Interface (SPI)
• Two independent SPI channels
• Master and slave mode
• Full-duplex, three-wire synchronous transfers
• Programmable transmit bit rate
• Double-buffered transmit and receive data registers
• Serial clock phase and polarity options
• Slave select output
• Control of SPI operation during wait mode
• Selectable MSB-first or LSB-first shifting
• Support for both transmit and receive by DMA
Carrier Modulator Timer (CMT)
• Four modes of operation
• Time; with independent control of high and low times
• Baseband
• Frequency shift key (FSK)
• Direct software control of CMT_IRO signal
• Extended space operation in time, baseband, and FSK modes
• Selectable input clock divider
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
13
NXP Semiconductors
Feature Descriptions
• Interrupt on end of cycle
• Ability to disable CMT_IRO signal and use as timer interrupt
General Purpose Input/Output (GPIO)
• Hysteresis and configurable pull up device on all input pins
• Independent pin value register to read logic level on digital pin
• All GPIO pins can generate IRQ and wake-up events
• Configurable drive strength on some output pins
• GPIO can be configured to function as a interrupt driven keyboard scanning matrix
• In the 48-pin package there are a total of 25 digital pins
• In the 40-pin package there are a total of 18 digital pins
FlexCAN (for KW36Z only)
• Full implementation of the CAN with Flexible Data Rate (CAN FD) protocol
specification and CAN protocol specification, Version 2.0 B
• Flexible Message Buffers (MBs); there are total 32 MBs of 8 bytes data length
each, configurable as Rx or Tx, all supporting standard and extended messages
• Programmable clock source to the CAN Protocol Interface, either peripheral clock
or oscillator clock
• Capability to select priority between mailboxes and Rx FIFO during matching
process
• Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either
128 extended, 256 standard, or 512 partial (8 bit) IDs, with up to 32 individual
masking capability
2.6 Security Features
Advanced Encryption Standard Accelerator(AES-128 Accelerator)
The Advanced Encryption Standard Accelerator (AESA) module is a standalone
hardware coprocessor capable of accelerating the 128-bit advanced encryption standard
(AES) cryptographic algorithms.
The AESA engine supports the following cryptographic features.
LTC includes the following features:
• Cryptographic authentication
• Message Authentication Codes (MAC)
14
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
Feature Descriptions
• Cipher-based MAC (AES-CMAC)
• Extended cipher block chaining message authentication code (AES-
XCBC-MAC)
• Auto padding
• Integrity Check Value(ICV) checking
• Authenticated encryption algorithms
• Counter with CBC-MAC (AES-CCM)
• Symmetric key block ciphers
• AES (128-bit keys)
• Cipher modes:
• AES-128 modes
• Electronic Codebook (ECB)
• Cipher Block Chaining (CBC)
• Counter (CTR)
• Secure scan
True Random Number Generator (TRNG)
True Random Number Generator (TRNG) is a hardware accelerator module that
constitutes a high-quality entropy source.
• TRNG generates a 512-bit (4x 128-bit) entropy as needed by an entropy-
consuming module, such as a deterministic random number generator.
• TRNG output can be read and used by a deterministic pseudo-random number
generator (PRNG) implemented in software.
• TRNG-PRNG combination achieves NIST-compliant true randomness and
cryptographic-strength random numbers using the TRNG output as the entropy
source.
• A fully FIPS 180 compliant solution can be realized using the TRNG together
with a FIPS-compliant deterministic random number generator and the SoC-level
security.
Flash Memory Protection
The on-chip flash memory controller enables the following useful features:
• Program flash protection scheme prevents accidental program or erase of stored
data.
• Automated, built-in, program and erase algorithms with verify.
• Read access to one program flash block is possible while programming or erasing
data in the other program flash block.
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
15
NXP Semiconductors
Transceiver Description
3 Transceiver Description
• Direct Conversion Receiver (Zero IF)
• Constant Envelope Transmitter
• 2.36 GHz to 2.483 GHz PLL Range
• Low Transmit and Receive Current Consumption
• Low BOM
3.1 Key Specifications
KW36Z/35Z meets or exceeds all Bluetooth Low Energy version 5.0 performance
specifications. The key specifications for the KW36Z/35Z are:
Frequency Band:
• ISM Band: 2400 to 2483.5 MHz
• MBAN Band: 2360 to 2400 MHz
Bluetooth Low Energy version 5.0 modulation scheme:
• Symbol rate: 1000 kbit/s
• Modulation: GFSK
• Receiver sensitivity: –95 dBm, typical
• Programmable transmitter output power: –30 dBm to +5 dBm
Generic FSK modulation scheme:
• Symbol rate: 250, 500 and 1000 kbit/s
• Modulation(s): GFSK (modulation index = 0.32, 0.5, 0.7 and 1.0, BT =0.3, 0.5, and
0.7), FSK and MSK
• Receiver Sensitivity: Mode and data rate dependent. –99 dBm typical for GFSK
(r=250 kbit/s, BT = 0.5, h = 0.5)
3.2 Channel Map Frequency Plans
16
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
Transceiver Description
3.2.1 Channel Plan for Bluetooth Low Energy
This section describes the frequency plan / channels associated with 2.4 GHz ISM and
MBAN bands for Bluetooth Low Energy.
2.4 GHz ISM Channel numbering:
• Fc=2402 + k * 2 MHz, k=0,.........,39.
MBAN Channel numbering:
• Fc=2360 + k in MHz, for k=0,.....,39
where k is the channel number.
Table 1. 2.4 GHz ISM and MBAN frequency plan and channel designations
2.4 GHz ISM1
MBAN2
2.4GHz ISM + MBAN
Channel
Channel
Freq (MHz)
2402
2404
2406
2408
2410
2412
2414
2416
2418
2420
2422
2424
2426
2428
2430
2432
2434
2436
2438
2440
2442
2444
2446
2448
Channel
Freq (MHz)
2360
2361
2362
2363
2364
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
Freq (MHz)
2390
2391
2392
2393
2394
2395
2396
2397
2398
2402
2404
2406
2408
2410
2412
2414
2416
2418
2420
2422
2424
2426
2428
2430
0
1
0
1
28
29
30
31
32
33
34
35
36
0
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Table continues on the next page...
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
17
NXP Semiconductors
Transceiver Description
Table 1. 2.4 GHz ISM and MBAN frequency plan and channel designations (continued)
2.4 GHz ISM1
MBAN2
2.4GHz ISM + MBAN
Channel
Channel
Freq (MHz)
2450
2452
2454
2456
2458
2460
2462
2464
2466
2468
2470
2472
2474
2476
2478
2480
Channel
24
Freq (MHz)
2384
2385
2386
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
Freq (MHz)
2432
2434
2436
2438
2440
2442
2444
2446
2448
2450
2452
2454
2456
2476
2478
2480
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
15
16
17
18
19
20
21
22
23
24
25
26
27
37
38
39
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
1. ISM frequency of operation spans from 2400.0 MHz to 2483.5 MHz
2. Per FCC guideline rules, Bluetooth Low Energy single mode operation is allowed in these channels.
3.2.2 Other Channel Plans
The RF synthesizer can be configured to use any channel frequency between 2.36 and
2.487 GHz.
3.3 Transceiver Functions
Receive
The receiver architecture is Zero IF (ZIF) where the received signal after passing
through RF front end is down-converted to a baseband signal. The signal is filtered and
amplified before it is fed to analog-to-digital converter. The digital signal then
decimates to a baseband clock frequency before it digitally processes, demodulates and
passes on to packet processing/link-layer processing.
18
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
Transceiver Electrical Characteristics
Transmit
The transmitter transmits GFSK/FSK modulation having power and channel selection
adjustment per user application. After the channel of operation is determined, coarse
and fine-tuning is executed within the Frac-N PLL to engage signal lock. After signal
lock is established, the modulated buffered signal is routed to a multi-stage amplifier
for transmission..
4 Transceiver Electrical Characteristics
4.1 Radio operating conditions
Table 2. Radio operating conditions
Characteristic
Symbol
fin
Min
2.360
–40
Typ
—
Max
2.480
105
Unit
GHz
°C
Input Frequency
Ambient Temperature Range
Maximum RF Input Power
TA
25
—
Pmax
fref
—
10
dBm
Crystal Reference Oscillator Frequency
26 MHz or 32 MHz
1
1. The recommended crystal accuracy is 40 ppm including initial accuracy, mechanical, temperature, and aging factors.
4.2 Receiver Feature Summary
Table 3. Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise
noted)
Characteristic1
Symbol
Ipdn
Min.
—
Typ.
200
6.3
Max.
1000
—
Unit
nA
Supply current power down on VDD_RFx supplies
Supply current Rx On with DC-DC converter enable
(Buck; VDCDC_IN = 3.6 V, VDD_1P5_buck=1.5 V) , 2
IRxon
—
mA
Supply current Rx On with DC-DC converter disabled
(Bypass) 2
IRxon
—
17.2
—
mA
Input RF Frequency
fin
2.360
—
—
2.4835
—
GHz
dBm
dBm
dB
GFSK Rx Sensitivity(250 kbit/s GFSK-BT=0.5, h=0.5)
Bluetooth LE Rx Sensitivity 3
SENSGFSK
SENSBLE
NFHG
–99
–95
7.5
—
—
Noise Figure for maximum gain mode @ typical
sensitivity
—
—
Table continues on the next page...
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
19
NXP Semiconductors
Transceiver Electrical Characteristics
Table 3. Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise
noted) (continued)
Characteristic1
Symbol
RSSIRange
RSSIRes
Min.
–100
—
Typ.
—
Max.
55
—
2
Unit
dBm
dB
Receiver Signal Strength Indicator Range4
Receiver Signal Strength Indicator Resolution
Typical RSSI variation over frequency
Typical RSSI variation over temperature
Narrowband RSSI accuracy6
1
–2
—
dB
–2
—
2
dB
RSSIAcc
–3
—
3
dB
Bluetooth LE Co-channel Interference (Wanted signal at
–67 dBm, BER <0.1%. Measurement resolution 1
MHz).
–7
dB
Adjacent/Alternate Channel Performance7
Bluetooth LE Adjacent +/–1 MHz Interference offset
(Wanted signal at –67 dBm, BER <0.1%. Measurement
resolution 1 MHz.)
SELBLE, 1 MHz
SELBLE, 2 MHz
SELBLE, 3 MHz
SELBLE, 4+ MHz
—
—
—
—
2
—
—
—
—
dB
dB
dB
dB
Bluetooth LE Adjacent +/–2 MHz Interference offset
(Wanted signal at –67 dBm, BER <0.1%. Measurement
resolution 1 MHz.)
43
50
50
Bluetooth LE Alternate +/–3 MHz Interference offset
(Wanted signal at –67 dBm, BER <0.1%. Measurement
resolution 1 MHz.)
Bluetooth LE Alternate ≥ +/–4 MHz Interference offset
(Wanted signal at –67 dBm, BER <0.1%. Measurement
resolution 1 MHz.)
Intermodulation Performance
Bluetooth LE Intermodulation with continuous wave
interferer at 3 MHz and modulated interferer is at
MHz (Wanted signal at –67 dBm, BER<0.1%.)
—
—
–23
–24
—
—
dBm
dBm
6
Bluetooth LE Intermodulation with continuous wave
interferer at 5 MHz and modulated interferer is at 10
MHz (Wanted signal at –67 dBm, BER<0.1%.)
Blocking Performance
Bluetooth LE Out of band blocking from 30 MHz to 1000
MHz and 4000 MHz to 5000 MHz (Wanted signal at –67
dBm, BER<0.1%. Interferer continuous wave signal.)8
—
—
–2
—
—
—
—
dBm
dBm
Bluetooth LE Out of band blocking from 1000 MHz to
2000 MHz and 3000 MHz to 4000 MHz (Wanted signal
at –67 dBm, BER<0.1%. Interferer continuous wave
signal.)
–8.4
Bluetooth LE Out of band blocking from 2001 MHz to
2339 MHz and 2484 MHz to 2999 MHz (Wanted signal
at –67 dBm, BER<0.1%. Interferer continuous wave
signal.)9
—
—
–17
—
—
—
—
dBm
dBm
Bluetooth LE Out of band blocking from 5000 MHz to
12750 MHz (Wanted signal at –67 dBm, BER<0.1%.
Interferer continuous wave signal.)9
10
Table continues on the next page...
20
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
Transceiver Electrical Characteristics
Table 3. Top-Level Receiver Specifications (TA=25 °C, nominal process unless otherwise
noted) (continued)
Characteristic1
Symbol
Min.
Typ.
Max.
Unit
Spurious Emission < 1.6 MHz offset (Measured with
100 kHz resolution and average detector. Device
transmit on RF channel with center frequency fc and
spurious power measured in 1 MHz at RF frequency f),
where |f-fc|< 1.6 MHz
—
—
–54
—
dBc
Spurious Emission > 2.5 MHz offset (Measured with
100 kHz resolution and average detector. Device
transmit on RF channel with center frequency fc and
spurious power measured in 1 MHz at RF frequency f),
where |f-fc|> 2.5 MHz10
—
—
–70
—
dBc
1. All the Rx parameters are measured at the KW36Z/35Z RF pins.
2. Transceiver power consumption.
3. Measured at 0.1% BER using 37 byte long packets in maximum gain mode and nominal conditions.
4. Narrow-band RSSI mode.
5. With RSSI_CTRL_0.RSSI_ADJ field calibrated to account for antenna to RF input losses.
6. With one point calibration over frequency and temperature.
7. Bluetooth LE adjacent and alternate selectivity performance is measured with modulated interference signals.
8. Exceptions allowed for carrier frequency sub harmonics.
9. Exceptions allowed for carrier frequency harmonics.
10. Exceptions allowed for twice the reference clock frequency(fref) multiples.
Table 4. Receiver Specifications with Generic FSK Modulations
Adjacent/Alternate Channel Selectivity (dB)1
Modulation
Type
Data
Rate
(kbit/s)
Channel
BW (kHz) Sensitivity signal
Typical
Desired Interferer Interferer Interferer Interferer
Co-
channel
at –/+1*
channel
BW
at –/+ 2*
channel
BW
at –/+ 3*
channel
BW
at –/+ 4*
channel
BW
(dBm)
level
(dBm)
offset
offset
offset
offset
GFSK BT =
0.5, h=0.5
1000
500
2000
1000
500
–95
–97
–99
–89
–92
–93
–97
–98
–99
–91
–93
–95
–96
–97
–67
–85
–85
–67
–85
–85
–85
–85
–85
–85
–85
–85
–85
–85
43
40
30
10
22
20
45
40
30
40
35
30
44
40
50
50
40
38
31
25
50
50
40
46
46
40
53
50
55
55
50
42
37
30
57
55
50
53
50
40
57
55
50
55
50
47
42
34
60
55
50
55
53
50
60
55
–7
–7
250
–7
GFSK, BT =
0.5, h=0.3
1000
500
1000
800
–10
–10
–13
–7
250
500
GFSK, BT =
0.5, h=0.7
1000
500
2000
1000
600
–7
250
–7
GMSK
BT=0.3
1000
500
1600
800
–8
–7
250
500
–7
GMSK, BT = 1000
2000
1000
–7
0.7
500
–7
Table continues on the next page...
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
21
NXP Semiconductors
Transceiver Electrical Characteristics
Table 4. Receiver Specifications with Generic FSK Modulations
(continued)
Adjacent/Alternate Channel Selectivity (dB)1
Modulation
Type
Data
Rate
(kbit/s)
Channel
BW (kHz) Sensitivity signal
Typical
Desired Interferer Interferer Interferer Interferer
Co-
channel
at –/+1*
channel
BW
at –/+ 2*
channel
BW
at –/+ 3*
channel
BW
at –/+ 4*
channel
BW
(dBm)
level
(dBm)
offset
offset
offset
offset
250
1000
500
600
3000
1600
800
–99
–96
–97
–99
–96
–97
–98
–85
–85
–85
–85
–85
–85
–85
30
43
43
35
45
40
35
40
53
50
45
55
45
45
50
60
60
55
55
50
45
50
63
60
55
59
50
50
–7
–7
–8
–7
–8
–8
–8
Generic
MSK
250
GFSK
BT=0.5, h=1
1000
500
3000
1400
800
250
1. Selectivity measured with an unmodulated blocker except for GFSK BT=0.5, h=0.5 1 Mbit/s and GFSK BT=0.5, h=0.32 1
Mbit/s. The desired signal is set at –85 dBm.
4.3 Transmit and PLL Feature Summary
• Supports constant envelope modulation of 2.4 GHz ISM and 2.36 GHz MBAN
frequency bands
• Fast PLL Lock time: < 25 µs
• Reference Frequency:
• 26 MHz and 32 MHz crystals supported for Bluetooth LE and Generic FSK
modes
Table 5. Top-Level Transmitter Specifications (TA=25 °C, nominal process unless otherwise
noted)
Characteristic1
Symbol
Ipdn
Min.
—
Typ.
200
5.7
Max.
—
Unit
nA
Supply current power down on VDD_RFx supplies
Supply current Tx On with PRF = 0 dBm and DC-DC
converter enabled (Buck; VDDDCDC_in = 3.6 V,
VDD_1P5_buck=1.5 V) , 2
ITxone
—
—
mA
Supply current Tx On with PRF = 0 dBm and DC-DC
converter disabled (Bypass) 2
ITxond
—
—
16
—
—
mA
mA
Supply current Tx On with PRF = +3.5 dBm and DC-DC
converter enabled (Buck; VDDDCDC_in = 3.6 V,
VDD_1P5_buck=1.5 V)2
ITX3.5dBm
6.9
Supply current Tx On with PRF = +3.5 dBm and DC-DC
converter disabled (Bypass)2
ITX3.5dBmb
—
19
—
mA
Table continues on the next page...
22
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
Transceiver Electrical Characteristics
Table 5. Top-Level Transmitter Specifications (TA=25 °C, nominal process unless otherwise
noted) (continued)
Characteristic1
Symbol
Min.
Typ.
Max.
Unit
Supply current Tx On with PRF = +5 dBm and DC-DC
converter enabled (Buck; VDDDCDC_in = 3.6 V,
VDD_1P5_buck=1.55 V, LDO-HF bumped)2, 3
ITX5dBm
—
8.0
—
mA
Supply current Tx On with PRF = +5 dBm and DC-DC
converter disabled (Bypass, LDO-HF bumped)2, 3
ITX5dBmb
—
21
—
mA
Output RF Frequency
fRFout
2.360
—
—
+5
2.4835
—
GHz
dBm
dBm
dBm
dB
Maximum RF Output Power; LDO-HF bumped 4
Maximum RF Output power, nominal power supply 5
Minimum RF Output power, nominal power supply 5
RF Output power control range
PRF,maxV
PRF,maxn
PRF,minn
PRFCR
—
+3.5
–30
34
—
—
—
—
—
Bluetooth LE Tx Output Spectrum 20dB BW
TXBWBLE
Δf1avg,BLE
1.0
—
MHz
kHz
Bluetooth LE average frequency deviation using a
00001111 modulation sequence
250
220
Bluetooth LE average frequency deviation using a
01010101 modulation sequence
Δf2avg,BLE
kHz
Bluetooth LE RMS FSK Error
FSKerr BLE
,
3%
3
Bluetooth LE Maximum Deviation of the Center
Frequency6
Fcdev,BLE
—
—
—
—
kHz
dBm
dBm
Bluetooth LE Adjacent Channel Transmit Power at 2
MHz offset7
PRF2MHz,BLE
PRF3MHz,BLE
—
—
–55
–59
Bluetooth LE Adjacent Channel Transmit Power at >= 3
MHz offset7
Bluetooth LE Frequency Hopping Support
YES
–46
Second Harmonic of Transmit Carrier Frequency (Pout
=
TXH2
TXH3
—
—
—
—
dBm/MHz
dBm/MHz
, 8
PRF,max
)
Third Harmonic of Transmit Carrier Frequency (Pout
=
–58
8
PRF,max
)
1. All the Tx parameters are measured at test hardware SMA connector.
2. Transceiver power consumption.
3. VDD_RFx shall be equal to or higher than 1.55 V to support a TX Pout of +5 dBm.
4. Measured at KW36Z/35Z RF pins, with BB_LDO_HF_TRIM=1.44 V.
5. Measured at the KW36Z/35Z RF pins.
6. Maximum drift of carrier frequency of the PLL during a Bluetooth LE packet with a nominal 32 MHz reference crystal.
7. Measured at Pout = +5 dBm and recommended Tx match.
8. Harmonic levels based on recommended 2 component match. Transmit harmonic levels depend on the quality of
matching components. Additional harmonic margin using a third matching component (1x shunt capacitor) is possible.
Transmit PA driver output as a function of the PA_POWER[5:0] field when measured
at the IC pins is as follows:
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
23
NXP Semiconductors
Transceiver Electrical Characteristics
Figure 3. TX Pout (dBm) as function TX-PA Power Code for default LDO-HF
Table 6. Transmit Output Power as a function of PA_POWER[5:0] with default LDO-HF
TX Pout (dBm)1
PA_POWER[5:0]
T = –40 °C
–30.1
–24.0
–17.9
–14.5
–12.0
–10.1
–8.5
T = 25 °C
–31.1
–25.0
–19.0
–15.6
–13.1
–11.2
–9.6
T = 105 °C
–32.6
–26.4
–20.4
–17.0
–14.5
–12.6
–11.0
–9.7
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
–7.2
–8.3
–6.1
–7.2
–8.6
–5.1
–6.2
–7.6
–4.2
–5.3
–6.7
–3.4
–4.5
–5.9
–2.7
–3.8
–5.2
–2.0
–3.1
–4.5
–1.4
–2.5
–3.9
–0.8
–1.9
–3.3
–0.3
–1.4
–2.8
Table continues on the next page...
24
NXP Semiconductors
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
Transceiver Electrical Characteristics
Table 6. Transmit Output Power as a function of PA_POWER[5:0] with default LDO-HF
(continued)
TX Pout (dBm)1
PA_POWER[5:0]
T = –40 °C
0.2
T = 25 °C
–1.0
–0.5
–0.1
0.3
T = 105 °C
–2.4
–1.9
–1.5
–1.1
–0.7
–0.3
0.0
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
0.6
1.1
1.5
1.9
0.7
2.2
1.1
2.6
1.4
2.9
1.8
0.3
3.2
2.1
0.6
3.5
2.4
0.9
3.7
2.6
1.2
3.9
2.9
1.5
4.2
3.1
1.7
4.4
3.3
1.9
4.5
3.5
2.1
1. Tx continuous wave power output at the RF pins with the recommended matching components mounted on PCB.
Figure 4. TX Pout (dBm) as a function of TX-PA Power Code for LDO-HF bumped
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
25
NXP Semiconductors
System and Power Management
Table 7. Transmit Output Power as a function of PA_POWER[5:0] with LDO-HF Bumped
TX Pout (dBm)1
PA_POWER[5:0]
T = –40 °C
–28.5
–22.4
–16.4
–12.9
–10.4
–8.5
–6.9
–5.6
–4.4
–3.4
–2.5
–1.7
–0.9
–0.3
0.4
T = 25 °C
–29.6
–23.4
–17.5
–13.9
–11.5
–9.5
–8.0
–6.6
–5.5
–4.5
–3.6
–2.8
–2.0
–1.4
–0.7
–0.1
0.3
T = 105 °C
–30.4
–24.2
–18.3
–14.8
–12.3
–10.4
–8.8
–7.5
–6.3
–5.3
–4.4
–3.6
–2.9
–2.2
–1.6
–1.0
–0.5
0.0
1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
1.0
1.4
2.0
0.9
2.4
1.3
0.4
2.9
1.8
0.9
3.3
2.2
1.3
3.7
2.6
1.7
4.1
3.0
2.1
4.5
3.4
2.5
4.8
3.7
2.8
5.2
4.0
3.1
5.5
4.4
3.4
5.8
4.6
3.7
6.0
4.9
4.0
6.3
5.2
4.2
6.5
5.4
4.5
6.7
5.6
4.7
1. Tx continuous wave power output at the RF pins with the recommended matching components mounted on PCB.
5 System and Power Management
26
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
System and Power Management
5.1 Power Management
The KW36Z/35Z includes internal power management features that can be used to
control the power usage. The power management of the KW36Z/35Z includes Power
Management Controller (PMC) and a DC-DC converter which can operate in a buck
or bypass configuration. The PMC is designed such that the RF radio remains in state-
retention while the core is in various stop modes. It makes sure that the device can
stay in low current consumption mode while the RF radio can wake-up quick enough
for communication.
5.1.1 DC-DC Converter
The features of the DC-DC converter include the following:
• Single inductor, multiple outputs.
• Buck mode (pin selectable; CFG=VDCDC_IN).
• Continuous or pulsed operation (hardware/software configurable).
• Power switch input to allow external control of power up, and to select DC-DC
bypass mode in which all the SoC power supplies (see Table 3) are externally
provided.
• Output signal to indicate power stable. Purpose is for the rest of the chip to be
used as a POR.
• Scaled battery output voltage suitable for SAR ADC utilization.
• Internal oscillator for support when the reference oscillator is not present.
5.2 Modes of Operation
The Arm Cortex-M0+ core in the KW36Z/35Z has three primary modes of operation:
Run, Wait, and Stop modes. For each run mode, there is a corresponding wait and stop
mode. Wait modes are similar to Arm sleep modes. Stop modes are similar to Arm
deep sleep modes. The very low-power run (VLPR) operation mode can drastically
reduce runtime power when the maximum bus frequency is not required to handle the
application needs.
The WFI instruction invokes both wait and stop modes. The primary modes are
augmented in a number of ways to provide lower power based on application needs.
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
27
NXP Semiconductors
System and Power Management
5.2.1 Power modes
The power management controller (PMC) provides multiple power options to allow the
user to optimize power consumption for the level of functionality needed.
Depending on the stop requirements of the user application, various stop modes are
available that provide state retention, partial power down, or full power down of certain
logic and/or memory. I/O states are held in all modes of operation. The following table
compares the various power modes available.
For each run mode, there is a corresponding wait and stop mode. Wait modes are
similar to Arm sleep modes. Stop modes (VLPS, STOP) are similar to Arm sleep deep
mode. The very-low-power run (VLPR) operating mode can drastically reduce runtime
power when the maximum bus frequency is not required to handle the application
needs.
The three primary modes of operation are run, wait, and stop. The WFI instruction
invokes either wait or stop depending on the SLEEPDEEP bit in Cortex-M0+ System
Control Register. The primary modes are augmented in a number of ways to provide
lower power based on application needs.
Table 8. Power modes (At 25 deg C)
Power mode
Description
CPU
Radio
recovery
method
Normal Run (all
Allows maximum performance of chip.
—
Radio can be active
peripherals clock off)
Normal Wait - via WFI Allows peripherals to function, while allowing CPU to
go to sleep reducing power.
Interrupt
Interrupt
Interrupt
Normal Stop - via
WFI
Places chip in static state. Lowest power mode that
retains all registers while maintaining LVD protection.
PStop2 (Partial Stop Core and system clocks are gated. Bus clock
2)
remains active. Masters and slaves clocked by bus
clock remain in Run or VLPRun mode. The clock
generators in MCG and the on-chip regulator in the
PMC also remain in Run or VLPRun mode.
PStop1 (Partial Stop Core, system clocks, and bus clock are gated. All
Interrupt
—
1)
bus masters and slaves enter Stop mode. The clock
generators in MCG and the on-chip regulator in the
PMC also remain in Run or VLPRun mode.
VLPR (Very Low-
power Run) (all
peripherals off)
Reduced frequency (1 MHz) Flash access mode,
regulator in low-power mode, LVD off. Internal
oscillator can provide low-power 4 MHz source for
core. (Values @2 MHz core/ 1 MHz bus and flash,
module off, execution from flash).
Radio operation is possible
only when DC-DC is
configured for continuous
mode.1 However, there may
be insufficient MIPS with a 4
MHz MCU to support much in
the way of radio operation.
Biasing is disabled when DC-DC is configured for
continuous mode in VLPR/W
Table continues on the next page...
28
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
System and Power Management
Table 8. Power modes (At 25 deg C) (continued)
Power mode
Description
CPU
Radio
recovery
method
VLPW (Very Low-
Similar to VLPR, with CPU in sleep to further reduce
Interrupt
power Wait) - via WFI power. (Values @4 MHz core/ 1 MHz bus, module
(all peripherals off)
off)
Biasing is disabled when DC-DC is configured for
continuous mode in VLPR/W
VLPS (Very Low-
Places MCU in static state with LVD operation off.
Interrupt
power Stop) via WFI Lowest power mode with ADC and all pin interrupts
functional. LPTMR, RTC, CMP can be operational.
Biasing is disabled when DC-DC is configured for
continuous mode in VLPS.
LLS3 (Low Leakage State retention power mode. LLWU, LPTMR, RTC,
Wake-up
Interrupt
Radio SOG is in state
retention in LLSx. The
Bluetooth LE/Generic FSK
DSM2 logic can be active
using the 32 kHz clock
Stop)
CMP can be operational. All of the radio Sea of
Gates(SOG) logic is in state retention.
LLS2 (Low Leakage State retention power mode. LLWU, LPTMR, RTC,
Wake-up
Interrupt
Stop)
CMP can be operational. 16 KB or 32 KB of
programmable RAM can be powered on. All of the
radio SOG logic is in state retention.
VLLS3 (Very Low
Leakage Stop3)
Full SRAM retention. LLWU, LPTMR, RTC, CMP can
be operational. All of the radio SOG logic is in state
retention.
Wake-up
Reset
Radio SOG is in state
retention in VLLS3/2. The
Bluetooth LE/Generic FSK
DSM logic can be active
using the 32 kHz clock.
VLLS2 (Very Low
Leakage Stop2)
Partial SRAM retention. 16 KB or 32 KB of
programmable RAM can be powered on. LLWU,
LPTMR, RTC, CMP can be operational. All of the
radio SOG logic is in state retention.
Wake-up
Reset
VLLS1 (Very Low
Leakage Stop1) with file remains powered for customer-critical data.
RTC + 32 kHz OSC
All SRAM powered off. The 32-byte system register
Wake-up
Reset
Radio operation not
supported. The Radio SOG is
power-gated in VLLS1. Radio
state is lost at VLLS1 and
lower power states.
LLWU, LPTMR, RTC, CMP can be operational.
Radio logic is power gated.
VLLS1 (Very Low
Leakage Stop1) with file remains powered for customer-critical data.
All SRAM powered off. The 32-byte system register
Wake-up
Reset
LPTMR + LPO
LLWU, LPTMR, RTC, CMP can be operational.
VLLS0 (Very Low
Leakage Stop0) with
Brown-out Detection
VLLS0 is not supported with DC-DC.
Wake-up
Reset
Radio operation not
supported. The Radio digital
is power-gated in VLLS0.
The 32-byte system register file remains powered for
customer-critical data. Disable all analog modules in
PMC and retains I/O state and DGO state. LPO
disabled, POR brown-out detection enabled, Pin
interrupt only. Radio logic is power gated.
VLLS0 (Very Low
Leakage Stop0)
without Brown-out
Detection
VLLS0 is not supported with DC-DC buck
configuration but is supported with bypass
configuration.
Wake-up
Reset
The 32-byte system register file remains powered for
customer-critical data. Disable all analog modules in
PMC and retains I/O state and DGO state. LPO
disabled, POR brown-out detection disabled, Pin
interrupt only. Radio logic is power gated.
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
29
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
1. Biasing is disabled, but the Flash is in a low-power mode for VLPx, so this configuration can realize some power savings
over use of Run/Wait/Stop.
2. DSM refers to Radio's deep sleep mode. DSM does not refer to the Arm sleep deep mode.
6 KW36Z/35Z Electrical Characteristics
6.1 AC electrical characteristics
Unless otherwise specified, propagation delays are measured from the 50% to the 50%
point, and rise and fall times are measured at the 20% and 80% points, as shown in the
following figure.
High
Low
VIH
80%
50%
20%
Input Signal
Midpoint1
VIL
Fall Time
Rise Time
The midpoint is VIL + (VIH - VIL) / 2
Figure 5. Input signal measurement reference
All digital I/O switching characteristics, unless otherwise specified, assume that the
output pins have the following characteristics.
• CL=30 pF loads
• Slew rate disabled
• Normal drive strength
6.2 Nonswitching electrical specifications
6.2.1 Voltage and current operating requirements
Table 9. Voltage and current operating requirements
Symbol
VDD
Description
Min.
1.71
Max.
3.6
Unit
V
Notes
Supply voltage
VDD_1P5
DCDC VDD_1P5 output pin
1.425
3.6
V
1
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30
NXP Semiconductors
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
KW36Z/35Z Electrical Characteristics
Table 9. Voltage and current operating requirements (continued)
Symbol
Description
Min.
1.71
–0.1
–0.1
Max.
3.6
Unit
V
Notes
VDDA
Analog supply voltage
VDD – VDDA VDD-to-VDDA differential voltage
VSS – VSSA VSS-to-VSSA differential voltage
0.1
V
0.1
V
VIH
Input high voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
0.7 × VDD
—
—
V
V
0.75 × VDD
VIL
Input low voltage
• 2.7 V ≤ VDD ≤ 3.6 V
• 1.7 V ≤ VDD ≤ 2.7 V
—
—
0.35 × VDD
0.3 × VDD
V
V
VHYS
IICIO
Input hysteresis
0.06 × VDD
–3
—
—
V
IO pin negative DC injection current — single pin
• VIN < VSS–0.3V
2
mA
IICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents of 16
contiguous pins
–25
—
mA
• Negative current injection
VODPU
VRAM
Open drain pullup voltage level
VDD
1.2
VDD
—
V
V
3
VDD voltage required to retain RAM
1. This limit applies in any DCDC mode.
2. All I/O pins are internally clamped to VSS through an ESD protection diode. There is no diode connection to VDD. If VIN
greater than VIO_MIN (= VSS–0.3 V) is observed, then there is no need to provide current limiting resistors at the pads.
If this limit cannot be observed then a current limiting resistor is required. The negative DC injection current limiting
resistor is calculated as R = (VIO_MIN - VIN)/|IICIO|.
3. Open drain outputs must be pulled to VDD
.
6.2.2 LVD and POR operating requirements
Table 10. VDD supply LVD and POR operating requirements
Symbol Description
Min.
0.8
Typ.
1.1
Max.
1.5
Unit
V
Notes
VPOR
Falling VDD POR detect voltage
VPOR_VDD_ VDD_1P5 POR threshold
1.25
1.31
1.37
V
1P5
VLVDH
Falling low-voltage detect threshold — high
2.48
2.56
2.64
V
range (LVDV = 01)
Low-voltage warning thresholds — high range
• Level 1 falling (LVWV = 00)
• Level 2 falling (LVWV = 01)
1
VLVW1H
VLVW2H
2.62
2.72
2.70
2.80
2.78
2.88
V
V
Table continues on the next page...
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
31
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
Table 10. VDD supply LVD and POR operating requirements (continued)
Symbol Description
VLVW3H • Level 3 falling (LVWV = 10)
VLVW4H
Min.
Typ.
Max.
Unit
Notes
2.82
2.90
2.98
V
• Level 4 falling (LVWV = 11)
2.92
—
3.00
60
3.08
—
V
VHYSH
VLVDL
Low-voltage inhibit reset/recover hysteresis —
high range
mV
Falling low-voltage detect threshold — low
range (LVDV=00)
1.54
1.60
1.66
V
Low-voltage warning thresholds — low range
• Level 1 falling (LVWV = 00)
1
VLVW1L
VLVW2L
VLVW3L
VLVW4L
1.74
1.84
1.94
2.04
—
1.80
1.90
2.00
2.10
40
1.86
1.96
2.06
2.16
—
V
V
• Level 2 falling (LVWV = 01)
• Level 3 falling (LVWV = 10)
V
• Level 4 falling (LVWV = 11)
V
VHYSL
Low-voltage inhibit reset/recover hysteresis —
low range
mV
VBG
tLPO
Bandgap voltage reference
0.97
900
1.00
1.03
V
Internal low-power oscillator period — factory
trimmed
1000
1100
μs
1. Rising thresholds are falling threshold + hysteresis voltage
6.2.3 Voltage and current operating behaviors
Table 11. Voltage and current operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
VOH
Output high voltage — Normal drive pad (except
RESET_b)
1, 2
VDD – 0.5
VDD – 0.5
VDD – 0.35
—
—
—
V
V
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –2.5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1 mA
VOH
Output high voltage — High drive pad (except
RESET_b)
1, 2
VDD – 0.5
VDD – 0.5
—
—
—
V
V
• 2.7 V ≤ VDD ≤ 3.6 V, IOH = –20 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOH = –10 mA
IOHT
VOL
Output high current total for all ports
Output low voltage — Normal drive pad
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 5 mA
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 2.5 mA
100
mA
1
1
—
—
0.5
0.5
V
V
VOL
Output low voltage — High drive pad
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32
NXP Semiconductors
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
KW36Z/35Z Electrical Characteristics
Table 11. Voltage and current operating behaviors (continued)
Symbol
Description
• 2.7 V ≤ VDD ≤ 3.6 V, IOL = 20 mA
Min.
Max.
Unit
Notes
—
0.5
V
• 1.71 V ≤ VDD ≤ 2.7 V, IOL = 10 mA
—
0.5
V
IOLT
IIN
Output low current total for all ports
—
—
100
500
mA
nA
Input leakage current (per pin) for full temperature
range
3
IIN
IIN
Input leakage current (per pin) at 25 °C
—
—
0.025
5
μA
μA
3
3
Input leakage current (total all pins) for full
temperature range
RPU
Internal pullup resistors
20
50
kΩ
4
1. PTB0-1 and PTC0-3, PTC6, PTC7, PTC17, PTC18 I/O have both high drive and normal drive capability selected by
the associated PTx_PCRn[DSE] control bit. All other GPIOs are normal drive only.
2. The reset pin only contains an active pull-up device when configured as the RESET signal or as a GPIO. When
configured as a GPIO output, it acts as a pseudo open drain output.
3. Measured at VDD = 3.6 V.
4. Measured at VDD supply voltage = VDD min and Vinput = VSS
.
6.2.4 Power mode transition operating behaviors
All specifications except tPOR and VLLSx→RUN recovery times in the following
table assume this clock configuration:
• CPU and system clocks = 48 MHz
• Bus and flash clock = 24 MHz
• FEI clock mode
POR and VLLSx→RUN recovery use FEI clock mode at the default CPU and system
frequency of 21 MHz, and a bus and flash clock frequency of 10.5 MHz.
Table 12. Power mode transition operating behaviors
Symbol
Description
Max.
Unit
Notes
tPOR
After a POR event, amount of time from the point VDD
reaches 1.8 V to execution of the first instruction across the
operating temperature range of the chip.
300
μs
1
• VLLS0 → RUN
169.0
168.9
97.3
μs
μs
μs
• VLLS1 → RUN
• VLLS2 → RUN
Table continues on the next page...
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
33
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
Table 12. Power mode transition operating behaviors (continued)
Symbol
Description
Max.
97.3
6.3
Unit
Notes
• VLLS3 → RUN
μs
• LLS → RUN
• VLPS → RUN
• STOP → RUN
μs
6.2
μs
6.2
μs
1. Normal boot (FTFA_FOPT[LPBOOT]=11). When the DC-DC converter is in bypass mode, TPOR will not meet the 300
µs spec when 1) VDD_1P5 < 1.6 V at 25 °C and 125 °C. 2) 1.5V ≤ VDD_1P5 ≤ 1.8 V. For the bypass mode special case
where VDD_1P5 = VDD_1P8, TPOR did not meet the 300 µs maximum spec when the supply slew rate <=100 V/s.
6.2.5 Power consumption operating behaviors
Table 13. Power consumption operating behaviors - Bypass Mode
Symbol
Description
Typ.
Max.
Unit
Notes
1
IDDA
Analog supply current
—
See note
mA
IDD_RUNCO_C Run mode current in compute operation - 48 MHz
2, 3
core / 24 MHz flash / bus disabled, LPTMR running
M
using LPO clock at 1kHz, CoreMark benchmark code
executing from flash at 3.0 V
6.80
4.05
8.41
4.98
mA
mA
IDD_RUNCO Run mode current in compute operation - 48 MHz
core / 24 MHz flash / bus clock disabled, code of
while(1) loop executing from flash at 3.0 V
3, 4
3, 4
IDD_RUN
Run mode current - 48 MHz core / 24 MHz bus and
flash, all peripheral clocks disabled, code of while(1)
loop executing from flash at 3.0 V
5.00
6.01
mA
IDD_RUN
Run mode current - 48 MHz core / 24 MHz bus and
flash, all peripheral clocks enabled, code of while(1)
loop executing from flash at 3.0 V
3, 4, 5
6.48
6.77
7.13
6.70
6.96
7.90
mA
mA
mA
at 25 °C
at 70 °C
at 105 °C
IDD_WAIT Wait mode current - core disabled / 48 MHz system /
24 MHz bus / flash disabled (flash doze enabled), all
peripheral clocks disabled at 3.0 V
4
4
3.07
2.29
4.31
3.15
mA
mA
IDD_WAIT Wait mode current - core disabled / 24 MHz system /
24 MHz bus / flash disabled (flash doze enabled), all
peripheral clocks disabled at 3.0 V
Table continues on the next page...
34
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
Table 13. Power consumption operating behaviors - Bypass Mode (continued)
Symbol
Description
Typ.
Max.
Unit
mA
μA
Notes
IDD_PSTOP2 Stop mode current with partial stop 2 clocking option
- core and system disabled / 10.5 MHz bus at 3.0 V
4
2.32
3.11
IDD_VLPRCO_ Very-low-power run mode current in compute
6
7
766.9
1538
operation - 4 MHz core / 0.8 MHz flash / bus clock
CM
disabled, LPTMR running using LPO clock at 1 kHz
reference clock, CoreMark benchmark code
executing from flash at 3.0 V
IDD_VLPRCO Very-low-power run mode current in compute
operation - 4 MHz core / 0.8 MHz flash / bus clock
disabled, code of while(1) loop executing from flash
at 3.0 V
158.45
377
410
μA
μA
IDD_VLPR Very-low-power run mode current - 4 MHz core / 0.8
MHz bus and flash, all peripheral clocks disabled,
7
5, 7
7
185.26
240.96
code of while(1) loop executing from flash at 3.0 V
IDD_VLPR Very-low-power run mode current - 4 MHz core / 0.8
MHz bus and flash, all peripheral clocks enabled,
805.3
552.8
μA
μA
code of while(1) loop executing from flash at 3.0 V
IDD_VLPW Very-low-power wait mode current - core disabled / 4 133.95
MHz system / 0.8 MHz bus / flash disabled (flash
doze enabled), all peripheral clocks disabled at 3.0 V
IDD_STOP Stop mode current at 3.0 V
at 25 °C
at 70 °C
at 105 °C
204.98
291.89
599.46
308.3
872.5
1662
μA
μA
μA
IDD_VLPS Very-low-power stop mode current at Bypass
mode(3.0 V),
6.4
30.64
157
18
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
76.6
328
IDD_LLS3
Low-leakage stop mode 3 current at Bypass
mode(3.0 V),
2.57
11.76
50.92
4.31
26.07
105.4
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
IDD_LLS2
Low-leakage stop mode 2 current at Bypass
mode(3.0 V),
2.35
9.74
3.30
21.40
80.23
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
42.34
IDD_VLLS3 Very-low-leakage stop mode 3 current at Bypass
mode(3.0 V),
2.13
3.3
μA
at 25 °C
Table continues on the next page...
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
35
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
Table 13. Power consumption operating behaviors - Bypass Mode (continued)
Symbol
Description
Typ.
Max.
Unit
Notes
at 70 °C
10.78
22.97
μA
at 105 °C
46.70
83.54
μA
IDD_VLLS2 Very-low-leakage stop mode 2 current at Bypass
mode(3.0 V),
1.84
7.88
2.40
15.19
57.85
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
34.76
IDD_VLLS1 Very-low-leakage stop mode 1 current at Bypass
mode(3.0 V),
851.45
3.57
1027.8
6.28
nA
μA
μA
at 25°C
at 70°C
at 105°C
17.62
23.06
IDD_VLLS0 Very-low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 0) at 3.0 V
433.00
3.15
720.3
6.14
23.2
nA
μA
μA
at 25 °C
at 70 °C
at 105 °C
17.2
IDD_VLLS0 Very-low-leakage stop mode 0 current
(SMC_STOPCTRL[PORPO] = 1) at 3.0 V
8
258.12
2.97
516.43
5.81
nA
μA
μA
at 25 °C
at 70 °C
at 105 °C
16.9
22.4
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. MCG configured for FEI mode. CoreMark benchmark compiled using IAR 7.70 with optimization level high, optimized for
balanced.
3. Radio is off.
4. MCG configured for FEI mode.
5. Incremental current consumption from peripheral activity is not included.
6. MCG configured for BLPI mode. CoreMark benchmark compiled using IAR 7.70 with optimization level high, optimized
for balanced.
7. MCG configured for BLPI mode.
8. No brownout.
Table 14. Power consumption operating behaviors - Buck Mode1
Symbol
Description
Typ.
Max.
Unit
Notes
2
IDDA
Analog supply current
—
See note
mA
IDD_RUNCO Run mode current in compute operation - 48 MHz
core / 24 MHz flash / bus clock disabled, code of
while(1) loop executing from flash at 3.0 V
3, 4
3.51
—
mA
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MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
Table 14. Power consumption operating behaviors - Buck Mode1 (continued)
Symbol
Description
Typ.
Max.
Unit
Notes
IDD_RUN
Run mode current - 48 MHz core / 24 MHz bus and
flash, all peripheral clocks disabled, code of while(1)
loop executing from flash at 3.0 V
3, 4
4.00
—
mA
IDD_RUN
Run mode current - 48 MHz core / 24 MHz bus and
flash, all peripheral clocks enabled, code of while(1)
loop executing from flash at 3.0 V
3, 4, 5
5.81
5.92
6.36
—
—
—
mA
mA
mA
at 25 °C
at 70 °C
at 105 °C
IDD_WAIT Wait mode current - core disabled / 48 MHz system /
24 MHz bus / flash disabled (flash doze enabled), all
peripheral clocks disabled at 3.0 V
3
3
2.97
2.51
—
—
mA
mA
IDD_WAIT Wait mode current - core disabled / 24 MHz system /
24 MHz bus / flash disabled (flash doze enabled), all
peripheral clocks disabled at 3.0 V
IDD_PSTOP2 Stop mode current with partial stop 2 clocking option
- core and system disabled / 10.5 MHz bus at 3.0 V
3
6
2.33
—
—
mA
μA
IDD_VLPRCO Very-low-power run mode current in compute
operation - 4 MHz core / 0.8 MHz flash / bus clock
disabled, code of while(1) loop executing from flash
at 3.0 V
101.75
IDD_VLPR Very-low-power run mode current - 4 MHz core / 0.8
MHz bus and flash, all peripheral clocks disabled,
6
5, 6
6
132.17
167.65
—
μA
code of while(1) loop executing from flash at 3.0 V
IDD_VLPR Very-low-power run mode current - 4 MHz core / 0.8
MHz bus and flash, all peripheral clocks enabled,
—
—
μA
μA
code of while(1) loop executing from flash at 3.0 V
IDD_VLPW Very-low-power wait mode current - core disabled / 4 105.72
MHz system / 0.8 MHz bus / flash disabled (flash
doze enabled), all peripheral clocks disabled at 3.0 V
IDD_STOP Stop mode current at 3.0 V
at 25 °C
at 70 °C
at 105 °C
1.43
1.56
1.99
2.32
4.35
4.68
mA
mA
mA
IDD_VLPS Very-low-power stop mode current at Buck mode(3.0
V),
7
7
4.18
44.30
218.64
14.98
110
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
446
IDD_LLS3
Low-leakage stop mode 3 current at Buck mode(3.0
V),
2.64
4.89
μA
μA
at 25 °C
at 70 °C
15.27
25.51
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MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
37
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
Table 14. Power consumption operating behaviors - Buck Mode1 (continued)
Symbol
Description
Typ.
Max.
Unit
Notes
at 105 °C
81.93
104.35
μA
IDD_LLS2
Low-leakage stop mode 2 current at Buck mode(3.0
V),
7
2.46
10.14
63.49
3.80
21.14
80.21
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
IDD_VLLS3 Very-low-leakage stop mode 3 current at Buck
mode(3.0 V),
7
7
7
2.03
12.44
62.23
3.28
23.8
83.9
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
IDD_VLLS2 Very-low-leakage stop mode 2 current at Buck
mode(3.0 V),
1.79
8.87
2.43
16.7
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
49.39
62.94
IDD_VLLS1 Very-low-leakage stop mode 1 current at Buck
mode(3.0 V),
0.830
4.95
1.07
10.67
36.14
μA
μA
μA
at 25 °C
at 70 °C
at 105 °C
27.51
1. The device was configured in buck mode auto-start to perform the measurements. The DCDC_IN was powered with 3.0
V. VDD_1P8OUT was configured to output 1.8 V and VDD_1P5OUT_PMCIN was configured to output 1.5 V.
2. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
3. MCG configured for FEI mode.
4. Radio is off.
5. Incremental current consumption from peripheral activity is not included.
6. MCG configured for BLPI mode.
7. DCDC configured in pulsed mode.
Table 15. Low power mode peripheral adders — typical value (Bypass Mode)
Symbol
Description
Temperature (°C)
Unit
–40
25
50
70
85
IIREFSTEN4MHz
4 MHz internal reference clock (IRC)
adder. Measured by entering STOP or
VLPS mode with 4 MHz IRC enabled.
46
46
47
47
47
µA
IIREFSTEN32KHz
32 kHz internal reference clock (IRC)
adder. Measured by entering STOP mode
with the 32 kHz IRC enabled.
88
91
90
89
88
µA
IEREFSTEN32KHz
External 32 kHz crystal clock adder by
means of the RTC bits. Measured by
Table continues on the next page...
38
NXP Semiconductors
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
KW36Z/35Z Electrical Characteristics
Table 15. Low power mode peripheral adders — typical value (Bypass Mode) (continued)
Symbol
Description
Temperature (°C)
Unit
–40
25
50
70
85
entering all modes with the crystal
enabled.
VLLS1
VLLS2
VLLS3
LLS2
1.4
1.6
2.7
1.8
1.3
1.5
1.9
1.4
1.6
1.9
2.9
1.7
2.4
4.2
7.7
4.1
4.1
7.7
15
8
μA
LLS3
2.6
22
1.7
19
2.8
20
7.6
21
15.2
21
ICMP
CMP peripheral adder measured by
placing the device in VLLS1 mode with
CMP enabled using the 6-bit DAC and a
single external input for compare. Includes
6-bit DAC power consumption.
µA
µA
IRTC
RTC peripheral adder measured by placing
the device in VLLS1 mode with external 32
kHz crystal enabled by means of the
1.4
1.3
1.6
2.4
4.3
RTC_CR[OSCE] bit and the RTC ALARM
set for 1 minute. Includes ERCLK32K (32
kHz external crystal) power consumption.
ILPUART
LPUART peripheral adder measured by
placing the device in STOP or VLPS mode
with selected clock source waiting for RX
data at 115200 baud rate. Includes
selected clock source power consumption.
MCGIRCLK (4 MHz internal reference
clock)
53
54
54
54
54
µA
ILPTMR
LPTMR peripheral adder measured by
placing the device in VLLS1 mode with
LPTMR enabled using LPO.
30
30
30
85
100
nA
ITPM
TPM peripheral adder measured by
placing the device in STOP or VLPS mode
with selected clock source configured for
output compare generating 100 Hz clock
signal. No load is placed on the I/O
generating the clock signal. Includes
selected clock source and I/O switching
currents.
58
59
59
59
59
µA
MCGIRCLK (4 MHz internal reference
clock)
Table continues on the next page...
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
39
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
Table 15. Low power mode peripheral adders — typical value (Bypass Mode) (continued)
Symbol
Description
Temperature (°C)
Unit
–40
25
50
70
85
IBG
Bandgap adder when BGEN bit is set and
device is placed in VLPx, LLS, or VLLSx
mode.
76
82
85
87
87
µA
IADC
ADC peripheral adder combining the
measured values at VDD and VDDA by
placing the device in STOP or VLPS mode.
ADC is configured for low-power mode
using the internal clock and continuous
conversions.
331
327
327
327
328
µA
6.2.6 Diagram: Typical IDD_RUN operating behavior
The following data is measured from previous devices with same MCU core (Arm®
Cortex-M0+) under these conditions:
• No GPIOs toggled
• Code execution from flash with cache enabled
• For the ALLOFF curve, all peripheral clocks are disabled except FTFA
NOTE
The results in the following graphs are obtained using the
device in Bypass mode.
40
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
Figure 6. Run mode supply current vs. core frequency
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
41
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
Figure 7. VLPR mode current vs. core frequency
6.2.7 SoC Power Consumption
Full KW36Z/35Z system-on-chip (SoC) power consumption is a function of the many
configurations possible for the MCU platform and its peripherals including the 2.4 GHz
radio and the DC-DC converter. A few measured SoC configurations are as follows:
Table 16. SoC Power Consumption with default LDO-HF
MCU State
Flash State
Radio State
DC-DC State
Typical
Average IC
current
Unit
STOP
STOP
STOP
Doze
Doze
Doze
Rx
Buck (VDCDC_IN=3.6 V)
Buck (VDCDC_IN=3.6 V)
Buck (VDCDC_IN=3.6 V)
8.5
7.8
9.2
mA
mA
mA
Tx (at 0 dBm)
Tx (at +3.5
dBm)
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42
NXP Semiconductors
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
KW36Z/35Z Electrical Characteristics
Table 16. SoC Power Consumption with default LDO-HF (continued)
MCU State
Flash State
Radio State
DC-DC State
Typical
Average IC
current
Unit
RUN
RUN
RUN
Enabled
Enabled
Enabled
Rx
Buck (VDCDC_IN=3.6 V)
Buck (VDCDC_IN=3.6 V)
Buck (VDCDC_IN=3.6 V)
10.4
9.9
mA
mA
mA
Tx (at 0 dBm)
Tx (at +3.5
dBm)
11.7
STOP
STOP
STOP
Doze
Doze
Doze
Rx
Disabled/Bypass
Disabled/Bypass
Disabled/Bypass
17.3
15.9
18.3
mA
mA
mA
Tx (at 0 dBm)
Tx (at +3.5
dBm)
RUN
RUN
RUN
Enabled
Enabled
Enabled
Rx
Disabled/Bypass
Disabled/Bypass
Disabled/Bypass
21.5
19.9
22.4
mA
mA
mA
Tx (at 0 dBm)
Tx (at +3.5
dBm)
Table 17. SoC Power Consumption with LDO-HF bumped
MCU State
Flash State
Radio State
DC-DC State
Typical
Average IC
current
Unit
STOP
STOP
RUN
Doze
Doze
Rx (LDO-HF Bumped)
Tx (LDO-HF Bumped, +5 dBm)
Rx (LDO-HF Bumped)
Buck (VDCDC_IN=3.6 V)
Buck (VDCDC_IN=3.6 V)
Buck (VDCDC_IN=3.6 V)
Buck (VDCDC_IN=3.6 V)
Disabled/Bypass (3.6 V)
Disabled/Bypass (3.6 V)
Disabled/Bypass (3.6 V)
Disabled/Bypass (3.6 V)
8.7
mA
mA
mA
mA
mA
mA
mA
mA
10.3
11.3
13.1
18.2
20.8
22.6
26.6
Enabled
Enabled
Doze
RUN
Tx (LDO-HF Bumped, +5 dBm)
Rx (LDO-HF Bumped)
STOP
STOP
RUN
Doze
Tx (LDO-HF Bumped, +5 dBm)
Rx (LDO-HF Bumped)
Enabled
Enabled
RUN
Tx (LDO-HF Bumped, +5 dBm)
6.2.8 Designing with radiated emissions in mind
To find application notes that provide guidance on designing your system to minimize
interference from radiated emissions:
1. Go to www.nxp.com
2. Perform a keyword search for “EMC design.”
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
43
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
6.2.9 Capacitance attributes
Table 18. Capacitance attributes
Symbol
Description
Min.
Max.
Unit
CIN
Input capacitance
—
7
pF
6.3 Switching electrical specifications
6.3.1 Device clock specifications
Table 19. Device clock specifications
Symbol
Description
Min.
Max.
Unit
Normal run mode
fSYS
fBUS
fFLASH
fLPTMR
System and core clock
Bus clock
—
—
—
—
48
24
24
24
MHz
MHz
MHz
MHz
Flash clock
LPTMR clock
VLPR and VLPS modes1
fSYS
fBUS
System and core clock
Bus clock
—
—
—
—
—
—
—
—
4
1
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
fFLASH
fLPTMR
fERCLK
Flash clock
LPTMR clock2
1
24
16
16
8
External reference clock
fLPTMR_ERCLK LPTMR external reference clock
fTPM
TPM asynchronous clock
fLPUART0
LPUART0 asynchronous clock
12
1. The frequency limitations in VLPR and VLPS modes here override any frequency specification listed in the timing
specification for any other module. These same frequency limits apply to VLPS, whether VLPS entered from RUN or
from VLPR.
2. The LPTMR can be clocked at this speed in VLPR or VLPS only when the source is an external pin.
6.3.2 General switching specifications
These general-purpose specifications apply to all signals configured for GPIO,
LPUART, CAN (for KW36Z only), CMT and I2C signals.
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MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
Table 20. General switching specifications
Description
Min.
Max.
Unit
Notes
GPIO pin interrupt pulse width (digital glitch filter
disabled) — Synchronous path
1.5
—
Bus clock cycles
1, 2
NMI_b pin interrupt pulse width (analog filter enabled) —
Asynchronous path
200
20
—
—
—
ns
ns
ns
3
3
GPIO pin interrupt pulse width (digital glitch filter
disabled, analog filter disabled) — Asynchronous path
External RESET_b input pulse width (digital glitch filter
disabled)
100
Port rise and fall time(high drive strength)
4, 5
—
—
25
16
ns
ns
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7 V
• 2.7 ≤ VDD ≤ 3.6 V
• Slew disabled
—
—
8
6
ns
ns
• 1.71 ≤ VDD ≤ 2.7 V
• 2.7 ≤ VDD ≤ 3.6 V
Port rise and fall time(low drive strength)
6, 7
• Slew enabled
• 1.71 ≤ VDD ≤ 2.7 V
• 2.7 ≤ VDD ≤ 3.6 V
• Slew disabled
—
—
24
16
10
6
ns
ns
• 1.71 ≤ VDD ≤ 2.7 V
• 2.7 ≤ VDD ≤ 3.6 V
—
—
ns
ns
1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry in run modes.
2. The greater of synchronous and asynchronous timing must be met.
3. This is the minimum pulse width that is guaranteed to be recognized.
4. PTB0, PTB1, PTC0, PTC1, PTC2, PTC3, PTC6, PTC7, PTC17, PTC18.
5. 75 pF load.
6. Ports A, B, and C.
7. 25 pF load.
6.4 Thermal specifications
6.4.1 Thermal operating requirements
Table 21. Thermal operating requirements
Symbol
TJ
Description
Min.
–40
–40
Max.
125
Unit
°C
Notes
Die junction temperature
Ambient temperature
TA
105
°C
1
1. Maximum TA can be exceeded only if the user ensures that TJ does not exceed the maximum. The simplest method to
determine TJ is: TJ = TA + RθJA × chip power dissipation.
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
45
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
6.4.2 Thermal attributes
Table 22. Thermal attributes
Board type
Symbol
Description
48-pin
LQFN
40-pin
"Wettable"
HVQFN
Unit
Notes
Four-layer (2s2p)
—
RθJA
Thermal resistance, junction to
ambient (natural convection)
48.3
0.5
19.2
°C/W
°C/W
1, 2
1, 3
ΨJT
Thermal characterization
parameter, junction to package top
(natural convection)
0.1
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board
construction.
2. Determined according to JEDEC Standard JESD51-2A.
3. Thermal characterization parameter indicating the temperature difference between the package top and the junction
temperature per JEDEC JESD51-2A.
The thermal characterization parameter (ΨJT) is used to determine the junction
temperature with a measurement of the temperature at the top of the package case using
the following equation:
TJ = TT + ΨJT x chip power dissipation
where TT is the thermocouple temperature at the top of the package.
6.5 Peripheral operating requirements and behaviors
6.5.1 Core modules
6.5.1.1 SWD electricals
Table 23. SWD full voltage range electricals
Symbol
Description
Min.
Max.
Unit
Operating voltage
1.71
3.6
V
J1
SWD_CLK frequency of operation
• Serial wire debug
0
25
—
MHz
ns
J2
J3
SWD_CLK cycle period
1/J1
SWD_CLK clock pulse width
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MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
KW36Z/35Z Electrical Characteristics
Table 23. SWD full voltage range electricals (continued)
Symbol
Description
• Serial wire debug
Min.
20
Max.
Unit
—
ns
J4
J9
SWD_CLK rise and fall times
—
10
0
3
ns
ns
ns
ns
ns
SWD_DIO input data setup time to SWD_CLK rise
SWD_DIO input data hold time after SWD_CLK rise
SWD_CLK high to SWD_DIO data valid
SWD_CLK high to SWD_DIO high-Z
—
—
32
—
J10
J11
J12
—
5
J2
J4
J3
J3
SWD_CLK (input)
J4
Figure 8. Serial wire clock input timing
SWD_CLK
SWD_DIO
SWD_DIO
SWD_DIO
SWD_DIO
J9
J10
Input data valid
J11
Output data valid
J12
J11
Output data valid
Figure 9. Serial wire data timing
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
47
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
6.5.2 System modules
There are no specifications necessary for the device's system modules.
6.5.3 Clock modules
6.5.3.1 MCG specifications
Table 24. MCG specifications
Symbol Description
Min.
Typ.
Max.
Unit
Notes
fints_ft Internal reference frequency (slow clock) —
—
32.768
—
kHz
factory trimmed at nominal VDD and 25 °C
fints_t
Internal reference frequency (slow clock) —
user trimmed
31.25
—
—
39.0625
0.6
kHz
Δfdco_res_t Resolution of trimmed average DCO output
frequency at fixed voltage and temperature —
using C3[SCTRIM] and C4[SCFTRIM]
0.3
%fdco
1
Δfdco_t
Total deviation of trimmed average DCO output
frequency over voltage and temperature
—
—
+0.5/–0.7
0.4
3
%fdco
%fdco
1, 2
1, 2
Δfdco_t
Total deviation of trimmed average DCO output
frequency over fixed voltage and temperature
range of 0–70 °C
1.5
fintf_ft
Internal reference frequency (fast clock) —
factory trimmed at nominal VDD and 25 °C
—
—
4
—
3
MHz
Δfintf_ft
Frequency deviation of internal reference clock
(fast clock) over temperature and voltage —
factory trimmed at nominal VDD and 25 °C
+1/–2
%fintf_ft
2
fintf_t
Internal reference frequency (fast clock) — user
trimmed at nominal VDD and 25 °C
3
—
—
—
5
MHz
kHz
kHz
floc_low
Loss of external clock minimum frequency —
RANGE = 00
(3/5) x
fints_t
—
—
floc_high Loss of external clock minimum frequency —
RANGE = 01, 10, or 11
(16/5) x
fints_t
FLL
FLL reference frequency range
31.25
20
—
39.0625
25
kHz
ffll_ref
fdco
DCO output
Low range (DRS = 00)
20.97
MHz
3, 4
5, 6
frequency range
640 × ffll_ref
Mid range (DRS = 01)
1280 × ffll_ref
40
—
—
41.94
23.99
47.97
48
—
—
MHz
MHz
MHz
fdco_t_DMX3 DCO output
Low range (DRS = 00)
732 × ffll_ref
frequency
2
Mid range (DRS = 01)
1464 × ffll_ref
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MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
KW36Z/35Z Electrical Characteristics
Table 24. MCG specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Jcyc_fll
FLL period jitter
• fVCO = 48 MHz
—
180
—
ps
7
tfll_acquire FLL target frequency acquisition time
—
—
1
ms
8
1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock
mode).
2. The deviation is relative to the factory trimmed frequency at nominal VDD and 25 °C, fints_ft
.
3. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 0.
4. The resulting system clock frequencies must not exceed their maximum specified values. The DCO frequency
deviation (Δfdco_t) over voltage and temperature must be considered.
5. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32 = 1.
6. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.
7. This specification is based on standard deviation (RMS) of period or frequency.
8. This specification applies to any time the following changes: FLL reference source or reference divider, trim value,
DMX32 bit, DRS bits, or FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE, FBE, FBI). If a crystal/resonator is
used as the reference, this specification assumes it is already running.
6.5.3.2 Reference Oscillator Specification
The KW36Z/35Z has been designed to meet targeted standard specifications for
frequency error over the life of the part, which includes the temperature, mechanical
and aging effects.
The table below lists the recommended crystal specifications. Note that these are
recommendations only and deviation may be allowed. However, deviations may result
in degraded RF performance or possibly a failure to meet RF protocol certification
standards. Designers must ensure that the crystal(s) they use meet the requirements of
their application.
Table 25. Recommended Crystal and Oscillator Specification
Symbol
Description
F0 = 32.0 MHz
F0 = 26.0 MHz
Unit
Notes
Min
Typ
Max
Min
Typ
Max
TA
Operating
–40
—
105
–40
—
105
°C
1
Temperature
Crystal initial
frequency
tolerance
–10
—
—
10
25
–10
–25
—
10
24
ppm
2,3
2,4
Crystal frequency –25
stability and aging
—
ppm
Oscillator variation –12
—
—
15
50
–12
–50
—
—
16
50
ppm
ppm
5
6
Total reference
–50
oscillator tolerance
Table continues on the next page...
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
49
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
Table 25. Recommended Crystal and Oscillator Specification (continued)
Symbol
Description
F0 = 32.0 MHz
F0 = 26.0 MHz
Min Typ
Unit
Notes
Min
Typ
Max
Max
for Bluetooth LE
applications
CL
Load capacitance
7
10
13
7
10
13
pF
pF
fF
2, 7
2,7
2,7
C0
Shunt capacitance 0.469
0.67
2.05
0.871
2.665
0.42
0.6
2.05
0.78
2.665
Cm1
Motional
capacitance
1.435
8.47
—
1.435
Lm1
Rm1
ESR
Pd
Motional
inductance
12.1
25
15.73
50
12.81
—
18.3
35
23.79
50
mH
2,7
2
Motional
resistance
Ohms
Ohms
uW
Equivalent series
resistance
—
—
60
—
—
60
2,8
2
Maximum crystal
drive
—
10
200
—
10
200
TS
Trim sensitivity
6.30
—
9.00
500
11.70
—
6.39
—
9.12
500
11.86
—
ppm/pF 2,7
μs
TOSC
Oscillator Startup
Time
9
1. Full temperature range of this device. A reduced range can be chosen to meet application needs.
2. Recommended crystal specification.
3. Measured at 25 °C.
4. Combination of frequency stability variation over desired temperature range and frequency variation due to aging over
desired lifetime of system.
5. Variation due to temperature, process, and aging of MCU.
6. Sum of crystal initial frequency tolerance, crystal frequency stability and aging, oscillator variation, and PCB
manufacturing variation must not exceed this value.
7. Typical is target. 30% tolerances shown.
8. ESR = Rm1 * (1 + [C0/CL])^2.
9. Time from oscillator enable to clock ready. Dependent on the complete hardware configuration of the oscillator.
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MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
Figure 10. Crystal Electrical Model
6.5.3.3 32 kHz Oscillator Frequency Specifications
Table 26. 32 kHz Crystal and Oscillator Specifications
Symbol
Description
Min.
Typ.
Max.
Unit
Notes
fosc_lo
Crystal
—
32.768
—
kHz
frequency
TA
Operating
temperature
–40
—
—
105
500
°C
1
Total crystal
frequency
tolerance
–500
ppm
2,3
CL
Load
capacitance
—
—
12.5
—
—
pF
2
2
ESR
Equivalent
series
80
kOhms
resistance
tstart
Crystal start-up
time
—
1000
32.768
—
—
ms
kHz
V
4
5
6
fec_extal32
vec_extal32
External input
clock frequency
—
—
External input
0.7
VDD
clock amplitude
1. Full temperature range of this device. A reduced range can be chosen to meet application needs.
2. Recommended crystal specification.
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
51
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
3. Sum of crystal initial frequency tolerance, crystal frequency stability, and aging tolerances given by crystal vendor.
4. Time from oscillator enable to clock stable. Dependent on the complete hardware configuration of the oscillator.
5. External oscillator connected to EXTAL32K. XTAL32K must be unconnected.
6. The parameter specified is a peak-to-peak value and VIH and VIL specifications do not apply. The voltage of the applied
clock must be within the range of VSS to VDD.
6.5.4 Memories and memory interfaces
6.5.4.1 Flash (FTFE) electrical specifications
This section describes the electrical characteristics of the FTFE module.
6.5.4.1.1 Flash timing specifications — commands
Table 27. Flash command timing specifications
Symbol Description
Read 1s Block execution time
• 256 KB program/data flash
Min.
Typ.
Max.
Unit
Notes
trd1blk256k
—
—
1.8
ms
trd1sec2k Read 1s Section execution time (2 KB flash)
—
—
—
—
—
—
—
90
75
95
μs
μs
μs
μs
1
1
1
tpgmchk
trdrsrc
Program Check execution time
Read Resource execution time
Program Phrase execution time
Erase Flash Block execution time
• 256 KB program/data flash
40
tpgm8
150
2
2
tersblk256k
tersscr
—
220
1850
ms
Erase Flash Sector execution time
—
—
15
10
115
—
ms
ms
tpgmsec2k Program Section execution time (2 KB flash)
Read 1s All Blocks execution time
trd1allx
trd1alln
• FlexNVM devices
—
—
—
—
3.4
3.4
ms
ms
• Program flash only devices
trdonce
Read Once execution time
—
—
—
—
—
—
90
30
—
μs
μs
1
tpgmonce Program Once execution time
tersall
tvfykey
tersallu
Erase All Blocks execution time
Verify Backdoor Access Key execution time
Erase All Blocks Unsecure execution time
Swap Control execution time
• control code 0x01
450
—
3700
30
ms
μs
2
1
2
450
3700
ms
tswapx01
tswapx02
tswapx04
tswapx08
—
—
—
—
200
90
90
—
—
150
150
30
μs
μs
μs
μs
• control code 0x02
• control code 0x04
Table continues on the next page...
52
NXP Semiconductors
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
KW36Z/35Z Electrical Characteristics
Table 27. Flash command timing specifications (continued)
Symbol Description
Min.
Typ.
Max.
Unit
Notes
tswapx10
• control code 0x08
—
90
150
μs
• control code 0x10
Program Partition for EEPROM execution time
• 32 KB EEPROM backup
tpgmpart32k
tpgmpart256k
—
—
230
240
—
—
ms
ms
• 256 KB EEPROM backup
Set FlexRAM Function execution time:
• Control Code 0xFF
tsetramff
tsetram32k
tsetram256k
—
—
—
112
0.8
—
μs
ms
ms
• 32 KB EEPROM backup
• 256 KB EEPROM backup
1.2
4.5
5.5
Byte-write to FlexRAM execution time:
• 32 KB EEPROM backup
teewr8b32k
—
—
385
1700
3250
μs
μs
teewr8b256k
• 256 KB EEPROM backup
1000
16-bit write to FlexRAM execution time:
• 32 KB EEPROM backup
teewr16b32k
teewr16b256k
—
—
385
1700
μs
μs
• 256 KB EEPROM backup
1000
360
3250
1500
teewr32bers 32-bit write to erased FlexRAM location
execution time
—
μs
32-bit write to FlexRAM execution time:
teewr32b32k
teewr32b256k
• 32 KB EEPROM backup
• 256 KB EEPROM backup
—
—
630
2000
3500
μs
μs
1900
1. Assumes 25MHz or greater flash clock frequency.
2. Maximum times for erase parameters based on expectations at cycling end-of-life.
6.5.4.1.2 Reliability specifications
Table 28. NVM reliability specifications
Symbol Description
Min.
Program Flash
Typ.1
Max.
Unit
Notes
tnvmretp10k Data retention after up to 10 K cycles
tnvmretp1k Data retention after up to 1 K cycles
nnvmcycp Cycling endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
10 K
2
2
Data Flash
tnvmretd10k Data retention after up to 10 K cycles
tnvmretd1k Data retention after up to 1 K cycles
nnvmcycd Cycling endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
10 K
Table continues on the next page...
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
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KW36Z/35Z Electrical Characteristics
Table 28. NVM reliability specifications (continued)
Symbol Description
Min.
Typ.1
Max.
Unit
Notes
FlexRAM as EEPROM
tnvmretee100 Data retention up to 100% of write endurance
tnvmretee10 Data retention up to 10% of write endurance
nnvmcycee Cycling endurance for EEPROM backup
nnvmwree16 Write endurance
5
50
—
—
—
years
years
cycles
20
100
50 K
20 K
2
3
140 K
1.26 M
5 M
400 K
3.2 M
12.8 M
50 M
—
—
—
—
writes
writes
writes
writes
nnvmwree128
nnvmwree512
nnvmwree2k
• EEPROM backup to FlexRAM ratio = 16
• EEPROM backup to FlexRAM ratio = 128
• EEPROM backup to FlexRAM ratio = 512
• EEPROM backup to FlexRAM ratio = 2,048
20 M
1. Typical data retention values are based on measured response accelerated at high temperature and derated to a
constant 25°C use profile. Engineering Bulletin EB618 does not apply to this technology. Typical endurance defined in
Engineering Bulletin EB619.
2. Cycling endurance represents number of program/erase cycles at -40°C ≤ Tj ≤ 125°C.
3. Write endurance represents the number of writes to each FlexRAM location at -40°C ≤Tj ≤ 125°C influenced by the
cycling endurance of the FlexNVM and the allocated EEPROM backup. Minimum and typical values assume all 16-bit or
32-bit writes to FlexRAM; all 8-bit writes result in 50% less endurance.
6.5.4.1.3 Write endurance to FlexRAM for EEPROM
When the FlexNVM partition code is not set to full data flash, the EEPROM data set
size can be set to any of several non-zero values.
The bytes not assigned to data flash via the FlexNVM partition code are used by the
FTFE to obtain an effective endurance increase for the EEPROM data. The built-in
EEPROM record management system raises the number of program/erase cycles that
can be attained prior to device wear-out by cycling the EEPROM data through a larger
EEPROM NVM storage space.
While different partitions of the FlexNVM are available, the intention is that a single
choice for the FlexNVM partition code and EEPROM data set size is used throughout
the entire lifetime of a given application.
6.5.5 Security and integrity modules
There are no specifications necessary for the device's security and integrity modules.
6.5.6 Analog
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MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
6.5.6.1 ADC electrical specifications
All other ADC channels meet the 13-bit differential/12-bit single-ended accuracy
specifications. The following specification is defined with the DC-DC converter
operating in Bypass mode.
6.5.6.1.1 16-bit ADC operating conditions
Table 29. 16-bit ADC operating conditions
Symbol Description
VDDA Supply voltage
ΔVDDA Supply voltage
Conditions
Min.
1.71
–100
–100
1.13
Typ.1
Max.
3.6
Unit
V
Notes
Absolute
—
Delta to VDD (VDD – VDDA
)
0
+100
+100
VDDA
mV
mV
V
2
2
3
ΔVSSA
Ground voltage Delta to VSS (VSS – VSSA
)
0
VREFH
ADC reference
voltage high
VDDA
VREFL
VADIN
ADC reference
voltage low
VSSA
VSSA
VSSA
V
V
3
Input voltage
• 16-bit differential mode
• All other modes
• 16-bit mode
VSSA
VSSA
—
—
31/32 ×
VREFH
VREFH
CADIN
Input
capacitance
—
—
8
4
10
5
pF
• 8-bit / 10-bit / 12-bit
modes
RADIN
RAS
Input series
resistance
—
—
2
5
5
kΩ
kΩ
Analog source
resistance
(external)
13-bit / 12-bit modes
fADCK < 4 MHz
4
—
fADCK
fADCK
Crate
ADC conversion ≤ 13-bit mode
clock frequency
1.0
2.0
—
—
18.0
12.0
MHz
MHz
5
5
6
ADC conversion 16-bit mode
clock frequency
ADC conversion ≤ 13-bit modes
rate
No ADC hardware averaging
20.000
37.037
—
—
818.330
461.467
kS/s
kS/s
Continuous conversions
enabled, subsequent
conversion time
Crate
ADC conversion 16-bit mode
6
rate
No ADC hardware averaging
Continuous conversions
enabled, subsequent
conversion time
1. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 1.0 MHz, unless otherwise stated. Typical values are for
reference only, and are not tested in production.
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
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KW36Z/35Z Electrical Characteristics
2. DC potential difference.
3. For packages without dedicated VREFH and VREFL pins, VREFH is internally tied to VDDA, and VREFL is internally tied to
VSSA
.
4. This resistance is external to MCU. To achieve the best results, the analog source resistance must be kept as low as
possible. The results in this data sheet are derived from a system that had < 8 Ω analog source resistance. The RAS/CAS
time constant should be kept to < 1 ns.
5. To use the maximum ADC conversion clock frequency, CFG2[ADHSC] must be set and CFG1[ADLPC] must be clear.
6. For guidelines and examples of conversion rate calculation, download the ADC calculator tool.
SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
leakage
ZAS
ADC SAR
ENGINE
RAS
RADIN
VADIN
CAS
VAS
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 11. ADC input impedance equivalency diagram
6.5.6.1.2 16-bit ADC electrical characteristics
Table 30. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA
)
Symbol Description
Conditions1
Min.
0.215
1.2
Typ.2
Max.
1.7
3.9
6.1
7.3
9.5
Unit
Notes
IDDA_ADC Supply current
—
mA
3
ADC asynchronous
clock source
• ADLPC=1, ADHSC=0
• ADLPC=1, ADHSC=1
• ADLPC=0, ADHSC=0
• ADLPC=0, ADHSC=1
2.4
4.0
5.2
6.2
MHz tADACK
=
1/fADACK
2.4
fADACK
3.0
4.4
Sample Time
See Reference Manual chapter for sample times
Table continues on the next page...
56
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MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
KW36Z/35Z Electrical Characteristics
Table 30. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
—
Typ.2
Max.
6.8
Unit
Notes
TUE
Total unadjusted
error
• 12-bit modes
• <12-bit modes
4
LSB4
5
—
1.4
2.1
DNL
Differential non-
linearity
• 12-bit mode; Buck
Mode6
• 12-bit mode; Bypass
Mode
—
—
0.7
0.5
–1.1 to +1.9
–1.1 to +1.9
LSB4
LSB4
5
5
INL
Integral non-
linearity
• 12-bit mode; Buck
Mode6
• 12-bit mode; Bypass
Mode
—
—
1.0
0.6
–2.7 to +1.9
–2.7 to +1.9
EFS
EQ
Full-scale error
• 12-bit modes
• <12-bit modes
• 16-bit modes
• ≤13-bit modes
—
—
—
—
–4
–1.4
–1 to 0
—
–5.4
–1.8
—
LSB4 VADIN
VDDA
=
5
Quantization error
LSB4
0.5
ENOB Effective number of 16-bit differential mode; Buck
bits
Mode6
7
12
12.75
11.75
—
—
bits
• Avg = 32
• Avg = 4
11.25
16-bit single-ended mode;
Buck Mode6
• Avg = 32
• Avg = 4
11
11.5
10.5
—
—
9.5
16-bit differential mode;
Bypass Mode
• Avg = 32
• Avg = 4
12.5
13
12
—
—
11.25
16-bit single-ended mode;
Bypass Mode
• Avg = 32
• Avg = 4
11
10
11.75
10.5
—
—
Signal-to-noise plus See ENOB
distortion
SINAD
6.02 × ENOB + 1.76
dB
THD Total harmonic
distortion
16-bit differential mode; Buck
Mode6
8
• Avg = 32
—
—
–90
–88
—
dB
16-bit single-ended mode;
Buck Mode6
• Avg = 32
—
16-bit differential mode;
Bypass Mode
Table continues on the next page...
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
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KW36Z/35Z Electrical Characteristics
Table 30. 16-bit ADC characteristics (VREFH = VDDA, VREFL = VSSA) (continued)
Symbol Description
Conditions1
Min.
Typ.2
Max.
Unit
Notes
• Avg = 32
—
–89
—
16-bit single-ended mode;
Bypass Mode
• Avg = 32
—
–87
—
Signal-to-noise plus See ENOB
distortion
SINAD
6.02 × ENOB + 1.76
dB
dB
SFDR Spurious free
dynamic range
distortion
16-bit differential mode; Buck
Mode6
8
• Avg = 32
85
85
89
87
—
16-bit single-ended mode;
Buck Mode6
• Avg = 32
—
—
—
16-bit differential mode;
Bypass Mode
• Avg = 32
87
85
94
16-bit single-ended mode;
Bypass Mode
• Avg = 32
88
EIL
Input leakage error
IIn × RAS
mV
IIn =
leakage
current
(see
Voltage
and
current
operating
ratings)
Temp sensor slope Across the full temperature
range of the device
1.67
706
1.74
716
1.81
726
mV/°
C
9
VTEMP25 Temp sensor
voltage
25 °C
mV
9
1. All accuracy numbers assume that the ADC is calibrated with VREFH = VDDA
.
2. Typical values assume VDDA = 3.0 V, Temp = 25 °C, fADCK = 2.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3. The ADC supply current depends on the ADC conversion clock speed, conversion rate and ADC_CFG1[ADLPC] (low-
power). For lowest power operation, ADC_CFG1[ADLPC] must be set, the ADC_CFG2[ADHSC] bit must be clear with 1
MHz ADC conversion clock speed.
4. 1 LSB = (VREFH - VREFL)/2N.
5. ADC conversion clock < 16 MHz, maximum hardware averaging (AVGE = %1, AVGS = %11).
6. VREFH = Output of Voltage Reference(VREF).
7. Input data is 100 Hz sine wave. ADC conversion clock < 12 MHz.
8. Input data is 1 kHz sine wave. ADC conversion clock < 12 MHz.
9. ADC conversion clock < 3 MHz.
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MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
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KW36Z/35Z Electrical Characteristics
6.5.6.2 Voltage reference electrical specifications
Table 31. VREF full-range operating requirements
Symbol
VDDA
TA
Description
Min.
Max.
Unit
V
Notes
Supply voltage
Temperature
1.71
3.6
–40 to 105
100
°C
nF
CL
Output load capacitance
1, 2
1. CL must be connected to VREF_OUT if the VREF_OUT functionality is being used for either an internal or external
reference.
2. The load capacitance should not exceed +/–25% of the nominal specified CL value over the operating temperature
range of the device.
Table 32. VREF full-range operating behaviors
Symbol Description
Min.
Typ.
Max.
Unit
Notes
Vout
Voltage reference output with factory trim at
1.190
1.1950
1.2
V
1
nominal VDDA and temperature=25 °C
Vout
Voltage reference output with user trim at
nominal VDDA and temperature=25 °C
1.1945
1.1950
1.1955
V
1
Vstep
Vtdrift
Voltage reference trim step
—
—
0.5
—
—
mV
mV
1
1
Temperature drift (Vmax -Vmin across the full
temperature range)
20
Ibg
Ilp
Bandgap only current
—
—
—
—
—
—
80
360
1
µA
uA
mA
µV
Low-power buffer current
High-power buffer current
1
1
Ihp
ΔVLOAD Load regulation
• current = 1.0 mA
1, 2
—
200
—
Tstup
Buffer startup time
—
—
—
—
100
35
µs
Tchop_osc_st Internal bandgap start-up delay with chop
ms
oscillator enabled
up
Vvdrift
Voltage drift (Vmax –Vmin across the full voltage
range)
—
2
—
mV
1
1. See the chip's Reference Manual for the appropriate settings of the VREF Status and Control register.
2. Load regulation voltage is the difference between the VREF_OUT voltage with no load vs. voltage with defined load
Table 33. VREF limited-range operating requirements
Symbol
Description
Min.
Max.
Unit
Notes
TA
Temperature
0
70
°C
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
59
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
Table 34. VREF limited-range operating behaviors
Symbol
Description
Min.
Max.
Unit
Notes
Vtdrift
Temperature drift (Vmax –Vmin across the limited
temperature range)
—
15
mV
6.5.6.3 CMP and 6-bit DAC electrical specifications
Table 35. Comparator and 6-bit DAC electrical specifications
Symbol
VDD
Description
Min.
1.71
—
Typ.
—
Max.
3.6
Unit
V
Supply voltage
IDDHS
IDDLS
VAIN
Supply current, High-speed mode (EN=1, PMODE=1)
Supply current, low-speed mode (EN=1, PMODE=0)
Analog input voltage
—
200
20
μA
μA
V
—
—
VSS – 0.3
—
—
VDD
20
VAIO
Analog input offset voltage
Analog comparator hysteresis1
• CR0[HYSTCTR] = 00
—
mV
VH
—
—
—
—
5
—
—
—
—
mV
mV
mV
mV
10
20
30
• CR0[HYSTCTR] = 01
• CR0[HYSTCTR] = 10
• CR0[HYSTCTR] = 11
VCMPOh
VCMPOl
tDHS
Output high
VDD – 0.5
—
—
—
50
250
—
7
—
0.5
200
600
40
V
V
Output low
Propagation delay, high-speed mode (EN=1, PMODE=1)
Propagation delay, low-speed mode (EN=1, PMODE=0)
Analog comparator initialization delay2
6-bit DAC current adder (enabled)
6-bit DAC integral non-linearity
20
ns
tDLS
80
ns
—
μs
IDAC6b
INL
—
—
μA
LSB3
LSB
–0.5
–0.3
—
—
0.5
0.3
DNL
6-bit DAC differential non-linearity
1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD–0.6 V.
2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to
CMP_DACCR[DACEN], CMP_DACCR[VRSEL], CMP_DACCR[VOSEL], CMP_MUXCR[PSEL], and
CMP_MUXCR[MSEL]) and the comparator output settling to a stable level.
3. 1 LSB = Vreference/64
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KW36Z/35Z Electrical Characteristics
0.08
0.07
0.06
0.05
0.04
0.03
HYSTCTR
Setting
00
01
10
11
0.02
0.01
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 12. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 0)
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KW36Z/35Z Electrical Characteristics
0.18
0.16
0.14
0.12
HYSTCTR
Setting
0.1
00
01
10
11
0.08
0.06
0.04
0.02
0
0.1
0.4
0.7
1
1.3
1.6
1.9
2.2
2.5
2.8
3.1
Vin level (V)
Figure 13. Typical hysteresis vs. Vin level (VDD = 3.3 V, PMODE = 1)
6.5.7 Timers
See General switching specifications.
6.5.8 Communication interfaces
6.5.8.1 CAN switching specifications
See General switching specifications.
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KW36Z/35Z Electrical Characteristics
6.5.8.2 DSPI switching specifications (limited voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. See
the DSPI chapter of the Reference Manual for information on the modified transfer
formats used for communicating with slower peripheral devices.
Table 36. Master mode DSPI timing (limited voltage range)
Num
Description
Min.
2.7
Max.
3.6
12
Unit
V
Notes
Operating voltage
Frequency of operation
—
MHz
ns
DS1
DS2
DS3
DSPI_SCK output cycle time
DSPI_SCK output high/low time
DSPI_PCSn valid to DSPI_SCK delay
2 x tBUS
—
(tSCK/2) − 2 (tSCK/2) + 2
ns
(tBUS x 2) −
2
—
ns
1
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
2
—
ns
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
–2
8.5
—
—
—
ns
ns
ns
ns
16.2
0
1. The delay is programmable in SPIx_CTARn[PCSSCK] and SPIx_CTARn[CSSCK].
2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
SPI_PCSn
DS1
DS3
DS2
DS4
SPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
SPI_SIN
DS5
DS6
First data
Data
Last data
SPI_SOUT
Figure 14. DSPI classic SPI timing — master mode
Table 37. Slave mode DSPI timing (limited voltage range)
Num
Description
Min.
Max.
3.6
6
Unit
V
Operating voltage
2.7
Frequency of operation
MHz
Table continues on the next page...
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KW36Z/35Z Electrical Characteristics
Table 37. Slave mode DSPI timing (limited voltage range) (continued)
Num
DS9
Description
DSPI_SCK input cycle time
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) − 2
(tSCK/2) + 2
DSPI_SCK to DSPI_SOUT valid
—
0
21.4
—
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
2.6
7.0
—
—
—
—
14
14
SPI_SS
DS10
DS9
SPI_SCK
(POL=0)
DS15
DS12
DS16
DS11
First data
DS14
Last data
SPI_SOUT
Data
Data
DS13
First data
Last data
SPI_SIN
Figure 15. DSPI classic SPI timing — slave mode
6.5.8.3 DSPI switching specifications (full voltage range)
The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with
master and slave operations. Many of the transfer attributes are programmable. The
tables below provide DSPI timing characteristics for classic SPI timing modes. See the
DSPI chapter of the Reference Manual for information on the modified transfer formats
used for communicating with slower peripheral devices.
Table 38. Master mode DSPI timing (full voltage range)
Num
Description
Min.
1.71
Max.
3.6
12
Unit
V
Notes
Operating voltage
1
Frequency of operation
—
MHz
ns
DS1
DS2
DSPI_SCK output cycle time
DSPI_SCK output high/low time
2 x tBUS
—
(tSCK/2) – 4 (tSCK/2) + 4
Table continues on the next page...
ns
64
NXP Semiconductors
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
KW36Z/35Z Electrical Characteristics
Table 38. Master mode DSPI timing (full voltage range) (continued)
Num
Description
Min.
Max.
Unit
Notes
DS3
DSPI_PCSn valid to DSPI_SCK delay
(tBUS x 2) −
4
—
ns
2
DS4
DSPI_SCK to DSPI_PCSn invalid delay
(tBUS x 2) −
4
—
ns
3
DS5
DS6
DS7
DS8
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
—
–1.2
23.3
0
10
—
—
—
ns
ns
ns
ns
1. The DSPI module can operate across the entire operating voltage for the processor, but to run across the full voltage
range the maximum frequency of operation is reduced.
2. The delay is programmable in SPIx_CTARn[PCSSCK] and SPIx_CTARn[CSSCK].
3. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].
SPI_PCSn
DS1
DS3
DS2
DS4
SPI_SCK
(CPOL=0)
DS8
DS7
Data
Last data
First data
SPI_SIN
DS5
DS6
First data
Data
Last data
SPI_SOUT
Figure 16. DSPI classic SPI timing — master mode
Table 39. Slave mode DSPI timing (full voltage range)
Num
Description
Min.
Max.
Unit
V
Operating voltage
1.71
3.6
Frequency of operation
—
6
MHz
ns
DS9
DSPI_SCK input cycle time
4 x tBUS
—
DS10
DS11
DS12
DS13
DS14
DS15
DS16
DSPI_SCK input high/low time
(tSCK/2) – 4
(tSCK/2) + 4
ns
DSPI_SCK to DSPI_SOUT valid
DSPI_SCK to DSPI_SOUT invalid
DSPI_SIN to DSPI_SCK input setup
DSPI_SCK to DSPI_SIN input hold
DSPI_SS active to DSPI_SOUT driven
DSPI_SS inactive to DSPI_SOUT not driven
—
0
29.1
—
ns
ns
3.2
7.0
—
—
—
ns
—
ns
25
25
ns
ns
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65
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
SPI_SS
DS10
DS9
SPI_SCK
DS15
DS12
DS16
DS11
(POL=0)
First data
DS14
Last data
SPI_SOUT
Data
Data
DS13
First data
Last data
SPI_SIN
Figure 17. DSPI classic SPI timing — slave mode
6.5.8.4 Inter-Integrated Circuit Interface (I2C) timing
Table 40. I 2C timing
Characteristic
Symbol
Standard Mode
Minimum Maximum
100
Fast Mode
Unit
Minimum
Maximum
400
SCL Clock Frequency
fSCL
0
0
kHz
µs
Hold time (repeated) START condition.
After this period, the first clock pulse is
generated.
tHD; STA
4
—
0.6
—
LOW period of the SCL clock
HIGH period of the SCL clock
tLOW
tHIGH
4.7
4
—
—
—
1.3
0.6
0.6
—
—
—
µs
µs
µs
Set-up time for a repeated START
condition
tSU; STA
4.7
Data hold time for I2C bus devices
tHD; DAT
tSU; DAT
tr
01
2504
—
3.452
—
03
1002, 5
0.91
—
µs
ns
ns
Data set-up time
5,
5,
Rise time of SDA and SCL signals
1000
20 +0.1Cb
300
6
Fall time of SDA and SCL signals
Set-up time for STOP condition
tf
—
300
20 +0.1Cb
300
ns
6
tSU; STO
tBUF
4
—
—
0.6
1.3
—
—
µs
µs
Bus free time between STOP and
START condition
4.7
Pulse width of spikes that must be
suppressed by the input filter
tSP
N/A
N/A
0
50
ns
1. The master mode I2C deasserts ACK of an address byte simultaneously with the falling edge of SCL. If no slaves
acknowledge this address byte, then a negative hold time can result, depending on the edge rates of the SDA and SCL
lines.
2. The maximum tHD; DAT must be met only if the device does not stretch the LOW period (tLOW) of the SCL signal.
3. Input signal Slew = 10 ns and Output Load = 50 pF.
4. Set-up time in slave-transmitter mode is 1 IP Bus clock period, if the TX FIFO is empty.
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KW36Z/35Z Electrical Characteristics
5. A Fast mode I2C bus device can be used in a Standard mode I2C bus system, but the requirement tSU; DAT ≥ 250 ns
must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If
such a device does stretch the LOW period of the SCL signal, then it must output the next data bit to the SDA line trmax
+ tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard mode I2C bus specification) before the SCL line is
released.
6. Cb = total capacitance of the one bus line in pF.
SDA
tSU; DAT
tf
tr
tBUF
tf
tr
tHD; STA
tSP
tLOW
SCL
tSU; STA
tSU; STO
HD; STA
S
SR
P
S
tHD; DAT
tHIGH
Figure 18. Timing definition for fast and standard mode devices on the I2C bus
6.5.8.5 LPUART
See General switching specifications.
6.5.9 Human-machine interfaces (HMI)
6.5.9.1 GPIO
The maximum input voltage on PTC0/1/2/3 is VDD+0.3V. For rest of the GPIO
specification, see General switching specifications.
6.6 DC-DC Converter Operating Requirements
Table 41. DC-DC Converter operating conditions
Characteristic
Symbol
Min
Typ
Max
Unit
Bypass Mode Supply Voltage (RF and Analog)
VDDRF1
VDDRF2
,
,
1.425
—
3.6
Vdc
VDDRF3, VDD_1P5
Bypass Mode Supply Voltage (Digital)
VDDX, VDCDC_IN
VDDA
,
1.71
2.1
—
—
3.6
3.6
Vdc
Vdc
Buck Mode Supply Voltage 1, 2
DC-DC Inductor
Value
VDCDC_IN
—
10
—
μH
Table continues on the next page...
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KW36Z/35Z Electrical Characteristics
Table 41. DC-DC Converter operating conditions (continued)
Characteristic
ESR
Symbol
Min
—
Typ
<0.2
26
Max
<0.5
—
Unit
Ohms
MHz
DC-DC internal oscillator
DCDCInt_Osc
—
1. In Buck mode, DC-DC converter needs 2.1 V minimum to start, the supply can drop to 1.8 V after DC-DC converter
settles.
2. In Buck mode, DC-DC converter generates 1.8 V at VDD_1P8OUT and 1.5 V at VDD_1P5OUT_PMCIN pins.
VDD_1P8OUT should supply to VDD1, VDD2 and VDDA. VDD_1P5OUT_PMCIN should supply to VDD_RF1 and
VDD_RF2. VDD_RF3 can be either supplied by 1.5 V or 1.8 V.
Table 42. DC-DC Converter Specifications
Characteristics
Conditions
Symbol
Min
—
Typ
—
Max
1951
1401
Unit
mW
mW
DC-DC Converter Output
Power (total power output of
1p8V and 1p5V)
VDCDC_IN above 2.7 V Pdcdc_out1
VDCDC_IN below 2.7 V Pdcdc_out2
—
—
Switching Frequency2
DCDC_FREQ
—
DC-DC
reference
—
MHz
frequency
divided by 16
3
Half FET Threshold
Double FET Threshold
Buck Mode
I_half_FET
—
—
5
—
—
mA
mA
I_double_FET
40
DC-DC Conversion Efficiency
DCDC_EFF_buck
VDD_1P8_buck
—
90%
—
—
—
1.71
min(VDCD Vdc
C_IN_buck
, 3.5)4, 5
1.8 V Output Voltage
VDD_1P8 = 3.0 V
IDD_1P8_buck1
IDD_1P8_buck2
IDD_1P8_buck3
—
—
—
—
—
—
39
45
35
mA
mA
mA
1.5 V <= VDC_1P5
<= 1.7 V
VDCDC_IN=3.1 V
VDD_1P8 = 2.65 V
1.5 V <= VDC_1P5
<= 1.7 V
1.8 V Output Current6, 7
VDCDC_IN=2.7 V
VDD_1P8 = 1.8 V
1.5 V <= VDC_1P5
<= 1.7 V
VDCDC_IN=2.1 V
Consumed by Radio VDD_1P5_buck
for Pout<=+3.5 dBm
1.45
1.55
1.58
1.8
1.8
Vdc
Vdc
1.5 V Output Voltage
1.5 V Output Voltage
Consumed by Radio VDD_1P5_buck
for Pout=+5 dBm
1.6259
Table continues on the next page...
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KW36Z/35Z Electrical Characteristics
Table 42. DC-DC Converter Specifications (continued)
Characteristics
Conditions
Symbol
Min
—
Typ
—
Max
45
Unit
mA
μs
1.5 V Output Current6, 10
IDD_1P5_buck
DC-DC Transition Operating
Behavior
LSS➔Run
t_DCDCbuck_LSS➔R
UN
—
50
—
DC-DC Turn on Time
TDCDC_ON
—
—
2.211
3.11
—
—
ms
DC-DC Settling Time for
increasing voltage
TDCDC_SETTLE_buck
ms/V
DC-DC Settling Time for
decreasing voltage
C = capacitance
attached to the DC-
DC V1P8 output rail.
TDCDC_SETTLE_buck
—
(C*(V1–
V2)/I2
—
s
V1 = the initial output
voltage of the DC-DC
V2 = the final output
voltage of the DC-DC
I2 = the load on the
DC-DC output
expressed in
Amperes.
VDD_1P8 ripple
Typical ripple based
on NXP
VDD_1P8ripple
—
30
—
mV
recommended
hardware
configuration and
typical loading (MCU
only; no extra loads
placed on DC-DC
outputs)
VDD_1P5 ripple
Typical ripple based
on NXP
VDD_1P5ripple
—
30
—
mV
recommended
hardware
configuration and
typical loading (MCU
only; no extra loads
placed on DC-DC
outputs)
1. This is the steady state DC output power. Excessive transient current load from external device causes 1p8V and 1P5
output voltage unregulated temporary.
2. This is the frequency that is observed at LN and LP pins.
3. DC-DC reference frequency derives from the RF oscillator or the DC-DC internal oscillator.
4. The voltage output level can be controlled by programming DCDC_VDD1P8CTRL_TRG field in DCDC_REG3.
5. In Buck mode, the maximum VDD_1P8 output is the minimum of either VDCDC_IN_BUCK minus 50 mV or 3.5 V. For
example, if VDCDC_IN = 2.1 V, maximum VDD_1P8 is 2.05 V. If VDCDC_IN = 3.6 V, maximum VDD_1P8 is 3.5 V.
6. The output current specification in buck mode represents the maximum current the DC-DC converter can deliver. The
KW36Z/35Z radio and MCU blocks current consumption is not excluded. The maximum output power of the DC-DC
converter is 140 mW when VDCDC_IN is below 2.7 V and 195 mW when VDCDC_IN is above 2.7 V. The available supply
current for external device depends on the energy consumed by the internal peripherals in KW36Z/35Z.
7. When using DC-DC in low-power mode (pulsed mode), current load must be less than 1 mA.
8. User needs to program DCDC_VDD1P5CTRL_TRG_BUCK field in DCDC_REG3 register to ensure that a worst case
minimum of 1.45 V is available as VDD_1P5_buck. VDD_1P5 must not be programmed higher than VDD_1P8.
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
69
NXP Semiconductors
KW36Z/35Z Electrical Characteristics
9. User needs to program DCDC_VDD1P5CTRL_TRG_BUCK field in DCDC_REG3 register to ensure that a worst case
minimum of 1.55 V is available as VDD_1P5_buck. VDD_1P5 must not be programmed higher than VDD_1P8.
10. 1.5 V is intended to supply power to KW36Z/35Z. It is not designed to supply power to an external device.
11. Turn on time is measured from the application of power (to DCDC_IN) till the DCDC_REG0[DCDC_STS_DC_OK] bit is
set. Code execution may begin before the DCDC_REG0[DCDC_STS_DC_OK] bit is set. The full device specification is
not guaranteed until the bit sets.
6.7 Ratings
6.7.1 Thermal handling ratings
Table 43. Thermal handling ratings
Symbol
TSTG
Description
Min.
–55
—
Max.
150
Unit
°C
Notes
Storage temperature
Solder temperature, lead-free
1
2
TSDR
260
°C
1. Determined according to JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
6.7.2 Moisture handling ratings
Table 44. Moisture handling ratings
Symbol
Description
Min.
Max.
Unit
Notes
MSL
Moisture sensitivity level
—
3
—
1
1. Determined according to IPC/JEDEC Standard J-STD-020, Moisture/Reflow Sensitivity Classification for Nonhermetic
Solid State Surface Mount Devices.
6.7.3 ESD handling ratings
Table 45. ESD handling ratings
Symbol Description
Min.
Max.
Unit
Notes
VHBM
VCDM
Electrostatic discharge voltage, human body model
–2000
+2000
V
1
2
Electrostatic discharge voltage, charged-device model
All pins except the corner pins
–500
–750
–100
500
750
V
V
Corner pins only
ILAT
Latch-up current at ambient temperature of 105 °C
+100
mA
3
1. Determined according to JEDEC Standard JESD22-A114, Electrostatic Discharge (ESD) Sensitivity Testing Human
Body Model (HBM).
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Pin Diagrams and Pin Assignments
2. Determined according to JEDEC Standard JESD22-C101, Field-Induced Charged-Device Model Test Method for
Electrostatic-Discharge-Withstand Thresholds of Microelectronic Components.
3. Determined according to JEDEC Standard JESD78, IC Latch-Up Test.
6.7.4 Voltage and current operating ratings
Table 46. Voltage and current operating ratings
Symbol
VDD
IDD
Description
Min.
–0.3
—
Max.
3.8
Unit
V
Digital supply voltage
Digital supply current
IO pin input voltage
120
mA
V
VIO
–0.3
–25
VDD + 0.3
25
ID
Instantaneous maximum current single pin limit (applies to
all port pins)
mA
VDDA
Analog supply voltage
VDD – 0.3
GND
VDD + 0.3
VDCDC
V
V
VIO_DCDC
IO pins in the DC-DC voltage domain (DCDC_CFG and
PSWITCH)
7 Pin Diagrams and Pin Assignments
7.1 KW36Z Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control and Interrupt
Module is used to select the functionality for each GPIO pin. ALT0 is reserved for
analog functions on some GPIO pins. ALT1 – ALT9 are assigned to the available
digital functions on each GPIO pin. GPIO pins with a default of “disabled” are high
impedance after reset – their input and output buffers are disabled.
40
48
LQF
N
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
ALT8
ALT9
"Wett
able"
QFN
—
—
—
4
5
6
PTA16
PTA17
PTA18
DISABLED
DISABLED
DISABLED
PTA16/
LLWU_P4
SPI1_
SOUT
LPUART1_
RTS_b
TPM0_CH0
PTA17/
LLWU_P5
SPI1_SIN
LPUART1_
RX
CAN0_TX
CAN0_RX
TPM_
CLKIN1
PTA18/
LLWU_P6
SPI1_SCK
LPUART1_
TX
TPM2_CH0
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Pin Diagrams and Pin Assignments
40
48
LQF
N
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
ALT8
ALT9
"Wett
able"
QFN
—
7
PTA19
ADC0_SE5 ADC0_SE5 PTA19/
SPI1_PCS0 LPUART1_
CTS_b
TPM2_CH1
LLWU_P7
—
24
ADC0_DP0 ADC0_
DP0/
ADC0_
DP0/
CMP0_IN0
CMP0_IN0
—
—
25
41
ADC0_DM0 ADC0_
DM0/
ADC0_
DM0/
CMP0_IN1
CMP0_IN1
PTC5
DISABLED
PTC5/
LPTMR0_
ALT2
LPUART0_
RTS_b
TPM1_CH1
TPM2_CH0
BSM_CLK
LLWU_P13/
RF_NOT_
ALLOWED
—
42
PTC6
DISABLED
PTC6/
LLWU_P14/
RF_
I2C1_SCL
LPUART0_
RX
BSM_
FRAME
RFOSC_
EN
—
1
43
48
PTC7
DISABLED
DISABLED
PTC7/
LLWU_P15
SPI0_PCS2 I2C1_SDA
SPI0_PCS0 I2C0_SCL
LPUART0_
TX
TPM2_CH1
BSM_CLK
BSM_DATA
PTC19
PTC19/
LLWU_P3/
RF_
LPUART0_
CTS_b
LPUART1_
CTS_b
EARLY_
WARNING
2
3
4
5
6
1
2
3
8
9
PTA0
SWD_DIO
SWD_CLK
RESET_b
PSWITCH
PTA0
PTA1
PTA2
SPI0_PCS1
SPI1_PCS0
TPM1_CH0
TPM1_CH1
TPM0_CH3
SWD_DIO
SWD_CLK
RESET_b
PTA1
PTA2
PSWITCH
PSWITCH
DCDC_
CFG
DCDC_
CFG
DCDC_
CFG
7
8
9
10
11
13
VDCDC_IN VDCDC_IN VDCDC_IN
DCDC_LP
DCDC_LP
DCDC_LP
DCDC_
GND
DCDC_
GND
DCDC_
GND
10
11
12
14
DCDC_LN
DCDC_LN
DCDC_LN
VDD_
VDD_
VDD_
1P8OUT
1P8OUT
1P8OUT
12
13
—
DCDC_LN
DCDC_LN
DCDC_LN
15
VDD_
VDD_
VDD_
1P5OUT_
PMCIN
1P5OUT_
PMCIN
1P5OUT_
PMCIN
14
16
PTB0
DISABLED
PTB0/
LLWU_P8/
RF_
I2C0_SCL
CMP0_
OUT
TPM0_CH1
CLKOUT
CAN0_TX
RFOSC_
EN
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NXP Semiconductors
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Pin Diagrams and Pin Assignments
40
48
LQF
N
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
ALT8
ALT9
"Wett
able"
QFN
15
16
17
17
18
19
PTB1
PTB2
PTB3
ADC0_SE1/ ADC0_SE1/ PTB1/
DTM_RX
I2C0_SDA
DTM_TX
LPTMR0_
ALT1
TPM0_CH2
TPM1_CH0
TPM1_CH1
CMT_IRO
CAN0_RX
CMP0_IN5
CMP0_IN5
RF_
PRIORITY
ADC0_SE3/ ADC0_SE3/ PTB2/
CMP0_IN3
CMP0_IN3
RF_NOT_
ALLOWED
ADC0_SE2/ ADC0_SE2/ PTB3/
LPUART1_
CLKOUT
RTC_
CMP0_IN4
CMP0_IN4
ERCLK32K RTS_b
CLKOUT
18
19
20
21
VDD_0
PTB16
VDD_0
VDD_0
EXTAL32K
EXTAL32K
PTB16
PTB17
LPUART1_
RX
I2C1_SCL
I2C1_SDA
I2C1_SCL
TPM2_CH0
TPM2_CH1
TPM0_CH0
20
21
22
23
22
23
26
27
PTB17
PTB18
XTAL32K
NMI_b
XTAL32K
LPUART1_
TX
BSM_CLK
NMI_b
ADC0_SE4/ PTB18
CMP0_IN2
LPUART1_
CTS_b
TPM_
CLKIN0
VREFL/
VSSA
VREFL/
VSSA
VREFL/
VSSA
VREFH/
VREFH/
VREFH/
VREF_OUT VREF_OUT VREF_OUT
VDDA VDDA VDDA
XTAL_OUT XTAL_OUT XTAL_OUT
24
25
26
27
28
29
30
31
32
33
28
29
30
31
32
33
34
35
36
37
EXTAL
XTAL
EXTAL
EXTAL
XTAL
XTAL
VDD_RF3
ANT
VDD_RF3
ANT
VDD_RF3
ANT
GANT
GANT
GANT
VDD_RF2
VDD_RF1
PTC1
VDD_RF2
VDD_RF1
DISABLED
VDD_RF2
VDD_RF1
PTC1/
RF_
I2C0_SDA
LPUART0_
RTS_b
TPM0_CH2
SPI1_SCK
BSM_CLK
EARLY_
WARNING
34
35
36
38
39
40
PTC2
PTC3
PTC4
DISABLED
DISABLED
DISABLED
PTC2/
LLWU_P10 SWITCH
TX_
I2C1_SCL
I2C1_SDA
EXTRG_IN
LPUART0_
RX
CMT_IRO
DTM_RX
DTM_TX
SPI1_
SOUT
BSM_
FRAME
PTC3/ RX_
LLWU_P11 SWITCH
LPUART0_
TX
TPM0_CH1
TPM1_CH0
SPI1_SIN
CAN0_TX
PTC4/
LPUART0_
CTS_b
BSM_DATA SPI1_PCS0 CAN0_RX
LLWU_P12/
BLE_RF_
ACTIVE
37
38
44
45
VDD_1
PTC16
VDD_1
VDD_1
DISABLED
PTC16/
LLWU_P0/
SPI0_SCK
I2C0_SDA
LPUART0_
RTS_b
TPM0_CH3
LPUART1_
RTS_b
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
73
NXP Semiconductors
Pin Diagrams and Pin Assignments
40
48
LQF
N
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
ALT8
ALT9
"Wett
able"
QFN
RF_
STATUS
39
46
47
PTC17
PTC18
DISABLED
PTC17/
SPI0_
SOUT
I2C1_SCL
I2C1_SDA
LPUART0_
RX
BSM_
FRAME
DTM_RX
DTM_TX
LPUART1_
RX
LLWU_P1/
RF_EXT_
OSC_EN
40
41
DISABLED
NA
PTC18/
LLWU_P2
SPI0_SIN
LPUART0_
TX
BSM_DATA
LPUART1_
TX
49-64 Ground
7.2 KW36Z Pinouts
KW36Z device pinouts are shown in the figures below.
GANT
30
29
28
27
26
25
24
23
22
21
PTC19
PTA0
1
2
41
ANT
VDD_RF3
XTAL
PTA1
3
PTA2
4
EXTAL
XTAL_OUT
VDDA
PSWITCH
DCDC_CFG
VDCDC_IN
DCDC_LP
DCDC_GND
DCDC_LN
5
6
7
VREFH/VREF_OUT
VREFL/VSSA
PTB18
8
9
10
*pin 41 is ground
Figure 19. 40-pin "Wettable" HVQFN pinout diagram
74
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
Pin Diagrams and Pin Assignments
VDD_RF1
VDD_RF2
GANT
36
35
34
33
32
31
30
29
28
27
26
25
PTA0
PTA1
1
2
PTA2
3
49
53
57
61
50
54
58
62
51
55
59
63
52
56
60
64
ANT
PTA16
4
VDD_RF3
XTAL
PTA17
5
PTA18
6
PTA19
EXTAL
7
PSWITCH
DCDC_CFG
VDCDC_IN
DCDC_LP
DCDC_LN
XTAL_OUT
VDDA
8
9
VREFH/VREF_OUT
VREFL/VSSA
ADC0_DM0
10
11
12
*pin 49 - 64 are ground
Figure 20. 48-pin LQFN pinout diagram
7.3 KW35Z Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control and Interrupt
Module is used to select the functionality for each GPIO pin. ALT0 is reserved for
analog functions on some GPIO pins. ALT1 – ALT9 are assigned to the available
digital functions on each GPIO pin. GPIO pins with a default of “disabled” are high
impedance after reset – their input and output buffers are disabled.
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
75
NXP Semiconductors
Pin Diagrams and Pin Assignments
48
LQF
N
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
ALT8
ALT9
49-64 Ground
NA
1
2
3
4
PTA0
PTA1
PTA2
PTA16
SWD_DIO
SWD_CLK
RESET_b
DISABLED
PTA0
SPI0_PCS1
SPI1_PCS0
TPM1_CH0
TPM1_CH1
TPM0_CH3
TPM0_CH0
SWD_DIO
SWD_CLK
RESET_b
PTA1
PTA2
PTA16/
LLWU_P4
SPI1_SOUT
SPI1_SIN
5
6
7
PTA17
DISABLED
DISABLED
ADC0_SE5
PSWITCH
PTA17/
LLWU_P5
TPM_
CLKIN1
PTA18
PTA18/
LLWU_P6
SPI1_SCK
SPI1_PCS0
TPM2_CH0
PTA19
ADC0_SE5
PSWITCH
PTA19/
LLWU_P7
TPM2_CH1
8
PSWITCH
9
DCDC_CFG DCDC_CFG DCDC_CFG
10
11
12
13
14
VDCDC_IN
DCDC_LP
DCDC_LN
VDCDC_IN
DCDC_LP
DCDC_LN
VDCDC_IN
DCDC_LP
DCDC_LN
DCDC_GND DCDC_GND DCDC_GND
VDD_
VDD_
VDD_
1P8OUT
1P8OUT
1P8OUT
15
16
VDD_
1P5OUT_
PMCIN
VDD_
1P5OUT_
PMCIN
VDD_
1P5OUT_
PMCIN
PTB0
DISABLED
PTB0/
I2C0_SCL
CMP0_OUT
TPM0_CH1
CLKOUT
LLWU_P8/
RF_
RFOSC_EN
17
18
19
PTB1
PTB2
PTB3
ADC0_SE1/
CMP0_IN5
ADC0_SE1/
CMP0_IN5
PTB1/
RF_
PRIORITY
DTM_RX
I2C0_SDA
DTM_TX
LPTMR0_
ALT1
TPM0_CH2
TPM1_CH0
TPM1_CH1
CMT_IRO
ADC0_SE3/
CMP0_IN3
ADC0_SE3/
CMP0_IN3
PTB2/
RF_NOT_
ALLOWED
ADC0_SE2/
CMP0_IN4
ADC0_SE2/
CMP0_IN4
PTB3/
ERCLK32K
CLKOUT
RTC_
CLKOUT
20
21
22
23
VDD_0
PTB16
PTB17
PTB18
VDD_0
VDD_0
EXTAL32K
XTAL32K
NMI_b
EXTAL32K
XTAL32K
PTB16
PTB17
PTB18
I2C1_SCL
I2C1_SDA
I2C1_SCL
TPM2_CH0
TPM2_CH1
TPM0_CH0
BSM_CLK
NMI_b
ADC0_SE4/
CMP0_IN2
TPM_
CLKIN0
24
25
ADC0_DP0
ADC0_DM0
ADC0_DP0/
CMP0_IN0
ADC0_DP0/
CMP0_IN0
ADC0_DM0/ ADC0_DM0/
CMP0_IN1 CMP0_IN1
76
NXP Semiconductors
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
Pin Diagrams and Pin Assignments
48
LQF
N
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
ALT8
ALT9
26
VREFL/
VSSA
VREFL/
VSSA
VREFL/
VSSA
27
VREFH/
VREFH/
VREFH/
VREF_OUT
VREF_OUT
VREF_OUT
28
29
30
31
32
33
34
35
36
37
VDDA
VDDA
VDDA
XTAL_OUT
EXTAL
XTAL
XTAL_OUT
EXTAL
XTAL_OUT
EXTAL
XTAL
XTAL
VDD_RF3
ANT
VDD_RF3
ANT
VDD_RF3
ANT
GANT
GANT
GANT
VDD_RF2
VDD_RF1
PTC1
VDD_RF2
VDD_RF1
DISABLED
VDD_RF2
VDD_RF1
PTC1/
RF_EARLY_
WARNING
I2C0_SDA
LPUART0_
RTS_b
TPM0_CH2
SPI1_SCK
BSM_CLK
38
39
40
PTC2
PTC3
PTC4
DISABLED
DISABLED
DISABLED
PTC2/
LLWU_P10
TX_SWITCH I2C1_SCL
LPUART0_
RX
CMT_IRO
DTM_RX
DTM_TX
SPI1_SOUT
SPI1_SIN
BSM_
FRAME
PTC3/
LLWU_P11
RX_
I2C1_SDA
EXTRG_IN
LPUART0_
TX
TPM0_CH1
TPM1_CH0
SWITCH
PTC4/
LPUART0_
CTS_b
BSM_DATA
SPI1_PCS0
LLWU_P12/
BLE_RF_
ACTIVE
41
42
43
PTC5
PTC6
PTC7
DISABLED
DISABLED
DISABLED
PTC5/
LPTMR0_
ALT2
LPUART0_
RTS_b
TPM1_CH1
TPM2_CH0
BSM_CLK
LLWU_P13/
RF_NOT_
ALLOWED
PTC6/
LLWU_P14/
RF_
I2C1_SCL
I2C1_SDA
LPUART0_
RX
BSM_
FRAME
RFOSC_EN
PTC7/
LLWU_P15
SPI0_PCS2
LPUART0_
TX
TPM2_CH1
TPM0_CH3
BSM_DATA
44
45
VDD_1
PTC16
VDD_1
VDD_1
DISABLED
PTC16/
LLWU_P0/
RF_STATUS
SPI0_SCK
I2C0_SDA
I2C1_SCL
LPUART0_
RTS_b
46
PTC17
DISABLED
PTC17/
SPI0_SOUT
LPUART0_
RX
BSM_
FRAME
DTM_RX
DTM_TX
LLWU_P1/
RF_EXT_
OSC_EN
47
48
PTC18
PTC19
DISABLED
DISABLED
PTC18/
LLWU_P2
SPI0_SIN
I2C1_SDA
I2C0_SCL
LPUART0_
TX
BSM_DATA
BSM_CLK
PTC19/
LLWU_P3/
SPI0_PCS0
LPUART0_
CTS_b
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
77
NXP Semiconductors
Pin Diagrams and Pin Assignments
48
LQF
N
Pin Name
Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
ALT8
ALT9
RF_EARLY_
WARNING
7.4 KW35Z Pinouts
KW35Z device pinouts are shown in the figures below.
VDD_RF1
VDD_RF2
GANT
36
35
34
33
32
31
30
29
28
27
26
25
PTA0
PTA1
1
2
PTA2
3
49
53
57
61
50
54
58
62
51
55
59
63
52
56
60
64
ANT
PTA16
4
VDD_RF3
XTAL
PTA17
5
PTA18
6
PTA19
EXTAL
7
PSWITCH
DCDC_CFG
VDCDC_IN
DCDC_LP
DCDC_LN
XTAL_OUT
VDDA
8
9
VREFH/VREF_OUT
VREFL/VSSA
10
11
12
ADC0_DM0
*pin 49 - 64 are ground
Figure 21. 48-pin LQFN pinout diagram
78
NXP Semiconductors
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
Pin Diagrams and Pin Assignments
7.5 Module Signal Description Tables
The following sections correlate the chip-level signal name with the signal name used
in the chapter of the module. They also briefly describe the signal function and
direction.
7.5.1 Core Modules
This section contains tables describing the core module signal descriptions.
Table 47. SWD Module Signal Descriptions
SoC Signal Name
SWD_DIO
Module Signal Name
SWD_DIO
Description
I/O
Serial Wire Debug Data
Input/Output1
Serial Wire Clock2
I/O
I
SWD_CLK
SWD_CLK
1. Pulled up internally by default
2. Pulled down internally by default
7.5.2 Radio Modules
This section contains tables describing the radio signals.
Table 48. Radio Module Signal Descriptions
Module Signal Name
ANT
Pin Direction
Pin Name
Pin Description
O
O
ANT
Antenna
BLE_RF_ACTIVE
BLE_RF_ACTIVE
An output which is asserted prior to any Radio
event and remains asserted for the duration of the
event.
BSM_CLK
O
BSM_CLK
Bit Streaming Mode (BSM) clock signal. 1 MHz bit
rate clock. BSM_DATA and BSM_FRAME are
synchronized to BSM_CLK. External device should
capture BSM_FRAME and BSM_DATA on rising
edge of BSM_CLK.
BSM_DATA
O
O
BSM_DATA
Serial Bluetooth LE packet bit stream, LSB-first.
Valid on rising edge of BSM_CLK.
BSM_FRAME
BSM_FRAME
Framing signal to indicate the start of reception.
Active high.
DTM_RX
DTM_TX
GANT
I
DTM_RX
DTM_TX
GANT
Direct Test Mode Receive
Direct Test Mode Transmit
Antenna ground
O
I
Table continues on the next page...
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79
NXP Semiconductors
Pin Diagrams and Pin Assignments
Table 48. Radio Module Signal Descriptions (continued)
Module Signal Name
Pin Direction
Pin Name
RF_STATUS
Pin Description
RF_STATUS
O
O
An output which indicates when the Radio is in an
Rx or Tx event; software can also control this
signal directly.
RF_PRIORITY
RF_PRIORITY
An output which indicates to the external WiFi
device that the Radio event is a high priority and it
needs access to the 2.4 GHz antenna.
RF_EARLY_WARNING O
RF_EARLY_WARNING Bluetooth LE LL generated signal which can be
used to wake an external sensor to make a
measurement before a Bluetooth LE event.
RF_NOT_ALLOWED
RF_TX_CONF
I
I
RF_NOT_ALLOWED
RF_TX_CONF
External signal which causes the internal Radio to
cease radio activity.
Signal from an external Radio which indicates the
availability of the 2.4 GHz antenna to the internal
Radio.
NOTE: This is a GPIO, not a dedicated PIN.
RX_SWITCH
TX_SWITCH
O
O
RX_SWITCH
TX_SWITCH
Front End Module receive mode signal.
Front End Module transmit mode signal.
Table 49. Radio Module Miscellaneous Pin Descriptions
Pin Name
Pad Direction
Pin Name
Pin Description
RF_INT_OSC_EN
I
RF_RFOSC_EN
External request to turn on the Radio's internal RF
oscillator.
RF_EXT_OSC_EN
O
RF_EXT_OSC_EN
Internal request to turn on an External oscillator for
use by the internal Radio. The request can also be
from the SoC if it is using the RF oscillator as its
clock.
7.5.3 System Modules
This section contains tables describing the system signals.
Table 50. System Module Signal Descriptions
SoC Signal Name
NMI_b
Module Signal Name
Description
Non-maskable interrupt
Reset bidirectional signal
Power supply
I/O
—
—
I
RESET_b
VDD_[1:0]
Ground
I/O
VDD
I
I
I
I
VSS
Ground
VDD_RF[3:1]
VDCDC_IN
VDD_RF
VDCDC_IN
Radio power supply
VDCDC_IN
Table continues on the next page...
80
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
Pin Diagrams and Pin Assignments
Table 50. System Module Signal Descriptions (continued)
SoC Signal Name
VDD_1P8OUT
Module Signal Name
VDD_1P8
Description
I/O
DC-DC 1.8 V Regulated
Output / Input in bypass
I/O
I/O
VDD_1P5OUT_PMCIN
VDD_1P5/VDD_PMC
DC-DC 1.5 V Regulated
Output / PMC Input in bypass
PSWITCH
DCDC_CFG
DCDC_LP
DCDC_LN
PSWITCH
DCDC_CFG
DCDC_LP
DCDC_LN
DC-DC enable switch
I
I
DC-DC switch mode select
DC-DC inductor input positive I/O
DC-DC inductor input
negative
I/O
DCDC_GND
DCDC_GND
DC-DC ground
I
Table 51. LLWU Module Signal Descriptions
SoC Signal Name
Module Signal Name
LLWU_P[15:0]
Description
Wake-up inputs
I/O
LLWU_P[15:0]
I
7.5.4 Clock Modules
This section contains tables for Clock signal descriptions.
Table 52. Clock Module Signal Descriptions
SoC Signal Name
EXTAL
Module Signal Name
EXTAL
Description
I/O
26 MHz/32 MHz External
clock/Oscillator input
I
XTAL
XTAL
26 MHz/32 MHz Oscillator
input
I
XTAL_OUT
XTAL_OUT_EN
EXTAL32K
XTAL_OUT
XTAL_OUT_ENABLE
EXTAL32K
26 MHz/32 MHz Clock
output
O
I
26 MHz/32 MHz Clock
output enable for XTAL_OUT
32 kHz External clock/
Oscillator input
I
XTAL32K
CLKOUT
XTAL32K
CLKOUT
32 kHz Oscillator input
Internal clocks monitor
I
O
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
81
NXP Semiconductors
Pin Diagrams and Pin Assignments
7.5.5 Analog Modules
This section contains tables for Analog signal descriptions.
Table 53. ADC0 Signal Descriptions
SoC Signal Name
ADC0_DM0
Module Signal Name
DADM0
Description
I/O
ADC Channel 0 Differential
Input Negative
I
I
ADC0_DP0
ADC0_SE[5:1]
VREFH
DADP0
AD[5:1]
VREFSH
ADC Channel 0 Differential
Input Positive
ADC Channel 0 Single-ended I
Input n
Voltage Reference Select
High
I
VDDA
VSSA
VDDA
VSSA
Analog Power Supply
Analog Ground
I
I
Table 54. CMP0 Signal Descriptions
SoC Signal Name
Module Signal Name
IN[5:0]
CMP0
Description
Analog voltage inputs
Comparator output
I/O
I/O
CMP0_IN[5:0]
CMP0_OUT
I
O
Table 55. VREF Signal Descriptions
SoC Signal Name
VREF_OUT
Module Signal Name
VREF_OUT
Description
Internally generated voltage
reference output
O
7.5.6 Timer Modules
This section contains tables describing timer module signals.
Table 56. TPM0 Module Signal Descriptions
SoC Signal Name
TPM_CLKIN[1:0]
Module Signal Name
TPM_EXTCLK
TPM_CH[3:0]
Description
External clock
TPM channel
I/O
I
TPM0_CH[3:0]
I/O
82
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
Pin Diagrams and Pin Assignments
Table 57. TPM1 Module Signal Descriptions
SoC Signal Name
TPM_CLKIN[1:0]
TPM1_CH[1:0]
Module Signal Name
TPM_EXTCLK
TPM_CH[1:0]
Description
External clock
TPM channel
I/O
I/O
I
I/O
Table 58. TPM2 Module Signal Descriptions
SoC Signal Name
Module Signal Name
TPM_EXTCLK
TPM_CH[1:0]
Description
External clock
TPM channel
TPM_CLKIN[1:0]
TPM2_CH[1:0]
I
I/O
Table 59. LPTMR0 Module Signal Descriptions
SoC Signal Name
LPTMR0_ALT[2:1]
Module Signal Name
Description
I/O
I/O
LPTMR0_ALT[2:1]
Pulse counter input pin
I
Table 60. RTC Module Signal Descriptions
SoC Signal Name
RTC_CLKOUT
Module Signal Name
RTC_CLKOUT
Description
1 Hz square-wave output
O
7.5.7 Communication Interfaces
This section contains tables for the signal descriptions for the communication
modules.
Table 61. SPI0 Module Signal Descriptions
SoC Signal Name
SPI0_PCS0
Module Signal Name
PCS0/SS
Description
Chip Select/Slave Select
Chip Select
I/O
I/O
O
SPI0_PCS[2:1]
SPI0_SCK
PCS[2:1]
SCK
Serial Clock
I/O
I
SPI0_SIN
SIN
Data In
SPI0_SOUT
SOUT
Data Out
O
Table 62. SPI1 Module Signal Descriptions
SoC Signal Name
SPI1_PCS0
Module Signal Name
SPI1_PCS0
Description
I/O
Chip Select/Slave Select
I/O
Table continues on the next page...
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
83
NXP Semiconductors
Pin Diagrams and Pin Assignments
Table 62. SPI1 Module Signal Descriptions (continued)
SoC Signal Name
SPI1_SCK
Module Signal Name
SCK
Description
Serial Clock
I/O
I/O
I
SPI1_SIN
SIN
Data In
SPI1_SOUT
SOUT
Data Out
O
Table 63. I2C0 Module Signal Descriptions
SoC Signal Name
Module Signal Name
SCL
SDA
Description
I2C serial clock line
I2C serial data line
I/O
I2C0_SCL
I2C0_SDA
I/O
I/O
Table 64. I2C1 Module Signal Descriptions
SoC Signal Name
Module Signal Name
SCL
SDA
Description
I2C serial clock line
I2C serial data line
I/O
I/O
I/O
I2C1_SCL
I2C1_SDA
I/O
I/O
Table 65. CAN0 Signal Descriptions (KW36 only)
SoC Signal Name
Module Signal Name
CAN RX
CAN TX
Description
CAN Receive Pin
CAN Transmit Pin
CAN0_RX
CAN0_TX
I
O
Table 66. LPUART0 Module Signal Descriptions
SoC Signal Name
Module Signal Name
LPUART CTS
Description
Clear To Send
LPUART0_CTS_b
LPUART0_RTS_b
LPUART0_RX
I
LPUART RTS
LPUART RxD
LPUART TxD
Request To Send
O
I
Receive Data
Transmit Data1
LPUART0_TX
I/O
1. This pin is normally an output, but is an input (tristated) in single wire mode whenever the transmitter is disabled or
transmit direction is configured for receive data
Table 67. LPUART1 Module Signal Descriptions (KW36 only)
SoC Signal Name
LPUART1_CTS_b
Module Signal Name
LPUART CTS
Description
Clear To Send
I/O
I
LPUART1_RTS_b
LPUART1_RX
LPUART1_TX
LPUART RTS
LPUART RxD
LPUART TxD
Request To Send
Receive Data
Transmit Data1
O
I
I/O
84
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
Package Information
1. This pin is normally an output, but is an input (tristated) in single wire mode whenever the transmitter is disabled or
transmit direction is configured for receive data
7.5.8 Human-Machine Interfaces(HMI)
This section contains tables describing the HMI signals.
Table 68. GPIO Module Signal Descriptions
SoC Signal Name
PTA[19:16][2:0]
Module Signal Name
Description
I/O
PORTA19-16, 2-0
General Purpose Input/
Output
I/O
I/O
I/O
PTB[18:16][3:0]
PTC[19:16][7:1]
PORTB18-16, 3-0
PORTC19-16, 7-1
General Purpose Input/
Output
General Purpose Input/
Output
8 Package Information
8.1 Obtaining package dimensions
Package dimensions are available in package drawings.
To find a package drawing, go to nxp.com and perform a keyword search for the
document number of the drawing:
Table 69. Packaging Dimensions
If you want the drawing for this package
40-pin "Wettable" HVQFN (6x6)
Then use this document number
98ASA01025D
98ASA00694D
48-pin LQFN (7x7)
9 Part identification
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
85
NXP Semiconductors
Part identification
9.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
9.2 Format
Part numbers for this device have the following format:
Q KW## A FFF R T PP CC N
9.3 Fields
This table lists the possible values for each field in the part number (not all
combinations are valid):
Table 70. Part number fields descriptions
Field
Description
Values
Q
Qualification status
• M = Fully qualified, general market flow
• P = Prequalification
KW##
Kinetis Wireless family
• KW35
• KW36
A
Key attribute
• Z = Industrial Qualification
• 512 = 512 KB
FFF
T
Program flash memory size
Temperature range (°C)
• V = –40 to 105
• C = –40 to 85
PP
Package identifier
• HT = 48 LQFN (7 mm x 7 mm)
• FP = 40 "Wettable" HVQFN (6 mm x 6 mm)
CC
N
Maximum CPU frequency (MHz)
Packaging type
• 4 = 48 MHz
• (Blank) = Tray
• R = Tape and reel
9.4 Example
This is an example part number:
MKW35Z512VHT4
86
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
Revision History
10 Revision History
Table 71. Revision History
Rev. No.
Date
Substantial Changes
Rev 8
05/2020
• Updated Tx output power to 5 dBm from 3.5 dBm throughout.Also preceded 5 dBM with a
plus "+" sign.
• Replaced VDD_XTAL with VDD_RF3.
• Appended the second row 'Supply current Rx On with DC-DC converter enable' with the
following text: VDD_1P5_buck=1.5 V in Receiver Feature Summary.
• In Top level Transmitter Specifications - Table 5 :
• Appended the rows for supply current Tx On with PRF and DC-DC converter enabled
for 0 dBM with VDD_1P5_buck=1.5 V.
• Added rows related to supply current Tx On with PRF = +3.5 dBm and 5dBm along
with associated footnotes.
• Updated symbol of Output RF Frequency to fRFout from fin.
• Added row for maximum RF Output Power; LDO-HF bumped along with an
associated footnote.
• Added Figure 4.
• Added Table 7. Also modified title of Table 6.
• Added VDD_1P5 specification in Voltage and current operating requirements.
• Added VPOR_VDD_1P5 specification in LVD and POR operating requirements
• Added VOH performance for normal drive pad at 1.71 V ≤ VDD ≤ 2.7 V, IOH = –1 mA in
Voltage and current operating behaviors.
• Added Table 17. Also updated title of Table 16.
• Updated VCDM ratings in ESD handling ratings.
• Added VDD_1P5 symbol to "Bypass Mode Supply Voltage (RF and Analog)" in Table 41.
• In Table 42 :
• Updated specifications of DC-DC Converter Output Power. Added conditions,
VDCDC_IN above 2.7 V and below 2.7 V.
• Updated specifications of 1.8 V Output Current.
• Updated minimum value to 1.45 V in "1.5 V Voltage Output" for Pout<=+3.5 dBM.
Updated the corresponding footnote with the correct value of 1.45 V.
• Added a separate row for "1.5 V Voltage Output" for Pout=+5 dBM along with a
footnote.
• Updated maximum value of 1.5 V Output Current to 45.
Rev 7
09/2019
• Changed 40-pin "Wettable" QFN to 40-pin "Wettable" HVQFN throughout.
• Applied new NXP Brand Guidelines for Bluetooth Low Energy. Removed references of
BLE and replaced with Bluetooth LE.
• Added "Top Line Marking" column to the Orderable parts details table.
• Removed "Galois counter mode (AES-GCM)" and "DES modes" features of LTC, and
flash access control feature from Security Features.
• Removed "Logic Input Voltage Low/High" rows from Table 2.
• Added the following footnote in Table 6 : "TX continuous wave power output at the RF
pins with the recommended matching components mounted on PCB.".
• Removed the following footnote from Table 13 : "Supported through the connectivity
software in its pre-defined Deep Sleep Modes.".
• Added the following footnote to Table 14 : "The device was configured in buck mode auto-
start to perform the measurements. The DCDC_IN was powered with 3.0 V.
VDD_1P8OUT was configured to output 1.8 V and VDD_1P5OUT_PMCIN was configured
to output 1.5 V."
• Updated Typical value of IDD_RUN at 70 °C to 5.92 in Table 14.
Table continues on the next page...
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
87
NXP Semiconductors
Revision History
Table 71. Revision History (continued)
Rev. No.
Date
Substantial Changes
• Added the following footnote to VLPS, LLSx and VLLSx modes in Table 14 : "DCDC
configured in pulsed mode.".
• Replaced standard JESD51-2 with JESD51-2A in the footnotes in Thermal attributes.
• Corrected name of vec_xtal32 to vec_extal32 in 32 kHz Oscillator Frequency Specifications.
• Removed "Flash timing specifications – program and erase" and "Flash high voltage
current behaviors" tables.
• Added DCDC internal oscillator row in Table 41.
• Updated Table 42 as follows:
• In Switching Frequency row, updated the Typical value to DCDC reference
frequency divided by 16 and added the following footnote to it: "DCDC reference
frequency is derived from the RF oscillator or the DCDC internal oscillator".
• Corrected maximum value of VDD_1P8 output in the footnote 6, in Table 42. DC-DC
Converter Specifications, from 3 V to 3.5 V.
• Updated minimum and maximum values of "1.5V Output Voltage". Also specified the
condition as "Consumed by radio".
• Added VDD_1P8 ripple and VDD_1P5 ripple rows.
• Updated introductory text beginning "The Port Control and Interrupt Module is used to
select the functionality for...." in KW36Z Signal Multiplexing and Pin Assignments. Same
update done for KW35Z as well.
• Updated "DEFAULT" column to correct "DISABLED" status of PTA19, PTB1/2/3 pin
names in KW36/35 pinouts.
• Corrected location of ground pins in 48-pin LQFN pinout diagram - Figure 20.
• Removed silicon revision (R) field from Table 68. Part number fields descriptions.
Rev 6
09/2018
• Changed ARM to Arm and applied registered trademark to Cortex on first instance.
• Updated Related Resources table for Web release.
• Added space between value and unit throughout.
• Removed SPI Clock Rate row from Radio Operating Conditions.
• Added figure title to Figure 3 in the topic Transmit and PLL Feature Summary.
• Updated max values of IDD_STOP, IDD_LLS3/LLS2, IDD_VLLS0 (POR PO = ) in Table
13
• Updated Table 25 and Table 26.
• Footnote 3 - "Write endurance represents the number of writes......" was added to Table
28 - NVM reliability specifications. It was missed out in the last release Rev 5.
• Backpage was also updated.
Rev 5
07/2018
• Updated title of the document to 'MKW36Z/35Z Data Sheet' from 'MKW35Z/36Z Data
Sheet'.
• Updated SoC name KW35A with KW36A/35A throughout.
• Replaced QFN with "Wettable" QFN throughout
• Added package drawings on front page and updated features under Multi-Standard Radio
section as follows: Modulation index: added 1.0 to the list.
• Updated Typical Rx Current and Typical Tx current values to 6.3 mA and 5.7 mA
respectively.
• Updated Receiver Sensitivity to –99 from –100 dBm in Radio features. Also added support
of 1 Mbps PHY to BLE link Layer hardware.
• Updated Low Power Mode (VLLS0) Current value to 258 nA from 182 nA.
• Added "Industrial Qualification" under Operating Characteristics on front page feature list.
• Replaced column name "Tier" with "Qualification" in this table.
• Updated Introduction section.
• Removed Radio version number "V2.1" from Block Diagram.
• Updated Radio features, Microcontroller features, and System features.
• Appended "(Zero IF)" to Direct Conversion Receiver in Transceiver Description.
• Edited Key Specifications.
Table continues on the next page...
88
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
Revision History
Table 71. Revision History (continued)
Rev. No.
Date
Substantial Changes
• Updated typical and minimum values in Table 3. Also updated footnote 7 to "BLE adjacent
and alternate selectivity performance is measured with modulated interference signals.".
• In Table 4 :
• updated and added receiver specifications with GFSK modulations, and
• updated footnote as follows: Selectivity measured with an unmodulated blocker
except for GFSK BT=0.5, h=0.5 1mbps and GFSK BT=0.5, h=0.32 1mbps. The
desired signal is set at –85 dBm.
.
• Updated typical and maximum values in Table 5. Also updated footnote for TXH2 and
TXH3 symbols as follows: "Harmonic Levels based on recommended 2 component match.
Transmit harmonic levels depend on the quality of matching components. Additional
harmonic margin using a 3rd matching component (1x shunt capacitor) is possible."
• Updated typical and maximum values in Table 13 and Table 14.
• Updated typical values in Table 16. Also added specifications of STOP and RUN modes of
radio state Tx (at +3.5 dBm).
• Updated 48-pin LQFN and 40-pin QFN values in Thermal attributes table. Removed
thermal metrics and kept thermal attributes RθJA and ΨJT. Also updated notes and added
information about how to use the thermal characterization parameter, ΨJT.
• Added following text in Reference Oscillator Specification : "The table below shows the
recommended crystal specifications. Note that these are recommendations.....". Also
updated 32M/26M typical values of Oscillator Startup Time to 500 μs.
• Updated typical and maximum values in Table 1
• Updated minimum, typical and maximum value of Temp sensor slope in Table 30
• Corrected spec name of Buck mode in DC-DC configuration to VDCDC_IN from VDDDCDC_IN
throughout.
• In Table 42,
• updated footnote example corresponding to '1.8V Output Voltage',
• updated maximum value in '1.8V Output Voltage' from "min(VDCDC_IN_buck, 3)" to
"min(VDCDC_IN_buck, 3.5)", and
• added the following information to the footnote corresponding to '1.5V Output
Voltage': "VDD_1P5 must not be programmed higher than VDD_1P8."
• Added VIO_DCDC row in Voltage and current operating ratings.
• Removed 40-pin "Wettable" QFN pinout diagram and signal names from KW35Z Signal
Multiplexing and Pin Assignments. Also updated signal name at pin 17 and pin 19 of 40
"Wettable" QFN and 48 LQFN in ALT1 functionality to PTB3/ERCLK32K in KW36A Signal
Multiplexing and Pin Assignments and KW35Z Signal Multiplexing and Pin Assignments.
Rev 4
10/2017
• BLE version 4.2 updated to 5.0.
• Updated maximum value of voltage range to 3.6 V.
• Minimum voltage range updated to 1.71 V.
• Updated Generic FSK modulation BT and receiver sensitivity from –100 dBm to –99 dBm.
• Added support of up to 26 devices by Whitelist and 8 private resolvable addresses in
hardware in the section Radio features.
• Updated number of GPIO digital pins in the 48-pin package to 25 in Peripheral features.
• Updated note text in Radio operating conditions as follows: "The recommended crystal
accuracy is 40 ppm including initial accuracy, mechanical, temperature and aging
factors."
• Updated maximum values in Power mode transition operating behaviors.
• Updated Typical values in Table 13 and Table 14. Also added the following note to the
tables for Run mode: "Radio is off".
• Updated Typical values in Table 16 as TBDs.
• Minor updates in introductory text of Reference Oscillator Specification section. Also
updated typical value of TOSC to 680 μs in .
Table continues on the next page...
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
89
NXP Semiconductors
Revision History
Table 71. Revision History (continued)
Rev. No.
Date
Substantial Changes
• Added 32 kHz Oscillator Frequency Specifications section.
• Updated Table 42 section.
• Added the following parameters: Switching Frequency, Half FET Threshold, Double
FET Threshold, DC-DC Conversion Efficiency, DCDC Settling Time for increasing
voltage and DCDC Settling Time for decreasing voltage.
• Updated Typ. value of the 'DCDC Turn on Time' parameter and added a footnote.
Rev 3
Rev 2
06/2017
03/2017
Updated Typical values in Table 13 and Table 14.
• Modified structure of the document to include orderable part numbers and Related
Resources table after the features list.
• Specified all supported part numbers on the front page.
• Specified the baudrate supported by FlexCAN in the features list.
• Removed support of DCDC Boost mode.
• Changed RSSI Range maximum value to 5 dBm in Table 3 and added the following
footnote: "With RSSI_CTRL_0.RSSI_ADJ field calibrated to account for antenna to RF
input losses.".
• Added Table 6 to show mapping relationship between TX_POWER and DBM. Also added
the corresponding graph.
• Added DCDC Inductor specifications in Table 41.
• Updated Table 42 :
• Removed repetitive fields from the table.
• Specified Typ. value of "DCDC Transition Operating Behavior" as 50 μs.
• Updated footnote 3 as follows: "In Buck mode, the maximum VDD_1P8 output is the
minimum of either VDCDC_IN_BUCK minus 50 mV or 3 V. For example, if
VDCDC_IN = 1.85 V, maximum VDD_1P8 is 1.8 V. If VDCDC_IN = 4.2 V, maximum
VDD_1P8 is 3 V".
• Replaced Laminate QFN with LQFN throughout.
• Added radio signals in Table 48.
• Added document numbers of the supported package drawings in Table 69.
• Added Part identification section.
Rev 1
01/2017
• Updated maximum supply voltage from 4.2 to 4.25 V.
• Corrected MBAN Channel numbering in Channel Plan for Bluetooth Low Energy.
• Corrected "Radio" description for VLLS1 and VLLS0 power modes in Table 8.
• Updated Section 9 Pin Diagrams and Pin Assignments.
• Corrected pin name from VDD_1P45OUT_PMCIN to VDD_1P5OUT_PMCIN
• Added ground pads in the pin diagrams
• Added the following note in Diagram: Typical IDD_RUN operating behavior : "The results
in the following graphs are obtained using the device in Bypass mode."
• Added TOSC row in , Reference Crystal Specification.
• Added DCDC Transition Operating Behavior and DCDC turn on Time in Table 42, DC-DC
Converter Specifications.
• Added the following note in Table 48 for the RF_TX_CONF pin: "This is a GPIO, not a
dedicated PIN."
Rev 0
11/2016
Initial Internal Release
90
MKW36Z/35Z Data Sheet, Rev. 8, 05/2020
NXP Semiconductors
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