首页 |元器件品牌

MM908E624AYEWR2 [NXP]

8-BIT, FLASH, 32MHz, MICROCONTROLLER, PDSO54, 0.65 MM PITCH, ROHS COMPLIANT, SOIC-54;
MM908E624AYEWR2
型号： MM908E624AYEWR2
厂家： NXP    NXP
描述：

8-BIT, FLASH, 32MHz, MICROCONTROLLER, PDSO54, 0.65 MM PITCH, ROHS COMPLIANT, SOIC-54

时钟 光电二极管 外围集成电路
文件： 总39页 (文件大小：636K)
中文：  中文翻译
下载：  下载PDF数据表文档文件
 查看货源
Document Number: MM908E624  
Rev. 11.0, 4/2012  
Freescale Semiconductor  
Technical Data  
Integrated Triple High Side  
Switch with Embedded MCU  
and LIN Serial Communication  
for Relay Drivers  
908E624  
HIGH SIDE SWITCH  
The 908E624 is an integrated single-package solution that  
includes a high performance HC08 microcontroller with a  
SMARTMOS analog control IC. The HC08 includes flash memory, a  
timer, enhanced serial communications interface (ESCI), an analog-  
to-digital converter (ADC), internal serial peripheral interface (SPI),  
and an internal clock generator module. The analog control die  
provides three high side outputs with diagnostic functions, voltage  
regulator, watchdog, current sense operational amplifier, and local  
interconnect network (LIN) physical layer.  
The single package solution, together with LIN, provides optimal  
application performance adjustments and space saving PCB design.  
It is well-suited for the control of automotive high current motors  
applications using relays (e.g., window lifts, fans, and sun roofs).  
EW (Pb-FREE) SUFFIX  
98ASA99294D  
54-pin SOICW  
Features  
• High performance M68HC908EY16 core  
• 16 KB of on-chip flash memory, 512 B of RAM  
• Internal clock generator module  
• Two 16-bit, two-channel timers  
• 10-bit ADC  
ORDERING INFORMATION  
Device  
Temperature  
Range (TA)  
(Add an R2 suffix for Tape  
and reel orders)  
Package  
• LIN physical layer interface  
• Low dropout voltage regulator  
• Three high side outputs  
• Two wake-up inputs  
MM908E624ACPEW  
MM908E624AYPEW  
-40°C to 85°C  
-40°C to 125°C  
54 SOICW  
• 16 microcontroller I/Os  
908E624  
VBAT  
LIN Interface  
5.0 V  
VSP1  
VSP  
LIN  
VREFH  
VDDA  
EVDD  
VCC  
HS3  
VDD  
L1  
L2  
VREFL  
VSSA  
EVSS  
AGND  
GND  
HS1  
RXD  
PTE1/RXD  
RST  
M
RST_A  
IRQ  
IRQ_A  
HS2  
+E  
PTD0/TACH0  
PW/MIN  
PTA0-4  
WDCONF  
PTB1;3-7  
PTC2-4  
Microcontroller  
Ports  
To Microcontroller A/D Channel  
PTD1/TACH1  
OUT  
-E  
Figure 1. 908E624 Simplified Application Diagram  
*This document contains certain information on a product under development.  
Freescale reserves the right to change or discontinue this product without notice.  
© Freescale Semiconductor, Inc., 2012. All rights reserved.  
 
INTERNAL BLOCK DIAGRAM  
INTERNAL BLOCK DIAGRAM  
AGND  
GND  
VSUP2  
VSUP1  
PWMIN  
RST_A  
IRQ_A  
WDCONF  
LIN  
RXD  
PTE1/RXD  
PTD0/TACH0  
RST  
IRQ  
C R T P O  
D D R C  
D T R P O  
D D R D  
E R T P O  
D D R  
E
s
B u  
a n r e I n t  
l
VREFL  
D D R A  
A T R P O  
D D R B  
B R T P O  
VSSA  
EVSS  
EVDD  
VDDA  
VREFH  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
2
 
PIN CONNECTIONS  
PIN CONNECTIONS  
1
PTB7/AD7/TBCH1  
PTB6/AD6/TBCH0  
PTC4/OSC1  
PTC3/OSC2  
PTC2/MCLK  
PTB5/AD5  
PTB4/AD4  
PTB3/AD3  
IRQ  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
PTA0/KBD0  
PTA1/KBD1  
PTA2/KBD2  
FLSVPP  
PTA3/KBD3  
PTA4/KBD4  
VREFH  
VDDA  
EVDD  
EVSS  
VSSA  
VREFL  
PTE1/RXD  
NC  
RXD  
WDCONF  
+E  
-E  
OUT  
VCC  
AGND  
VDD  
NC  
VSUP1  
GND  
LIN  
VSUP2  
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
RST  
PTB1/AD1  
PTD0/TACH0  
PTD1/TACH1  
NC  
NC  
NC  
PWMIN  
RST_A  
IRQ_A  
NC  
NC  
NC  
L1  
L2  
HS3  
HS2  
HS1  
Figure 3. Pin Connections  
Table 1. Pin Definitions  
A functional description of each pin can be found in the Functional Pin Description section beginning on page 16.  
Die  
Pin  
Pin Name  
Formal Name  
Definition  
These pins are special function, bidirectional I/O port pins, that are  
shared with other functional modules in the MCU.  
MCU  
1
2
6
PTB7/AD7/TBCH1  
PTB6/AD6/TBCH0  
PTB5/AD5  
Port B I/Os  
7
PTB4/AD4  
8
PTB3/AD3  
11  
PTB1/AD1  
These pins are special function, bidirectional I/O port pins, that are  
shared with other functional modules in the MCU.  
MCU  
3
4
5
PTC4/OSC1  
PTC3/OSC2  
PTC2/MCLK  
Port C I/Os  
This pin is an asynchronous external interrupt input pin.  
MCU  
MCU  
MCU  
—
9
IRQ  
External Interrupt  
Input  
This pin is bidirectional, allowing a reset of the entire system. It is driven  
low when any internal reset source is asserted.  
10  
RST  
External Reset  
These pins are special function, bidirectional I/O port pins, that are  
shared with other functional modules in the MCU.  
12  
13  
PTD0/TACH0  
PTD1/TACH1  
Port D I/Os  
Not connected.  
14, 15, 16,  
20, 21, 22,  
32, 41  
NC  
No Connect  
This pin is a special function, bidirectional I/O port pin, that can is shared  
with other functional modules in the MCU.  
MCU  
42  
PTE1/RXD  
Port E I/O  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
3
 
PIN CONNECTIONS  
Table 1. Pin Definitions (continued)  
A functional description of each pin can be found in the Functional Pin Description section beginning on page 16.  
Die  
Pin  
Pin Name  
Formal Name  
Definition  
These pins are the reference voltage pins for the analog-to-digital  
converter (ADC).  
MCU  
43  
48  
VREFL  
VREFH  
ADC References  
These pins are the power supply pins for the analog-to-digital converter.  
MCU  
MCU  
MCU  
44  
47  
VSSA  
VDDA  
ADC Supply Pins  
These pins are the ground and power supply pins, respectively. The  
MCU operates from a single power supply.  
45  
46  
EVSS  
EVDD  
MCU Power Supply  
Pins  
These pins are special function, bidirectional I/O port pins that are  
shared with other functional modules in the MCU.  
49  
50  
52  
53  
54  
PTA4/KBD4  
PTA3/KBD3  
PTA2/KBD2  
PTA1/KBD1  
PTA0/KBD0  
Port A I/Os  
For test purposes only. Do not connect in the application.  
MCU  
51  
17  
FLSVPP  
PWMIN  
Test Pin  
This pin allows the enabling and PWM control of the high side HS1 and  
HS2 pins.  
Analog  
Direct High Side  
Control Input  
This pin is the reset output pin of the analog die.  
Analog  
Analog  
18  
19  
RST_A  
IRQ_A  
Internal Reset Output  
This pin is the interrupt output pin of the analog die indicating errors or  
wake-up events.  
Internal Interrupt  
Output  
These pins are the wake-up inputs of the analog chip.  
Analog  
Analog  
23  
24  
L1  
L2  
Wake-Up Inputs  
These output pins are low R  
high side switches.  
25  
26  
27  
HS3  
HS2  
HS1  
High Side Output  
DS(ON)  
These pins are device power supply pins.  
Analog  
31  
28  
VSUP1  
VSUP2  
Power Supply Pins  
This pin represents the single-wire bus transmitter and receiver.  
These pins are device power ground connections.  
Analog  
Analog  
29  
LIN  
LIN Bus  
30  
34  
GND  
AGND  
Power Ground Pins  
The +5.0 V voltage regulator output pin is intended to supply the  
embedded microcontroller.  
Analog  
Analog  
33  
35  
36  
VDD  
VCC  
OUT  
Voltage Regulator  
Output  
This pin is the single +5.0 V power supply for the current sense  
operational amplifier.  
Amplifier Power  
Supply  
This pin is the output of the current sense operational amplifier.  
Analog  
Analog  
Amplifier Output  
Amplifier Inputs  
These pins are the current sense operational amplifier inverted and  
non-inverted inputs.  
37  
38  
-E  
+E  
This input pin is for configuration of the watchdog period and allows the  
disabling of the watchdog.  
Analog  
Analog  
39  
WDCONF  
Window  
Watchdog  
Configuration Pin  
This pin is the output of LIN transceiver.  
40  
RXD  
LIN Transceiver  
Output  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
4
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
Table 2. Maximum Ratings  
All voltages are with respect to ground unless otherwise noted. Exceeding limits on any pin may cause permanent damage to  
the device.  
Rating  
Symbol  
Value  
Unit  
ELECTRICAL RATINGS  
Supply Voltage  
V
Analog Chip Supply Voltage under Normal Operation (Steady-state)  
Analog Chip Supply Voltage under Transient Conditions  
MCU Chip Supply Voltage  
V
-0.3 to 27  
-0.3 to 40  
-0.3 to 5.5  
SUP(SS)  
V
SUP(PK)  
VDD  
Input Pin Voltage  
Analog Chip  
V
V
-0.3 to V +0.3  
DD  
IN(ANALOG)  
Microcontroller Chip  
V
V
-0.3 to V +0.3  
SS DD  
IN(MCU)  
Maximum Microcontroller Current per Pin  
All Pins except VDD, VSS, PTA0:PTA6, PTC0:PTC1  
PTA0:PTA6, PTC0:PTC1 Pins  
mA  
I
I
±15  
±25  
PIN(1)  
PIN(2)  
Maximum Microcontroller VSS Output Current  
Maximum Microcontroller VDD Input Current  
I
100  
100  
mA  
mA  
MVSS  
MVDD  
I
Current Sense Operational Amplifier  
Maximum Input Voltage, +E, -E Pins  
Maximum Input Current, +E, -E Pins  
Maximum Output Voltage, OUT Pin  
Maximum Output Current, OUT Pin  
V
-0.3 to 7.0  
±20  
V
mA  
V
+E-E  
I
+E-E  
V
-0.3 to V +0.3  
CC  
OUT  
I
±20  
mA  
OUT  
LIN Supply Voltage  
V
V
V
Normal Operation (Steady-state)  
V
-18 to 40  
BUS(SS)  
Transient Input Voltage (per ISO7637 Specification) and with  
External Components (Figure 4, page 13)  
V
-150 to 100  
BUS(PK)  
L1 and L2 Pin Voltage  
Normal Operation with a 33 kΩ resistor (Steady-state)  
V
-18 to 40  
WAKE(SS)  
WAKE(PK)  
Transient Input Voltage (per ISO7637 Specification) and with  
External Components (Figure 4, page 13)  
V
-100 to 100  
ESD Voltage  
Human Body Model (1)  
Machine Model (1)  
Charge Device Model (1)  
V
±2000  
±100  
ESD1  
V
V
ESD2  
ESD3  
±500  
Notes  
1. ESD1 testing is performed in accordance with the Human Body Model (CZAP =100 pF, RZAP = 1500 Ω), the Machine Model (CZAP  
=
200 pF, RZAP = 0 Ω), and the Charge Device Model, Robotic (C  
=4.0 pF).  
ZAP  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
5
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
Table 2. Maximum Ratings (continued)  
All voltages are with respect to ground unless otherwise noted. Exceeding limits on any pin may cause permanent damage to  
the device.  
Rating  
Symbol  
Value  
Unit  
THERMAL RATINGS  
Package Operating Ambient Temperature (4)  
T
°C  
A
MM908E624ACPEW  
MM908E624AYPEW  
-40 to 85  
-40 to 125  
Operating Junction Temperature (2)(4)  
T
°C  
J
-40 to 125  
-40 to 125  
MM908E624ACPEW  
MM908E624AYPEW  
Storage Temperature  
T
-40 to 150  
Note 5  
°C  
STG  
Peak Package Reflow Temperature During Reflow(3)(5)  
TPPRT  
°C  
Notes  
2. The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because  
of higher power dissipation of the analog die. The analog die junction temperature must not exceed 150°C under these conditions.  
3. Pin soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may  
cause malfunction or permanent damage to the device.  
4. Independent of TA, device parametrics are only guaranteed for -40 < TJ < 125 °C. Please see note 2. TJ is a factor of power dissipation,  
package thermal resistance, and available heat sinking.  
5. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow  
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes  
and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
6
 
 
 
 
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. Static Electrical Characteristics  
All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller  
chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values  
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
SUPPLY VOLTAGE RANGE  
Nominal Operating Voltage  
V
5.5  
—
—
—
18  
27  
V
V
SUP  
Functional Operating Voltage (6)  
SUPPLY CURRENT RANGE  
Normal Mode (7)  
V
SUPOP  
V
= 13.5 V, Analog Chip in Normal Mode, MCU Operating Using  
SUP  
Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI, ADC  
Enabled  
I
—
—
—
20  
60  
35  
—
75  
45  
mA  
μA  
μA  
RUN  
,
(8)  
Stop Mode (7)  
V
= 13.5 V, LIN in recessive state  
I
SUP  
STOP  
,
(8)  
Sleep Mode (7)  
V
= 13.5 V, LIN in recessive state  
I
SUP  
SLEEP  
DIGITAL INTERFACE RATINGS (ANALOG DIE)  
Output Pin RST_A  
Low-state Output Voltage (IOUT = -1.5 mA)  
High-state Output Current (VOUT > 3.5 V)  
Pull-down Current Limitation  
VOL  
IOH  
—
—
—
250  
—
0.4  
—
V
μA  
mA  
IOL_MAX  
-1.5  
-8.0  
Output Pin IRQ_A  
V
Low-state Output Voltage (IOUT = -1.5 mA)  
High-state Output Voltage (IOUT = 250 μA)  
VOL  
VOH  
—
—
—
0.4  
—
3.85  
Output Pin RXD  
Low-state Output Voltage (IOUT = -1.5 mA)  
High-state Output Voltage (IOUT = 250 μA)  
VOL  
VOH  
CIN  
—
3.85  
—
—
—
0.4  
—
V
V
Capacitance (9)  
4.0  
—
pF  
Input Pin PWMIN  
Input Logic Low Voltage  
Input Logic High Voltage  
Input Current  
VIL  
VIH  
IIN  
—
3.5  
-10  
—
—
—
1.5  
—
V
V
—
10  
—
μA  
pF  
Capacitance (9)  
Pin TXD, SS–Pull-up Current  
Notes  
CIN  
4.0  
I
—
40  
—
μA  
PU  
6. Device is fully functional. All functions are operating. Over-temperature may occur.  
7. Total current (I + I ) measured at GND pin.  
VSUP1  
VSUP2  
8. Stop and Sleep mode current will increase if VSUP exceeds 15 V.  
9. This parameter is guaranteed by process monitoring but is not production tested.  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
7
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. Static Electrical Characteristics (continued)  
All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller  
chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values  
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.  
Characteristic  
SYSTEM RESETS AND INTERRUPTS  
Symbol  
Min  
Typ  
Max  
Unit  
Low-voltage Reset (LVR)  
Threshold  
V
V
V
LVRON  
3.6  
4.0  
4.4  
Low-voltage Interrupt (LVI)  
Threshold  
V
5.7  
—
6.0  
1.0  
6.6  
—
LVI  
Hysteresis  
V
V
LVI_HYS  
High-voltage Interrupt (HVI)  
Threshold  
V
18  
—
19.25  
220  
20.5  
—
V
HVI  
Hysteresis  
mV  
HVI_HYS  
VOLTAGE REGULATOR (10)  
Normal Mode Output Voltage  
V
V
DDRUN  
2.0 mA < I  
< 50 mA, 5.5 V < V  
< 27 V  
SUP  
4.75  
50  
5.0  
5.25  
200  
DD  
Normal Mode Output Current Limitation (11)  
I
110  
mA  
V
DDRUN  
Dropout Voltage  
V
DDDROP  
V
SUP = 4.9 V, I  
= 50 mA  
—
0.1  
0.2  
DD  
Stop Mode Output Voltage (12)  
Stop Mode Regulator Current Limitation  
Line Regulation  
V
4.75  
4.0  
5.0  
8.0  
5.25  
14  
V
DDSTOP  
DDSTOP  
I
mA  
mV  
Normal Mode, 5.5 V < V  
< 27 V, I = 10 mA  
DD  
V
—
—
20  
10  
150  
100  
SUP  
LRRUN  
Stop Mode, 5.5 V < V  
< 27 V, I  
= 2.0 mA  
DD  
V
SUP  
LRSTOP  
Load Regulation  
Normal Mode, 1.0 mA < I < 50 mA, VSUP = 18 V  
mV  
V
—
—
40  
40  
150  
150  
DD  
LRRUN  
Stop Mode, 1.0 mA < I  
< 5.0 mA, VSUP = 18 V  
V
DD  
LDSTOP  
Over-temperature Prewarning (Junction) (13)  
Thermal Shutdown Temperature (Junction) (13)  
Temperature Threshold Difference  
T
120  
155  
135  
170  
160  
—
°C  
°C  
°C  
PRE  
T
SD  
ΔT  
T
SD- PRE  
T
-T  
20  
30  
45  
SD PRE  
Notes  
10. Specification with external capacitor 2.0 μF< C < 10 μF and 200 mΩ ≤ ESR ≤ 10 Ω. Capacitor value up to 47 μF can be used.  
11. Total VDD regulator current. A 5.0 mA current for current sense operational amplifier is included. Digital output supplied from VDD.  
12. When switching from Normal to Stop mode or from Stop mode to Normal mode, the output voltage can vary within the output voltage  
specification.  
13. This parameter is guaranteed by process monitoring but not production tested  
908E624  
Analog Integrated Circuit Device Data  
8
Freescale Semiconductor  
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. Static Electrical Characteristics (continued)  
All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller  
chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values  
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.  
Characteristic  
WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)  
External Resistor Range  
Symbol  
Min  
Typ  
Max  
Unit  
R
10  
—
—
100  
15  
kΩ  
EXT  
Watchdog Period Accuracy with External Resistor  
(Excluding Resistor Accuracy) (14)  
WD  
%
CACC  
-15  
LIN PHYSICAL LAYER  
LIN Transceiver Output Voltage  
V
Recessive State, TXD HIGH, I  
= 1.0 μA  
V
VSUP-1  
—
—
—
—
OUT  
LIN_REC  
Dominant State, TXD LOW, 500 Ω External Pull-up Resistor  
Normal Mode Pullup Resistor to VSUP  
Stop, Sleep Mode Pull-up Current Source  
Output Current Shutdown Threshold  
V
1.4  
LIN_DOM  
R
20  
—
50  
30  
2.0  
75  
60  
—
kΩ  
μA  
mA  
μA  
PU  
I
PU  
I
150  
OV-CUR  
Leakage Current to GND  
I
BUS  
VSUP Disconnected, V  
at 18 V  
—
0.0  
-1.0  
1.0  
3.0  
—
10  
20  
BUS  
Recessive State, 8.0 V ≤ V  
≤ 18 V, 8.0 V≤ V  
≤ 18 V, V  
≥ V  
BUS SUP  
SUP  
BUS  
1.0  
GND Disconnected, V  
= V  
, V  
at -18 V  
GND  
SUP BUS  
LIN Receiver  
V
SUP  
Receiver Threshold Dominant  
Receiver Threshold Recessive  
Receiver Threshold Center  
Receiver Threshold Hysteresis  
VBUS_DOM  
VBUS_REC  
VBUS_CNT  
VBUS_HYS  
—
0.6  
—
—
0.4  
—
0.475  
—
0.5  
—
0.525  
0.175  
HIGH SIDE OUTPUTS HS1 AND HS2  
Switch On Resistance  
R
Ω
DS(ON)  
TJ = 25 °C, ILOAD = 150 mA, V  
> 9.0 V  
—
—
—
2.0  
—
2.5  
4.5  
—
SUP  
TJ = 125 °C, ILOAD = 150 mA, V  
> 9.0 V  
SUP  
3.0  
TJ = 125 °C, ILOAD = 120 mA, 5.5 V < V  
> 9.0 V  
SUP  
Output Current Limit  
I
300  
155  
—
—
—
—
600  
190  
10  
mA  
°C  
μA  
V
LIM  
,
Over-temperature Shutdown (15)  
Leakage Current  
(16)  
THSSD  
I
LEAK  
Output Clamp Voltage  
V
CL  
I
= -100 mA  
-6.0  
—
—
OUT  
Notes  
14. Watchdog timing period calculation formula: PWD = 0.991 REXT+0.648 (REXT in kΩ and PWD in ms).  
*
15. This parameter is guaranteed by process monitoring but it is not production tested  
16. When over-temperature occurs, switch is turned off and latched off. Flag is set in SPI.  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
9
 
 
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. Static Electrical Characteristics (continued)  
All characteristics are for the analog chip only. Refer to the 68HC908EY16 data sheet for characteristics of the microcontroller  
chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted. Typical values  
noted reflect the approximate parameter mean at TA = 25°C under nominal conditions, unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
HIGH SIDE OUTPUT HS3  
Switch On Resistance  
R
Ω
DS(ON)  
TJ = 25 °C, ILOAD = 50 m A, V  
> 9.0 V  
> 9.0 V  
—
—
—
—
—
—
7.0  
10  
14  
SUP  
TJ = 125 °C, ILOAD = 50 mA, V  
SUP  
TJ = 125 °C, ILOAD = 30 mA, 5.5 V < V  
> 9.0 V  
SUP  
Output Current Limitation  
I
60  
155  
—
100  
—
200  
190  
10  
mA  
°C  
LIM  
,
Over-temperature Shutdown (17)  
Leakage Current  
(18)  
T
HSSD  
LEAK  
I
—
μA  
CURRENT SENSE OPERATIONAL AMPLIFIER  
Rail-to-Rail Input Voltage  
V
-0.1  
—
V
+0.1  
CC  
V
V
IMC  
Output Voltage Range  
Output Current ±1.0 mA  
Output Current ±5.0 mA  
V
V
0.1  
0.3  
—
—
V
V
-0.1  
-0.3  
OUT1  
OUT2  
CC  
CC  
Input Bias Current  
Input Offset Current  
Input Offset Voltage  
L1 AND L2 INPUTS  
Low Detection Threshold  
I
—
—
—
—
250  
nA  
nA  
B
I
-100  
-25  
100  
25  
O
V
mV  
IO  
V
V
V
THL  
THH  
HYS  
5.5 V < V  
6.0 V < V  
< 6.0 V  
< 18 V  
< 27 V  
2.0  
2.5  
2.7  
2.5  
3.0  
3.2  
3.0  
3.5  
3.7  
SUP  
SUP  
SUP  
18 V < V  
High Detection Threshold  
V
5.5 V < V  
< 6.0 V  
< 18 V  
< 27 V  
2.7  
3.0  
3.5  
3.3  
4.0  
4.2  
3.8  
4.5  
4.7  
SUP  
SUP  
SUP  
6.0 V < V  
18 V < V  
Hysteresis  
V
V
5.5 V < V  
< 27 V  
0.5  
-10  
—
—
1.3  
10  
SUP  
Input Current  
-0.2 V < V < 40 V  
I
μA  
IN  
IN  
Notes  
17. This parameter is guaranteed by process monitoring but it is not production tested  
18. When over-temperature occurs, switch is turned off and latched off. Flag is set in SPI.  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
10  
 
 
ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
Table 4. Dynamic Electrical Characteristics  
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 data sheet for characteristics of the  
microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted.  
Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
LIN PHYSICAL LAYER  
,
(20)  
Driver Characteristics for Normal Slew Rate (19)  
Dominant Propagation Delay TXD to LIN  
Dominant Propagation Delay TXD to LIN  
Recessive Propagation Delay TXD to LIN  
Recessive Propagation Delay TXD to LIN  
tDOM-MIN  
tDOM-MAX  
tREC-MIN  
tREC-MAX  
DT1  
—
—
—
—
—
—
—
—
50  
50  
50  
50  
—
11  
μs  
μs  
μs  
μs  
μs  
μs  
—
—
Propagation Delay Symmetry: t  
- t  
-10.44  
—
DOM-MIN REC-MAX  
Propagation Delay Symmetry: t  
- t  
DT2  
DOM-MAX REC-MIN  
,
(21)  
Driver Characteristics for Slow Slew Rate (19)  
Dominant Propagation Delay TXD to LIN  
Dominant Propagation Delay TXD to LIN  
Recessive Propagation Delay TXD to LIN  
Recessive Propagation Delay TXD to LIN  
tDOM-MIN  
tDOM-MAX  
tREC-MIN  
tREC-MAX  
DT1S  
—
—
—
—
—
—
—
—
100  
100  
100  
100  
—
μs  
μs  
μs  
μs  
μs  
μs  
—
—
Propagation Delay Symmetry: t  
Propagation Delay Symmetry: t  
- t  
-22  
—
DOM-MIN REC-MAX  
- t  
DT2S  
23  
DOM-MAX REC-MIN  
Driver Characteristics for Fast Slew Rate  
LIN High Slew Rate (Programming Mode)  
Receiver Characteristics and Wake-Up Timings  
Receiver Dominant Propagation Delay (22)  
Receiver Recessive Propagation Delay (22)  
Receiver Propagation Delay Symmetry  
Bus Wake-up Deglitcher  
SRFAST  
—
15  
—
V/μs  
tRL  
tRH  
—
—
3.5  
3.5  
—
6.0  
6.0  
2.0  
150  
—
μs  
μs  
μs  
μs  
μs  
tR-SYM  
tPROPWL  
tWAKE  
-2.0  
35  
—
Bus Wake-up Event Reported (23)  
—
20  
Notes  
19.  
V
from 7.0 V to 18 V, bus load R0 and C0 1.0 nF/1.0 kΩ, 6.8 nF/660 Ω, 10 nF/500 Ω. Measurement thresholds: 50% of TXD signal  
SUP  
to LIN signal threshold defined at each parameter.  
20. See Figure 6, page 14.  
21. See Figure 7, page 14.  
22. Measured between LIN signal threshold V or V and 50% of RXD signal.  
IL  
IH  
23.  
t
is typically 2 internal clock cycles after LIN rising edge detected. See Figure 8 and Figure 9, page 15. In Sleep mode the V  
DD  
WAKE  
rise time is strongly dependent upon the decoupling capacitor at VDD pin.  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
11  
ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
Table 4. Dynamic Electrical Characteristics (continued)  
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 data sheet for characteristics of the  
microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted.  
Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.  
Characteristic  
LIN PHYSICAL LAYER (CONTINUED)  
Symbol  
Min  
Typ  
Max  
Unit  
Output Current Shutdown Delay  
SPI INTERFACE TIMING  
t
—
10  
—
μs  
OV-DELAY  
SPI Operating Recommended Frequency  
L1 AND L2 INPUTS  
f
0.25  
8.0  
—
4.0  
38  
MHz  
μs  
SPIOP  
Wake-up Filter Time (24)  
t
t
20  
WUF  
PWD  
WINDOW WATCHDOG CONFIGURATION PIN (WDCONF)  
Watchdog Period  
ms  
External Resistor REXT = 10 kΩ (1%)  
External Resistor REXT = 100 kΩ (1%)  
Without External Resistor REXT (WDCONF Pin Open)  
—
—
97  
10.558  
99.748  
150  
—
—
205  
STATE MACHINE TIMING  
Reset Low Level Duration after VDD High (28)  
Interrupt Low Level Duration  
t
0.65  
7.0  
97  
1.0  
10  
1.35  
13  
ms  
μs  
ms  
μs  
μs  
μs  
RST  
t
INT  
NRTOUT  
Normal Request Mode Timeout (28)  
t
150  
3.0  
3.0  
35  
205  
10  
,
,
Delay Between SPI Command and HS1/HS2/HS3 Turn On (25)  
Delay Between SPI Command and HS1/HS2/HS3 Turn Off (25)  
(26)  
(26)  
tS-HSON  
tS-HSOFF  
tS-NR2N  
—
—
10  
Delay Between Normal Request and Normal Mode After W/D Trigger  
Command (27)  
6.0  
70  
Delay Between SS Wake-Up (SS LOW to HIGH) and Normal Request Mode  
(VDD On and Reset High)  
tW-SS  
μs  
μs  
15  
40  
80  
Delay Between SS Wake-Up (SS LOW to HIGH) and First Accepted SPI  
Command  
tW-SPI  
90  
30  
15  
—
—
—
N/A  
N/A  
—
Delay Between Interrupt Pulse and First SPI Command Accepted  
Minimum Time Between Two Rising Edges on SS  
Notes  
tS-1STSPI  
t2SS  
μs  
μs  
24. This parameter is guaranteed by process monitoring but is not production tested.  
25. Delay between turn-on or turn-off command and high side on or high side off, excluding rise or fall time due to external load.  
26. Delay between the end of the SPI command (rising edge of the SS) and start of device activation/deactivation.  
27. This parameter is guaranteed by process monitoring but it is not production tested.  
28. Also see Figure 10 on page 15  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
12  
 
ELECTRICAL CHARACTERISTICS  
MICROCONTROLLER PARAMETRICS  
Table 4. Dynamic Electrical Characteristics (continued)  
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 data sheet for characteristics of the  
microcontroller chip. Characteristics noted under conditions 9.0 V ≤ VSUP ≤ 16 V, -40 °C ≤ TJ ≤ 125 °C, unless otherwise noted.  
Typical values noted reflect the approximate parameter mean at TA = 25 °C under nominal conditions, unless otherwise noted.  
Characteristic  
CURRENT SENSE OPERATIONAL AMPLIFIER  
Supply Voltage Rejection Ratio (29)  
Common Mode Rejection Ratio (29)  
Gain Bandwidth (29)  
Symbol  
Min  
Typ  
Max  
Unit  
SVR  
CMR  
GBP  
SR  
60  
70  
1.0  
0.5  
40  
—
—
—
—
—
—
85  
—
—
—
—
—
—
dB  
dB  
MHz  
V/μs  
°
Slew Rate  
Phase Margin (for Gain = 1, Load 100 pF/ 5.0 kΩ (29)  
Open Loop Gain  
PHMO  
OLG  
dB  
Notes  
29. This parameter is guaranteed by process monitoring but it is not production tested.  
MICROCONTROLLER PARAMETRICS  
Table 5. Microcontroller  
For a detailed microcontroller description, refer to the MC68HC908EY16 data sheet.  
Module  
Description  
Core  
Timer  
Flash  
RAM  
ADC  
SPI  
High-Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz  
Two 16-Bit Timers with 2 Channels (TIM A and TIM B)  
16 K Bytes  
512 Bytes  
10-Bit Analog-to-Digital Converter  
SPI Module  
ESCI  
Standard Serial Communication Interface (SCI) Module  
Bit-Time Measurement  
Arbitration  
Prescaler with Fine Baud-Rate Adjustment  
ICG  
Internal Clock Generation Module  
TIMING DIAGRAMS  
Transient Pulse  
LIN, L1, and L2  
Generator  
10 kΩ  
1.0 nF  
Note Waveform in accordance with ISO7637 Part 1, Test Pulses 1, 2, 3a, and 3b.  
Figure 4. Test Circuit for Transient Test Pulses  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
13  
ELECTRICAL CHARACTERISTICS  
TIMING DIAGRAMS  
VSUP  
R0  
C0  
TXD  
RXD  
R0 and C0 Combinations:  
LIN  
‚Ä¢ 1.0 kΩ and 1.0  
‚Ä¢ 600 Ω and 6.8  
‚Ä¢ 500 Ω and 10  
Figure 5. Test Circuit for LIN Timing Measurements  
TXD  
LIN  
tREC-MAX  
tDOM-MIN  
58.1% VSUP  
40% VSUP  
74.4% VSUP  
VLIN_REC  
60% VSUP  
28.4% VSUP  
42.2% VSUP  
tDOM-MAX  
tREC-MIN  
RXD  
tRL  
tRH  
Figure 6. LIN Timing Measurements for Normal Slew Rate  
TXD  
tREC-MAX  
LIN  
tDOM-MIN  
VLIN_REC  
61.6% VSUP  
40% Vsup  
77.8% VSUP  
60% VSUP  
25.1% VSUP  
38.9% VSUP  
tDOM-MAX  
tREC-MIN  
RXD  
tRL  
tRH  
Figure 7. LIN Timing Measurements for Slow Slew Rate  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
14  
ELECTRICAL CHARACTERISTICS  
TIMING DIAGRAMS  
LIN  
VLIN_REC  
0.4 VSUP  
l  
Dominant Level  
VDD  
t
t
WAKE  
PROPWL  
L  
Figure 8. Wake-up Sleep Mode Timing  
LIN  
VLIN_REC  
P  
0.4 VSUP  
Dominant Level  
IRQ_A  
t
t
WAKE  
PROPWL  
Figure 9. Wake-up Stop Mode Timing  
VSUP  
VDD  
RST_A  
tRST  
tNRTOUT  
Figure 10. Power On Reset and Normal Request Timeout Timing  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
15  
 
 
 
FUNCTIONAL DESCRIPTION  
INTRODUCTION  
FUNCTIONAL DESCRIPTION  
INTRODUCTION  
The 908E624 was designed and developed as a highly  
integrated and cost-effective solution for automotive and  
industrial applications. For automotive body electronics, the  
908E624 is well suited to perform relay control in applications  
like window lift, sunroof, etc., via a three-wire LIN bus.  
high side outputs. Other ports are also provided, which  
include a current sense operational amplifier port and two  
wake-up pins. An internal voltage regulator provides power to  
the MCU chip.  
Also included in this device is a LIN physical layer, which  
communicates using a single wire. This enables this device  
to be compatible with three-wire bus systems, where one wire  
is used for communication, one for battery, and one for  
ground.  
The device combines an HC908EY16 MCU core with flash  
memory together with a SmartMOS IC chip. The SmartMOS  
IC chip combines power and control in one chip. Power  
switches are provided on the SmartMOS IC configured as  
FUNCTIONAL PIN DESCRIPTION  
See Figure 1, 908E624 Simplified Application Diagram,  
page 1, for a graphic representation of the various pins  
referred to in the following paragraphs. Also, see the pin  
diagram on page 3 for a depiction of the pin locations on the  
package.  
For details, refer to the 68HC908EY16 data sheet.  
PORT E I/O PIN (PTE1)  
PTE1/RXD and PTE0/TXD are special function,  
bidirectional I/O port pins that can also be programmed to be  
enhanced serial communication.  
PORT A I/O PINS (PTA0:4)  
PTE0/TXD is internally connected to the TXD pin of the  
analog die. The connection for the receiver must be done  
externally.  
These pins are special function, bidirectional I/O port pins  
that are shared with other functional modules in the MCU.  
PTA0:PTA4 are shared with the keyboard interrupt pins  
KBD0:KBD4.  
For details, refer to the 68HC908EY16 data sheet.  
The PTA5/SPSCK pin is not accessible in this device and  
is internally connected to the SPI clock pin of the analog die.  
The PTA6/SS pin is likewise not accessible.  
EXTERNAL INTERRUPT PIN (IRQ)  
The IRQ pin is an asynchronous external interrupt pin. This  
pin contains an internal pull-up resistor that is always  
activated, even when the IRQ pin is pulled LOW.  
For details, refer to the 68HC908EY16 data sheet.  
For details, refer to the 68HC908EY16 data sheet.  
PORT B I/O PINS (PTB1:7)  
These pins are special function, bidirectional I/O port pins  
that are shared with other functional modules in the MCU. All  
pins are shared with the ADC module. The PTB6:PTB7 pins  
are also shared with the Timer B module.  
EXTERNAL RESET PIN (RST)  
A logic [0] on the RST pin forces the MCU to a known  
startup state. It is driven LOW when any internal reset source  
is asserted.  
The PTB0/AD0 and PTB2/AD2 pins are not accessible in  
this device.  
This pin contains an internal pull-up resistor that is always  
activated, even when the reset pin is pulled LOW.  
For details, refer to the 68HC908EY16 data sheet.  
Important To ensure proper operation, do not add any  
external pull-up resistor.  
PORT C I/O PINS (PTC2:4)  
For details, refer to the 68HC908EY16 data sheet.  
These pins are special function, bidirectional I/O port pins  
that are shared with other functional modules in the MCU. For  
example, PTC2:PTC4 are shared with the ICG module.  
MCU POWER SUPPLY PINS (EVDD AND EVSS)  
PTC0/MISO and PTC1/MOSI are not accessible in this  
device and are internally connected to the MISO and MOSI  
SPI pins of the analog die.  
EVDD and EVSS are the power supply and ground pins,  
respectively. The MCU operates from a single power supply.  
Fast signal transitions on MCU pins place high, short  
duration current demands on the power supply. To prevent  
noise problems, take special care to provide power supply  
bypassing at the MCU.  
For details, refer to the 68HC908EY16 data sheet.  
PORT D I/O PINS (PTD:0:1)  
For details, refer to the 68HC908EY16 data sheet.  
PTD1/TACH1 and PTD0/TACH0/BEMF are special  
function, bidirectional I/O port pins that can also be  
programmed to be timer pins.  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
16  
FUNCTIONAL DESCRIPTION  
FUNCTIONAL PIN DESCRIPTION  
the watchdog period. If the pin is open, the watchdog period  
is fixed to its default value.  
ADC SUPPLY PINS (VDDA AND VSSA)  
VDDA and VSSA are the power supply pins for the analog-  
to-digital converter (ADC). It is recommended that a high-  
quality ceramic decoupling capacitor be placed between  
these pins.  
The watchdog can be disabled (e.g., for flash  
programming or software debugging) by connecting this pin  
to GND.  
Important VDDA is the supply for the ADC and should be  
tied to the same potential as EVDD via separate traces.  
VSSA is the ground pin for the ADC and should be tied to the  
same potential as EVSS via separate traces.  
POWER SUPPLY PINS (VSUP1AND VSUP2)  
This VSUP1 power supply pin supplies the voltage  
regulator, the internal logic, and LIN transceiver.  
For details, refer to the 68HC908EY16 data sheet.  
This VSUP2 power supply pin is the positive supply for the  
high side switches.  
ADC REFERENCE PINS (VREFL AND VREFH)  
POWER GROUND PIN (GND)  
VREFL and VREFH are the reference voltage pins for the  
ADC. It is recommended that a high quality ceramic  
decoupling capacitor be placed between these pins.  
This pin is the device ground connection.  
Important VREFH is the high reference supply for the  
ADC and should be tied to the same potential as VDDA via  
separate traces. VREFL is the low reference supply for the  
ADC and should be tied to the same potential as VSSA via  
separate traces.  
HIGH SIDE OUTPUT PINS (HS1 AND HS2)  
These pins are high side switch outputs to drive loads such  
as relays or lamps. Each switch is protected with over-  
temperature and current limit (over-current). The output has  
an internal clamp circuitry for inductive load. The HS1 and  
HS2 outputs are controlled by the SPI and have a direct  
enabled input (PWMIN) for PWM capability.  
For details, refer to the 68HC908EY16 data sheet.  
TEST PIN (FLSVPP)  
HIGH SIDE OUTPUT PIN (HS3)  
This pin is for test purposes only. Do not connect in the  
application or connect to GND.  
This high side switch can be used to drive small lamps,  
Hall-effect sensors, or switch pull-up resistors. The switch is  
protected with over-temperature and current limit (over-  
current). The output is controlled only by the SPI.  
PWMIN PIN (PWMIN)  
This pin is the direct PWM input for high side outputs 1 and  
2 (HS1 and HS2). If no PWM control is required, PWMIN  
must be connected to VDD to enable the HS1 and HS2  
outputs.  
LIN BUS PIN (LIN)  
The LIN pin represents the single-wire bus transmitter and  
receiver. It is suited for automotive bus systems and is based  
on the LIN bus specification.  
LIN TRANSCEIVER OUTPUT PIN (RXD)  
This pin is the output of LIN transceiver. The pin must be  
connected to the microcontroller’s Enhanced Serial  
Communications Interface (ESCI) module (RXD pin).  
WAKE-UP PINS (L1 AND L2)  
These pins are high-voltage capable inputs used to sense  
external switches and to wake-up the device from Sleep or  
Stop mode. During Normal mode the state of these pins can  
be read through the SPI.  
RESET PIN (RST_A)  
RST_A is the reset output pin of the analog die and must  
be connected to the RST pin of the MCU.  
Important If unused, these pins should be connected to  
VSUP or GND to avoid parasitic transitions. In Low Power  
Mode, this could lead to random wake-up events.  
Important To ensure proper operation, do not add any  
external pull-up resistor.  
CURRENT SENSE OPERATIONAL AMPLIFIER  
PINS (E+, E-, OUT, VCC)  
INTERRUPT PIN (IRQ_A)  
IRQ_A is the interrupt output pin of the analog die  
indicating errors or wake-up events. This pin must be  
connected to the IRQ pin of the MCU.  
These are the pins of the single supply current sense  
operational amplifier.  
• The E+ and E- input pins are the non-inverting and  
inverting inputs of the current sense operational  
amplifier, respectively.  
• The OUT pin is the output pin of the current sense  
operational amplifier.  
WINDOW WATCHDOG CONFIGURATION PIN  
(WDCONF)  
This pin is the configuration pin for the internal watchdog.  
A resistor is connected to this pin. The resistor value defines  
• The VCC pin is the +5.0 V single supply connection.  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
17  
FUNCTIONAL DESCRIPTION  
FUNCTIONAL PIN DESCRIPTION  
Note If the operational amplifier is not used, it is possible  
to connect all pins (E+, E-, OUT and VCC) to GND. In this  
case, all of the four pins must be grounded.  
VOLTAGE REGULATOR AND CURRENT SENSE  
AMPLIFIER GROUND PIN (AGND)  
The AGND pin is the ground pin of the voltage regulator  
and the current sense operational amplifier.  
+5.0 V VOLTAGE REGULATOR OUTPUT PIN (VDD)  
Important GND, AGND, VSS, EVSS, VSSA, and VREFL  
The VDD pin is needed to place an external capacitor to  
stabilize the regulated output voltage. The VDD pin is  
intended to supply the embedded microcontroller. The pin is  
protected against shorts to GND with an integrated current  
limit (temperature shutdown could occur).  
pins must be connected together.  
NO CONNECT PINS (NC)  
The NC pins are not connected internally.  
Note Each of the NC pins can be left open or connected  
to ground (recommended).  
Important The VDD, EVDD, VDDA, and VREFH pins  
must be connected together.  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
18  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
Wake-up from Stop mode is initiated by a wake-up  
interrupt. Wake-up from Sleep mode is done by a reset and  
the voltage regulator is turned back on.  
908E624 ANALOG DIE MODES OF OPERATION  
The 908E624 offers three operating modes: Normal (Run),  
Stop, and Sleep. In Normal mode the device is active and is  
operating under normal application conditions. The Stop and  
Sleep modes are low-power modes with wake-up  
capabilities.  
The selection of the different modes is controlled by the  
MODE1:2 bits in the SPI Control register.  
Figure 11 describes how transitions are done between the  
different operating modes and Table 6, page 20, gives an  
overview of the operating mode.  
In Stop mode, the voltage regulator still supplies the MCU  
with V (limited current capability), and in Sleep mode the  
DD  
voltage regulator is turned off (V = 0 V).  
DD  
Normal Request Timeout Expired (tNRTOUT  
)
V
Low  
DD  
VDD High and  
Power Up  
Reset Delay (t  
) Expired  
RST  
Power  
Normal  
Reset  
Down  
Request  
VDD Low  
Normal  
WD Failed  
VDDLOW(>tN  
T) Expired  
R  
T
O
U
andLVF = 0  
Sleep Command  
Wake-up(Reset)  
Sleep  
Stop  
VLow  
DD  
Legend  
WD: Watchdog  
WD Disabled: Watchdog disabled (WDCONF pin connected to GND)  
WD Trigger: Watchdog is triggered by SPI command  
WD Failed: No watchdog trigger or trigger occurs in closed window  
Stop Command: Stop command sent via SPI  
Sleep Command: Sleep command sent via SPI  
Wake-up: L1 or L2 state change or LIN bus wake-up or SS rising edge  
Figure 11. Operating Modes and Transitions  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
19  
 
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
Table 6. Operating Modes Overview  
Device  
Mode  
Wake-up  
Capabilities  
Watchdog  
Function  
HS1, HS2,  
and HS3  
Sense  
Amplifier  
RST_A  
Output  
Voltage Regulator  
DD ON  
LIN Interface  
Reset  
V
N/A  
LOW  
HIGH  
Disabled  
Disabled  
Enabled  
Recessive only  
Not active  
Not active  
Normal  
Request  
VDD ON  
N/A  
150 ms time out if  
WD enabled  
Transmit and  
receive  
Normal  
(Run)  
VDD ON  
N/A  
HIGH  
HIGH  
Window WD if  
enabled  
Enabled  
Disabled  
Transmit and  
receive  
Active  
Stop  
VDD ON with limited  
current capability  
LIN wake-up,  
L1, L2 state change,  
SS rising edge  
Disabled  
Recessive state with Not active  
wake-up capability  
Sleep  
V
DD OFF  
LIN wake-up  
L1, L2 state change  
LOW  
Disabled  
Disabled  
Recessive state with Not active  
wake-up capability  
INTERRUPTS  
Wake-up Interrupts  
In Normal (Run) mode the 908E624 has four different  
interrupt sources. An interrupt pulse on the IRQ_A pin is  
generated to report a fault to the MCU. All interrupts are not  
maskable and cannot be disabled.  
In Stop mode the IRQ_A pin reports wake-up events on the  
L1, L2, or the LIN bus to the MCU. All wake-up interrupts are  
not maskable and cannot be disabled.  
After a wake-up interrupt, the INTSRC bit in the Serial  
Peripheral Interface (SPI) Status register is set, indicating the  
source of the event. This wake-up source information is only  
transferred once, and the INTSRC bit is cleared  
automatically.  
After an Interrupt the INTSRC bit in the SPI Status register  
is set, indicating the source of the event. This interrupt source  
information is only transferred once, and the INTSRC bit is  
cleared automatically.  
Figure 12, page 21, describes the Stop/Wake-up  
procedure.  
Low-Voltage Interrupt  
Low-voltage interrupt (LVI) is related to external supply  
voltage VSUP1. If this voltage falls below the LVI threshold,  
it will set the LVF bit in the SPI Status register and an interrupt  
will be initiated. The LVF bit remains set as long as the Low-  
voltage condition is present.  
Voltage Regulator Temperature Prewarning (VDDT)  
Voltage regulator temperature prewarning (VDDT) is  
generated if the voltage regulator temperature is above the  
T
threshold. It will set the VDDT bit in the SPI Status  
PRE  
During Sleep and Stop mode the low-voltage interrupt  
circuitry is disabled.  
register and an interrupt will be initiated. The VDDT bit  
remains set as long as the error condition is present.  
During Sleep and Stop mode the voltage regulator  
temperature prewarning circuitry is disabled.  
High-voltage Interrupt  
High-voltage interrupt (HVI) is related to external supply  
voltage VSUP1. If this voltage rises above the HVI threshold,  
it will set the HVF bit in the SPI Status register and an  
interrupt will be initiated. The HVF bit remains set as long as  
the high-voltage condition is present.  
High Side Switch Thermal Shutdown (HSST)  
The high side switch thermal shutdown HSST is generated  
if one of the high side switches HS1:HS3 is above the HSST  
threshold, it will shutdown all high side switches, set the  
HSST flag in the SPI Status register and an interrupt will be  
initiated. The HSST bit remains set as long as the error  
condition is present.  
During Sleep and Stop mode the high-voltage interrupt  
circuitry is disabled.  
During Sleep and Stop mode the high side switch thermal  
shutdown circuitry is disabled.  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
20  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
MCU  
Power Die  
From Reset  
initialize  
operate  
SPI:  
2x STOP  
Command  
Switch to VREG  
low current mode  
STOP  
Wake-up on  
LIN or L1, L2?  
IRQ  
interrupt  
?
Assert IRQ  
SPI: reason for  
interrupt  
Switch to VREG  
high current mode  
operate  
Figure 12. Stop Mode/Wake-up Procedure  
If no PWM control is required, PWMIN must be connected  
to the VDD pin.  
ANALOG DIE INPUTS/OUTPUTS  
High Side Output Pins HS1 and HS2  
Current Limit (Over-current) Protection  
These are two high side switches used to drive loads such  
as relays or lamps. They are protected with over-temperature  
and current limit (over-current) and include an active internal  
clamp circuitry for inductive load drive. Control is done using  
the SPI Control register. PWM capability is offered through  
the PWMIN input pin.  
These high side switches feature current limit to protect  
them against over-current and short circuit conditions.  
Over-temperature Protection  
If an over-temperature condition occurs on any of the three  
high side switches, all high side switches (HS1, HS2, and  
HS3) are turned off and latched off. The failure is reported by  
the HSST bit in the SPI Control register.  
The high side switch is turned on if both the HSxON bit in  
the SPI Control register is set and the PWMIN input is HIGH  
(refer to Figure 13, page 22). In order to have HS1 on, the  
PWMIN must be HIGH and bit HS1ON must be set. The  
same applies to the HS2 output.  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
21  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
Sleep and Stop Mode  
Current Limit (Over-current) Protection  
In Sleep and Stop modes the high sides are disabled.  
This high side feature switch feature current limit to protect  
it against over-current and short-circuit conditions.  
High Side Output HS3  
Over-temperature Protection  
This high side switch can be used to drive small lamps,  
Hall-effect sensors, or switch pull-up resistors. Control is  
done using the SPI Control register. No direct PWM control is  
possible on this pin (refer to Figure 14, page 22).  
If an over-temperature condition occurs on any of the three  
high side switches, all high side switches (HS1, HS2, and  
HS3) are turned off and latched off. The failure is reported by  
the HSST bit in the SPI Control register.  
Sleep and Stop Mode  
In Sleep and Stop mode the high side is disabled.  
.
PWMIN  
VSUP2  
MODE1:2  
On/Off  
High Side Driver  
Charge Pump,  
HSxON  
HSx  
Control  
Status  
Current Limit Protection,  
Over-temperature Protection  
Figure 13. High Side HS1 and HS2 Circuitry  
.
MODE1:2  
VSUP2  
On/Off  
High Side Driver  
Charge Pump,  
HS3ON  
Control  
Status  
Current Limit Protection,  
Over-temperature Protection  
HS3  
Figure 14. High Side HS3 Circuitry  
node. The fall time from dominant to recessive and the rise  
time from recessive to dominant is controlled. The symmetry  
between both slew rate controls is guaranteed.  
LIN PHYSICAL LAYER  
The LIN bus pin provides a physical layer for single-wire  
communication in automotive applications. The LIN physical  
layer is designed to meet the LIN physical layer specification.  
The slew rate can be selected for optimized operation at  
10 and 20 kBit/s as well as a fast baud rate for test and  
programming. The slew rate can be adapted with the bits  
LINSL2:1 in the SPI Control Register. The initial slew rate is  
optimized for 20 kBit/s.  
The LIN driver is a low side MOSFET with over-current  
protection and thermal shutdown. An internal pull-up resistor  
with a serial diode structure is integrated, so no external  
pullup components are required for the application in a slave  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
22  
 
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
The LIN pin offers high susceptibility immunity level from  
external disturbance, guaranteeing communication during  
external disturbance.  
the transmitter and set the LINFAIL flag in the SPI Status  
Register.  
For improved performance and safe behavior in case of  
LIN bus short to Ground or LIN bus leakage during low power  
mode the internal pull-up resistor on the LIN pin can be  
disconnected, with the LIN-PU bit in the SPI Control Register,  
and a small current source keeps the LIN bus at recessive  
level. In case of a LIN bus short to GND, this feature will  
reduce the current consumption in STOP and SLEEP modes.  
The LIN transmitter circuitry is enabled in Normal and  
Normal Request mode.  
An over-current condition (e.g. LIN bus short to V  
) or a  
BAT  
over-temperature in the output low side FET will shutdown  
MODE2:1  
LINSL2:1  
Control  
LIN-PU  
VSUP1  
LINWU  
2µA  
LINFAIL  
30k  
LIN bus  
TXD  
Slope  
Control  
Wake-up  
Filter  
GND  
RXD  
Figure 15. LIN Interface  
TXD Pin  
STOP Mode and Wake-up Feature  
The TXD pin is the MCU interface to control the state of the  
LIN transmitter (see Figure 2, page 2). When TXD is LOW,  
the LIN pin is low (dominant state). When TXD is HIGH, the  
LIN output MOSFET is turned off (recessive state). The TXD  
pin has an internal pull-up current source in order to set the  
LIN bus to recessive state in the event, for instance, the  
microcontroller could not control it during system power-up or  
power-down.  
During STOP mode operation the transmitter of the  
physical layer is disabled. In case the bit LIN-PU was set in  
the Stop mode sequence the internal pull-up resistor is  
disconnected from VSUP and a small current source keeps  
the LIN pin in recessive state. The receiver is still active and  
able to detect wake-up events on the LIN bus line.  
A dominant level longer than t  
followed by an rising  
PROPWL  
edge will generate a wake-up interrupt and set the LINWF  
flag in the SPI Status Register. Also see Figure 9, page 15.  
RXD Pin  
SLEEP Mode and Wake-up Feature  
The RXD transceiver pin is the MCU interface, which  
reports the state of the LIN bus voltage. LIN HIGH (recessive  
state) is reported by a high level on RXD, LIN LOW (dominant  
state) by a low level on RXD.  
During SLEEP mode operation the transmitter of the  
physical layer is disabled. In case the bit LIN-PU was set in  
the Sleep mode sequence the internal pull-up resistor is  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
23  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
disconnected from VSUP and a small current source keeps  
the LIN pin in recessive state. The receiver is still active to be  
able to detect wake-up events on the LIN bus line.  
Current Limit (Over-current) Protection  
The voltage regulator has current limit to protect the device  
against over-current and short-circuit conditions.  
A dominant level longer than t  
followed by an rising  
PROPWL  
edge will generate a system wake-up (reset) and set the  
LINWF flag in the SPI Status Register. Also see Figure 8,  
page 15).  
Over-temperature Protection  
The voltage regulator also features an over-temperature  
protection having an over-temperature warning (Interrupt -  
VDDT) and an over-temperature shutdown.  
WINDOW WATCHDOG  
Stop Mode  
The window watchdog is configurable using an external  
resistor at the WDCONF pin. The watchdog is cleared  
through by the MODE1:2 bits in the SPI Control register (refer  
to Table 8, page 26).  
During Stop mode, the Stop mode regulator supplies a  
regulated output voltage. The Stop mode regulator has a  
limited output current capability.  
A watchdog clear is only allowed in the open window. If the  
watchdog is cleared in the closed window or has not been  
cleared at the end of the open window, the watchdog will  
generate a reset on the RST_A pin and reset the whole  
device.  
Sleep Mode  
In Sleep mode the voltage regulator external V is turned  
off.  
DD  
Note The watchdog clear in Normal request mode  
(150 ms) (first watchdog clear) has no window.  
FACTORY TRIMMING AND CALIBRATION  
To enhance the ease of use of the 908E624, various  
parameters (e.g., ICG trim value) are stored in the flash  
memory of the device. The following flash memory locations  
are reserved for this purpose and might have a value different  
from the “empty” (0xFF) state:  
Window closed  
Window open  
no watchdog clear allowed  
for watchdog clear  
• 0xFD80:0xFDDF Trim and Calibration Values  
• 0xFFFE:0xFFFF Reset Vector  
In the event the application uses these parameters, one  
has to take care not to erase or override these values. If these  
parameters are not used, these flash locations can be erased  
and otherwise used.  
WD timing x 50%  
WD timing x 50%  
(t  
WD period
WD timing selected by resistor on WDCONF terminal.  
)
PWD  
Trim Values  
The usage of the trim values, located in the flash memory,  
is explained in the following.  
Figure 16. Window Watchdog Operation  
Internal Clock Generator (ICG) Trim Value  
Watchdog Configuration  
The internal clock generator (ICG) module is used to  
create a stable clock source for the microcontroller without  
using any external components. The untrimmed frequency of  
the low frequency base clock (IBASE), will vary as much as  
±25%, due to process, temperature, and voltage  
dependencies. To compensate for these dependencies, an  
ICG trim value is located at the address $FDC2. After  
trimming the ICG, a range of typ. ±2% (±3% max.) at nominal  
If the WDCONF pin is left open, the default watchdog  
period is selected (typ. 150 ms). If no watchdog function is  
required, the WDCONF pin must be connected to GND.  
The watchdog period is calculated using the following  
formula:  
t
[ms] = 0.991  
R
[kΩ] + 0.648  
PWD  
EXT  
*
conditions (filtered (100 nF) and stabilized (4.7 μF) V  
=
DD  
VOLTAGE REGULATOR  
5.0 V, T  
~23 °C) and will vary over-temperature and  
Ambient  
The 908E624 chip contains a low-power, low dropout  
voltage regulator to provide internal power and external  
power for the MCU. The on-chip regulator consist of two  
elements, the main voltage regulator and the low-voltage  
reset circuit.  
voltage (V ) as indicated in the 68HC908EY16 data sheet.  
DD  
To trim the ICG, these values must be copied to the ICG  
Trim Register ICGTR at address $38 of the MCU.  
Important The value has to be copied after every reset.  
The V regulator accepts an unregulated input supply  
DD  
OPERATING MODES OF THE MCU  
and provides a regulated VDD supply to all digital sections of  
the device. The output of the regulator is also connected to  
the VDD pin to provide the 5.0 V to the microcontroller.  
For a detailed description of the operating modes of the  
MCU, refer to the MC68HC908EY16 data sheet.  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
24  
FUNCTIONAL DEVICE OPERATION  
LOGIC COMMANDS AND REGISTERS  
LOGIC COMMANDS AND REGISTERS  
• MOSI—Master-Out Slave-In  
908E624 SPI INTERFACE AND CONFIGURATION  
• MISO—Master-In Slave-Out  
• SPSCK—Serial Clock  
The serial peripheral interface creates the communication  
link between the microcontroller and the analog die of the  
908E624.  
A complete data transfer via the SPI consists of 1 byte.  
The master sends 8 bits of control information and the slave  
replies with 8 bits of status data.  
The interface consists of four pins (see Figure 17):  
•
SS—Slave Select  
SS  
Register write data  
D4 D3  
D7  
D6  
D5  
D2  
D1  
D0  
MOSI  
MISO  
Register read data  
D4 D3  
D7  
D6  
D5  
D2  
D1  
D0  
SPSCK  
Read data latch  
Write data latch  
Rising edge of SPSCK  
Falling edge of SPSCK  
Change MISO/MOSI Output  
Sample MISO/MOSI Input  
Figure 17. SPI Protocol  
During the inactive phase of the SS (HIGH), the new data  
transfer is prepared.  
The data transfer is only valid if exactly 8 sample clock  
edges are present in the active (low) phase of SS.  
The falling edge of the SS indicates the start of a new data  
transfer and puts the MISO in the low-impedance state and  
latches the analog status data (Register read data).  
The rising edge of the slave select SS indicates the end of  
the transfer and latches the write data (MOSI) into the  
register The SS high forces MISO to the high-impedance  
state.  
With the rising edge of the SPI clock, SPSCK the data is  
moved to MISO/MOSI pins. With the falling edge of the SPI  
clock SPSCK the data is sampled by the Receiver.  
SPI REGISTER OVERVIEW  
Table 7 summarizes the SPI Register bit meaning, reset  
value, and bit reset condition.  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
25  
 
FUNCTIONAL DEVICE OPERATION  
LOGIC COMMANDS AND REGISTERS  
.
Table 7. SPI Register Overview  
Bit  
Read/Write  
Information  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
MODE2  
L2  
D0  
MODE1  
L1  
Write  
LINSL2  
LINSL1  
LIN-PU  
HVF  
HS3ON  
HS2ON  
VDDT  
HS1ON  
HSST  
(30)  
INTSRC  
LINWU  
or  
LINFAIL  
LVF  
or  
BATFAIL  
Read  
(31)  
Write Reset Value  
0
0
0
0
0
0
—
—
—
—
Write Reset Condition  
POR,  
POR,  
POR  
POR, RESET  
POR,  
POR,  
RESET  
RESET  
RESET  
RESET  
Notes  
30. D7 signals interrupts and wake-up interrupts, D6:D0 indicated the source.  
31. The first SPI read after reset returns the BATFAIL flag state on bit D4.  
SPI Control Register (Write)  
reduce the power consumption, e.g. in combination with  
STOP/SLEEP mode.  
Table 8 shows the SPI Control register bits by name.  
HS3ON:HS1ON—High Side H3:HS1 Enable Bits  
Table 8. Control Bits Function (Write Operation)  
These bits enable the HSx. Reset clears the HSxON bit.  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
• 1 = HSx switched on (refer to Note below).  
• 0 = HSx switched off.  
LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1  
Note If no PWM on HS1 and HS2 is required, the PWMIN  
pin must be connected to the VDD pin.  
LINSL2:1—LIN Baud Rate and Low-power Mode  
Selection Bits  
These bits select the LIN slew rate and requested low-  
power mode in accordance with Table 9. Reset clears the  
LINSL2:1 bits.  
MODE2:1—Mode Section Bits  
The MODE2:1 bits control the operating modes and the  
watchdog in accordance with Table 10.  
Table 9. LIN Baud Rate and Low-power Mode Selection  
Bits  
Table 10. Mode Selection Bits  
MODE2  
MODE1  
Description  
LINSL2  
LINSL1  
Description  
(32)  
0
0
1
1
0
1
0
1
Sleep Mode  
Stop Mode  
(32)  
(33)  
0
0
1
0
1
0
Baud Rate up to 20 kbps (normal)  
Baud Rate up to 10 kbps (slow)  
Watchdog Clear  
Run (Normal) Mode  
Fast Program Download  
Baud Rate up to 100 kbps  
Notes  
32. To enter Sleep and Stop mode, a special sequence of SPI  
commands is implemented.  
1
1
Low-power Mode (Sleep or Stop) Request  
33. The device stays in Run (Normal) mode.  
LIN-PU—LIN Pull-up Enable Bit  
To safely enter Sleep or Stop mode and to ensure that  
these modes are not affected by noise issue during SPI  
transmission, the Sleep/Stop commands require two SPI  
transmissions.  
This bit controls the LIN pull-up resistor during Sleep and  
Stop modes.  
• 1 = Pull-up disconnected in Sleep and Stop modes.  
• 0 = Pull-up connected in Sleep and Stop modes.  
Sleep Mode Sequence  
If the Pull-up is disconnected, a small current source is  
used to pull the LIN pin in recessive state. In case of an  
erroneous short of the LIN bus to ground, this will significantly  
The Sleep command, as shown in Table 11, must be sent  
twice.  
Table 11. Sleep Command Bits  
LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1  
0/1  
1
1
0
0
0
0
0
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
26  
 
 
 
 
FUNCTIONAL DEVICE OPERATION  
Stop Mode Sequence  
The Stop command, as shown in Table 12, must be sent  
twice.  
Table 12. Stop Command Bits  
LINSL2 LINSL1 LIN-PU HS3ON HS2ON HS1ON MODE2 MODE1  
0/1  
1
1
0
0
0
0
1
SPI Status Register (Read)  
Table 13 shows the SPI Status register bits by name.  
Table 13. Control Bits Function (Read Operation)  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
L2  
D0  
L1  
INTSRC LINWU  
HVF  
LVF  
or  
VDDT  
HSST  
or  
LINFAIL  
BATFAIL  
INTSCR —Register Content Flags or Interrupt Source  
• 1 = Low-voltage condition has occurred.  
• 0 = No low-voltage condition.  
This bit indicates if the register contents reflect the flags or  
an interrupt/wake-up interrupt source.  
VDDT—Voltage Regulator Status Flag Bit  
• 1 = D6:D0 reflects the interrupt or wake-up source.  
• 0 = No interrupt occurred. Other SPI bits report real time  
status.  
This flag is set as prewarning in case of an over-  
temperature condition on the voltage regulator.  
• 1 = Voltage regulator over-temperature condition,  
prewarning.  
LINWU/LINFAIL—LIN Status Flag Bit  
• 0 = No over-temperature detected.  
This bit indicates a LIN wake-up condition.  
• 1 = LIN bus wake-up occurred or LIN over-current/over-  
temperature occurred.  
• 0 = No LIN bus wake-up occurred.  
HSST—High Side Status Flag Bit  
This flag is set on over-temperature conditions on one of  
the high side outputs.  
In case of a LIN over-current/over-temperature condition  
the LIN transmitter is disabled. To reenable the LIN  
transmitter, the error condition must be GONE and the  
LINWU/LINFAIL flag must be cleared.  
• 1 = HSx off due to over-temperature.  
• 0 = No over-temperature.  
In case one of the high sides has an over-temperature  
condition all high side switches are disabled.  
The flag is cleared by reading the flag when it is set (SPI  
command).  
To reenable the high side switches, the flags have to be  
cleared, by reading the flag when it is set and by writing a one  
to high side HSxON bit (two SPI commands are necessary).  
HVF —High-voltage Flag Bit  
This flag is set on an over-voltage (VSUP1) condition.  
L2:L1— Wake-up Inputs L1, L2 Status Flag Bit  
• 1 = High-voltage condition has occurred.  
• 0 = no High-voltage condition.  
These flags reflect the status of the L2 and L1 input pins  
and indicate the wake-up source.  
LVF/BATFAIL—Low-voltage Flag Bit  
• 1 = L2:L1 input high or wake-up by L2:L1 (first register  
read after wake-up indicated with INTSRC = 1).  
• 0 = L2:L1 input low.  
This flag is set on an under-voltage (VSUP1) condition.  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
27  
 
 
TYPICAL APPLICATIONS  
TYPICAL APPLICATIONS  
The programming is principally possible at two stages in  
DEVELOPMENT SUPPORT  
the manufacturing process — first on chip level, before the IC  
is soldered onto a PCB board and second after the IC is  
soldered onto the PCB board.  
As the 908E624 has the MC68HC908EY16 MCU  
embedded typically all the development tools available for  
the MCU also apply for this device, however due to the fact  
of the additional analog die circuitry and the nominal +12 V  
supply voltage some additional items have to be considered:  
Chip Level Programming  
On Chip level the easiest way is to only power the MCU  
with +5.0 V (see Figure 18) and not to provide the analog  
chip with VSUP, in this setup all the analog pin should be left  
open (e.g. VSUP[1:2]) and interconnections between MCU  
and analog die have to be separated (e.g. IRQ - IRQ_A).  
• nominal 12 V rather than 5.0 or 3.0 V supply  
• high voltage V  
but IRQ_A pin  
might be applied not only to IRQ pin,  
TST  
• MCU monitoring (Normal request timeout) has to be  
disabled  
This mode is well described in the MC68HC908EY16 data  
sheet - section development support.  
For a detailed information on the MCU related  
development support see the MC68HC908EY16 data sheet -  
section development support.  
VSUP[1:2]  
GND  
VDD  
AGND  
+5V  
VREFH  
VDDA  
EVDD  
RST  
RST_A  
VDD  
100nF  
4.7µF  
1
16  
C1+  
VCC  
VTST  
IRQ  
VREFL  
VSSA  
EVSS  
MM908E624  
+
+
+
1µF  
1µF  
1µF  
1µF  
3
4
15  
2
C1-  
GND  
V+  
1µF  
+
IRQ_A  
C2+  
6
V-  
VDD  
10k  
9.8304MHz CLOCK  
PTB4/AD4  
+5V  
MAX232  
5
C2-  
CLK  
RS232  
DB-9  
+
PTC4/OSC1  
PTA0/KBD0  
10k  
10k  
10k  
74HC125  
PTA1/KBD1  
PTB3/AD3  
WDCONF  
2
3
5
7
8
10  
9
6
5
DATA  
T2OUT  
R2IN  
T2IN  
74HC125  
4
R2OUT  
3
2
1
Figure 18. Normal Monitor Mode Circuit (MCU only)  
Of course it is also possible to supply the whole system  
with VSUP (12 V) instead as described in Figure 19, page 29.  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
28  
 
TYPICAL APPLICATIONS  
PCB Level Programming  
system has to be powered up providing V  
(see  
SUP  
Figure 19).  
If the IC is soldered onto the PCB board, it is typically not  
possible to separately power the MCU with +5.0 V, the whole  
VDD  
VSUP  
VSUP[1:2]  
GND  
VDD  
+
100nF  
AGND  
47µF  
VREFH  
VDDA  
EVDD  
RST  
RST_A  
VDD  
100nF  
4.7µF  
1
16  
C1+  
VCC  
VTST  
IRQ  
VREFL  
VSSA  
EVSS  
MM908E624  
+
+
+
1µF  
1µF  
1µF  
1µF  
2.2k  
3
4
15  
2
C1-  
GND  
V+  
1µF  
+
IRQ_A  
C2+  
6
V-  
VDD  
10k  
9.8304MHz CLOCK  
PTB4/AD4  
VDD  
MAX232  
5
C2-  
CLK  
RS232  
DB-9  
+
PTC4/OSC1  
PTA0/KBD0  
10k  
10k  
10k  
74HC125  
PTA1/KBD1  
PTB3/AD3  
WDCONF  
2
3
5
7
8
10  
9
6
5
DATA  
T2OUT  
R2IN  
T2IN  
74HC125  
4
R2OUT  
3
2
1
Figure 19. Normal Monitor Mode Circuit  
Table 14 summarizes the possible configurations and the  
necessary setups.  
Table 14. Monitor Mode Signal Requirements and Options  
Serial  
Communication  
Mode  
Selection  
Communication Speed  
Bus  
Normal  
Request  
Timeout  
Reset  
Vector  
Mode IRQ RST WDCONF  
ICG  
COP  
External  
Baud  
Rate  
PTA0  
PTA1 PTB3 PTB4  
Frequenc  
y
Clock  
Normal  
Monitor  
9.8304  
MHz  
2.4576  
MHz  
V
V
V
V
GND  
GND  
X
1
0
0
0
X
X
1
X
X
OFF  
OFF  
ON  
disabled  
disabled  
disabled  
enabled  
disabled  
disabled  
disabled  
enabled  
9600  
9600  
TST  
DD  
DD  
9.8304  
MHz  
2.4576  
MHz  
V
DD  
Forced  
Monitor  
$FFFF  
(blank)  
1
Nominal  
1.6 MHz  
Nominal  
6300  
GND  
—
—
not $FFFF  
(not blank)  
Nominal  
1.6 MHz  
Nominal  
6300  
User  
V
R
EXT  
X
X
ON  
DD  
DD  
Notes  
34. PTA0 must have a pull-up resistor to V in monitor mode.  
DD  
35. External clock is a 4.9152 MHz, 9.8304 MHz or 19.6608 MHz canned oscillator on OCS1.  
36. Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256.  
37. X = don’t care.  
38.  
V
is a high voltage V + 3.5 V ≤ VTST ≤ V + 4.5 V.  
TST DD DD  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
29  
 
 
TYPICAL APPLICATIONS  
MCU Digital Supply Pins (EVDD and EVSS)  
EMC/EMI RECOMMENDATIONS  
This paragraph gives some device specific  
Fast signal transitions on MCU pins place high, short  
duration current demands on the power supply. To prevent  
noise problems, take special care to provide power supply  
bypassing at the MCU. It is recommended that a high quality  
ceramic decoupling capacitor be placed between these pins.  
recommendations to improve EMC/EMI performance.  
Further generic design recommendations can be found on  
the Freescale website: www.freescale.com.  
VSUP Pins (VSUP1 and VSUP2)  
MCU Analog Supply Pins (VREFH, VDDA, VREFL, and  
VSSA)  
Its recommended to place a high quality ceramic  
decoupling capacitor close to the VSUP pins to improve  
EMC/EMI behavior.  
To avoid noise on the analog supply pins it is important to  
take special care on the layout. The MCU digital and analog  
supplies should be tied to the same potential via separate  
traces and connected to the voltage regulator output.  
LIN Pin  
For DPI (Direct Power Injection) and ESD (Electro Static  
Discharge) it is recommended to place a high quality ceramic  
decoupling capacitor near the LIN pin. An additional varistor  
will further increase the immunity against ESD. A ferrite in the  
LIN line will suppress some of the noise induced.  
Figure 20 and Figure 21 show the recommendations on  
schematics and layout level and Table 15 indicates  
recommended external components and layout  
considerations.  
Voltage Regulator Output Pins (VDD and AGND)  
Use a high quality ceramic decoupling capacitor to  
stabilize the regulated voltage.  
D1  
VSUP  
VSUP1  
VSUP2  
VDD  
+
C2  
AGND  
C1  
VREFH  
VDDA  
EVDD  
L1  
LIN  
LIN  
V1  
C5  
C3  
C4  
VREFL  
VSSA  
EVSS  
MM908E624  
GND  
Figure 20. EMC/EMI Recommendations  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
30  
 
TYPICAL APPLICATIONS  
1
54  
53  
2
3
52  
4
51  
5
50  
6
49  
7
VREFH 48  
VDDA 47  
EVDD 46  
EVSS 45  
VSSA 44  
VREFL 43  
42  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
41  
908E624  
40  
39  
38  
37  
Comment:  
Terminal 32 NC - used for signal routing  
36  
35  
C4  
AGND 34  
VDD 33  
NC  
32  
VSUP1 31  
GND 30  
LIN  
29  
D1  
VBAT  
LIN  
VSUP2 28  
C5  
L1  
Figure 21. PCB Layout Recommendations  
Table 15. Component Value Recommendation  
.
Component  
Recommended Value(39)  
Comments / Signal routing  
D1  
C1  
C2  
C3  
Reverse battery protection  
Bulk Capacitor  
100 nF, SMD Ceramic  
100 nF, SMD Ceramic  
Close (<5.0 mm) to VSUP1, VSUP2 pins with good ground return  
Close (<3.0 mm) to digital supply pins (EVDD, EVSS) with good  
ground return.  
The positive analog (VREFH, VDDA) and the digital (EVDD) supply  
should be connected right at the C3.  
C4  
C5  
4.7 μF, SMD Ceramic or Low ESR  
Bulk Capacitor  
180 pF, SMD Ceramic  
Close (<5.0 mm) to LIN pin.  
Total Capacitance per LIN node has to be below 220 pF.  
(C  
= C  
+ C5 + C  
~ 10 pF + 180 pF + 15 pF)  
TOTAL  
LIN-PIN  
VARISTOR  
(40)  
V1  
Varistor Type TDK AVR-M1608C270MBAAB  
SMD Ferrite Bead Type TDK MMZ2012Y202B  
Optional (close to LIN connector)  
Optional, (close to LIN connector)  
(40)  
L1  
Notes  
39. Freescale does not assume liability, endorse, or want components from external manufactures that are referenced in circuit drawings  
or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their  
application.  
40. Components are recommended to improve EMC and ESD performance.  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
31  
 
 
PACKAGING  
PACKAGING DIMENSIONS  
PACKAGING  
PACKAGING DIMENSIONS  
Important For the most current revision of the package, visit www.freescale.com and do a keyword search on the  
98ASA99294D drawing number below. Dimensions shown are provided for reference ONLY.  
EW SUFFIX (Pb-FREE)  
54-Pin SOIC WIDE BODY  
98ASA99294D  
ISSUE B  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
32  
PACKAGING  
PACKAGING DIMENSIONS  
EW SUFFIX (Pb-FREE)  
54-Pin SOIC WIDE BODY  
98ASA99294D  
ISSUE B  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
33  
PACKAGING  
PACKAGING DIMENSIONS  
EW SUFFIX (Pb-FREE)  
54-Pin SOIC WIDE BODY  
98ASA99294D  
ISSUE B  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
34  
ADDITIONAL DOCUMENTATION  
THERMAL ADDENDUM (REV 3.0)  
ADDITIONAL DOCUMENTATION  
908E624  
THERMAL ADDENDUM (REV 3.0)  
INTRODUCTION  
This thermal addendum is provided as a supplement to the MM908E624  
technical datasheet. The addendum provides thermal performance information  
that may be critical in the design and development of system applications. All  
electrical, application, and packaging information is provided in the datasheet.  
54-Pin  
SOICW  
Packaging and Thermal Considerations  
The MM908E624 is a dual die package. There are two heat sources in the  
package independently heating with P and P . This results in two junction  
1
2
temperatures, T and T , and a thermal resistance matrix with RθJAmn  
.
J1  
J2  
For m, n = 1, RθJA11 is the thermal resistance from Junction 1 to the reference  
temperature while only heat source 1 is heating with P .  
1
EW (Pb-FREE) SUFFIX  
98ASA99294D  
For m = 1, n = 2, RθJA12 is the thermal resistance from Junction 1 to the  
reference temperature while heat source 2 is heating with P . This applies to  
RθJ21 and RθJ22, respectively.  
54-Pin SOICW  
2
Note For package dimensions, refer to  
98ASA99294D.  
RθJA11 RθJA12  
RθJA21 RθJA22  
T
T
P
P
J1  
J2  
1
2
.
=
The stated values are solely for a thermal performance comparison of one  
package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a  
package in an application-specific environment. Stated values were obtained by measurement and simulation according to the  
standards listed below  
Standards  
Table 16. Thermal Performance Comparison  
1 = Power Chip, 2 = Logic Chip [°C/W]  
Thermal  
m = 1,  
n = 1  
m = 1, n = 2  
m = 2, n = 1  
m = 2,  
n = 2  
Resistance  
(1)(2)  
R
40  
25  
57  
21  
31  
16  
47  
12  
36  
21  
52  
16  
θJAmn  
θJBmn  
θJAmn  
θJCmn  
(2)(3)  
(1)(4)  
(5)  
R
R
R
Notes:  
1. Per JEDEC JESD51-2 at natural convection, still air  
condition.  
2. 2s2p thermal test board per JEDEC JESD51-7and  
JESD51-5.  
54 Terminal SOIC  
0.65 mm Pitch  
17.9 mm x 7.5 mm Body  
3. Per JEDEC JESD51-8, with the board temperature on the  
center trace near the power outputs.  
4. Single layer thermal test board per JEDEC JESD51-3 and  
JESD51-5.  
5. Thermal resistance between the die junction and the  
exposed pad, “infinite” heat sink attached to exposed pad.  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
35  
ADDITIONAL DOCUMENTATION  
THERMAL ADDENDUM (REV 3.0)  
A
PTB7/AD7/TBCH1  
PTB6/AD6/TBCH0  
PTC4/OSC1  
PTC3/OSC2  
PTC2/MCLK  
PTB5/AD5  
PTB4/AD4  
PTB3/AD3  
IRQ  
1
2
3
4
5
6
7
8
PTA0/KBD0  
PTA1/KBD1  
PTA2/KBD2  
FLSVPP  
PTA3/KBD3  
PTA4/KBD4  
VREFH  
VDDA  
EVDD  
EVSS  
VSSA  
VREFL  
PTE1/RXD  
NC  
RXD  
WDCONF  
+E  
-E  
OUT  
VCC  
AGND  
VDD  
NC  
VSUP1  
GND  
LIN  
VSUP2  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
9
RST  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
PTB1/AD1  
PTD0/TACH0  
PTD1/TACH1  
NC  
NC  
NC  
PWMIN  
RST_A  
IRQ_A  
NC  
NC  
NC  
L1  
L2  
HS3  
HS2  
HS1  
908E624 Pin Connections  
54-Pin SOICW  
0.65 mm Pitch  
17.9 mm x 7.5 mm Body  
Figure 22. Surface Mount for SOIC Wide Body  
Non-exposed Pad  
Device on Thermal Test Board  
Table 17. Thermal Resistance Performance  
Material:  
Single layer printed circuit board  
1 = Power Chip, 2 = Logic Chip (°C/W)  
FR4, 1.6 mm thickness  
Pin  
Resistance  
Area A  
(mm2)  
Cu traces, 0.07 mm thickness  
m = 1,  
n = 1  
m = 1, n = 2  
m = 2, n = 1  
m = 2,  
n = 2  
Outline:  
80 mm x 100 mm board area,  
including edge connector for thermal  
testing  
R
0
58  
56  
54  
48  
46  
45  
53  
51  
50  
mn  
θJA  
300  
600  
Area A:  
Cu heat-spreading areas on board  
surface  
Ambient Conditions: Natural convection, still air  
RθJAmn is the thermal resistance between die junction and  
ambient air.  
This device is a dual die package. Index m indicates the  
die that is heated. Index n refers to the number of the die  
where the junction temperature is sensed.  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
36  
ADDITIONAL DOCUMENTATION  
THERMAL ADDENDUM (REV 3.0)  
θJA  
70  
60  
50  
40  
30  
20  
10  
0
R
θ
JA11  
R
R
x
θ
JA22  
JA12 = R  
θJA21  
θ
0
300  
600  
Heat spreading area [mm²]  
A
Figure 23. Device on Thermal Test Board  
100  
10  
1
R
x
θ
JA11  
JA22  
R
θ
R
JA12 = R  
θJA21  
θ
0.1  
1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04  
Time[s]  
Figure 24. Transient Thermal Resistance RθJA (1.0 W Step Response)  
Device on Thermal Test Board Area A = 600 (mm2)  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
37  
 
REVISION HISTORY  
REVISION HISTORY  
REVISION  
DATE  
DESCRIPTION OF CHANGES  
•
•
•
Implemented Revision History page  
Added Pb-Free package option (Suffix EW) and higher Soldering temperature  
5/2006  
7.0  
Added “Y” temperature (T -40°C to 125°C) code option (MM908E624AYEW) and updated condi-  
J
tion statement for Static and Dynamic Electrical Characteristics  
•
Corrected Figure 11, Operating Modes and Transitions (“STOP command” for transition from Nor-  
mal to Stop state)  
•
•
•
•
•
•
•
•
•
Updated Figure 21, PCB Layout Recommendations, comment NC Pin used for signal routing  
Updated Table 15, Component Value Recommendation  
Corrected Figure 23, Device on Thermal Test Board  
Removed reference to Note 11, Voltage Regulator - Dropout Voltage  
Added comment “LIN in recessive state” to Supply Current Range in Stop Mode and Sleep Mode  
Updated format to match current data sheet standard.  
Added Figure 10, Power On Reset and Normal Request Timeout Timing  
Added LIN P/L details  
Made clarifications on Max Ratings Table for T and T Thermal Ratings and the accompanying  
A
J
Note  
3/2007  
9/2010  
•
•
Removed “Advance Information” watermark from first page.  
Changed Peak Package Reflow Temperature During Reflow  
8.0  
9.0  
(3)(5)  
description.  
(5)  
•
•
•
•
•
•
•
Added note  
Deleted MM908E624ACDWB/R2  
8/2011  
10.0  
Added MM908E624ACPEW/R2 and MM908E624AYPEW/R2  
Update Freescale form and style.  
Updated package drawing  
Removed part number MM908E624ACEW/ R2 and MM908E624AYEW/ R2.  
Update Freescale form and style.  
4/2012  
11.0  
908E624  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
38  
Information in this document is provided solely to enable system and software  
implementers to use Freescale products. There are no express or implied copyright  
licenses granted hereunder to design or fabricate any integrated circuits on the  
information in this document.  
How to Reach Us:  
Home Page:  
freescale.com  
Web Support:  
freescale.com/support  
Freescale reserves the right to make changes without further notice to any products  
herein. Freescale makes no warranty, representation, or guarantee regarding the  
suitability of its products for any particular purpose, nor does Freescale assume any  
liability arising out of the application or use of any product or circuit, and specifically  
disclaims any and all liability, including without limitation consequential or incidental  
damages. “Typical” parameters that may be provided in Freescale data sheets and/or  
specifications can and do vary in different applications, and actual performance may  
vary over time. All operating parameters, including “typicals,” must be validated for  
each customer application by customer’s technical experts. Freescale does not convey  
any license under its patent rights nor the rights of others. Freescale sells products  
pursuant to standard terms and conditions of sale, which can be found at the following  
address: http://www.reg.net/v2/webservices/Freescale/Docs/TermsandConditions.htm  
Freescale, the Freescale logo, AltiVec, C-5, CodeTest, CodeWarrior, ColdFire, C-Ware,  
Energy Efficient Solutions logo, mobileGT, PowerQUICC, QorIQ, Qorivva, StarCore, and  
Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.  
Airfast, BeeKit, BeeStack, ColdFire+, CoreNet, Flexis, MagniV, MXC, Platform in a  
Package, Processor expert, QorIQ Qonverge, QUICC Engine, Ready Play,  
SMARTMOS, TurboLink, Vybrid, and Xtrinsic are trademarks of Freescale  
Semiconductor, Inc. All other product or service names are the property of their  
respective owners.  
© 2012 Freescale Semiconductor, Inc.  
Document Number: MM908E624  
Rev. 11.0  
4/2012  

相关型号：

MM908E624AYPEWR2

 Relay driver, 3x HSS, I-sense, VREG, 8-bit MCU, 512B RAM, 16KB Flash, LIN, SOICW 54 , Reel
NXP

MM908E625

 Integrated Quad Half H-Bridge with Power Supply, Embedded MCU, and LIN Serial Communication
MOTOROLA

MM908E625

 Integrated Quad Half H-Bridge with Power Supply, Embedded MCU, and LIN Serial Communication
FREESCALE

MM908E625ACDWB

 Integrated Quad Half H-Bridge with Power Supply, Embedded MCU, and LIN Serial Communication
FREESCALE

MM908E625ACDWB/R2

 Integrated Quad Half H-Bridge with Power Supply, Embedded MCU, and LIN Serial Communication
MOTOROLA

MM908E625ACDWB/R2

 Integrated Quad Half H-Bridge with Power Supply, Embedded MCU, and LIN Serial Communication
FREESCALE

MM908E625ACEK

 Integrated Quad Half H-Bridge with Power Supply, Embedded MCU, and LIN Serial Communication
FREESCALE

MM908E625ACPEK

 Stepper motor driver, 4x H-B, 1 HSS, 3x Hall input, 8-bit MCU, 16KB Flash , LIN,SOIC-EP 54, Rail
NXP

MM908E625ACPEKR2

 Stepper motor driver, 4x H-B, 1 HSS, 3x Hall input, 8-bit MCU, 16KB Flash , LIN,SOIC-EP 54, Reel
NXP

MM908E626

 Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication
FREESCALE

MM908E626AVDWB

 Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication
FREESCALE

MM908E626AVDWB/R2

 Integrated Stepper Motor Driver with Embedded MCU and LIN Serial Communication
FREESCALE
©2020 ICPDF网 联系我们和版权申明