MM908E625ACPEKR2_技术文档

Document Number: MM908E625

Rev 10, 04/2012

Freescale Semiconductor

Technical Data

Integrated Quad Half H-Bridge

with Power Supply, Embedded

MCU, and LIN Serial

908E625

Communication

H-BRIDGE POWER SUPPLY WITH

EMBEDDED MCU AND LIN

The 908E625 is an integrated single package solution including a

high performance HC08 microcontroller with a SMARTMOS analog

control IC. The HC08 includes flash memory, a timer, enhanced serial

communications interface (ESCI), an analog-to-digital converter

(ADC), internal serial peripheral interface (SPI), and an internal clock

generator (ICG) module. The analog control die provides fully

protected H-Bridge/high side outputs, voltage regulator, autonomous

watchdog with cyclic wake-up, and local interconnect network (LIN)

physical layer.

The single package solution, together with LIN, provides optimal

application performance adjustments and space saving PCB design.

It is well-suited for the control of automotive mirror, door lock, and

light-leveling applications.

EK SUFFIX

98ARL10519D

54-PIN SOICW-EP

Features

• High-performance M68HC908EY16 core

• 16 KB of on-chip flash memory & 512 B of RAM

• Internal clock generation module

• Two 16-bit, two-channel timers

• 10-bit ADC

ORDERING INFORMATION

Device

Temperature

Range (T)

(Add an R2 suffix for Tape

Package

A

and reel orders)

• LIN physical layer

54 SOICW

EP

• Autonomous watchdog with cyclic wake-up

• Three two-pin Hall effect sensor input ports

• One analog input with switchable current source

• Four low R_DS(ON)half-bridge outputs

• One low R_DS(ON)high side output

• 13 micro controller I/Os

MM908E625ACPEK

-40 to 85 °C

908E625

VSP1:3]

LIN

HB1

HB2

VREFH

VDDA

EVDD

VDD

Four Half-bridges

Controlling 3 Loads

M

HB3

HB4

HS

VREFL

VSSA

EVSS

VSS

High Side Output

Switchable Internal V Output

DD

HVDD

RST A

RST

IRQ A

IRQ

SS

PTB1/AD1

RXD

H1

H2

H3

Three 2-pin Hall-effect Sensor Inputs

PTE1/RXD

PTD1/TACH1

FGEN

BEMF

PTD0/TACH0/BEMF

PA1

Analog Input with Current Source

Microcontroller Ports

PORTA I/Os

PORTB I/Os

PORTC I/Os

GND[1:2]

EP

Figure 1. 908E625 Simplified Application Diagram

* This document contains information on a new product.

Specifications and information herein are subject to change without notice.

INTERNAL BLOCK DIAGRAM

GND1-2

VSUP1-3

RST_A

IRQ_A

BEMF

FGEN

LIN

RXD

SS

PTE1/RXD

PTD1/TACH1

PTD0/TACH0

PTB1/AD1

RST

C T

P O R

D T

P O R

E T

P O R

D D R C

D D R D

D D R E

IRQ

VREFL

VSSA

I n t e r n a l B u s

D D R A

P O R

D D R B

P O R

A T

B T

EVSS

EVDD

VDDA

VREFH

Figure 2. 908E625 Simplified Internal Block Diagram

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

2

PIN CONNECTIONS

PTB7/AD7/TBCH1

PTB6/AD6/TBCH0

PTC4/OSC1

PTC3/OSC2

PTC2/MCLK

PTB5/AD5

PTB4/AD4

PTB3/AD3

IRQ

1

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

PTA0/KBD0

PTA1/KBD1

PTA2/KBD2

FLSVPP

PTA3/KBD3

PTA4/KBD4

VREFH

VDDA

EVDD

EVSS

2

3

4

5

6

7

8

9

RST

10

11

12

13

PTB1/AD1

PTD0/TACH0/BEMF

PTD1/TACH1

NC

VSSA

VREFL

PTE1/RXD

RXD

VSS

PA1

VDD

H1

H2

H3

HVDD

NC

HB4

VSUP3

GND2

HB3

Exposed

Pad

14

15

16

17

18

19

20

21

22

23

24

25

26

27

FGEN

BEMF

RST_A

IRQ_A

SS

LIN

NC

HB1

VSUP1

GND1

HB2

VSUP2

HS

Figure 3. 908E625 Pin Connections (Transparent Package Top View)

Table 1. 908E625 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 14.

Pin Function

Pin Name

Formal Name

Definition

MCU

1

2

6

PTB7/AD7/TBCH1

PTB6/AD6/TBCH0

PTB5/AD5

Port B I/Os

These pins are special function, bi-directional I/O port pins that

are shared with other functional modules in the MCU.

7

PTB4/AD4

8

PTB3/AD3

11

PTB1/AD1

MCU

3

4

5

PTC4/OSC1

PTC3/OSC2

PTC2/MCLK

Port C I/Os

These pins are special function, bi-directional I/O port pins that

are shared with other functional modules in the MCU.

IRQ

MCU

9

External Interrupt Input

External Reset

This pin is an asynchronous external interrupt input pin.

RST

10

This pin is bi-directional, allowing a reset of the entire system.

It is driven low when any internal reset source is asserted.

MCU

–

12

13

PTD0/TACH0/BEMF

PTD1/TACH1

Port D I/Os

No Connect

These pins are special function, bi-directional I/O port pins that

are shared with other functional modules in the MCU.

14, 21, 22, 33

NC

Not connected.

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

3

PIN CONNECTIONS

Table 1. 908E625 Pin Definitions (continued)

A functional description of each pin can be found in the Functional Pin Description section beginning on page 14.

Pin Function

Pin Name

Formal Name

Definition

MCU

42

PTE1/RXD

Port E I/O

This pin is a special function, bi-directional I/O port pin that can

is shared with other functional modules in the MCU.

MCU

43

48

VREFL

VREFH

ADC References

ADC Supply pins

These pins are the reference voltage pins for the analog-to-

digital converter (ADC).

44

47

VSSA

VDDA

These pins are the power supply pins for the analog-to-digital

converter.

MCU

45

46

EVSS

EVDD

MCU Power Supply These pins are the ground and power supply pins, respectively.

Pins

The MCU operates from a single power supply.

49

50

52

53

54

PTA4/KBD4

PTA3/KBD3

PTA2/KBD2

PTA1/KBD1

PTA0/KBD0

Port A I/Os

These pins are special function, bi-directional I/O port pins that

are shared with other functional modules in the MCU.

MCU

51

15

FLSVPP

FGEN

Test Pin

For test purposes only. Do not connect in the application.

Analog

Current Limitation

Frequency Input

This is the input pin for the half-bridge current limitation and the

high side inrush current limiter PWM frequency.

Analog

16

BEMF

Back Electromagnetic This pin gives the user information about back electromagnetic

Force Output

force (BEMF).

Analog

17

18

Internal Reset

RST_A

IRQ_A

This pin is the bi-directional reset pin of the analog die.

Internal Interrupt

Output

This pin is the interrupt output pin of the analog die indicating

errors or wake-up events.

Analog

19

20

Slave Select

LIN Bus

This pin is the SPI slave select pin for the analog chip.

SS

LIN

This pin represents the single wire bus transmitter and receiver.

23

26

29

32

HB1

HB2

HB3

HB4

Half-bridge Outputs This device includes power MOSFETs configured as four half-

bridge driver outputs. These outputs may be configured for step

motor drivers, DC motor drivers, or as high side and low side

switches.

Analog

24

27

31

VSUP1

VSUP2

VSUP3

Power Supply Pins

These pins are device power supply pins.

25

30

GND1

GND2

Power Ground Pins These pins are device power ground connections.

High-Side Output This output pin is a low R_DS(ON)high side switch.

Analog

28

34

HS

HVDD

Switchable V_DDOutput This pin is a switchable V_DDoutput for driving resistive loads

requiring a regulated 5.0 V supply; e.g., 3-pin Hall-effect

sensors.

Analog

35

36

37

H3

H2

H1

Hall-effect Sensor

Inputs

These pins provide inputs for Hall-effect sensors and switches.

38

VDD

Voltage Regulator

Output

The +5.0 V voltage regulator output pin is intended to supply

the embedded microcontroller.

Analog

39

40

PA1

VSS

Analog Input

This pin is an analog input port with selectable source values.

Voltage Regulator

Ground

Ground pin for the connection of all non-power ground

connections (microcontroller and sensors).

Analog

–

41

RXD

LIN Transceiver Output This pin is the output of LIN transceiver.

Exposed Pad The exposed pad pin on the bottom side of the package

conducts heat from the chip to the PCB board.

EP

Exposed Pad

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

4

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings

Symbol

Value

Unit

ELECTRICAL RATINGS

Supply Voltage

V

-0.3 to 28

-0.3 to 40

-0.3 to 6.0

SUP(SS)

SUP(PK)

Analog Chip Supply Voltage under Normal Operation, Steady State

V

Analog Chip Supply Voltage under Transient Conditions ⁽¹⁾

Microcontroller Chip Supply Voltage

V

DD

Input Pin Voltage

Analog Chip

V

-0.3 to 5.5

IN(ANALOG)

Microcontroller Chip

V

-0.3 to V +0.3

SS DD

V

IN(MCU)

Maximum Microcontroller Current per Pin

All Pins Except VDD, VSS, PTA0:PTA6, PTC0:PTC1

Pins PTA0:PTA6, PTC0:PTC1

mA

I

±15

±25

PIN(1)

PIN(2)

Maximum Microcontroller V_SSOutput Current

Maximum Microcontroller V_DDInput Current

I

100

mA

V

MVSS

I

MVDD

LIN Supply Voltage

Normal Operation (Steady-State)

V

-18 to 28

40

BUS(SS)

Transient Conditions ⁽¹⁾

V

BUS(DYNAMIC)

ESD Voltage

V

±3000

±150

±500

ESD

Human Body Model (HBM)⁽²⁾

Machine Model (MM)⁽³⁾

Charge Device Model (CDM)⁽⁴⁾

THERMAL RATINGS

Storage Temperature

T

-40 to 150

-40 to 85

°C

STG

Ambient Operating Temperature

Operating Case Temperature ⁽⁵⁾

T

A

C

T

Operating Junction Temperature⁽⁶⁾

J

T

-40 to 125

Note 8

°C

Peak Package Reflow Temperature During Reflow⁽⁷⁾⁽⁸⁾

T_PPRT

°C

Notes

1. Transient capability for pulses with a time of t < 0.5 sec.

2. ESD voltage testing is performed in accordance with the Human Body Model (C

= 100 pF, R

= 1500 Ω)

ZAP

3. ESD voltage testing is performed in accordance with the Machine Model (C

=200 pF, R

= 0 Ω)

ZAP

4. ESD voltage testing is performed in accordance with Charge Device Model, robotic (C

=4.0 pF).

ZAP

5. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking.

6. The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because

of higher power dissipation on the analog die. The analog die temperature must not exceed 150 °C under these conditions.

7. Pin soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may cause

malfunction or permanent damage to the device.

8. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes

and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

5

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the

microcontroller chip. Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40 °C ≤ T_J≤ 125 °C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

SUPPLY VOLTAGE

Nominal Operating Voltage

V

8.0

–

18

V

SUP

SUPPLY CURRENT

Normal Mode

I

mA

RUN

V

= 12 V, Power Die ON (PSON=1), MCU Operating Using

–

20

–

SUP

Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI,

ADC Enabled

μA

STOP Mode ⁽⁹⁾

I

60

STOP

V

= 12 V, Cyclic Wake-up Disabled

SUP

DIGITAL INTERFACE RATINGS (ANALOG DIE)

Output Pins RST_A, IRQ_A

V_OL

V_OH

–

0.4

–

Low State Output Voltage (I_OUT= -1.5 mA)

High State Output Voltage (I_OUT= 1.0 μA)

V

3.85

Output Pins BEMF, RXD

Low State Output Voltage (I_OUT= -1.5 mA)

High State Output Voltage (I_OUT= 1.5 mA)

V_OL

V_OH

–

0.4

–

V

3.85

Output Pin RXD–Capacitance ⁽¹⁰⁾

C_IN

–

4.0

–

pF

Input Pins RST_A, FGEN, SS

Input Logic Low Voltage

Input Logic High Voltage

V_IL

V_IH

C_IN

–

1.5

–

V

3.5

Input Pins RST_A, FGEN, SS–Capacitance ⁽¹⁰⁾

Pins RST_A, IRQ_A–Pull-up Resistor

Pin SS–Pull-up Resistor

–

4.0

–

pF

R

–

10

60

35

–

kΩ

μA

PULLUP1

PULLUP2

Pins FGEN, MOSI, SPSCK–Pull-down Resistor

Pin TXD–Pull-up Current Source

Notes

R

PULLDOWN

I

PULLUP

9. STOP mode current will increase if V

exceeds 15 V.

SUP

10. This parameter is guaranteed by process monitoring but is not production tested.

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

6

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the

microcontroller chip. Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40 °C ≤ T_J≤ 125 °C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless otherwise noted.

Characteristic

SYSTEM RESETS AND INTERRUPTS

Symbol

Min

Typ

Max

Unit

High Voltage Reset

Threshold

V

27

–

30

33

–

HVRON

Hysteresis

1.5

V

HVRH

Low Voltage Reset

Threshold

3.6

–

4.0

4.5

–

V

LVRON

Hysteresis

100

mV

V

LVRH

High Voltage Interrupt

Threshold

V

17.5

–

21

23

–

HVION

Hysteresis

1.0

V

HVIH

Low Voltage Interrupt

Threshold

V

6.5

–

8.0

–

LVION

Hysteresis

0.4

V

LVIH

High Temperature Reset ⁽¹¹⁾

Threshold

°C

T

–

170

–

RON

5.0

T

Hysteresis

RH

High Temperature Interrupt ⁽¹²⁾

Threshold

T

–

160

–

ION

5.0

Hysteresis

T

IH

VOLTAGE REGULATOR

Normal Mode Output Voltage

V

mV

V

DDRUN

I

_OUT= 60 mA, 6.0 V < V

< 18 V

4.75

5.0

5.25

SUP

Load Regulation

_OUT= 80 mA, V

V

LR

–

100

5.0

I

= 9.0 V, T_J= 125°C

SUP

Stop Mode Output Voltage (Maximum Output Current 100 μA)

V

4.45

4.7

DDSTOP

LIN-LOW

LIN-HIGH

LIN PHYSICAL LAYER

Output Low Level

V

TXD LOW, 500 Ω Pull-up to V

–

1.4

SUP

Output High Level

V

TXD HIGH, I

= 1.0 μA

V_SUP-1.0

20

–

OUT

Pullup Resistor to V_SUP

R

30

60

kΩ

μA

SLAVE

Leakage Current to GND

I

BUS_PAS_rec

Recessive State (-0.5 V < V_LIN< V_SUP

)

0.0

–

20

Leakage Current to GND (V_SUPDisconnected)

Including Internal Pull-up Resistor, V_LIN@ -18 V

Including Internal Pull-up Resistor, V_LIN@ +18 V

μA

I

–

-600

25

–

BUS_NO_GND

I

BUS

Notes

11. This parameter is guaranteed by process monitoring but is not production tested.

12. High Temperature Interrupt (HTI) threshold is linked to High Temperature Reset (HTR) threshold (HTR = HTI + 10°C).

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

7

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the

microcontroller chip. Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40 °C ≤ T_J≤ 125 °C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

LIN Receiver

Recessive

V

0.6 V

–

V_SUP

IH

LIN

Dominant

V

IL

0.4 V_LIN

0.0

–

V

/2

Threshold

SUP

–

V

–

ITH

Input Hysteresis

0.01 V

0.1 V_SUP

SUP

V

IHY

LIN Wake-up Threshold

V

–

/2

–

V

WTH

SUP

HIGH SIDE OUTPUT (HS)

R

–

600

–

700

7.0

mΩ

Switch ON Resistance @ T_J= 25 °C with I_LOAD= 1.0 A

DS(ON)HS

High Side Over-current Shutdown

I

3.9

A

HSOC

HALF-BRIDGE OUTPUTS (HB1:HB4)

mΩ

Switch ON Resistance @ T_J= 25 °C with I_LOAD= 1.0 A

R

–

425

400

500

High Side

Low Side

DS(ON)HB_HS

R

DS(ON)HB_LS

High Side Over-current Shutdown

Low Side Over-current Shutdown

Low Side Current Limitation @ T_J= 25°C

4.0

2.8

–

7.5

I

A

HBHSOC

I

HBLSOC

mA

I

–

55

–

CL1

Current Limit 1 (CLS2 = 0, CLS1 = 1, CLS0 = 1)

Current Limit 2 (CLS2 = 1, CLS1 = 0, CLS0 = 0)

Current Limit 3 (CLS2 = 1, CLS1 = 0, CLS0 = 1)

Current Limit 4 (CLS2 = 1, CLS1 = 1, CLS0 = 0)

Current Limit 5 (CLS2 = 1, CLS1 = 1, CLS0 = 1)

I

210

300

450

600

260

370

550

740

315

440

650

880

CL2

I

CL3

I

CL4

CL5

Half-bridge Output High Threshold for BEMF Detection

Half-bridge Output Low Threshold for BEMF Detection

Hysteresis for BEMF Detection

V

–

-30

-60

30

0

-5.0

–

V

BEMFH

V

mV

V/A

BEMFL

V

BEMFHY

Low Side Current-to-Voltage Ratio (V

[V]/I [A])

HB

ADOUT

RATIO

7.0

1.0

12.0

2.0

14.0

3.0

H

CSA = 1

CSA = 0

RATIO

L

SWITCHABLE V_DDOUTPUT (PH.D.)

Over-current Shutdown Threshold

I

24

30

40

mA

–

HVDDOCT

V_SUPDOWN-SCALER

Voltage Ratio (RATIO_VSUP= V_SUP/V_ADOUT

)

RATIO_VSUP

4.8

5.1

5.35

INTERNAL DIE TEMPERATURE SENSOR

Voltage/Temperature Slope

S

–

19

–

mV/°C

V

TTOV

Output Voltage @ 25 °C

V

1.7

2.1

2.5

T25

HALL-EFFECT SENSOR INPUTS (H1:H3)

Output Voltage

V

< 16.2 V

> 16.2 V

V

–

V

_SUP-1.2

–

SUP

HALL1

HALL2

15

V

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

8

ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics (continued)

All characteristics are for the analog chip only. Refer to the 68HC908EY16 specification for characteristics of the

microcontroller chip. Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40 °C ≤ T_J≤ 125 °C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

Sense Current

Threshold

mA

I

6.9

–

8.8

11

–

HSCT

0.88

Hysteresis

I

HSCH

Output Current Limitation

–

90

3.0

0.5

–

mA

V

I

HL

Over-current Warning HP_OCF Flag Threshold]

Dropout Voltage @ I = 15 mA

V_HPOCT

V

LOAD

HPDO

ANALOG INPUT (PA1)

Current Source PA1

μA

I_CSPA1

CSSEL1 = 1, CSSEL0 = 1

570

670

770

Selectable Scaling Factor Current Source PA1 (I(N) = I_CSPA1* N)

%

N_CSPA1-0

N_CSPA1-1

N_CSPA1-2

8.5

10

30

60

11.5

31.5

61.5

CSSEL1 = 0, CSSEL0 = 0

CSSEL1 = 0, CSSEL0 = 1

CSSEL1 = 1, CSSEL0 = 0

28.5

58.5

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

9

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

All characteristics are for the analog chip only. Please refer to the specification for 68HC908EY16 for characteristics of the

microcontroller chip. Characteristics noted under conditions 9.0 V ≤ V_SUP≤ 16 V, -40 °C ≤ T_J≤ 125 °C, unless otherwise noted.

Typical values noted reflect the approximate parameter mean at T_A= 25 °C under nominal conditions, unless otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

LIN PHYSICAL LAYER

(14)

Propagation Delay ⁽¹³⁾

,

μs

t

–

6.0

8.0

2.0

TXD-LIN-low

TXD Low to LIN Low

t

TXD-LIN-high

TXD High to LIN High

LIN Low to RXD Low

LIN High to RXD High

TXD Symmetry

t

–

4.0

–

LIN-RXD-low

–

t

LIN-RXD-

high

-2.0

t

TXD-SYM

RXD-SYM

–

RXD Symmetry

(15)

Output Falling Edge Slew Rate ⁽¹³⁾

80% to 20%

,

F

SR

V/μs

-1.0

-2.0

-3.0

(15)

Output Rising Edge Slew Rate ⁽¹³⁾

,

R

SR

1.0

2.0

–

3.0

2.0

20% to 80%, R_BUS> 1.0 kΩ, C_BUS< 10 nF

LIN Rise/Fall Slew Rate Symmetry ⁽¹³⁾

,

S

(15)

SR

-2.0

μs

HALL-EFFECT SENSOR INPUTS (H1:H3)

Propagation Delay

t

–

1.0

40

–

HPPD

AUTONOMOUS WATCHDOG (AWD)

AWD Oscillator Period

t

μs

OSC

AWD Period Low = 512 t_OSC

T_J< 25 °C

t

ms

AWDPH

16

27

22

34

28

T_J≥ 25 °C

AWD Period High = 256 t_OSC

T_J< 25 °C

t

ms

AWDPL

8.0

13.5

11

17

14

T_J≥ 25 °C

AWD Cyclic Wake-up On Time

t

–

90

–

μs

AWDHPON

Notes

13. All LIN characteristics are for initial LIN slew rate selection (20 kBaud) (SRS0:SRS1= 00).

14. See Figure 2.

15. See Figure 3.

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

10

ELECTRICAL CHARACTERISTICS

MICROCONTROLLER PARAMETRICS

Table 5. Microcontroller Description

For a detailed microcontroller description, refer to the MC68HC908EY16 data sheet.

Module

Core

Timer

Flash

RAM

ADC

Description

High Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz

Two 16-Bit Timers with Two Channels (TIM A and TIM B)

16 K Bytes

512 Bytes

10-Bit Analog-to-Digital Converter

SPI Module

SPI

ESCI

Standard Serial Communication Interface (SCI) Module

Bit-Time Measurement

Arbitration

Prescaler with Fine Baud Rate Adjustment

ICG

Internal Clock Generation Module (25% Accuracy with Trim Capability to 2%)

BEMF Counter

Special Counter for SMARTMOS™ BEMF Output

TIMING DIAGRAMS

t

TXD-LIN-high

Tx-LIN-high

t

TXD-LIN-low

Tx-LIN-low

TXD

Tx

TXD

LLIINN

0.9 V

0.9 VSUP

Recessive State

SUP

0.7 V

0.6 VSUP

LIN

0.4 VSUP

0.3 V

LIN

0.1 V

SUP

0.1 VSUP

Dominant State

Rx

RXD

t

_Lt_IN_LI_-_N_R_-_X_R_D_x_-_-_l_l_o_o_w_w

t_LIN-RXD-high

LIN-Rx-high

Figure 4. LIN Timing Description

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

11

ELECTRICAL CHARACTERISTICS

ELECTRICAL PERFORMANCE CURVES

Δt Fall-time

Δt Rise-time

0.8 V

0.8 VSUP

SUP

00..88VVSUP

SUP

ΔV Fall

ΔV Rise

0.2 V

0.2 VSUP

SUP

0.2 V

0.2 VSUP

SUP

Dominant State

ΔV Fall

ΔV Rise

Δt Rise-time

SR_F=

SR_R=

Δt Fall-time

Figure 5. LIN Slew Rate Description

ELECTRICAL PERFORMANCE CURVES

1.6

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.0

T_J= 25°C

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

I_LOAD(A)

H-Bridge Low Side

Figure 6. Free Wheel Diode Forward Voltage vs. I_LOAD

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

12

ELECTRICAL CHARACTERISTICS

ELECTRICAL PERFORMANCE CURVES

250

200

150

100

50

T_A= 125°C

T_A= 25°C

T_A= -40°C

20

0

5

10

15

25

I

_Load(mA)

Figure 7. Dropout Voltage on HVDD vs. I_LOAD

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

FUNCTIONAL DESCRIPTION

INTRODUCTION

FUNCTIONAL DESCRIPTION

INTRODUCTION

The 908E625 device was designed and developed as a

highly integrated and cost effective solution for automotive

and industrial applications. For automotive body electronics,

the 908E625 is well suited to perform complete mirror, door

lock, and light-levelling control all via a three-wire LIN bus.

one high side switch. Other ports are also provided; they

include Hall-effect sensor input ports, analog input ports, and

a selectable HVDD pin. An internal voltage regulator is

provided on the SMARTMOS IC chip, which provides power

to the MCU chip.

This device combines an standard HC08 MCU core

(68HC908EY16) with flash memory together with a

SMARTMOS IC chip. The SMARTMO™ IC chip combines

power and control in one chip. Power switches are provided

on the SMARTMOS IC configured as half-bridge outputs with

Also included in this device is a LIN physical layer, which

communicates using a single wire. This enables the device to

be compatible with three-wire bus systems, where one wire is

used for communication, one for battery, and the third for

ground.

FUNCTIONAL PIN DESCRIPTION

See Figure 1 for a graphic representation of the various

pins referred to in the following paragraphs. Also, see the pin

diagram on Figure 3 for a depiction of the pin locations on the

package.

PORT D I/O PINS (PTD0:1)

PTD1/TACH1 and PTD0/TACH0/BEMF are special

function, bi-directional I/O port pins that can also be

programmed to be timer pins.

In step motor applications, the PTD0 pin should be

connected to the BEMF output of the analog die, to evaluate

the BEMF signal with a special BEMF module of the MCU.

PORT A I/O PINS (PTA0:4)

These pins are special-function, bidirectional I/O port pins

that are shared with other functional modules in the MCU.

PTA0:PTA4 are shared with the keyboard interrupt pins,

KBD0:KBD4.

PTD1 pin is recommended for use as an output pin for

generating the FGEN signal (PWM signal), if required by the

application.

The PTA5/SPSCK pin is not accessible in this device and

is internally connected to the SPI clock pin of the analog die.

The PTA6/SS pin is likewise not accessible.

PORT E I/O PIN (PTE1)

PTE1/RXD and PTE0/TXD are special function, bi-

directional I/O port pins that can also be programmed to be

enhanced serial communication.

For details refer to the 68HC908EY16 datasheet.

PORT B I/O PINS (PTB1, PTB3:7)

PTE0/TXD is internally connected to the TXD pin of the

analog die. The connection for the receiver must be done

externally.

These pins are special function, bi-directional I/O port pins

that are shared with other functional modules in the MCU. All

pins are shared with the ADC module. The PTB6:PTB7 pins

are also shared with the Timer B module.

EXTERNAL INTERRUPT PIN (IRQ)

PTB0/AD0 is internally connected to the ADOUT pin of the

analog die, allowing diagnostic measurements to be

The IRQ pin is an asynchronous external interrupt pin. This

pin contains an internal pull-up resistor that is always

activated, even when the IRQ pin is pulled LOW.

calculated; e.g., current recopy, V

, etc. The PTB2/AD2

SUP

pin is not accessible in this device.

For details refer to the 68HC908EY16 datasheet.

EXTERNAL RESET PIN (RST)

PORT C I/O PINS (PTC2:4)

A Logic [0] on the RST pin forces the MCU to a known

startup state. RST is bi-directional, allowing a reset of the

entire system. It is driven LOW when any internal reset

source is asserted.

These pins are special function, bi-directional I/O port pins

that are shared with other functional modules in the MCU. For

example, PTC2:PTC4 are shared with the ICG module.

PTC0/MISO and PTC1/MOSI are not accessible in this

device and are internally connected to the MISO and MOSI

SPI pins of the analog die.

This pin contains an internal pull-up resistor that is always

activated, even when the reset pin is pulled LOW.

For details refer to the 68HC908EY16 datasheet.

Input pin for the half-bridge current limitation and the high

side inrush current limiter PWM frequency. This input is not a

CURRENT LIMITATION FREQUENCY INPUT PIN

(FGEN)

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

14

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

real PWM input pin; it should just supply the period of the

PWM. The duty cycle will be generate automatically.

POWER GROUND PINS (GND1 AND GND2)

GND1 and GND2 are device power ground connections.

Owing to the low ON-resistance and current requirements of

the half-bridge driver outputs and high side output driver,

multiple pins are provided.

Important The recommended FGEN frequency should

be in the range of 0.1 kHz to 20 kHz.

GND1 and GND2 pins must be connected to get full chip

functionality.

BACK ELECTROMAGNETIC FORCE OUTPUT PIN

(BEMF)

This pin gives the user information about back

electromagnetic force (BEMF). This feature is mainly used in

step motor applications for detecting a stalled motor. In order

to evaluate this signal the pin must be directly connected to

pin PTD0/TACH0/BEMF.

HIGH SIDE OUTPUT PIN (HS)

The HS output pin is a low R_DS(ON)high side switch. The

switch is protected against over-temperature and over-

current. The output is capable of limiting the inrush current

with an automatic PWM generation using the FGEN module.

RESET PIN (RST_A)

SWITCHABLE VDD OUTPUT PIN (HVDD)

RST_A is the bi-directional reset pin of the analog die. It is

an open drain with pull-up resistor and must be connected to

the RST pin of the MCU.

The HVDD pin is a switchable V_DDoutput for driving

resistive loads requiring a regulated 5.0 V supply; e.g., 3-pin

Hall-effect sensors. The output is short-circuit protected.

INTERRUPT PIN (IRQ_A)

HALL-EFFECT SENSOR INPUT PINS (H1:H3)

IRQ_A is the interrupt output pin of the analog die

indicating errors or wake-up events. It is an open drain with

pull-up resistor and must be connected to the IRQ pin of the

MCU.

The Hall-effect sensor input pins H1:H3 provide inputs for

Hall-effect sensors and switches.

+5.0 V VOLTAGE REGULATOR OUTPUT PIN (VDD)

SLAVE SELECT PIN (SS)

The VDD pin is needed to place an external capacitor to

stabilize the regulated output voltage. The VDD pin is

intended to supply the embedded microcontroller.

This pin is the SPI Slave Select pin for the analog chip. All

other SPI connections are done internally. SS must be

connected to PTB1 or any other logic I/O of the

microcontroller.

Important The VDD pin should not be used to supply

other loads; use the HVDD pin for this purpose. The VDD,

EVDD, VDDA, and VREFH pins must be connected together.

LIN BUS PIN (LIN)

ANALOG INPUT PIN (PA1)

The LIN pin represents the single-wire bus transmitter and

receiver. It is suited for automotive bus systems and is based

on the LIN bus specification.

This pin is an analog input port with selectable current

source values.

HALF-BRIDGE OUTPUT PINS (HB1:HB4)

VOLTAGE REGULATOR GROUND PIN (VSS)

The 908E625 device includes power MOSFETs

configured as four half-bridge driver outputs. The HB1:HB4

outputs may be configured for step motor drivers, DC motor

drivers, or as high side and low-side switches.

The VSS pin is the ground pin for the connection of all non-

power ground connections (microcontroller and sensors).

Important VSS, EVSS, VSSA, and VREFL pins must be

connected together.

The HB1:HB4 outputs are short-circuit and over-

temperature protected, and they feature current recopy,

current limitation, and BEMF generation. Current limitation

and recopy are done on the low side MOSFETs.

LIN TRANSCEIVER OUTPUT PIN (RXD)

This pin is the output of LIN transceiver. The pin must be

connected to the microcontroller’s Enhanced Serial

Communications Interface (ESCI) module (RXD pin).

POWER SUPPLY PINS (VSUP1:VSUP3)

VSUP1:VSUP3 are device power supply pins. The

nominal input voltage is designed for operation from 12 V

systems. Owing to the low ON-resistance and current

requirements of the half-bridge driver outputs and high side

output driver, multiple VSUP pins are provided.

ADC REFERENCE PINS (VREFL AND VREFH)

VREFL and VREFH are the reference voltage pins for the

ADC. It is recommended that a high quality ceramic

decoupling capacitor be placed between these pins.

Important VREFH is the high reference supply for the

ADC and should be tied to the same potential as VDDA via

separate traces. VREFL is the low reference supply for the

All VSUP pins must be connected to get full chip

functionality.

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

ADC and should be tied to the same potential as VSS via

separate traces.

Fast signal transitions on MCU pins place high, short

duration current demands on the power supply. To prevent

noise problems, take special care to provide power supply

bypassing at the MCU.

For details refer to the 68HC908EY16 datasheet.

ADC SUPPLY PINS (VDDA AND VSSA)

VDDA and VSSA are the power supply pins for the analog-

to-digital converter (ADC). It is recommended that a high

quality ceramic decoupling capacitor be placed between

these pins.

TEST PIN (FLSVPP)

This pin is for test purposes only. This pin should be either

left open (not connected) or connected to GND.

Important VDDA is the supply for the ADC and should be

tied to the same potential as EVDD via separate traces.

VSSA is the ground pin for the ADC and should be tied to the

same potential as EVSS via separate traces.

EXPOSED PAD PIN

The exposed pad pin on the bottom side of the package

conducts heat from the chip to the PCB board. For thermal

performance the pad must be soldered to the PCB board. It

is recommended that the pad be connected to the ground

potential.

For details refer to the 68HC908EY16 datasheet.

MCU POWER SUPPLY PINS (EVDD AND EVSS)

EVDD and EVSS are the power supply and ground pins.

The MCU operates from a single power supply.

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

16

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

INTERRUPTS

AUTONOMOUS WATCHDOG INTERRUPT (AWD)

The 908E625 has seven different interrupt sources as

described in the following paragraphs. The interrupts can be

disabled or enabled via the SPI. After reset all interrupts are

automatically disabled.

Refer to Autonomous Watchdog Autonomous Watchdog

(AWD) on page 36.

LIN INTERRUPT

If the LINIE bit is set, a falling edge on the LIN pin will

generate an interrupt. During STOP mode this interrupt will

initiate a system wake-up.

LOW VOLTAGE INTERRUPT

The low voltage interrupt (LVI) is related to the external

supply voltage, V

. If this voltage falls below the LVI

SUP

threshold, it will set the LVI flag. If the low voltage interrupt is

enabled, an interrupt will be initiated.

HALL-EFFECT SENSOR INPUT PIN INTERRUPT

If the PHIE bit is set, the enabled Hall-effect sensor input

pins H1:H3 can generate an interrupt if a current above the

threshold is detected. During Stop mode this interrupt,

combined with the cyclic wake-up feature of the AWD, can

wake up the system. Refer to pin Hall-Effect Sensor Input

Pins (H1:H3).

With LVI the H-Bridges (high side MOSFET only) and the

high side driver are switched off. All other modules are not

influenced by this interrupt.

During STOP mode the LVI circuitry is disabled.

HIGH VOLTAGE INTERRUPT

OVER-CURRENT INTERRUPT

The high voltage interrupt (HVI) is related to the external

supply voltage, V

threshold, it will set the HVI flag. If the high voltage interrupt

is enabled, an interrupt will be initiated.

. If this voltage rises above the HVI

If an over-current condition on a half-bridge occurs, the

high side or the HVDD output is detected and the OCIE bit is

set and an interrupt generated.

SUP

With HVI the H-Bridges (high side MOSFET only) and the

high side driver are switched off. All other modules are not

influenced by this interrupt.

SYSTEM WAKE-UP

System wake-up can be initiated by any of four events:

During STOP mode the HVI circuitry is disabled.

• A falling edge on the LIN pin

• A wake-up signal from the AWD

• A Logic [1] at Hall-effect sensor input pin during cyclic

check via AWD

HIGH TEMPERATURE INTERRUPT

The high temperature interrupt (HTI) is generated by the

on-chip temperature sensors. If the chip temperature is

above the HTI threshold, the HTI flag will be set. If the high

temperature interrupt is enabled, an interrupt will be initiated.

• An LVR condition

If one of these wake-up events occurs and the interrupt

mask bit for this event is set, the interrupt will wake-up the

microcontroller as well as the main voltage regulator (MREG)

(Figure 8).

During STOP mode the HTI circuitry is disabled.

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

MCU Die

Analog Die

From Reset

Initialize

Operate

SPI:

GS =1

STOP MREG

(MREG off)

Wait for Action

LIN

STOP

AWD

Hallport

IRQ

Interrupt?

Assert IRQ_A

SPI: Reason for

Interrupt

Start

MREG

Operate

MREG = Main Voltage

Regulator

Figure 8. STOP Mode/Wake-up Procedure

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

18

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

• MOSI—Master-Out Slave-In

SERIAL SPI INTERFACE

• MISO—Master-In Slave-Out

• SPSCK—Serial Clock

The SPI creates the communication link between the

microcontroller and the 908E625. The interface consists of

four pins. See Figure 9:

A complete data transfer via the SPI consists of 2 bytes.

The master sends address and data, slave system status,

and data of the selected address.

•

SS—Slave Select

SS

Read/Write, Address, Parity

Data (Register write)

R/W

A4

S6

A3

A2

A1

A0

P

X

D7

D6

D5

D4

D3

D2

D1

D0

MOSI

MISO

System Status Register

Data (Register read)

S7

S5

S4

S3

S2

S1

S0

D5

D4

D3

D2

SPSCK

Rising edge of SPSCK

Change MISO/MOSI

Output

Falling edge of SPSCK

Sample MISO/MOSI

Input

Slave latch

register address

Slave latch

data

Figure 9. SPI Protocol

During the inactive phase of SS, the new data transfer is

PARITY P

prepared. The falling edge on the SS line indicates the start

of a new data transfer and puts MISO in the low-impedance

mode. The first valid data are moved to MISO with the rising

edge of SPSCK.

The parity bit is equal to 0 if the number of 1 bits is an even

number contained within R/W, A4:A0. If the number of 1 bits

is odd, P equals 1. For example, if R/W = 1, A4:A0 = 00001,

then P equals 0.

The MISO output changes data on a rising edge of

SPSCK. The MOSI input is sampled on a falling edge of

SPSCK. The data transfer is only valid if exactly 16 sample

clock edges are present in the active phase of SS.

The parity bit is only evaluated during a write operation.

BIT X

Not used.

After a write operation, the transmitted data is latched into

the register by the rising edge of SS. Register read data is

internally latched into the SPI at the time when the parity bit

is transferred. SS HIGH forces MISO to high impedance.

MASTER DATA BYTE

Contains data to be written or no valid data during a read

operation.

A4:A0

SLAVE STATUS BYTE

Contains the address of the desired register.

Contains the contents of the System Status Register ($0c)

independent of whether it is a write or read operation or which

register was selected.

R/W

Contains information about a read or a write operation.

• If R/W = 1, the second byte of master contains no valid

information, slave just transmits back register data.

• If R/W = 0, the master sends data to be written in the

second byte, slave sends concurrently contents of

selected register prior to write operation, write data is

latched in the SMARTMOS register on rising edge of

SS.

SLAVE DATA BYTE

Contains the contents of selected register. During a write

operation it includes the register content prior to a write

operation.

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

19

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

SPI REGISTER OVERVIEW

Table 6 summarizes the SPI register addresses and the

bit names of each register.

Table 6. List of Registers

Bit

Addr

$01

$02

$03

$04

$05

$06

$07

Register Name

R/W

7

6

5

HB3_H

0

4

3

HB2_H

0

2

1

0

R

W

R

H-Bridge Output

(HBOUT)

HB4_H

HB4_L

HB3_L

0

HB2_L

HB1_H

HB1_L

H-Bridge Control

(HBCTL)

OFC_EN

CSA

SRS1

HPIE

CLS2

0

CLS1

0

CLS0

W

R

0

GS

0

System Control

(SYSCTL)

PSON

SRS0

LINIE

W

R

Interrupt Mask

(IMR)

0

HTIE

LVIE

HVIE

OCIE

OCF

W

R

0

Interrupt Flag

(IFR)

HPF

0

LINF

0

HTF

0

LVF

0

HVF

0

W

R

Reset Mask

(RMR)

TTEST

0

HVRE

SS1

HTRE

SS0

W

R

0

Analog Multiplexer

Configuration (ADMUX)

SS3

0

SS2

W

R

Hall-Effect Sensor Input

Pin Control

0

$08

$09

H3EN

H3F

H2EN

H2F

H1EN

H1F

W

R

(HACTL)

Hall-Effect Sensor Input

Pin Status

0

W

(HASTAT)

R

W

R

0

AWD Control

(AWDCTL)

$0a

$0b

$0c

AWDRE

CSSEL0

HS_OCF

AWDIE

AWDCC

AWDF

HVDDON

HB_OCF

AWDR

AWDRST

Power Output

(POUT)

CSSEL1

CSEN1

LVF

CSEN0

HVF

HS_ON

HTF

W

R

LINCL

System Status

(SYSSTAT)

HVDD_OC

F

HP_OCF

W

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

20

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

condition is still present while writing a Logic [1] to HTF, the

writing has no effect. Therefore, a high temperature interrupt

cannot be lost due to inadvertent clearing of HTF. Reset

clears the HTF bit. Writing a Logic [0] to HTF has no effect.

INTERRUPT FLAG REGISTER (IFR)

Register Name and Address: IFR - $05

• 1 = High temperature condition has occurred

• 0 = High temperature condition has not occurred

Bits

Read

Write

Reset

7

0

6

5

4

3

2

1

0

OCF

0

HPF LINF HTF LVF HVF

Low Voltage Flag Bit (LVF)

This read/write flag is set on a low voltage condition. Clear

LVF by writing a Logic [1] to LVF. If a low voltage condition is

still present while writing a Logic [1] to LVF, the writing has no

effect. Therefore, a low voltage interrupt cannot be lost due

to inadvertent clearing of LVF. Reset clears the LVF bit.

Writing a Logic [0] to LVF has no effect.

0

Hall-Effect Sensor Input Pin Flag Bit (HPF)

This read/write flag is set depending on Run/Stop mode.

• 1 = Low voltage condition has occurred

• 0 = Low voltage condition has not occurred

RUN Mode

An interrupt will be generated when a state change on any

enabled Hall-effect sensor input pin is detected. Clear HPF

by writing a Logic [1] to HPF. Reset clears the HPF bit.

Writing a Logic [0] to HPF has no effect.

High Voltage Flag Bit (HVF)

This read/write flag is set on a high voltage condition.

Clear HVF by writing a Logic [1] to HVF. If high voltage

condition is still present while writing a Logic [1] to HVF, the

writing has no effect. Therefore, a high voltage interrupt

cannot be lost due to inadvertent clearing of HVF. Reset

clears the HVF bit. Writing a Logic [0] to HVF has no effect.

• 1 = State change on the hallflags detected

• 0 = No state change on the hallflags detected

STOP Mode

An interrupt will be generated when AWDCC is set and a

current above the threshold is detected on any enabled Hall-

effect sensor input pin. Clear HPF by writing a Logic [1] to

HPF. Reset clears the HPF bit. Writing a Logic [0] to HPF has

no effect.

• 1 = High voltage condition has occurred

• 0 = High voltage condition has not occurred

Over-current Flag Bit (OCF)

This read-only flag is set on an over-current condition.

Reset clears the OCF bit. To clear this flag, write a Logic [1]

to the appropriate over-current flag in the SYSSTAT

Register. See Figure 10,illustrating the three signals

triggering the OCF.

• 1 = One or more of the selected Hall-effect sensor input

pins had been pulled HIGH

• 0 = None of the selected Hall-effect sensor input pins

has been pulled HIGH

• 1 = High current condition has occurred

• 0 = High current condition has not occurred

LIN Flag Bit (LINF)

This read/write flag is set on the falling edge at the LIN

data line. Clear LINF by writing a Logic [1] to LINF. Reset

clears the LINF bit. Writing a Logic [0] to LINF has no effect.

HVDD_OCF

HS_OCF

HB_OCF

OCF

• 1 = Falling edge on LIN data line has occurred

• 0 = Falling edge on LIN data line has not occurred since

last clear

Figure 10. Principal Implementation for OCF

High-Temperature Flag Bit (HTF)

This read/write flag is set on a high temperature condition.

Clear HTF by writing a Logic [1] to HTF. If a high temperature

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

21

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

High Voltage Interrupt Enable Bit (HVIE)

INTERRUPT MASK REGISTER (IMR)

This read/write bit enables CPU interrupts by the high

voltage flag, HVF. Reset clears the HVIE bit.

Register Name and Address: IMR - $04

• 1 = Interrupt requests from HVF flag enabled

• 0 = Interrupt requests from HVF flag disabled

Bits

7

0

6

5

4

3

2

1

0

Read

Write

Reset

HPIE LINIE HTIE LVIE HVIE OCIE

Over-current Interrupt Enable Bit (OCIE)

This read/write bit enables CPU interrupts by the over-

current flag, OCF. Reset clears the OCIE bit.

0

• 1 = Interrupt requests from OCF flag enabled

• 0 = Interrupt requests from OCF flag disabled

Hall-Effect Sensor Input Pin Interrupt Enable Bit (HPIE)

This read/write bit enables CPU interrupts by the Hall-

effect sensor input pin flag, HPF. Reset clears the HPIE bit.

RESET

• 1 = Interrupt requests from HPF flag enabled

• 0 = Interrupt requests from HPF flag disabled

The 908E625 chip has four internal reset sources and one

external reset source, as explained in the paragraphs below.

Figure 11 depicts the internal reset sources.

LIN Line Interrupt Enable Bit (LINIE)

RESET INTERNAL SOURCES

Autonomous Watchdog

This read/write bit enables CPU interrupts by the LIN flag,

LINF. Reset clears the LINIE bit.

• 1 = Interrupt requests from LINF flag enabled

• 0 = Interrupt requests from LINF flag disabled

AWD modules generates a reset because of a timeout

(watchdog function).

High Temperature Interrupt Enable Bit (HTIE)

High Temperature Reset

This read/write bit enables CPU interrupts by the high

temperature flag, HTF. Reset clears the HTIE bit.

To prevent damage to the device, a reset will be initiated if

the temperature rises above a certain value. The reset is

maskable with bit HTRE in the reset mask register. After a

reset the high temperature reset is disabled.

• 1 = Interrupt requests from HTF flag enabled

• 0 = Interrupt requests from HTF flag disabled

Low Voltage Interrupt Enable Bit (LVIE)

Low Voltage Reset

This read/write bit enables CPU interrupts by the low

voltage flag, LVF. Reset clears the LVIE bit.

The LVR is related to the internal V . In case the voltage

falls below a certain threshold, it will pull down the RST_A pin.

DD

• 1 = Interrupt requests from LVF flag enabled

• 0 = Interrupt requests from LVF flag disabled

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

22

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

SPI REGISTERS

AWDRE Flag

HVRE Flag

AWD Reset

Sensor

VDD

High-Voltage

Reset Sensor

HTRE Flag

High-Temperature

Reset Sensor

RST_A

MONO

FLOP

Low-Voltage Reset

Figure 11. Internal Reset Routing

High-Voltage Reset

High Temperature Reset Test (TTEST)

The HVR is related to the external V

voltage. In case

This read/write bit is for test purposes only. It decreases

the over-temperature shutdown limit for final test. Reset

clears the HTRE bit.

SUP

the voltage is above a certain threshold, it will pull down the

RST_A pin. The reset is maskable with bit HVRE in the Reset

Mask Register. After a reset the high voltage reset is

disabled.

• 1 = Low temperature threshold enabled

• 0 = Low temperature threshold disabled

RESET EXTERNAL SOURCE

External Reset Pin

High Voltage Reset Enable Bit (HVRE)

This read/write bit enables resets on high voltage

conditions. Reset clears the HVRE bit.

The microcontroller has the capability of resetting the

SMARTMOS device by pulling down the RST pin.

• 1 = High voltage reset enabled

• 0 = High voltage reset disabled

RESET MASK REGISTER (RMR)

High Temperature Reset Enable Bit (HTRE)

This read/write bit enables resets on high temperature

conditions. Reset clears the HTRE bit.

Register Name and Address: RMR - $06

• 1 = High temperature reset enabled

• 0 = High temperature reset disabled

Bits

Read

Write

Reset

7

TTEST

0

6

5

4

3

2

1

0

HVRE HTRE

0

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

23

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Analog Multiplexer/ADOUT Pin

ANALOG DIE I/OS

LIN Physical Layer

The ADOUT pin is the analog output interface to the ADC

of the MCU. See Figure 12. An analog multiplexer is used to

read seven internal diagnostic analog voltages.

The LIN bus pin provides a physical layer for single-wire

communication in automotive applications. The LIN physical

layer is designed to meet the LIN physical layer specification.

Current Recopy

The LIN driver is a low side MOSFET with internal current

limitation and thermal shutdown. An internal pull-up resistor

with a serial diode structure is integrated, so no external pull-

up components are required for the application in a slave

node. The fall time from dominant to recessive and the rise

time from recessive to dominant is controlled. The symmetry

between both slew rate controls is guaranteed.

The analog multiplexer is connected to the four low side

current sense circuits of the half-bridges. These sense

circuits offer a voltage proportional to the current through the

low side MOSFET. High or low resolution is selectable: 5.0 V/

2.5 A or 5.0 V/500 mA, respectively. Refer to Half-Bridge

Current Recopy on page 32.)

Analog Input PA1

The LIN pin offers high susceptibility immunity level from

external disturbance, guaranteeing communication during

external disturbance.

The analog input PA1 is directly connected to the analog

multiplexer, permitting analog values from the periphery to be

read.

The LIN transmitter circuitry is enabled by setting the

PSON bit in the System Control Register (SYSCTL). If the

transmitter works in the current limitation region, the LINCL

bit in the System Status Register (SYSSTAT) is set. Due to

excessive power dissipation in the transmitter, software is

advised to monitor this bit and turn the transmitter off

immediately.

TEMPERATURE SENSOR

The 908E625 includes an on-chip temperature sensor.

This sensor offers a voltage that is proportional to the actual

chip junction temperature.

V

PRESCALER

SUP

TXD PIN

The V

prescaler permits the reading or measurement

SUP

The TXD pin is the MCU interface to control the state of the

LIN transmitter (see Figure 1). When TXD is LOW, LIN output

is low (dominant state). When TXD is HIGH, the LIN output

MOSFET is turned off. The TXD pin has an internal pull-up

current source in order to set the LIN bus in recessive state

in the event, for instance, the microcontroller could not control

it during system power-up or power-down.

of the external supply voltage. The output of this voltage is

V_SUP/RATIO_VSUP

.

The different internal diagnostic analog voltages can be

selected with the ADMUX Register.

ANALOG MULTIPLEXER CONFIGURATION

REGISTER (ADMUX)

RXD PIN

Register Name and Address: ADMUX - $07

The RXD transceiver pin is the MCU interface, which

reports the state of the LIN bus voltage. LIN HIGH (recessive

state) is reported by a high level on RXD, LIN LOW (dominant

state) by a low level on RXD.

Bits

Read

Write

Reset

7

0

6

0

5

0

4

0

3

2

1

0

SS3 SS2 SS1 SS0

STOP MODE/WAKE-UP FEATURE

0

During STOP mode operation the transmitter of the

physical layer is disabled. The receiver pin is still active and

able to detect wake-up events on the LIN bus line.

SS3, SS2, SS1, and SS0—A/D Input Select Bits

If LIN interrupt is enabled (LINIE bit in the Interrupt Mask

Register is set), a falling edge on the LIN line causes an

interrupt. This interrupt switches on the main voltage

regulator and generates a system wake-up.

These read/write bits select the input to the ADC in the

microcontroller according to Table 7. Reset clears SS3, SS2,

SS1, and SS0 bits.

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

24

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

ANALOG INPUT PA1

Table 7. Analog Multiplexer Configuration Register

The Analog input PA1 pin provides an input for reading

analog signals and is internally connected to the analog

multiplexer. It can be used for reading switches,

potentiometers or resistor values, etc.

SS3

0

SS2

0

SS1

0

SS0

0

Channel

Current Recopy HB1

Current Recopy HB2

Current Recopy HB3

Current Recopy HB4

V_SUPPrescaler

0

1

ANALOG INPUT PA1 CURRENT SOURCE

0

1

0

The analog input PA1 has an additional selectable current

source. It enables the reading of switches, NTC, etc., without

the need of an additional supply line for the sensor illustrated

in Figure 12. With this feature it is also possible to read

multiple switches on one input.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Temperature Sensor

Not Used

Current source is enabled if the PSON bit in the System

Control Register (SYSCTL) and the CSEN bit in the Power

Output Register (POUT) is set.

PA1 Pin

Four different current source values can be selected with the CSSELx bits

shown in Table 8. This function ceases during STOP mode operation.

Table 8. PA1 Current Source Level Selection Bits

CSSEL1 CSSEL0

Current Source Enable (typ.)

Not Used

0

1

0

1

0

1

10%

30%

60%

100%

Source Selection Bits

SSx

VDD

3

Selectable

Current

CSSEL

Source

PSON

CSEN

Analog

Multiplexer

ADOUT

PA1

Analog Input PA1

NTC

Figure 12. Analog Input PA1 and Multiplexer

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

25

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

• 1 = Lamp driver enabled

• 0 = Lamp driver disabled

POWER OUTPUT REGISTER (POUT)

Register Name and Address: POUT - $0b

Hall-Effect Sensor Input Pins (H1:H3)

Function

Bits

Read

Write

Reset

Notes

7

6

5

4

3

2

1

0

0⁽¹⁶⁾

The Hall-effect sensor input pins provide three inputs for

two-pin Hall-effect sensors for detecting stall and position or

reading Hall-effect sensor contact switches. The Hall-effect

sensor input pins are not influenced by the PSON bit in the

System Control Register.

CSSEL1 CSSEL0 CSEN

HVDDON HS_ON

0

Each pin of the Hall-effect sensor can be enabled by

setting the HxEN bit in the Hall-effect sensor input pin control

register (HACTL). If the pins are enabled, the Hall-effect

sensors are supplied with V_SUPvoltage and the sense

circuitry is working. An internal clamp circuity limits the supply

voltage to the sensor to 15 V. This sense circuitry monitors

the current to VSS. The result of this sense operation is given

by the HxF flags in the Hall-effect sensor input pin status

register (HASTAT).

16. This bit must always be set to 0.

Current Source Select Bits (CSSEL0:CSSEL1)

These read/write bits select the current source values.

Reset clears the CSSEL0:CSSEL1 bits.

Current Source Enable Bit (CSEN)

This read/write bit enables the current source for PA1.

Reset clears the CSEN bit (Table 9).

The flag is set if the sensed current is higher than I

.

HSCT

To prevent noise on this flag, a hysteresis is implemented on

these pins.

Table 9. PA1 Current Source Enable Bit

After switching on the Hall-effect sensor input pins (HxEN

= 1), the Hall-effect sensors need some time to stabilize the

output. In RUN mode the software must wait at least 40 μs

between enabling the Hall-effect sensor and reading the hall

flag.

CSEN

Current Source Enable

Current Source Off

Current Source On

0

1

HVDD On Bit (HVDDON)

The Hall-effect sensor input pin works in an dynamic

output voltage range from V_SUPdown to 2.0 V. Below 2.0 V

the hallflags are not functional anymore. If the output voltage

is below a certain threshold, the Hall-effect sensor input pin

over-current flag (HP_OCF) in the system status register is

set.

This read/write bit enables HVDD output. Reset clears the

HVDDON bit.

• 1 = HVDD enabled

• 0 = HVDD disabled

Figures 13 through 15 illustrate the connections to the

Hall-effect input sensors.

Lamp Driver On Bit (HS_ON)

This read/write bit enables the Lamp driver. Reset clears

the HS_ON bit.

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

26

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

HxEN

Two-Terminal Hall-Effect Sensor

Hx

Sense

Circuitry

HxF

GND

V

Figure 13. Hall-effect Sensor Input Pin Connected to Two Pin Hall-effect Sensor

HxEN

Rv

Hx

Sense

Circuitry

HxF

GND

V

Figure 14. Hall-effect Sensor Input Pin Connected to Local Switch

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

27

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Three-Terminal Hall-Effect Sensor

Vs

HxEN

Hx

Out

Sense

Circuitry

HxF

GND

V

Figure 15. Hall-effect Sensor Input Pin Connected to Three Pin Hall-effect Sensor

CYCLIC WAKE-UP

Interrupts

The Hall-effect sensor inputs can be used to wake up the

The Hall-effect sensor input pins are interrupt capable.

system. This wake-up function is provided by the cyclic check

wake-up feature of the AWD (Autonomous Watchdog).

How and when an interrupt occurs is dependent on the

operating mode, RUN or Stop.

If the cyclic check wake-up feature is enabled (AWDCC bit

is set), the AWD switches on the enabled Hall-effect sensor

pins periodically. To ensure that the Hall-effect sensor current

is stabilized after switching on, the inputs are sensed after

RUN Mode

In RUN mode the Hall-effect sensor input pin interrupt flag

(HPF) will be set if a state change on the hallflags (HxF) is

detected. The interrupt is maskable with the HPIE bit in the

interrupt mask register. Before enabling the interrupt, the flag

should be cleared in order to prevent a wrong interrupt.

~40 μs. If a 1 is detected (I

> I

) and the

HSCT

Hall sensor

interrupt mask bit HPIE is set, an interrupt is performed. This

wakes up the MCU and starts the main voltage regulator.

The wake-up function via this input is available when all

three conditions exist:

STOP Mode

• The two-pin Hall-effect sensor input is enabled

(HxEN = 1)

In STOP mode the Hall-effect sensor input pins are

disabled independent of the state of the HxEN flags.

• The cyclic wake-up of the AWD is enabled (AWDCC =

1); see Figure 16

• The Hall-effect sensor input pin interrupt is enabled

(HPIE = 1)

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

28

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

SPI:

AWDCC = 1

GS = 1

SPI Command

STOP

MREG

No

AWD

Timer Overflow?

STOP

Yes

No

Switch on

Selected Hallport

IRQ?

Yes

SPI:

Wait 40 µs

Reason for Wakeup

Yes

Operate

Assert IRQ_A

Hallport = 1

No

Switch off

Selected Hallport

MREG = Main Voltage

Regulator

Figure 16. Hall-effect Sensor Input Pin Cyclic Check Wake-up Feature

HALL-EFFECT SENSOR INPUT PIN CONTROL

REGISTER (HACTL)

HALL-EFFECT SENSOR INPUT PIN STATUS

REGISTER (HASTAT)

Register Name and Address: HACTL - $08

Register Name and Address: HASTAT - $09

Bits

Read

Write

Reset

7

6

5

4

3

2

1

0

Bits

Read

Write

Reset

7

6

5

4

3

2

1

0

H3F H2F H1F

H3EN H2EN H1EN

0

Hall-Effect Sensor Input Pin Enable Bits (H3EN:H1EN)

Hall-Effect Sensor Input Pin Flag Bits (H3F:H1F)

These read/write bits enable the Hall-effect sensor input

pins. Reset clears the H3EN:H1EN bits.

These read-only flag bits reflect the input Hx while the Hall-

effect sensor input pin Hx is enabled (HxEN = 1). Reset

clears the H3F:H1F bits.

• 1 = Hall-effect sensor input pin Hx switched on and

sensed

• 0 = Hall-effect sensor input pin Hx disabled

• 1 = Hall-effect sensor input pin current above threshold

• 0 = Hall-effect sensor input pin current below threshold

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

29

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

HB1:HB4 output features:

HALF-BRIDGES

• Short-circuit (over-current) protection on high side and

low side MOSFETs

• Current recopy feature (low side MOSFET)

• Over-temperature protection

• Over-voltage and under-voltage protection

• Current limitation feature (low side MOSFET)

Outputs HB1:HB4 provide four low-resistive half-bridge

output stages. The half-bridges can be used in H-Bridge, high

side, or low side configurations.

Reset clears all bits in the H-Bridge output register

(HBOUT) owing to the fact that all half-bridge outputs are

switched off.

VSUP

On/Off

High Side Driver

Charge Pump,

OVer-temperature Protection,

OVer-current Protection

Status

BEMF

Control

HBx

On/Off

Status

Low Side Driver

Current Recopy,

Current Limitation,

OVer-current Protection

Current

Limit

GND

Figure 17. Half-bridge Push-Pull Output Driver

HALF-BRIDGE CONTROL

HALF-BRIDGE OUTPUT REGISTER (HBOUT)

Each output MOSFET can be controlled individually. The

general enable of the circuitry is done by setting PSON in the

system control register (SYSCTL). HBx_L and HBx_H form

one half-bridge. It is not possible to switch on both MOSFETs

in one half-bridge at the same time. If both bits are set, the

high-side MOSFET has a higher priority.

Register Name and Address: HBOUT - $01

Bits

7

6

5

4

3

2

1

0

Read HB4_ HB4_ HB3_ HB3_ HB2_ HB2_ HB1_ HB1_

H

0

L

0

H

0

L

0

H

0

L

0

H

0

L

0

To avoid both MOSFETs (high side and low side) of one

half-bridge being on at the same time, a break-before-make

circuit exists. Switching the high side MOSFET on is inhibited

Write

Reset

as long as the potential between gate and V is not below a

SS

certain threshold. Switching the low side MOSFET on is

blocked as long as the potential between gate and source of

the high-side MOSFET did not fall below a certain threshold.

Low Side On/Off Bits (HBx_L)

These read/write bits turn on the low side MOSFETs.

Reset clears the HBx_L bits.

• 1 = Low side MOSFET turned on for half-bridge output x

• 0 = Low side MOSFET turned off for half-bridge output x

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

30

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

High Side On/Off Bits (HBx_H)

and the load characteristics. The FGEN input provides the

PWM frequency, whereas the duty cycle is controlled by the

load characteristics.

These read/write bits turn on the high side MOSFETs.

Reset clears the HBx_H bits.

The recommended frequency range for the FGEN and the

PWM is 0.1 kHz to 20 kHz.

• 1 = High side MOSFET turned on for half-bridge output

x

• 0 = High side MOSFET turned on for half-bridge output

x

Functionality

Each low side MOSFET switches off if a current above the

selected current limit was detected. The 908E625 offers five

different current limits. Refer to Table 10 for current limit

values. The low side MOSFET switches on again if a rising

edge on the FGEN input was detected (Figure 18).

HALF-BRIDGE CURRENT LIMITATION

Each low side MOSFET offers a current limit or constant

current feature. This features is realized by a pulse width

modulation on the low side MOSFET. The pulse width

modulation on the outputs is controlled by the FGEN input

H-Bridge low-side

MOSFET will be switched

off if select current limit is

reached.

Coil Current

H-Bridge low-side

MOSFET will be turned on

with each rising edge of

the FGEN input.

t

Half-Bridge

Low-Side Output

FGEN Input

(MCU PWM

Signal)

Minimum 50 μs

Figure 18. Half-bridge Current Limitation

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

31

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

and HB4 will switch on the low side MOSFETs with the falling

edge on the FGEN input. In step motor applications this

feature allows the reduction of EMI due to a reduction of the

di/dt (Figure 19).

OFFSET CHOPPING

If bit OFC_EN in the H-Bridge control register (HBCTL) is

set, HB1 and HB2 will continue to switch on the low side

MOSFETs with the rising edge of the FGEN signal and HB3

Coil1 Current

Coil2 Current

FGEN Input

(MCU PWM

Signal)

HB1

Coil1…..

HB2

HB3

Coil2…..

HB4

Current in

VSUP Line

Figure 19. Offset Chopping for Step Motor Control

HALF-BRIDGE CURRENT RECOPY

HALF-BRIDGE BEMF GENERATION

Each low side MOSFET has an additional sense output to

allow a current recopy feature. This sense source is internally

connected to a shunt resistor. The drop voltage is amplified

and switched to the analog multiplexer.

The BEMF output is set to 1 if a recirculation current is

detected in any half-bridge. This recirculation current flows

via the two freewheeling diodes of the power MOSFETs. The

BEMF circuitry detects that and generates a HIGH on the

BEMF output as long as a recirculation current is detected.

This signal provides a flexible and reliable detection of stall in

step motor applications. For this the BEMF circuitry takes

advantage of the instability of the electrical and mechanical

behavior of a step motor when blocked. In addition the signal

can be used for open load detection (absence of this signal),

see Figure 20.

The factor for the current sense amplification can be

selected via bit CSA in the system control register.

• CSA = 1: Low resolution selected (500 mA

measurement range)

• CSA = 0: High resolution selected (2.5 A measurement

range)

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

32

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

Coil Current

1

Voltage on

1

BEMF Signal

Figure 20. BEMF Signal Generation

The over-voltage/under-voltage status flags are cleared

(and the outputs re-enabled) by writing a Logic [1] to the LVF/

HVF flags in the interrupt flag register or by reset. Clearing

this flag is useless as long as a high or low voltage condition

is present.

HALF-BRIDGE OVER-TEMPERATURE

PROTECTION

The half-bridge outputs provide an over-temperature pre-

warning with the HTF in the Interrupt Flag Register (IFR). In

order to protect the outputs against over-temperature, the

high temperature reset must be enabled. If this value is

reached, the part generates a reset and disables all power

outputs.

HALF-BRIDGE CONTROL REGISTER (HBCTL)

Register Name and Address: HBCTL - $02

HALF-BRIDGE OVER-CURRENT PROTECTION

Bits

7

6

5

4

3

2

1

0

The half-bridges are protected against short to GND, short

to VSUP, and load shorts.

0

Read

Write

Reset

OFC_EN CSA

CLS2 CLS1 CLS0

In the event an over-current on the high side is detected,

the high side MOSFETs on all HB high side MOSFETs are

switched off automatically. In the event an over-current on the

low side is detected, all HB low side MOSFETs are switched

off automatically. In both cases the over-current status flag

HB_OCF in the system status register (SYSSTAT) is set.

0

H-Bridge Offset Chopping Enable Bit (OFC_EN)

This read/write bit enables offset chopping. Reset clears

the OFC_EN bit.

The over-current status flag is cleared (and the outputs re-

enabled) by writing a Logic [1] to the HB_OCF flag in the

System status register or by reset.

• 1 = Offset chopping enabled

• 0 = Offset chopping disabled

HALF-BRIDGE OVER-VOLTAGE/UNDER-

VOLTAGE

H-Bridges Current Sense Amplification Select Bit (CSA)

This read/write bit selects the current sense amplification

of the H-Bridges. Reset clears the CSA bit.

The half-bridge outputs are protected against under-

voltage and over-voltage conditions. This protection is done

by the low and high voltage interrupt circuitry. If one of these

flags (LVF, HVF) is set, the outputs are automatically

disabled.

• 1 = Current sense amplification set for measuring 0.5 A.

• 0 = Current sense amplification set for measuring 2.5 A.

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

33

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

H-Bridge Current Limitation Selection Bits (CLS2:CLS0)

HIGH SIDE DRIVER

The high side output is a low-resistive high side switch

targeted for driving lamps. The high side is protected against

over-temperature. To limit the high inrush current of bulbs,

over-current protection circuitry is used to limit the current.

The output is enabled with bit PSON in the system control

register and can be switched on/off with bit HS_ON in the

power output register. Figure 21 depicts the high-side switch

circuitry and connection to external lamp.

These read/write bits select the current limitation value

according to Figure 10. Reset clears the CLS2:CLS0 bits.

Table 10. H-Bridge Current Limitation Value Selection

Bits

CLS2

CLS1

CLS0

Current Limit

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No Limit

HIGH-SIDE OVER-VOLTAGE/UNDER-VOLTAGE

PROTECTION

The high side output pin, HS, is protected against under-

voltage/over-voltage conditions. This protection is done by

the low and high voltage interrupt circuitry. If one of these

flags (LVF, HVF) is set, the output is disabled.

55 mA (typ)

260 mA (typ)

370 mA (typ)

550 mA (typ)

740 mA (typ)

The over-voltage/under-voltage status flags are cleared

and the output re-enabled by writing a Logic [1] to the LVF/

HVF flags in the interrupt flag register or by reset. Clearing

this flag is useless as long as a high or low voltage condition

is present.

VSUP

On/Off

Status

High Side Driver

Charge Pump,

OVer-current Protection,

Inrush Current Limiter

Control

Current

Limit

HS

Figure 21. High Side Circuitry

inrush. If an PWM frequency is supplied to the FGEN output

during the switching on of a bulb, the inrush current is limited

to the over-current shutdown limit. This means if the current

reaches the over-current shutdown, the high side will be

switched off, but each rising edge on the FGEN input will

enable the driver again.

HIGH SIDE OVER-TEMPERATURE PROTECTION

The high side output provides an over-temperature pre-

warning with the HTF in the interrupt flag register. In order to

protect the output against over-temperature, the high-

temperature reset must be enabled. If this value is reached,

the part generates a reset and disables all power outputs.

To distinguish between a shutdown due to an inrush

current or a real shutdown, the software must check if the

over-current status flag (HS_OCF) in the System Status

Register is set beyond a certain period of time. The over-

current status flag is cleared by writing a Logic [1] to the

HS_OCF in the System Status Register, see Figure 22.

HIGH-SIDE OVER-CURRENT PROTECTION

The high side output is protected against over-current. In

the event over-current limit is or was reached, the output

automatically switches off and the over-current flag is set.

Due to the high inrush current of bulbs, a special feature of

the 908E625 prevents an over-current shutdown during this

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

34

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

HS Current

HS Over-current Shutdown Threshold

t

FGEN Input

(MCU PWM

Signal)

t

Figure 22. Inrush Current Limiter on High Side Output

SWITCHABLE VDD OUTPUT (HVDD)

SYSTEM CONTROL REGISTER (SYSCTL)

The HVDD pin is a switchable VDD output pin. It can be

used for driving external circuitry that requires a V voltage.

DD

Register Name and Address: SYSCTL - $03

The output is enabled with bit PSON in the system control

register and can be switched on/off with bit HVDDON in the

power output register. Low or high voltage conditions (LVI/

HVI) have no influence on this circuitry.

Bits

7

6

5

4

3

2

1

0

Read

Write

Reset

PSON SRS1 SRS0

GS

0

HVDD OVER-TEMPERATURE PROTECTION

0

Over-temperature protection is enabled if the high

temperature reset is enabled.

Power Stages On Bit (PSON)

This read/write bit enables the power stages (half-bridges,

high side, LIN transmitter, Analog Input PA1 current sources,

and HVDD output). Reset clears the PSON bit.

HVDD OVER-CURRENT PROTECTION

The HVDD output is protected against over-current. In the

event the over-current limit is or was reached, the output

automatically switches off and the HVDD over-current flag in

the system status register is set.

• 1 = Power stages enabled.

• 0 = Power stages disabled.

LIN Slew Rate Selection Bits (SRS0:SRS1)

These read/write bits enable the user to select the

appropriate LIN slew rate for different baud rate

configurations as shown in Table 11.

The high speed slew rates are used, for example, for

programming via the LIN and are not intended for use in the

application.

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

35

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

HVDD_OCF bit. Writing a Logic [0] to HVDD_OCF has no

effect.

Table 11. LIN Slew Rate Selection Bits

SRS1

SRS0

LIN Slew Rate

Initial Slew Rate (20 kBaud)

Slow Slew Rate (10 kBaud)

High Speed II (8x)

•1 = Over-current condition on HVDD has occurred

•0 = No over-current condition on HVDD has occurred

0

1

0

1

0

1

High Side Over-current Flag Bit (HS_OCF)

This read/write flag is set on an over-current condition at

the high side driver. Clear HS_OCF and enable the high side

driver by writing a Logic [1] to HS_OCF. Reset clears the

HS_OCF bit. Writing a Logic [0] to HS_OCF has no effect.

High Speed I (4x)

Go to STOP Mode Bit (GS)

• 1 = Over-current condition on high side drivers has

This write-only bit instructs the 908E625 to power down

and go into Stop mode. Reset or CPU interrupt requests clear

the GS bit.

occurred

• 0 = No over-current condition on high side drivers has

occurred

• 1 = Power down and go into Stop mode

• 0 = Not in STOP mode

Low Voltage Bit (LVF)

This read only bit is a copy of the LVF bit in the Interrupt

Flag Register.

SYSTEM STATUS REGISTER (SYSSTAT)

• 1 = Low voltage condition has occurred

• 0 = No low voltage condition has occurred

Register Name and Address: SYSSTAT - $0c

Bits

7

6

5

4

3

2

1

0

High Voltage Sensor Bit (HVF)

Read

Write

Reset

LINCL

LVF

HVF

HTF

This read-only bit is a copy of the HVF bit in the Interrupt

Flag Register.

HP_

OCF

HVDD HS_

_OCF OCF

HB_

OCF

• 1 = High voltage condition has occurred

• 0 = No high voltage condition has occurred

0

Hall-Effect Sensor Input Pin Over-current Flag Bit

(HP_OCF)

H-Bridge Over-current Flag Bit (HB_OCF)

This read/write flag is set on an over-current condition at

the H-Bridges. Clear HB_OCF and enable the H-Bridge

driver by writing a Logic [1] to HB_OCF. Reset clears the

HB_OCF bit. Writing a Logic [0] to HB_OCF has no effect.

This read/write flag is set on an over-current condition at

one of the Hall-effect sensor input pins. Clear HP_OCF and

enable the output by writing a Logic [1] to the HP_OCF flag.

Reset clears the HP_OCF bit. Writing a Logic [0] to HP_OCF

has no effect.

• 1 = Over-current condition on H-Bridges has occurred

• 0 = No over-current condition on H-Bridges has

occurred

• 1 = Over-current condition on Hall-effect sensor input

pin has occurred

• 0 = No over-current condition on Hall-effect sensor input

pin has occurred

Over-temperature Status Bit (HTF)

This read-only bit is a copy of the HTF bit in the Interrupt

Flag Register.

LIN Current Limitation Bit (LINCL)

• 1 = Over-temperature condition has occurred

• 0 = No over-temperature condition has occurred

This read-only bit is set if the LIN transmitter operates in

current limitation region. Due to excessive power dissipation

in the transmitter, software is advised to turn the transmitter

off immediately.

AUTONOMOUS WATCHDOG (AWD)

•1 = Transmitter operating in current limitation region

•0 = Transmitter not operating in current limitation region

The Autonomous Watchdog module consists of three

functions:

• Watchdog function for the CPU in RUN mode

• Periodic interrupt function in STOP mode

• Cyclic wake-up function in STOP mode

HVDD Output Over-current Flag Bit (HVDD_OCF)

This read/write flag is set on an over-current condition at

the HVDD pin. Clear HVDD_OCF and enable the output by

writing a Logic [1] to the HVDD_OCF Flag. Reset clears the

The AWD is enabled if AWDIE, AWDRE, or AWDCC in the

AWDCTL Register is set. If these bits are cleared, the AWD

oscillator is disabled and the watchdog switched off.

The watchdog function is only available in RUN mode. On

setting the AWDRE bit, watchdog functionality in RUN mode

WATCHDOG

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

36

FUNCTIONAL DEVICE OPERATION

LOGIC COMMANDS AND REGISTERS

is activated. Once this function is enabled, it is not possible to

disable it via software.

Autonomous Watchdog Reset Enable Bit (AWDRE)

This read/write bit enables resets on AWD timeouts. A

reset on the RST_A is only asserted when the device is in

RUN mode. AWDRE is one time setable (write once) after

each reset. Reset clears the AWDRE bit.

If the timer reaches end value and AWDRE is set, a

system reset is initiated. Operations of the watchdog function

cease in STOP mode. Normal operation will be continued

when the system is back to RUN mode.

• 1 = Autonomous watchdog enabled

• 0 = Autonomous watchdog disabled

To prevent a watchdog reset, the watchdog timeout

counter must be reset before it reaches the end value. This is

done by a write to the AWDRST bit in the AWDCTL Register.

Autonomous Watchdog Interrupt Enable Bit (AWDIE)

This read/write bit enables CPU interrupts by the

Autonomous Watchdog timeout flag, AWFD. IRQ_A is only

asserted when the device is in STOP mode. Reset clears the

AWDIE bit.

PERIODIC INTERRUPT

Periodic interrupt is only available in STOP mode. It is

enabled by setting the AWDIE bit in the AWDCTL Register. If

AWDIE is set, the AWD wakes up the system after a fixed

period of time. This time period can be selected with bit

AWDR in the AWDCTL Register.

• 1 = CPU interrupt requests from AWDF enabled

• 0 = CPU interrupt requests from AWDF disabled

Autonomous Watchdog Cyclic Check (AWDCC)

CYCLIC WAKE-UP

This read/write bit enables the cyclic check of the two pin

Hall-effect sensor and the analog inputs. Reset clears the

AWDCC bit.

The cyclic wake-up feature is only available in STOP

mode. If this feature is enabled, the selected Hall-effect

sensor input pins are switched on and sensed. If a “1” is

detected on one of these inputs and the interrupt for the Hall-

effect sensors is enabled, a system wake-up is performed.

(Switch on main voltage regulator and assert IRQ_A to the

microcontroller).

• 1 = Cyclic check of the Hall-effect sensor and analog

port

• 0 = No cyclic check of the Hall-effect sensor and analog

port

Autonomous Watchdog Timeout Flag Bit (AWDF)

AUTONOMOUS WATCHDOG CONTROL

REGISTER (AWDCTL)

This read/write flag is set when the Autonomous

Watchdog has timed out. Clear AWDF by writing a Logic [1]

to AWDF. Clearing AWDF also resets the AWD counter and

starts a new timeout period. Reset clears the AWDF bit.

Writing a Logic [0] to AWDF has no effect.

Register Name and Address: AWDCTL - $0a

Bits

7

6

5

4

3

2

1

AWDF

0

• 1 = AWD has timed out

• 0 = AWD has not yet timed out

0

Read

Write

AWDR AWDI

AWDC

C

AWD

R

E

AWDRS

T

Autonomous Watchdog Rate Bit (AWDR)

0

Reset

This read/write bit selects the clock rate of the

Autonomous Watchdog. Reset clears the AWDR bit.

Autonomous Watchdog Reset Bit (AWDRST)

• 1 = Fast rate selected (10 ms)

• 0 = Slow rate selected (20 ms)

This write-only bit resets the Autonomous Watchdog

timeout period. AWDRST always reads 0. Reset clears

AWDRST bit.

VOLTAGE REGULATOR

• 1 = Reset AWD and restart timeout period

• 0 = No effect

The 908E625 chip contains a low power, low drop voltage

regulator to provide internal power and external power for the

MCU. The on-chip regulator consist of two elements, the

main voltage regulator and the low voltage reset circuit.

The V regulator accepts a unregulated input supply and

DD

provides a regulated V_DDsupply to all digital sections of the

device. The output of the regulator is also connected to the

VDD pin to provide the 5.0 V to the microcontroller.

RUN Mode

During RUN mode the main voltage regulator is on. It

provides a regulated supply to all digital sections.

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

37

FUNCTIONAL DEVICE OPERATION

FACTORY TRIMMING AND CALIBRATION

STOP Mode

very limited output current capability. The output voltage will

be lower than the output voltage of the main voltage

regulator.

During STOP mode the STOP mode regulator supplies a

regulated output voltage. The STOP mode regulator has a

FACTORY TRIMMING AND CALIBRATION

To enhance the ease-of-use of the 908E625, various

parameters (e.g. ICG trim value) are stored in the flash

memory of the device. The following flash memory locations

are reserved for this purpose and might have a value different

from the empty (0xFF) state:

Internal Clock Generator (ICG) Trim Value

The internal clock generator (ICG) module is used to

create a stable clock source for the microcontroller without

using any external components. The untrimmed frequency of

the low frequency base clock (IBASE), will vary as much as

±25 percent due to process, temperature, and voltage

dependencies. To compensate this dependencies a ICG trim

values is located at address $FDC2. After trimming the ICG

is a range of typ. ±2% (±3% max.) at nominal conditions

•0xFD80:0xFDDF Trim and Calibration Values

•0xFFFE:0xFFFF Reset Vector

In the event the application uses these parameters, one

has to take care not to erase or override these values. If these

parameters are not used, these flash locations can be erased

and otherwise used.

(filtered (100 nF) and stabilized (4,7 μF) V = 5.0 V,

DD

T

~25 °C) and will vary over temperature and voltage

AMBIENT

(V ) as indicated in the 68HC908EY16 datasheet.

DD

To trim the ICG this values has to be copied to the ICG

Trim Register ICGTR at address $38 of the MCU.

Trim Values

Below the usage of the trim values located in the flash

memory is explained

Important The value has to copied after every reset.

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

38

TYPICAL APPLICATIONS

FACTORY TRIMMING AND CALIBRATION

TYPICAL APPLICATIONS

DEVELOPMENT SUPPORT

As the 908E625 has the MC68HC908EY16 MCU

The programming is principally possible at two stages in

the manufacturing process - first on chip level, before the IC

is soldered onto a pcb board and second after the IC is

soldered onto the pcb board.

embedded typically all the development tools available for

the MCU also apply for this device, however due to the fact

of the additional analog die circuitry and the nominal +12 V

supply voltage some additional items have to be considered:

Chip level programming

• nominal 12 V rather than 5.0 V or 3.0 V supply

• high voltage V

but IRQ_A pin

might be applied not only to IRQ pin,

On Chip level the easiest way is to only power the MCU

with +5.0 V (see Figure 23) and not to provide the analog

chip with VSUP, in this setup all the analog pin should be left

open (e.g. VSUP[1:3]) and interconnections between MCU

and analog die have to be separated (e.g. IRQ - IRQ_A).

TST

For a detailed information on the MCU related

development support see the MC68HC908EY16 datasheet -

section development support.

This mode is well described in the MC68HC908EY16

datasheet - section development support.

VSUP[1:3]

GND[1:2]

VDD

VSS

+5V

VREFH

VDDA

EVDD

RST

RST_A

+5V

100nF

4.7µF

V_TST

IRQ

VREFL

VSSA

EVSS

1

16

C1+

V_CC

IRQ_A

MM908E625

+

1µF

3

4

15

2

C1-

GND

V+

1µF

+

C2+

9.8304MHz CLOCK

6

V-

+5V

CLK

10k

PTC4/OSC1

PTA0/KBD0

MAX232

5

C2-

PTB4/AD4

+5V

RS232

DB-9

+

10k

74HC125

10k

PTA1/KBD1

PTB3/AD3

2

3

5

7

8

10

9

6

5

DATA

T2_OUT

R2_IN

T2_IN

74HC125

4

R2_OUT

3

2

1

Figure 23. Normal Monitor Mode Circuit (MCU only)

Of course its also possible to supply the whole system with

Vsup (12 V) instead as described in Figure 24, page 40.

PCB level programming

If the IC is soldered onto the pcb board its typically not

possible to separately power the MCU with +5.0 V, the whole

system has to be powered up providing V

Figure 24).

(see

SUP

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

39

TYPICAL APPLICATIONS

FACTORY TRIMMING AND CALIBRATION

V_DD

V_SUP

VSUP[1:3]

GND[1:2]

VDD

VSS

+

100nF

47µF

VREFH

VDDA

EVDD

RST

RST_A

V_DD

100nF

4.7µF

V_TST

IRQ

VREFL

VSSA

EVSS

1

16

C1+

V_CC

IRQ_A

MM908E625

+

1µF

3

4

15

2

C1-

GND

V+

1µF

+

C2+

9.8304MHz CLOCK

6

V-

V_DD

CLK

PTC4/OSC1

PTA0/KBD0

10k

MAX232

5

C2-

PTB4/AD4

V_DD

RS232

DB-9

+

10k

74HC125

10k

PTA1/KBD1

PTB3/AD3

2

3

5

7

8

10

9

6

5

DATA

T2_OUT

R2_IN

T2_IN

74HC125

4

R2_OUT

3

2

1

Figure 24. Normal Monitor Mode Circuit

Table 12 summarizes the possible configurations and the

necessary setups.

Table 12. Monitor Mode Signal Requirements and Options

Serial

Communication

Mode

Selection

Communication Speed

Normal

Request

Timeout

Reset

Vector

Mode IRQ RST

ICG

COP

External

Clock

Baud

Rate

Bus

Frequency

PTA0

PTA1 PTB3 PTB4

Normal

9.8304

MHz

2.4576

MHz

V_TSTV_DD

Monitor

X

1

0

X

1

X

OFF

ON

disabled

enabled

disabled

enabled

9600

9.8304

MHz

2.4576

MHz

V_DD

Forced

Monitor

$FFFF

(blank)

V_DD

1

Nominal

1.6MHz

Nominal

6300

GND

—

not $FFFF

(not blank)

Nominal

1.6MHz

Nominal

6300

User

V_DDV_DD

X

ON

Notes

1. PTA0 must have a pull-up resistor to V in monitor mode

DD

2. External clock is a 4.9152 MHz, 9.8304 MHz or 19.6608 MHz canned oscillator on OCS1

3. Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256

4. X = don’t care

5.

V

is a high voltage V + 3.5 V ≤ V_TST≤ V + 4.5 V

TST DD DD

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

40

TYPICAL APPLICATIONS

FACTORY TRIMMING AND CALIBRATION

EMC/EMI RECOMMENDATIONS

This paragraph gives some device specific MCU digital supply pins (EVDD and EVSS)

recommendations to improve EMC/EMI performance.

Further generic design recommendations can be e.g. found

on the Freescale web site www.freescale.com.

Fast signal transitions on MCU pins place high, short-

duration current demands on the power supply. To prevent

noise problems, take special care to provide power supply

bypassing at the MCU. It is recommended that a high quality

ceramic decoupling capacitor be placed between these pins.

VSUP pins (VSUP1:VSUP3)

Its recommended to place a high-quality ceramic

decoupling capacitor close to the VSUP pins to improve

EMC/EMI behavior.

MCU analog supply pins (VREFH, VDDA and VREFL,

VSSA)

To avoid noise on the analog supply pins its important to

take special care on the layout. The MCU digital and analog

supplies should be tied to the same potential via separate

traces and connected to the voltage regulator output.

LIN pin

For DPI (Direct Power Injection) and ESD (Electro Static

Discharge) its recommended to place a high quality ceramic

decoupling capacitor near the LIN pin. An additional varistor

will further increase the immunity against ESD. A ferrite in the

LIN line will suppress some of the noise induced.

Figure 25 and Figure 26 show the recommendations on

schematics and layout level and Table 13 indicates

recommended external components and layout

considerations.

Voltage regulator output pins (VDD and AGND)

Use a high quality ceramic decoupling capacitor to

stabilize the regulated voltage.

D1

V_SUP

VSUP1

VSUP2

VSUP3

VDD

VSS

+

C2

C1

VREFH

VDDA

EVDD

L1

LIN

V1

C5

C3

C4

EVSS

VSSA

MM908E625

GND1

GND2

VREFL

Figure 25. EMC/EMI Recommendations

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

41

TYPICAL APPLICATIONS

FACTORY TRIMMING AND CALIBRATION

1

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

2

3

4

5

6

7

VREFH

VDDA

EVDD

EVSS

VSSA

VREFL

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

NC

908E625

VSS

VDD

C4

LIN

NC

LIN

GND

VBAT

L1

NC

VSUP1

GND1

VSUP3

GND2

VSUP2

C2

D1

Figure 26. PCB Layout Recommendations

.

Table 13. Component Value Recommendation

(1)

Component

Recommended Value

Comments / Signal routing

D1

C1

C2

C3

reverse battery protection

Bulk Capacitor

100nF, SMD Ceramic, Low ESR

Close (<5mm) to VSUP1, VSUP2 pins with good ground return

Close (<3mm) to digital supply pins (EVDD, EVSS) with good ground

return.

The positive analog (VREFH, VDDA) and the digital (EVDD) supply

should be connected right at the C3.

C4

C5

4,7uF, SMD Ceramic, Low ESR

180pF, SMD Ceramic, Low ESR

Bulk Capacitor

Close (<5.0 mm) to LIN pin.

Total Capacitance on LIN has to be below 220 pF.

(C

= C

+ C5 + C

~ 10 pF + 180 pF + 15 pF)

Varistor

total

LIN-Pin

(2)

V1

Varistor Type TDK AVR-M1608C270MBAAB

SMD Ferrite Bead Type TDK MMZ2012Y202B

Optional (close to LIN connector)

Optional, (close to LIN connector)

(2)

L1

Notes

1. Freescale does not assume liability, endorse, or want components from external manufactures that are referenced in circuit drawings

or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their

application.

2. Components are recommended to improve EMC and ESD performance.

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

42

PACKAGING

PACKAGING DIMENSIONS

PACKAGING

PACKAGING DIMENSIONS

Important: For the most current revision of the package, visit www.freescale.com and do a keyword search on the

98ARL10519D drawing number below. Dimensions shown are provided for reference ONLY.

EK SUFFIX (PB-FREE)

54-PIN

98ARL10519D

ISSUE D

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

43

PACKAGING

PACKAGING DIMENSIONS

EK SUFFIX (PB-FREE)

54-PIN

98ARL10519D

ISSUE D

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

44

PACKAGING

PACKAGING DIMENSIONS

EK SUFFIX (PB-FREE)

54-PIN

98ARL10519D

ISSUE D

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

45

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 2.0)

ADDITIONAL DOCUMENTATION

908E625

THERMAL ADDENDUM (REV 2.0)

Introduction

This thermal addendum ia provided as a supplement to the MM908E625

technical data sheet. The addendum provides thermal performance information

that may be critical in the design and development of system applications. All

electrical, application and packaging information is provided in the data sheet.

54-PIN

SOICW-EP

Package and Thermal Considerations

This MM908E625 is a dual die package. There are two heat sources in the

package independently heating with P and P . This results in two junction

1

2

temperatures, T and T , and a thermal resistance matrix with R_θJAmn

.

J1

J2

For m, n = 1, R_θJA11is the thermal resistance from Junction 1 to the reference

temperature while only heat source 1 is heating with P .

1

EK SUFFIX (Pb-Free)

98ARL10519D

54-PIN SOICW-EP

For m = 1, n = 2, R_θJA12is the thermal resistance from Junction 1 to the

reference temperature while heat source 2 is heating with P . This applies to

R_θJ21and R_θJ22, respectively.

2

R_θJA11R_θJA12

R_θJA21R_θJA22

T

P

J1

J2

1

2

.

=

Note For package dimensions, refer to

98ARL10519D.

The stated values are solely for a thermal performance comparison of one

package to another in a standardized environment. This methodology is not

meant to and will not predict the performance of a package in an application-

specific environment. Stated values were obtained by measurement and

simulation according to the standards listed below.

Standards

Table 1. Thermal Performance Comparison

1 = Power Chip, 2 = Logic Chip [°C/W]

1.0

Thermal

Resistance

m = 1,

n = 1

m = 1, n = 2

m = 2, n = 1

m = 2,

n = 2

(1)(2)

R_θJAmn

R_θJBmn

R_θJAmn

R_θJCmn

23

9.0

52

20

6.0

47

0

24

10

52

2.0

0.2

(2)(3)

(1)(4)

(5)

* All measurements

are in millimeters

Soldermast

openings

1.0

Notes:

Thermal vias

connected to top

buried plane

1. Per JEDEC JESD51-2 at natural convection, still air

condition.

2. 2s2p thermal test board per JEDEC JESD51-7and

JESD51-5.

54 Terminal SOIC-EP

0.65 mm Pitch

3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the power outputs.

17.9 mm x 7.5 mm Body

10.3 mm x 5.1 mm Exposed Pad

4. Single layer thermal test board per JEDEC JESD51-3 and

JESD51-5.

5. Thermal resistance between the die junction and the

exposed pad, “infinite” heat sink attached to exposed pad.

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

46

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 2.0)

A

PTB7/AD7/TBCH1

PTB6/AD6/TBCH0

PTC4/OSC1

PTC3/OSC2

PTC2/MCLK

PTB5/AD5

PTB4/AD4

PTB3/AD3

IRQ

PTA0/KBD0

PTA1/KBD1

PTA2/KBD2

FLSVPP

PTA3/KBD3

PTA4/KBD4

VREFH

VDDA

EVDD

EVSS

1

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

2

3

4

5

6

7

8

9

RST

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

PTB1/AD1

PTD0/TACH0/BEMF

PTD1/TACH1

NC

VSSA

VREFL

PTE1/RXD

RXD

VSS

PA1

VDD

H1

H2

H3

HVDD

NC

HB4

VSUP3

GND2

HB3

Exposed

Pad

FGEN

BEMF

RST_A

IRQ_A

SS

LIN

NC

HB1

VSUP1

GND1

HB2

VSUP2

HS

908E625 Pin Connections

54-Pin SOICW-EP

0.65 mm Pitch

17.9 mm x 7.5 mm Body

10.3 mm x 5.1 mm Exposed Pad

Figure 27. Thermal Test Board

Device on Thermal Test Board

Table 14. Thermal Resistance Performance

Material:

Single layer printed circuit board

1 = Power Chip, 2 = Logic Chip (°C/W)

FR4, 1.6 mm thickness

Area A

(mm²)

Thermal

Resistance

m = 1,

n = 1

m = 1, n = 2

m = 2, n = 1

m = 2,

n = 2

Cu traces, 0.07 mm thickness

Outline:

80 mm x 100 mm board area,

including edge connector for thermal

testing

R_θJAmn

0

53

39

35

21

15

14

48

34

30

16

11

9.0

53

38

34

20

15

13

300

600

0

Area A:

Cu heat-spreading areas on board

surface

R_θJSmn

300

600

Ambient Conditions: Natural convection, still air

R_θJAis the thermal resistance between die junction and

ambient air.

R_θJSmnis the thermal resistance between die junction and

the reference location on the board surface near a center

lead of the package.

This device is a dual die package. Index m indicates the

die that is heated. Index n refers to the number of the die

where the junction temperature is sensed.

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

47

REVISION HISTORY

REVISION

DATE

DESCRIPTION OF CHANGES

•

Implemented Revision History page

9/2010

7.0

(7)(8)

Changed Peak Package Reflow Temperature During Reflow

description.

(8)

•

Added note

Changes to AWD Period Low = 512 tOSC and AWD Period High = 256 tOSC

Change to LIN Timing Description

7/2011

8.0

Change to Stop Mode Output Voltage (Maximum Output Current 100 μA)

Added MM908E625ACEK and MM908E625ACPEK to the ordering information

Removed part numbers with DWB suffix

Updated Freescale form and style

Updated packaging information

10/2011

04/2012

•

Change to LIN Timing Description

9.0

Removed part number MM908E625ACEK.

10.0

Updated Freescale form and style

908E625

Analog Integrated Circuit Device Data

Freescale Semiconductor

48

Information in this document is provided solely to enable system and software

implementers to use Freescale products. There are no express or implied copyright

licenses granted hereunder to design or fabricate any integrated circuits on the

information in this document.

How to Reach Us:

Home Page:

freescale.com

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Freescale reserves the right to make changes without further notice to any products

herein. Freescale makes no warranty, representation, or guarantee regarding the

suitability of its products for any particular purpose, nor does Freescale assume any

liability arising out of the application or use of any product or circuit, and specifically

disclaims any and all liability, including without limitation consequential or incidental

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specifications can and do vary in different applications, and actual performance may

vary over time. All operating parameters, including “typicals,” must be validated for

each customer application by customer’s technical experts. Freescale does not convey

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Symphony are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

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Semiconductor, Inc. All other product or service names are the property of their

respective owners.

Document Number: MM908E625

Rev 10

04/2012


型号：	MM908E625ACPEKR2
厂家：	NXP
描述：	Stepper motor driver, 4x H-B, 1 HSS, 3x Hall input, 8-bit MCU, 16KB Flash , LIN,SOIC-EP 54, Reel 时钟光电二极管外围集成电路
文件：	总49页 (文件大小：837K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MM908E625ACPEKR2 [NXP]

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