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MM908E626AVEKR2 [NXP]

MICROCONTROLLER;
MM908E626AVEKR2
型号： MM908E626AVEKR2
厂家： NXP    NXP
描述：

MICROCONTROLLER

时钟 光电二极管 外围集成电路
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中文：  中文翻译
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Document number: MM908E626  
Rev. 10.0, 8/2012  
Freescale Semiconductor  
Technical Data  
Integrated Stepper Motor Driver  
with Embedded MCU and LIN  
Serial Communication  
908E626  
The 908E626 is an integrated single package solution that includes  
a high performance HC08 microcontroller with a SMARTMOS analog  
control IC. The HC08 includes flash memory, a timer, enhanced serial  
communications interface (ESCI), an analog-to-digital converter  
(ADC), internal serial peripheral interface (SPI), and an internal clock  
generator (ICG) module. The analog control die provides fully  
protected H-Bridge outputs, voltage regulator, autonomous watchdog,  
and local interconnect network (LIN) physical layer.  
STEPPER MOTOR DRIVER  
WITH EMBEDDED MCU AND LIN  
The single package solution, together with LIN, provides optimal  
application performance adjustments and space-saving PCB design. It  
is well-suited for the control of automotive stepper applications like  
climate control and light-leveling.  
EK SUFFIX (PB-FREE)  
98ARL10519D  
54-PIN SOICW-EP  
Features  
• High performance M68HC08EY16 core  
• 16 KB of on-chip flash memory  
• 512 B of RAM  
ORDERING INFORMATION  
• Internal clock generation module  
• Two 16-bit, two-channel timers  
• 10-bit analog-to-digital converter  
• Four low RDS(ON) half-bridge outputs  
• 13 microcontroller I/Os  
Device  
(Add an R2 suffix for Tape  
and reel orders)  
Temperature  
Package  
Range (T )  
A
MM908E626AVPEK  
MM908E626AVEK  
-40 to 115 °C 54 SOICW EP  
908E626  
VSP1:3]  
LIN  
VREFH  
VDDA  
EVDD  
VDD  
VREFL  
VSSA  
EVSS  
VSS  
HB1  
HB2  
Bipolar  
Step  
Motor  
HB3  
HB4  
N
S
RST  
RST A  
IRQ  
IRQ A  
SS  
PTB1/AD1  
RXD  
Switchable Internal V Output  
DD  
HVDD  
PTE1/RXD  
PTD1/TACH1  
FGEN  
BEMF  
PORTA I/Os  
PORTB I/Os  
PORTC I/Os  
Microcontroller Ports  
PTD0/TACH0/BEMF  
GND[1:2]  
EP  
Figure 1. 908E626 Simplified Application Diagram  
* This document contains certain information on a new product.  
Specifications and information herein are subject to change without notice.  
© Freescale Semiconductor, Inc., 2005-2012. All rights reserved.  
GND1-2  
VSUP1-3  
RST_A  
IRQ_A  
BEMF  
FGEN  
LIN  
RXD  
SS  
PTE1/RXD  
PTD1/TACH1  
PTD0/TACH0  
PTB1/AD1  
RST  
PORT C  
DDRC  
PORT D PORT E  
DDRD DDRE  
IRQ  
VREFL  
VSSA  
Internal Bus  
DDRA  
PORT A  
DDRB  
PORT B  
EVSS  
EVDD  
VDDA  
VREFH  
Figure 2. 908E626 Simplified Internal Block Diagram  
908E626  
Analog Integrated Circuit Device Data  
2
Freescale Semiconductor  
PIN CONNECTIONS  
PIN CONNECTIONS  
Transparent Top  
View of Package  
PTB7/AD7/TBCH1  
PTB6/AD6/TBCH0  
PTC4/OSC1  
PTC3/OSC2  
PTC2/MCLK  
PTB5/AD5  
PTB4/AD4  
PTB3/AD3  
IRQ  
1
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
PTA0/KBD0  
PTA1/KBD1  
PTA2/KBD2  
FLSVPP  
PTA3/KBD3  
PTA4/KBD4  
VREFH  
VDDA  
EVDD  
EVSS  
2
3
4
5
6
7
8
9
RST  
10  
11  
12  
13  
PTB1/AD1  
PTD0/TACH0/BEMF  
PTD1/TACH1  
NC  
VSSA  
VREFL  
PTE1/RXD  
RXD  
VSS  
NC  
VDD  
NC  
NC  
NC  
HVDD  
NC  
HB4  
VSUP3  
GND2  
HB3  
Exposed  
Pad  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
FGEN  
BEMF  
RST_A  
IRQ_A  
SS  
LIN  
NC  
NC  
HB1  
VSUP1  
GND1  
HB2  
VSUP2  
NC  
Figure 3. 908E626 Pin Connections  
Table 1. 908E626 PIN DEFINITIONS  
A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.  
Die  
Pin  
Pin Name  
Formal Name  
Definition  
These pins are special function, bidirectional I/O port pins that are  
shared with other functional modules in the MCU.  
MCU  
1
2
6
PTB7/AD7/TBCH1  
PTB6/AD6/TBCH0  
PTB5/AD5  
Port B I/Os  
7
PTB4/AD4  
8
PTB3/AD3  
11  
PTB1/AD1  
These pins are special function, bidirectional I/O port pins that are  
shared with other functional modules in the MCU.  
MCU  
3
4
5
PTC4/OSC1  
PTC3/OSC2  
PTC2/MCLK  
Port C I/Os  
This pin is an asynchronous external interrupt input pin.  
MCU  
MCU  
MCU  
9
IRQ  
External Interrupt  
Input  
This pin is bidirectional, allowing a reset of the entire system. It is  
driven low when any internal reset source is asserted.  
10  
RST  
External Reset  
These pins are special function, bidirectional I/O port pins that are  
shared with other functional modules in the MCU.  
12  
13  
PTD0/TACH0/BEMF  
PTD1/TACH1  
Port D I/Os  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
3
PIN CONNECTIONS  
Table 1. 908E626 PIN DEFINITIONS  
A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.  
Die  
Pin  
Pin Name  
Formal Name  
Definition  
–
14, 21, 22,  
28, 33, 35,  
36, 37, 39  
NC  
No Connect  
Not connected.  
MCU  
MCU  
MCU  
42  
PTE1/RXD  
Port E I/O  
This pin is a special function, bidirectional I/O port pin that can is  
shared with other functional modules in the MCU.  
43  
48  
VREFL  
VREFH  
ADC References  
ADC Supply Pins  
These pins are the reference voltage pins for the analog-to-digital  
converter (ADC).  
44  
47  
VSSA  
VDDA  
These pins are the power supply pins for the analog-to-digital  
converter.  
MCU  
MCU  
45  
46  
EVSS  
EVDD  
MCU Power Supply  
Pins  
These pins are the ground and power supply pins, respectively. The  
MCU operates from a single power supply.  
49  
50  
52  
53  
54  
PTA4/KBD4  
PTA3/KBD3  
PTA2/KBD2  
PTA1/KBD1  
PTA0/KBD0  
Port A I/Os  
These pins are special function, bidirectional I/O port pins that are  
shared with other functional modules in the MCU.  
MCU  
51  
15  
FLSVPP  
FGEN  
Test Pin  
For test purposes only. Do not connect in the application.  
Analog  
Current Limitation  
Frequency Input  
This is the input pin for the half-bridge current limitation PWM  
frequency.  
Analog  
16  
BEMF  
Back Electromagnetic This pin gives the user information about back electromagnetic force  
Force Output  
(BEMF).  
Analog  
Analog  
17  
18  
Internal Reset  
RST_A  
IRQ_A  
This pin is the bidirectional reset pin of the analog die.  
Internal Interrupt  
Output  
This pin is the interrupt output pin of the analog die indicating errors  
or wake-up events.  
Analog  
Analog  
Analog  
19  
20  
Slave Select  
LIN Bus  
This pin is the SPI slave select pin for the analog chip.  
SS  
LIN  
This pin represents the single-wire bus transmitter and receiver.  
23  
26  
29  
32  
HB1  
HB2  
HB3  
HB4  
Half-bridge Outputs  
This device includes power MOSFETs configured as four half-bridge  
driver outputs. These outputs may be configured for step motor  
drivers, DC motor drivers, or as high side and low side switches.  
Analog  
24  
27  
31  
VSUP1  
VSUP2  
VSUP3  
Power Supply Pins  
Power Ground Pins  
These pins are device power supply pins.  
Analog  
Analog  
25  
30  
GND1  
GND2  
These pins are device power ground connections.  
34  
HVDD  
Switchable VDD  
Output  
This pin is a switchable VDD output for driving resistive loads  
requiring a regulated 5.0 V supply; e.g., 3 pin Hall-effect sensors.  
Analog  
Analog  
38  
40  
VDD  
VSS  
Voltage Regulator  
Output  
The 5.0 V voltage regulator output pin is intended to supply the  
embedded microcontroller.  
Voltage Regulator  
Ground  
Ground pin for the connection of all non-power ground connections  
(microcontroller and sensors).  
Analog  
–
41  
RXD  
LIN Transceiver  
Output  
This pin is the output of LIN transceiver.  
EP  
Exposed Pad  
Exposed Pad  
The exposed pad pin on the bottom side of the package conducts  
heat from the chip to the PCB board.  
908E626  
Analog Integrated Circuit Device Data  
4
Freescale Semiconductor  
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
Table 2. MAXIMUM RATINGS  
All voltages are with respect to ground unless otherwise noted. Exceeding limits on any pin may cause permanent damage to  
the device.  
Rating  
Symbol  
Value  
Unit  
ELECTRICAL RATINGS  
Supply Voltage  
V
V
Analog Chip Supply Voltage under Normal Operation (Steady-  
state)  
-0.3 to 28  
SUP(SS)  
SUP(PK)  
Analog Chip Supply Voltage under Transient Conditions (1)  
Microcontroller Chip Supply Voltage  
V
-0.3 to 40  
-0.3 to 6.0  
V
DD  
Input Pin Voltage  
Analog Chip  
V
V
-0.3 to 5.5  
IN(ANALOG)  
Microcontroller Chip  
V
-0.3 to V +0.3  
SS DD  
V
IN  
(MCU)  
Maximum Microcontroller Current per Pin  
All Pins Except VDD, VSS, PTA0:PTA6, PTC0:PTC1  
Pins PTA0:PTA6, PTC0:PTC1  
mA  
I
I
±15  
±25  
PIN(1)  
PIN(2)  
Maximum Microcontroller VSS Output Current  
Maximum Microcontroller VDD Input Current  
I
100  
100  
mA  
mA  
V
MVSS  
I
MVDD  
LIN Supply Voltage  
Normal Operation (Steady-state)  
V
-18 to 28  
40  
BUS(SS)  
Transient Conditions (1)  
V
BUS(DYNAMIC)  
ESD Voltage  
V
Human Body Model (2)  
Machine Model (3)  
Charge Device Model (4)  
V
±3000  
±150  
±500  
ESD1  
V
ESD2  
V
ESD3  
Notes  
1. Transient capability for pulses with a time of t < 0.5 sec.  
2. ESD1 testing is performed in accordance with the Human Body Model (C  
= 100 pF, R  
= 1500 ).  
ZAP  
ZAP  
3. ESD2 testing is performed in accordance with the Machine Model (C  
=200 pF, R  
= 0 ).  
ZAP  
ZAP  
4. ESD3 testing is performed in accordance with Charge Device Model, robotic (C  
=4.0 pF).  
ZAP  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
5
ELECTRICAL CHARACTERISTICS  
MAXIMUM RATINGS  
Table 2. MAXIMUM RATINGS  
All voltages are with respect to ground unless otherwise noted. Exceeding limits on any pin may cause permanent damage to  
the device.  
Rating  
Symbol  
Value  
Unit  
THERMAL RATINGS  
Storage Temperature  
T
-40 to 150  
-40 to 115  
C  
C  
STG  
Operating Case Temperature (5)  
Operating Junction Temperature(6)  
C
T
T
-40 to 135  
Note 8  
C  
C  
J
Peak Package Reflow Temperature During Solder Mounting (7)(8)  
TPPRT  
Notes  
5. The limiting factor is junction temperature, taking into account the power dissipation, thermal resistance, and heat sinking.  
6. The temperature of analog and MCU die is strongly linked via the package, but can differ in dynamic load conditions, usually because  
of higher power dissipation on the analog die. The analog die temperature must not exceed 150 °C under these conditions  
7. Pin soldering temperature is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may  
cause malfunction or permanent damage to the device.  
8. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow  
Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes  
and enter the core ID to view all orderable parts (i.e. MC33xxxD enter 33xxx), and review parametrics.  
908E626  
Analog Integrated Circuit Device Data  
6
Freescale Semiconductor  
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. STATIC ELECTRICAL CHARACTERISTICS  
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller  
chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40 C TJ 135 C, unless otherwise noted. Typical values  
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
SUPPLY VOLTAGE  
Nominal Operating Voltage  
SUPPLY CURRENT  
NORMAL Mode  
V
8.0  
–
18  
V
SUP  
RUN  
V
= 12 V, Power Die ON (PSON=1), MCU Operating Using  
I
mA  
SUP  
–
–
20  
–
–
Internal Oscillator at 32 MHz (8.0 MHz Bus Frequency), SPI, ESCI,  
ADC Enabled  
STOP Mode (9)  
I
STOP  
V
= 12 V, Cyclic Wake-up Disabled  
75  
A  
SUP  
DIGITAL INTERFACE RATINGS (ANALOG DIE)  
Output Pins RST_A, IRQ_A  
V
Low State Output Voltage (IOUT = -1.5 mA)  
High State Output Voltage (IOUT = 1.0 A)  
VOL  
VOH  
–
–
–
0.4  
–
3.85  
Output Pins BEMF, RXD  
V
Low State Output Voltage (IOUT = -1.5 mA)  
High State Output Voltage (IOUT = 1.5 mA)  
VOL  
VOH  
–
–
–
0.4  
–
3.85  
Output Pin RXD– Capacitance (10)  
CIN  
–
4.0  
–
pF  
V
Input Pins RST_A, FGEN, SS  
Input Logic Low Voltage  
Input Logic High Voltage  
VIL  
VIH  
–
–
–
1.5  
–
3.5  
Input Pins RST_A, FGEN, SS–Capacitance (10)  
Pins RST_A, IRQ_A–Pull-up Resistor  
Pin SS–Pull-up Resistor  
CIN  
–
4.0  
–
pF  
R
R
–
–
–
–
10  
60  
60  
35  
–
–
–
–
k  
k  
k  
A  
PULLUP1  
PULLUP2  
Pins FGEN, MOSI, SPSCK–Pull-down Resistor  
Pin TXD–Pull-up Current Source  
Notes  
R
PULLDOWN  
I
PULLUP  
9. STOP mode current will increase if V  
exceeds 15 V.  
SUP  
10. This parameter is guaranteed by process monitoring but is not production tested.  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
7
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. STATIC ELECTRICAL CHARACTERISTICS (continued)  
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller  
chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40 C TJ 135 C, unless otherwise noted. Typical values  
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.  
Characteristic  
SYSTEM RESETS AND INTERRUPTS  
Symbol  
Min  
Typ  
Max  
Unit  
High Voltage Reset  
Threshold  
V
V
V
V
V
27  
–
30  
33  
–
HVRON  
Hysteresis  
1.5  
V
HVRH  
Low Voltage Reset  
Threshold  
3.6  
–
4.0  
4.7  
–
V
LVRON  
Hysteresis  
100  
mV  
V
LVRH  
High Voltage Interrupt  
Threshold  
V
17.5  
–
21  
23  
–
HVION  
Hysteresis  
1.0  
V
HVIH  
Low Voltage Interrupt  
Threshold  
V
6.5  
–
–
8.0  
–
LVION  
Hysteresis  
0.4  
V
LVIH  
High Temperature Reset (12)  
Threshold  
C  
C  
T
–
170  
–
–
–
RON  
5.0  
Hysteresis  
T
RH  
High Temperature Interrupt (13)  
Threshold  
T
–
160  
–
–
–
ION  
5.0  
Hysteresis  
T
IH  
VOLTAGE REGULATOR  
Normal Mode Output Voltage  
V
V
mV  
V
DDRUN  
I
OUT = 60 mA, 6.0 V < V  
< 18 V  
4.75  
5.0  
5.25  
SUP  
Load Regulation  
OUT = 80 mA, V  
V
LR  
I
= 9.0 V  
–
–
100  
5.0  
SUP  
STOP Mode Output Voltage (Maximum Output Current 100 A)(11)  
DDSTOP  
V
4.45  
4.7  
Notes  
11. Tested to be VLVRON < VDDSTOP  
12. This parameter is guaranteed by process monitoring but is not production tested.  
13. High Temperature Interrupt (HTI) threshold is linked to High Temperature Reset (HTR) threshold (HTR = HTI + 10 C).  
908E626  
Analog Integrated Circuit Device Data  
8
Freescale Semiconductor  
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. STATIC ELECTRICAL CHARACTERISTICS (continued)  
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller  
chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40 C TJ 135 C, unless otherwise noted. Typical values  
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
LIN PHYSICAL LAYER  
Output Low Level  
V
V
V
LIN-LOW  
TXD LOW, 500 Pull-up to V  
–
–
1.4  
SUP  
Output High Level  
V
LIN-HIGH  
TXD HIGH, I  
= 1.0 A  
VSUP -1.0  
20  
–
–
OUT  
Pull-up Resistor to VSUP  
R
30  
60  
k  
A  
SLAVE  
REC  
Leakage Current to GND  
I
BUS_PAS_  
Recessive State (-0.5 V < VLIN < VSUP  
)
0.0  
–
20  
Leakage Current to GND (VSUP Disconnected)  
Including Internal Pull-up Resistor, VLIN @ -18 V  
Including Internal Pull-up Resistor, VLIN @ +18 V  
A  
I
–
–
-600  
25  
–
–
BUS_NO_GND  
I
BUS  
LIN Receiver  
Recessive  
V
V
0.6V  
LIN  
–
–
VSUP  
IH  
Dominant  
V
IL  
0.4VLIN  
0
–
V
V
/2  
Threshold  
SUP  
V
–
ITH  
Input Hysteresis  
0.01V  
SUP  
–
0.1VSUP  
V
IHY  
LIN Wake-up Threshold  
V
–
/2  
–
V
WTH  
SUP  
HALF-BRIDGE OUTPUTS (HB1:HB4)  
Switch ON Resistance @ TJ = 25 C with ILOAD = 1.0 A  
m  
R
–
–
425  
400  
500  
500  
High Side  
Low Side  
DS(ON)HB_HS  
R
DS(ON)HB_LS  
High Side Over-current Shutdown  
Low Side Over-current Shutdown  
Low Side Current Limitation @ TJ = 25 C  
3.0  
2.5  
–
–
7.5  
7.5  
I
A
A
HBHSOC  
I
HBLSOC  
mA  
I
–
55  
–
CL1  
Current Limit 1 (CLS2 = 0, CLS1 = 1, CLS0 = 1)  
Current Limit 2 (CLS2 = 1, CLS1 = 0, CLS0 = 0)  
Current Limit 3 (CLS2 = 1, CLS1 = 0, CLS0 = 1)  
Current Limit 4 (CLS2 = 1, CLS1 = 1, CLS0 = 0)  
Current Limit 5 (CLS2 = 1, CLS1 = 1, CLS0 = 1)  
I
210  
300  
450  
600  
260  
370  
550  
740  
315  
440  
650  
880  
CL2  
I
CL3  
I
I
CL4  
CL5  
Half-bridge Output HIGH Threshold for BEMF Detection  
Half-bridge Output LOW Threshold for BEMF Detection  
Hysteresis for BEMF Detection  
V
–
–
–
-30  
-60  
30  
0.0  
-5.0  
–
V
BEMFH  
V
mV  
mV  
V/A  
BEMFL  
V
BEMFHY  
Low Side Current-to-Voltage Ratio (V  
[V]/I [A])  
HB  
ADOUT  
RATIOH  
RATIOL  
7.0  
1.0  
12.0  
2.0  
14.0  
3.0  
CSA = 1  
CSA = 0  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
9
ELECTRICAL CHARACTERISTICS  
STATIC ELECTRICAL CHARACTERISTICS  
Table 3. STATIC ELECTRICAL CHARACTERISTICS (continued)  
All characteristics are for the analog chip only. Refer to the 68HC908EY16 datasheet for characteristics of the microcontroller  
chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40 C TJ 135 C, unless otherwise noted. Typical values  
noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.  
Characteristic  
OUTPUT (HVDD)  
Symbol  
Min  
Typ  
Max  
Unit  
SWITCHABLE V  
DD  
Over-current Shutdown Threshold  
VSUP DOWN-SCALER  
I
24  
30  
40  
mA  
HVDDOCT  
Voltage Ratio (RATIOVSUP = VSUP /VADOUT  
)
RATIOVSUP  
4.8  
5.1  
5.35  
–
INTERNAL DIE TEMPERATURE SENSOR  
Voltage/Temperature Slope  
STTOV  
–
19  
–
mV/°C  
V
Output Voltage @ 25 °C  
V
1.7  
2.1  
2.5  
T25  
908E626  
Analog Integrated Circuit Device Data  
10  
Freescale Semiconductor  
ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
DYNAMIC ELECTRICAL CHARACTERISTICS  
Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS  
All characteristics are for the analog chip only. Please refer to the 68HC908EY16 datasheet for characteristics of the  
microcontroller chip. Characteristics noted under conditions 9.0 V VSUP 16 V, -40 C TJ 135 C, unless otherwise noted.  
Typical values noted reflect the approximate parameter mean at TA = 25 C under nominal conditions, unless otherwise noted.  
Characteristic  
Symbol  
Min  
Typ  
Max  
Unit  
LIN PHYSICAL LAYER  
(15)  
Propagation Delay (14)  
,
s  
t
–
–
–
–
6.0  
6.0  
8.0  
8.0  
2.0  
2.0  
TXD-LIN-LOW  
TXD LOW to LIN LOW  
TXD HIGH to LIN HIGH  
LIN LOW to RXD LOW  
LIN HIGH to RXD HIGH  
TXD Symmetry  
tTXD-LIN-HIGH  
t LIN-RXD-LOW  
tLIN-RXD-HIGH  
–
4.0  
4.0  
–
–
-2.0  
-2.0  
t
t
TXD-SYM  
RXD-SYM  
–
RXD Symmetry  
(16)  
Output Falling Edge Slew Rate (14)  
80% to 20%  
,
F
SR  
V/s  
V/s  
-1.0  
-2.0  
-3.0  
(16)  
Output Rising Edge Slew Rate (14)  
,
R
SR  
1.0  
2.0  
–
3.0  
2.0  
20% to 80%, RBUS > 1.0 k, CBUS < 10 nF  
LIN Rise/Fall Slew Rate Symmetry (14)  
AUTONOMOUS WATCHDOG (AWD)  
AWD Oscillator Period  
,
S
(16)  
SR  
-2.0  
s  
t
–
40  
–
s  
OSC  
AWD Period Low = 512 tOSC  
t
ms  
AWDPH  
16  
16  
27  
22  
34  
28  
TJ < 25 °C  
TJ 25 °C  
AWD Period High = 256 tOSC  
t
ms  
AWDPL  
8.0  
8.0  
13.5  
11  
17  
14  
TJ < 25 °C  
TJ 25 °C  
AWD Cyclic Wake-up On Time  
t
–
90  
–
s  
AWDHPON  
Notes  
14. All LIN characteristics are for initial LIN slew rate selection (20 kbaud) (SRS0:SRS1= 00).  
15. See Figure 4, page 12.  
16. See Figure 5, page 13.  
MICROCONTROLLER PARAMETRICS  
Table 5. MICROCONTROLLER  
For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet.  
Module  
Description  
Core  
Timer  
Flash  
RAM  
High Performance HC08 Core with a Maximum Internal Bus Frequency of 8.0 MHz  
Two 16-Bit Timers with Two Channels (TIM A and TIM B)  
16 k Bytes  
512 Bytes  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
11  
ELECTRICAL CHARACTERISTICS  
TIMING DIAGRAMS  
Table 5. MICROCONTROLLER  
For a detailed microcontroller description, refer to the MC68HC908EY16 datasheet.  
Module  
Description  
ADC  
SPI  
10 Bit Analog-to-Digital Converter  
SPI Module  
ESCI  
Standard Serial Communication Interface (SCI) Module   
Bit-Time Measurement  
Arbitration  
Prescaler with Fine Baud Rate Adjustment  
ICG  
Internal Clock Generation Module  
BEMF Counter  
Special Counter for SMARTMOS BEMF Output  
TIMING DIAGRAMS  
t
t
TXD-LIN-HIGH  
TXD-LIN-LOW  
TXD  
LIN  
0.9 V  
Recessive State  
Recessive State  
SUP  
0.7 V  
LIN  
0.3 V  
LIN  
0.1 V  
SUP  
Dominant State  
RXD  
t
t
LIN-RXD-LOW  
LIN-RXD-HIGH  
Figure 4. LIN Timing Description  
908E626  
Analog Integrated Circuit Device Data  
12  
Freescale Semiconductor  
ELECTRICAL CHARACTERISTICS  
FUNCTIONAL DIAGRAMS  
t Fall-time  
t Rise-time  
0.8 V  
SUP  
0.8 V  
SUP  
V Fall  
V Rise  
0.2 V  
SUP  
0.2 V  
SUP  
Dominant State  
V Fall  
V Rise  
SRF =  
SRR  
=
t Fall-time  
t Rise-time  
Figure 5. LIN Slew Rate Description  
FUNCTIONAL DIAGRAMS  
1.6  
1.4  
1.2  
1.0  
0.8  
0.6  
0.4  
0.2  
0.0  
T = 25°C  
J
0.0  
0.5  
1.0  
1.5  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
5.0  
Amperes  
H-Bridge Low Side  
Figure 6. Free Wheel Diode Forward Voltage  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
13  
ELECTRICAL CHARACTERISTICS  
FUNCTIONAL DIAGRAMS  
250  
200  
50  
00  
50  
T = 125°C  
A
T = 25°C  
A
T = -40°C  
A
0
0
5.0  
10  
15  
20  
25  
ILOAD (mA)  
Figure 7. Dropout Voltage on HVDD  
908E626  
Analog Integrated Circuit Device Data  
14  
Freescale Semiconductor  
FUNCTIONAL DESCRIPTION  
INTRODUCTION  
FUNCTIONAL DESCRIPTION  
INTRODUCTION  
The 908E626 device was designed and developed as a  
highly integrated and cost-effective solution for automotive  
and industrial applications. For automotive body electronics,  
the 908E626 is well suited to perform stepper motor control,  
e.g. for climate or light-levelling control via a 3-wire LIN bus.  
on the SMARTMOS IC configured as four half-bridge  
outputs. Other ports are also provided including a selectable  
HVDD pin. An internal voltage regulator is provided on the  
SMARTMOS IC chip, which provides power to the MCU chip.  
Also included in this device is a LIN physical layer, which  
communicates using a single wire. This enables the device to  
be compatible with 3-wire bus systems, where one wire is  
used for communication, one for battery, and the third for  
ground.  
This device combines an standard HC08 MCU core  
(68HC908EY16) with flash memory together with a  
SMARTMOS IC chip. The SMARTMOS IC chip combines  
power and control in one chip. Power switches are provided  
FUNCTIONAL PIN DESCRIPTION  
See Figures 1, for a graphic representation of the various  
pins referred to in the following paragraphs. Also, see the pin  
diagram on Figures 3 for a depiction of the pin locations on  
the package.  
PORT D I/O PINS (PTD0:1)  
PTD1/TACH1 and PTD0/TACH0/BEMF are special  
function, bidirectional I/O port pins that can also be  
programmed to be timer pins.  
In step motor applications, the PTD0 pin should be  
connected to the BEMF output of the analog die, to evaluate  
the BEMF signal with a special BEMF module of the MCU.  
PORT A I/O PINS (PTA0:4)  
These pins are special function, bidirectional I/O port pins  
that are shared with other functional modules in the MCU.  
PTA0:PTA4 are shared with the keyboard interrupt pins,  
KBD0:KBD4.  
PTD1 pin is recommended for use as an output pin for  
generating the FGEN signal (PWM signal), if required by the  
application.  
The PTA5/SPSCK pin is not accessible in this device and  
is internally connected to the SPI clock pin of the analog die.  
The PTA6/SS pin is likewise not accessible.  
PORT E I/O PIN (PTE1)  
PTE1/RXD and PTE0/TXD are special function,  
bidirectional I/O port pins that can also be programmed to be  
enhanced serial communication.  
For details refer to the 68HC908EY16 datasheet.  
PTE0/TXD is internally connected to the TXD pin of the  
analog die.The connection for the receiver must be done  
externally.  
PORT B I/O PINS (PTB1, PTB3:7)  
These pins are special function, bidirectional I/O port pins  
that are shared with other functional modules in the MCU. All  
pins are shared with the ADC module. The PTB6:PTB7 pins  
are also shared with the Timer B module.  
EXTERNAL INTERRUPT PIN (IRQ)  
PTB0/AD0 is internally connected to the ADOUT pin of the  
analog die, allowing diagnostic measurements to be  
The IRQ pin is an asynchronous external interrupt pin. This  
pin contains an internal pull-up resistor that is always  
activated, even when the IRQ pin is pulled LOW.  
calculated; e.g., current recopy, V  
, etc. The PTB2/AD2  
SUP  
pin is not accessible in this device.  
For details refer to the 68HC908EY16 datasheet.  
For details refer to the 68HC908EY16 datasheet.  
EXTERNAL RESET PIN (RST)  
PORT C I/O PINS (PTC2:4)  
A logic [0] on the RST pin forces the MCU to a known  
startup state. RST is bidirectional, allowing a reset of the  
entire system. It is driven LOW when any internal reset  
source is asserted.  
These pins are special function, bidirectional I/O port pins  
that are shared with other functional modules in the MCU. For  
example, PTC2:PTC4 are shared with the ICG module.  
PTC0/MISO and PTC1/MOSI are not accessible in this  
device and are internally connected to the MISO and MOSI  
SPI pins of the analog die.  
This pin contains an internal pull-up resistor that is always  
activated, even when the reset pin is pulled LOW.  
For details refer to the 68HC908EY16 datasheet.  
For details refer to the 68HC908EY16 datasheet.  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
15  
FUNCTIONAL DESCRIPTION  
FUNCTIONAL PIN DESCRIPTION  
requirements of the half-bridge driver outputs, multiple VSUP  
pins are provided.  
CURRENT LIMITATION FREQUENCY INPUT PIN  
(FGEN)  
All VSUP pins must be connected to get full chip  
functionality.  
Input pin for the half-bridge current limitation PWM  
frequency. This input is not a real PWM input pin; it should  
just supply the period of the PWM. The duty cycle will be  
generated automatically.  
POWER GROUND PINS (GND1 AND GND2)  
Important The recommended FGEN frequency should  
be in the range of 0.1 kHz to 20 kHz.  
GND1 and GND2 are device power ground connections.  
Owing to the low ON-resistance and current requirements of  
the half-bridge driver outputs multiple pins are provided.  
GND1 and GND2 pins must be connected to get full chip  
functionality.  
BACK ELECTROMAGNETIC FORCE OUTPUT PIN  
(BEMF)  
This pin gives the user information about back  
electromagnetic force (BEMF). This feature allows stall  
detection and coil failures in step motor applications. In order  
to evaluate this signal the pin must be directly connected to  
pin PTD0/TACH0/BEMF.  
SWITCHABLE VDD OUTPUT PIN (HVDD)  
The HVDD pin is a switchable VDD output for driving  
resistive loads requiring a regulated 5.0 V supply; The output  
is short-circuit protected.  
+5.0 V VOLTAGE REGULATOR OUTPUT PIN (VDD)  
RESET PIN (RST_A)  
The VDD pin is needed to place an external capacitor to  
stabilize the regulated output voltage. The VDD pin is  
intended to supply the embedded microcontroller.  
RST_A is the bidirectional reset pin of the analog die. It is  
an open drain with pull-up resistor and must be connected to  
the RST pin of the MCU.  
Important The VDD pin should not be used to supply  
other loads; use the HVDD pin for this purpose. The VDD,  
EVDD, VDDA, and VREFH pins must be connected together.  
INTERRUPT PIN (IRQ_A)  
IRQ_A is the interrupt output pin of the analog die  
indicating errors or wake-up events. It is an open drain with  
pull-up resistor and must be connected to the IRQ pin of the  
MCU.  
VOLTAGE REGULATOR GROUND PIN (VSS)  
The VSS pin is the ground pin for the connection of all non-  
power ground connections (microcontroller and sensors).  
Important VSS, EVSS, VSSA, and VREFL pins must be  
connected together.  
SLAVE SELECT PIN (SS)  
This pin is the SPI Slave Select pin for the analog chip. All  
other SPI connections are done internally. SS must be  
connected to PTB1 or any other logic I/O of the  
microcontroller.  
LIN TRANSCEIVER OUTPUT PIN (RXD)  
This pin is the output of LIN transceiver. The pin must be  
connected to the microcontroller’s Enhanced Serial  
Communications Interface (ESCI) module (RXD pin).  
LIN BUS PIN (LIN)  
The LIN pin represents the single-wire bus transmitter and  
receiver. It is suited for automotive bus systems and is based  
on the LIN bus specification.  
ADC REFERENCE PINS (VREFL AND VREFH)  
VREFL and VREFH are the reference voltage pins for the  
ADC. It is recommended that a high quality ceramic  
decoupling capacitor be placed between these pins.  
HALF-BRIDGE OUTPUT PINS (HB1:HB4)  
Important VREFH is the high reference supply for the  
ADC and should be tied to the same potential as VDDA via  
separate traces. VREFL is the low reference supply for the  
ADC and should be tied to the same potential as VSS via  
separate traces.  
The 908E626 device includes power MOSFETs  
configured as four half-bridge driver outputs. The HB1:HB4  
outputs may be configured for step motor drivers, DC motor  
drivers, or as high side and low side switches.  
The HB1:HB4 outputs are short-circuit and over-  
temperature protected, and they feature current recopy,  
current limitation, and BEMF generation. Current limitation  
and recopy are done on the low side MOSFETs.  
For details refer to the 68HC908EY16 datasheet.  
ADC SUPPLY PINS (VDDA AND VSSA)  
VDDA and VSSA are the power supply pins for the analog-  
to-digital converter (ADC). It is recommended that a high  
quality ceramic decoupling capacitor be placed between  
these pins.  
POWER SUPPLY PINS (VSUP1:VSUP3)  
VSUP1:VSUP3 are device power supply pins. The  
nominal input voltage is designed for operation from 12 V  
systems. Owing to the low ON-resistance and current  
Important VDDA is the supply for the ADC and should be  
tied to the same potential as EVDD via separate traces.  
908E626  
Analog Integrated Circuit Device Data  
16  
Freescale Semiconductor  
FUNCTIONAL DESCRIPTION  
FUNCTIONAL PIN DESCRIPTION  
VSSA is the ground pin for the ADC and should be tied to the  
same potential as EVSS via separate traces.  
For details refer to the 68HC908EY16 datasheet.  
TEST PIN (FLSVPP)  
For details refer to the 68HC908EY16 datasheet.  
This pin is for test purposes only. This pin should be either  
left open (not connected) or connected to GND.  
MCU POWER SUPPLY PINS (EVDD AND EVSS)  
EVDD and EVSS are the power supply and ground pins.  
The MCU operates from a single power supply.  
EXPOSED PAD PIN  
The exposed pad pin on the bottom side of the package  
conducts heat from the chip to the PCB board. For thermal  
performance the pad must be soldered to the PCB board. It  
is recommended that the pad be connected to the ground  
potential.  
Fast signal transitions on MCU pins place high, short-  
duration current demands on the power supply. To prevent  
noise problems, take special care to provide power supply  
bypassing at the MCU.  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
17  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
above the HTI threshold, the HTI flag will be set. If the High  
INTERRUPTS  
Temperature Interrupt is enabled, an interrupt will be  
initiated.  
The 908E626 has six different interrupt sources as  
described in the following paragraphs. The interrupts can be  
disabled or enabled via the SPI. After reset all interrupts are  
automatically disabled.  
During STOP mode the HTI circuitry is disabled.  
AUTONOMOUS WATCHDOG INTERRUPT (AWD)  
LOW VOLTAGE INTERRUPT  
Refer to Autonomous Watchdog (AWD) on page 30.  
The Low Voltage Interrupt (LVI) is related to the external  
supply voltage, V  
. If this voltage falls below the LVI  
LIN INTERRUPT  
SUP  
threshold, it will set the LVI flag. If the Low Voltage Interrupt  
is enabled, an interrupt will be initiated.  
If the LINIE bit is set, a falling edge on the LIN pin will  
generate an interrupt. During STOP mode this interrupt will  
initiate a system wake-up.  
With LVI the H-Bridges (high side MOSFET only) are  
switched off. All other modules are not influenced by this  
interrupt.  
OVER-CURRENT INTERRUPT  
During STOP mode the LVI circuitry is disabled.  
If an over-current condition on a half-bridge or the HVDD  
output is detected and the OCIE bit is set and an interrupt  
generated.  
HIGH VOLTAGE INTERRUPT  
The High Voltage Interrupt (HVI) is related to the external  
supply voltage, V  
. If this voltage rises above the HVI  
SYSTEM WAKE-UP  
SUP  
threshold, it will set the HVI flag. If the High Voltage Interrupt  
is enabled, an interrupt will be initiated.  
System wake-up can be initiated by any of four events:  
• A falling edge on the LIN pin  
• A wake-up signal from the AWD  
• An LVR condition  
With HVI the H-Bridges (high side MOSFET only) are  
switched off. All other modules are not influenced by this  
interrupt.  
If one of these wake-up events occurs and the interrupt  
mask bit for this event is set, the interrupt will wake-up the  
microcontroller as well as the main voltage regulator (MREG)  
Figures 8.  
During STOP mode the HVI circuitry is disabled.  
HIGH TEMPERATURE INTERRUPT  
The High Temperature Interrupt (HTI) is generated by the  
on-chip temperature sensors. If the chip temperature is  
908E626  
Analog Integrated Circuit Device Data  
18  
Freescale Semiconductor  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
MCU Die  
Analog Die  
From Reset  
Initialize  
Operate  
SPI:  
GS =1  
STOP MREG  
(MREG off)  
Wait for Action  
LIN  
STOP  
AWD  
Hallport  
IRQ  
Interrupt?  
Assert IRQ_A  
SPI: Reason for  
Interrupt  
Start  
MREG  
Operate  
MREG = Main Voltage  
Regulator  
Figure 8. STOP Mode/Wake-up Procedure  
• 1 = Falling edge on LIN data line has occurred.  
• 0 = Falling edge on LIN data line has not occurred since  
last clear.  
INTERRUPT FLAG REGISTER (IFR)  
Register Name and Address: IFR - $05  
Bit7  
6
0
0
5
LINF  
0
4
HTF  
0
3
LVF  
0
2
HVF  
0
1
Bit0  
0
HTF—HIGH TEMPERATURE FLAG BIT  
Read  
Write  
Reset  
OCF  
0
0
This read/write flag is set on a high temperature condition.  
Clear HTF by writing a logic [1] to HTF. If a high temperature  
condition is still present while writing a logic [1] to HTF, the  
writing has no effect. Therefore, a high temperature interrupt  
cannot be lost due to inadvertent clearing of HTF. Reset  
clears the HTF bit. Writing a logic [0] to HTF has no effect.  
0
0
LINF—LIN FLAG BIT  
This read/write flag is set on the falling edge at the LIN  
data line. Clear LINF by writing a logic [1] to LINF. Reset  
clears the LINF bit. Writing a logic [0] to LINF has no effect.  
• 1 = High temperature condition has occurred.  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
19  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
• 0 = High temperature condition has not occurred.  
INTERRUPT MASK REGISTER (IMR)  
Register Name and Address: IMR - $04  
LVF—LOW VOLTAGE FLAG BIT  
Bit7  
6
0
0
5
4
3
LVIE  
0
2
1
Bit0  
0
This read/write flag is set on a low voltage condition. Clear  
LVF by writing a logic [1] to LVF. If a low voltage condition is  
still present while writing a logic [1] to LVF, the writing has no  
effect. Therefore, a low voltage interrupt cannot be lost due  
to inadvertent clearing of LVF. Reset clears the LVF bit.  
Writing a logic [0] to LVF has no effect.  
Read  
Write  
Reset  
0
0
LINIE HTIE  
HVIE OCIE  
0
0
0
0
0
LINIE—LIN LINE INTERRUPT ENABLE BIT  
• 1 = Low voltage condition has occurred.  
• 0 = Low voltage condition has not occurred.  
This read/write bit enables CPU interrupts by the LIN flag,  
LINF. Reset clears the LINIE bit.  
• 1 = Interrupt requests from LINF flag enabled.  
• 0 = Interrupt requests from LINF flag disabled.  
HVF—HIGH VOLTAGE FLAG BIT  
This read/write flag is set on a high voltage condition.  
Clear HVF by writing a logic [1] to HVF. If high voltage  
condition is still present while writing a logic [1] to HVF, the  
writing has no effect. Therefore, a high voltage interrupt  
cannot be lost due to inadvertent clearing of HVF. Reset  
clears the HVF bit. Writing a logic [0] to HVF has no effect.  
HTIE—HIGH TEMPERATURE INTERRUPT  
ENABLE BIT  
This read/write bit enables CPU interrupts by the high  
temperature flag, HTF. Reset clears the HTIE bit.  
• 1 = Interrupt requests from HTF flag enabled.  
• 0 = Interrupt requests from HTF flag disabled.  
• 1 = High voltage condition has occurred.  
• 0 = High voltage condition has not occurred.  
LVIE—LOW VOLTAGE INTERRUPT ENABLE BIT  
OCF—OVER-CURRENT FLAG BIT  
This read/write bit enables CPU interrupts by the low  
voltage flag, LVF. Reset clears the LVIE bit.  
This read-only flag is set on an over-current condition.  
Reset clears the OCF bit. To clear this flag, write a logic [1] to  
the appropriate over-current flag in the SYSSTAT Register.  
See Figure 9, which shows the two signals triggering the  
OCF.  
• 1 = Interrupt requests from LVF flag enabled.  
• 0 = Interrupt requests from LVF flag disabled.  
HVIE—HIGH VOLTAGE INTERRUPT ENABLE BIT  
• 1 = High current condition has occurred.  
• 0 = High current condition has not occurred.  
This read/write bit enables CPU interrupts by the high  
voltage flag, HVF. Reset clears the HVIE bit.  
• 1 = Interrupt requests from HVF flag enabled.  
• 0 = Interrupt requests from HVF flag disabled.  
HVDD_OCF  
OCF  
HB_OCF  
OCIE—OVER-CURRENT INTERRUPT ENABLE BIT  
Figure 9. Principal Implementation for OCF  
This read/write bit enables CPU interrupts by the over-  
current flag, OCF. Reset clears the OCIE bit.  
• 1 = Interrupt requests from OCF flag enabled.  
• 0 = Interrupt requests from OCF flag disabled.  
RESET  
The 908E626 chip has four internal reset sources and one  
external reset source, as explained in the paragraphs below.  
Figure 10 depicts the internal reset sources.  
908E626  
Analog Integrated Circuit Device Data  
20  
Freescale Semiconductor  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
SPI REGISTERS  
AWDRE Flag  
HVRE Flag  
AWD Reset  
Sensor  
VDD  
High-Voltage  
Reset Sensor  
HTRE Flag  
High-Temperature  
Reset Sensor  
RST_A  
MONO  
FLOP  
Low-Voltage Reset  
Figure 10. Internal Reset Routing  
Reset Mask Register (RMR)  
RESET INTERNAL SOURCES  
Autonomous Watchdog  
Register Name and Address: RMR - $06  
Bit7  
TTEST  
0
6
0
5
0
4
0
3
0
2
0
1
Bit0  
AWD modules generates a reset because of a timeout  
(watchdog function).  
Read  
Write  
Reset  
HVRE HTRE  
High Temperature Reset  
0
0
0
0
0
0
0
To prevent damage to the device, a reset will be initiated if  
the temperature rises above a certain value. The reset is  
maskable with bit HTRE in the Reset Mask Register. After a  
reset the high temperature reset is disabled.  
TTEST—High Temperature Reset Test  
This read/write bit is for test purposes only. It decreases  
the over-temperature shutdown limit for final test. Reset  
clears the HTRE bit.  
Low Voltage Reset  
• 1 = Low temperature threshold enabled.  
• 0 = Low temperature threshold disabled.  
The LVR is related to the internal V . In case the voltage  
falls below a certain threshold, it will pull down the RST_A pin.  
DD  
HVRE—High Voltage Reset Enable Bit  
High Voltage Reset  
This read/write bit enables resets on high voltage  
conditions. Reset clears the HVRE bit.  
The HVR is related to the external V  
voltage. In case  
SUP  
the voltage is above a certain threshold, it will pull down the  
RST_A pin. The reset is maskable with bit HVRE in the Reset  
Mask Register. After a reset the high voltage reset is  
disabled.  
• 1 = High voltage reset enabled.  
• 0 = High voltage reset disabled.  
HTRE—High Temperature Reset Enable Bit  
RESET EXTERNAL SOURCE  
External Reset Pin  
This read/write bit enables resets on high temperature  
conditions. Reset clears the HTRE bit.  
• 1 = High temperature reset enabled.  
• 0 = High temperature reset disabled.  
The microcontroller has the capability of resetting the  
SMARTMOS device by pulling down the RST pin.  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
21  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
SERIAL PERIPHERAL INTERFACE  
The serial peripheral interface (SPI) creates the  
communication link between the microcontroller and the  
908E626.  
• MOSI—Master-Out Slave-In  
• MISO—Master-In Slave-Out  
• SPSCK—Serial Clock (maximum frequency 4.0 MHz)  
The interface consists of four pins (see Figure 11):  
A complete data transfer via the SPI consists of 2 bytes.  
The master sends address and data, slave system status,  
and data of the selected address.  
•
SS—Slave Select  
SS  
Read/Write, Address, Parity  
Data (Register write)  
R/W  
A4  
S6  
A3  
A2  
A1  
A0  
P
X
D7  
D7  
D6  
D6  
D5  
D4  
D3  
D2  
D1  
D1  
D0  
D0  
MOSI  
MISO  
System Status Register  
Data (Register read)  
S7  
S5  
S4  
S3  
S2  
S1  
S0  
D5  
D4  
D3  
D2  
SPSCK  
Rising edge of SPSCK  
Change MISO/MOSI  
Output  
Falling edge of SPSCK  
Sample MISO/MOSI  
Input  
Slave latch  
register address  
Slave latch  
data  
Figure 11. SPI Protocol  
During the inactive phase of SS, the new data transfer is  
prepared. The falling edge on the SS line indicates the start  
of a new data transfer and puts MISO in the low-impedance  
mode. The first valid data are moved to MISO with the rising  
edge of SPSCK.  
• If R/W = 1, the second byte of master contains no valid  
information, slave just transmits back register data.  
• If R/W = 0, the master sends data to be written in the  
second byte, slave sends concurrently contents of  
selected register prior to write operation, write data is  
latched in the SMARTMOS register on rising edge of  
SS.  
The MISO output changes data on a rising edge of  
SPSCK. The MOSI input is sampled on a falling edge of  
SPSCK. The data transfer is only valid if exactly 16 sample  
clock edges are present in the active phase of SS.  
Parity P  
After a write operation, the transmitted data is latched into  
the register by the rising edge of SS. Register read data is  
internally latched into the SPI at the time when the parity bit  
is transferred. SS HIGH forces MISO to high-impedance.  
The parity bit is equal to “0” if the number of 1 bits is an  
even number contained within R/W, A4:A0. If the number of  
1 bits is odd, P equals “1”. For example, if R/W = 1, A4:A0 =  
00001, then P equals “0.”  
The parity bit is only evaluated during a write operation.  
MASTER ADDRESS BYTE  
Bit X  
A4:A0  
Not used.  
Contains the address of the desired register.  
Master Data Byte  
R/W  
Contains data to be written or no valid data during a read  
operation.  
Contains information about a read or a write operation.  
908E626  
Analog Integrated Circuit Device Data  
22  
Freescale Semiconductor  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
Table 6. List of Registers  
Bit  
Addr  
$01  
Register Name  
R/W  
7
6
5
HB3_H  
0
4
HB3_L  
0
3
HB2_H  
0
2
1
0
R
W
R
H-bridge Output  
(HBOUT)  
HB4_H  
HB4_L  
HB2_L  
HB1_H  
HB1_L  
H-bridge Control  
(HBCTL)  
$02  
OFC_EN  
PSON  
CSA  
SRS1  
0
CLS2  
0
CLS1  
0
CLS0  
0
W
R
0
0
System Control  
(SYSCTL)  
$03  
SRS0  
LINIE  
W
GS  
0
R
W
R
Interrupt Mask  
(IMR)  
$04  
$05  
$06  
$07  
0
0
HTIE  
LVIE  
HVIE  
OCIE  
OCF  
0
Interrupt Flag  
(IFR)  
0
0
LINF  
0
HTF  
0
LVF  
0
HVF  
0
W
R
Reset Mask  
(RMR)  
TTEST  
0
HVRE  
SS1  
HTRE  
SS0  
W
R
0
0
0
0
0
0
Analog Multiplexer  
Configuration (ADMUX)  
SS3  
0
SS2  
W
R
0
0
$08  
$09  
Reserved  
Reserved  
0
0
0
0
0
0
W
R
0
0
0
0
W
R
0
0
0
0
0
AWD Control  
(AWDCTL)  
$0a  
$0b  
$0c  
AWDRE  
AWDIE  
0
AWDF  
AWDR  
W
R
AWDRST  
Power Output  
(POUT)  
0
0
0
0
0
HVDDON  
HB_OCF  
0
W
R
LINCL  
LVF  
HVF  
HTF  
System Status  
(SYSSTAT)  
HVDD_OC  
F
0
W
Slave Status Byte  
up components are required for the application in a slave  
node. The fall time from dominant to recessive and the rise  
time from recessive to dominant is controlled. The symmetry  
between both slew rate controls is guaranteed.  
Contains the contents of the System Status Register ($0c)  
independent of whether it is a write or read operation or which  
register was selected.  
The LIN pin offers high susceptibility immunity level from  
external disturbance, guaranteeing communication during  
external disturbance.  
Slave Data Byte  
Contains the contents of selected register. During a write  
operation it includes the register content prior to a write  
operation.  
The LIN transmitter circuitry is enabled by setting the  
PSON bit in the System Control Register (SYSCTL). If the  
transmitter works in the current limitation region, the LINCL  
bit in the System Status Register (SYSSTAT) is set. Due to  
excessive power dissipation in the transmitter, software is  
advised to monitor this bit and turn the transmitter off  
immediately.  
SPI Register Overview  
Table 6 summarizes the SPI Register addresses and the  
bit names of each register.  
ANALOG DIE I/OS  
LIN Physical Layer  
TXD Pin  
The TXD pin is the MCU interface to control the state of the  
LIN transmitter (see Figure 2). When TXD is LOW, LIN output  
is low (dominant state). When TXD is HIGH, the LIN output  
MOSFET is turned off. The TXD pin has an internal pull-up  
current source in order to set the LIN bus in recessive state  
in the event, for instance, the microcontroller could not control  
it during system power-up or power-down.  
The LIN bus pin provides a physical layer for single-wire  
communication in automotive applications. The LIN physical  
layer is designed to meet the LIN physical layer specification.  
The LIN driver is a low side MOSFET with internal current  
limitation and thermal shutdown. An internal pull-up resistor  
with a serial diode structure is integrated, so no external pull-  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
23  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
RXD Pin  
SS3, SS2, SS1, and SS0—A/D Input Select Bits  
These read/write bits select the input to the ADC in the  
microcontroller according to Table 7. Reset clears SS3, SS2,  
SS1, and SS0 bits.  
The RXD transceiver pin is the MCU interface, which  
reports the state of the LIN bus voltage. LIN HIGH (recessive  
state) is reported by a high level on RXD, LIN LOW (dominant  
state) by a low level on RXD.  
Table 7. Analog Multiplexer Configuration Register  
STOP Mode/Wake-up Feature  
SS3  
0
SS2  
0
SS1  
0
SS0  
0
Channel  
During STOP mode operation the transmitter of the  
physical layer is disabled. The receiver pin is still active and  
able to detect wake-up events on the LIN bus line.If LIN  
interrupt is enabled (LINIE bit in the Interrupt Mask Register  
is set), a falling edge on the LIN line causes an interrupt. This  
interrupt switches on the main voltage regulator and  
generates a system wake-up.  
Current Recopy HB1  
Current Recopy HB2  
Current Recopy HB3  
Current Recopy HB4  
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
V
SUP Prescaler  
Analog Multiplexer/ADOUT Pin  
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
Temperature Sensor  
The ADOUT pin is the analog output interface to the ADC  
of the MCU (see Figure 2). An analog multiplexer is used to  
read six internal diagnostic analog voltages.  
Current Recopy  
The analog multiplexer is connected to the four low side  
current sense circuits of the half-bridges. These sense  
circuits offer a voltage proportional to the current through the  
low side MOSFET. High or low resolution is selectable: 5.0 V/  
2.5 A or 5.0 V/500 mA, respectively. (Refer to Half-bridge  
Current Recopy on page 27.)  
Not Used  
Temperature Sensor  
The 908E626 includes an on-chip temperature sensor.  
This sensor offers a voltage that is proportional to the actual  
chip junction temperature.  
VSUP Prescaler  
Power Output Register (POUT)  
The V  
prescaler permits the reading or measurement  
SUP  
of the external supply voltage. The output of this voltage is  
VSUP/RATIOVSUP  
Register Name and Address: P  
- $0b  
OUT  
.
Bit7  
0
6
0
5
4
3
2
1
Bit0  
The different internal diagnostic analog voltages can be  
selected with the ADMUX Register.  
Read  
Write  
Reset  
Notes  
0
0
0
0
0
(17)  
HVDD  
ON  
(17)  
(17)  
(17)  
(17)  
Analog Multiplexer Configuration Register (ADMUX)  
0
0
0
0
0
0
0
0
Register Name and Address: ADMUX - $07  
17. This bit must always be set to 0.  
Bit7  
0
6
0
5
0
4
0
3
SS3  
0
2
SS2  
0
1
SS1  
0
Bit0  
SS0  
0
HVDDON—HVDD On Bit  
Read  
Write  
Reset  
This read/write bit enables HVDD output. Reset clears the  
HVDDON bit.  
0
0
0
0
• 1 = HVDD enabled.  
• 0 = HVDD disabled.  
908E626  
Analog Integrated Circuit Device Data  
24  
Freescale Semiconductor  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
HB1:HB4 output features:  
HALF-BRIDGES  
• Short-circuit (over-current) protection on high side and  
low side MOSFETs.  
• Current recopy feature (low side MOSFET).  
• Over-temperature protection.  
• Over-voltage and under-voltage protection.  
• Current limitation feature (low side MOSFET).  
Outputs HB1:HB4 provide four low resistive half-bridge  
output stages. The half-bridges can be used in H-Bridge, high  
side, or low side configurations.  
Reset clears all bits in the H-Bridge Output Register  
(HBOUT) owing to the fact that all half-bridge outputs are  
switched off.  
VSUP  
On/Off  
High Side Driver  
Charge Pump,  
Over-temperature Protection,  
Over-current Protection  
Status  
BEMF  
Control  
HBx  
On/Off  
Status  
Low Side Driver  
Current Recopy,  
Current Limitation,  
Over-current Protection  
Current  
Limit  
GND  
Figure 12. Half-bridge Push-Pull Output Driver  
Half-bridge Control  
Half-bridge Output Register (HBOUT)  
Each output MOSFET can be controlled individually. The  
general enable of the circuitry is done by setting PSON in the  
System Control Register (SYSCTL). HBx_L and HBx_H form  
one half-bridge. It is not possible to switch on both MOSFETs  
in one half-bridge at the same time. If both bits are set, the  
high side MOSFET has a higher priority.  
Register Name and Address: HBOUT - $01  
Bit7  
6
5
4
3
2
1
Bit0  
Read  
Write  
Reset  
HB4_H HB4_L HB3_H HB3_L HB2_H HB2_L HB1_H HB1_L  
0
0
0
0
0
0
0
0
To avoid both MOSFETs (high side and low side) of one  
half-bridge being on at the same time, a break-before-make  
circuit exists.Switching the high side MOSFET on is inhibited  
HBx_L—Low Side On/Off Bits  
These read/write bits turn on the low side MOSFETs.  
Reset clears the HBx_L bits.  
as long as the potential between gate and V is not below a  
SS  
certain threshold. Switching the low side MOSFET on is  
blocked as long as the potential between gate and source of  
the high side MOSFET did not fall below a certain threshold.  
• 1 = Low side MOSFET turned on for half-bridge output  
x.  
• 0 = Low side MOSFET turned off for half-bridge output  
x.  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
25  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
HBx_H—High Side On/Off Bits  
and the load characteristics. The FGEN input provides the  
PWM frequency, whereas the duty cycle is controlled by the  
load characteristics.  
These read/write bits turn on the high side MOSFETs.  
Reset clears the HBx_H bits.  
The recommended frequency range for the FGEN and the  
PWM is 0.1 kHz to 20 kHz.  
• 1 = High side MOSFET turned on for half-bridge output  
x.  
• 0 = High side MOSFET turned on for half-bridge output  
x.  
Functionality  
Each low side MOSFET switches off if a current above the  
selected current limit was detected. The 908E626 offers five  
different current limits (refer to Table 8, for current limit  
values). The low side MOSFET switches on again if a rising  
edge on the FGEN input was detected (Figure 13).  
HALF-BRIDGE CURRENT LIMITATION  
Each low side MOSFET offers a current limit or constant  
current feature. This features is realized by a pulse width  
modulation on the low side MOSFET. The pulse width  
modulation on the outputs is controlled by the FGEN input  
H-Bridge low side  
MOSFET will be switched  
off if select current limit is  
reached.  
Coil Current  
H-Bridge low side  
MOSFET will be turned on  
with each rising edge of  
the FGEN input.  
t (µs)  
t (µs)  
t (µs)  
Half-bridge  
Low Side Output  
FGEN Input  
(MCU PWM  
Signal)  
Minimum 50 µs  
Figure 13. Half-bridge Current Limitation  
908E626  
Analog Integrated Circuit Device Data  
26  
Freescale Semiconductor  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
Offset Chopping  
and HB4 will switch on the low side MOSFETs with the falling  
edge on the FGEN input. In step motor applications, this  
feature allows the reduction of EMI due to a reduction of the  
di/dt (Figure 14).  
If bit OFC_EN in the H-bridge Control Register (HBCTL) is  
set, HB1 and HB2 will continue to switch on the low side  
MOSFETs with the rising edge of the FGEN signal and HB3  
Coil1 Current  
Coil2 Current  
FGEN Input  
(MCU PWM  
Signal)  
HB1  
Coil1…..  
HB2  
HB3  
Coil2…..  
HB4  
Current in  
VSUP Line  
Figure 14. Offset Chopping for Step Motor Control  
HALF-BRIDGE CURRENT RECOPY  
HALF-BRIDGE BEMF GENERATION  
Each low side MOSFET has an additional sense output to  
allow a current recopy feature. This sense source is internally  
connected to a shunt resistor. The drop voltage is amplified  
and switched to the analog multiplexer.  
The BEMF output is set to “1” if a recirculation current is  
detected in any half-bridge. This recirculation current flows  
via the two freewheeling diodes of the power MOSFETs. The  
BEMF circuitry detects that and generates a HIGH on the  
BEMF output as long as a recirculation current is detected.  
This signal provides a flexible and reliable detection of stall in  
step motor applications. For this the BEMF circuitry takes  
advantage of the instability of the electrical and mechanical  
behavior of a step motor when blocked. In addition the signal  
can be used for open load detection (absence of this signal)  
(see Figure 15).  
The factor for the current sense amplification can be  
selected via bit CSA in the System Control Register.  
• CSA = 1: Low resolution selected (500 mA  
measurement range).  
• CSA = 0: High resolution selected (2.5 A measurement  
range).  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
27  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
Coil Current  
1
Voltage on  
1
BEMF Signal  
Figure 15. BEMF Signal Generation  
by the low and high voltage interrupt circuitry. If one of these  
flags (LVF, HVF) is set, the outputs are automatically  
disabled.  
HALF-BRIDGE OVER-TEMPERATURE  
PROTECTION  
The half-bridge outputs provide an over-temperature  
prewarning with the HTF in the Interrupt Flag Register (IFR).  
In order to protect the outputs against over-temperature, the  
High Temperature Reset must be enabled. If this value is  
reached, the part generates a reset and disables all power  
outputs.  
The over-voltage/under-voltage status flags are cleared  
(and the outputs re-enabled) by writing a logic [1] to the LVF/  
HVF flags in the Interrupt Flag Register or by reset. Clearing  
this flag is useless as long as a high or low voltage condition  
is present.  
Half-bridge Control Register (HBCTL)  
HALF-BRIDGE OVER-CURRENT PROTECTION  
The half-bridges are protected against short to GND, short  
to VSUP, and load shorts.  
Register Name and Address: HBCTL - $02  
Bit7  
6
5
0
4
0
3
0
2
1
Bit0  
In the event an over-current on the high side is detected,  
the high side MOSFETs on all HB high side MOSFETs are  
switched off automatically. In the event an over-current on the  
low side is detected, all HB low side MOSFETs are switched  
off automatically. In both cases, the over-current status flag  
HB_OCF in the System Status Register (SYSSTAT) is set.  
Read  
Write  
Reset  
OFC_EN CSA  
CLS2 CLS1 CLS0  
0
0
0
0
0
0
0
0
OFC_EN—H-bridge Offset Chopping Enable Bit  
The over-current status flag is cleared (and the outputs re-  
enabled) by writing a logic [1] to the HB_OCF flag in the  
System Status Register or by reset.  
This read/write bit enables offset chopping. Reset clears  
the OFC_EN bit.  
• 1 = Offset chopping enabled.  
• 0 = Offset chopping disabled.  
HALF-BRIDGE OVER-VOLTAGE/UNDER-  
VOLTAGE  
The half-bridge outputs are protected against under-  
voltage and over-voltage conditions. This protection is done  
908E626  
Analog Integrated Circuit Device Data  
28  
Freescale Semiconductor  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
CSA—H-bridges Current Sense Amplification Select Bit  
PSON—Power Stages On Bit  
This read/write bit selects the current sense amplification  
of the H-bridges. Reset clears the CSA bit.  
This read/write bit enables the power stages (half-bridges,  
LIN transmitter and HVDD output). Reset clears the PSON  
bit.  
• 1 = Current sense amplification set for measuring 0.5 A.  
• 0 = Current sense amplification set for measuring 2.5 A.  
• 1 = Power stages enabled.  
• 0 = Power stages disabled.  
CLS2:CLS0—H-Bridge Current Limitation Selection Bits  
SRS0:SRS1—LIN Slew Rate Selection Bits  
These read/write bits select the current limitation value  
according to Table 8. Reset clears the CLS2:CLS0 bits.  
These read/write bits enable the user to select the  
appropriate LIN slew rate for different baud rate  
configurations as shown in Table 9.  
Table 8. H-Bridge Current Limitation Value Selection  
Bits  
The high speed slew rates are used, for example, for  
programming via the LIN and are not intended for use in the  
application.  
CLS2  
CLS1  
CLS0  
Current Limit  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table 9. LIN Slew Rate Selection Bits  
No Limit  
SRS1  
SRS0  
LIN Slew Rate  
Initial Slew Rate (20 kBaud)  
Slow Slew Rate (10 kBaud)  
High Speed II (8x)  
0
0
1
1
0
1
0
1
55 mA (typ)  
260 mA (typ)  
370 mA (typ)  
550 mA (typ)  
740 mA (typ)  
High Speed I (4x)  
Go to STOP Mode Bit (GS)  
This write-only bit instructs the 908E626 to power down  
and go into STOP mode. Reset or CPU interrupt requests  
clear the GS bit.  
Switchable VDD Outputs  
The HVDD pin is a switchable VDD output pin. It can be  
• 1 = Power down and go into STOP mode  
• 0 = Not in STOP mode  
used for driving external circuitry that requires a V voltage.  
DD  
The output is enabled with bit PSON in the System Control  
Register and can be switched on/off with bit HVDDON in the  
Power Output Register. Low or high voltage conditions (LVI/  
HVI) have no influence on this circuitry.  
System Status Register (SYSSTAT)  
Register Name and Address: SYSSTAT - $0c  
Bit7  
6
5
4
3
2
1
Bit0  
HTF  
HVDD Over-temperature Protection  
Read  
Write  
Reset  
LINCL  
LVF  
HVF  
HVDD  
_OCF  
HB_  
OCF  
Over-temperature protection is enabled if the high  
temperature reset is enabled.  
0
0
0
0
0
0
0
0
0
0
HVDD Over-current Protection  
LINCL — LIN Current Limitation Bit  
The HVDD output is protected against over-current. In the  
event the over-current limit is or was reached, the output  
automatically switches off and the HVDD over-current flag in  
the System Status Register is set.  
This read-only bit is set if the LIN transmitter operates in  
current limitation region. Due to excessive power dissipation  
in the transmitter, software is advised to turn the transmitter  
off immediately.  
• 1 = Transmitter operating in current limitation region.  
• 0 = Transmitter not operating in current limitation  
region.  
System Control Register (SYSCTL)  
Register Name and Address: SYSCTL - $03  
Bit7  
6
5
4
0
3
0
2
0
1
0
Bit0  
0
HVDD_OCF—HVDD Output Over-current Flag Bit  
Read  
Write  
Reset  
This read/write flag is set on an over-current condition at  
the HVDD pin. Clear HVDD_OCF and enable the output by  
writing a logic [1] to the HVDD_OCF Flag. Reset clears the  
PSON SRS1 SRS0  
GS  
0
0
0
0
0
0
0
0
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
29  
FUNCTIONAL DEVICE OPERATION  
OPERATIONAL MODES  
HVDD_OCF bit. Writing a logic [0] to HVDD_OCF has no  
effect.  
To prevent a watchdog reset, the watchdog timeout  
counter must be reset before it reaches the end value. This is  
done by a write to the AWDRST bit in the AWDCTL Register.  
• 1 = Over-current condition on HVDD has occurred.  
• 0 = No over-current condition on HVDD has occurred.  
PERIODIC INTERRUPT  
LVF—Low Voltage Bit  
Periodic interrupt is only available in STOP mode. It is  
enabled by setting the AWDIE bit in the AWDCTL Register. If  
AWDIE is set, the AWD wakes up the system after a fixed  
period of time. This time period can be selected with bit  
AWDR in the AWDCTL Register.  
This read only bit is a copy of the LVF bit in the Interrupt  
Flag Register.  
• 1 = Low voltage condition has occurred.  
• 0 = No low voltage condition has occurred.  
Autonomous Watchdog Control Register (AWDCTL)  
HVF—High Voltage Sensor Bit  
This read-only bit is a copy of the HVF bit in the Interrupt  
Flag Register.  
Register Name and Address: AWDCTL - $0a  
Bit7  
0
6
0
5
4
AWDRE  
0
3
AWDIE  
0
2
1
0
0
Bit0  
AWDR  
0
• 1 = High voltage condition has occurred.  
• 0 = No high voltage condition has occurred.  
0
AWDRST  
0
Read  
Write  
0(18)  
0
HB_OCF—H-Bridge Over-current Flag Bit  
0
0
Reset  
This read /write flag is set on an over-current condition at  
the H-Bridges. Clear HB_OCF and enable the H-Bridge  
driver by writing a logic [1] to HB_OCF. Reset clears the  
HB_OCF bit. Writing a logic [0] to HB_OCF has no effect.  
Notes  
18. This bit must always be set to 0.  
AWDRST—Autonomous Watchdog Reset Bit  
• 1 = Over-current condition on H-Bridges has occurred.  
• 0 = No over-current condition on H-Bridges has  
occurred.  
This write-only bit resets the Autonomous Watchdog  
timeout period. AWDRST always reads 0. Reset clears  
AWDRST bit.  
• 1 = Reset AWD and restart timeout period.  
• 0 = No effect.  
HTF—Over-temperature Status Bit  
This read-only bit is a copy of the HTF bit in the Interrupt  
Flag Register.  
AWDRE—Autonomous Watchdog Reset Enable Bit  
• 1 = Over-temperature condition has occurred.  
• 0 = No over-temperature condition has occurred.  
This read/write bit enables resets on AWD timeouts. A  
reset on the RST_A is asserted when the Autonomous  
Watchdog has reached the timeout and the Autonomous  
Watchdog is enabled. AWDRE is one-time setable (write  
once) after each reset. Reset clears the AWDRE bit.  
AUTONOMOUS WATCHDOG (AWD)  
The Autonomous Watchdog module consists of three  
functions:  
• 1 = Autonomous watchdog enabled.  
• 0 = Autonomous watchdog disabled.  
• Watchdog function for the CPU in RUN mode  
• Periodic interrupt function in STOP mode  
Autonomous Watchdog Interrupt Enable Bit (AWDIE)  
The Autonomous Watchdog module allows to protect the  
CPU against code runaways.  
This read/write bit enables CPU interrupts by the  
Autonomous Watchdog timeout flag, AWFD. IRQ_A is only  
asserted when the device is in STOP mode. Reset clears the  
AWDIE bit.  
The AWD is enabled if AWDIE, AWDRE in the AWDCTL  
Register is set. If this bit is cleared, the AWD oscillator is  
disabled and the watchdog switched off.  
• 1 = CPU interrupt requests from AWDF enabled  
• 0 = CPU interrupt requests from AWDF disabled  
Watchdog  
The watchdog function is only available in RUN mode. On  
setting the AWDRE bit, watchdog functionality in RUN mode  
is activated. Once this function is enabled, it is not possible to  
disable it via software.  
AWDR—Autonomous Watchdog Rate Bit  
This read/write bit selects the clock rate of the  
Autonomous Watchdog. Reset clears the AWDR bit.  
• 1 = Fast rate selected (10 ms).  
• 0 = Slow rate selected (20 ms).  
If the timer reaches end value and AWDRE is set, a  
system reset is initiated. Operations of the watchdog function  
cease in STOP mode. Normal operation will be continued  
when the system is back to RUN mode.  
908E626  
Analog Integrated Circuit Device Data  
30  
Freescale Semiconductor  
FUNCTIONAL DEVICE OPERATION  
FACTORY TRIMMING AND CALIBRATION  
RUN Mode  
VOLTAGE REGULATOR  
The 908E626 chip contains a low power, low drop voltage  
regulator to provide internal power and external power for the  
During RUN mode, the main voltage regulator is on. It  
provides a regulated supply to all digital sections.  
MCU. The V regulator accepts a unregulated input supply  
DD  
and provides a regulated VDD supply to all digital sections of  
the device. The output of the regulator is also connected to  
the VDD pin to provide the 5.0 V to the microcontroller.  
STOP Mode  
During STOP mode the STOP mode regulator supplies a  
regulated output voltage. The STOP mode regulator has a  
very limited output current capability. The output voltage will  
be lower than the output voltage of the main voltage  
regulator.  
Note: Under loss of power conditions, the discharge of the  
V
capacitor may occur relatively slow. Based on the  
DD  
selected external components and external VDD load,  
additional external load may be required guarantee the MCU  
POR threshold being reached before the next power up.  
FACTORY TRIMMING AND CALIBRATION  
To enhance the ease-of-use of the 908E626, various  
parameters (e.g. ICG trim value) are stored in the flash  
memory of the device. The following flash memory locations  
are reserved for this purpose and might have a value different  
from the empty (0xFF) state:  
Internal Clock Generator (ICG) Trim Value  
The internal clock generator (ICG) module is used to  
create a stable clock source for the microcontroller without  
using any external components. The untrimmed frequency of  
the low frequency base clock (IBASE), will vary as much as  
±25%, due to process, temperature, and voltage  
dependencies. To compensate this dependencies a ICG trim  
values is located at address $FDC2. After trimming the ICG  
is a range of typ. ±2% (±3% max.) at nominal conditions  
• 0xFD80:0xFDDF Trim and Calibration Values  
• 0xFFFE:0xFFFF Reset Vector  
In the event the application uses these parameters, one  
has to take care not to erase or override these values. If these  
parameters are not used, these flash locations can be erased  
and otherwise used.  
(filtered (100 nF) and stabilized (4.7 F) V = 5.0 V,  
DD  
T
~25 °C) and will vary over temperature and voltage  
AMBIENT  
(VDD) as indicated in the 68HC908EY16 datasheet.  
To trim the ICG this values has to be copied to the ICG  
Trim Register ICGTR at address $38 of the MCU.  
Trim Values  
Below the usage of the trim values located in the flash  
memory is explained  
Important The value has to be copied after every reset.  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
31  
TYPICAL APPLICATIONS  
TYPICAL APPLICATIONS  
DEVELOPMENT SUPPORT  
As the 908E626 has the MC68HC908EY16 MCU  
is soldered onto a pcb board, and second, after the IC is  
soldered onto the pc board.  
embedded, typically all the development tools available for  
the MCU also apply for this device. However, due to the fact  
of the additional analog die circuitry and the nominal +12 V  
supply voltage some additional items have to be considered:  
Chip level programming  
At the Chip level, the easiest way is to only power the MCU  
with +5.0 V (see Figure 16), and not provide the analog chip  
with VSUP. In this setup, all the analog pins should be left  
open (e.g. VSUP[1:3]), and interconnections between the  
MCU and the analog die have to be separated (e.g. IRQ -  
IRQ_A).  
• nominal 12 V rather than 5.0 V or 3.0 V supply  
• high voltage V  
might be applied not only to IRQ pin,  
TST  
but also the IRQ_A pin  
For a detailed information on the MCU related  
development support, see the MC68HC908EY16 datasheet -  
section, development support.  
This mode is well described in the MC68HC908EY16  
datasheet - section, development support.  
The programming is principally possible at two stages in  
the manufacturing process - first on chip level, before the IC  
VSUP[1:3]  
GND[1:2]  
VDD  
VSS  
+5V  
VREFH  
VDDA  
EVDD  
RST  
RST_A  
+5V  
100nF  
4.7µF  
VTST  
IRQ  
VREFL  
VSSA  
EVSS  
1
16  
C1+  
VCC  
IRQ_A  
MM908E626  
+
+
+
1µF  
1µF  
1µF  
1µF  
3
4
15  
2
C1-  
GND  
V+  
1µF  
+
C2+  
9.8304MHz CLOCK  
6
V-  
+5V  
CLK  
10k  
PTC4/OSC1  
PTA0/KBD0  
MAX232  
5
C2-  
PTB4/AD4  
+5V  
RS232  
DB-9  
+
10k  
74HC125  
10k  
10k  
PTA1/KBD1  
PTB3/AD3  
2
3
5
7
8
10  
9
6
5
DATA  
T2OUT  
R2IN  
T2IN  
74HC125  
4
R2OUT  
3
2
1
Figure 16. Normal Monitor Mode Circuit (MCU only)  
It is also possible to supply the whole system with V  
(12 V) instead as described in Figure 17.  
PCB level programming  
SUP  
If the IC is soldered onto the pc board, it is typically not  
possible to separately power the MCU with +5.0 V. The  
whole system has to be powered up providing V  
Figure 17).  
(see  
SUP  
908E626  
Analog Integrated Circuit Device Data  
32  
Freescale Semiconductor  
TYPICAL APPLICATIONS  
VDD  
VSUP  
VSUP[1:3]  
GND[1:2]  
VDD  
VSS  
+
100nF  
47µF  
VREFH  
VDDA  
EVDD  
RST  
RST_A  
VDD  
100nF  
4.7µF  
VTST  
IRQ  
VREFL  
VSSA  
EVSS  
1
16  
C1+  
VCC  
IRQ_A  
MM908E626  
+
+
+
1µF  
1µF  
1µF  
1µF  
3
4
15  
2
C1-  
GND  
V+  
1µF  
+
C2+  
9.8304MHz CLOCK  
6
V-  
VDD  
CLK  
PTC4/OSC1  
PTA0/KBD0  
10k  
MAX232  
5
C2-  
PTB4/AD4  
VDD  
RS232  
DB-9  
+
10k  
74HC125  
10k  
10k  
PTA1/KBD1  
PTB3/AD3  
2
3
5
7
8
10  
9
6
5
DATA  
T2OUT  
R2IN  
T2IN  
74HC125  
4
R2OUT  
3
2
1
Figure 17. Normal Monitor Mode Circuit  
Table 10 summarizes the possible configurations and the  
necessary setups.  
Table 10. Monitor Mode Signal Requirements and Options  
Serial  
Communication  
Mode  
Selection  
Communication Speed  
Normal  
Request  
Timeout  
Reset  
Vector  
Mode IRQ RST  
ICG  
COP  
External  
Clock  
Baud  
Rate  
Bus  
Frequency  
PTA0  
PTA1 PTB3 PTB4  
Normal VTST VDD  
Monitor  
X
1
0
0
0
1
OFF disabled disabled 9.8304  
MHz  
2.4576  
MHz  
9600  
9600  
Forced VDD VDD $FFFF  
Monitor  
1
X
X
OFF disabled disabled 9.8304  
MHz  
2.4576  
MHz  
(blank)  
GND  
ON disabled disabled  
—
Nominal Nominal  
1.6 MHz 6300  
User  
VDD VDD  
not  
$FFFF  
X
X
X
X
ON enabled enabled  
—
Nominal Nominal  
1.6 MHz 6300  
(not  
blank)  
Notes  
19. PTA0 must have a pull-up resistor to VDD in monitor mode  
20. External clock is a 4.9152 MHz, 9.8304 MHz or 19.6608 MHz canned oscillator on OCS1  
21. Communication speed with external clock is depending on external clock value. Baud rate is bus frequency / 256  
22. X = don’t care  
23. VTST is a high voltage VDD + 3.5 V VTST VDD + 4.5 V  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
33  
TYPICAL APPLICATIONS  
EMC/EMI RECOMMENDATIONS  
This paragraph gives some device specific  
MCU digital supply pins (EVDD and EVSS)  
recommendations to improve EMC/EMI performance.  
Further generic design recommendations can be found on  
the Freescale web site, www.freescale.com.  
Fast signal transitions on MCU pins place high, short  
duration current demands on the power supply. To prevent  
noise problems, take special care to provide power supply  
bypassing at the MCU. It is recommended that a high quality  
ceramic decoupling capacitor be placed between these pins.  
VSUP Pins (VSUP1:VSUP3)  
Its recommended to place a high quality ceramic  
decoupling capacitor close to the VSUP pins to improve  
EMC/EMI behavior.  
MCU analog supply pins (VREFH, VDDA, VREFL, and  
VSSA)  
To avoid noise on the analog supply pins its important to  
take special care on the layout. The MCU digital and analog  
supplies should be tied to the same potential via separate  
traces and connected to the voltage regulator output.  
LIN Pin  
For DPI (Direct Power Injection) and ESD (Electrostatic  
Discharge) its recommended to place a high quality ceramic  
decoupling capacitor near the LIN pin. An additional varistor  
will further increase the immunity against ESD. A ferrite in the  
LIN line will suppress some of the noise induced.  
Figure 18 and Figure 19 show the recommendations on  
schematics and layout level and Table 11 indicates  
recommended external components and layout  
considerations.  
Voltage Regulator Output Pins (VDD and AGND)  
Use a high quality ceramic decoupling capacitor to  
stabilize the regulated voltage.  
D1  
VSUP  
VSUP1  
VSUP2  
VSUP3  
VDD  
VSS  
+
C2  
C1  
VREFH  
VDDA  
EVDD  
L1  
LIN  
LIN  
V1  
C5  
C3  
C4  
EVSS  
VSSA  
MM908E625  
GND1  
GND2  
VREFL  
Figure 18. EMC/EMI Recommendations  
908E626  
Analog Integrated Circuit Device Data  
34  
Freescale Semiconductor  
TYPICAL APPLICATIONS  
1
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
2
3
4
5
6
7
VREFH  
VDDA  
EVDD  
EVSS  
VSSA  
VREFL  
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
NC  
908E626  
VSS  
VDD  
C4  
LIN  
NC  
NC  
LIN  
GND  
VBAT  
L1  
NC  
VSUP1  
GND1  
VSUP3  
GND2  
VSUP2  
C2  
Figure 19. PCB Layout Recommendations  
.
Table 11. Component Value Recommendation  
Component  
Recommended Value(24)  
Comments / Signal Routing  
C1  
C2  
C3  
Bulk Capacitor  
100 nF, SMD Ceramic, Low ESR  
100 nF, SMD Ceramic, Low ESR  
Close (<5.0 mm) to the VSUP1, VSUP2 pins with good ground return  
Close (<3.0 mm) to the digital supply pins (EVDD, EVSS) with good  
ground return.  
The positive analog (VREFH, VDDA) and the digital (EVDD) supply  
should be connected right at the C3.  
C4  
C5  
4,7 F, SMD Ceramic, Low ESR  
Bulk Capacitor  
180 pF, SMD Ceramic, Low ESR  
Close (<5.0 mm) to LIN pin.  
Total Capacitance on LIN has to be below 220 pF.  
(CTOTAL = CLIN-PIN + C5 + CVARISTOR ~ 10 pF + 180 pF + 15 pF)  
V1(25)  
L1(25)  
Varistor Type TDK AVR-M1608C270MBAAB  
SMD Ferrite Bead Type TDK MMZ2012Y202B  
Optional (close to LIN connector)  
Optional, (close to LIN connector)  
Notes  
24. Freescale does not assume liability, endorse, or want components from external manufactures that are referenced in circuit drawings  
or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their  
application.  
25. Components are recommended to improve EMC and ESD performance.  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
35  
PACKAGING  
PACKAGING DIMENSIONS  
PACKAGING  
PACKAGING DIMENSIONS  
Important: For the most current revision of the package, visit www.freescale.com and perform a keyword search on  
98ARL10519D. Dimensions shown are provided for reference ONLY.  
EK SUFFIX (PB-FREE)  
54-PIN  
98ARL10519D  
ISSUE D  
908E626  
Analog Integrated Circuit Device Data  
36  
Freescale Semiconductor  
PACKAGING  
PACKAGING DIMENSIONS  
EK SUFFIX (PB-FREE)  
54-PIN  
98ARL10519D  
ISSUE D  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
37  
PACKAGING  
PACKAGING DIMENSIONS  
EK SUFFIX (PB-FREE)  
54-PIN  
98ARL10519D  
ISSUE D  
908E626  
Analog Integrated Circuit Device Data  
38  
Freescale Semiconductor  
ADDITIONAL DOCUMENTATION  
THERMAL ADDENDUM (REV 1.0)  
ADDITIONAL DOCUMENTATION  
908E626  
THERMAL ADDENDUM (REV 1.0)  
Introduction  
This thermal addendum ia provided as a supplement to the MM908E626  
technical data sheet. The addendum provides thermal performance information  
that may be critical in the design and development of system applications. All  
electrical, application and packaging information is provided in the data sheet.  
54-PIN  
SOICW-EP  
Package and Thermal Considerations  
This MM908E626 is a dual die package. There are two heat sources in the  
package independently heating with P and P . This results in two junction  
1
2
temperatures, T and T , and a thermal resistance matrix with RJAmn  
.
J1  
J2  
For m, n = 1, RJA11 is the thermal resistance from Junction 1 to the reference  
temperature while only heat source 1 is heating with P .  
1
98ARL10519D  
54-PIN SOICW-EP  
For m = 1, n = 2, RJA12 is the thermal resistance from Junction 1 to the  
reference temperature while heat source 2 is heating with P . This applies to  
2
RJ21 and RJ22, respectively.  
Note For package dimensions, refer to  
98ARL10519D.  
RJA11 RJA12  
RJA21 RJA22  
T
T
P
P
J1  
J2  
1
2
.
=
The stated values are solely for a thermal performance comparison of one  
package to another in a standardized environment. This methodology is not meant to and will not predict the performance of a  
package in an application-specific environment. Stated values were obtained by measurement and simulation according to the  
standards listed below.  
Standards  
Table 12. Thermal Performance Comparison  
1 = Power Chip, 2 = Logic Chip [C/W]  
1.0  
Thermal  
m = 1,  
n = 1  
m = 1, n = 2  
m = 2, n = 1  
m = 2,  
n = 2  
Resistance  
1.0  
(1)(2)  
0.2  
RJAmn  
RJBmn  
RJAmn  
RJCmn  
23  
9.0  
52  
20  
6.0  
47  
0
24  
10  
52  
2.0  
0.2  
(2)(3)  
(1)(4)  
(5)  
* All measurements  
are in millimeters  
Soldermast  
openings  
1.0  
Notes:  
Thermal vias  
connected to top  
buried plane  
1. Per JEDEC JESD51-2 at natural convection, still air  
condition.  
2. 2s2p thermal test board per JEDEC JESD51-7and  
JESD51-5.  
54 Terminal SOIC-EP  
0.65 mm Pitch  
17.9 mm x 7.5 mm Body  
10.3 mm x 5.1 mm Exposed Pad  
3. Per JEDEC JESD51-8, with the board temperature on the  
center trace near the power outputs.  
4. Single layer thermal test board per JEDEC JESD51-3 and  
JESD51-5.  
Figure 20. Thermal Land Pattern for Direct Thermal  
Attachment Per JEDEC JESD51-5Thermal Test Board  
5. Thermal resistance between the die junction and the  
exposed pad, “infinite” heat sink attached to exposed pad.  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
39  
ADDITIONAL DOCUMENTATION  
THERMAL ADDENDUM (REV 1.0)  
A
A
PTB7/AD7/TBCH1  
PTB6/AD6/TBCH0  
PTA0/KBD0  
PTA1/KBD1  
PTA2/KBD2  
FLSVPP  
PTA3/KBD3  
PTA4/KBD4  
VREFH  
VDDA  
EVDD  
EVSS  
1
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
2
PTC4/OSC1  
PTC3/OSC2  
PTC2/MCLK  
3
4
5
PTB5/AD5  
PTB4/AD4  
PTB3/AD3  
6
7
8
IRQ  
9
RST  
10  
PTB1/AD1  
PTD0/TACH0/BEMF  
VSSA  
11  
VREFL  
PTE1/RXD  
RXD  
VSS  
NC  
VDD  
NC  
NC  
NC  
HVDD  
NC  
HB4  
VSUP3  
GND2  
HB3  
12  
PTD1/TACH1  
13  
Exposed  
Pad  
NC  
FGEN  
BEMF  
RST_A  
IRQ_A  
SS  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
LIN  
NC  
NC  
HB1  
VSUP1  
GND1  
HB2  
VSUP2  
NC  
908E626 Pin Connections  
54-Pin SOICW-EP  
0.65 mm Pitch  
17.9 mm x 7.5 mm Body  
10.3 mm x 5.1 mm Exposed Pad  
Figure 21. Thermal Test Board  
Device on Thermal Test Board  
Table 13. Thermal Resistance Performance  
Material:  
Single layer printed circuit board  
FR4, 1.6 mm thickness  
1 = Power Chip, 2 = Logic Chip (C/W)  
Area A  
(mm2)  
Thermal  
m = 1,  
n = 1  
m = 1, n = 2  
m = 2, n = 1  
m = 2,  
n = 2  
Cu traces, 0.07 mm thickness  
Resistance  
Outline:  
80 mm x 100 mm board area,  
including edge connector for thermal  
testing  
RJAmn  
0
53  
39  
35  
21  
15  
14  
48  
34  
30  
16  
11  
9.0  
53  
38  
34  
20  
15  
13  
300  
600  
0
Area A:  
Cu heat-spreading areas on board  
surface  
RJSmn  
300  
600  
Ambient Conditions: Natural convection, still air  
RJAis the thermal resistance between die junction and  
ambient air.  
RJSmn is the thermal resistance between die junction and  
the reference location on the board surface near a center  
lead of the package.  
This device is a dual die package. Index m indicates the  
die that is heated. Index n refers to the number of the die  
where the junction temperature is sensed.  
908E626  
Analog Integrated Circuit Device Data  
40  
Freescale Semiconductor  
ADDITIONAL DOCUMENTATION  
THERMAL ADDENDUM (REV 1.0)  
60  
50  
40  
30  
20  
10  
0
R
R
x
JA11  
JA22  
R
= R  
JA21  
JA12  
0
300  
600  
Heat spreading area A [mm²]  
Figure 22. Device on Thermal Test Board RJA  
100  
10  
1
R
R
x
JA11  
JA22  
R
= R  
JA21  
JA12  
0.1  
1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04  
Time[s]  
Figure 23. Transient Thermal Resistance RJA (1.0 W Step Response)  
Device on Thermal Test Board Area A = 600 (mm2)  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
41  
REVISION HISTORY  
REVISION HISTORY  
REVISION  
DATE  
DESCRIPTION OF CHANGES  
•
•
•
•
•
•
Implemented Revision History page  
4.0  
9/2008  
Minor corrections throughout the document  
Updated to current Freescale format and style  
Added MM908E626AVEK to the ordering information  
Corrected package drawing designation  
Added STOP mode  
•
Corrected several non-technical cross-references.  
5.0  
6.0  
7/2009  
9/2011  
•
•
•
•
•
•
•
•
•
•
Corrected text for Autonomous Watchdog Interrupt. Page 17.  
Corrected part number in Go to STOP Mode Bit. Page 30.  
Removed footnotes in register table for SYSCTL and AWDCTL.  
Corrected Figure 4 LIN Timing description.  
Updated Freescale form and style  
Added MM908E626AVPEK to the ordering information.  
Removed the DWB package type.  
Added RoHS image to page 1 and RoHS statement to back page.  
Changed Peak Package Reflow Temperature During Reflow description  
Added note (8)  
•
•
•
Added MM908E626AVPEK to the ordering information  
Removed 908E626AVEK/R2 from the ordering information  
Updated Freescale form and style  
7.0  
4/2012  
•
•
•
Corrected Figure 4, LIN Timing Description, replacing VLIN with VSUP  
Added MM908E626AVEK/R2 to the ordering information  
Corrected broken links within the document.  
8.0  
9.0  
4/2012  
6/2012  
8/2012  
10.0  
908E626  
Analog Integrated Circuit Device Data  
Freescale Semiconductor  
42  
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