MPC5602CF1CLH6R [NXP]

MICROCONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026BCD, LQFP-64;


型号：	MPC5602CF1CLH6R
厂家：	NXP
描述：	MICROCONTROLLER, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, 0.50 MM PITCH, MS-026BCD, LQFP-64 CD
文件：	总106页 (文件大小：1693K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Freescale Semiconductor

Data Sheet: Advance Information

Document Number: MPC5604BC

Rev. 8, 11/2010

MPC5604B/C

MAPBGA–225

QFN12

144 LQFP

208 MAPBGA

15 mm x 15 mm

##_mm_x_##mm

(20 x 20 x 1.4 mm)

(17 x 17 x 1.7 mm)

SOT-343R

PKG-TBD

MPC5604B/C

Microcontroller Data Sheet

##_mm_x_##mm

## mm x ## mm

100 LQFP

64 LQFP

TBD

(14 x 14 x 1.4 mm)

(10 x 10 x 1.4 mm)

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.1 Document overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

1.2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Package pinouts and signal descriptions . . . . . . . . . . . . . . . . . 8

3.1 Package pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

3.2 Pin muxing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . 33

4.3 NVUSRO register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 35

4.5 Recommended operating conditions . . . . . . . . . . . . . . 36

4.6 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 38

4.7 I/O pad electrical characteristics . . . . . . . . . . . . . . . . . 40

4.8 RESET electrical characteristics . . . . . . . . . . . . . . . . . 51

4.9 Power management electrical characteristics . . . . . . . 53

4.10 Low voltage domain power consumption . . . . . . . . . . . 56

4.11 Flash memory electrical characteristics . . . . . . . . . . . . 58

4.12 Electromagnetic compatibility (EMC) characteristics . . 62

4.13 Fast external crystal oscillator (4 to 16 MHz) electrical

characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

4.14 Slow external crystal oscillator (32 kHz) electrical

characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

4.15 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . 69

4.16 Fast internal RC oscillator (16 MHz) electrical

characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.17 Slow internal RC oscillator (128 kHz) electrical

characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4.18 ADC electrical characteristics. . . . . . . . . . . . . . . . . . . . 72

4.19 On-chip peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

Package characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

5.1 Package mechanical data. . . . . . . . . . . . . . . . . . . . . . . 89

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . 100

32-bit MCU family built on the Power Architecture for

automotive body electronics applications

Features

•

Single issue, 32-bit CPU core complex (e200z0)

— Compliant with the Power Architecture

embedded category

— Includes an instruction set enhancement

allowing variable length encoding (VLE) for

code size footprint reduction. With the optional

encoding of mixed 16-bit and 32-bit

instructions, it is possible to achieve significant

code size footprint reduction.

•

Up to 512 KB on-chip code flash supported with the

flash controller

•

64 (4 × 16) KB on-chip data flash memory with ECC

Up to 48 KB on-chip SRAM

Memory protection unit (MPU) with 8 region

descriptors and 32-byte region granularity

•

Interrupt controller (INTC) with 148 interrupt

vectors, including 16 external interrupt sources and

18 external interrupt/wakeup sources

•

Frequency modulated phase-locked loop (FMPLL)

Crossbar switch architecture for concurrent access to

peripherals, flash, or RAM from multiple bus

masters

•

Boot assist module (BAM) supports internal flash

programming via a serial link (CAN or SCI)

Timer supports input/output channels providing a

range of 16-bit input capture, output compare, and

pulse width modulation functions (eMIOS-lite)

•

10-bit analog-to-digital converter (ADC)

3 serial peripheral interface (DSPI) modules

This document contains information on a product under development. Freescale reserves the

right to change or discontinue this product without notice.

Introduction

•

Up to 4 serial communication interface (LINFlex) modules

Up to 6 enhanced full CAN (FlexCAN) modules with configurable buffers

1 inter IC communication interface (I C) module

Up to 123 configurable general purpose pins supporting input and output operations (package dependent)

Real Time Counter (RTC) with clock source from 128 kHz or 16 MHz internal RC oscillator supporting autonomous

wakeup with 1 ms resolution with max timeout of 2 seconds

•

Up to 6 periodic interrupt timers (PIT) with 32-bit counter resolution

1 System Module Timer (STM)

Nexus development interface (NDI) per IEEE-ISTO 5001-2003 Class Two Plus standard

Device/board boundary Scan testing supported with per Joint Test Action Group (JTAG) of IEEE (IEEE 1149.1)

On-chip voltage regulator (VREG) for regulation of input supply for all internal levels

Introduction

1.1

Document overview

This document describes the features of the family and options available within the family members, and highlights important

electrical and physical characteristics of the device. To ensure a complete understanding of the device functionality, refer also

to the device reference manual and errata sheet.

1.2

Description

The MPC5604B/C is a family of next generation microcontrollers built on the Power Architecture embedded category.

The MPC5604B/C family of 32-bit microcontrollers is the latest achievement in integrated automotive application controllers.

It belongs to an expanding family of automotive-focused products designed to address the next wave of body electronics

applications within the vehicle. The advanced and cost-efficient host processor core of this automotive controller family

complies with the Power Architecture embedded category and only implements the VLE (variable-length encoding) APU,

providing improved code density. It operates at speeds of up to 64 MHz and offers high performance processing optimized for

low power consumption. It capitalizes on the available development infrastructure of current Power Architecture devices and

is supported with software drivers, operating systems and configuration code to assist with users implementations.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Table 1. MPC5604B/C device comparison

Device

Feature

MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC560

02BxLH 02BxLL 02BxLQ 02CxLH 02CxLL 03BxLH 03BxLL 03BxLQ 03CxLH 03CxLL 04BxLH 04BxLL 04BxLQ 04CxLH 04CxLL 4BxMG

CPU

e200z0h

Execution

speed²

Static – up to 64 MHz

Code Flash

Data Flash

RAM

256 KB

384 KB

512 KB

64 KB (4 × 16 KB)

24 KB

32 KB

28 KB

40 KB

32 KB

48 KB

MPU

8-entry

ADC

12 ch, 28 ch, 36 ch,

8 ch,

28 ch, 12 ch, 28 ch, 36 ch, 8 ch,

28 ch, 12 ch, 28 ch, 36 ch,

8 ch,

28 ch, 36 ch,

10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit 10-bit

10-bit

CTU

Yes

Total timer I/O³12 ch, 28 ch, 56 ch, 12 ch, 28 ch, 12 ch, 28 ch, 56ch, 12 ch, 28 ch, 12 ch, 28 ch, 56 ch, 12 ch, 28 ch, 56 ch,

eMIOS

16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit

16-bit

• PWM + MC 2 ch

+ IC/OC⁴

5 ch

10 ch

40 ch

6 ch

2 ch

10 ch

0 ch

5 ch

20 ch

3 ch

2 ch

10 ch

0 ch

5 ch

20 ch

3 ch

10 ch

40 ch

6 ch

2 ch

10 ch

0 ch

5 ch

2 ch

10 ch

0 ch

5 ch

20 ch

3 ch

10 ch

40 ch

6 ch

2 ch

10 ch

0 ch

5 ch

20 ch

3 ch

10 ch

• PWM +

IC/OC⁴

10 ch

20 ch

40 ch

6 ch

• IC/OC⁴

0 ch

3 ch

3⁵

3 ch

SCI (LINFlex)

SPI (DSPI)

CAN

2⁶

3⁷

(FlexCAN)

I²C

32 kHz

Yes

oscillator

GPIO⁸

123

Debug

JTAG

Nexus2+

Table 1. MPC5604B/C device comparison (continued)

Device

Feature

MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC56 MPC560

02BxLH 02BxLL 02BxLQ 02CxLH 02CxLL 03BxLH 03BxLL 03BxLQ 03CxLH 03CxLL 04BxLH 04BxLL 04BxLQ 04CxLH 04CxLL 4BxMG

Package

100

144

100

144

100

144

100

208

LQFP⁹LQFP LQFP LQFP⁹LQFP LQFP⁹LQFP LQFP LQFP⁹LQFP LQFP⁹LQFP LQFP LQFP⁹LQFP MAPBG

A¹⁰

Feature set dependent on selected peripheral multiplexing—table shows example implementation

Based on 125 °C ambient operating temperature

Refer to eMIOS section of device reference manual for information on the channel configuration and functions

IC - Input Capture; OC - Output Compare; PWM - Pulse Width Modulation; MC - Modulus counter

SCI0, SCI1 and SCI2 are available. SCI3 is not available.

CAN0, CAN1 are available. CAN2, CAN3, CAN4 and CAN5 are not available.

CAN0, CAN1 and CAN2 are available. CAN3, CAN4 and CAN5 are not available.

I/O count based on multiplexing with peripherals

All 64 LQFPinformation is indicative and must be confirmed during silicon validation.

¹⁰208 MAPBGA available only as development package for Nexus2+

Block diagram

Figure 1 shows a top-level block diagram of the MPC5604B/C device series.

Figure 1. MPC5604B/C series block diagram

SRAM

48 KB

Code Flash Data Flash

512 KB 64 KB

JTAG

JTAG port

Instructions

Nexus port

SRAM

Flash

controller

e200z0h

Nexus 2+

(Master)

Nexus

controller

Data

NMI

(Slave)

(Master)

SIUL

Voltage

regulator

(Slave)

Interrupt requests

from peripheral

blocks

(Slave)

NMI

MPU

registers

INTC

Clocks

CMU

FMPLL

RTC

MC_RGM MC_CGM MC_ME MC_PCU

Peripheral bridge

SSCM

STM

PIT

BAM

SWT

ECSM

SIUL

36 Ch.

ADC

2 x

eMIOS

4 x

LINFlex

3 x

DSPI

6 x

FlexCAN

CTU

I C

Reset control

Interrupt

request

External

interrupt

request

IMUX

WKPU

GPIO and

pad control

Interrupt

request with

wakeup

. . .

I/O

functionality

Legend:

ADC

BAM

Analog-to-Digital Converter

Boot Assist Module

MC_ME

MC_PCU Power Control Unit

MC_RGM Reset Generation Module

Mode Entry Module

FlexCAN Controller Area Network

CMU

CTU

DSPI

Clock Monitor Unit

Cross Triggering Unit

Deserial Serial Peripheral Interface

MPU

Nexus

NMI

Memory Protection Unit

Nexus Development Interface (NDI) Level

Non-Maskable Interrupt

eMIOS

FMPLL

I C

IMUX

INTC

JTAG

Enhanced Modular Input Output System

Frequency-Modulated Phase-Locked Loop

Inter-integrated Circuit Bus

Internal Multiplexer

Interrupt Controller

PIT

RTC

SIUL

SRAM

SSCM

STM

Periodic Interrupt Timer

Real-Time Clock

System Integration Unit Lite

Static Random-Access Memory

System Status Configuration Module

System Timer Module

JTAG controller

LINFlex

ECSM

Serial Communication Interface (LIN support)

Error Correction Status Module

SWT

WKPU

Software Watchdog Timer

Wakeup Unit

MC_CGM Clock Generation Module

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Block diagram

Table 2 summarizes the functions of all blocks present in the MPC5604B/C series of microcontrollers. Please note that the

presence and number of blocks varies by device and package.

Table 2. MPC5604B/C series block summary

Block

Function

Analog-to-digital converter (ADC) Multi-channel, 10-bit analog-to digital-converter

Boot assist module (BAM)

A block of read-only memory containing VLE code which is executed according

to the boot mode of the device

Clock monitor unit (CMU)

Cross triggering unit (CTU)

Monitors clock source (internal and external) integrity

Enables synchronization of ADC conversions with a timer event from the eMIOS

or from the PIT

Deserial serial peripheral interface Provides a synchronous serial interface for communication with external devices

(DSPI)

Error Correction Status Module

(ECSM)

Provides a myriad of miscellaneous control functions for the device including

program-visible information about configuration and revision levels, a reset status

information on memory errors reported by error-correcting codes

Enhanced Direct Memory Access Performs complex data transfers with minimal intervention from a host processor

(eDMA)

via “n” programmable channels.

Enhanced modular input output

system (eMIOS)

Provides the functionality to generate or measure events

Flash memory

Provides non-volatile storage for program code, constants and variables

FlexCAN (controller area network) Supports the standard CAN communications protocol

FMPLL (frequency-modulated

phase-locked loop)

Generates high-speed system clocks and supports programmable frequency

modulation

Internal multiplexer (IMUX) SIU

subblock

Allows flexible mapping of peripheral interface on the different pins of the device

Inter-integrated circuit (I²C™) bus A two wire bidirectional serial bus that provides a simple and efficient method of

data exchange between devices

Interrupt controller (INTC)

JTAG controller

Provides priority-based preemptive scheduling of interrupt requests

Provides the means to test chip functionality and connectivity while remaining

transparent to system logic when not in test mode

LINflex controller

Manages a high number of LIN (Local Interconnect Network protocol) messages

efficiently with a minimum of CPU load

Clock generation module

(MC_CGM)

Provides logic and control required for the generation of system and peripheral

clocks

Mode entry module (MC_ME)

Provides a mechanism for controlling the device operational mode and mode

transition sequences in all functional states; also manages the power control unit,

reset generation module and clock generation module, and holds the

configuration, control and status registers accessible for applications

Power control unit (MC_PCU)

Reduces the overall power consumption by disconnecting parts of the device

from the power supply via a power switching device; device components are

grouped into sections called “power domains” which are controlled by the PCU

Reset generation module

(MC_RGM)

Centralizes reset sources and manages the device reset sequence of the device

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Block diagram

Table 2. MPC5604B/C series block summary (continued)

Function

Block

Memory protection unit (MPU)

Provides hardware access control for all memory references generated in a

device

Nexus development interface

(NDI)

Provides real-time development support capabilities in compliance with the

IEEE-ISTO 5001-2003 standard

Periodic interrupt timer (PIT)

Real-time counter (RTC)

Produces periodic interrupts and triggers

A free running counter used for time keeping applications, the RTC can be

configured to generate an interrupt at a predefined interval independent of the

mode of operation (run mode or low-power mode)

System integration unit (SIU)

Provides control over all the electrical pad controls and up 32 ports with 16 bits

of bidirectional, general-purpose input and output signals and supports up to 32

external interrupts with trigger event configuration

Static random-access memory

(SRAM)

Provides storage for program code, constants, and variables

System status configuration

module (SSCM)

Provides system configuration and status data (such as memory size and status,

device mode and security status), device identification data, debug status port

enable and selection, and bus and peripheral abort enable/disable

System timer module (STM)

Provides a set of output compare events to support AUTOSAR and operating

system tasks

System watchdog timer (SWT)

Wakeup unit (WKPU)

Provides protection from runaway code

The wakeup unit supports up to 18 external sources that can generate interrupts

or wakeup events, of which 1 can cause non-maskable interrupt requests or

wakeup events.

Crossbar (XBAR) switch

Supports simultaneous connections between two master ports and three slave

ports. The crossbar supports a 32-bit address bus width and a 64-bit data bus

width

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Package pinouts and signal descriptions

3.1

Package pinouts

The available LQFP pinouts and the 208 MAPBGA ballmap are provided in the following figures. For pin signal descriptions,

please refer to the device reference manual.

Figure 2. LQFP 64-pin configuration (top view)

48 PA[11]

47 PA[10]

46 PA[9]

45 PA[8]

44 PA[7]

43 PA[3]

42 PB[15]

41 PB[14]

40 PB[13]

39 PB[12]

38 PB[11]

37 PB[7]

36 PB[6]

PB[3]

PC[9]

PA[2]

PA[1]

PA[0]

VPP_TEST

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PC[10]

PB[0]

64 LQFP

PB[5]

PB[1]

PC[6]

34 VDD_HV_ADC

33 VSS_HV_ADC

Figure 3. LQFP 64-pin configuration 5CAN 4LIN (top view)

48 PA[11]

47 PA[10]

46 PA[9]

PB[3]

PC[9]

PA[2]

45 PA[8]

PA[1]

PA[0]

44 PA[7]

43 PF[14]

42 PF[15]

41 PG[0]

VPP_TEST

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PC[10]

PB[0]

40 PG[1]

39 PA[3]

38 PB[15]

37 PB[14]

36 PB[11]

35 PB[7]

64 LQFP

PB[1]

PC[6]

34 VDD_HV_ADC

33 VSS_HV_ADC

1. All 64 LQFPinformation is indicative and must be confirmed during silicon validation.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Package pinouts and signal descriptions

Figure 4. LQFP 100-pin configuration (top view)

PB[3]

PC[9]

PC[14]

PC[15]

PA[2]

PE[0]

PA[1]

PE[1]

PE[8]

PA[11]

PA[10]

PA[9]

PA[8]

PA[7]

VDD_HV

VSS_HV

PA[3]

PB[15]

PD[15]

PB[14]

PD[14]

PB[13]

PD[13]

PB[12]

PD[12]

PB[11]

PD[11]

PD[10]

PD[9]

PB[7]

PB[6]

PB[5]

VDD_HV_ADC

VSS_HV_ADC

PE[9]

PE[10]

PA[0]

PE[11]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PC[11]

PC[10]

PB[0]

100 LQFP

PB[1]

PC[6]

Note:

Availability of port pin alternate functions depends on product selection.

2. All 64 LQFPinformation is indicative and must be confirmed during silicon validation.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Package pinouts and signal descriptions

Figure 5. LQFP 144-pin configuration (top view)

PB[3]

PC[9]

PC[14]

PC[15]

PG[5]

PG[4]

PG[3]

PG[2]

PA[2]

PE[0]

PA[1]

PE[1]

PE[8]

PE[9]

PE[10]

PA[0]

PE[11]

VSS_HV

VDD_HV

VSS_HV

RESET

VSS_LV

VDD_LV

VDD_BV

PG[9]

108

107

106

105

104

103

102

101

100

PA[11]

PA[10]

PA[9]

PA[8]

PA[7]

PE[13]

PF[14]

PF[15]

VDD_HV

VSS_HV

PG[0]

PG[1]

PH[3]

PH[2]

PH[1]

PH[0]

PG[12]

PG[13]

PA[3]

144 LQFP

PB[15]

PD[15]

PB[14]

PD[14]

PB[13]

PD[13]

PB[12]

PD[12]

PB[11]

PD[11]

PD[10]

PD[9]

PB[7]

PB[6]

PB[5]

VDD_HV_ADC

VSS_HV_ADC

PG[8]

PC[11]

PC[10]

PG[7]

PG[6]

PB[0]

PB[1]

PF[9]

PF[8]

PF[12]

PC[6]

Note:

Availability of port pin alternate functions depends on product selection.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Package pinouts and signal descriptions

PE[15]

PG[15]

PE[14]

PG[10]

PG[1]

PH[0]

VDD_HV

MDO3

PC[8]

PC[9]

PC[13]

PB[2]

PH[8]

PE[6]

PH[7]

PH[6]

PH[4]

PH[5]

PE[5]

PE[4]

PC[5]

PC[4]

PE[3]

PE[2]

PC[0]

PH[9]

VSS_LV

PC[2]

PC[3]

PA[5]

PA[6]

PC[12]

PE[7]

PH[10]

PC[1]

PG[11]

PG[14]

PE[12]

PF[14]

PG[0]

PH[1]

PA[11]

PA[9]

PE[13]

PA[10]

PA[8]

PA[7]

PC[14] VDD_HV

PB[3]

PC[15]

PG[3]

PA[1]

PE[10]

VDD_LV VDD_HV

PG[4]

PE[0]

PE[9]

PG[5]

PA[2]

PE[8]

PG[2]

PE[1]

PA[0]

PF[15] VDD_HV

PH[3]

PH[2]

MSEO

MDO1

VSS_HV VSS_HV VSS_HV VSS_HV

VSS_HV PE[11] VDD_HV

MDO2

MDO0

RESET VSS_LV

EVTI

PG[9]

PG[7]

PB[1]

PF[8]

PF[12]

PG[8]

PG[6]

PF[9]

VDD_BV VDD_LV

PG[12]

PD[15]

PD[13]

PD[10]

PA[3]

PD[14]

PD[12]

PD[9]

PB[6]

PG[13]

PB[14]

PB[12]

PD[11]

PB[7]

PB[5]

PB[4]

PC[10]

PB[0]

PC[7]

PF[10]

EVTO

PC[11]

PB[15]

PB[13]

PB[11]

PD[3]

PD[4]

PD[5]

PA[4]

VSS_LV

VDD_LV

PA[13]

PA[12]

EXTAL VDD_HV

PF[0]

PF[1]

PF[3]

PF[2]

PF[4]

PF[5]

PF[7]

PF[6]

VDD_HV

_ADC

PA[14]

XTAL

PB[10]

PD[0]

PD[2]

PD[1]

OSC32K

_XTAL

VSS_HV

_ADC

PC[6]

PF[11] VDD_HV PA[15]

PD[7]

PD[6]

OSC32K

_EXTAL

MCKO

PF[13]

PD[8]

Note: 208 MAPBGA available only as development package for Nexus 2+.

= Not connected

Figure 6. 208 MAPBGA configuration

3.2

Pin muxing

Table 3 defines the pin list and muxing for this device.

Each entry of Table 3 shows all the possible configurations for each pin, via the alternate functions. The default function

assigned to each pin after reset is indicated by AF0.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Table 3. Functional port pin descriptions

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PA[0]

PA[1]

PCR[0]

PCR[1]

AF0

AF1

AF2

AF3

—

GPIO[0]

E0UC[0]

CLKOUT

—

SIUL

eMIOS0

CGL

—

WKPU

I/O

—

Tristate

WKUP[19]⁴

AF0

AF1

AF2

AF3

—

GPIO[1]

E0UC[1]

—

SIUL

eMIOS0

—

WKPU

I/O

—

NMI⁵

—

WKUP[2]⁴

PA[2]

PA[3]

PA[4]

PA[5]

PCR[2]

PCR[3]

PCR[4]

PCR[5]

AF0

AF1

AF2

AF3

—

GPIO[2]

E0UC[2]

—

SIUL

eMIOS0

—

WKPU

I/O

—

Tristate

K15

—

WKUP[3]⁴

AF0

AF1

AF2

AF3

—

GPIO[3]

E0UC[3]

—

EIRQ[0]

SIUL

eMIOS0

—

SIUL

I/O

—

AF0

AF1

AF2

AF3

—

GPIO[4]

E0UC[4]

—

SIUL

eMIOS0

—

WKPU

I/O

—

WKUP[9]⁴

AF0

AF1

AF2

AF3

GPIO[5]

E0UC[5]

—

SIUL

eMIOS0

—

I/O

—

118

C11

—

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PA[6]

PA[7]

PA[8]

PCR[6]

PCR[7]

PCR[8]

AF0

AF1

AF2

AF3

—

GPIO[6]

E0UC[6]

—

EIRQ[1]

SIUL

eMIOS0

—

SIUL

I/O

—

Tristate

119

104

105

D11

D16

C16

AF0

AF1

AF2

AF3

—

GPIO[7]

E0UC[7]

LIN3TX

—

SIUL

eMIOS0

LINFlex_3

—

I/O

—

EIRQ[2]

SIUL

AF0

AF1

AF2

AF3

—

GPIO[8]

E0UC[8]

—

SIUL

eMIOS0

—

SIUL

I/O

—

Input,

weak

pull-up

—

EIRQ[3]

ABS[0]

LIN3RX

N/A⁶

—

BAM

LINFlex_3

PA[9]

PCR[9]

AF0

AF1

AF2

AF3

N/A⁶

GPIO[9]

E0UC[9]

—

FAB

SIUL

eMIOS_0

—

BAM

I/O

—

Pull-

down

106

C15

PA[10] PCR[10]

PA[11] PCR[11]

AF0

AF1

AF2

AF3

GPIO[10]

E0UC[10]

SDA

SIUL

eMIOS_0

I2C_0

—

I/O

—

Tristate

107

108

B16

B15

—

AF0

AF1

AF2

AF3

GPIO[11]

E0UC[11]

SCL

SIUL

eMIOS0

I2C_0

—

I/O

—

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PA[12] PCR[12]

AF0

AF1

AF2

AF3

—

GPIO[12]

—

SIN_0

SIUL

—

DSPI0

I/O

—

Tristate

PA[13] PCR[13]

PA[14] PCR[14]

AF0

AF1

AF2

AF3

GPIO[13]

SOUT_0

—

SIUL

DSPI_0

—

I/O

—

Tristate

—

AF0

AF1

AF2

AF3

—

GPIO[14]

SCK_0

CS0_0

—

SIUL

DSPI_0

—

I/O

—

EIRQ[4]

SIUL

PA[15] PCR[15]

AF0

AF1

AF2

AF3

—

GPIO[15]

CS0_0

SIUL

DSPI_0

—

I/O

—

Tristate

SCK_0

—

WKUP[10]⁴

WKPU

PB[0] PCR[16]

PB[1] PCR[17]

AF0

AF1

AF2

AF3

GPIO[16]

CAN0TX

—

SIUL

FlexCAN_0

I/O

—

Tristate

—

AF0

AF1

AF2

AF3

—

GPIO[17]

—

SIUL

—

I/O

—

WKUP[4]⁴

CAN0RX

WKPU

FlexCAN_0

—

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PB[2] PCR[18]

PB[3] PCR[19]

AF0

AF1

AF2

AF3

GPIO[18]

LIN0TX

SDA

SIUL

LINFlex_0

I2C_0

—

I/O

—

Tristate

100

144

—

AF0

AF1

AF2

AF3

—

GPIO[19]

—

SCL

SIUL

—

I2C_0

—

WKPU

LINFlex_0

I/O

—

I/O

—

WKUP[11]⁴

LIN0RX

—

PB[4] PCR[20]

PB[5] PCR[21]

PB[6] PCR[22]

PB[7] PCR[23]

AF0

AF1

AF2

AF3

—

GPIO[20]

SIUL

—

ADC

Tristate

—

T16

R16

P15

P16

—

ANP[0]

AF0

AF1

AF2

AF3

—

GPIO[21]

SIUL

—

ADC

—

ANP[1]

AF0

AF1

AF2

AF3

—

GPIO[22]

SIUL

—

ADC

—

ANP[2]

AF0

AF1

AF2

AF3

—

GPIO[23]

SIUL

—

ADC

—

ANP[3]

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PB[8] PCR[24]

PB[9] PCR[25]

PB[10] PCR[26]

AF0

AF1

AF2

AF3

—

GPIO[24]

SIUL

—

ADC

SXOSC

Tristate

—

ANS[0]

—

OSC32K_XTAL⁷

I/O

AF0

AF1

AF2

AF3

—

GPIO[25]

SIUL

—

ADC

—

ANS[1]

—

OSC32K_EXTAL⁷SXOSC

I/O

AF0

AF1

AF2

AF3

—

GPIO[26]

—

SIUL

—

ADC

WKPU

I/O

—

ANS[2]

—

WKUP[8]⁴

PB[11]⁸PCR[27]

PB[12] PCR[28]

PB[13] PCR[29]

AF0

AF1

AF2

AF3

—

GPIO[27]

E0UC[3]

—

CS0_0

ANS[3]

SIUL

eMIOS_0

—

DSPI_0

ADC

I/O

—

I/O

Tristate

—

N13

M16

M13

AF0

AF1

AF2

AF3

—

GPIO[28]

E0UC[4]

—

CS1_0

ANX[0]

SIUL

eMIOS

—

DSPI_0

ADC

I/O

—

AF0

AF1

AF2

AF3

—

GPIO[29]

E0UC[5]

—

CS2_0

ANX[1]

SIUL

eMIOS_0

—

DSPI_0

ADC

I/O

—

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PB[14] PCR[30]

PB[15] PCR[31]

AF0

AF1

AF2

AF3

—

GPIO[30]

E0UC[6]

—

CS3_0

ANX[2]

SIUL

eMIOS0

—

DSPI_0

ADC

I/O

—

Tristate

L16

AF0

AF1

AF2

AF3

—

GPIO[31]

E0UC[7]

—

CS4_0

ANX[3]

SIUL

eMIOS_0

—

DSPI_0

ADC

I/O

—

L13

PC[0]⁹PCR[32]

PC[1]⁹PCR[33]

PC[2] PCR[34]

AF0

AF1

AF2

AF3

GPIO[32]

SIUL

—

JTAGC

—

I/O

—

Input,

weak

pull-up

126

121

117

—

TDI

—

AF0

AF1

AF2

AF3

GPIO[33]

—

SIUL

—

JTAGC

—

I/O

—

Tristate

TDO¹⁰

—

AF0

AF1

AF2

AF3

—

GPIO[34]

SCK_1

CAN4TX¹¹

—

SIUL

DSPI_1

LINFlex_4

—

I/O

—

A11

EIRQ[5]

SIUL

PC[3] PCR[35]

AF0

AF1

AF2

AF3

—

GPIO[35]

CS0_1

MA[0]

SIUL

DSPI_1

ADC

I/O

—

Tristate

116

B11

—

CAN1RX

CAN4RX¹¹

EIRQ[6]

FlexCAN_1

FlexCAN_4

SIUL

—

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PC[4] PCR[36]

PC[5] PCR[37]

AF0

AF1

AF2

AF3

—

GPIO[36]

SIUL

—

I/O

—

Tristate

131

—

SIN_1

DSPI_1

FlexCAN_3

—

CAN3RX¹¹

AF0

AF1

AF2

AF3

—

GPIO[37]

SOUT_1

CAN3TX¹¹

—

SIUL

DSPI1

FlexCAN_3

—

I/O

—

130

EIRQ[7]

SIUL

PC[6] PCR[38]

PC[7] PCR[39]

AF0

AF1

AF2

AF3

GPIO[38]

LIN1TX

—

SIUL

LINFlex_1

—

I/O

—

Tristate

—

AF0

AF1

AF2

AF3

—

GPIO[39]

SIUL

—

I/O

—

LIN1RX

LINFlex_1

WKPU

—

WKUP[12]⁴

PC[8] PCR[40]

PC[9] PCR[41]

AF0

AF1

AF2

AF3

GPIO[40]

LIN2TX

—

SIUL

LINFlex_2

—

I/O

—

Tristate

143

—

AF0

AF1

AF2

AF3

—

GPIO[41]

SIUL

—

I/O

—

LIN2RX

LINFlex_2

WKPU

—

WKUP[13]⁴

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PC[10] PCR[42]

PC[11] PCR[43]

AF0

AF1

AF2

AF3

GPIO[42]

CAN1TX

CAN4TX¹¹

MA[1]

SIUL

FlexCAN_1

FlexCAN_4

ADC

I/O

Tristate

—

AF0

AF1

AF2

AF3

—

GPIO[43]

—

SIUL

—

I/O

—

CAN1RX

CAN4RX¹¹

WKUP[5]⁴

FlexCAN_1

FlexCAN_4

WKPU

—

PC[12] PCR[44]

AF0

AF1

AF2

AF3

—

GPIO[44]

E0UC[12]

—

SIN_2

SIUL

eMIOS_0

—

DSPI_2

I/O

—

Tristate

—

141

PC[13] PCR[45]

PC[14] PCR[46]

AF0

AF1

AF2

AF3

GPIO[45]

E0UC[13]

SOUT_2

—

SIUL

eMIOS_0

DSPI_2

—

I/O

Tristate

—

142

—

AF0

AF1

AF2

AF3

—

GPIO[46]

E0UC[14]

SCK_2

—

SIUL

eMIOS_0

DSPI_2

—

I/O

—

EIRQ[8]

SIUL

PC[15] PCR[47]

AF0

AF1

AF2

AF3

GPIO[47]

E0UC[15]

CS0_2

—

SIUL

eMIOS_0

DSPI_2

—

I/O

—

Tristate

—

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PD[0] PCR[48]

PD[1] PCR[49]

PD[2] PCR[50]

PD[3] PCR[51]

PD[4] PCR[52]

PD[5] PCR[53]

AF0

AF1

AF2

AF3

—

GPIO[48]

SIUL

—

ADC

Tristate

—

P12

T12

R12

P13

R13

T13

—

ANP[4]

AF0

AF1

AF2

AF3

—

GPIO[49]

SIUL

—

ADC

—

ANP[5]

AF0

AF1

AF2

AF3

—

GPIO[50]

SIUL

—

ADC

—

ANP[6]

AF0

AF1

AF2

AF3

—

GPIO[51]

SIUL

—

ADC

—

ANP[7]

AF0

AF1

AF2

AF3

—

GPIO[52]

SIUL

—

ADC

—

ANP[8]

AF0

AF1

AF2

AF3

—

GPIO[53]

SIUL

—

ADC

—

ANP[9]

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PD[6] PCR[54]

PD[7] PCR[55]

PD[8] PCR[56]

PD[9] PCR[57]

PD[10] PCR[58]

PD[11] PCR[59]

AF0

AF1

AF2

AF3

—

GPIO[54]

SIUL

—

ADC

Tristate

—

T14

R14

T15

N15

N14

N16

—

ANP[10]

AF0

AF1

AF2

AF3

—

GPIO[55]

SIUL

—

ADC

—

ANP[11]

AF0

AF1

AF2

AF3

—

GPIO[56]

SIUL

—

ADC

—

ANP[12]

AF0

AF1

AF2

AF3

—

GPIO[57]

SIUL

—

ADC

—

ANP[13]

AF0

AF1

AF2

AF3

—

GPIO[58]

SIUL

—

ADC

—

ANP[14]

AF0

AF1

AF2

AF3

—

GPIO[59]

SIUL

—

ADC

—

ANP[15]

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PD[12]⁸PCR[60]

PD[13] PCR[61]

PD[14] PCR[62]

PD[15] PCR[63]

PE[0] PCR[64]

AF0

AF1

AF2

AF3

—

GPIO[60]

CS5_0

E0UC[24]

—

SIUL

DSPI_0

eMIOS_0

—

I/O

—

Tristate

—

M15

M14

L15

L14

ANS[4]

ADC

AF0

AF1

AF2

AF3

—

GPIO[61]

CS0_1

E0UC[25]

—

SIUL

DSPI_1

eMIOS_0

—

I/O

—

ANS[5]

ADC

AF0

AF1

AF2

AF3

—

GPIO[62]

CS1_1

E0UC[26]

—

SIUL

DSPI_1

eMIOS_0

—

I/O

—

ANS[6]

ADC

AF0

AF1

AF2

AF3

—

GPIO[63]

CS2_1

E0UC[27]

—

SIUL

DSPI_1

eMIOS_0

—

I/O

—

ANS[7]

ADC

AF0

AF1

AF2

AF3

—

GPIO[64]

E0UC[16]

—

SIUL

eMIOS_0

—

I/O

—

CAN5RX¹¹

WKUP[6]⁴

FlexCAN_5

WKPU

—

PE[1] PCR[65]

AF0

AF1

AF2

AF3

GPIO[65]

E0UC[17]

CAN5TX¹¹

—

SIUL

eMIOS_0

FlexCAN_5

—

I/O

Tristate

—

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PE[2] PCR[66]

AF0

AF1

AF2

AF3

—

GPIO[66]

E0UC[18]

—

SIN_1

SIUL

eMIOS0

—

DSPI_1

I/O

—

Tristate

—

128

PE[3] PCR[67]

PE[4] PCR[68]

AF0

AF1

AF2

AF3

GPIO[67]

E0UC[19]

SOUT_1

—

SIUL

eMIOS0

DSPI_1

—

I/O

Tristate

—

129

132

—

AF0

AF1

AF2

AF3

—

GPIO[68]

E0UC[20]

SCK_1

—

SIUL

eMIOS0

DSPI_1

—

I/O

—

EIRQ[9]

SIUL

PE[5] PCR[69]

PE[6] PCR[70]

PE[7] PCR[71]

PE[8] PCR[72]

AF0

AF1

AF2

AF3

GPIO[69]

E0UC[21]

CS0_1

SIUL

eMIOS_0

DSPI_1

ADC

I/O

Tristate

—

133

139

140

MA[2]

AF0

AF1

AF2

AF3

GPIO[70]

E0UC[22]

CS3_0

SIUL

eMIOS_0

DSPI_0

ADC

I/O

MA[1]

AF0

AF1

AF2

AF3

GPIO[71]

E0UC[23]

CS2_0

SIUL

eMIOS_0

DSPI_0

ADC

I/O

MA[0]

AF0

AF1

AF2

AF3

GPIO[72]

CAN2TX¹²

E0UC[22]

CAN3TX¹¹

SIUL

FlexCAN_2

I/O

eMIOS0

FlexCAN_3

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PE[9] PCR[73]

AF0

AF1

AF2

AF3

—

GPIO[73]

—

SIUL

—

eMIOS_0

—

WKPU

FlexCAN_2

FlexCAN_3

I/O

—

I/O

—

Tristate

—

E0UC[23]

—

WKUP[7]⁴

CAN2RX¹²

CAN3RX¹¹

—

PE[10] PCR[74]

PE[11] PCR[75]

AF0

AF1

AF2

AF3

—

GPIO[74]

LIN3TX

CS3_1

—

SIUL

LINFlex_3

DSPI_1

—

I/O

—

Tristate

—

EIRQ[10]

SIUL

AF0

AF1

AF2

AF3

—

GPIO[75]

—

CS4_1

—

SIUL

—

DSPI_1

—

LINFlex_3

WKPU

I/O

—

LIN3RX

—

WKUP[14]⁴

PE[12] PCR[76]

AF0

AF1

AF2

AF3

—

GPIO[76]

—

SIUL

—

eMIOS_1

—

DSPI_2

SIUL

I/O

—

I/O

—

Tristate

—

109

C14

E1UC[19]¹³

—

SIN_2

EIRQ[11]

—

PE[13] PCR[77]

PE[14] PCR[78]

AF0

AF1

AF2

AF3

GPIO[77]

SOUT2

E1UC[20]

—

SIUL

DSPI_2

eMIOS_1

—

I/O

—

Tristate

—

103

112

D15

C13

AF0

AF1

AF2

AF3

—

GPIO[78]

SCK_2

E1UC[21]

—

SIUL

DSPI_2

eMIOS_1

—

I/O

—

EIRQ[12]

SIUL

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PE[15] PCR[79]

PF[0] PCR[80]

AF0

AF1

AF2

AF3

GPIO[79]

CS0_2

E1UC[22]

—

SIUL

DSPI_2

eMIOS_1

—

I/O

—

Tristate

—

113

A13

AF0

AF1

AF2

AF3

—

GPIO[80]

E0UC[10]

CS3_1

—

SIUL

eMIOS_0

DSPI_1

—

I/O

—

N10

ANS[8]

ADC

PF[1] PCR[81]

PF[2] PCR[82]

PF[3] PCR[83]

PF[4] PCR[84]

AF0

AF1

AF2

AF3

—

GPIO[81]

E0UC[11]

CS4_1

—

SIUL

eMIOS_0

DSPI_1

—

I/O

—

Tristate

—

P10

T10

R10

N11

ANS[9]

AF0

AF1

AF2

AF3

—

GPIO[82]

E0UC[12]

CS0_2

—

SIUL

eMIOS_0

DSPI_2

—

I/O

—

ANS[10]

ADC

AF0

AF1

AF2

AF3

—

GPIO[83]

E0UC[13]

CS1_2

—

SIUL

eMIOS_0

DSPI_2

—

I/O

—

ANS[11]

ADC

AF0

AF1

AF2

AF3

—

GPIO[84]

E0UC[14]

CS2_2

—

SIUL

eMIOS_0

DSPI_2

—

I/O

—

ANS[12]

ADC

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PF[5] PCR[85]

PF[6] PCR[86]

PF[7] PCR[87]

AF0

AF1

AF2

AF3

—

GPIO[85]

E0UC[22]

CS3_2

—

SIUL

eMIOS_0

DSPI_2

—

I/O

—

Tristate

—

P11

T11

R11

ANS[13]

ADC

AF0

AF1

AF2

AF3

—

GPIO[86]

E0UC[23]

—

ANS[14]

SIUL

eMIOS_0

—

ADC

I/O

—

AF0

AF1

AF2

AF3

—

GPIO[87]

SIUL

—

ADC

I/O

—

ANS[15]

PF[8] PCR[88]

PF[9] PCR[89]

AF0

AF1

AF2

AF3

GPIO[88]

CAN3TX¹⁴

CS4_0

SIUL

FlexCAN_3

DSPI_0

I/O

Tristate

—

CAN2TX¹⁵

FlexCAN_2

AF0

AF1

AF2

AF3

—

GPIO[89]

—

SIUL

—

DSPI_0

—

FlexCAN_2

FlexCAN_3

I/O

—

CS5_0

—

CAN2RX¹⁵

CAN3RX¹⁴

—

PF[10] PCR[90]

AF0

AF1

AF2

AF3

GPIO[90]

SIUL

—

I/O

—

Tristate

—

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PF[11] PCR[91]

AF0

AF1

AF2

AF3

—

GPIO[91]

SIUL

—

WKPU

I/O

—

Tristate

—

WKUP[15]⁴

PF[12] PCR[92]

PF[13] PCR[93]

AF0

AF1

AF2

AF3

GPIO[92]

E1UC[25]

—

SIUL

eMIOS_1

—

I/O

—

Tristate

—

AF0

AF1

AF2

AF3

—

GPIO[93]

E1UC[26]

—

SIUL

eMIOS_1

—

WKPU

I/O

—

WKUP[16]⁴

PF[14] PCR[94]

PF[15] PCR[95]

AF0

AF1

AF2

AF3

GPIO[94]

CAN4TX¹¹

E1UC[27]

CAN1TX

SIUL

I/O

Tristate

—

102

101

D14

E15

FlexCAN_4

eMIOS_1

FlexCAN_4

AF0

AF1

AF2

AF3

—

GPIO[95]

—

SIUL

—

I/O

—

CAN1RX

CAN4RX¹¹

EIRQ[13]

FlexCAN_1

FlexCAN_4

SIUL

—

PG[0] PCR[96]

AF0

AF1

AF2

AF3

GPIO[96]

CAN5TX¹¹

E1UC[23]

—

SIUL

FlexCAN_5

eMIOS_1

—

I/O

—

Tristate

—

E14

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PG[1] PCR[97]

AF0

AF1

AF2

AF3

—

GPIO[97]

—

SIUL

—

eMIOS_1

—

FlexCAN_5

SIUL

I/O

—

I/O

—

Tristate

—

E13

E1UC[24]

—

CAN5RX¹¹

EIRQ[14]

—

PG[2] PCR[98]

PG[3] PCR[99]

AF0

AF1

AF2

AF3

GPIO[98]

E1UC[11]

—

SIUL

eMIOS_1

—

I/O

—

Tristate

—

AF0

AF1

AF2

AF3

—

GPIO[99]

E1UC[12]

—

SIUL

eMIOS_1

—

WKPU

I/O

—

WKUP[17]⁴

PG[4] PCR[100]

PG[5] PCR[101]

AF0

AF1

AF2

AF3

GPIO[100]

E1UC[13]

—

SIUL

eMIOS_1

—

I/O

—

Tristate

—

AF0

AF1

AF2

AF3

—

GPIO[101]

E1UC[14]

—

SIUL

eMIOS_1

—

WKPU

I/O

—

WKUP[18]⁴

PG[6] PCR[102]

PG[7] PCR[103]

AF0

AF1

AF2

AF3

GPIO[102]

E1UC[15]

—

SIUL

eMIOS_1

—

I/O

—

Tristate

—

AF0

AF1

AF2

AF3

GPIO[103]

E1UC[16]

—

SIUL

eMIOS_1

—

I/O

—

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PG[8] PCR[104]

AF0

AF1

AF2

AF3

—

GPIO[104]

E1UC[17]

—

CS0_2

EIRQ[15]

SIUL

eMIOS_1

—

DSPI_2

SIUL

I/O

—

I/O

Tristate

—

PG[9] PCR[105]

PG[10] PCR[106]

PG[11] PCR[107]

PG[12] PCR[108]

PG[13] PCR[109]

PG[14] PCR[110]

AF0

AF1

AF2

AF3

GPIO[105]

E1UC[18]

—

SIUL

eMIOS1

—

I/O

—

Tristate

—

114

115

SCK_2

DSPI_2

I/O

AF0

AF1

AF2

AF3

GPIO[106]

E0UC[24]

—

SIUL

eMIOS_0

—

I/O

—

D13

B12

K14

K16

B14

—

AF0

AF1

AF2

AF3

GPIO[107]

E0UC[25]

—

SIUL

eMIOS_0

—

I/O

—

AF0

AF1

AF2

AF3

GPIO[108]

E0UC[26]

—

SIUL

eMIOS_0

—

I/O

—

AF0

AF1

AF2

AF3

GPIO[109]

E0UC[27]

—

SIUL

eMIOS_0

—

I/O

—

AF0

AF1

AF2

AF3

GPIO[110]

E1UC[0]

—

SIUL

eMIOS_1

—

I/O

—

110

—

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PG[15] PCR[111]

PH[0] PCR[112]

AF0

AF1

AF2

AF3

GPIO[111]

E1UC[1]

—

SIUL

eMIOS_1

—

I/O

—

Tristate

—

111

B13

—

AF0

AF1

AF2

AF3

—

GPIO[112]

E1UC[2]

—

SIUL

eMIOS_1

—

DSPI_1

I/O

—

F13

—

SIN1

PH[1] PCR[113]

PH[2] PCR[114]

PH[3] PCR[115]

PH[4] PCR[116]

PH[5] PCR[117]

AF0

AF1

AF2

AF3

GPIO[113]

E1UC[3]

SOUT1

—

SIUL

eMIOS_1

DSPI_1

—

I/O

Tristate

—

F14

F16

F15

—

AF0

AF1

AF2

AF3

GPIO[114]

E1UC[4]

SCK_1

—

SIUL

eMIOS_1

DSPI_1

—

I/O

—

AF0

AF1

AF2

AF3

GPIO[115]

E1UC[5]

CS0_1

—

SIUL

eMIOS_1

DSPI_1

—

I/O

—

AF0

AF1

AF2

AF3

GPIO[116]

E1UC[6]

—

SIUL

eMIOS_1

—

I/O

—

134

135

—

AF0

AF1

AF2

AF3

GPIO[117]

E1UC[7]

—

SIUL

eMIOS_1

—

I/O

—

Table 3. Functional port pin descriptions (continued)

Pin No.

100

LQFP

5CAN4

LIN

Port

PCR

Alternate

I/O

Pad RESET

208

MAP

BGA³

Function

Peripheral

direction²type config.

LQFP

144

LQFP LQFP

PH[6] PCR[118]

PH[7] PCR[119]

PH[8] PCR[120]

PH[9]⁹PCR[121]

PH[10]⁹PCR[122]

AF0

AF1

AF2

AF3

GPIO[118]

E1UC[8]

—

SIUL

eMIOS_1

—

I/O

—

Tristate

—

136

137

138

127

120

MA[2]

ADC

AF0

AF1

AF2

AF3

GPIO[119]

E1UC[9]

CS3_2

SIUL

eMIOS_1

DSPI_2

ADC

I/O

MA[1]

AF0

AF1

AF2

AF3

GPIO[120]

E1UC[10]

CS2_2

SIUL

eMIOS_1

DSPI_2

ADC

I/O

MA[0]

AF0

AF1

AF2

AF3

GPIO[121]

SIUL

—

JTAGC

—

I/O

—

Input,

weak

pull-up

—

TCK

—

AF0

AF1

AF2

AF3

GPIO[122]

SIUL

—

JTAGC

—

I/O

—

Input,

weak

pull-up

—

TMS

—

Alternate functions are chosen by setting the values of the PCR.PA bitfields inside the SIUL module. PCR.PA = 00 -> AF0;

PCR.PA = 01 -> AF1; PCR.PA = 10 -> AF2; PCR.PA = 11 -> AF3. This is intended to select the output functions; to use one of the input

functions, the PCR.IBE bit must be written to ‘1’, regardless of the values selected in the PCR.PA bitfields. For this reason, the value

corresponding to an input only function is reported as “—”.

Multiple inputs are routed to all respective modules internally. The input of some modules must be configured by setting the values of

the PSMIO.PADSELx bitfields inside the SIUL module.

208 MAPBGA available only as development package for Nexus2+

All WKUP pins also support external interrupt capability. See wakeup unit chapter for further details.

NMI has higher priority than alternate function. When NMI is selected, the PCR.AF field is ignored.

“Not applicable” because these functions are available only while the device is booting. Refer to BAM chapter of the reference manual

for details.

Value of PCR.IBE bit must be 0

This pad is used on MPC5607B 100-pin and 144-pinto provide supply for the second ADC. Therefore it is recommended not using it to

keep the compatibility with the family devices.

Out of reset all the functional pins except PC[0:1] and PH[9:10] are available to the user as GPIO.

PC[0:1] are available as JTAG pins (TDI and TDO respectively).

PH[9:10] are available as JTAG pins (TCK and TMS respectively).

It is up to the user to configure these pins as GPIO when needed, in this case MPC5604B/C get incompliance with IEEE 1149.1-2001.

¹⁰The TDO pad has been moved into the STANDBY domain in order to allow low-power debug handshaking in STANDBY mode. However,

no pull-resistor is active on the TDO pad while in STANDBY mode. At this time the pad is configured as an input. When no debugger is

connected the TDO pad is floating causing additional current consumption. To avoid the extra consumption TDO must be connected.

An external pull-up resistor in the range of 47–100 kOhms should be added between the TDO pin and VDD. Only in case the TDO pin

is used as application pin and a pull-up cannot be used then a pull-down resistor with the same value should be used between TDO pin

and GND instead.

¹¹Available only on MPC560xC versions and MPC5604B 208 MAPBGA devices

¹²Not available on MPC5602B devices

¹³Not available in 100 LQFP package

¹⁴Available only on MPC5604B 208 MAPBGA devices

¹⁵Not available on MPC5603B 144-pin devices

Electrical characteristics

4.1

Introduction

This section contains electrical characteristics of the device as well as temperature and power considerations.

This product contains devices to protect the inputs against damage due to high static voltages. However, it is advisable to take precautions to avoid application

of any voltage higher than the specified maximum rated voltages.

To enhance reliability, unused inputs can be driven to an appropriate logic voltage level (V or V ). This could be done by the internal pull-up and pull-down,

which is provided by the product for most general purpose pins.

The parameters listed in the following tables represent the characteristics of the device and its demands on the system.

In the tables where the device logic provides signals with their respective timing characteristics, the symbol “CC” for Controller Characteristics is included in

the Symbol column.

In the tables where the external system must provide signals with their respective timing characteristics to the device, the symbol “SR” for System Requirement

is included in the Symbol column.

CAUTION

All 64 LQFPinformation is indicative and must be confirmed during silicon validation.

Electrical characteristics

4.2

Parameter classification

The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better

understanding, the classifications listed in Table 4 are used and the parameters are tagged accordingly in the tables where

appropriate.

Table 4. Parameter classifications

Classification tag

Tag description

Those parameters are guaranteed during production testing on each individual device.

Those parameters are achieved by the design characterization by measuring a statistically

relevant sample size across process variations.

Those parameters are achieved by design characterization on a small sample size from typical

devices under typical conditions unless otherwise noted. All values shown in the typical column

are within this category.

Those parameters are derived mainly from simulations.

NOTE

The classification is shown in the column labeled “C” in the parameter tables where

appropriate.

4.3

NVUSRO register

Portions of the device configuration, such as high voltage supply, oscillator margin, and watchdog enable/disable after reset are

controlled via bit values in the Non-Volatile User Options Register (NVUSRO) register.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.3.1

NVUSRO[PAD3V5V] field description

Table 5 shows how NVUSRO[PAD3V5V] controls the device configuration.

Table 5. PAD3V5V field description

Value²

Description

High voltage supply is 5.0 V

High voltage supply is 3.3 V

See the device reference manual for more information on the NVUSRO register.

'1' is delivery value. It is part of shadow Flash, thus programmable by customer.

The DC electrical characteristics are dependent on the PAD3V5V bit value.

4.3.2

NVUSRO[OSCILLATOR_MARGIN] field description

Table 6 shows how NVUSRO[OSCILLATOR_MARGIN] controls the device configuration.

Table 6. OSCILLATOR_MARGIN field description

Value²

Description

Low consumption configuration (4 MHz/8 MHz)

High margin configuration (4 MHz/16 MHz)

See the device reference manual for more information on the NVUSRO register.

'1' is delivery value. It is part of shadow Flash, thus programmable by customer.

The fast external crystal oscillator consumption is dependent on the OSCILLATOR_MARGIN bit value.

For a detailed description of the NVUSRO register, please refer to the MPC5604B/C Reference Manual.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.4

Absolute maximum ratings

Table 7. Absolute maximum ratings

Value

Unit

Symbol

Parameter

Conditions

Min

Max

V_SS

V_DD

SR Digital ground on VSS_HV pins

—

SR Voltage on VDD_HV pins with respect to

0.3

6.0

ground (V_SS

)

V_{SS_LV}SR Voltage on VSS_LV (low voltage digital

supply) pins with respect to ground

—

V_SS0.1 V_SS+0.1

(V_SS

)

V_{DD_BV}SR Voltage on VDD_BV pin (regulator

supply) with respect to ground (V_SS

0.3

6.0

)

Relative to V_DD

V_DD+0.3

V_{SS_ADC}SR Voltage on VSS_HV_ADC (ADC

—

V_SS0.1 V_SS+0.1

reference) pin with respect to ground

(V_SS

)

V_{DD_ADC}SR Voltage on VDD_HV_ADC pin (ADC

reference) with respect to ground (V_SS

—

0.3

6.0

)

Relative to V_DD

V_DD0.3 V_DD+0.3

V_IN

SR Voltage on any GPIO pin with respect to

ground (V_SS

0.3

—

6.0

V_DD+0.3

)

I_INJPADSR Injected input current on any pin during

overload condition

—

10

I_INJSUMSR Absolute sum of all injected input

currents during overload condition

50

I_AVGSEGSR Sum of all the static I/O current within a V_DD= 5.0 V 10%, PAD3V5V = 0

—

supply segment

V_DD= 3.3 V 10%, PAD3V5V = 1

I_CORELVSR Low voltage static current sink through

VDD_BV

—

150

°C

T_STORAGESR Storage temperature

—

55

150

NOTE

Stresses exceeding the recommended absolute maximum ratings may cause permanent

damage to the device. This is a stress rating only and functional operation of the device at

these or any other conditions above those indicated in the operational sections of this

specification are not implied. Exposure to absolute maximum rating conditions for

extended periods may affect device reliability. During overload conditions (V > V or

< V ), the voltage on pins with respect to ground (V ) must not exceed the

SS SS

recommended values.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.5

Recommended operating conditions

Table 8. Recommended operating conditions (3.3 V)

Value

Symbol

Parameter

Conditions

Unit

Min

Max

V_SS

SR Digital ground on VSS_HV pins

—

V_DD

SR Voltage on VDD_HV pins with respect to

3.0

3.6

ground (V_SS

)

V_{SS_LV}

SR Voltage on VSS_LV (low voltage digital

supply) pins with respect to ground (V_SS

—

V_SS0.1 V_SS+0.1

3.0 3.6

)

V_{DD_BV}

SR Voltage on VDD_BV pin (regulator supply)

with respect to ground (V_SS

)

Relative to V_DD

V_DD0.1 V_DD+0.1

V_SS0.1 V_SS+0.1

V_{SS_ADC}

SR Voltage on VSS_HV_ADC (ADC reference)

pin with respect to ground (V_SS

—

)

3.0⁵

V_DD0.1 V_DD+0.1

3.6

V_{DD_ADC}

SR Voltage on VDD_HV_ADC pin (ADC

reference) with respect to ground (V_SS

—

Relative to V_DD

—

)

V_IN

SR Voltage on any GPIO pin with respect to

ground (V_SS

V_SS0.1

—

V_DD+0.1

)

Relative to V_DD

—

I_INJPAD

I_INJSUM

TV_DD

SR Injected input current on any pin during

overload condition

5

SR Absolute sum of all injected input currents

during overload condition

—

50

SR V_DDslope to ensure correct power up⁶

—

0.25 V/µs

T_{A C-Grade Part}SR Ambient temperature under bias

T_{J C-Grade Part}SR Junction temperature under bias

T_{A V-Grade Part}SR Ambient temperature under bias

T_{J V-Grade Part}SR Junction temperature under bias

T_{A M-Grade Part}SR Ambient temperature under bias

T_{J M-Grade Part}SR Junction temperature under bias

f_CPU< 64 MHz

40

°C

—

f_CPU< 64 MHz

—

110

105

130

125

150

f_CPU< 64 MHz

—

100 nF capacitance needs to be provided between each V_DD/V_SSpair

330 nF capacitance needs to be provided between each V_{DD_LV}/V_{SS_LV}supply pair.

400 nF capacitance needs to be provided between V_{DD_BV}and the nearest V_{SS_LV}(higher value may be needed

depending on external regulator characteristics).

100 nF capacitance needs to be provided between V_{DD_ADC}/V_{SS_ADC}pair.

Full electrical specification cannot be guaranteed when voltage drops below 3.0 V. In particular, ADC electrical

characteristics and I/Os DC electrical specification may not be guaranteed. When voltage drops below V_LVDHVL

device is reset.

Guaranteed by device validation

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Table 9. Recommended operating conditions (5.0 V)

Value

Unit

Symbol

Parameter

Conditions

Min

Max

V_SS

SR Digital ground on VSS_HV pins

—

V_DD

SR Voltage on VDD_HV pins with respect to

4.5

3.0

5.5

ground (V_SS

)

Voltage drop²

V_{SS_LV}

SR Voltage on VSS_LV (low voltage digital

supply) pins with respect to ground

—

V_SS0.1 V_SS+0.1

(V_SS

)

V_{DD_BV}

SR Voltage on VDD_BV pin (regulator

supply) with respect to ground (V_SS

—

4.5

3.0

5.5

)

Voltage drop²

Relative to V_DD

V_DD0.1 V_DD+0.1

V_SS0.1 V_SS+0.1

V_{SS_ADC}

SR Voltage on VSS_HV_ADC (ADC

—

reference) pin with respect to ground

(V_SS

V_{DD_ADC}

SR Voltage on VDD_HV_ADC pin (ADC

reference) with respect to ground (V_SS

—

4.5

3.0

5.5

)

Voltage drop²

Relative to V_DD

V_DD0.1 V_DD+0.1

V_IN

SR Voltage on any GPIO pin with respect to

ground (V_SS

—

V_SS0.1

—

V_DD+0.1

)

Relative to V_DD

I_INJPAD

I_INJSUM

TV_DD

SR Injected input current on any pin during

overload condition

—

5

SR Absolute sum of all injected input

currents during overload condition

—

50

SR V_DDslope to ensure correct power up⁶

—

0.25 V/µs

T_{A C-Grade Part}SR Ambient temperature under bias

T_{J C-Grade Part}SR Junction temperature under bias

T_{A V-Grade Part}SR Ambient temperature under bias

T_{J V-Grade Part}SR Junction temperature under bias

T_{A M-Grade Part}SR Ambient temperature under bias

T_{J M-Grade Part}SR Junction temperature under bias

100 nF capacitance needs to be provided between each V_DD/V_SSpair.

f_CPU< 64 MHz

40

°C

—

110

105

130

125

150

f_CPU< 64 MHz

—

f_CPU< 64 MHz

—

Full device operation is guaranteed by design when the voltage drops below 4.5 V down to 3.0 V. However, certain

analog electrical characteristics will not be guaranteed to stay within the stated limits.

330 nF capacitance needs to be provided between each V_{DD_LV}/V_{SS_LV}supply pair.

100 nF capacitance needs to be provided between V_{DD_BV}and the nearest V_{SS_LV}(higher value may be needed

depending on external regulator characteristics).

100 nF capacitance needs to be provided between V_{DD_ADC}/V_{SS_ADC}pair.

Guaranteed by device validation

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

NOTE

RAM data retention is guaranteed with V

not below 1.08 V.

DD_LV

4.6

Thermal characteristics

4.6.1

Package thermal characteristics

Table 10. LQFP thermal characteristics

Conditions²

Symbol

Parameter

Thermal resistance,

Pin count Value Unit

R_JACC

Single-layer board - 1s

Four-layer board - 2s2p

Single-layer board - 1s

Four-layer board - 2s2p

Single-layer board - 1s

Four-layer board - 2s2p

Single-layer board - 1s

Four-layer board - 2s2p

100

144

°C/W

junction-to-ambient natural

convection³

100

144

R_JBCC

R_JCCC

_JBCC

Thermal resistance,

junction-to-board⁴

100

144

100

144

Thermal resistance,

junction-to-case⁵

100

144

100

144

Junction-to-board thermal

characterization parameter,

natural convection

TBD °C/W

100

144

TBD

100

144

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Table 10. LQFP thermal characteristics (continued)

Symbol

Parameter

Conditions²

Pin count Value Unit

_JCCC

Junction-to-case thermal

characterization parameter,

natural convection

Single-layer board - 1s

100

144

TBD °C/W

TBD

Four-layer board - 2s2p

100

144

Thermal characteristics are based on simulation.

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= -40 to 125 °C

Junction-to-ambient thermal resistance determined per JEDEC JESD51-3 and JESD51-6. Thermal test

board meets JEDEC specification for this package.

Junction-to-board thermal resistance determined per JEDEC JESD51-8. Thermal test board meets JEDEC

specification for the specified package.

Junction-to-case at the top of the package determined using MIL-STD 883 Method 1012.1. The cold plate

temperature is used for the case temperature. Reported value includes the thermal resistance of the interface

layer.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.6.2

Power considerations

The average chip-junction temperature, T , in degrees Celsius, may be calculated using Equation 1:

T = T + (P x R )

JA

Eqn. 1

Where:

T is the ambient temperature in °C.

is the package junction-to-ambient thermal resistance, in °C/W.

JA

P is the sum of P

and P (P = P

+ P ).

INT

I/O

INT I/O

is the product of I and V , expressed in watts. This is the chip internal power.

DD DD

INT

I/O

represents the power dissipation on input and output pins; user determined.

Most of the time for the applications, P < P

and may be neglected. On the other hand, P may be significant, if the device

I/O

INT

I/O

is configured to continuously drive external modules and/or memories.

An approximate relationship between P and T (if P is neglected) is given by:

I/O

P = K / (T + 273 °C)

Eqn. 2

Eqn. 3

Therefore, solving equations 1 and 2:

Where:

K = P x (T + 273 °C) + R

x P

JA

K is a constant for the particular part, which may be determined from Equation 3 by measuring P (at equilibrium)

for a known T Using this value of K, the values of P and T may be obtained by solving equations 1 and 2

iteratively for any value of T .

4.7

I/O pad electrical characteristics

I/O pad types

4.7.1

The device provides four main I/O pad types depending on the associated alternate functions:

•

Slow pads—These pads are the most common pads, providing a good compromise between transition time and low

electromagnetic emission.

Medium pads—These pads provide transition fast enough for the serial communication channels with controlled

current to reduce electromagnetic emission.

•

Fast pads—These pads provide maximum speed. There are used for improved Nexus debugging capability.

Input only pads—These pads are associated to ADC channels and the external 32 kHz crystal oscillator (SXOSC)

providing low input leakage.

Medium and Fast pads can use slow configuration to reduce electromagnetic emission, at the cost of reducing AC performance.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.7.2

I/O input DC characteristics

Table 11 provides input DC electrical characteristics as described in Figure 7.

Figure 7. I/O input DC electrical characteristics definition

HYS

PDIx = ‘1’

(GPDI register of SIUL)

PDIx = ‘0’

Table 11. I/O input DC electrical characteristics

Value

Symbol

Parameter

Conditions¹

Unit

Min

Typ

Max

V_IHSR P Input high level CMOS (Schmitt

Trigger)

—

0.65V_DD

—

V_DD+0.4

V_ILSR P Input low level CMOS (Schmitt

Trigger)

0.4

—

0.35V_DD

—

V_HYSCC C Input hysteresis CMOS (Schmitt

Trigger)

0.1V_DD

I_LKGCC P Digital input leakage

No injection

on adjacent

T_A= 40 °C

T_A= 25 °C

T_A= 105 °C

T_A= 125 °C

—

500

1000

—

W_FISR P Wakeup input filtered pulse

—

W_NFISR P Wakeup input not filtered pulse

1000

—

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified

In the range from 40 to 1000 ns, pulses can be filtered or not filtered, according to operating temperature and

voltage.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.7.3

I/O output DC characteristics

The following tables provide DC characteristics for bidirectional pads:

•

Table 12 provides weak pull figures. Both pull-up and pull-down resistances are supported.

Table 13 provides output driver characteristics for I/O pads when in SLOW configuration.

Table 14 provides output driver characteristics for I/O pads when in MEDIUM configuration.

Table 15 provides output driver characteristics for I/O pads when in FAST configuration.

Table 12. I/O pull-up/pull-down DC electrical characteristics

Value

Symbol

Parameter

Conditions¹

Unit

Min Typ Max

|I_WPU| CC P Weak pull-up current

V_IN= V_IL, V_DD= 5.0 V 10% PAD3V5V = 0

—

150 µA

250

absolute value

PAD3V5V = 1²10

V_IN= V_IL, V_DD= 3.3 V 10% PAD3V5V = 1

150

|I_WPD| CC P Weak pull-down current

V_IN= V_IH, V_DD= 5.0 V 10% PAD3V5V = 0

PAD3V5V = 1

150 µA

250

absolute value

V_IN= V_IH, V_DD= 3.3 V 10% PAD3V5V = 1

150

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified.

The configuration PAD3V5 = 1 when V_DD= 5 V is only a transient configuration during power-up. All pads but RESET

and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Table 13. SLOW configuration output buffer electrical characteristics

Value

Symbol

Parameter

Conditions¹

Unit

Min

Typ

Max

V_OHCC P Output high level

SLOW configuration

Push Pull I_OH= 2 mA,

0.8V_DD

—

V_DD= 5.0 V 10%, PAD3V5V = 0

(recommended)

_OH= 2 mA,

0.8V_DD

—

V_DD= 5.0 V 10%, PAD3V5V = 1²

I_OH= 1 mA,

V_DD0.8

V_DD= 3.3 V 10%, PAD3V5V = 1

(recommended)

V_OLCC P Output low level

SLOW configuration

Push Pull I_OL= 2 mA,

—

0.1V_DD

V_DD= 5.0 V 10%, PAD3V5V = 0

(recommended)

_OL= 2 mA,

—

0.1V_DD

0.5

V_DD= 5.0 V 10%, PAD3V5V = 1²

I_OL= 1 mA,

_DD= 3.3 V 10%, PAD3V5V = 1

(recommended)

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified

The configuration PAD3V5 = 1 when V_DD= 5 V is only a transient configuration during power-up. All pads but RESET

and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Table 14. MEDIUM configuration output buffer electrical characteristics

Value

Symbol

Parameter

Conditions¹

Unit

Min

Typ

Max

V_OHCC C Output high level

MEDIUM configuration

Push Pull I_OH= 3.8 mA,

V_DD= 5.0 V 10%, PAD3V5V = 0

0.8V_DD

—

_OH= 2 mA,

0.8V_DD

—

V_DD= 5.0 V 10%, PAD3V5V = 0

(recommended)

_OH= 1 mA,

0.8V_DD

—

V_DD= 5.0 V 10%, PAD3V5V = 1²

_OH= 1 mA,

_DD= 3.3 V 10%, PAD3V5V = 1

(recommended)

V_DD0.8

_OH= 100 µA,

0.8V_DD

—

V_DD= 5.0 V 10%, PAD3V5V = 0

V_OLCC C Output low level

Push Pull I_OL= 3.8 mA,

0.2V_DD

0.1V_DD

MEDIUM configuration

V_DD= 5.0 V 10%, PAD3V5V = 0

I_OL= 2 mA,

—

V_DD= 5.0 V 10%, PAD3V5V = 0

(recommended)

I_OL= 1 mA,

—

0.1V_DD

0.5

V_DD= 5.0 V 10%, PAD3V5V = 1²

I_OL= 1 mA,

V_DD= 3.3 V 10%, PAD3V5V = 1

(recommended)

_OL= 100 µA,

—

0.1V_DD

V_DD= 5.0 V 10%, PAD3V5V = 0

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified

The configuration PAD3V5 = 1 when V_DD= 5 V is only a transient configuration during power-up. All pads but RESET

and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

Table 15. FAST configuration output buffer electrical characteristics

Value

Symbol C

Parameter

Conditions¹

Unit

Min

Typ

Max

V_OHCC P Output high level

FAST configuration

Push

Pull

I_OH= 14mA,

V_DD= 5.0 V 10%, PAD3V5V = 0

0.8V_DD

—

(recommended)

_OH= 7mA,

0.8V_DD

—

V_DD= 5.0 V 10%, PAD3V5V = 1²

I_OH= 11mA,

V_DD0.8

V_DD= 3.3 V 10%, PAD3V5V = 1

(recommended)

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Table 15. FAST configuration output buffer electrical characteristics (continued)

Value

Symbol C

Parameter

Conditions¹

Unit

Min

Typ

Max

V_OLCC P Output low level

FAST configuration

Push

Pull

I_OL= 14mA,

V_DD= 5.0 V 10%, PAD3V5V = 0

(recommended)

—

0.1V_DD

_OL= 7mA,

—

0.1V_DD

0.5

V_DD= 5.0 V 10%, PAD3V5V = 1²

I_OL= 11mA,

_DD= 3.3 V 10%, PAD3V5V = 1

(recommended)

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified

The configuration PAD3V5 = 1 when V_DD= 5 V is only a transient configuration during power-up. All pads but

RESET and Nexus output (MDOx, EVTO, MCKO) are configured in input or in high impedance state.

4.7.4

Output pin transition times

Table 16. Output pin transition times

Value

Symbol

Parameter

Conditions¹

Unit

Min

Typ

Max

T_trCC D Output transition time output pin²C_L= 25 pF V_DD= 5.0 V 10%,

—

100

125

100

125

SLOW configuration

PAD3V5V = 0

C_L= 50 pF

C_L= 100 pF

C_L= 25 pF V_DD= 3.3 V 10%,

PAD3V5V = 1

C_L= 50 pF

C_L= 100 pF

T_trCC D Output transition time output pin²C_L= 25 pF V_DD= 5.0 V 10%,

MEDIUM configuration

PAD3V5V = 0

SIUL.PCRx.SRC = 1

C_L= 50 pF

C_L= 100 pF

C_L= 25 pF V_DD= 3.3 V 10%,

PAD3V5V = 1

SIUL.PCRx.SRC = 1

C_L= 50 pF

C_L= 100 pF

T_trCC D Output transition time output pin²C_L= 25 pF V_DD= 5.0 V 10%,

FAST configuration

PAD3V5V = 0

C_L= 50 pF

C_L= 100 pF

C_L= 25 pF V_DD= 3.3 V 10%,

PAD3V5V = 1

C_L= 50 pF

C_L= 100 pF

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

C_Lincludes device and package capacitances (C_PKG< 5 pF).

4.7.5

I/O pad current specification

The I/O pads are distributed across the I/O supply segment. Each I/O supply segment is associated to a V /V supply pair as

DD SS

described in Table 17.

Table 18 provides I/O consumption figures.

In order to ensure device reliability, the average current of the I/O on a single segment should remain below the I

maximum value.

AVGSEG

In order to ensure device functionality, the sum of the dynamic and static current of the I/O on a single segment should remain

below the I

maximum value.

DYNSEG

Table 17. I/O supply segment

Supply segment

Package

208 MAPBGA¹

144 LQFP

Equivalent to 144 LQFP segment pad distribution

pin20–pin49 pin51–pin99 pin100–pin122 pin 123–pin19

MCKO

—

MDOn/MSEO

—

100 LQFP

pin16–pin35

pin8–pin26

pin37–pin69

pin28–pin55

pin70–pin83

pin56–pin7

pin 84–pin15

—

64 LQFP²

—

208 MAPBGA available only as development package for Nexus2+

All 64 LQFPinformation is indicative and must be confirmed during silicon validation.

Table 18. I/O consumption

Value

Min Typ Max

Symbol

Parameter

Conditions¹

Unit

I_SWTSLW

CC D Dynamic I/O current C_L= 25 pF

V_DD= 5.0 V 10%,

PAD3V5V = 0

—

for SLOW

configuration

V_DD= 3.3 V 10%,

PAD3V5V = 1

I_SWTMED

CC D Dynamic I/O current C_L= 25 pF

for MEDIUM

V_DD= 5.0 V 10%,

PAD3V5V = 0

configuration

V_DD= 3.3 V 10%,

PAD3V5V = 1

I_SWTFST

CC D Dynamic I/O current C_L= 25 pF

V_DD= 5.0 V 10%,

PAD3V5V = 0

110 mA

for FAST

configuration

V_DD= 3.3 V 10%,

PAD3V5V = 1

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Table 18. I/O consumption (continued)

Conditions¹

Value

Symbol

Parameter

Unit

Min Typ Max

I_RMSSLW

CC D Root medium square C_L= 25 pF, 2 MHz

V_DD= 5.0 V 10%,

PAD3V5V = 0

—

2.3 mA

3.2

I/O current for SLOW

C_L= 25 pF, 4 MHz

configuration

C_L= 100 pF, 2 MHz

C_L= 25 pF, 2 MHz

C_L= 25 pF, 4 MHz

C_L= 100 pF, 2 MHz

6.6

V_DD= 3.3 V 10%,

PAD3V5V = 1

1.6

2.3

4.7

I_RMSMEDCC D Root medium square C_L= 25 pF, 13 MHz V_DD= 5.0 V 10%,

6.6 mA

13.4

18.3

I/O current for

MEDIUM

configuration

PAD3V5V = 0

C_L= 25 pF, 40 MHz

C_L= 100 pF, 13 MHz

C_L= 25 pF, 13 MHz V_DD= 3.3 V 10%,

PAD3V5V = 1

C_L= 25 pF, 40 MHz

8.5

C_L= 100 pF, 13 MHz

I_RMSFST

CC D Root medium square C_L= 25 pF, 40 MHz V_DD= 5.0 V 10%,

I/O current for FAST

configuration

PAD3V5V = 0

C_L= 25 pF, 64 MHz

C_L= 100 pF, 40 MHz

C_L= 25 pF, 40 MHz V_DD= 3.3 V 10%,

PAD3V5V = 1

C_L= 25 pF, 64 MHz

C_L= 100 pF, 40 MHz

I_AVGSEG

SR D Sum of all the static V_DD= 5.0 V 10%, PAD3V5V = 0

I/O current within a

V_DD= 3.3 V 10%, PAD3V5V = 1

supply segment

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to125 °C, unless otherwise specified

Stated maximum values represent peak consumption that lasts only a few ns during I/O transition.

Table 19 provides the weight of concurrent switching I/Os.

In order to ensure device functionality, the sum of the weight of concurrent switching I/Os on a single segment should remain

below the 100%.

Table 19. I/O weight

144/100 LQFP

64 LQFP²

PAD

Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V

SRE=0

SRE=1

SRE=0

SRE=1

SRE=0

SRE=1

SRE=0

SRE=1

PB[3]

PC[9]

10%

—

12%

11%

—

10%

—

12%

11%

—

PC[14]

PC[15]

—

13%

12%

13%

12%

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Table 19. I/O weight

144/100 LQFP

64 LQFP²

PAD

Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V

SRE=0

SRE=1

SRE=0

SRE=1

SRE=0

SRE=1

SRE=0

SRE=1

PG[5]

PG[4]

PG[3]

PG[2]

PA[2]

—

12%

—

11%

10%

—

11%

—

12%

—

11%

10%

—

11%

—

12%

—

10%

—

12%

—

10%

—

PE[0]

PA[1]

—

PE[1]

PE[8]

PE[9]

PE[10]

PA[0]

10%

—

10%

—

PE[11]

PG[9]

PG[8]

PC[11]

PC[10]

PG[7]

PG[6]

PB[0]

PB[1]

PF[9]

—

10%

11%

12%

11%

10%

—

10%

11%

12%

11%

10%

—

13%

14%

—

12%

—

13%

14%

—

12%

—

10%

—

PF[8]

15%

—

13%

—

15%

—

13%

—

PF[12]

PC[6]

PC[7]

PF[10]

PF[11]

PA[15]

PF[13]

PA[14]

PA[4]

—

14%

—

12%

—

14%

—

12%

—

12%

—

11%

—

12%

—

11%

—

11%

—

10%

—

11%

—

10%

—

PA[13]

10%

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Table 19. I/O weight

144/100 LQFP

64 LQFP²

PAD

Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V

SRE=0

SRE=1

SRE=0

SRE=1

SRE=0

SRE=1

SRE=0

SRE=1

PA[12]

PB[9]

PB[8]

PB[10]

PF[0]

PF[1]

PF[2]

PF[3]

PF[4]

PF[5]

PF[6]

PF[7]

PD[0]

PD[1]

PD[2]

PD[3]

PD[4]

PD[5]

PD[6]

PD[7]

PD[8]

PB[4]

PB[5]

PB[6]

PB[7]

PD[9]

PD[10]

PD[11]

PB[11]

PD[12]

PB[12]

PD[13]

PB[13]

11%

10%

—

17%

18%

—

10%

11%

21%

—

10%

13%

12%

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Table 19. I/O weight

144/100 LQFP

64 LQFP²

PAD

Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V

SRE=0

SRE=1

SRE=0

SRE=1

SRE=0

SRE=1

SRE=0

SRE=1

PD[14]

PB[14]

PD[15]

PB[15]

PA[3]

10%

—

12%

11%

10%

—

18%

17%

16%

15%

14%

11%

10%

—

21%

20%

19%

18%

17%

14%

12%

11%

10%

—

PG[13]

PG[12]

PH[0]

13%

12%

—

11%

—

26%

25%

—

23%

22%

—

PH[1]

PH[2]

PH[3]

PG[1]

PG[0]

PF[15]

PF[14]

PE[13]

PA[7]

—

25%

—

22%

—

23%

—

21%

—

PA[8]

—

PA[9]

—

PA[10]

PA[11]

PE[12]

PG[14]

PG[15]

PE[14]

PE[15]

PG[10]

PG[11]

PC[3]

—

10%

—

14%

—

12%

—

12%

—

11%

—

11%

—

10%

—

PC[2]

—

PA[5]

PA[6]

PC[1]

—

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Table 19. I/O weight

144/100 LQFP

64 LQFP²

PAD

Weight 5V Weight 5V Weight 3.3V Weight 3.3V Weight 5V Weight 5V Weight 3.3V Weight 3.3V

SRE=0

SRE=1

SRE=0

SRE=1

SRE=0

SRE=1

SRE=0

SRE=1

PC[0]

PE[2]

PE[3]

PC[5]

PC[4]

PE[4]

PE[5]

PH[4]

PH[5]

PH[6]

PH[7]

PH[8]

PE[6]

PE[7]

PC[12]

PC[13]

PC[8]

PB[2]

10%

11%

12%

13%

—

10%

11%

12%

13%

—

10%

11%

—

10%

11%

—

10%

11%

12%

10%

11%

12%

13%

14%

—

12%

13%

—

13%

14%

—

12%

13%

—

10%

—

15%

13%

15%

13%

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to125 °C, unless otherwise specified

All 64 LQFPinformation is indicative and must be confirmed during silicon validation.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.8

RESET electrical characteristics

The device implements a dedicated bidirectional RESET pin.

Figure 8. Start-up reset requirements

DDMIN

RESET

device reset forced by RESET

device start-up phase

Figure 9. Noise filtering on reset signal

V_RESET

hw_rst

‘1’

‘0’

filtered by

lowpass filter

unknown reset

state

filtered by

hysteresis

filtered by

lowpass filter

device under hardware reset

FRST

NFRST

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Table 20. Reset electrical characteristics

Value

Symbol

Parameter

Conditions¹

Unit

Min

Typ

Max

V_IHSR P Input High Level CMOS

(Schmitt Trigger)

—

0.65V_DD

—

V_DD+0.4

V_ILSR P Input low Level CMOS

(Schmitt Trigger)

0.4

0.1V_DD

—

0.35V_DD

—

V_HYSCC C Input hysteresis CMOS

(Schmitt Trigger)

V_OLCC P Output low level

Push Pull, I_OL= 2mA,

0.1V_DD

V_DD= 5.0 V 10%, PAD3V5V = 0

(recommended)

Push Pull, I_OL= 1mA,

—

0.1V_DD

0.5

V_DD= 5.0 V 10%, PAD3V5V = 1²

Push Pull, I_OL= 1mA,

V_DD= 3.3 V 10%, PAD3V5V = 1

(recommended)

T_tr

CC D Output transition time

output pin³

C_L= 25pF,

V_DD= 5.0 V 10%, PAD3V5V = 0

—

C_L= 50pF,

V_DD= 5.0 V 10%, PAD3V5V = 0

C_L= 100pF,

V_DD= 5.0 V 10%, PAD3V5V = 0

—

C_L= 25pF,

V_DD= 3.3 V 10%, PAD3V5V = 1

—

C_L= 50pF,

V_DD= 3.3 V 10%, PAD3V5V = 1

—

C_L= 100pF,

V_DD= 3.3 V 10%, PAD3V5V = 1

—

W_FRSTSR P RESET input filtered

pulse

—

µA

W_NFRSTSR P RESET input not filtered

pulse

—

1000

|I_WPU

CC P Weak pull-up current

V_DD= 3.3 V 10%, PAD3V5V = 1

V_DD= 5.0 V 10%, PAD3V5V = 0

V_DD= 5.0 V 10%, PAD3V5V = 1²

—

150

250

absolute value

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified

This transient configuration does not occurs when device is used in the V_DD= 3.3 V 10% range.

C_Lincludes device and package capacitance (C_PKG< 5 pF).

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.9

Power management electrical characteristics

Voltage regulator electrical characteristics

4.9.1

The device implements an internal voltage regulator to generate the low voltage core supply V

from the high voltage

DD_LV

ballast supply V

. The regulator itself is supplied by the common I/O supply V . The following supplies are involved:

DD_BV

•

HV—High voltage external power supply for voltage regulator module. This must be provided externally through V

power pin.

BV—High voltage external power supply for internal ballast module. This must be provided externally through

power pin. Voltage values should be aligned with V

DD_BV

LV—Low voltage internal power supply for core, FMPLL and flash digital logic. This is generated by the internal

voltage regulator but provided outside to connect stability capacitor. It is further split into four main domains to ensure

noise isolation between critical LV modules within the device:

— LV_COR—Low voltage supply for the core. It is also used to provide supply for FMPLL through double bonding.

— LV_CFLA—Low voltage supply for code flash module. It is supplied with dedicated ballast and shorted to

LV_COR through double bonding.

— LV_DFLA—Low voltage supply for data flash module. It is supplied with dedicated ballast and shorted to

LV_COR through double bonding.

— LV_PLL—Low voltage supply for FMPLL. It is shorted to LV_COR through double bonding.

Figure 10. Voltage regulator capacitance connection

(LV_COR/LV_CFLA)

REG2

GND

DD_LV

SS_LV

DD_BV

DD_LVn

SS_LVn

REF

DD_BV

DD_LV

DEVICE

Voltage Regulator

SS_LV

GND

SS_LV

DD_LV

DEVICE

GND

(supply/IO decoupling)

(LV_COR/LV_PLL)

DEC2

REG3

The internal voltage regulator requires external capacitance (C

) to be connected to the device in order to provide a stable

REGn

low voltage digital supply to the device. Capacitances should be placed on the board as near as possible to the associated pins.

Care should also be taken to limit the serial inductance of the board to less than 5 nH.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Each decoupling capacitor must be placed between each of the three V

supply pairs to ensure stable voltage (see

DD_LV SS_LV

Section 4.5, “Recommended operating conditions).

Table 21. Voltage regulator electrical characteristics

Value

Symbol

Parameter

Conditions¹

Unit

Min

Typ

Max

C_REGn

R_REG

SR — Internal voltage regulator external

capacitance

—

200

—

500



SR — Stability capacitor equivalent serial

resistance

—

100³

400

—

0.2

—

C_DEC1

SR — Decoupling capacitance²ballast

_{DD_BV}/V_{SS_LV}pair:

_{DD_BV}= 4.5 V to 5.5 V

470⁴

_{DD_BV}/V_{SS_LV}pair:

V_{DD_BV}= 3 V to 3.6 V

C_DEC2

V_MREG

SR — Decoupling capacitance regulator

supply

V_DD/V_SSpair

100

CC T Main regulator output voltage

Before exiting from

reset

—

1.32

After trimming

—

1.15

—

1.28

—

1.32

150

I_MREG

SR — Main regulator current provided to

V_{DD_LV}domain

I_MREGINTCC D Main regulator module current

consumption

I_MREG= 200 mA

I_MREG= 0 mA

—

V_LPREG

I_LPREG

CC P Low power regulator output voltage After trimming

1.15

—

1.23

—

1.32

SR — Low power regulator current

provided to V_{DD_LV}domain

—

I_LPREGINTCC D Low power regulator module current I_LPREG= 15 mA;

—

600

—

µA

consumption

T_A= 55 °C

—

I_LPREG= 0 mA;

T_A= 55 °C

V_ULPREGCC P Ultra low power regulator output

voltage

After trimming

1.15

—

1.23

—

1.32

I_ULPREG

SR — Ultra low power regulator current

provided to V_{DD_LV}domain

—

µA

I_ULPREGINTCC D Ultra low power regulator module

current consumption

I_ULPREG= 5 mA;

T_A= 55 °C

—

100

—

I_ULPREG= 0 mA;

T_A= 55 °C

—

I_{DD_BV}

CC D In-rush current on V_{DD_BV}during

power-up⁵

—

400⁶mA

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified

This capacitance value is driven by the constraints of the external voltage regulator supplying the V_{DD_BV}voltage.

A typical value is in the range of 470 nF.

This value is acceptable to guarantee operation from 4.5 V to 5.5 V

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

External regulator and capacitance circuitry must be capable of providing I_{DD_BV}while maintaining supply V_{DD_BV}

in operating range.

In-rush current is seen only for short time during power-up and on standby exit (max 20 µs, depending on external

LV capacitances to be load)

The duration of the in-rush current depends on the capacitance placed on LV pins. BV decaps must be sized

accordingly. Refer to IMREG value for minimum amount of current to be provided in cc.

4.9.2

Voltage monitor electrical characteristics

The device implements a Power-on Reset (POR) module to ensure correct power-up initialization, as well as four low voltage

detectors (LVDs) to monitor the V and the V voltage while device is supplied:

DD_LV

•

POR monitors V during the power-up phase to ensure device is maintained in a safe reset state

LVDHV3 monitors V to ensure device reset below minimum functional supply

LVDHV5 monitors V when application uses device in the 5.0 V ± 10% range

LVDLVCOR monitors power domain No. 1

LVDLVBKP monitors power domain No. 0

NOTE

When enabled, power domain No. 2 is monitored through LVD_DIGBKP.

Figure 11. Low voltage monitor vs reset

LVDHVxH

LVDHVxL

RESET

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Table 22. Low voltage monitor electrical characteristics

Value

Typ

Symbol

Parameter

Conditions¹

Unit

Min

Max

V_PORUP

V_PORH

SR P Supply for functional POR module

CC P Power-on reset threshold

—

1.0

1.5

—

5.5

2.6

T_A= 25 °C,

after trimming

—

1.5

—

2.6

2.95

2.9

V_LVDHV3HCC T LVDHV3 low voltage detector high threshold

V_LVDHV3LCC P LVDHV3 low voltage detector low threshold

V_LVDHV5HCC T LVDHV5 low voltage detector high threshold

V_LVDHV5LCC P LVDHV5 low voltage detector low threshold

V_LVDLVCORLCC P LVDLVCOR low voltage detector low threshold

V_LVDLVBKPLCC P LVDLVBKP low voltage detector low threshold

2.6

—

4.5

3.8

1.08

4.4

1.15

1.14

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified

4.10 Low voltage domain power consumption

Table 23 provides DC electrical characteristics for significant application modes. These values are indicative values; actual

consumption depends on the application.

Table 23. Low voltage power domain electrical characteristics

Value

Symbol

Parameter

Conditions¹

Unit

115 140³mA

Min Typ Max

I_DDMAX

CC D RUN mode maximum

average current

—

I_DDRUN

CC T RUN modetypicalaverage f_CPU= 8 MHz

current⁵

—

f_CPU= 16 MHz

f_CPU= 32 MHz

f_CPU= 48 MHz

f_CPU= 64 MHz

I_DDHALT

CC C HALT mode current⁶

Slow internal RC oscillator T_A= 25 °C

(128 kHz) running

T_A= 125 °C

I_DDSTOPCC P STOP mode current⁷

Slow internal RC oscillator T_A= 25 °C

180 700⁸µA

(128 kHz) running

T_A= 55 °C

500

—

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

—

4.5

12⁸

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Table 23. Low voltage power domain electrical characteristics (continued)

Value

Symbol

Parameter

Conditions¹

Unit

Min Typ Max

I_DDSTDBY2CC P STANDBY2 mode current⁹Slow internal RC oscillator T_A= 25 °C

(128 kHz) running

—

100

—

µA

T_A= 55 °C

T_A= 85 °C

180

315

—

T_A= 105 °C

—

T_A= 125 °C

560 1700

I_DDSTDBY1CC T STANDBY1 mode

Slow internal RC oscillator T_A= 25 °C

—

µA

current¹⁰

(128 kHz) running

T_A= 55 °C

T_A= 85 °C

T_A= 105 °C

T_A= 125 °C

100

165

280

—

900

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified

Running consumption is given on voltage regulator supply (V_DDREG). I_DDMAXis composed of three components:

I_DDMAX= I_DD(vdd_bv) + I_DD(vdd_hv) + I_DD(Vdd_hv_adc). It does not include a fourth component linked to I/Os

toggling which is highly dependent on the application. The given value is thought to be a worst case value with all

peripherals running, and code fetched from code flash while modify operation on-going on data flash. It is to be

noticed that this value can be significantly reduced by application: switch-off not used peripherals (default), reduce

peripheral frequency through internal prescaler, fetch from RAM most used functions, use low power mode when

possible.

Higher current may be sinked by device during power-up and standby exit. please refer to in rush current on Table 21.

RUN current measured with typical application with accesses on both flash and RAM.

Only for the “P” classification: Data and Code Flash in Normal Power. Code fetched from RAM: Serial IPs CAN and

LIN in loop back mode, DSPi as Master, PLL as system Clock (4 x Multiplier) peripherals on (eMIOS/CTU/ADC) and

running at max frequency, periodic SW/WDG timer reset enabled.

Data Flash Power Down. Code Flash in Low Power. RC-osc128kHz & RC-OSC 16MHz on. 10MHz XTAL clock.

FlexCAN: instances: 0, 1, 2 ON (clocked but not reception or transmission), instances: 4, 5, 6 clock gated. LINFlex:

instances: 0, 1, 2 ON (clocked but not reception or transmission), instance: 3 clock gated. eMIOS: instance: 0 ON

(16 channels on PA[0]-PA[11] and PC[12]-PC[15]) with PWM 20kHz, instance: 1 clock gated. DSPI: instance: 0

(clocked but no communication). RTC/API ON.PIT ON. STM ON. ADC ON but not conversion except 2 analogue

watchdog

Only for the “P” classification: No clock, RC 16MHz off, RC128kHz on, PLL off, HPvreg off, ULPVreg/LPVreg on. All

possible peripherals off and clock gated. Flash in power down mode.

When going from RUN to STOP mode and the core consumption is > 6 mA , it is normal operation for the main

regulator module to be kept on by the on-chip current monitoring circuit. This is most likely to occur with junction

temperatures exceeding 125 °C and under these circumstances, it is possible for the current to initially exceed the

maximum STOP specification by up to 2 mA. After entering stop, the application junction temperature will reduce to

the ambient level and the main regulator will be automatically switched off when the load current is below 6 mA.

Only for the “P” classification: ULPreg on, HP/LPVreg off, 32kB RAM on, device configured for minimum

consumption, all possible modules switched-off.

¹⁰ULPreg on, HP/LPVreg off, 8kB RAM on, device configured for minimum consumption, all possible modules

switched-off.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.11 Flash memory electrical characteristics

4.11.1 Program/Erase characteristics

Table 24 shows the program and erase characteristics.

Table 24. Program and erase specifications

Value

Symbol

Parameter

Unit

Initial

max²

Min

Typ¹

Max³

T_dwprogramCC C Double word (64 bits) program time⁴

—

300

400

800

—

500

600

1300

500

5000

7500

µs

T_16Kpperase

T_32Kpperase

T_128Kpperase

T_esus

16 KB block pre-program and erase time

32 KB block pre-program and erase time

128 KB block pre-program and erase time

CC D Erase Suspend Latency

Typical program and erase times assume nominal supply values and operation at 25 °C.

Initial factory condition: < 100 program/erase cycles, 25 °C, typical supply voltage.

The maximum program and erase times occur after the specified number of program/erase cycles. These maximum

values are characterized but not guaranteed.

Actual hardware programming times. This does not include software overhead.

Table 25. Flash module life

Value

Symbol

Parameter

Conditions

Unit

Min

Typ

Max

P/E

CC C Number of program/erase cycles per

block for 16 KB blocks over the

—

100,000

—

cycles

operating temperature range (T_J)

P/E

CC C Number of program/erase cycles per

block for 32 KB blocks over the

—

10,000 100,000

1,000 100,000

—

cycles

operating temperature range (T_J)

CC C Number of program/erase cycles per

block for 128 KB blocks over the

operating temperature range (T_J)

Retention CC C Minimum data retention at 85 °C

average ambient temperature¹

Blocks with 0–1,000 P/E

cycles

—

years

Blocks with

1,001–10,000 P/E

cycles

Blocks with

—

years

10,001–100,000 P/E

cycles

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Ambient temperature averaged over duration of application, not to exceed recommended product operating

temperature range.

ECC circuitry provides correction of single bit faults and is used to improve further automotive reliability results.

Some units will experience single bit corrections throughout the life of the product with no impact to product

reliability.

Table 26. Flash read access timing

Symbol

Parameter

Conditions¹

Max Unit

f_READCC P Maximum frequency for Flash reading

2 wait states

1 wait state

0 wait states

MHz

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.11.2 Flash power supply DC characteristics

Table 27 shows the power supply DC characteristics on external supply.

Table 27. Code Flash power supply DC electrical characteristics

Value

Symbol

Parameter

Conditions¹

Unit

Min Typ Max

I_FREADCC D Sum of the current consumption on

V_DDHVand V_DDBVon read access

Code Flash module read

f_CPU= 64 MHz³

—

33 mA

Data Flash module read

_CPU= 64 MHz³

I_FMODCC D Sum of the current consumption on

Program/Erase on-going while

reading Code Flash registers

33 mA

V_DDHVand V_DDBVon matrix

modification (program/erase)

_CPU= 64 MHz³

Program/Erase on-going while

reading Data Flash registers

—

_CPU= 64 MHz³

I_FLPWCC D Sum of the current consumption on

V_DDHVand V_DDBV

during Code Flash low-power

mode

—

900 µA

900

during Data Flash low-power

mode

I_FPWDCC D Sum of the current consumption on

V_DDHVand V_DDBV

during Code Flash power-down

mode

150 µA

150

during Data Flash power-down

mode

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified

This value is only relative to the actual duration of the read cycle

f_CPU64 MHz can be achieved only at up to 105 °C

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.11.3 Start-up/Switch-off timings

Table 28. Start-up time/Switch-off time

Value

Unit

Symbol

Parameter

Conditions¹

Min

Typ

Max

T_FLARSTEXITCC T Delay for Flash module to exit reset mode

Code Flash

Data Flash

Code Flash

Data Flash

Code Flash

Data Flash

Code Flash

Data Flash

Code Flash

Data Flash

—

125

0.5

µs

T_FLALPEXIT

CC T Delay for Flash module to exit low-power

mode

T_FLAPDEXIT

CC T Delay for Flash module to exit power-down

mode

T_FLALPENTRYCC T Delay for Flash module to enter low-power

0.5

1.5

mode

T_FLAPDENTRYCC T

Delay for Flash module to enter power-down

mode

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.12 Electromagnetic compatibility (EMC) characteristics

Susceptibility tests are performed on a sample basis during product characterization.

4.12.1 Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical application environment and simplified

MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in

particular.

Therefore it is recommended that the user apply EMC software optimization and prequalification tests in relation with the EMC

level requested for his application.

•

Software recommendations:The software flowchart must include the management of runaway conditions such as:

— Corrupted program counter

— Unexpected reset

— Critical data corruption (control registers...)

•

Prequalification trials:Most of the common failures (unexpected reset and program counter corruption) can be

reproduced by manually forcing a low state on the reset pin or the oscillator pins for 1 second.

To complete these trials, ESD stress can be applied directly on the device. When unexpected behavior is detected, the

software can be hardened to prevent unrecoverable errors occurring.

4.12.2 Electromagnetic interference (EMI)

The product is monitored in terms of emission based on a typical application. This emission test conforms to the IEC 61967-1

standard, which specifies the general conditions for EMI measurements.

1,2

Table 29. EMI radiated emission measurement

Value

Symbol

Parameter

Conditions

Unit

Min Typ Max

—

SR — Scan range

—

0.150

—

1000 MHz

f_CPUSR — Operating frequency

V_{DD_LV}SR — LV operating voltages

S_EMICC T Peak level

—

MHz

—

1.28

—

V_DD= 5 V, T_A= 25 °C,

LQFP144 package

No PLL frequency

modulation

—

18 dBµV

Test conforming to IEC 61967-2,

f_OSC= 8 MHz/f_CPU= 64 MHz

2% PLL frequency

modulation

—

14 dBµV

EMI testing and I/O port waveforms per IEC 61967-1, -2, -4

For information on conducted emission and susceptibility measurement (norm IEC 61967-4), please contact your

local marketing representative.

4.12.3 Absolute maximum ratings (electrical sensitivity)

Based on two different tests (ESD and LU) using specific measurement methods, the product is stressed in order to determine

its performance in terms of electrical sensitivity.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.12.3.1 Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according

to each pin combination. The sample size depends on the number of supply pins in the device (3 parts*(n+1) supply pin). This

test conforms to the AEC-Q100-002/-003/-011 standard.

1 2

Table 30. ESD absolute maximum ratings

Symbol

Ratings

Conditions

T_A= 25 °C

Class Max value

Unit

V_ESD(HBM)CC T Electrostatic discharge voltage

(Human Body Model)

H1C

2000

conforming to AEC-Q100-002

V_ESD(MM)CC T Electrostatic discharge voltage

(Machine Model)

T_A= 25 °C

conforming to AEC-Q100-003

200

V_ESD(CDM)CC T Electrostatic discharge voltage

(Charged Device Model)

T_A= 25 °C

conforming to AEC-Q100-011

C3A

500

750 (corners)

All ESD testing is in conformity with CDF-AEC-Q100 Stress Test Qualification for Automotive Grade Integrated

Circuits.

A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device

specification requirements. Complete DC parametric and functional testing shall be performed per applicable

device specification at room temperature followed by hot temperature, unless specified otherwise in the device

specification.

4.12.3.2 Static latch-up (LU)

Two complementary static tests are required on six parts to assess the latch-up performance:

•

A supply overvoltage is applied to each power supply pin.

A current injection is applied to each input, output and configurable I/O pin.

These tests are compliant with the EIA/JESD 78 IC latch-up standard.

Table 31. Latch-up results

Parameter Conditions

Symbol

LU CC

Class

T Static latch-up class

T_A= 125 °C

II level A

conforming to JESD 78

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.13 Fast external crystal oscillator (4 to 16 MHz) electrical

characteristics

The device provides an oscillator/resonator driver. Figure 12 describes a simple model of the internal oscillator driver and

provides an example of a connection for an oscillator or a resonator.

Table 32 provides the parameter description of 4 MHz to 16 MHz crystals used for the design simulations.

Figure 12. Crystal oscillator and resonator connection scheme

EXTAL

XTAL

DEVICE

EXTAL

XTAL

DEVICE

XTAL

DEVICE

Note: XTAL/EXTAL must not be directly used to drive external circuits.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Shunt

Table 32. Crystal description

Crystal

motional

capacitance

(C_m) fF

Crystal

motional

inductance

(L_m) mH

Load on

capacitance

between

xtalout

Nominal

frequency

(MHz)

equivalent

series

NDK crystal

reference

xtalin/xtalout

C1 = C2

(pF)¹

resistance

ESR 

and xtalin

C0²(pF)

NX8045GB

NX5032GA

300

150

120

2.68

2.46

2.93

3.11

3.90

591.0

160.7

86.6

2.93

3.01

2.91

2.93

3.00

56.5

25.3

The values specified for C1 and C2 are the same as used in simulations. It should be ensured that the testing

includes all the parasitics (from the board, probe, crystal, etc.) as the AC / transient behavior depends upon them.

The value of C0 specified here includes 2 pF additional capacitance for parasitics (to be seen with bond-pads,

package, etc.).

Figure 13. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics

S_MTRANS bit (ME_GS register)

‘1’

‘0’

XTAL

1/f

FXOSC

90%

10%

FXOSCOP

valid internal clock

FXOSCSU

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Table 33. Fast external crystal oscillator (4 to 16 MHz) electrical characteristics

Value

Symbol

Parameter

Conditions¹

Unit

Min

Typ

Max

f_FXOSC

SR — Fast external crystal

oscillator frequency

—

4.0

—

16.0

MHz

g_mFXOSCCC C Fast external crystal

oscillator

V_DD= 3.3 V 10%,

PAD3V5V = 1

OSCILLATOR_MARGIN = 0

2.2

2.0

2.7

2.5

—

8.2

7.4

9.7

9.2

mA/V

transconductance

CC P

CC C

V_DD= 5.0 V 10%,

PAD3V5V = 0

OSCILLATOR_MARGIN = 0

V_DD= 3.3 V 10%,

PAD3V5V = 1

OSCILLATOR_MARGIN = 1

V_DD= 5.0 V 10%,

PAD3V5V = 0

OSCILLATOR_MARGIN = 1

V_FXOSC

CC T Oscillation amplitude at

EXTAL

f_OSC= 4 MHz,

OSCILLATOR_MARGIN = 0

1.3

—

_OSC= 16 MHz,

OSCILLATOR_MARGIN = 1

V_FXOSCOPCC P Oscillation operating point

—

0.95

I_FXOSC

CC T Fast external crystal

oscillator consumption

T_FXOSCSUCC T Fast external crystal

oscillator start-up time

f_OSC= 4 MHz,

OSCILLATOR_MARGIN = 0

—

f_OSC= 16 MHz,

OSCILLATOR_MARGIN = 1

1.8

V_IH

V_IL

SR P Input high level CMOS

(Schmitt Trigger)

Oscillator bypass mode

0.65V_DD

0.4

V_DD+0.4

0.35V_DD

SR P Input low level CMOS

(Schmitt Trigger)

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified

Stated values take into account only analog module consumption but not the digital contributor (clock tree and

enabled peripherals)

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.14 Slow external crystal oscillator (32 kHz) electrical characteristics

The device provides a low power oscillator/resonator driver.

Figure 14. Crystal oscillator and resonator connection scheme

OSC32K_EXTAL

OSC32K_XTAL

DEVICE

Note: OSC32K_XTAL/OSC32K_EXTAL must not be directly used to drive external circuits.

Figure 15. Equivalent circuit of a quartz crystal

Crystal

R_m

L_m

C_m

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Symbol

Table 34. Crystal motional characteristics

Value

Typ

Parameter

Conditions

Unit

Min

Max

L_m

Motional inductance

Motional capacitance

—

11.796

—

C_m

C1/C2 Load capacitance at OSC32K_XTAL and

OSC32K_EXTAL with respect to ground²

—

AC coupled @ C0 = 2.85 pF⁴

AC coupled @ C0 = 4.9 pF⁴

AC coupled @ C0 = 7.0 pF⁴

AC coupled @ C0 = 9.0 pF⁴

—

k

R_m

Motional resistance

The crystal used is Epson Toyocom MC306.

This is the recommended range of load capacitance at OSC32K_XTAL and OSC32K_EXTAL with respect to

ground. It includes all the parasitics due to board traces, crystal and package.

Maximum ESR (R_m) of the crystal is 50 k

C0 Includes a parasitic capacitance of 2.0 pF between OSC32K_XTAL and OSC32K_EXTAL pins

Figure 16. Slow external crystal oscillator (32 kHz) electrical characteristics

OSCON bit (OSC_CTL register)

OSC32K_XTAL

1/f

SXOSC

90%

10%

valid internal clock

SXOSCSU

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Table 35. Slow external crystal oscillator (32 kHz) electrical characteristics

Value

Symbol

Parameter

Conditions¹

Unit

Min

Typ

Max

f_SXOSC

SR — Slow external crystal oscillator

frequency

—

32.768

kHz

V_SXOSC

CC T Oscillation amplitude

—

2.1

2.5

—

I_SXOSCBIASCC T Oscillation bias current

µA

I_SXOSC

CC T Slow external crystal oscillator

consumption

T_SXOSCSUCC T Slow external crystal oscillator

start-up time

—

2²

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified

Start-up time has been measured with EPSON TOYOCOM MC306 crystal. Variation may be seen with other crystal

4.15 FMPLL electrical characteristics

The device provides a frequency-modulated phase-locked loop (FMPLL) module to generate a fast system clock from the main

oscillator driver.

Table 36. FMPLL electrical characteristics

Value

Symbol

Parameter

Conditions¹

Unit

Min

Typ

Max

f_PLLINSR — FMPLL reference clock²

—

MHz

_PLLINSR — FMPLL reference clock duty

cycle²

f_PLLOUTCC D FMPLL output clock frequency

—

MHz

f_VCO

CC P VCO frequency without

frequency modulation

256

512 MHz

C VCO frequency with frequency

modulation

—

245

—

533

f_CPUSR — System clock frequency

f_FREECC P Free-running frequency

t_LOCKCC P FMPLL lock time

—

MHz

—

150 MHz

Stable oscillator (f_PLLIN= 16 MHz)

100

µs

t_LTJITCC — FMPLL long term jitter

f_PLLIN= 16 MHz (resonator),

f_PLLCLK@ 64 MHz, 4000 cycles

—

I_PLL

CC C FMPLL consumption

T_A= 25 °C

—

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified.

PLLIN clock retrieved directly from FXOSC clock. Input characteristics are granted when oscillator is used in

functional mode. When bypass mode is used, oscillator input clock should verify f_PLLINand _PLLIN

Frequency modulation is considered 4%

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.16 Fast internal RC oscillator (16 MHz) electrical characteristics

The device provides a 16 MHz fast internal RC oscillator. This is used as the default clock at the power-up of the device.

Table 37. Fast internal RC oscillator (16 MHz) electrical characteristics

Value

Symbol

f_FIRC

Parameter

Conditions¹

Unit

Min

Typ

Max

CC P Fast internal RC oscillator high T_A= 25 °C, trimmed

frequency

—

MHz

SR —

—

I_FIRCRUN

CC T Fast internal RC oscillator high T_A= 25 °C, trimmed

—

200

µA

frequency current in running

mode

I_FIRCPWDCC D Fast internal RC oscillator high T_A= 125 °C

frequency current in power

—

down mode

I_FIRCSTOPCC T Fast internal RC oscillator high T_A= 25 °C sysclk = off

frequency and system clock

—

500

600

700

900

1250

1.1

—

2.0

sysclk = 2 MHz

current in stop mode

sysclk = 4 MHz

sysclk = 8 MHz

sysclk = 16 MHz

T_FIRCSUCC C Fast internal RC oscillator

start-up time

V_DD= 5.0 V 10%

µs

_FIRCPRECC T Fast internal RC oscillator

precision after software

T_A= 25 °C

1

—

trimming of f_FIRC

_FIRCTRIMCC T Fast internal RC oscillator

—

1.6

—

trimming step

_FIRCVARCC P Fast internal RC oscillator

variation in overtemperature

and supply with respect to f_FIRC

at T_A= 25 °C in high-frequency

configuration

—

5

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified.

This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is

ON.

4.17 Slow internal RC oscillator (128 kHz) electrical characteristics

The device provides a 128 kHz slow internal RC oscillator. This can be used as the reference clock for the RTC module.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Table 38. Slow internal RC oscillator (128 kHz) electrical characteristics

Value

Symbol

Parameter

Conditions¹

Unit

Min Typ Max

f_SIRC

CC P Slow internal RC oscillator low

T_A= 25 °C, trimmed

—

100

—

128

—

150

kHz

frequency

SR —

I_SIRC

CC C Slow internal RC oscillator low

frequency current

T_A= 25 °C, trimmed

—

µA

µs

T_SIRCSUCC P Slow internal RC oscillator start-up T_A= 25 °C, V_DD= 5.0 V 10%

time

—

2

_SIRCPRECC C Slow internal RC oscillator precision T_A= 25 °C

—

2.7

—

after software trimming of f_SIRC

_SIRCTRIMCC C Slow internal RC oscillator trimming

—

step

_SIRCVARCC C Slow internal RC oscillator variation High frequency configuration

in temperature and supply with

10

+10

respect to f_SIRCat T_A= 55 °C in high

frequency configuration

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified.

This does not include consumption linked to clock tree toggling and peripherals consumption when RC oscillator is

ON.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.18 ADC electrical characteristics

4.18.1 Introduction

The device provides a 10-bit Successive Approximation Register (SAR) analog-to-digital converter.

Figure 17. ADC characteristic and error definitions

Offset Error OSE

Gain Error GE

1023

1022

1021

1020

1019

1 LSB ideal = V

/ 1024

DD_ADC

1018

(2)

code out

(1)

(1) Example of an actual transfer curve

(2) The ideal transfer curve

(5)

(3) Differential non-linearity error (DNL)

(4) Integral non-linearity error (INL)

(5) Center of a step of the actual transfer curve

(4)

(3)

1 LSB (ideal)

1017 1018 1019 1020 1021 1022 1023

(LSB

)

ideal

in(A)

Offset Error OSE

4.18.2 Input impedance and ADC accuracy

In the following analysis, the input circuit corresponding to the precise channels is considered.

To preserve the accuracy of the A/D converter, it is necessary that analog input pins have low AC impedance. Placing a capacitor

with good high frequency characteristics at the input pin of the device can be effective: the capacitor should be as large as

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

possible, ideally infinite. This capacitor contributes to attenuating the noise present on the input pin; furthermore, it sources

charge during the sampling phase, when the analog signal source is a high-impedance source.

A real filter can typically be obtained by using a series resistance with a capacitor on the input pin (simple RC filter). The RC

filtering may be limited according to the value of source impedance of the transducer or circuit supplying the analog signal to

be measured. The filter at the input pins must be designed taking into account the dynamic characteristics of the input signal

(bandwidth) and the equivalent input impedance of the ADC itself.

In fact a current sink contributor is represented by the charge sharing effects with the sampling capacitance: C being

substantially a switched capacitance, with a frequency equal to the conversion rate of the ADC, it can be seen as a resistive path

to ground. For instance, assuming a conversion rate of 1 MHz, with C equal to 3 pF, a resistance of 330 k is obtained (R

= 1 / (f *C ), where f represents the conversion rate at the considered channel). To minimize the error induced by the voltage

partitioning between this resistance (sampled voltage on C ) and the sum of R + R + R + R + R , the external circuit

must be designed to respect the Equation 4:

Eqn. 4

R + R + R + R

+ R

--------------------------------------------------------------------------



 -- LSB

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Equation 4 generates a constraint for external network design, in particular on a resistive path. Internal switch resistances (R

and R ) can be neglected with respect to external resistances.

Figure 18. Input equivalent circuit (precise channels)

EXTERNAL CIRCUIT

INTERNAL CIRCUIT SCHEME

Channel

Sampling

Selection

Source

Filter

Current Limiter

SW1

Source Impedance

Filter Resistance

Filter Capacitance

Current Limiter Resistance

Channel Selection Switch Impedance

Sampling Switch Impedance

Pin Capacitance (two contributions, C and C

Sampling Capacitance

SW1

)

Figure 19. Input equivalent circuit (extended channels)

EXTERNAL CIRCUIT

INTERNAL CIRCUIT SCHEME

Channel

Selection

Extended

Switch

Sampling

Source

Filter

Current Limiter

SW2

SW1

Source Impedance

Filter Resistance

Filter Capacitance

Current Limiter Resistance

Channel Selection Switch Impedance (two contributions R

Sampling Switch Impedance

Pin Capacitance (three contributions, C , C and C )

Sampling Capacitance

and R

)

SW2

SW1

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

A second aspect involving the capacitance network shall be considered. Assuming the three capacitances C , C and C are

initially charged at the source voltage V (refer to the equivalent circuit in Figure 18): A charge sharing phenomenon is installed

when the sampling phase is started (A/D switch close).

Figure 20. Transient behavior during sampling phase

Voltage transient on C_S

V <0.5 LSB

₁< (R_SW+ R_AD) C_S<< T_S

₂= R_L(C_S+ C_P1+ C_P2)

In particular two different transient periods can be distinguished:

1. A first and quick charge transfer from the internal capacitance C and C to the sampling capacitance C occurs (C

is supposed initially completely discharged): considering a worst case (since the time constant in reality would be

faster) in which C is reported in parallel to C (call C = C + C ), the two capacitances C and C are in series,

and the time constant is

Eqn. 5

C  C

--------------------

 



= R

+ R

C + C

Equation 5can again be simplified considering only C as an additional worst condition. In reality, the transient is

faster, but the A/D converter circuitry has been designed to be robust also in the very worst case: the sampling time T

is always much longer than the internal time constant:

Eqn. 6



 R

+ R

  C « T

The charge of C and C is redistributed also on C , determining a new value of the voltage V on the capacitance

according to Equation 7:

Eqn. 7

 C + C + C  = V  C + C



2. A second charge transfer involves also C (that is typically bigger than the on-chip capacitance) through the resistance

R : again considering the worst case in which C and C were in parallel to C (since the time constant in reality

would be faster), the time constant is:

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Eqn. 8



 R  C + C + C

P1 P2



In this case, the time constant depends on the external circuit: in particular imposing that the transient is completed

well before the end of sampling time T , a constraints on R sizing is obtained:

Eqn. 9

10   = 10  R  C + C + C   T

P1 P2 S

Of course, R shall be sized also according to the current limitation constraints, in combination with R (source

impedance) and R (filter resistance). Being C definitively bigger than C , C and C , then the final voltage V

P1 P2

(at the end of the charge transfer transient) will be much higher than V . Equation 10 must be respected (charge

balance assuming now C already charged at V ):

Eqn. 10

 C + C + C + C  = V  C + V  C + C + C 

P1 P2 A1 P1 P2

The two transients above are not influenced by the voltage source that, due to the presence of the R C filter, is not able to

provide the extra charge to compensate the voltage drop on C with respect to the ideal source V ; the time constant R C of

F F

the filter is very high with respect to the sampling time (T ). The filter is typically designed to act as anti-aliasing.

Figure 21. Spectral representation of input signal

Analog source bandwidth (V_A)

T_C< 2 R_FC_F(conversion rate vs. filter pole)

Noise

f_F= f₀(anti-aliasing filtering condition)

2 f₀< f_C(Nyquist)

f₀

Anti-aliasing filter (f_F= RC filter pole)

Sampled signal spectrum (f_C= conversion rate)

f_F

f₀

f_C

Calling f the bandwidth of the source signal (and as a consequence the cut-off frequency of the anti-aliasing filter, f ),

according to the Nyquist theorem the conversion rate f must be at least 2f ; it means that the constant time of the filter is greater

than or at least equal to twice the conversion period (T ). Again the conversion period T is longer than the sampling time T ,

which is just a portion of it, even when fixed channel continuous conversion mode is selected (fastest conversion rate at a

specific channel): in conclusion it is evident that the time constant of the filter R C is definitively much higher than the

sampling time T , so the charge level on C cannot be modified by the analog signal source during the time in which the

sampling switch is closed.

The considerations above lead to impose new constraints on the external circuit, to reduce the accuracy error due to the voltage

drop on C ; from the two charge balance equations above, it is simple to derive Equation 11 between the ideal and real sampled

voltage on C :

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Eqn. 11

+ C + C

----------- = -------------------------------------------------------

+ C + C + C

P2 S

From this formula, in the worst case (when V is maximum, that is for instance 5 V), assuming to accept a maximum error of

half a count, a constraint is evident on C value:

Eqn. 12

 2048  C

4.18.3 ADC electrical characteristics

Table 39. ADC input leakage current

Value

Typ

Symbol C

Parameter

Conditions

Unit

Min

Max

I_LKGCC C Input leakage current T_A= 40 °C No current injection on adjacent pin

—

T_A= 25 °C

T_A= 105 °C

T_A= 125 °C

200

400

Table 40. ADC conversion characteristics

Value

Symbol

Parameter

Conditions¹

Unit

Min

Typ

Max

V_{SS_ADC}SR — Voltage on

VSS_HV_ADC (ADC

—

0.1

—

0.1

reference) pin with

respect to ground

(V_SS

)

V_{DD_ADC}SR — Voltage on

VDD_HV_ADC pin

—

V_DD0.1

—

V_DD+0.1

(ADC reference) with

respect to ground

(V_SS

)

V_AINxSR — Analog input voltage³

—

V_{SS_ADC}0.1

—

V_{DD_ADC}+0.1

f_ADCSR — ADC analog frequency

32 + 4% MHz



_{ADC_SYS}SR — ADC digital clock duty ADCLKSEL = 1⁴

µA

µs

cycle (ipg_clk)

I_ADCPWDSR — ADC0 consumption in

power down mode

—

I_ADCRUNSR — ADC0 consumption in

running mode

t_{ADC_PU}SR — ADC power up delay

1.5

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Table 40. ADC conversion characteristics (continued)

Value

Symbol

Parameter

Sample time⁵

Conditions¹

Unit

Min

Typ

Max

t_{ADC_S}CC

f_ADC= 32 MHz,

INPSAMP = 17

0.5

—

µs

_ADC= 6 MHz,

—

0.625

—

INPSAMP = 255

t_{ADC_C}CC

Conversion time⁶

f_ADC= 32 MHz,

INPCMP = 2

µs

k

C_S

CC D ADC input sampling

capacitance

—

C_P1

C_P2

C_P3

CC D ADC input pin

capacitance 1

—

CC D ADC input pin

capacitance 2

—

CC D ADC input pin

capacitance 3

—

R_SW1CC D Internal resistance of

analog source

—

R_SW2CC D Internal resistance of

analog source

—

R_ADCC D Internal resistance of

analog source

—

I_INJ

SR — Input current Injection Current

V_DD

5

injection on one 3.3 V 10%

ADC input,

different from

the converted

one

V_DD

5.0 V 10%

5

| INL | CC

| DNL | CC

Absolute value for

integral non-linearity

No overload

—

0.5

1.5

1.0

LSB

Absolute differential

non-linearity

No overload

| OFS | CC

| GNE | CC

TUEp CC

Absolute offset error

—

2

3

0.5

0.6

—

LSB

Absolute gain error

—

Total unadjusted error⁷Without current injection

for precise channels,

With current injection

input only pins

TUEx CC

Total unadjusted error⁷Without current injection

3

4

LSB

for extended channel

With current injection

V_DD= 3.3 V 10% / 5.0 V 10%, T_A= 40 to 125 °C, unless otherwise specified.

Analog and digital V_SSmust be common (to be tied together externally).

V_AINxmay exceed V_{SS_ADC}and V_{DD_ADC}limits, remaining on absolute maximum ratings, but the results of the

conversion will be clamped respectively to 0x000 or 0x3FF.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Duty cycle is ensured by using system clock without prescaling. When ADCLKSEL = 0, the duty cycle is ensured

by internal divider by 2.

During the sample time the input capacitance C_Scan be charged/discharged by the external source. The internal

resistance of the analog source must allow the capacitance to reach its final voltage level within t_{ADC_S}. After the

end of the sample time t_{ADC_S}, changes of the analog input voltage have no effect on the conversion result. Values

for the sample clock t_{ADC_S}depend on programming.

This parameter does not include the sample time t_{ADC_S}, but only the time for determining the digital result and the

time to load the result’s register with the conversion result.

Total Unadjusted Error: The maximum error that occurs without adjusting Offset and Gain errors. This error is a

combination of Offset, Gain and Integral Linearity errors.

4.19 On-chip peripherals

4.19.1 Current consumption

Table 41. On-chip peripherals current consumption

Value

Typ

Symbol

Parameter

Conditions

Unit

I_{DD_BV(CAN)}

CC T CAN (FlexCAN) supply 500 Kbps Total (static + dynamic)

8 * f_periph+ 85

8 * f_periph+ 27

µA

current on V_{DD_BV}

consumption:

125 Kbps

• FlexCAN in loop-back

mode

• XTAL@ 8MHz used as

CAN engine clock

source

• Messagesendingperiod

is 580 µs

I_{DD_BV(eMIOS)}CC T eMIOS supply current Static consumption:

29 * f_periph

on V_{DD_BV}

• eMIOS channel OFF

• Global prescaler enabled

Dynamic consumption:

• It does not change varying the

frequency (0.003 mA)

I_{DD_BV(SCI)}

CC T SCI (LINFlex) supply

current on V_{DD_BV}

Total (static + dynamic) consumption:

• LIN mode

5 * f_periph+ 31

• Baudrate: 20 Kbps

I_{DD_BV(SPI)}

CC T SPI (DSPI) supply

current on V_{DD_BV}

Ballast static consumption (only

clocked)

Ballast dynamic consumption

(continuous communication):

• Baudrate: 2 Mbit

16 * f_periph

• Trasmission every 8 µs

• Frame: 16 bits

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Table 41. On-chip peripherals current consumption (continued)

Value

Symbol

Parameter

Conditions

Unit

Typ

I_{DD_BV(ADC)}

CC T ADC supply current on V_DD= 5.5 V Ballast static consumption

41 * f_periph

µA

V_{DD_BV}

(no conversion)

_DD= 5.5 V

Ballast dynamic

consumption (continuous

conversion)

5 * f_periph

I_{DD_HV_ADC(ADC)}CC T ADC supply current on V_DD= 5.5 V Analog static consumption

2 * f_periph

V_{DD_HV_ADC}

(no conversion)

V_DD= 5.5 V

Analog dynamic

consumption (continuous

conversion)

75 * f_periph+ 32

I_{DD_HV(FLASH)}CC T CFlash + DFlash

supply current on

—

8.21

µA

V_{DD_HV_ADC}

I_{DD_HV(PLL)}

CC T PLL supply current on V_DD= 5.5 V

V_{DD_HV}

—

3 * f_periph

Operating conditions: T_A= 25 °C, f_periph= 8 MHz to 64 MHz

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

4.19.2 DSPI characteristics

Table 42. DSPI characteristics

DSPI0/DSPI1

DSPI2

No.

Symbol

Parameter

Unit

Min

Typ

Max

Min

Typ

Max

t_SCK

SR D SCK cycle time

Master mode

(MTFE = 0)

125

—

333

—

Slave mode

(MTFE = 0)

125

—

333

125

—

Master mode

(MTFE = 1)

Slave mode

(MTFE = 1)

—

f_DSPI

SR D DSPI digital controller frequency

—

f_CPU

130²

—

f_CPU

15³

MHz

t_CSCCC D Internal delay between pad Master mode

associated to SCK and pad

associated to CSn in

master mode for CSn1->0

—

t_ASCCC D Internal delay between pad Master mode

associated to SCK and pad

—

130³

—

130³

associated to CSn in

master mode for CSn1->1

t_CSCextSR D CS to SCK delay

Slave mode

Master mode

Slave mode

—

t_ASCextSR D After SCK delay

1/f_DSPI+ 5

—

t_SCK/2

—

1/f_DSPI+ 5

—

t_SDC

CC D SCK duty cycle

SR D

—

t_SCK/2

—

t_SCK/2

—

t_SCK/2

—

t_A

t_DI

SR D Slave access time

—

1/f_DSPI+ 70

—

1/f_DSPI+ 130

SR D Slave SOUT disable time Slave mode

SR D Data setup time for inputs Master mode

Slave mode

—

t_SUI

—

145

—

t_HI

SR D Data hold time for inputs

Master mode

Slave mode

—

2⁶

—

2⁶

—

Table 42. DSPI characteristics (continued)

DSPI0/DSPI1

DSPI2

Typ

No.

Symbol

Parameter

Unit

Min

Typ

Max

Min

Max

t_SUO

CC D Data valid after SCK edge Master mode

Slave mode

—

160

—

t_HO

CC D Data hold time for outputs Master mode

Slave mode

—

Operating conditions: Cout = 10 to 50 pF, Slew_IN= 3.5 to 15 ns.

Maximum value is reached when CSn pad is configured as SLOW pad while SCK pad is configured as MEDIUM. A positive value means that SCK

starts before CSn is asserted. DSPI2 has only SLOW SCK available.

Maximum value is reached when CSn pad is configured as MEDIUM pad while SCK pad is configured as SLOW. A positive value means that CSn is

deasserted before SCK. DSPI0 and DSPI1 have only MEDIUM SCK available.

The t_CSCdelay value is configurable through a register. When configuring t_CSC(using PCSSCK and CSSCK fields in DSPI_CTARx registers), delay

between internal CS and internal SCK must be higher than t_CSCto ensure positive t_CSCext

The t_ASCdelay value is configurable through a register. When configuring t_ASC(using PASC and ASC fields in DSPI_CTARx registers), delay between

internal CS and internal SCK must be higher than t_ASCto ensure positive t_ASCext

This delay value corresponds to SMPL_PT = 00b which is bit field 9 and 8 of DSPI_MCR register.

SCK and SOUT configured as MEDIUM pad

Electrical characteristics

Figure 22. DSPI classic SPI timing – master, CPHA = 0

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

Last Data

SIN

First Data

Data

Last Data

SOUT

Note: Numbers shown reference Table 42

Figure 23. DSPI classic SPI timing – master, CPHA = 1

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

Data

First Data

Last Data

SIN

SOUT

Last Data

First Data

Note: Numbers shown reference Table 42

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Figure 24. DSPI classic SPI timing – slave, CPHA = 0

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

Data

First Data

Last Data

SOUT

SIN

Data

Last Data

First Data

Note: Numbers shown reference Table 42.

Figure 25. DSPI classic SPI timing – slave, CPHA = 1

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

Last Data

Data

SOUT

SIN

First Data

Last Data

First Data

Note: Numbers shown reference Table 42

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Figure 26. DSPI modified transfer format timing – master, CPHA = 0

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

SIN

First Data

Last Data

Data

SOUT

First Data

Data

Note: Numbers shown reference Table 42.

Figure 27. DSPI modified transfer format timing – master, CPHA = 1

PCSx

SCK Output

(CPOL = 0)

SCK Output

(CPOL = 1)

SIN

Last Data

First Data

Data

First Data

Last Data

SOUT

Note: Numbers shown reference Table 42

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

Figure 28. DSPI modified transfer format timing – slave, CPHA = 0

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

First Data

Data

Last Data

SOUT

SIN

Last Data

First Data

Note: Numbers shown reference Table 42

Figure 29. DSPI modified transfer format timing – slave, CPHA = 1

SCK Input

(CPOL = 0)

SCK Input

(CPOL = 1)

Last Data

First Data

Data

SOUT

SIN

First Data

Last Data

Note: Numbers shown reference Table 42

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.19.3 Nexus characteristics

Table 43. Nexus characteristics

Value

Typ

No.

Symbol

Parameter

Unit

Max

Min

t_TCYC

t_MCYC

t_MDOV

t_MSEOVCC D MCKO low to MSEO_b data valid

CC D TCK cycle time

—

CC D MCKO cycle time

CC D MCKO low to MDO data valid

t_EVTOV

t_NTDIS

CC D MCKO low to EVTO data valid

CC D TDI data setup time

—

t_NTMSSCC D TMS data setup time

t_NTDIHCC D TDI data hold time

t_NTMSHCC D TMS data hold time

t_TDOV

t_TDOI

CC D TCK low to TDO data valid

CC D TCK low to TDO data invalid

Figure 30. Nexus TDI, TMS, TDO timing

TCK

TMS, TDI

TDO

Note: Numbers shown reference Table 43

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Electrical characteristics

4.19.4 JTAG characteristics

Table 44. JTAG characteristics

Value

Typ

No.

Symbol

Parameter

Unit

Min

Max

t_JCYC

t_TDIS

CC D TCK cycle time

CC D TDI setup time

CC D TDI hold time

—

t_TDIH

t_TMSS

t_TMSH

t_TDOV

t_TDOI

CC D TMS setup time

CC D TMS hold time

CC D TCK low to TDO valid

CC D TCK low to TDO invalid

—

Figure 31. Timing diagram – JTAG boundary scan

TCK

2/4

3/5

INPUT DATA VALID

DATA INPUTS

DATA OUTPUTS

OUTPUT DATA VALID

Note: Numbers shown reference Table 44

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Package characteristics

Package mechanical data

64 LQFP

5.1

5.1.1

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Package characteristics

Figure 32. 64 LQFP package mechanical drawing (1 of 3)

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Package characteristics

Figure 33. 64 LQFP package mechanical drawing (2 of 3)

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Package characteristics

Figure 34. 64 LQFP package mechanical drawing (3 of 3)

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Package characteristics

5.1.2

100 LQFP

Figure 35. 100 LQFP package mechanical drawing (1 of 3)

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Package characteristics

Figure 36. 100 LQFP package mechanical drawing (2 of 3)

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Package characteristics

Figure 37. 100 LQFP package mechanical drawing (3 of 3)

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Package characteristics

5.1.3

144 LQFP

Figure 38. 144 LQFP package mechanical drawing (1 of 2)

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Package characteristics

Figure 39. 144 LQFP package mechanical drawing (2 of 2)

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Package characteristics

5.1.4

208 MAPBGA

Figure 40. 208 MAPBGA package mechanical drawing (1 of 2)

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Package characteristics

Figure 41. 208 MAPBGA package mechanical drawing (2 of 2)

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

Ordering information

Figure 42. Commercial product code structure

Example code:

Qualification Status

PowerPC Core

Automotive Platform

Core Version

Flash Size (core dependent)

Product

Fab and Mask Indicator

Temperature spec.

Package Code

Frequency

R = Tape & Reel (blank if Tray)

Qualification Status

Flash Size (z0 core)

2 = 256 KB

3 = 384 KB

Temperature spec.

C = -40 to 85 °C

V = -40 to 105 °C

M = -40 to 125 °C

M = MC status

S = Auto qualified

P = PC status

4 = 512 KB

Automotive Platform

56 = PPC in 90nm

Product

B = Body

Package Code

LH = 64 LQFP

C = Gateway

LL = 100 LQFP

LQ = 144 LQFP

MG = 208 MAPBGA

Core Version

0 = e200z0

Fab and Mask Indicator

F = ATMC

1 = Maskset Revision

Frequency

4 = Up to 48 MHz

6 = Up to 64 MHz

208 MAPBGA available only as development package for Nexus2+

Document revision history

Table 45 summarizes revisions to this document.

Table 45. Revision history

Revision

Date

Description of Changes

04-Apr-2008 Initial release.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

100

Freescale Semiconductor

Document revision history

Table 45. Revision history (continued)

Description of Changes

Revision

Date

06-Mar-2009 Made minor editing and formatting changes to improve readability

Harmonized oscillator naming throughout document

Features:

—Replaced 32 KB with 48 KB as max SRAM size

—Updated descripiton of INTC

—Changed max number of GPIO pins from 121 to 123

Updated Section 1.2, Description

Updated Table 2

Added Section 2, Block diagram

Section 3, Package pinouts and signal descriptions: Removed signal descriptions (these

are found in the device reference manual)

Updated Figure 5:

—Replaced VPP with VSS_HV on pin 18

—Added MA[1] as AF3 for PC[10] (pin 28)

—Added MA[0] as AF2 for PC[3] (pin 116)

—Changed description for pin 120 to PH[10] / GPIO[122] / TMS

—Changed description for pin 127 to PH[9] / GPIO[121] / TCK

—Replaced NMI[0] with NMI on pin 11

Updated Figure 4:

—Replaced VPP with VSS_HV on pin 14

—Added MA[1] as AF3 for PC[10] (pin 22)

—Added MA[0] as AF2 for PC[3] (pin 77)

—Changed description for pin 81 to PH[10] / GPIO[122] / TMS

—Changed description for pin 88 to PH[9] / GPIO[121] / TCK

—Removed E1UC[19] from pin 76

—Replaced [11] with WKUP[11] for PB[3] (pin 1)

—Replaced NMI[0] with NMI on pin 7

Updated Figure 6:

—Changed description for ball B8 from TCK to PH[9]

—Changed description for ball B9 from TMS to PH[10]

—Updated descriptions for balls R9 and T9

Added Section 4.2, Parameter classification and tagged parameters in tables where

appropriate

Added Section 4.3, NVUSRO register

Updated Table 5

Section 4.5, Recommended operating conditions: Added note on RAM data retention to

end of section

Updated Table 6 and Table 7

Added Section 4.6.1, Package thermal characteristics

Updated Section 4.6.2, Power considerations

Updated Figure 7

Updated Table 9, Table 10, Table 11, Table 12 and Table 13

Added Section 4.7.4, Output pin transition times

Updated Table 16

Updated Figure 8

Updated Table 18

Section 4.9.1, Voltage regulator electrical characteristics: Amended description of

LV_PLL

Figure 10: Exchanged position of symbols C_DEC1and C_DEC2

Updated Table 19

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

101

Document revision history

Table 45. Revision history (continued)

Description of Changes

Revision

Date

06-Mar-2009 Added Figure 11

Updated Table 20 and Table 21

Updated Section 4.11, Flash memory electrical characteristics

Added Section 4.12, Electromagnetic compatibility (EMC) characteristics

Updated Section 4.13, Fast external crystal oscillator (4 to 16 MHz) electrical

characteristics

Updated Section 4.14, Slow external crystal oscillator (32 kHz) electrical characteristics

Updated Table 34, Table 35 and Table 36

Added Section 4.19, On-chip peripherals

Added Table 37

Updated Table 38

Updated Table 47

Added Section Appendix A, Abbreviations

06-Aug-2009 Updated Figure 6

Table 5

• V_{DD_ADC}: changed min value for “relative to V_DD“ condition

• V_IN: changed min value for “relative to V_DD“ condition

• I_CORELV: added new row

Table 7

• T_{A C-Grade Part,}T_{J C-Grade Part,}T_{A V-Grade Part,}T_{J V-Grade Part,}T_{A M-Grade Part,}T_{J M-Grade Part}

added new rows

• Changed capacitance value in footnote

Table 14

• MEDIUM configuration: added condition for PAD3V5V = 0

Updated Figure 10

Table 19

• C_DEC1: changed min value

• I_MREG:changed max value

• I_{DD_BV}: added max value footnote

Table 20

• V_LVDHV3H: changed max value

• V_LVDHV3L: added max value

• V_LVDHV5H: changed max value

• V_LVDHV5L: added max value

Updated Table 21

Table 23

• Retention: deleted min value footnote for “Blocks with 100,000 P/E cycles“

Table 31

• I_FXOSC: added typ value

Table 33

• V_SXOSC: changed typ value

• T_SXOSCSU: added max value footnote

Table 34

• t_LTJIT: added max value

Updated Figure 36

MPC5604B/C Microcontroller Data Sheet, Rev. 8

102

Freescale Semiconductor

Document revision history

Table 45. Revision history (continued)

Description of Changes

Revision

Date

02-Nov-2009 In the “MPC5604B/C series block summary“ table, added a new row.

In the “Absolute maximum ratings” table, changed max value of V_{DD_BV}, V_{DD_ADC}, and

V_IN.

In the ”Recommended operating conditions (3.3 V)” table, deleted min value of TV_DD

In the “Reset electrical characteristics“ table, changed footnotes 3 and 5.

In the “Voltage regulator electrical characteristics“ table:

• C_REGn: changed max value.

• C_DEC1: split into 2 rows.

• Updated voltage values in footnote 4

In the “Low voltage monitor electrical characteristics“ table:

• Updated column Conditions.

• V_LVDLVCORL, V_LVDLVBKPL: changed min/max value.

In the “Program and erase specifications“ table, added initial max valueof T_dwprogram

In the “Flash module life“ table, changed min value for blocks with 100K P/E cycles

In the “Flash power supply DC electrical characteristics“ table:

• IFREAD, IFMOD: added typ value.

• Added footnote 1.

Added “ NVUSRO[WATCHDOG_EN] field description“ section.

Section 4.18: “ADC electrical characteristics“ has been moved up in hierarchy (it was

Section 4.18.5).

In the “ ADC conversion characteristics“ table, changed initial max value of R_AD

In the “On-chip peripherals current consumption“ table:

• Removed min/max from the heading.

• Changed unit of measurement and consequently rounded the values.

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

103

Document revision history

Table 45. Revision history (continued)

Description of Changes

Revision

Date

15-Mar-2010 In the “Introduction” section, relocated a note.

In the “MPC5604B/C device comparison“ table, added footnote regarding SCI and CAN.

In the “Absolute maximum ratings“ table, removed the min value of V_INrelative tio V_DD

In the ”Recommended operating conditions (3.3 V)” table:

• T_{A C-Grade Part,}T_{J C-Grade Part,}T_{A V-Grade Part,}T_{J V-Grade Part,}T_{A M-Grade Part,}T_{J M-Grade Part}

added new rows.

• TV_DD: made single row.

In the “LQFP thermal characteristics” table, added more rows.

Removed “208 MAPBGA thermal characteristics” table.

In the “I/O consuption“ table:

• Removed I_DYNSEGrow.

• Added “I/O weight “ table.

In the “Voltage regulator electrical characteristics“ table:

• Updated the values.

• Removed I_VREGREFand I_VREDLVD12

• Added a note about I_{DD_BC}

In the “Low voltage monitor electrical characteristics“ table:

• Updated V_PORHvalues.

• Updated V_LVDLVCORLvalue.

Entirely updated the “Low voltage power domain electrical characteristics“ table.

In the “Program and erase specifications“ table, inserted T_eslatrow.

Entirely updated the “Flash power supply DC electrical characteristics“ table.

Entirely updated the “Start-up time/Switch-off time“ table.

In the “Crystal oscillator and resonator connection scheme“ figure, relocated a note.

In the ”Slow external crystal oscillator (32 kHz) electrical characteristics” table:

• Removed g_mSXOSCrow.

• Inserted values of I_SXOSCBIAS

Entirely updated the “Fast internal RC oscillator (16 MHz) electrical characteristics“ table.

In the “ADC conversion characteristics” table: updated the description of the conditions of

t_{ADC_PU}and t_{ADC_S.}

Entirely updated the “DSPI characteristics“ table.

In the “Orderable part number summary” table, modified some orderable part number.

Updated the “Commercial product code structure” figure.

Removed the note about the condition from “Flash read access timing“ table

Removed the notes that assert the values need to be confirmed before validation

Exchanged the order of “LQFP 100-pin configuration” and “LQFP 144-pin configuration”

Exchanged the order of “LQFP 100-pin package mechanical drawing” and “LQFP 144-pin

package mechanical drawing”

MPC5604B/C Microcontroller Data Sheet, Rev. 8

104

Freescale Semiconductor

Document revision history

Table 45. Revision history (continued)

Description of Changes

Revision

Date

05-Jul-2010 Added 64 LQFP package information

Updated the “Features“ section.

Figures “LQFP 100-pin configuration” and “LQFP 100-pin configuration”: removed

alternate function information

Added “Functional port pin descriptions” table

Added eDMA block in the “MPC5604B/C series block diagram” figure

Deleted the “NVUSRO[WATCHDOG_EN] field description“ section

In the ”Recommended operating conditions (3.3 V)” and ”Recommended operating

conditions (5.0 V)” tables, deleted the conditions of T_{A C-Grade Part,}T_{A V-Grade Part,}T_{A M-Grade}

Part

In the “LQFP thermal characteristics” table, rounded the values.

In the “RESET electrical characteristics” section, replaced “nRSTIN” with “RESET”.

In the “I/O input DC electrical characteristics” table:

• W_FI: insered a footnote

• W_NFI: insered a footnote

In the “Low voltage monitor electrical characteristics“ table:

• changed min valueV_LVDHV3L, from 2.7 to 2.6

• Inserted max value of V_LVDLVCORL

In the ”FMPLL electrical characteristics” table, rounded the values of f_VCO.

In the “DSPI characteristics” table:

• Added t_ASCrow

• Update values of t_A

In the “ADC conversion characteristics” table, added “I_ADCPWD” and “I_ADCRUN” rows

Removed “Orderable part number summary” table.

25-Nov-2010 Editorial changes and improvements.

In the “MPC5604B/C device comparison“ table, changed the temperature value from 105

to 125 °C, in the footnote regarding “Execution speed”.

In the ”Recommended operating conditions (3.3 V)” and ”Recommended operating

conditions (5.0 V)” tables, restored the conditions of T_{A C-Grade Part,}T_{A V-Grade Part,}T_A

M-Grade Part

In the “LQFP thermal characteristics” table, added values concerning 64 LQFP package.

In the “MEDIUM configuration output buffer electrical characteristics” table: fixed a typo in

last row of conditions column, there was I_OHthat now is I_OL

In the “Reset electrical characteristics” table, changed the parameter classification tag for

V_OLand |I_WPU|.

In the “Low voltage monitor electrical characteristics“ table, changed the max value of

V_LVDLVCORLfrom 1.5V to 1.15V.

In the “Program and erase specifications“ table, replaced “T_eslat” with “T_esus”.

In the “FMPLL electrical characteristics” table, changed the parameter classification tag

for f_VCO

MPC5604B/C Microcontroller Data Sheet, Rev. 8

Freescale Semiconductor

105

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MPC5604BC

Rev. 8

11/2010

MPC5602CF1CLH6R [NXP]

相关型号：

MPC5602CF1CLL6R

MPC5602CF1MLH4

MPC5602CF1MLH4R

MPC5602CF1MLH6

MPC5602CF1MLH6R

MPC5602CF1MLL6R

MPC5602CF1VLH4R

MPC5602CF1VLH6

MPC5602CF1VLH6R

MPC5602CF1VLL4

MPC5602CF1VLL6

MPC5602CF1VLL6R