MPC7410RX400LD_技术文档

MPC7410EC

Rev. 6.1, 11/2007

Freescale Semiconductor

Technical Data

MPC7410 RISC Microprocessor

Hardware Specifications

Contents

The MPC7410 is a PowerPC™ reduced instruction set computing

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

(RISC) microprocessor. This document describes pertinent

electrical and physical characteristics of the MPC7410. For

functional characteristics of the processor, refer to the MPC7410

RISC Microprocessor User’s Manual.

2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

3. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

4. Electrical and Thermal Characteristics . . . . . . . . . . . . 7

5. Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

6. Pinout Listings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

7. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 29

8. System Design Information . . . . . . . . . . . . . . . . . . . 34

9. Document Revision History . . . . . . . . . . . . . . . . . . . 48

10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 53

To locate any published errata or updates for this document, refer

to the web site at http://www.freescale.com.

1 Overview

The MPC7410 is the second implementation of the fourth

generation (G4) microprocessors from Freescale. The MPC7410

implements the full PowerPC 32-bit architecture and is targeted at

both computing and embedded systems applications.

Some comments on the MPC7410 with respect to the MPC750:

•

The MPC7410 adds an implementation of the new

AltiVec™ technology instruction set.

•

The MPC7410 includes significant improvements in

memory subsystem (MSS) bandwidth and offers an

optional, high-bandwidth MPX bus interface.

•

The MPC7410 adds full hardware-based multiprocessing

capability, including a five-state cache coherency protocol

(four MESI states plus a fifth state for shared

intervention).

Features

•

The MPC7410 is implemented in a next generation process technology for core frequency improvement.

The MPC7410 floating-point unit has been improved to make latency equal for double- and single-precision

operations involving multiplication.

•

The completion queue has been extended to eight slots.

There are no other significant changes to scalar pipelines, decode/dispatch/completion mechanisms, or the

branch unit. The MPC750 four-stage pipeline model is unchanged (fetch, decode/dispatch, execute,

complete/writeback).

Some comments on the MPC7410 with respect to the MPC7400:

•

The MPC7410 adds configurable direct-mapped SRAM capability to the L2 cache interface.

The MPC7410 adds 32-bit interface support to the L2 cache interface. The MPC7410 implements a 19th L2

address pin (L2ASPARE on the MPC7400) in order to support additional address range.

•

The MPC7410 removes support for 3.3-V I/O on the L2 cache interface.

Figure 1 shows a block diagram of the MPC7410.

2 Features

This section summarizes features of the MPC7410 implementation of the PowerPC architecture. Major features of

the MPC7410 are as follows:

•

Branch processing unit

— Four instructions fetched per clock

— One branch processed per cycle (plus resolving two speculations)

— Up to one speculative stream in execution, one additional speculative stream in fetch

— 512-entry branch history table (BHT) for dynamic prediction

— 64-entry, four-way set-associative branch target instruction cache (BTIC) for eliminating branch delay

slots

•

Dispatch unit

— Full hardware detection of dependencies (resolved in the execution units)

— Dispatch two instructions to eight independent units (system, branch, load/store, fixed-point unit 1,

fixed-point unit 2, floating-point, AltiVec permute, AltiVec ALU)

— Serialization control (predispatch, postdispatch, execution serialization)

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

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Features

Figure 1. MPC7410 Block Diagram

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

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3

Features

•

Decode

— Register file access

— Forwarding control

— Partial instruction decode

•

Completion

— Eight-entry completion buffer

— Instruction tracking and peak completion of two instructions per cycle

— Completion of instructions in program order while supporting out-of-order instruction execution,

completion serialization, and all instruction flow changes

Fixed point units (FXUs) that share 32 GPRs for integer operands

— Fixed point unit 1 (FXU1)—multiply, divide, shift, rotate, arithmetic, logical

— Fixed point unit 2 (FXU2)—shift, rotate, arithmetic, logical

— Single-cycle arithmetic, shifts, rotates, logical

— Multiply and divide support (multi-cycle)

— Early out multiply

•

Three-stage floating-point unit and a 32-entry FPR file

— Support for IEEE Std 754™ single- and double-precision floating-point arithmetic

— Three-cycle latency, one-cycle throughput (single- or double-precision)

— Hardware support for divide

— Hardware support for denormalized numbers

— Time deterministic non-IEEE mode

•

System unit

— Executes CR logical instructions and miscellaneous system instructions

— Special register transfer instructions

AltiVec unit

— Full 128-bit data paths

— Two dispatchable units: vector permute unit and vector ALU unit.

— Contains its own 32-entry, 128-bit vector register file (VRF) with 6 renames

— The vector ALU unit is further subdivided into the vector simple integer unit (VSIU), the vector

complex integer unit (VCIU), and the vector floating-point unit (VFPU).

— Fully pipelined

•

Load/store unit

— One-cycle load or store cache access (byte, half word, word, double word)

— Two-cycle load latency with 1-cycle throughput

— Effective address generation

— Hits under misses (multiple outstanding misses)

— Single-cycle unaligned access within double-word boundary

— Alignment, zero padding, sign extend for integer register file

— Floating-point internal format conversion (alignment, normalization)

— Sequencing for load/store multiples and string operations

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

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Features

— Store gathering

— Executes the cache and TLB instructions

— Big- and little-endian byte addressing supported

— Misaligned little-endian supported

— Supports FXU, FPU, and AltiVec load/store traffic

— Complete support for all four architecture AltiVec DST streams

Level 1 (L1) cache structure

•

— 32 Kbyte, 32-byte line, eight-way set-associative instruction cache (iL1)

— 32 Kbyte, 32-byte line, eight-way set-associative data cache (dL1)

— Single-cycle cache access

— Pseudo least-recently-used (LRU) replacement

— Data cache supports AltiVec LRU and transient instructions algorithm

— Copy-back or write-through data cache (on a page-per-page basis)

— Supports all PowerPC memory coherency modes

— Nonblocking instruction and data cache

— Separate copy of data cache tags for efficient snooping

— No snooping of instruction cache except for ICBI instruction

Level 2 (L2) cache interface

•

— Internal L2 cache controller and tags; external data SRAMs

— 512-Kbyte, 1-Mbyte, and 2-Mbyte two-way set-associative L2 cache support

— Copy-back or write-through data cache (on a page basis, or for all L2)

— 32-byte (512-Kbyte), 64-byte (1-Mbyte), or 128-byte (2-Mbyte) sectored line size

— Supports pipelined (register-register) synchronous BurstRAMs and pipelined (register-register) late

write synchronous BurstRAMs

— Supports direct-mapped mode for 256 Kbytes, 512 Kbytes, 1 Mbyte, or 2 Mbytes of SRAM (either all,

half, or none of L2 SRAM must be configured as direct-mapped)

— Core-to-L2 frequency divisors of ÷1, ÷1.5, ÷2, ÷2.5, ÷3, ÷3.5, and ÷4 supported

— 64-bit data bus which also supports 32-bit bus mode

— Selectable interface voltages of 1.8 and 2.5 V

Memory management unit

•

— 128-entry, two-way set-associative instruction TLB

— 128-entry, two-way set-associative data TLB

— Hardware reload for TLBs

— Four instruction BATs and four data BATs

52

— Virtual memory support for up to 4 hexabytes (2 ) of virtual memory

32

— Real memory support for up to 4 gigabytes (2 ) of physical memory

— Snooped and invalidated for TLBI instructions

•

Efficient data flow

— All data buses between VRF, load/store unit, dL1, iL1, L2, and the bus are 128 bits wide

— dL1 is fully pipelined to provide 128 bits/cycle to/from the VRF

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

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5

Features

— L2 is fully pipelined to provide 128 bits per L2 clock cycle to the L1s.

— Up to eight outstanding, out-of-order, cache misses between dL1 and L2/bus

— Up to seven outstanding, out-of-order transactions on the bus

— Load folding to fold new dL1 misses into older, outstanding load and store misses to the same line

— Store miss merging for multiple store misses to the same line. Only coherency action taken (that is,

address only) for store misses merged to all 32 bytes of a cache line (no data tenure needed).

— Two-entry finished store queue and four-entry completed store queue between load/store unit and dL1

— Separate additional queues for efficient buffering of outbound data (castouts, write throughs, and so on)

from dL1 and L2

•

Bus interface

— MPX bus extension to 60x processor interface

— Mode-compatible with 60x processor interface

— 32-bit address bus

— 64-bit data bus

— Bus-to-core frequency multipliers of 2x, 2.5x, 3x, 3.5x, 4x, 4.5x, 5x, 5.5x, 6x, 6.5x, 7x, 7.5x, 8x, 9x

supported

— Selectable interface voltages of 1.8, 2.5, and 3.3 V

Power management

•

— Low-power design with thermal requirements very similar to MPC740 and MPC750

— Low-voltage processor core

— Selectable interface voltages can reduce power in output buffers

— Three static power saving modes: doze, nap, and sleep

— Dynamic power management

•

Testability

— LSSD scan design

— IEEE Std 1149.1™ JTAG interface

— Array built-in self test (ABIST)—factory test only

— Redundancy on L1 data arrays and L2 tag arrays

Reliability and serviceability

— Parity checking on 60x and L2 cache buses

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

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General Parameters

3 General Parameters

The following list provides a summary of the general parameters of the MPC7410:

Technology

Die size

0.18 µm CMOS, six-layer metal

2

6.32 mm × 8.26 mm (52 mm )

Transistor count

Logic design

Packages

10.5 million

Fully static

Surface mount 360 ceramic ball grid array (CBGA)

Surface mount 360 high coefficient of thermal expansion ceramic ball grid array

(HCTE_CBGA)

Surface mount 360 high coefficient of thermal expansion ceramic ball grid array with

lead free C5 spheres (HCTE_CBGA Lead Free C5 Spheres)

Surface mount 360 high coefficient of thermal expansion ceramic land grid array

(HCTE_LGA)

Core power supply 1.8 V ± 100 mV DC (nominal; see Table 3 for recommended operating conditions)

I/O power supply 1.8 V ± 100 mV DC or

2.5 V ± 100 mV

3.3 V ± 165 mV (system bus only)

(input thresholds are configuration pin selectable)

4 Electrical and Thermal Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the MPC7410.

4.1 DC Electrical Characteristics

The tables in this section describe the MPC7410 DC electrical characteristics. Table 1 provides the absolute

maximum ratings.

1

Table 1. Absolute Maximum Ratings

Characteristic

Symbol

Maximum Value

Unit

Notes

Core supply voltage

PLL supply voltage

V

–0.3 to 2.1

–0.3 to 3.6

–0.3 to 2.8

V

4

DD

AV

DD

L2 DLL supply voltage

Processor bus supply voltage

L2 bus supply voltage

Input voltage

L2AV

V

4

DD

OV

V

3, 6

3

DD

L2OV

V

DD

Processor bus

L2 bus

V

–0.3 to OV + 0.2 V

V

2, 5

—

in

DD

–0.3 to L2OV + 0.2 V

V

DD

JTAG signals

–0.3 to OV + 0.2 V

V

DD

Storage temperature range

T

–55 to 150

°C

stg

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

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7

Electrical and Thermal Characteristics

Table 1. Absolute Maximum Ratings (continued)

Characteristic Symbol Maximum Value

260

1

Unit

Notes

Rework temperature

T

°C

—

rwk

Notes:

1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only,

and functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device

reliability or cause permanent damage to the device.

2. Caution: V must not exceed OV or L2OV by more than 0.2 V at any time including during power-on reset.

in

DD

3. Caution: L2OV /OV must not exceed V /AV /L2AV by more than 2.0 V at any time including during

DD

power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down

sequences.

4. Caution: V /AV /L2AV must not exceed L2OV /OV by more than 0.4 V at any time including during

DD

power-on reset; this limit may be exceeded for a maximum of 20 ms during power-on reset and power-down

sequences.

5. V may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.

in

6. Mxx7410xxnnnLE (Rev. 1.4) and later only. Previous revisions do not support 3.3 V OV and have a maximum

DD

value OV of –0.3 to 2.8 V.

DD

Figure 2 shows the allowable undershoot and overshoot voltage for the MPC7410.

(L2)OV

+ 20%

+ 5%

DD

(L2)OV

DD

(L2)OV

DD

V

IH

V

IL

GND

GND – 0.3 V

GND – 0.7 V

Not to Exceed 10%

of t (OV

)

DD

SYSCLK

or t

(L2OV

)

DD

L2CLK

Figure 2. Overshoot/Undershoot Voltage

The MPC7410 provides several I/O voltages to support both compatibility with existing systems and migration to

future systems. The MPC7410 core voltage must always be provided at nominal voltage (see Table 3 for actual

recommended core voltage). Voltage to the L2 I/Os and processor interface I/Os are provided through separate sets

of supply pins and may be provided at the voltages shown in Table 2. Voltage must be provided to the L2OV

DD

power pins even if the interface is not used. The input voltage threshold for each bus is selected by sampling the

state of the voltage select pins BVSEL and L2VSEL at the negation of the signal HRESET. These signals must

remain stable during part operation and cannot change. The output voltage will swing from GND to the maximum

voltage applied to the OV or L2OV power pins.

DD

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

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Electrical and Thermal Characteristics

Table 2. Input Threshold Voltage Setting

Processor Bus Input

Threshold is Relative to:

L2 Bus Input Threshold is

Relative to:

3

BVSEL Signal

L2VSEL Signal

Notes

0

1.8 V

2.5 V

3.3 V

0

1.8 V

2.5 V

1

1, 2

1, 4, 5

6

HRESET

1

HRESET

1

2.5 V

¬HRESET

Not Supported

Notes:

1. Caution: The input threshold selection must agree with the OV /L2OV voltages supplied.

DD

2. To select the 2.5-V threshold option, BVSEL and/or L2VSEL should be tied to HRESET so that the two signals

change state together. This is the preferred method for selecting this mode of operation.

3. To overcome the internal pull-up resistance, a pull-down resistance less than 250 Ω should be used.

4. Default voltage setting if left unconnected (internal pulled-up). MPC7410RXnnnLE (Rev 1.4) and later only.

Previous revisions do not support 3.3 V OV ; the default voltage setting if left unconnected is 2.5 V.

DD

5. Mxx7410xxnnnLE (Rev. 1.4) and later only. Previous revisions do not support 3.3 V OV ; having BVSEL = 1 selects

DD

the 2.5-V threshold.

6. Mxx7410xxnnnLE (Rev. 1.4) and later only. Previous revisions do not support BVSEL = ¬HRESET. (¬HRESET is

the inverse of HRESET.)

Table 3 provides the recommended operating conditions for the MPC7410.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

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9

Electrical and Thermal Characteristics

Characteristic

1

Table 3. Recommended Operating Conditions

Recommended

Value

Symbol

Unit

Notes

Core supply voltage

PLL supply voltage

L2 DLL supply voltage

V

1.8 V 100 mV

2.5 V 100 mV

3.3 V 165 mV

V

—

DD

AV

DD

L2AV

—

DD

Processor bus supply

voltage

BVSEL = 0

OV

—

DD

BVSEL = HRESET

—

DD

BVSEL = ¬HRESET or

BVSEL = 1

2, 3

L2 bus supply voltage

Input voltage

L2VSEL = 0

L2OV

1.8 V 100 mV

2.5 V 100 mV

V

—

DD

L2VSEL = HRESET or

L2VSEL = 1

Processor bus and

JTAG signals

V

GND to OV

V

—

in

DD

L2 bus

V

GND to L2OV

0 to 105

V

—

in

DD

Die-junction temperature

T

°C

j

Notes:

1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions

is not guaranteed.

2. Mxx7410xxnnnLE (Rev. 1.4) and later only. Previous revisions do not support 3.3 V OV and have a

DD

recommended OV value of 2.5 V 100 mV for BVSEL = 1.

DD

3. Mxx7410xxnnnLE (Rev. 1.4) and later only. Previous revisions do not support BVSEL = ¬HRESET.

Table 4 provides the package thermal characteristics for the MPC7410.

Table 4. Package Thermal Characteristics

Value

Characteristic

Symbol

Unit

Notes

MPC7410 MPC7410

CBGA

HCTE

Junction-to-ambient thermal resistance, natural convection,

four-layer (2s2p) board

R

18

20

°C/W

1, 2

3

JMA

θ

Junction-to-ambient thermal resistance, 1m/sec airflow,

four-layer (2s2p) board

14

13

9

16

15

11

Junction-to-ambient thermal resistance, 2m/sec airflow,

four-layer (2s2p) board

Junction-to-board thermal resistance

R

JB

θ

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

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Electrical and Thermal Characteristics

Table 4. Package Thermal Characteristics (continued)

Value

Characteristic

Symbol

Unit

Notes

MPC7410 MPC7410

CBGA

HCTE

Junction-to-case thermal resistance

R

< 0.1

°C/W

4

JC

θ

Notes:

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site

(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board

thermal resistance.

2. Per JEDEC JESD51-6 with the board horizontal.

3. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is

measured on the top surface of the board near the package.

4. Thermal resistance between the active portion of the die and the calculated case temperature at the top of the die.

The actual value of R JC is less than 0.1 °C/W.

Note: Refer to Section 8.8, “Thermal Management Information,” for details on thermal management.

Table 5 provides the DC electrical characteristics for the MPC7410.

Table 5. DC Electrical Specifications

At recommended operating conditions (see Table 3)

Nominal

Characteristic

Bus

Voltage

Symbol

Min

Max

Unit

Notes

1

Input high voltage (all inputs except

SYSCLK)

1.8

2.5

3.3

1.8

2.5

3.3

1.8

2.5

3.3

1.8

2.5

3.3

1.8

2.5

3.3

V

0.65 × (L2)OV

(L2)OV + 0.2

V

2, 3, 8

IH

DD

V

1.7

2.0

(L2)OV + 0.2

DD

IH

OV + 0.3

DD

Input low voltage (all inputs except

SYSCLK)

V

–0.3

1.5

0.35 × (L2)OV

0.2 × (L2)OV

V

8

2, 8

8

IL

DD

0.8

OV + 0.2

SYSCLK input high voltage

SYSCLK input low voltage

Input leakage current,

CV

IH

DD

2.0

OV + 0.2

DD

2.4

OV + 0.3

DD

CV

–0.3

—

0.2

0.4

20

V

IL

I

µA

2, 3,

6, 7

in

V

= L2OV /OV

in

DD DD

—

35

in

—

70

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

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11

Electrical and Thermal Characteristics

Table 5. DC Electrical Specifications (continued)

At recommended operating conditions (see Table 3)

Nominal

Characteristic

Bus

Voltage

Symbol

Min

Max

Unit

Notes

1

High-Z (off-state) leakage current,

1.8

2.5

3.3

1.8

2.5

3.3

1.8

2.5

3.3

I

—

20

35

µA

2, 3,

5, 7

TSI

V

= L2OV /OV

in

DD DD

70

Output high voltage, I

= –5 mA

V

(L2)OV – 0.45

—

V

8

OH

DD

V

1.7

2.4

—

OH

V

—

OH

Output low voltage, I = 5 mA

V

0.45

0.4

6.0

OL

—

Capacitance, V = 0 V, f = 1 MHz

C

—

pF

3, 4, 7

in

Notes:

1. Nominal voltages; see Table 3 for recommended operating conditions.

2. For processor bus signals, the reference is OV while L2OV is the reference for the L2 bus signals.

DD

3. Excludes factory test signals.

4. Capacitance is periodically sampled rather than 100% tested.

5. The leakage is measured for nominal OV and L2OV , or both OV and L2OV must vary in the same

DD

direction (for example, both OV and L2OV vary by either +5% or –5%).

DD

6. Measured at max OV /L2OV

.

DD

7. Excludes IEEE 1149.1 boundary scan (JTAG) signals.

8. For JTAG support: all signals controlled by BVSEL and L2VSEL will see V /V /V /V /CV /CV DC limits of

IL IH OL OH

IH

IL

1.8 V mode while either the EXTEST or CLAMP instruction is loaded into the IEEE 1149.1 instruction register by

the UpdateIR TAP state until a different instruction is loaded into the instruction register by either another UpdateIR

or a Test-Logic-Reset TAP state. If only TSRT is asserted to the part, and then a SAMPLE instruction is executed,

there is no way to control or predict what the DC voltage limits are. If HRESET is asserted before executing a

SAMPLE instruction, the DC voltage limits will be controlled by the BVSEL/L2VSEL settings during HRESET.

Anytime HRESET is not asserted (that is, just asserting TRST), the voltage mode is not known until either EXTEST

or CLAMP is executed, at which time the voltage level will be at the DC limits of 1.8 V.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

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Electrical and Thermal Characteristics

Table 6 provides the power consumption for the MPC7410.

Table 6. Power Consumption for MPC7410

Processor (CPU) Frequency

450 MHz

Unit

Notes

400 MHz

500 MHz

Full-On Mode

4.7

Typical

4.2

9.5

5.3

W

1, 3

1, 2

Maximum

10.7

11.9

Doze Mode

Nap Mode

Maximum

4.3

1.35

1.3

4.8

5.3

1.65

1.6

W

1

1.5

Sleep Mode

1.45

Sleep Mode—PLL and DLL Disabled

Typical

600

1.1

600

1.1

600

1.1

mW

W

1

Maximum

Notes:

1. These values apply for all valid processor bus and L2 bus ratios. The values do not include I/O supply power (OV

DD

and L2OV ) or PLL/DLL supply power (AV and L2AV ). OV and L2OV power is system dependent, but

DD

is typically <5% of V power. Worst case power consumption for AV = 15 mW and L2AV = 15 mW.

DD

2. Maximum power is measured at 105°C and V = 1.8 V while running an entirely cache-resident, contrived

DD

sequence of instructions which keep the execution units, including AltiVec, maximally busy.

3. Typical power is an average value measured at 65°C and V = 1.8 V in a system while running typical benchmarks.

DD

4.2 AC Electrical Characteristics

This section provides the AC electrical characteristics for the MPC7410. After fabrication, functional parts are

sorted by maximum processor core frequency, see Section 4.2.1, “Clock AC Specifications,” and tested for

conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus

(SYSCLK) frequency and the settings of the PLL_CFG[0:3] signals. Parts are sold by maximum processor core

frequency; see Section 10, “Ordering Information.”

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

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13

Electrical and Thermal Characteristics

4.2.1 Clock AC Specifications

Table 7 provides the clock AC timing specifications as defined in Figure 3.

Table 7. Clock AC Timing Specifications

At recommended operating conditions (see Table 3)

Maximum Processor Core Frequency

400 MHz 450 MHz 500 MHz

Characteristic

Symbol

Unit

Notes

Min

Max

Min

Max

Min

Max

Processor frequency

VCO frequency

f

350

700

33

400

800

133

30

350

700

33

450

900

133

30

350

700

33

500

1000

133

30

MHz

ns

1

core

f

VCO

SYSCLK frequency

SYSCLK cycle time

SYSCLK rise and fall time

SYSCLK duty cycle

f

t

1

SYSCLK

7.5

—

7.5

—

7.5

—

2

t

and t

0.5

60

0.5

60

0.5

ns/V

%

KR

KF

t

/t

40

60

3

KHKL SYSCLK

measured at OV /2

DD

SYSCLK jitter

Internal PLL-relock time

Notes:

—

150

100

—

150

100

—

150

100

ps

4

5

μs

1. Caution: The SYSCLK frequency and PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus)

frequency, CPU (core) frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum operating

frequencies. Refer to the PLL_CFG[0:3] signal description in Section 8.1, “PLL Configuration,” for valid PLL_CFG[0:3]

settings.

2. Rise and fall times measurement are determined by the slew rates of the bus interface, rather than by time. As a result, the

0.5 ns rise/fall time spec of the 1.8- and 2.5-V bus interfaces is equivalent to the 1 ns rise/fall time of the 3.3-V bus interface.

Both interfaces required a 2 V/ns slew rate. The slew rate is measured as a 1-V change (from 0.2 to 1.2 V) in 0.5 ns for the

1.8- and 2.5-V bus interfaces, whereas the 3.3-V bus interface required a 2-V change (from 0.4 to 2.4 V) in 1 ns.

3. Timing is guaranteed by design and characterization.

4. This represents total input jitter—short- and long-term combined—and is guaranteed by design.

5. Relock timing is guaranteed by design and characterization. PLL-relock time is the maximum amount of time required for PLL

lock after a stable V and SYSCLK are reached during the power-on reset sequence. This specification also applies when

DD

the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted

for a minimum of 255 bus clocks after the PLL-relock time during the power-on reset sequence.

Figure 3 provides the SYSCLK input timing diagram.

CV

IH

SYSCLK

VM

t

VM

CV

IL

t

KHKL

t

KR

KF

t

SYSCLK

VM = Midpoint Voltage (OV /2)

DD

Figure 3. SYSCLK Input Timing Diagram

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

14

Freescale Semiconductor

Electrical and Thermal Characteristics

4.2.2 Processor Bus AC Specifications

Table 8 provides the processor bus AC timing specifications for the MPC7410 as defined in Figure 4 and Figure 5.

Timing specifications for the L2 bus are provided in Section 4.2.3, “L2 Clock AC Specifications.”

1

Table 8. Processor Bus AC Timing Specifications

At recommended operating conditions (see Table 3)

400, 450, 500 MHz

2

Parameter

Symbol

Unit

Notes

Min

Max

Input setup

t

1.0

0

—

ns

4

IVKH

Input hold

IXKH

Output valid times:

5, 6

t

—

3.0

2.3

3.0

TS

ARTRY, SHD0, SHD1

All other outputs

KHTSV

KHARV

KHOV

Output hold times:

ns

5

9

t

0.5

—

TS

ARTRY, SHD0, SHD1

All other outputs

KHTSX

t

KHARX

t

KHOX

SYSCLK to output enable

t

0.5

—

ns

KHOE

SYSCLK to output high impedance (all except ABB/AMON(0),

ARTRY/SHD, DBB/DMON(0), SHD0, SHD1)

3.5

KHOZ

SYSCLK to ABB/AMON(0), DBB/DMON(0) high impedance after

precharge

t

—

1

t

3, 7, 9

3, 8, 9

KHABPZ

SYSCLK

Maximum delay to ARTRY, SHD0, SHD1 precharge

t

KHARP

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

15

Electrical and Thermal Characteristics

Table 8. Processor Bus AC Timing Specifications (continued)

1

At recommended operating conditions (see Table 3)

400, 450, 500 MHz

2

Parameter

Symbol

Unit

Notes

Min

Max

SYSCLK to ARTRY, SHD0, SHD1 high impedance after precharge

t

—

2

t

3, 8, 9

KHARPZ

SYSCLK

Notes:

1. All input specifications are measured from the midpoint of the signal in question to the midpoint of the rising edge of the input

SYSCLK. All output specifications are measured from the midpoint of the rising edge of SYSCLK to the midpoint of the signal

in question. All output timings assume a purely resistive 50-Ω load (see Figure 4). Input and output timings are measured at

the pin; time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. The symbology used for timing specifications herein follows the pattern of t

for inputs and

(signal)(state)(reference)(state)

t

for outputs. For example, t

symbolizes the time input signals (I) reach the valid state (V)

(reference)(state)(signal)(state)

IVKH

relative to the SYSCLK reference (K) going to the high (H) state or input setup time. And t

symbolizes the time from

KHOV

SYSCLK(K) going high (H) until outputs (O) are valid (V) or output valid time. Input hold time can be read as the time that

the input signal (I) went invalid (X) with respect to the rising clock edge (KH)— note the position of the reference and its state

for inputs—and output hold time can be read as the time from the rising edge (KH) until the output went invalid (OX).

3. t

is the period of the external clock (SYSCLK) in ns. The numbers given in the table must be multiplied by the period

SYSCLK

of SYSCLK to compute the actual time duration (in ns) of the parameter in question.

4. Includes mode select signals: BVSEL, EMODE, L2VSEL. See Figure 5 for mode select timing with respect to HRESET.

5. All other output signals are composed of the following— A[0:31], AP[0:3], TT[0:4], TS, TBST, TSIZ[0:2], GBL, WT, CI,

DH[0:31], DL[0:31], DP[0:7], BR, CKSTP_OUT, DRDY, HIT, QREQ, RSRV.

6. Output valid time is measured from 2.4 to 0.8 V which may be longer than the time required to discharge from V to 0.8 V.

DD

7. According to the 60x bus protocol, ABB and DBB are driven only by the currently active bus master. They are asserted low

then precharged high before returning to high-Z as shown in Figure 6. The nominal precharge width for ABB or DBB is 0.5

× t

, that is, less than the minimum t

period, to ensure that another master asserting ABB, or DBB on the

SYSCLK

following clock will not contend with the precharge. Output valid and output hold timing is tested for the signal asserted.

Output valid time is tested for precharge. The high-Z behavior is guaranteed by design.

8. According to the 60x bus protocol, ARTRY can be driven by multiple bus masters through the clock period immediately

following AACK. Bus contention is not an issue since any master asserting ARTRY will be driving it low. Any master asserting

it low in the first clock following AACK will then go to high-Z for one clock before precharging it high during the second cycle

after the assertion of AACK. The nominal precharge width for ARTRY is 1.0 t

; that is, it should be high-Z as shown in

SYSCLK

Figure 6 before the first opportunity for another master to assert ARTRY. Output valid and output hold timing are tested for

the signal asserted. Output valid time is tested for precharge. The high-Z behavior is guaranteed by design.

9. Guaranteed by design and not tested.

Figure 4 provides the AC test load for the MPC7410.

Z = 50 Ω

Output

OV /2

DD

0

R = 50 Ω

L

Figure 4. AC Test Load

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

16

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 5 provides the mode select input timing diagram for the MPC7410. The mode select inputs are sampled

twice, once before and once after HRESET negation.

VM

SYSCLK

HRESET

Mode Signals

First sample

Second sample

VM = Midpoint Voltage (OV /2)

DD

Figure 5. Mode Input Timing Diagram

Figure 6 provides the input/output timing diagram for the MPC7410.

SYSCLK

VM

t

IXKH

t

IVKH

All Inputs

t

KHOV

t

KHOX

All Outputs

(Except TS, ABB,

ARTRY, DBB)

t

khoe

t

KHOZ

All Outputs

(Except TS, ABB,

ARTRY, DBB)

t

KHABPZ

t

KHTSV

t

KHTSX

t

TS,

KHTSV

ABB/AMON(0),

DBB/DMON(0)

t

KHARPZ

t

KHARV

t

KHARV

KHARP

ARTRY,

SHD0,

SHD1

t

KHARX

VM = Midpoint Voltage (OV /2)

DD

Figure 6. Input/Output Timing Diagram

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

17

Electrical and Thermal Characteristics

4.2.3 L2 Clock AC Specifications

The L2CLK frequency is programmed by the L2 Configuration Register (L2CR[4:6]) core-to-L2 divisor ratio. See

Table 14 for example core and L2 frequencies at various divisors. Table 9 provides the potential range of L2CLK

output AC timing specifications as defined in Figure 7.

The L2SYNC_OUT signal is intended to be routed halfway out to the SRAMs and then returned to the L2SYNC_IN

input of the MPC7410 to synchronize L2CLK_OUT at the SRAM with the processor’s internal clock. L2CLK_OUT

at the SRAM can be offset forward or backward in time by shortening or lengthening the routing of L2SYNC_OUT

to L2SYNC_IN. See Freescale Application Note AN1794, Backside L2 Timing Analysis for the PCB Design

Engineer.

The minimum L2CLK frequency in Table 9 is specified by the maximum delay of the internal DLL. The variable-tap

DLL introduces up to a full clock period delay in the L2CLK_OUTA, L2CLK_OUTB, and L2SYNC_OUT signals

so that the returning L2SYNC_IN signal is phase-aligned with the next core clock (divided by the L2 divisor ratio).

Do not choose a core-to-L2 divisor that results in an L2 frequency below this minimum, or the L2CLK_OUT signals

provided for SRAM clocking will not be phase-aligned with the MPC7410 core clock at the SRAMs.

The maximum L2CLK frequency shown in Table 9 is the core frequency divided by one. Very few L2 SRAM

designs will be able to operate in this mode. Most designs will select a greater core-to-L2 divisor to provide a longer

L2CLK period for read and write access to the L2 SRAMs. The maximum L2CLK frequency for any application of

the MPC7410 will be a function of the AC timings of the MPC7410, the AC timings for the SRAM, bus loading,

and printed-circuit board trace length.

Freescale is similarly limited by system constraints and cannot perform tests of the L2 interface on a socketed part

on a functional tester at the maximum frequencies in Table 9. Therefore, functional operation and AC timing

information are tested at core-to-L2 divisors of two or greater.

L2 input and output signals are latched or enabled, respectively, by the internal L2CLK (which is SYSCLK

multiplied up to the core frequency and divided down to the L2CLK frequency). In other words, the AC timings in

Table 10 are entirely independent of L2SYNC_IN. In a closed loop system, where L2SYNC_IN is driven through

the board trace by L2SYNC_OUT, L2SYNC_IN only controls the output phase of L2CLK_OUTA and

L2CLK_OUTB which are used to latch or enable data at the SRAMs. However, since in a closed loop system

L2SYNC_IN is held in phase-alignment with the internal L2CLK, the signals in Table 10 are referenced to this

signal rather than the not-externally-visible internal L2CLK. During manufacturing test, these times are actually

measured relative to SYSCLK.

Table 9. L2CLK Output AC Timing Specifications

At recommended operating conditions (see Table 3)

400 MHz

450 MHz

500 MHz

Parameter

Symbol

Unit

Notes

Min

Max

Min

Max

Min

Max

L2CLK frequency

f

t

133

2.5

400

7.5

133

2.5

400

7.5

133

2.5

400

7.5

MHz

ns

1, 4

—

2

L2CLK

L2CLK cycle time

L2CLK

L2CLK duty cycle

t

/t

50

%

CHCL L2CLK

Internal DLL-relock time

DLL capture window

—

640

0

—

10

50

640

0

—

10

50

640

0

—

10

50

L2CLK

ns

3

—

5

L2CLK_OUT

t

—

ps

6

L2CSKW

output-to-output skew

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

18

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 9. L2CLK Output AC Timing Specifications (continued)

At recommended operating conditions (see Table 3)

400 MHz

450 MHz

500 MHz

Parameter

Symbol

Unit

Notes

Min

Max

Min

Max

Min

Max

L2CLK_OUT output jitter

—

150

—

150

—

150

ps

6

Notes:

1. L2CLK outputs are L2CLK_OUTA, L2CLK_OUTB, and L2SYNC_OUT pins. The L2CLK frequency to core

frequency settings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their

respective maximum or minimum operating frequencies. The maximum L2CLK frequency will be system

dependent. L2CLK_OUTA and L2CLK_OUTB must have equal loading.

2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.

3. The DLL-relock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of

L2CLK to compute the actual time duration in ns. Relock timing is guaranteed by design and characterization.

4. The L2CR[L2SL] bit should be set for L2CLK frequencies less than 150 MHz. This adds more delay to each tap of

the DLL.

5. Allowable skew between L2SYNC_OUT and L2SYNC_IN.

6. Guaranteed by design and not tested. This output jitter number represents the maximum delay of one tap forward

or one tap back from the current DLL tap as the phase comparator seeks to minimize the phase difference between

L2SYNC_IN and the internal L2CLK. This number must be comprehended in the L2 timing analysis. The input jitter

on SYSCLK affects L2CLK_OUT and the L2 address/data/control signals equally and, therefore, is already

comprehended in the AC timing and does not have to be considered in the L2 timing analysis.

The L2CLK_OUT timing diagram is shown in Figure 7.

L2 Single-Ended Clock Mode

t

L2CF

L2CR

t

L2CLK

t

CHCL

L2CLK_OUTA

L2CLK_OUTB

VM

t

L2CSKW

L2SYNC_OUT

L2 Differential Clock Mode

t

L2CLK

t

CHCL

L2CLK_OUTB

L2CLK_OUTA

VM

L2SYNC_OUT

VM = Midpoint Voltage (L2OV /2)

DD

Figure 7. L2CLK_OUT Output Timing Diagram

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

19

Electrical and Thermal Characteristics

4.2.4 L2 Bus AC Specifications

Table 10 provides the L2 bus interface AC timing specifications for the MPC7410 as defined in Figure 8 and

Figure 9 for the loading conditions described in Figure 10.

Table 10. L2 Bus Interface AC Timing Specifications

At recommended operating conditions (see Table 3)

400, 450, 500 MHz

Parameter

Symbol

Unit

Notes

Min

Max

L2SYNC_IN rise and fall time

Setup times: Data and parity

Input hold times: Data and parity

Valid times:

t

and t

—

1.5

—

1.0

—

ns

1

2

L2CR

L2CF

t

DVL2CH

DXL2CH

L2CHOV

t

0.0

2

3, 4

—

2.5

2.9

3.5

All outputs when L2CR[14–15] = 00

All outputs when L2CR[14–15] = 01

All outputs when L2CR[14–15] = 10

All outputs when L2CR[14–15] = 11

Output hold times

t

ns

3

L2CHOX

L2CHOZ

0.4

0.8

1.2

1.6

—

All outputs when L2CR[14–15] = 00

All outputs when L2CR[14–15] = 01

All outputs when L2CR[14–15] = 10

All outputs when L2CR[14–15] = 11

L2SYNC_IN to high impedance:

—

2.0

2.5

3.0

3.5

All outputs when L2CR[14–15] = 00

All outputs when L2CR[14–15] = 01

All outputs when L2CR[14–15] = 10

All outputs when L2CR[14–15] = 11

Notes:

1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OV

.

DD

2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising

edge of the input L2SYNC_IN (see Figure 8). Input timings are measured at the pins.

3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint

of the signal in question. The output timings are measured at the pins. All output timings assume a purely resistive

50-Ω load (see Figure 10).

4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous

BurstRAMs, L2CR[14–15] = 00 is recommended. For pipelined late write synchronous BurstRAMs,

L2CR[14–15] = 10 is recommended.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

20

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 8 shows the L2 bus input timing diagrams for the MPC7410.

t

L2CF

L2CR

L2SYNC_IN

VM

t

DVL2CH

t

DXL2CH

L2 Data and

Data Parity

Inputs

VM = Midpoint Voltage (L2OV /2)

DD

Figure 8. L2 Bus Input Timing Diagrams

Figure 9 shows the L2 bus output timing diagrams for the MPC7410.

L2SYNC_IN

All Outputs

L2DATA Bus

VM

t

L2CHOV

t

L2CHOX

t

L2CHOZ

VM = Midpoint Voltage (L2OV /2)

DD

Figure 9. L2 Bus Output Timing Diagrams

Figure 10 provides the AC test load for L2 interface of the MPC7410.

Output

Z = 50 Ω

0

L2OV /2

DD

R = 50 Ω

L

Figure 10. AC Test Load for the L2 Interface

4.2.5 IEEE 1149.1 AC Timing Specifications

Table 11 provides the IEEE 1149.1 (JTAG) AC timing specifications as defined in Figure 12 through Figure 15.

1

Table 11. JTAG AC Timing Specifications (Independent of SYSCLK)

At recommended operating conditions (see Table 3)

Parameter

Symbol

Min

Max

Unit

Notes

TCK frequency of operation

TCK cycle time

f

0

30

15

0

33.3

—

MHz

ns

—

TCLK

t

TCLK

TCK clock pulse width measured at OV /2

t

—

ns

DD

JHJL

TCK rise and fall times

t

and t

2

ns

JR

JF

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

21

Electrical and Thermal Characteristics

Table 11. JTAG AC Timing Specifications (Independent of SYSCLK) (continued)

1

At recommended operating conditions (see Table 3)

Parameter

Symbol

Min

Max

Unit

Notes

TRST assert time

Input setup times:

t

25

—

ns

2

TRST

t

4

0

—

3

4

Boundary-scan data

TMS, TDI

DVJH

IVJH

Input hold times:

Valid times:

ns

t

20

25

—

Boundary-scan data

TMS, TDI

DXJH

t

IXJH

t

4

20

25

Boundary-scan data

TDO

JLDV

JLOV

TCK to output high impedance:

t

3

19

9

4, 5

5

Boundary-scan data

TDO

JLDZ

JLOZ

Notes:

1. All outputs are measured from the midpoint voltage of the falling/rising edge of TCLK to the midpoint of the signal

in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load

(see Figure 11). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

3. Non-JTAG signal input timing with respect to TCK.

4. Non-JTAG signal output timing with respect to TCK.

5. Guaranteed by design and characterization.

Figure 11 provides the AC test load for TDO and the boundary-scan outputs of the MPC7410.

Output

OV /2

DD

Z = 50 Ω

0

R = 50 Ω

L

Figure 11. Alternate AC Test Load for the JTAG Interface

Figure 12 provides the JTAG clock input timing diagram.

TCLK

VM

t

VM

t

JF

JHJL

JR

t

TCLK

VM = Midpoint Voltage (OV /2)

DD

Figure 12. JTAG Clock Input Timing Diagram

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

22

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 13 provides the TRST timing diagram.

VM

TRST

t

TRST

VM = Midpoint Voltage (OV /2)

DD

Figure 13. TRST Timing Diagram

Figure 14 provides the boundary-scan timing diagram.

TCK

VM

t

DVJH

t

DXJH

Boundary

Data Inputs

Input

Data Valid

t

JLDV

t

JLDX

Boundary

Data Outputs

Output Data Valid

t

JLDZ

Boundary

Data Outputs

Output Data Valid

VM = Midpoint Voltage (OV /2)

DD

Figure 14. Boundary-Scan Timing Diagram

Figure 15 provides the test access port timing diagram.

TCK

TDI, TMS

TDO

VM

t

IVJH

t

IXJH

Input

Data Valid

t

JLOV

t

JLOX

Output Data Valid

t

JLOZ

TDO

Output Data Valid

VM = Midpoint Voltage (OV /2)

DD

Figure 15. Test Access Port Timing Diagram

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

23

Pin Assignments

5 Pin Assignments

Figure 16, part A shows the pinout for the MPC7410, 360 CBGA, 360 HCTE, and 360 HCTE Lead Free C5 Spheres

packages as viewed from the top surface. Figure 16, part B shows the side profile of the CBGA and HCTE_CBGA

packages to indicate the direction of the top surface view. Figure 16, part C shows the side profile of the

HCTE_LGA package to indicate the direction of the top surface view.

Part A

17 18 19

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

A

B

C

D

E

F

G

H

J

K

L

M

N

P

R

T

U

V

W

Not to Scale

Part B

View

BGA Package

Die

Substrate Assembly

Encapsulant

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

24

Freescale Semiconductor

Pinout Listings

Part C

View

LGA Package

Substrate Assembly

Encapsulant

Die

Figure 16. Pinout of the MPC7410, 360 CBGA and 360 HCTE Packages

as Viewed from the Top Surface

6 Pinout Listings

Table 12 provides the pinout listing for the MPC7410 360 CBGA, 360 HCTE packages.

Table 12. Pinout Listing for the MPC7410, 360 CBGA and 360 HCTE Packages

1

Signal Name

Pin Number

Active

I/O

I/F Select

Notes

A[0:31]

A13, D2, H11, C1, B13, F2, C13, E5, D13, G7, F12, G3,

G6, H2, E2, L3, G5, L4, G4, J4, H7, E1, G2, F3, J7, M3, H3,

J2, J6, K3, K2, L2

High

I/O

BVSEL

AACK

ABB

N3

Low

High

Low

—

Input

Output

I/O

BVSEL

—

12, 16

—

L7

AP[0:3]

ARTRY

C4, C5, C6, C7

L6

I/O

—

AV

A8

H1

E7

W1

Input

Output

Input

V

—

DD

BG

Low

High

BVSEL

N/A

—

BR

—

BVSEL

1, 3, 8,

9, 14

CHK

K11

C2

B8

D7

E3

K5

K1

Low

High

Low

High

Input

I/O

BVSEL

2, 8, 9

—

CI

CKSTP_IN

CKSTP_OUT

CLK_OUT

DBB

Input

Output

Input

I/O

—

12, 16

—

DBG

DH[0:31]

W12, W11, V11, T9, W10, U9, U10, M11, M9, P8, W7, P9,

W9, R10, W6, V7, V6, U8, V9, T7, U7, R7, U6, W5, U5, W4,

P7, V5, V4, W3, U4, R5

—

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

25

Pinout Listings

Table 12. Pinout Listing for the MPC7410, 360 CBGA and 360 HCTE Packages (continued)

1

Signal Name

Pin Number

Active

I/O

I/F Select

Notes

DL[0:31]

M6, P3, N4, N5, R3, M7, T2, N6, U2, N7, P11, V13, U12,

P12, T13, W13, U13, V10, W8, T11, U11, V12, V8, T1, P1,

V1, U1, N1, R2, V3, U3, W2

High

I/O

BVSEL

—

DP[0:7]

DRDY

L1, P2, M2, V2, M1, N2, T3, R1

High

Low

I/O

BVSEL

—

6, 8, 13

—

K9

D1

Output

Input

DBWO

DTI[0]

DTI[1:2]

EMODE

GBL

H6, G1

A3

High

Low

—

Input

I/O

BVSEL

N/A

5, 10, 13

7, 10

—

B1

GND

D10, D14, D16, D4, D6, E12, E8, F4, F6, F10, F14, F16,

G9, G11, H5, H8, H10, H12, H15, J9, J11, K4, K6, K8, K10,

K12, K14, K16, L9, L11, M5, M8, M10, M12, M15, N9, N11,

P4, P6, P10, P14, P16, R8, R12, T4, T6, T10, T14, T16

—

HIT

B5

Low

High

Output

Input

BVSEL

L2VSEL

6, 8

—

2

HRESET

INT

B6

C11

F8

Input

L1_TSTCLK

L2ADDR[0:16]

Input

L17, L18, L19, M19, K18, K17, K15, J19, J18, J17, J16,

H18, H17, J14, J13, H19, G18

Output

—

L2ADDR[17:18] K19,W19

High

—

Output

Input

L2VSEL

8

L2AV

L13

P17

N15

L16

V

—

DD

L2CE

Low

High

Output

I/O

L2VSEL

L2CLK_OUTA

L2CLK_OUTB

L2DATA[0:63]

U14, R13, W14, W15, V15, U15, W16, V16, W17, V17,

U17, W18, V18, U18, V19, U19, T18, T17, R19, R18, R17,

R15, P19, P18, P13, N14, N13, N19, N17, M17, M13, M18,

H13, G19, G16, G15, G14, G13, F19, F18, F13, E19, E18,

E17, E15, D19, D18, D17, C18, C17, B19, B18, B17, A18,

A17, A16, B16, C16, A14, A15, C15, B14, C14, E13

L2DP[0:7]

V14, U16, T19, N18, H14, F17, C19, B15

High

—

I/O

—

L2VSEL

N/A

—

L2OV

D15, E14, E16, H16, J15, L15, M16, K13, P15, R14, R16,

T15, F15

11

DD

L2SYNC_IN

L14

High

Input

Output

Input

L2VSEL

BVSEL

—

2

L2SYNC_OUT M14

L2_TSTCLK F7

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

26

Freescale Semiconductor

Pinout Listings

Table 12. Pinout Listing for the MPC7410, 360 CBGA and 360 HCTE Packages (continued)

1

Signal Name

Pin Number

Active

I/O

I/F Select

Notes

L2VSEL

A19

High

Input

N/A

1, 3, 8,

9, 14

L2WE

N16

G17

F9

Low

High

Low

—

Output

Input

—

L2VSEL

BVSEL

N/A

—

2

L2ZZ

LSSD_MODE

MCP

B11

15

—

OV

D5, D8, D12, E4, E6, E9, E11, F5, H4, J5, L5, M4, P5, R4,

R6, R9, R11, T5, T8, T12

DD

PLL_CFG[0:3]

QACK

QREQ

RSRV

SHD0

SHD1

SMI

A4, A5, A6, A7

High

Low

—

Input

Output

I/O

BVSEL

4

—

8

B2

J3

D3

B3

B4

I/O

5, 8

—

9

A12

Input

Output

Input

Output

Input

I/O

SRESET

SYSCLK

TA

E10

H9

F1

Low

High

Low

High

Low

High

Low

High

Low

TBEN

TBST

TCK

A2

A11

B10

TDI

B7

TDO

D9

—

9

TEA

J1

TMS

C8

TRST

TS

A10

9

K7

—

TSIZ[0:2]

TT[0:4]

WT

A9, B9, C9

Output

I/O

C10, D11, B12, C12, F11

C3

I/O

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

27

Pinout Listings

Table 12. Pinout Listing for the MPC7410, 360 CBGA and 360 HCTE Packages (continued)

1

Signal Name

Pin Number

Active

I/O

I/F Select

Notes

V

G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12

—

N/A

—

DD

Notes:

1. OV

supplies power to the processor bus, JTAG, and all control signals except the L2 cache controls (L2CE, L2WE, and

DD

L2ZZ); L2OV supplies power to the L2 cache interface (L2ADDR[0:18], L2DATA[0:63], L2DP[0:7], and L2SYNC_OUT)

DD

and the L2 control signals; and V supplies power to the processor core and the PLL and DLL (after filtering to become

DD

AV and L2AV , respectively). These columns serve as a reference for the nominal voltage supported on a given signal

DD

as selected by the BVSEL/L2VSEL pin configurations of Table 2 and the voltage supplied. For actual recommended value

of V or supply voltages, see Table 3.

in

2. These are test signals for factory use only and must be pulled up to OV for normal machine operation.

DD

3. To allow for future I/O voltage changes, provide the option to connect BVSEL and L2VSEL independently to either OV

,

DD

GND, HRESET, or ¬HRESET. For the MPC7410 the L2 bus only supports 2.5- and 1.8-V options. The default selection, if

L2VSEL is left unconnected, is 2.5-V operation. For the MPC7410 the processor bus supports 3.3-, 2.5-, and 1.8-V options.

The default selection, if BVSEL is left unconnected, is 3.3-V operation. Refer to Table 2 for supported BVSEL and L2VSEL

settings.

4. PLL_CFG[0:3] must remain stable during operation; should only be changed during the assertion of HRESET or during sleep

mode and must adhere to the internal PLL-relock time requirement.

5. Ignored input in 60x bus mode.

6. Unused output in 60x bus mode. Signal is three-stated in 60x mode.

7. Deasserted (pulled high) at HRESET negation for 60x bus mode. Asserted (pulled low) at HRESET negation for MPX bus

mode.

8. Uses one of nine existing no connects in the MPC750 360 BGA package.

9. Internal pull up on die. Pulled-up signals are V based.

DD

10.Reuses MPC750 DRTRY, DBDIS, and TLBISYNC pins (DTI1, DTI2, and EMODE, respectively).

11.The VOLTDET pin position on the MPC750 360 BGA package is now an L2OV pin on the MPC7410 360 package.

DD

12.Output only for MPC7410, was I/O for MPC750.

13.MPX bus mode only.

14.If necessary, to overcome the internal pull-up resistance and ensure this input will recognize a low signal, a pull-down

resistance less than 250 Ω should be used.

15.MCP minimum pulse width: asynchronous, falling-edge input needs to be held asserted for a minimum of 2 cycles to

guarantee that it is latched by the processor.

16.In MPX bus mode the ABB signal is called AMON and the DBB signal is called DMON. These signals are not a requirement

of the MPX bus protocol and may not be available on future products.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

28

Freescale Semiconductor

Package Description

7 Package Description

The following sections provide the package parameters and mechanical dimensions for the MPC7410, 360 CBGA

and 360 HCTE packages.

7.1 Package Parameters for the MPC7410, 360 CBGA and

360 HCTE_CBGA

The package parameters are as provided in the following list. The package types are the 25 × 25 mm, 360-lead

ceramic ball grid array package (CBGA) or the 25 × 25 mm, 360-lead high coefficient of thermal expansion CBGA

package (HCTE_CBGA).

Package outline

25 × 25 mm

Interconnects

360 (19 × 19 ball array – 1)

1.27 mm (50 mil)

2.72 mm

Pitch

Minimum module height

Maximum module height

Ball diameter

3.20 mm

0.89 mm (35 mil)

6.8 ppm/°C (CBGA)

12.3ppm/°C (HCTE_CBGA)

Coefficient of thermal expansion

7.2 Package Parameters for the MPC7410, 360 HCTE_CBGA (Lead

Free C5 Spheres)

The package parameters are as listed here. The package types are the 25 × 25 mm, 360-lead high coefficient of

thermal expansion CBGA package with lead-free C5 spheres (HCTE_CBGA lead-free spheres).

Package outline

25 × 25 mm

Interconnects

360 (19 × 19 ball array – 1)

1.27 mm (50 mil)

2.32 mm

Pitch

Minimum module height

Maximum module height

Ball diameter

2.80 mm

0.76 mm (30 mil)

12.3ppm/°C

Coefficient of thermal expansion

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

29

Package Description

7.3 Mechanical Dimensions for the MPC7410, 360 CBGA and

360 HCTE_CBGA

Figure 17 provides the mechanical dimensions and bottom surface nomenclature of the MPC7410, 360 CBGA and

360 HCTE_CBGA packages.

2X

Capacitor Region

0.2

Millimeters

D

A

DIM

MIN

MAX

A1 CORNER

D2

D4

A

2.72

0.80

1.10

—

3.20

1.00

1.30

0.60

0.90

0.93

C

A1

A2

A3

A4

b

0.15 C

0.25 C

//

0.35 C

0.82

//

E2

E

E4

D

25.00 BSC

L1

L2

D2

D4

e

—

12.50

9.00

K3

6.00

1.27 BSC

25.00 BSC

L3

L4

2X

E

K2

K1

0.2

E2

E4

F

—

14.30

11.00

K4

B

8.00

22.86 BSC

171819

1

2

3

4

5

6

7

8

9 10111213141516

W

V

U

K1

K2

K3

K4

L1

L2

L3

L4

—

9.75

—

6.46

8.20

2.75

—

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

8.60

—

9.50

—

F

6.94

3.10

3.00

A3

A2

3.30

—

A4

A1

A

e

F

360X

b

NOTES:

1. DIMENSIONING AND TOLERANCING

0.3 C A B

PER ASME Y14.5M, 1994.

C

0.15

2. DIMENSIONS IN MILLIMETERS.

3. TOP SIDE A1 CORNER INDEX IS A

METALIZED FEATURE WITH

VARIOUS SHAPES. BOTTOM SIDE A1

CORNER IS DESIGNATED WITH A

BALL MISSING FROM THE ARRAY.

Figure 17. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7410,

360 CBGA and 360 HCTE_CBGA Packages

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

30

Freescale Semiconductor

Package Description

7.4 Mechanical Dimensions for the MPC7410, 360 HCTE_CBGA

(Lead Free C5 Spheres)

Figure 18 provides the mechanical dimensions and bottom surface nomenclature of the MPC7410,

360 HCTE_CBGA (lead-free C5 spheres) package.

2X

Capacitor Region

0.2

Millimeters

D

A

DIM

MIN

MAX

A1 CORNER

D2

D4

A

2.32

0.40

1.10

—

2.80

0.60

1.30

0.60

0.90

C

A1

A2

A3

A4

b

0.15 C

0.25 C

//

0.35 C

0.82

0.60

//

E2

E

E4

D

25.00 BSC

L1

L2

D2

D4

e

—

12.50

9.00

K3

6.00

1.27 BSC

25.00 BSC

L3

L4

2X

E

K2

K1

0.2

E2

E4

F

—

14.30

11.00

K4

B

8.00

22.86 BSC

171819

1

2

3

4

5

6

7

8

9 10111213141516

W

V

U

K1

K2

K3

K4

L1

L2

L3

L4

—

9.75

—

6.46

8.20

2.75

—

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

8.60

—

9.50

—

F

6.94

3.10

3.00

A3

A2

3.30

—

A4

A1

A

e

F

360X

b

NOTES:

1. DIMENSIONING AND TOLERANCING

0.3 C A B

PER ASME Y14.5M, 1994.

C

0.15

2. DIMENSIONS IN MILLIMETERS.

3. TOP SIDE A1 CORNER INDEX IS A

METALIZED FEATURE WITH

VARIOUS SHAPES. BOTTOM SIDE A1

CORNER IS DESIGNATED WITH A

BALL MISSING FROM THE ARRAY.

Figure 18. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7410

360 HCTE_CBGA (Lead-Free C5 Spheres) Package

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

31

Package Description

7.5 Package Parameters for the MPC7410, 360 HCTE_LGA

The package parameters are as listed here. The package type is the 25 × 25 mm, 360 high coefficient of thermal

expansion LGA package (HCTE_LGA).

Package outline

25 × 25 mm

Interconnects

360 (19 × 19 land array – 1)

1.27 mm (50 mil)

1.92 mm

Pitch

Minimum module height

Maximum module height

Coefficient of thermal expansion

2.20 mm

12.3ppm/°C

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

32

Freescale Semiconductor

Package Description

7.5.1 Mechanical Dimensions for the MPC7410, 360 HCTE_LGA

Figure 19 provides the mechanical dimensions and bottom surface nomenclature of the MPC7410, 360 HCTE_LGA

package.

2X

Capacitor Region

0.2

Millimeters

D

A

DIM

MIN

MAX

A1 CORNER

D2

D4

A

A2

A3

A4

b

1.92

1.10

—

2.20

1.30

0.60

0.90

0.99

C

0.82

0.79

0.25 C

//

0.1

0.35 C

D

25.00 BSC

//

E2

E

E4

D2

D4

e

—

12.50

9.00

L1

L2

6.00

K3

1.27 BSC

25.00 BSC

E

L4

L3

2X

K2

K1

E2

E4

F

—

14.30

11.00

0.2

8.00

K4

B

22.86 BSC

K1

K2

K3

K4

L1

L2

L3

L4

—

9.75

—

171819

1

2

3

4

5

6

7

8

9 10111213141516

W

V

U

6.46

8.20

2.75

—

8.60

—

T

R

P

N

M

L

K

J

H

G

F

E

D

C

B

A

9.50

—

6.94

3.10

3.00

F

3.30

—

A3

A2

A4

A

e

F

360X

b

NOTES:

1. DIMENSIONING AND TOLERANCING

0.3 C A B

PER ASME Y14.5M, 1994.

C

0.15

2. DIMENSIONS IN MILLIMETERS.

3. TOP SIDE A1 CORNER INDEX IS A

METALIZED FEATURE WITH

VARIOUS SHAPES. BOTTOM SIDE A1

CORNER IS DESIGNATED WITH A

PAD MISSING FROM THE ARRAY.

Figure 19. Mechanical Dimensions and Bottom Surface Nomenclature for the MPC7410,

360 HCTE_LGA Package

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

33

System Design Information

7.6 Substrate Capacitors for the MPC7410

Figure 20 shows the connectivity of the substrate capacitor pads for the MPC7410, 360 CBGA and 360 HCTE

packages.

Package

Caps

Value

µF

Voltage

Reference

A1 CORNER

C6-2

C6-1

C1-1

C1-2

C2-1

C2-2

C3-1

C3-2

C4-1

C4-2

C5-1

C5-2

C6-1

C6-2

L2OV_DD

GND

C1-1

C1-2

0.01

C5-1

C5-2

L2OV_DD

GND

C4-1

C4-2

V_DD

GND

L2 L1

OV_DD

GND

OV_DD

GND

C2-2

C2-1

C3-1

C3-2

V_DD

GND

Figure 20. Substrate Bypass Capacitors for the MPC7410

8 System Design Information

This section provides electrical and thermal design recommendations for successful application of the MPC7410.

8.1 PLL Configuration

The MPC7410 PLL is configured by the PLL_CFG[0:3] signals. For a given SYSCLK (bus) frequency, the PLL

configuration signals set the internal CPU and VCO frequency of operation. The PLL configuration for the

MPC7410 is shown in Table 13 for example frequencies. In this example, shaded cells represent settings that, for a

given SYSCLK frequency, result in core and/or VCO frequencies that do not comply with the minimum and

maximum core frequencies listed in Table 8.

Table 13. MPC7410 Microprocessor PLL Configuration

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

PLL_CFG

Bus-to-

Core

Multiplier Multiplier

Core-to

VCO

[0:3]

Bus

33.3 MHz 50 MHz 66.6 MHz 75 MHz 83.3 MHz 100 MHz 133 MHz

0100

0110

1000

2x

2.5x

3x

2x

—

400

(800)

1110

1010

3.5x

4x

2x

—

350

(700)

465

(930)

400

—

(800)

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

34

Freescale Semiconductor

System Design Information

Table 13. MPC7410 Microprocessor PLL Configuration (continued)

Example Bus-to-Core Frequency in MHz (VCO Frequency in MHz)

PLL_CFG

[0:3]

Bus-to-

Core

Multiplier Multiplier

Core-to

VCO

Bus

33.3 MHz 50 MHz 66.6 MHz 75 MHz 83.3 MHz 100 MHz 133 MHz

0111

1011

1001

1101

0101

0010

0001

1100

0000

4.5x

2x

—

375

(750)

450

(900)

—

5x

375

(750)

416

(833)

500

(1000)

5.5x

6x

366

(733)

412

(825)

458

(916)

—

400

(800)

450

(900)

500

(1000)

6.5x

7x

433

(866)

488

(967)

—

350

(700)

466

(933)

—

7.5x

8x

375

(750)

500

(1000)

400

(800)

—

9x

450

(900)

0011

1111

PLL off/bypass

PLL off

PLL off, SYSCLK clocks core circuitry directly, 1x bus-to-core implied

PLL off, no core clocking occurs

Notes:

1. PLL_CFG[0:3] settings not listed are reserved.

2. The sample bus-to-core frequencies shown are for reference only. Some PLL configurations may select bus, core,

or VCO frequencies which are not useful, not supported, or not tested for by the MPC7410; see Section 4.2.1,

“Clock AC Specifications,” for valid SYSCLK, core, and VCO frequencies.

3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the

bus mode is set for 1:1 mode operation. This mode is intended for factory use and third-party emulator tool

development only.

Note: The AC timing specifications given in this document do not apply in PLL-bypass mode.

4. In PLL-off mode, no clocking occurs inside the MPC7410 regardless of the SYSCLK input.

5. PLL-off mode should not be used during chip power-up sequencing.

The MPC7410 generates the clock for the external L2 synchronous data SRAMs by dividing the core clock

frequency of the MPC7410. The divided-down clock is then phase-adjusted by an on-chip delay-lock-loop (DLL)

circuit and should be routed from the MPC7410 to the external RAMs. A separate clock output, L2SYNC_OUT is

sent out half the distance to the SRAMs and then returned as an input to the DLL on pin L2SYNC_IN so that the

rising-edge of the clock as seen at the external RAMs can be aligned to the clocking of the internal latches in the L2

bus interface.

The core-to-L2 frequency divisor for the L2 PLL is selected through the L2CLK bits of the L2CR register. Generally,

the divisor must be chosen according to the frequency supported by the external RAMs, the frequency of the

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

35

System Design Information

MPC7410 core, and the phase adjustment range that the L2 DLL supports. Table 14 shows various example L2 clock

frequencies that can be obtained for a given set of core frequencies. The minimum L2 frequency target is 133 MHz.

Sample core-to-L2 frequencies for the MPC7410 is shown in Table 14. In this example, shaded cells represent

settings that, for a given core frequency, result in L2 frequencies that do not comply with the minimum and

maximum L2 frequencies listed in Table 10.

Table 14. Sample Core-to-L2 Frequencies

Core Frequency

÷1

÷1.5

÷2

÷2.5

÷3

÷3.5

÷4

(MHz)

350

366

400

433

450

466

500

350

366

400

—

233

244

266

288

300

311

333

175

183

200

216

225

233

250

140

147

160

173

180

186

200

—

133

144

150

155

166

—

133

143

—

Note: The core and L2 frequencies are for reference only. Some examples may

represent core or L2 frequencies which are not useful, not supported, or not tested

for by the MPC7410; see Section 4.2.3, “L2 Clock AC Specifications,” for valid

L2CLK frequencies. The L2CR[L2SL] bit should be set for L2CLK frequencies less

than 150 MHz.

8.2 PLL and DLL Power Supply Filtering

The AV and L2AV power signals are provided on the MPC7410 to supply power to the PLL and DLL,

DD

respectively. Both AV and L2AV can be supplied power from the V power plane. High frequency noise in

DD

the 500 kHz to 10 MHz resonant frequency range of the PLL on the V power plane could affect the stability of

DD

the internal clocks.

On systems that use the MPC7410 HCTE device, the AV and L2AV input signals should both implement the

DD

circuit shown in Figure 21.

On systems that use the MPC7410 CBGA device, the L2AV input should implement the circuit shown in

DD

Figure 21.

When selecting which filter to use on the AV input of the MPC7410 CBGA device specifically, system designers

DD

should refer to Erratum No. 18 in the MPC7410 RISC Microprocessor Chip Errata (MPC7410CE). The AV input

DD

of the MPC7410 CBGA device is sensitive to system noise on both the V power plane, as described above, and

DD

the OV power plane as described in the Erratum No. 18. With these AV sensitivities to OV and V noise,

DD

care must be taken when selecting the filter circuit for the AV input of the MPC7410 CBGA device. Erratum

DD

No. 18 does not apply to the AV input of the MPC7401 HCTE device, nor does it affect the L2AV input of

DD

either the HCTE or the CBGA device.

As described in Erratum No. 18, when there is a high amount of noise on the OV power plane due to I/O switching

DD

rates, it is possible for the OV noise to couple into the PLL supply voltage (AV ) internal to the MPC7410

DD

CBGA package. It is the recommendation of Freescale, that new designs using the MPC7410 CBGA package

provide the ability to implement either filter shown in Figure 21 and Figure 22 at the AV input. Existing designs

DD

that implemented Figure 21 on AV may never experience the error described in Erratum No. 18. Both new and

DD

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

36

Freescale Semiconductor

System Design Information

existing designs should qualify both AV filter solutions, and the filter providing the most robust margin should

DD

be implemented.

10 Ω

AV (or L2AV

)

DD

V

DD

2.2 µF

Low ESL Surface Mount Capacitors

GND

Figure 21. PLL Power Supply Filter Circuit No.1

51 Ω

AV

V

DD

Capacitor

Pad Sites

GND

Figure 22. PLL Power Supply Filter Circuit No. 2

The filter circuit should be placed as close as possible to the AV pin to minimize noise coupled from nearby

DD

circuits. A separate circuit should be placed as close as possible to the L2AV pin. It is often possible to route

DD

directly from the capacitors to the AV pin, which is on the periphery of the 360 BGA footprint, without the

DD

inductance of vias. The L2AV pin may be more difficult to route, but is proportionately less critical.

DD

It is the recommendation of Freescale, that systems that implement the AV filter shown in Figure 22 design in the

DD

pads for the removed capacitors (shown in Figure 21), to provide for the possible reintroduction of the filter in

Figure 21. This would be necessary in case there is a planned transition from the CBGA package to the HCTE

package of the MPC7410.

8.3 Decoupling Recommendations

Due to the MPC7410 dynamic power management feature, large address and data buses, and high operating

frequencies, the MPC7410 can generate transient power surges and high frequency noise in its power supply,

especially while driving large capacitive loads. This noise must be prevented from reaching other components in the

MPC7410 system, and the MPC7410 itself requires a clean, tightly regulated source of power. Therefore, it is

recommended that the system designer place at least one decoupling capacitor at each V , OV , and L2OV

DD

pin of the MPC7410. It is also recommended that these decoupling capacitors receive their power from separate

V

, (L2)OV , and GND power planes in the PCB, utilizing short traces to minimize inductance.

DD

These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology) capacitors

should be used to minimize lead inductance, preferably 0508 or 0603 orientations, where connections are made

along the length of the part.

In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB, feeding the

V

, L2OV , and OV planes, to enable quick recharging of the smaller chip capacitors. These bulk capacitors

DD

DD DD

should have a low ESR (equivalent series resistance) rating to ensure the quick response time necessary. They should

also be connected to the power and ground planes through two vias to minimize inductance. Suggested bulk

capacitors—100–330 µF (AVX TPS tantalum or Sanyo OSCON).

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

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37

System Design Information

8.4 Connection Recommendations

To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level

through a resistor. Unused active low inputs should be tied to OV . Unused active high inputs should be connected

DD

to GND. All NC (no connect) signals must remain unconnected.

Power and ground connections must be made to all external V , OV , L2OV , and GND pins of the MPC7410.

DD

Note that power must be supplied to L2OV even if the L2 interface of the MPC7410 will not be used; the

DD

remainder of the L2 interface may be left unterminated.

8.5 Output Buffer DC Impedance

The MPC7410 60x and L2 I/O drivers are characterized over process, voltage, and temperature. To measure Z , an

0

external resistor is connected from the chip pad to OV or GND. Then, the value of each resistor is varied until

DD

the pad voltage is OV /2 (see Figure 23).

DD

The output impedance is the average of two components, the resistances of the pull-up and pull-down devices. When

data is held low, SW2 is closed (SW1 is open), and R is trimmed until the voltage at the pad equals (L2)OV /2.

N

DD

R then becomes the resistance of the pull-down devices. When data is held high, SW1 is closed (SW2 is open), and

N

R is trimmed until the voltage at the pad equals (L2)OV /2. R then becomes the resistance of the pull-up devices.

P

DD

P

R and R are designed to be close to each other in value. Then, Z = (R + R )/2.

P

N

0

P

N

Figure 23 describes the driver impedance measurement circuit described above.

OV

DD

R

N

SW2

SW1

Pad

Data

R

P

OGND

Figure 23. Driver Impedance Measurement Circuit

Alternately, the following is another method to determine the output impedance of the MPC7410. A voltage source,

V

, is connected to the output of the MPC7410, as in Figure 24. Data is held low, the voltage source is set to a

force

value that is equal to (L2)OV /2, and the current sourced by V

is measured. The voltage drop across the

DD

force

pull-down device, which is equal to (L2)OV /2, is divided by the measured current to determine the output

DD

impedance of the pull-down device, R . Similarly, the impedance of the pull-up device is determined by dividing

N

the voltage drop of the pull-up, (L2)OV /2, by the current sank by the pull-up when the data is high and V

is

DD

force

equal to (L2)OV /2. This method can be employed with either empirical data from a test setup or with data from

DD

simulation models, such as IBIS.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

38

Freescale Semiconductor

System Design Information

R and R are designed to be close to each other in value. Then, Z = (R + R )/2. Figure 24 describes the alternate

P

N

0

P

N

driver impedance measurement circuit.

(L2)OV

DD

BGA

V

Data

force

OGND

Figure 24. Alternate Driver Impedance Measurement Circuit

Table 15 summarizes the signal impedance results. The driver impedance values were characterized at 0°, 65°, and

105°C. The impedance increases with junction temperature and is relatively unaffected by bus voltage.

Table 15. Impedance Characteristics

V_DD= 1.8 V, OV_DD= 2.5 V, T_j= 0° – 105°C

Impedance

Processor Bus

L2 Bus

Symbol

Unit

R

N

41.5–54.3

37.3–55.3

42.7–54.1

39.3–50.0

Z

Ω

0

R

P

Z

0

8.6 Pull-Up Resistor Requirements

The MPC7410 requires pull-up resistors (1 kΩ–5 kΩ) on several control pins of the bus interface to maintain the

control signals in the negated state after they have been actively negated and released by the MPC7410 or other bus

masters. These pins are: TS, ARTRY, SHDO, SHD1.

Four test pins also require pull-up resistors (100 Ω−1 kΩ). These pins are CHK, L1_TSTCLK, L2_TSTCLK, and

LSSD_MODE. These signals are for factory use only and must be pulled up to OV for normal machine

DD

operation.

If pull-down resistors are used to configure BVSEL or L2VSEL, the resistors should be less than 250 Ω (see Table

12). Because PLL_CFG[0:3] must remain stable during normal operation, strong pull-up and pull-down resistors

(1 kΩ or less) are recommended to configure these signals in order to protect against erroneous switching due to

ground bounce, power supply noise or noise coupling.

In addition, CKSTP_OUT is an open-drain style output that requires a pull-up resistor (1 kΩ–5 kΩ) if it is used by

the system. The CKSTP_IN signal should likewise be pulled up through a pull-up resistor (1 kΩ–5 kΩ) to prevent

erroneous assertions of this signal.

During inactive periods on the bus, the address and transfer attributes may not be driven by any master and may,

therefore, float in the high-impedance state for relatively long periods of time. Since the MPC7410 must continually

monitor these signals for snooping, this float condition may cause excessive power draw by the input receivers on

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

39

System Design Information

the MPC7410 or by other receivers in the system. These signals can be pulled up through weak (10-kΩ) pull-up

resistors by the system, address bus driven mode can be enabled (see the MPC7410 RISC Microprocessor Family

Users’ Manual for more information on this mode), or these signals may be otherwise driven by the system during

inactive periods of the bus to avoid this additional power draw. The snooped address and transfer attribute inputs

are: A[0:31], AP[0:3], TT[0:4], CI, WT, and GBL.

In systems where GBL is not connected and other devices may be asserting TS for a snoopable transaction while not

driving GBL to the processor, we recommend that a strong (1 kΩ) pull-up resistor be used on GBL. Note that the

MPC7410 will only snoop transactions when GBL is asserted.

The data bus input receivers are normally turned off when no read operation is in progress and, therefore, do not

require pull-up resistors on the bus. Other data bus receivers in the system, however, may require pull-ups, or that

those signals be otherwise driven by the system during inactive periods by the system. The data bus signals are:

DH[0:31], DL[0:31], and DP[0:7].

If address or data parity is not used by the system, and the respective parity checking is disabled through HID0, the

input receivers for those pins are disabled, and those pins do not require pull-up resistors and should be left

unconnected by the system. If parity checking is disabled through HID0, and parity generation is not required by the

MPC7410 (note that the MPC7410 always generates parity), then all parity pins may be left unconnected by the

system.

The L2 interface does not normally require pull-up resistors.

8.7 JTAG Configuration Signals

Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the IEEE

1149.1 specification, but is provided on all processors that implement the PowerPC architecture. While it is possible

to force the TAP controller to the reset state using only the TCK and TMS signals, more reliable power-on reset

performance will be obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is

also used for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not

practical.

The COP function of these processors allows a remote computer system (typically, a PC with dedicated hardware

and debugging software) to access and control the internal operations of the processor. The COP interface connects

primarily through the JTAG port of the processor, with some additional status monitoring signals. The COP port

requires the ability to independently assert HRESET or TRST in order to fully control the processor. If the target

system has independent reset sources, such as voltage monitors, watchdog timers, power supply failures, or

push-button switches, then the COP reset signals must be merged into these signals with logic.

The arrangement shown in Figure 25 allows the COP port to independently assert HRESET or TRST, while ensuring

that the target can drive HRESET as well. If the JTAG interface and COP header will not be used, TRST should be

tied to HRESET through a 0-Ω isolation resistor so that it is asserted when the system reset signal (HRESET) is

asserted, ensuring that the JTAG scan chain is initialized during power-on. While Freescale recommends that the

COP header be designed into the system as shown in Figure 25, if this is not possible, the isolation resistor will allow

future access to TRST in the case where a JTAG interface may need to be wired onto the system in debug situations.

The COP header shown in Figure 25 adds many benefits—breakpoints, watchpoints, register and memory

examination/modification, and other standard debugger features are possible through this interface—and can be as

inexpensive as an unpopulated footprint for a header to be added when needed.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

40

Freescale Semiconductor

System Design Information

SRESET

From Target

Board Sources HRESET

6

HRESET

(if any)

QACK

10 kΩ

HRESET

13

11

OV

DD

SRESET

OV

DD

OV

5

0 Ω

6

TRST

1

3

2

4

TRST

4

6

VDD_SENSE

OV

DD

10 kΩ

2 kΩ

5

6

1

5

DD

7

8

CHKSTP_OUT

15

10 kΩ

9

10

12

OV

DD

Key

14

11

10 kΩ

2

DD

KEY

No Pin

13

15

CHKSTP_IN

TMS

CHKSTP_IN

TMS

8

9

1

3

16

TDO

TDI

COP Connector

Physical Pin Out

TDO

TDI

TCK

7

2

TCK

QACK

10

NC

OV

DD

3

2 kΩ

10 kΩ

12

16

OV

4

10 kΩ

Notes:

1. RUN/STOP, normally found on pin 5 of the COP header, is not implemented on the MPC7410. Connect

pin 5 of the COP header to OV with a 10-kΩ pull-up resistor.

DD

2. Key location; pin 14 is not physically present on the COP header.

3. Component not populated. Populate only if debug tool does not drive QACK.

4. Populate only if debug tool uses an open-drain type output and does not actively negate QACK.

5. If the JTAG interface is implemented, connect HRESET from the target source to TRST from the COP

header though an AND gate to TRST of the part. If the JTAG interface is not implemented, connect

HRESET from the target source to TRST of the part through a 0-Ω isolation resistor.

6. The COP port and target board should be able to independently assert HRESET and TRST to the pro-

cessor in order to fully control the processor as shown above.

Figure 25. COP Connector Diagram

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

41

System Design Information

The COP interface has a standard header for connection to the target system, based on the 0.025" square-post 0.100"

centered header assembly (often called a Berg header). The connector typically has pin 14 removed as a connector

key.

There is no standardized way to number the COP header shown in Figure 25; consequently, many different pin

numbers have been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while

others use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as with

an IC). Regardless of the numbering, the signal placement recommended in Figure 25 is common to all known

emulators.

The QACK signal shown in Figure 25 is usually connected to the PCI bridge chip in a system and is an input to the

MPC7410 informing it that it can go into the quiescent state. Under normal operation this occurs during a low-power

mode selection. In order for COP to work, the MPC7410 must see this signal asserted (pulled down). While shown

on the COP header, not all emulator products drive this signal. If the product does not, a pull-down resistor can be

populated to assert this signal. Additionally, some emulator products implement open-drain type outputs and can

only drive QACK asserted; for these tools, a pull-up resistor can be implemented to ensure this signal is negated

when it is not being driven by the tool. Note that the pull-up and pull-down resistors on the QACK signal are

mutually exclusive and it is never necessary to populate both in a system. To preserve correct power-down operation,

QACK should be merged via logic so that it also can be driven by the PCI bridge.

8.8 Thermal Management Information

This section provides thermal management information for the MPC7410 for air-cooled applications. Proper

thermal control design is primarily dependent on the system-level design—the heat sink, airflow, and thermal

interface material. To reduce the die-junction temperature, heat sinks may be attached to the package by several

methods such as spring clip to holes in the printed circuit board or with screws and springs to the printed circuit

board; see Figure 26 for the BGA package and Figure 27 for the LGA package. This spring force should not exceed

5.5 pounds of force. Note that care should be taken to avoid focused forces being applied to die corners and/or edges

when mounting heat sinks.

BGA Package

Heat Sink

Clip

Thermal Interface Material

Printed-Circuit Board

Figure 26. BGA Package Exploded Cross-Sectional View with Heat Sink Clip to PCB Option

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

42

Freescale Semiconductor

System Design Information

LGA Package

Heat Sink

Clip

Thermal

Interface Material

Printed-Circuit Board

Figure 27. LGA Package Exploded Cross-Sectional View with Heat Sink Clip to PCB Option

The board designer can choose between several types of heat sinks to place on the MPC7410. There are several

commercially-available heat sinks for the MPC7410 from the following vendors:

Aavid Thermalloy

70 Commercial Street, Suite 200

Concord, NH 03301

603-224-9988

408-567-8082

800-347-4572

Internet: www.aavidthermalloy.com

Alpha Novatech

473 Sapena Ct. #12

Santa Clara, CA 95054

Internet: www.alphanovatech.com

The Bergquist Company

18930 West 78th St.

Chanhassen, MN 55317

Internet: www.bergquistcompany.com

International Electronic Research Corporation (IERC) 818-842-7277

413 North Moss St.

Burbank, CA 91502

Internet: www.ctscorp.com

Wakefield Engineering

33 Bridge St.

603-635-2800

Pelham, NH 03076

Internet: www.wakefield.com

Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal performance at

a given air velocity, spatial volume, mass, attachment method, assembly, and cost.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

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System Design Information

8.8.1 Internal Package Conduction Resistance

For the exposed-die packaging technology, shown in Table 3, the intrinsic conduction thermal resistance paths are

as follows:

•

The die junction-to-case (or top-of-die for exposed silicon) thermal resistance

The die junction-to-ball thermal resistance

Figure 28 depicts the primary heat transfer path for a package with an attached heat sink mounted to a printed-circuit

board.

Heat generated on the active side of the chip is conducted through the silicon, then through the heat sink attach

material (or thermal interface material), and finally to the heat sink where it is removed by forced-air convection.

Since the silicon thermal resistance is quite small, for a first-order analysis, the temperature drop in the silicon may

be neglected. Thus, the heat sink attach material and the heat sink conduction/convective thermal resistances are the

dominant terms.

External Resistance

Radiation

Convection

Heat Sink

Thermal Interface Material

Die/Package

Die Junction

Package/Leads

Internal Resistance

Printed-Circuit Board

Radiation

Convection

External Resistance

Note the internal versus external package resistance.

Figure 28. C4 Package with Heat Sink Mounted to a Printed-Circuit Board

8.8.2 Adhesives and Thermal Interface Materials

A thermal interface material is recommended at the package lid-to-heat sink interface to minimize the thermal

contact resistance. For those applications where the heat sink is attached by spring clip mechanism, Figure 29 shows

the thermal performance of three thin-sheet thermal-interface materials (silicone, graphite/oil, floroether oil), a bare

joint, and a joint with thermal grease as a function of contact pressure. As shown, the performance of these thermal

interface materials improves with increasing contact pressure. The use of thermal grease significantly reduces the

interface thermal resistance. That is, the bare joint results in a thermal resistance approximately seven times greater

than the thermal grease joint.

Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see Figure 26).

This spring force should not exceed 5.5 pounds of force. Therefore, the synthetic grease offers the best thermal

performance, considering the low interface pressure. Of course, the selection of any thermal interface material

depends on many factors—thermal performance requirements, manufacturability, service temperature, dielectric

properties, cost, and so on.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

44

Freescale Semiconductor

System Design Information

Figure 29 describes the thermal performance of selected thermal interface materials.

Silicone Sheet (0.006")

Bare Joint

2

Floroether Oil Sheet (0.007")

Graphite/Oil Sheet (0.005")

Synthetic Grease

1.5

1

0.5

0

10

20

30

Contact Pressure (psi)

Figure 29. Thermal Performance of Select Thermal Interface Material

40

50

60

70

80

The board designer can choose between several types of thermal interface. Heat sink adhesive materials should be

selected based on high conductivity, yet adequate mechanical strength to meet equipment shock/vibration

requirements. There are several commercially-available thermal interfaces and adhesive materials provided by the

following vendors:

Chomerics, Inc.

781-935-4850

77 Dragon Court

Woburn, MA 01888-4014

Internet: www.chomerics.com

Dow-Corning Corporation

Dow-Corning Electronic Materials

2200 W. Salzburg Rd.

800-248-2481

Midland, MI 48686-0997

Internet: www.dow.com

Shin-Etsu MicroSi, Inc.

10028 S. 51st St.

888-642-7674

Phoenix, AZ 85044

Internet: www.microsi.com

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

45

System Design Information

Thermagon Inc.

888-246-9050

4707 Detroit Ave.

Cleveland, OH 44102

Internet: www.thermagon.com

8.8.3 Heat Sink Selection Example

For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:

T = T + T + (θ + θ + θ ) × P

d

j

a

r

jc

int

sa

where:

T is the die-junction temperature

j

T is the inlet cabinet ambient temperature

a

T is the air temperature rise within the computer cabinet

r

θ is the junction-to-case thermal resistance

jc

θ

is the adhesive or interface material thermal resistance

is the heat sink base-to-ambient thermal resistance

int

sa

P is the power dissipated by the device

d

During operation the die-junction temperatures (T ) should be maintained less than the value specified in Table 3.

j

The temperature of the air cooling the component greatly depends upon the ambient inlet air temperature and the air

temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (T ) may range from 30°

a

to 40°C. The air temperature rise within a cabinet (T ) may be in the range of 5° to 10°C. The thermal resistance of

r

the thermal interface material (θ ) is typically about 1°C/W. Assuming a T of 30°C, a T of 5°C, a CBGA package

int

a

r

θ = 0.03, and a power consumption (P ) of 5.0 W, the following expression for T is obtained:

jc

d

j

Die-junction temperature: T = 30°C + 5°C + (0.03°C/W + 1.0°C/W + θ ) × 5.0 W

j

sa

For a Thermalloy heat sink #2328B, the heat sink-to-ambient thermal resistance (θ ) versus airflow velocity is

sa

shown in Figure 30.

Assuming an air velocity of 0.5 m/s, we have an effective R of 7°C/W, thus

sa

T = 30°C + 5°C + (0.03°C/W + 1.0°C/W + 7°C/W) × 5.0 W,

j

resulting in a die-junction temperature of approximately 75°C which is well within the maximum operating

temperature of the component.

Other heat sinks offered by Aavid Thermalloy, Alpha Novatech, The Bergquist Company, IERC, and Wakefield

Engineering offer different heat sink-to-ambient thermal resistances, and may or may not need airflow.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

46

Freescale Semiconductor

System Design Information

8

7

6

5

4

3

2

1

Thermalloy #2328B Pin-Fin Heat Sink

(25 × 28 × 15 mm)

0

0.5

1

1.5

2

2.5

3

3.5

Approach Air Velocity (m/s)

Figure 30. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity

Though the die junction-to-ambient and the heat sink-to-ambient thermal resistances are a common figure-of-merit

used for comparing the thermal performance of various microelectronic packaging technologies, one should

exercise caution when only using this metric in determining thermal management because no single parameter can

adequately describe three-dimensional heat flow. The final die-junction operating temperature, is not only a function

of the component-level thermal resistance, but the system-level design and its operating conditions. In addition to

the component's power consumption, a number of factors affect the final operating die-junction

temperature—airflow, board population (local heat flux of adjacent components), heat sink efficiency, heat sink

attach, heat sink placement, next-level interconnect technology, system air temperature rise, altitude, and so on.

Due to the complexity and the many variations of system-level boundary conditions for today's microelectronic

equipment, the combined effects of the heat transfer mechanisms (radiation, convection, and conduction) may vary

widely. For these reasons, we recommend using conjugate heat transfer models for the board, as well as,

system-level designs.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

47

Document Revision History

9 Document Revision History

Table 16 provides a revision history for this hardware specification.

Table 16. Document Revision History

Revision

Date

Substantive Change(s)

6.1

11/16/2007 Updated Table 17 and Table 19 to show the VU package is available as an MC prefix device compared

to an MPC prefix for the other package types; this was done to match the specification documents

with the device ordering and part marking information.

Updated title of Table 19 to reflect correct name of referenced document and updated respective

document order information below table.

Updated notes in Table 1–Table 3 replacing references to MPC7410RXnnnLE with Mxx7410xxnnnLE

since notes to apply to all the available packages types.

6

8/14/2007 Updated Table 4 thermal information:

• Deleted rows on single-layer (1s) boards.

• CBGA package R

• HCTE package R

for natural convection for four layer boards changed from 17 to 18 °C/W.

for natural convection for four layer boards changed from 22 to 20 °C/W.

for 200 ft./min airflow for four layer boards changed from 19 to 16 °C/W with

JMA

θ

JMA

• HCTE package R

JMA

θ

airflow rate specification changed from 200 ft./min to 1 m/sec.

• HCTE package R for 400 ft./min airflow for four layer boards changed from 18 to 15 °C/W with

JMA

θ

airflow rate specification changed from 400 ft./min to 2 m/sec.

• CBGA package R

• HCTE package R

changed from 8 to 9°C/W.

changed from 14 to 11°C/W.

JB

θ

JB

• Table 4 Notes 2 - 4 have been revised and updated; Note 5 is no longer used. Notes on table rows

have been renumbered.

Updated Figure 26 removing optional heat sink clip to package.

Removed references in document to adhesive attached thermal solutions.

Updated thermal solution vendor information in Section 8.8.

Added HCTE_CBGA Lead Free C5 Spheres (VU) packaging information to document:

• Added Section 7.2, “Package Parameters for the MPC7410, 360 HCTE_CBGA (Lead Free C5

Spheres).

• Added Figure 18 for HCTE_CBGA Lead Free C5 Spheres package, similar to Figure 17 but with

differences in dimensions A, A1, and b in the figure’s dimension table.

• Added HCTE_CBGA Lead Free C5 Spheres (VU) packaging information in Table 17 and Table 19.

• Changed part marking example in Figure 31 to an HCTE_CBGA device.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

48

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Document Revision History

Table 16. Document Revision History (continued)

Substantive Change(s)

Revision

Date

5

4/13/2005 Section numbering revised. In all previous versions, section numbering began with ‘1.’ These extra

‘1’s’ were deleted. For example, previously numbered section 1.8.2 changed to 8.2.

Section 7.1—added CTE value for HCTE package. Corrected minimum module height from 2.65 mm

to 2.72 mm per Figure 17.

Section 3—added HCTE_LGA (VS package descriptor) package description which is the

HCTE_CBGA (HX package descriptor) with the spheres removed.

Table 4—generalized ‘HCTE CBGA’ column to ‘HCTE’ to include both HCTE_CBGA and HCTE_LGA

package thermal characteristics.

Section 5—added HCTE_LGA package. The HCTE_LGA has the same pin assignments as the

CBGA and HCTE_CBGA packages. Added side view Part C for HCTE_LGA.

Section 6—added HCTE_LGA package (VS package descriptor). The HCTE_LGA has the same

pinout listing as the CBGA and HCTE packages.

Section 7.3—added HCTE_LGA package parameters.

Section 7.4—added HCTE_LGA package mechanical dimensions.

Table 17—added HCTE_LGA package (VS package descriptor) to part numbering nomenclature.

4

3

—

Table 5—Changed measurement test condition I from -6mA to –5 mA for V and I from 6 mA

OH OH OL

to 5 mA for V per Product Bulletin.

OL

Section 1.8.2—revised text regarding AV filter selection for the CBGA package.

DD

Table 6—Changed note 1 to specify that OV and L2OV power is typically <5% of V power.

DD

Figure 17—revised diagram and dimensions to specify ‘cap regions’ versus individual cap

measurements. Moved individual capacitor placement to separate figure.

Figure 18—Added this figure to show each individual capacitor placement and value.

Figure 22—updated COP Connector Diagram to recommend a weak pull-up resistor on TCK.

Public release, includes Rev 1.1 changes.

2

—

Section 1.7.2—added package capacitor values.

Section 1.8.6—added recommendation that strong pull-up/down resistors be used on the

PLL_CFG[0:3] signals.

Table 8—removed mode input setup and hold times. These inputs adhere to the general input setup

and hold specifications.

Figure 5—revised mode input diagram to show sample points around HRESET negation.

Section 1.3—added HCTE package description.

Figure 22—added note 6 to emphasize that COP emulator and target board need to be able to drive

HRESET and TRST independently to the CPU.

Section 1.8.2—revised section for HCTE package. Added text and figure for AV filter for the CBGA

DD

package.

Section 1.8.6—removed AACK, TEA, and TS from control signals requiring pull-ups. Removed TBST

from snooped transfer attribute list. TBST is an output and is not snooped.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

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49

Document Revision History

Table 16. Document Revision History (continued)

Substantive Change(s)

Revision

Date

1.1

—

Internal release.

Table 12—added note 16 for ABB/AMON and DBB/DMON signal clarification.

Table 12—changed CHK note 4 reference to note 2, signal is for factory test only. Changed previous

note 4 (CHK related) to now provide additional PLL info.

Table 1—modified maximum value for OV from –0.3 to 3.465 to now be –0.3 to 3.6 and L2OV

DD

from –0.3 to 2.6 to now be –0.3 to 2.8. Modified note 6, OV for revisions prior to Rev. 1.4 have

DD

maximum value for OV of –0.3 to 2.8.

DD

Table 8—removed note 12. L2_TSTCLK is for factory use only (see Table 12, note 2).

Section 1.10.2—revised section to include nomenclature tables for part markings not covered by this

spec.

Figure 2—added that under/overshoot for L2OV references t

while OV references t

.

DD

L2CLK

DD

SYSCLK

Table 4—added HCTE package (HX package descriptor) thermal characteristics.

Section 1.5—added HCTE package (HX package descriptor). Both the CBGA and HCTE packages

have the same pin assignments.

Section 1.6—added HCTE package (HX package descriptor). Both the CBGA and HCTE packages

have the same pinout listings.

Section 1.7—added HCTE package (HX package descriptor). Both the CBGA and HCTE packages

have the same package parameters and dimensions.

Table 17—added HCTE package (HX package descriptor) to part numbering nomenclature.

Table 21—added MPC7410THXnnnLE extended temperature HCTE package part numbers and part

number specification document reference.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

50

Freescale Semiconductor

Document Revision History

Table 16. Document Revision History (continued)

Substantive Change(s)

Revision

Date

1.0

—

Section 1.3 and Table 3—revised OV

from 3.3 V 100 mV to 3.3 V 165 mV.

DD

Table 13—removed unsupported PLL configurations.

Table 12—added note 15 for minimum MCP pulse width, correct note 3 for 3.3-V processor bus

support.

Table 13—revised note 3 to include emulator tool development.

Table 14—removed unsupported Core-to-L2 example frequencies.

Section 1.8.8—updated heat sink vendors list.

Section 1.8.8.2—updated interface vendors list.

Table 1—updated voltage sequencing requirements notes 3 and 4.

Table 4—Updated/added thermal characteristics.

Table 5—removed table and TAU related information, TAU is no longer supported.

Table 6—updated I and I

leakage current specs.

in

TSI

Section 1.8.3—removed section.

Section 1.10—reformatted section.

Section 1.8.6—changed recommended pull-up resistor value to 1 kW–5 kW. Added AACK, TEA, and

TS to control signals needing pull-ups. Added pull-up resistor value recommendation for

L1_TSTCLK, L2_TSTCLK, and LSSD_MODE factory test signals.

Section 1.8.7—revised text regarding connection of TRST. Combined Figure 22, Figure 23, and Table

17, into Figure 21.

Table 7—corrected min VCO frequencies from 450 to 700 MHz to match min processor frequency of

350 MHz.

Table 2—added note 3 to clarify BVSEL for revisions prior to Rev. E which do not support 3.3 V OV

.

DD

Table 3—added notes 5 and 6 to clarify BVSEL for revisions prior to Rev. E which do not support 3.3 V

OV

.

DD

Table 5—added note 8 regarding DC voltage limits for JTAG signals.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

51

Document Revision History

Table 16. Document Revision History (continued)

Revision

Date

Substantive Change(s)

0.3

—

Added 3.3 V support on the processor bus (BVSEL).

Table 7—update typical and maximum power numbers for full-on mode in. Removed note 4.

Reworded notes 2 and 3.

Table 9, Note 2—removed reference to application note.

Figure 17—corrected side view datum A to be datum C.

Section 1.8.7—added CI and WT to transfer attribute signals requiring pull-ups.

Section 1.8.7—added 1-kΩ pull-up recommendation to GBL when GBL is not connected.

Table 2— added pull-down resistance necessary for internally pulled-up voltage select pins. Added

3.3-V support for BVSEL.

Table 13—added note 14 for BVSEL, L2VSEL, and TRST pins to address pull-down resistance

necessary for these internally pulled-up pins to recognize a low signal.

Table 6—lowered 2.5 V CV from 2.2 to 2.0 V to be compatible with V of the MPC107. Added

IH

OH

support for 3.3-V processor bus.

Table 15—modified note 1, use L2CR[L2SL] for L2CLK frequency less than 150 MHz.

Table 8—revised note 2 discussing for 3.3-V bus voltage support.

Table 14—added note 5, do not use PL off during power-up sequence.

Table 1—update output hold times (t

).

L2CHOX

0.2

—

Corrected Section 1.3—technology from 0.13 µm to 0.18 µm.

Updated Table 7—adds power consumption numbers; adds note on estimated decrease w/o AltiVec.

Updated Table 8—adds minimum values for processor frequency and VCO frequency.

Updated Table 9—input setup, output valid times, output hold times, SYSCLK to output high

impedance.

Updated Table 11—L2SYNC_IN to high impedance.

Updated Figure 17—mechanical dimensions, adds capacitor pad dimensions.

0.1

0

—

Minor updates.

Initial release.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

52

Freescale Semiconductor

Ordering Information

10 Ordering Information

Ordering information for the parts fully covered by this specification document is provided in Section 10.1, “Part

Numbers Addressed by This Specification.” Section 10.2, “Part Numbers Not Fully Addressed by This Document,”

lists the part numbers which do not fully conform to the specifications of this document. These special part numbers

require an additional document called a part number specification.

10.1 Part Numbers Addressed by This Specification

Table 17 provides the Freescale part numbering nomenclature for the MPC7410 Note that the individual part

numbers correspond to a maximum processor core frequency. For available frequencies, contact your local Freescale

sales office. In addition to the processor frequency, the part numbering scheme also includes an application modifier

which may specify special application conditions. Each part number also contains a revision code which refers to

the die mask revision number.

Table 17. Part Numbering Nomenclature

Mxx 7410

xx

nnn

x

Product

Code Identifier

Part

Processor

Frequency

Application

Modifier

1

Package

Revision Level

2

MPC

7410

RX = CBGA

400

450

500

L: 1.8 V 100 mV C: 1.2; PVR = 800C 1102

0° to 105°C

D: 1.3; PVR = 800C 1103

E: 1.4; PVR = 800C 1104

HX = HCTE_CBGA

VS = HCTE_LGA

E: 1.4; PVR = 800C 1104

MC

VU = HCTE_CBGA

(Lead Free C5

400

500

Solder Spheres)

Notes:

1. See Section 7, “Package Description,” for more information on available package types and Table 4 for more

information on thermal characteristics.

2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this

specification support all core frequencies. Additionally, parts addressed by part number specifications may

support other maximum core frequencies.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

53

Ordering Information

10.2 Part Numbers Not Fully Addressed by This Document

Parts with application modifiers or revision levels not fully addressed in this specification document are described

in separate part number specifications which supplement and supersede this document, as described in the following

tables.

Table 18. Part Numbers Addressed by MPC7410RXnnnPx Series Part Number Specifications

MPC 7410

RX

nnn

P

x

Product

Code

Part

Identifier

Processor

Frequency

Application

Modifier

Package

RX = CBGA

Revision Level

1

MPC

7410

450

500

550

P: 2.0 V 50 mV

C: 1.2; PVR = 800C 1102

D: 1.3; PVR = 800C 1103

2

0° to 65°C

3

E: 1.4; PVR = 800C 1104

Notes: Document order numbers:

1. MPC7410PCPNS.

2. MPC7410PDPNS.

3. MPC7410PEPNS.

Table 19. Part Numbers Addressed by MPC7410 RISC Microprocessor HardwareSpecifications Addendum

for the MPC7410xxnnnNE Series

Mxx

7410

xx

nnn

N

E

Product

Code

Part

Identifier

Processor

Frequency

Application

Modifier

Package

Revision Level

1

MPC

7410

RX = CBGA

400

450

500

N: 1.5 V 50 mV

E: 1.4; PVR = 800C 1104

HX = HCTE_CBGA

VS = HCTE_LGA

400

450

MC

VU = HCTE_CBGA

(Lead Free C5 Solder

Spheres)

Note: Document order number: MPC7410ECS02AD

Table 20. Part Numbers Addressed by MPC7410TRXnnnNE Part Number Specification

MPC 7410

T

RX

nnn

N

E

Product

Code

Part

Identifier

Process

Descriptor

Processor

Frequency

Application

Modifier

Package

Revision Level

1

MPC

7410

T: –40° to 105°C RX = CBGA

400

450

N: 1.5 V 50 mV E: 1.4; PVR = 800C 1104

Note: Document order number: MPC7410TRXNEPNS.

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

54

Freescale Semiconductor

Ordering Information

10.3 Part Marking

Parts are marked as the example shown in Figure 31.

MPC7410

HXnnnLE

MMMMMM

AWLYYWWA

7410

HCTE_CBGA

Notes:

MMMMMM is the 6-digit mask number.

AWLYYWWA is the traceability code.

CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.

Figure 31. Part Marking for HCTE_CBGA Device

MPC7410 RISC Microprocessor Hardware Specifications, Rev. 6.1

Freescale Semiconductor

55

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Information in this document is provided solely to enable system and software implementers to

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rights reserved.

MPC7410EC

Rev. 6.1

11/2007


型号：	MPC7410RX400LD
厂家：	NXP
描述：	IC,MICROPROCESSOR,32-BIT,CMOS,BGA,360PIN,CERAMIC 时钟外围集成电路
文件：	总56页 (文件大小：864K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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