MPC8245ARVV400D [NXP]
32-BIT, 400MHz, RISC PROCESSOR, PBGA352, 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, LEAD FREE, TBGA-352;
| 型号： | MPC8245ARVV400D |
| 厂家： | 
NXP |
| 描述： | 32-BIT, 400MHz, RISC PROCESSOR, PBGA352, 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, LEAD FREE, TBGA-352 时钟 外围集成电路 |
| 文件： | 总16页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MPC8245ECS02AD
Rev. 3, 12/2005
Freescale Semiconductor
Technical Data
MPC8245 Hardware Specifications
Addendum for the
MPC8245ARXXnnnx Series
Freescale Part Numbers Affected:
MPC8245ARZU400D
Specifications provided in this document supersede those in
the MPC8245 Integrated Processor Hardware
Specifications, Rev. 3 or later, for the part numbers listed in
Table A only.
MPC8245ARVV400D
Specifications not addressed in this document are
unchanged. Because this document is frequently updated,
refer to http://www.freescale.com or to your Freescale sales
office for the latest version.
Note that headings and table numbers in this document are
not consecutively numbered. They are intended to
correspond to the heading or table affected in the general
hardware specification.
Part numbers addressed in this document are listed in
Table A. For more detailed ordering information, see
Section 9, “Ordering Information.”
© Freescale Semiconductor, Inc., 2005. All rights reserved.
Electrical and Thermal Characteristics
Table A. Part Numbers Addressed in this Data Sheet
Operating Conditions
Processor
Version
Register
Value
Freescale
Significant Differences from
Hardware Specification
CPU
Frequency
(MHz)
1
Part No.
T
J
V
DD
(°C)
MPC8245ARZU400D
MPC8245ARVV400D
Modified voltage and temperature
specifications to achieve 400 MHz
400
2.1 100 mV
0 to 85
0x80811014
Note:
The ‘A’ in the part number represents parts that are manufactured under a 29-angstrom process instead of the original
35-angstrom process. Package Options: ZU - TBGA, V V- Lead Free TBGA
4 Electrical and Thermal Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the
MPC8245.
4.1.1 Absolute Maximum Ratings
The tables in this section describe the MPC8245 DC electrical characteristics. Table 1 provides the
absolute maximum ratings.
Table 1. Absolute Maximum Ratings
1
Characteristic
Symbol
Range
Unit
Supply voltage—CPU core and peripheral logic
Supply voltage—memory bus drivers
Supply voltage—PCI and standard I/O buffers
Supply voltage—PLLs
V
–0.3 to 2.2
–0.3 to 3.6
–0.3 to 3.6
–0.3 to 2.2
–0.3 to 5.4
–0.3 to 3.6
0 to 85
V
V
DD
GV
OV
DD
DD
V
AV /AV
2
DD
V
DD
Supply voltage—PCI reference
LV
V
V
DD
in
2
Input voltage
V
Operational die-junction temperature range
Storage temperature range
Notes:
T
°C
°C
j
T
–55 to 150
stg
1. Table 2 shows functional and tested operating conditions. Absolute maximum ratings are stress ratings only, and functional
operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause permanent
damage to the device.
2. PCI inputs with LV = 5 V 5ꢀ V DC may undergo corresponding stress at voltages exceeding LV + 0.5 V DC.
DD
DD
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
Freescale Semiconductor
2
Electrical and Thermal Characteristics
4.1.2 Recommended Operating Conditions
Table 2 provides the recommended operating conditions for the MPC8245 part numbers described herein.
(1)
Table 2. Recommended Operating Conditions
Recommended
Characteristic
Symbol
Value for
Unit
400 MHz CPU
Supply voltage
V
2.1 V 100 mV
2.1 V 100 mV
2.1 V 100 mV
0 to 85
V
V
DD
CPU PLL supply voltage
AV
DD
PLL supply voltage—peripheral logic
AV
2
V
DD
(2)
Die-junction temperature
T
°C
j
Notes:
1. Freescale tested these operating conditions and recommends them. Proper device operation outside of these conditions is
not guaranteed.
2. For information about the thermal characteristics of this part, refer to the MPC8245 Integrated Processor Hardware
Specifications. Note that the lower die-junction temperature creates a greater need to use a heat sink with this part.
4.1.5 Power Characteristics
The AC electrical characteristics and AC timing for the parts described in this document are unaffected,
and comply with the MPC8245 Integrated Processor Hardware Specifications. Table 5 provides the power
consumption for the MPC8245 part numbers described herein.
Table 5. Power Consumption
PCI Bus Clock/Memory
Bus Clock
CPU Clock Frequency
Mode
Unit
Notes
(MHz)
66/133/399
Typical
Max—CFP
Max—INT
Doze
2.8
3.3
2.8
1.9
0.7
0.4
W
W
W
W
W
W
1, 5
1, 2
1, 3
1, 4, 6
1, 4, 6
1, 4, 6
Nap
Sleep
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
Freescale Semiconductor
3
Electrical and Thermal Characteristics
Table 5. Power Consumption (continued)
PCI Bus Clock/Memory
Bus Clock
CPU Clock Frequency
(MHz)
Mode
Unit
Notes
66/133/399
10
I/O Power Supplies
Mode
Range
Unit
Notes
Typ—OV
Typ—GV
Notes:
140–360
mW
7, 8
DD
340–920
mW
7, 9
DD
1. The values include V , AV , and AV 2, but do not include I/O supply power.
DD
DD
DD
2. Maximum—FP power is measured at V = 2.1 V with dynamic power management enabled while running an entirely
DD
cache-resident, looping, floating point multiplication instruction.
3. Maximum—INT power is measured at V = 2.1 V with dynamic power management enabled while running entirely
DD
cache-resident, looping, integer instructions.
4. Power saving mode maximums are measured at V = 2.1 V while the device is in doze, nap, or sleep mode.
DD
5. Typical power is measured at V = AV = 2.1 V, OV = 3.3 V where a nominal FP value, a nominal INT value, and a
DD
DD
DD
value where there is a continuous flush of cache lines with alternating ones and zeros on 64-bit boundaries to local memory
are averaged.
6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled.
7. The typical minimum I/O power values was the result of the MPC8245 performing cache resident integer operations at the
slowest frequency combination of 33:66:200 (PCI:Mem:CPU) MHz.
8. The typical maximum OV value resulted from the MPC8245 operating at the fastest frequency combination of 66:133:399
DD
(PCI:Mem:CPU) MHz for the 400-MHz part, and performing continuous flushes of cache lines with alternating ones and
zeros to PCI memory.
9. The typical maximum GV value resulted from the MPC8245 operating at the fastest frequency combination of
DD
66:133:399 (PCI:Mem:CPU) MHz for the 400-MHz part, and performing continuous flushes of cache lines with alternating
ones and zeros on 64-bit boundaries to local memory.
10. Power consumption of PLL supply pins (AV and AV 2) < 15 mW that the design guarantees but were not tested.
DD
DD
4.3.1 Clock AC Specifications
Figure 7 through Figure 10 show the DLL locking range loop delay vs. frequency of operation for
29 angstrom parts. These graphs define the areas of DLL locking for various modes. The gray areas show
where the DLL will lock.
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
4
Freescale Semiconductor
Electrical and Thermal Characteristics
Register settings that define each DLL mode are shown in Table 9.
Table 9. DLL Mode Definition
Value of Bit 2 of Config
Register at 0x76
Value of Bit 7 of Config
Register at 0x72
DLL Mode
Normal tap delay,
No DLL extend
0
0
1
1
0
1
0
1
Normal tap delay,
DLL extend
Max tap delay,
No DLL extend
Max tap delay,
DLL extend
The DLL_MAX_DELAY bit can lengthen the amount of time through the delay line. This is accomplished
by increasing the time between each of the 128 tap points in the delay line. Although this increased time
makes it easier to guarantee that the reference clock will be within the DLL lock range, it also means there
may be slightly more jitter in the output clock of the DLL, should the phase comparator shift the clock
between adjacent tap points. Refer to Freescale application note AN2164, MPC8245/MPC8241 Memory
Clock Design Guidelines:Part 1, for details about DLL modes and memory design.
The value of the current tap point once the DLL has locked can be determined by reading bits 6–0
(DLL_TAP_COUNT) of the DLL tap count register (DTCR, located at offset 0xE3). These bits store the
value (binary 0 through 127) of the current tap point and can indicate whether the DLL advances or
decrements as it maintains the DLL lock. Therefore, for evaluation purposes, DTCR can be read for all
DLL modes that support the T
value that is used for the trace length of SDRAM_SYNC_OUT to
loop
SDRAM_SYNC_IN. The DLL mode that provides the smallest tap point value seen in DTCR should be
used. This is because the bigger the tap point value, the more jitter that can be expected for clock signals.
Note that keeping a DLL mode that is locked below tap point 12 is not recommended.
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
Freescale Semiconductor
5
Electrical and Thermal Characteristics
30
25
20
15
10
N = 1
N = 2
7.5
0
1
2
3
4
5
T
Propagation Delay Time (ns)
loop
Figure 7. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 0
and Normal Tap Delay
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
6
Freescale Semiconductor
Electrical and Thermal Characteristics
30
25
20
15
N = 1
10
N = 2
7.5
0
1
2
3
4
5
T
Propagation Delay Time (ns)
loop
Figure 8. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 1
and Normal Tap Delay
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
Freescale Semiconductor
7
Electrical and Thermal Characteristics
30
25
20
15
10
N = 1
N = 2
7.5
0
1
2
3
4
5
T
Propagation Delay Time (ns)
loop
Figure 9. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 0
and Max Tap Delay
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
8
Freescale Semiconductor
Electrical and Thermal Characteristics
30
25
20
15
N = 1
N = 2
10
7.5
0
1
2
3
4
5
T
Propagation Delay Time (ns)
loop
Figure 10. DLL Locking Range Loop Delay vs. Frequency of Operation for DLL_Extend = 1
and Max Tap Delay
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
Freescale Semiconductor
9
PLL Configuration
6 PLL Configuration
The MPC8245 internal PLLs are configured by the PLL_CFG[0:4] signals. For a given PCI_SYNC_IN
(PCI bus) frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO)
frequency of operation for the PCI-to-memory frequency multiplying and the MPC603e CPU PLL (VCO)
frequency of operation for memory-to-CPU frequency multiplying. The PLL configurations for the
400-MHz parts are shown in Table 18.
Table 18. PLL Configurations for the 400-MHz Part Offering
9
400-MHz Part
Multipliers
Periph
Logic/Mem CPU Clock
Bus Clock
Range
(MHz)
PLL_CFG
[0:4]
PCI Clock Input
Ref
11,14,15
(PCI_SYNC_IN)
PCI-to-Mem Mem-to-CPU
Range
(MHz)
1
Range
(Mem VCO)
(CPU VCO)
(MHz)
2
0
00000
00001
25–44
75–132
75–132
50–66
188–330
225–396
225–297
100–133
100–184
3 (2)
3 (2)
2.5 (2)
3 (2)
5
1
25–44
13
9
1
1
2
00010
50 –66
1 (4)
4.5 (2)
2 (4)
16
8
3
00011
50 –66
50–66
1 (Bypass)
2 (4)
4
4
00100
25–46
50–92
2 (4)
17
6
00110
Bypass
60–66
Bypass
1 (Bypass)
4 (2)
Bypass
3 (2)
6
1
7 (Rev. B)
00111
60 –66
180–198
350–392
180–198
180–264
225–396
204–297
180–230
238–347
180–276
263–399
180–264
250–330
180–198
300–396
182–329
272–400
200–368
13
5
7 (Rev. D)
00111
25–28
100–112
60–66
3.5 (2)
3 (2)
6
1
1
8
9
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
60 –66
1 (4)
6
45 –66
90–132
50–88
2 (2)
2 (2)
5
A
25–44
2 (4)
4.5 (2)
3 (2)
3
1
4
1
4
B
45 –66
68–99
1.5 (2)
2 (4)
6
C
36 –46
72–92
2.5 (2)
3.5 (2)
3 (2)
3
D
45 –66
68–99
1.5 (2)
2 (4)
6
E
30 –46
60–92
5
F
25–38
30–44
75–114
60–132
100–132
90–99
3 (2)
3.5 (2)
2 (2)
2
10
11
12
13
14
15
16
3 (2)
2
25–33
4 (2)
2.5 (2)
2 (2)
6
1
60 –66
1.5 (2)
4 (2)
5
25–33
100–132
52–94
3 (2)
6
4
5
26 –47
2 (4)
3.5 (2)
4 (2)
3
27 –40
68–100
50–92
2.5 (2)
2 (4)
4
25–46
4 (2)
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
Freescale Semiconductor
10
PLL Configuration
Table 18. PLL Configurations for the 400-MHz Part Offering (continued)
9
400-MHz Part
Multipliers
Periph
Logic/Mem CPU Clock
Bus Clock
Range
(MHz)
PLL_CFG
[0:4]
PCI Clock Input
Ref
11,14,15
(PCI_SYNC_IN)
PCI-to-Mem Mem-to-CPU
Range
(MHz)
1
Range
(Mem VCO)
(CPU VCO)
(MHz)
2
17
10111
11000
11001
11010
25–33
100–132
68–132
72–132
50–66
200–264
204–396
180–330
200–264
204–396
198–297
180–248
4 (2)
2.5 (2)
2 (2)
1 (4)
2 (2)
1.5 (2)
1.5 (2)
Off
2 (2)
3 (2)
2.5 (2)
4 (2)
3 (2)
3 (2)
2.5 (2)
Off
3
5
1
1
1
1
1
18
27 –53
6
19
1A
36 –66
9
50 –66
13
3
1B
11011
34 –66
68–132
6
1C
11100
11101
44 –66
66–99
6
1D
48 –66
72–99
10
1E (Rev. B)
1E (Rev. D)
1F
11110
Not usable
66–114
Not usable
3
5
11110
33 –57
231–399
2 (2)
Off
3.5 (2)
Off
10
11111
Notes:
1. Limited by maximum PCI input frequency (66 MHz).
2. Limited by maximum system memory interface operating frequency (133 MHz).
3. Limited by minimum memory VCO frequency (132 MHz).
4. Limited due to maximum memory VCO frequency (372 MHz).
5. Limited by maximum CPU operating frequency (400 MHz).
6. Limited by minimum CPU VCO frequency (360 MHz).
7. Limited by maximum CPU VCO frequency (800 MHz).
8. Limited by minimum CPU operating frequency (100 MHz).
9. Limited by minimum memory bus frequency (50 MHz).
10. In clock off mode, no clocking occurs inside the MPC8245, regardless of the PCI_SYNC_IN input.
11. Range values are shown rounded down to the nearest whole number (decimal place accuracy removed) for
clarity.
12. PLL_CFG[0:4] settings that are not listed are reserved.
13. Multiplier ratios for this PLL_CFG[0:4] setting are different from the MPC8240 and are not
backwards-compatible.
14. PCI_SYNC_IN range for this PLL_CFG[0:4] setting is different from the MPC8240 and may not be fully
backwards-compatible.
15. Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.
16. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral
logic PLL is disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is intended for
hardware modeling support. The AC timing specifications given in this document do not apply in the PLL
bypass mode.
17. In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the
peripheral logic PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In
this mode, the OSC_IN input signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode
operation, and the processor PLL is disabled. The PCI_SYNC_IN and OSC_IN input clocks must be
externally synchronized. This mode is intended for hardware modeling support. The AC timing specifications
given in this document do not apply in the dual PLL bypass mode.
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
Freescale Semiconductor
11
Ordering Information
9 Ordering Information
Ordering information for the parts covered in this document is provided in Section 9.1, “Part Numbers
Fully Addressed by This Document.” Section 9.3, “Part Marking,” addresses the marking specifications.
9.1
Part Numbers Fully Addressed by This Document
Table 21 provides the ordering information for the MPC8245 parts described herein. Note that the
individual part numbers correspond to a maximum processor core frequency.
Table 23. Part Numbers Addressed by This Document.
MPC nnnn
X
xx
nnn
x
X
Processor
Version
Register
Value
3
Product
Code
Part
Process
Process
Descriptor
Processor
Frequency
1
Package
Revision Level
2
Identifier Identifier
MPC
8245
A
R: 0° to 85°C ZU = TBGA
400 MHz
2.1 V 100 mV
D:1.4 Rev ID:0x14
0x80811014
V V= Lead-free
TBGA
Notes:
1. See Section 5, “Package Description,” for more information on available package types.
2. Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by part number specifications may support other
maximum core frequencies.
3. Process identifier ‘A’ represents parts that are manufactured under a 29-angstrom process verses the original
35-angstrom process.
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
12
Freescale Semiconductor
Document Revision History
9.3 Part Marking
Parts are marked as in the example shown in Figure 33.
MPC8245ARXXnnnx
ATWLYYWW
CCCCC
MMMMMM
YWWLAZ
Notes:
MMMMMM is the 6-digit mask number.
ATWLYYWW is Test traceability code.
YWWLAZ is the Assembly traceability code.
CCCCC is the country code.
Figure 33. Freescale Part Marking for TBGA Device
2 Document Revision History
Table B provides a revision history for this part number specification.
Table B Document Revision History
Rev. No.
Date
Substantive Change(s)
3
12/05
• Changed Document ID from MPC8245ARUPNS to MPC8245ECS02AD.
• Changed title of document from MPC8245 Part Number Specification for the MPC8245ARZUnnnX
Series” to the “MPC8245 Hardware Specification Addendum for the MPC8245ARXXnnnx Series.”
• Table A and Table 23 were updated to reflect current part offerings for the part.
• Removed Section 2, “Features” and Section 3, “.General Parameters.”
• Added Section 4, “Electrical and Thermal Characteristics.” heading and introduction.
• Remove all 466 MHz specific information as this part is not available for new orders. Section 4.3.3
was removed because it was specific to the 466 MHz part.
• Figure 33 was updated to reflect current part marking format.
2
07/12/04 • Updated to Freescale template.
• Updated section numbers to accurately reflect hardware specifications sections.
• Changed junction temperature range in Table 1 to reflect range depicted in Table A (0° to 85°C).
• Added Section 4.3.1 to illustrate DLL locking graphs for 29 angstrom parts (400- and 466-MHz parts).
1.0
• Added to list of parts covered by this document, including the non-A process identifier parts. Updated
Table A and Table 20.
• Nontechnical reformatting.
0.1
0
Minor edit to part number.
Original release.
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
Freescale Semiconductor
13
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
Freescale Semiconductor
14
Document Revision History
THIS PAGE INTENTIONALLY LEFT BLANK
MPC8245 Hardware Specifications Addendum for the MPC8245ARXXnnnx Series, Rev. 3
Freescale Semiconductor
15
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Document Number: MPC8245ECS02AD
Rev. 3
12/2005
相关型号：
MPC8245LVV333D
32-BIT, 333MHz, RISC PROCESSOR, PBGA352, 35 X 35 MM, 1.65 MM HEIGHT, 1.27 MM PITCH, LEAD FREE, TBGA-352
NXP
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