MPC8245LZU350D_技术文档

MPC8245EC

Rev. 10, 08/2007

Freescale Semiconductor

Technical Data

MPC8245 Integrated Processor

Hardware Specifications

Contents

The MPC8245 combines a PowerPC™ MPC603e processor

core built on Power Architecture™ technology with a PCI

bridge so that system designers can rapidly design systems

using peripherals designed for PCI and the other standard

interfaces. Also, a high-performance memory controller

supports various types of ROM and SDRAM. The MPC8245

is the second of a family of products that provide

system-level support for industry-standard interfaces with an

MPC603e processor core.

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

3. General Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4. Electrical and Thermal Characteristics . . . . . . . . . . . . 5

5. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 31

6. PLL Configurations . . . . . . . . . . . . . . . . . . . . . . . . . 39

7. System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

8. Document Revision History . . . . . . . . . . . . . . . . . . . 56

9. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 62

This hardware specification describes pertinent electrical

and physical characteristics of the MPC8245. For functional

characteristics of the processor, refer to the MPC8245

Integrated Processor Reference Manual (MPC8245UM).

For published errata or updates to this document, visit the

website listed on the back cover of the document.

1 Overview

The MPC8245 integrated processor is composed of a

peripheral logic block and a 32-bit superscalar MPC603e

core, as shown in Figure 1.

Overview

MPC8245

Processor Core Block

(64-Bit) Two-Instruction Fetch

Additional Features:

• Prog I/O with Watchpoint

• JTAG/COP Interface

• Power Management

Processor

PLL

Branch

Processing

Unit

Instruction Unit

(BPU)

(64-Bit) Two-Instruction Dispatch

System

Register

Unit

Floating-

Integer

Unit

(IU)

Load/Store

Point

Unit

(FPU)

(LSU)

(SRU)

64-Bit

Data

MMU

Instruction

MMU

16-Kbyte

Data

Cache

16-Kbyte

Instruction

Cache

Peripheral Logic Bus

Peripheral Logic Block

Data Bus

Data (64-Bit)

Address

(32-Bit)

Data Path

(32- or 64-Bit)

with 8-Bit Parity

or ECC

ECC Controller

Message

Unit

(with I O)

2

Central

Control

Unit

Memory

Controller

Memory/ROM/

PortX Control/Address

DMA

Controller

Performance

Monitor

SDRAM_SYNC_IN

SDRAM Clocks

2

I C

Controller

DLL

Peripheral Logic

PLL

PCI_SYNC_IN

PIC

5 IRQs/

16 Serial

Interrupts

Interrupt

Controller/

Timers

Configuration

Registers

PCI Bus

Interface Unit

DUART

Address

Translator

PCI

Arbiter

Watchpoint

Facility

Fanout

Buffers

PCI Bus

Clocks

Five

Request/Grant Pairs

32-Bit

PCI Interface

OSC_IN

Figure 1. MPC8245 Block Diagram

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

2

Freescale Semiconductor

Features

The peripheral logic integrates a PCI bridge, dual universal asynchronous receiver/transmitter (DUART),

memory controller, DMA controller, PIC interrupt controller, a message unit (and I₂O interface), and an

I²C controller. The processor core is a full-featured, high-performance processor with floating-point

support, memory management, a 16-Kbyte instruction cache, a 16-Kbyte data cache, and power

management features. The integration reduces the overall packaging requirements and the number of

discrete devices required for an embedded system.

An internal peripheral logic bus interfaces the processor core to the peripheral logic. The core can operate

at a variety of frequencies, allowing the designer to trade off performance for power consumption. The

processor core is clocked from a separate PLL that is referenced to the peripheral logic PLL. This allows

the microprocessor and the peripheral logic block to operate at different frequencies while maintaining a

synchronous bus interface. The interface uses a 64- or 32-bit data bus (depending on memory data bus

width) and a 32-bit address bus along with control signals that enable the interface between the processor

and peripheral logic to be optimized for performance. PCI accesses to the MPC8245 memory space are

passed to the processor bus for snooping when snoop mode is enabled.

The general-purpose processor core and peripheral logic serve a variety of embedded applications. The

MPC8245 can be used as either a PCI host or PCI agent controller.

2 Features

Major features of the MPC8245 are as follows:

•

Processor core

— High-performance, superscalar processor core

— Integer unit (IU), floating-point unit (FPU) (software enabled or disabled), load/store unit

(LSU), system register unit (SRU), and branch processing unit (BPU)

— 16-Kbyte instruction cache

— 16-Kbyte data cache

— Lockable L1 caches—Entire cache or on a per-way basis up to three of four ways

— Dynamic power management: 60x nap, doze, and sleep modes

Peripheral logic

•

— Peripheral logic bus

– Various operating frequencies and bus divider ratios

– 32-bit address bus, 64-bit data bus

– Full memory coherency

– Decoupled address and data buses for pipelining of peripheral logic bus accesses

– Store gathering on peripheral logic bus-to-PCI writes

— Memory interface

– Up to 2 Gbytes of SDRAM memory

– High-bandwidth data bus (32- or 64-bit) to SDRAM

– Programmable timing supporting SDRAM

– One to eight banks of 16-, 64-, 128-, 256-, or 512-Mbit memory devices

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

3

Features

– Write buffering for PCI and processor accesses

– Normal parity, read-modify-write (RMW), or ECC

– Data-path buffering between memory interface and processor

– Low-voltage TTL logic (LVTTL) interfaces

– 272 Mbytes of base and extended ROM/Flash/PortX space

– Base ROM space for 8-bit data path or same size as the SDRAM data path (32- or 64-bit)

– Extended ROM space for 8-, 16-, 32-bit gathering data path, 32- or 64-bit (wide) data path

– PortX: 8-, 16-, 32-, or 64-bit general-purpose I/O port using ROM controller interface with

programmable address strobe timing, data ready input signal (DRDY), and 4 chip selects

— 32-bit PCI interface

– Operates up to 66 MHz

– PCI 2.2-compatible

– PCI 5.0-V tolerance

– Dual address cycle (DAC) for 64-bit PCI addressing (master only)

– Accesses to PCI memory, I/O, and configuration spaces

– Selectable big- or little-endian operation

– Store gathering of processor-to-PCI write and PCI-to-memory write accesses

– Memory prefetching of PCI read accesses

– Selectable hardware-enforced coherency

– PCI bus arbitration unit (five request/grant pairs)

– PCI agent mode capability

– Address translation with two inbound and outbound units (ATU)

– Internal configuration registers accessible from PCI

— Two-channel integrated DMA controller (writes to ROM/PortX not supported)

– Direct mode or chaining mode (automatic linking of DMA transfers)

– Scatter gathering—Read or write discontinuous memory

– 64-byte transfer queue per channel

– Interrupt on completed segment, chain, and error

– Local-to-local memory

– PCI-to-PCI memory

– Local-to-PCI memory

– PCI memory-to-local memory

— Message unit

– Two doorbell registers

– Two inbound and two outbound messaging registers

– I₂O message interface

— I²C controller with full master/slave support that accepts broadcast messages

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

4

Freescale Semiconductor

General Parameters

— Programmable interrupt controller (PIC)

– Five hardware interrupts (IRQs) or 16 serial interrupts

– Four programmable timers with cascade

— Two (dual) universal asynchronous receiver/transmitters (UARTs)

— Integrated PCI bus and SDRAM clock generation

— Programmable PCI bus and memory interface output drivers

System-level performance monitor facility

•

Debug features

— Memory attribute and PCI attribute signals

— Debug address signals

— MIV signal—Marks valid address and data bus cycles on the memory bus

— Programmable input and output signals with watchpoint capability

— Error injection/capture on data path

— IEEE Std 1149.1® (JTAG)/test interface

3 General Parameters

The following list summarizes the general parameters of the MPC8245:

Technology

Die size

0.25-µm CMOS, five-layer metal

49.2 mm²

Transistor count

Logic design

Packages

4.5 million

Fully-static

Surface-mount 352 tape ball grid array (TBGA)

Core power supply 1.7 V to 2.1 V DC for 266 and 300 MHz with the condition that the usage

is “nominal” ± 100 mV where “nominal” is 1.8/1.9/2.0 volts.

1.9 V to 2.2 V DC for 333 and 350 MHz with the condition that the usage

is “nominal” ± 100 mV where “nominal” is 2.0/2.1 volts.

See Table 2 for details of recommended operating conditions)

I/O power supply

3.0- to 3.6-V DC

4 Electrical and Thermal Characteristics

This section provides the AC and DC electrical specifications and thermal characteristics for the

MPC8245.

4.1

DC Electrical Characteristics

This section covers ratings, conditions, and other DC electrical characteristics.

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

5

Electrical and Thermal Characteristics

4.1.1

Absolute Maximum Ratings

The tables in this section describe the MPC8245 DC electrical characteristics. Table 1 provides the

absolute maximum ratings.

Table 1. Absolute Maximum Ratings

1

Characteristic

Symbol

Range

Unit

Supply voltage—CPU core and peripheral logic

Supply voltage—memory bus drivers

Supply voltage—PCI and standard I/O buffers

Supply voltage—PLLs

V

–0.3 to 2.25

–0.3 to 3.6

–0.3 to 2.25

V

DD

GV

OV

DD

AV /AV

DD

2

Supply voltage—PCI reference

LV

V

–0.3 to 5.4

–0.3 to 3.6

V

DD

in

2

Input voltage

3

Operational die-junction temperature range

Storage temperature range

Notes:

T

0 to 105

°C

j

T

–55 to 150

stg

1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and

functional operation at the maximums is not guaranteed. Stress beyond those listed may affect device reliability or cause

permanent damage to the device.

2. PCI inputs with LV = 5 V ± 5% V DC may be correspondingly stressed at voltages exceeding LV + 0.5 V DC.

DD

3. Note that this temperature range does not apply to the 400 MHz parts. For details, refer to the hardware specifications

addendum MPC8245ECSO2AD.

4.1.2

Recommended Operating Conditions

Table 2 provides the recommended operating conditions for the MPC8245. Some voltage values do not

apply to the 400-MHz parts. For details, refer to the hardware specifications addendum

MPC8245ECSO2AD.

1

Table 2. Recommended Operating Conditions

Recommended

Characteristic

Symbol

Unit

Notes

Value

Supply voltage

V

1.8/1.9/2.0 V ±

100 mV

V

4, 7

DD

2.0/2.1 V ±

100 mV

V

5, 7

I/O buffer supply for PCI and standard

Supply voltages for memory bus drivers

CPU PLL supply voltage

OV

GV

AV

3.3 ± 0.3

3.3 ± 5%

V

7

DD

9

DD

1.8/1.9/2.0 V ±

2.0/2.1 V ±

4, 7, 12

5, 7, 12

DD

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

6

Freescale Semiconductor

Electrical and Thermal Characteristics

1

Table 2. Recommended Operating Conditions (continued)

Recommended

Value

Characteristic

PLL supply voltage—peripheral logic

Symbol

AV

Unit

Notes

2

1.8/1.9/2.0 V ±

2.0/2.1 V ±

5.0 ± 5%

V

4, 7, 12

5, 7, 12

2, 10, 11

3, 10, 11

2, 3

DD

PCI reference

Input voltage

LV

V

DD

3.3 ± 0.3

V

PCI inputs

0 to 3.6 or 5.75

0 to 3.6

V

in

All other inputs

V

6

Die-junction temperature

T

0 to 105

°C

j

Notes:

1. These are the recommended and tested operating conditions. Proper device operation outside of these conditions is not

guaranteed.

2. PCI pins are designed to withstand LV + 5% V DC when LV is connected to a 5.0-V DC power supply.

DD

3. PCI pins are designed to withstand LV + 0.5 V DC when LV is connected to a 3.3-V DC power supply.

DD

4. The voltage supply value of 1.8/1.9/2.0 V ± 100 mV applies to parts marked as having a maximum CPU speed of 266 and

300 MHz. See Table 7. For each chosen nominal value (1.8/1.9/2.0 V) the supply voltage should not exceed ± 100 mV of

the nominal value.

5. The voltage supply value of 2.0/2.1 V ± 100 m V applies to parts marked as having a maximum CPU speed of 333 and 350

MHz. See Table 7. For each chosen nominal value (2.0/2.1 V) the supply voltage should not exceed ± 100 mV of the nominal

value.

Cautions:

6. Input voltage (V ) must not be greater than the supply voltage (V /AV /AV 2) by more than 2.5 V at all times, including

in

DD

during power-on reset. Input voltage (V ) must not be greater than GV /OV by more than 0.6 V at all times, including

in

DD

during power-on reset.

7. OV must not exceed V /AV /AV 2 by more than 1.8 V at any time, including during power-on reset. This limit may

DD

be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

8. V /AV /AV 2 must not exceed OV by more than 0.6 V at any time, including during power-on reset. This limit may

DD

be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

9. GV must not exceed V /AV /AV 2 by more than 1.8 V at any time, including during power-on reset. This limit may

DD

be exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

10.LV must not exceed V /AV /AV 2 by more than 5.4 V at any time, including during power-on reset. This limit may be

DD

exceeded for a maximum of 20 ms during power-on reset and power-down sequences.

11. LV must not exceed OV by more than 3.0 V at any time, including during power-on reset. This limit may be exceeded

DD

for a maximum of 20 ms during power-on reset and power-down sequences.

12.This voltage is the input to the filter discussed in Section 7.1, “PLL Power Supply Filtering,” and not necessarily the voltage

at the AV pin, which may be reduced from V by the filter.

DD

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

7

Electrical and Thermal Characteristics

Figure 2 shows supply voltage sequencing and separation cautions.

LV @ 5 V

DD

5 V

11 10

See Note 1

3.3 V

2.0 V

11

OV /GV /(LV @ 3.3 V - - - -)

DD DD DD

10

7, 9

8

V

/AV /AV

2

DD

100 µs

PLL

V

Stable

DD

Relock

3

Time

0

6

Time

HRST_CPU,

PLL

HRST_CTRL

Asserted 255

External Memory

Clock Cycles

2

Power Supply Ramp Up

Reset

3

Configuration Pins

Nine External Memory

4

Clock Cycles Setup Time

HRST_CPU,

HRST_CTRL

VM = 1.4 V

Maximum Rise Time Must Be Less Than

5

One External Memory Clock Cycle

Notes:

1. Numbers associated with waveform separations correspond to caution numbers listed in Table 2.

2. See the Cautions section of Table 2 for details on this topic.

3. See Table 8 for details on PLL relock and reset signal assertion timing requirements.

4. Refer to Table 10 for additional information on reset configuration pin setup timing requirements.

5. HRST_CPU/HRST_CTRL must transition from a logic 0 to a logic 1 in less than one

SDRAM_SYNC_IN clock cycle for the device to be in the nonreset state.

6. PLL_CFG signals must be driven on reset and must be held for at least 25 clock cycles after the

negation of HRST_CTRL and HRST_CPU in order to be latched.

Figure 2. Supply Voltage Sequencing and Separation Cautions

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

8

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 3 shows the undershoot and overshoot voltage of the memory interface.

4 V

GV + 5%

DD

V

GV

IH

DD

GND

GND – 0.3 V

V

IL

GND – 1.0 V

Not to Exceed 10%

of t

SDRAM_CLK

Figure 3. Overshoot/Undershoot Voltage

Figure 4 and Figure 5 show the undershoot and overshoot voltage of the PCI interface for the 3.3- and 5-V

signals, respectively.

11 ns

(Min)

+7.1 V

Overvoltage

Waveform

7.1 V p-to-p

(Min)

0 V

4 ns

(Max)

4 ns

(Max)

62.5 ns

+3.6 V

Undervoltage

Waveform

7.1 V p-to-p

(Min)

–3.5 V

Figure 4. Maximum AC Waveforms for 3.3-V Signaling

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

9

Electrical and Thermal Characteristics

11 ns

(Min)

+11 V

0 V

Overvoltage

Waveform

11 V p-to-p

(Min)

4 ns

(Max)

4 ns

(Max)

62.5 ns

+5.25 V

Undervoltage

Waveform

10.75 V p-to-p

(Min)

–5.5 V

Figure 5. Maximum AC Waveforms for 5-V Signaling

4.2

DC Electrical Characteristics

Table 3 provides the DC electrical characteristics for the MPC8245 at recommended operating conditions.

Table 3. DC Electrical Specifications

At recommended operating conditions (see Table 2)

3

Characteristic

Input high voltage

Condition

Symbol

Min

Max

Unit

Notes

PCI only, except

PCI_SYNC_IN

V

0.65 × OV

LV

V

1

IH

DD

Input low voltage

Input high voltage

PCI only, except

PCI_SYNC_IN

V

—

0.3 × OV

V

IL

DD

All other pins, including

PCI_SYNC_IN

V

2.0

3.3

IH

(GV = 3.3 V)

DD

Input low voltage

All inputs, including

PCI_SYNC_IN

V

I

GND

—

0.8

V

IL

Input leakage current for pins using 0.5 V ≤ V ≤ 2.7 V

DRV_PCI driver

±70

µA

4

2

in

L

@ LV = 4.75 V

DD

Input leakage current for

all others

LV = 3.6 V

I

—

2.4

—

±10

—

µA

V

DD

GV ≤ 3.465 V

DD

Output high voltage

I

= driver-dependent

V

OH

(GV = 3.3 V)

DD

Output low voltage

I

= driver-dependent

V

0.4

V

OL

(GV = 3.3 V)

DD

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

10

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 3. DC Electrical Specifications (continued)

At recommended operating conditions (see Table 2)

3

Characteristic Condition

Symbol

Min

Max

Unit

Notes

Capacitance

Notes:

1. See Table 16 for pins with internal pull-up resistors.

V

= 0 V, f = 1 MHz

C

—

16.0

pF

in

2. See Table 4 for the typical drive capability of a specific signal pin based on the type of output driver associated with that pin

as listed in Table 16.

3. These specifications are for the default driver strengths indicated in Table 4.

4. Leakage current is measured on input and output pins in the high-impedance state. The leakage current is measured for

nominal OV /LV

and V or both OV /LV and V must vary in the same direction.

DD

DD,

DD DD DD DD

4.2.1

Output Driver Characteristics

Table 4 provides information on the characteristics of the output drivers referenced in Table 16. The values

are preliminary estimates from an IBIS model and are not tested.

5

Table 4. Drive Capability of MPC8245 Output Pins

Programmable

Supply

Driver Type

Output Impedance

I

Unit

Notes

OH

OL

Voltage

(Ω)

DRV_STD_MEM

20 (default)

40

OV = 3.3 V

36.6

18.6

12.0

6.1

18.0

9.2

mA

2, 4, 6

1, 3

DD

DRV_PCI

20

12.4

6.3

40 (default)

1, 3

DRV_MEM_CTRL

DRV_PCI_CLK

DRV_MEM_CLK

Notes:

6 (default)

GV = 3.3 V

89.0

36.6

18.6

42.3

18.0

9.2

2, 4

DD

20

40

2, 4

1. For DRV_PCI, I read from the IBIS listing in the pull-up mode, I(Min) column, at the 0.33-V label by interpolating between

OH

the 0.3- and 0.4-V table entries’ current values that correspond to the PCI V = 2.97 = 0.9 × OV (OV = 3.3 V) where

OH

DD

table entry voltage = OV – PCI V

.

DD

OH

2. For all others with GV or OV = 3.3 V, I read from the IBIS listing in the pull-up mode, I(Min) column, at the 0.9-V table

DD

OH

entry that corresponds to the V

= 2.4 V where table entry voltage = GV /OV – V

.

OH

DD

OH

3. For DRV_PCI, I read from the IBIS listing in the pull-down mode, I(Min) column, at 0.33 V = PCI V = 0 × OV (OV

DD

OL

DD

= 3.3 V) by interpolating between the 0.3- and 0.4-V table entries.

4. For all others with GV or OV = 3.3 V, I read from the IBIS listing in the pull-down mode, I(Min) column, at the 0.4-V

DD

OL

table entry.

5. See driver bit details for output driver control register (0x73) in the MPC8245 Integrated Processor Reference Manual.

6. See Chip Errata No. 19 in the MPC8245/MPC8241 RISC Microprocessor Chip Errata.

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

11

Electrical and Thermal Characteristics

4.3

Power Characteristics

Table 5 provides power consumption data for the MPC8245.

Table 5. Power Consumption

PCI Bus Clock/Memory Bus Clock/CPU Clock Frequency (MHz)

Mode

Unit Notes

66/66/266 66/133/266

66/66/300

66/100/300

33/83/333

66/133/333 66/100/350

Typical

Max—FP

Max—INT

Doze

1.7

(1.5)

2.0

(1.8)

1.8

(1.7)

2.0

(1.8)

2.0

2.3

2.8

2.4

1.6

0.7

0.4

2.2

2.8

2.4

1.5

0.6

0.3

W

1, 5

1, 2

2.2

(1.9)

2.4

(2.1)

2.3

(2.0)

2.5

(2.2)

2.6

2.2

1.4

0.5

1.8

(1.6)

2.1

(1.8)

2.0

(1.8)

2.1

(1.8)

1, 3

1.1

(1.0)

1.4

(1.3)

1.2

(1.1)

1.4

(1.3)

1, 4, 6

Nap

0.4

(0.4)

0.7

(0.7)

0.4

(0.4)

0.6

(0.6)

Sleep

0.2

0.4

0.2

0.3

(0.2)

(0.4)

(0.3)

10

I/O Power Supplies

Mode

Min

Max

Unit Notes

Typ—OV

Typ—GV

Notes:

134 (121)

334 (301)

mW

7, 8

7, 9

DD

324 (292)

800 (720)

1. The values include V , AV , and AV 2 but do not include I/O supply power. Information on OV and GV supply

DD

power is captured in the I/O power supplies section of this table. Values shown in parenthesis ( ) indicate power consumption

at V /AV /AV 2 = 1.8 V.

DD

2. Maximum—FP power is measured at V = 2.1 V with dynamic power management enabled while running an entirely

DD

cache-resident, looping, floating-point multiplication instruction.

3. Maximum—INT power is measured at V = 2.1 V with dynamic power management enabled while running entirely

DD

cache-resident, looping, integer instructions.

4. Power saving mode maximums are measured at V = 2.1 V while the device is in doze, nap, or sleep mode.

DD

5. Typical power is measured at V = AV = 2.0 V, OV = 3.3 V where a nominal FP value, a nominal INT value, and a

DD

value where there is a continuous flush of cache lines with alternating ones and zeros on 64-bit boundaries to local memory

are averaged.

6. Power saving mode data measured with only two PCI_CLKs and two SDRAM_CLKs enabled.

7. The typical minimum I/O power values were results of the MPC8245 performing cache resident integer operations at the

slowest frequency combination of 33:66:200 (PCI:Mem:CPU) MHz.

8. The typical maximum OV value resulted from the MPC8245 operating at the fastest frequency combination of 66:100:350

DD

(PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeros to PCI memory.

9. The typical maximum GV value resulted from the MPC8245 operating at the fastest frequency combination of 66:100:350

DD

(PCI:Mem:CPU) MHz and performing continuous flushes of cache lines with alternating ones and zeros on 64-bit boundaries

to local memory.

10.Power consumption of PLL supply pins (AV and AV 2) < 15 mW. Guaranteed by design and not tested.

DD

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

12

Freescale Semiconductor

Electrical and Thermal Characteristics

4.4

Thermal Characteristics

Table 6 provides the package thermal characteristics for the MPC8245. For details, see Section 7.8,

“Thermal Management.”

Table 6. Thermal Characteristics

Characteristic

Junction-to-ambient natural convection

Symbol

Value

Unit

Notes

R

16.1

°C/W

1, 2

JA

θ

(Single-layer board—1s)

Junction-to-ambient natural convection

(Four-layer board—2s2p)

R

12.0

11.6

9.0

°C/W

1, 3

JMA

θ

JMA

θ

JMA

θ

Junction-to-ambient (@200 ft/min)

(Single-layer board—1s)

R

Junction-to-ambient (@200 ft/min)

(Four layer board—2s2p)

Junction-to-board

R

4.8

1.8

1.0

°C/W

4

5

6

JB

JC

θ

Junction-to-case

R

θ

Junction-to-package top (natural convection)

Ψ_JT

Notes:

1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)

temperature, ambient temperature, airflow, power dissipation of other components on the board, and board thermal

resistance.

2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.

3. Per JEDEC JESD51-6 with the board horizontal.

4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on

the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method

1012.1) with the cold plate used for case temperature.

6. Thermal characterization parameter indicating the temperature difference between the package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written

as Psi-JT.

4.5

AC Electrical Characteristics

After fabrication, functional parts are sorted by maximum processor core frequency as shown in Table 7

and tested for conformance to the AC specifications for that frequency. The processor core frequency is

determined by the bus (PCI_SYNC_IN) clock frequency and the settings of the PLL_CFG[0:4] signals.

Parts are sold by maximum processor core frequency. See Section 9, “Ordering Information,” for details

on ordering parts.

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

13

Electrical and Thermal Characteristics

Table 7 provides the operating frequency information for the MPC8245 at recommended operating

conditions (see Table 2) with LV_DD= 3.3 V ± 0.3 V.

1

Table 7. Operating Frequency

266 MHz

300 MHz

333 MHz

350 MHz

2, 3

Characteristic

Unit

V

/AV /AV 2 = 1.8/1.9/2.0 V

V

DD

/AV /AV 2 = 2.0/2.1 V

DD

± 100 mV

Processor frequency (CPU)

Memory bus frequency

PCI input frequency

Notes:

100–266

50–133

100–300

100–333

50–133

100–350

MHz

4

50–100

25–66

1. For details, refer to the hardware specifications addendum MPC8245ECSO2AD.

2. Caution: The PCI_SYNC_IN frequency and PLL_CFG[0:4] settings must be chosen such that the resulting peripheral

logic/memory bus frequency and CPU (core) frequencies do not exceed their respective maximum or minimum operating

frequencies. Refer to the PLL_CFG[0:4] signal description in Section 6, “PLL Configurations,” for valid PLL_CFG[0:4] settings

and PCI_SYNC_IN frequencies.

3. See Table 17 and Table 18 for details on VCO limitations for memory and CPU VCO frequencies of various PLL

configurations.

4. No available PLL_CFG[0:4] settings support 133-MHz memory interface operation at 300- and 350-MHz CPU operation,

since the multipliers do not allow a 300:133 and 350:133 ratio relation. However, running these parts at slower processor

speeds may produce ratios that run above 100 MHz. See Table 17 for the PLL settings.

4.5.1

Clock AC Specifications

Table 8 provides the clock AC timing specifications at recommended operating conditions, as defined in

Section 4.5.2, “Input AC Timing Specifications.” These specifications are for the default driver strengths

indicated in Table 4.

Table 8. Clock AC Timing Specifications

At recommended operating conditions (see Table 2) with LV_DD= 3.3 V ± 0.3 V

Num

Characteristics and Conditions

Min

Max

Unit

Notes

1

Frequency of operation (PCI_SYNC_IN)

25

—

40

6

66

2.0

60

MHz

ns

%

2, 3 PCI_SYNC_IN rise and fall times

1

4

PCI_SYNC_IN duty cycle measured at 1.4 V

PCI_SYNC_IN pulse width high measured at 1.4 V

PCI_SYNC_IN pulse width low measured at 1.4 V

PCI_SYNC_IN jitter

5a

5b

7

9

ns

ps

µs

ns

2

6

9

—

200

250

190

100

8a

8b

10

15

PCI_CLK[0:4] skew (pin-to-pin)

SDRAM_CLK[0:3] skew (pin-to-pin)

Internal PLL relock time

3

2, 4, 5

6

DLL lock range with DLL_EXTEND = 0 (disabled)

and normal tap delay; (default DLL mode)

See Figure 7

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

14

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 8. Clock AC Timing Specifications (continued)

At recommended operating conditions (see Table 2) with LV_DD= 3.3 V ± 0.3 V

Num

Characteristics and Conditions

DLL lock range for other modes

Min

Max

Unit

Notes

16

17

See Figure 8 through Figure 10

ns

MHz

ns

6

Frequency of operation (OSC_IN)

OSC_IN rise and fall times

25

—

40

—

66

5

19

7

20

OSC_IN duty cycle measured at 1.4 V

OSC_IN frequency stability

60

100

%

21

ppm

Notes:

1. Rise and fall times for the PCI_SYNC_IN input are measured from 0.4 to 2.4 V.

2. Specification value at maximum frequency of operation.

3. Pin-to-pin skew includes quantifying the additional amount of clock skew (or jitter) from the DLL besides any intentional skew

added to the clocking signals from the variable length DLL synchronization feedback loop, that is, the amount of variance

between the internal sys_logic_clk and the SDRAM_SYNC_IN signal after the DLL is locked. While pin-to-pin skew between

SDRAM_CLKs can be measured, the relationship between the internal sys_logic_clk and the external SDRAM_SYNC_IN

cannot be measured and is guaranteed by design.

4. Relock time is guaranteed by design and characterization. Relock time is not tested.

5. Relock timing is guaranteed by design. PLL-relock time is the maximum amount of time required for PLL lock after a stable

V

and PCI_SYNC_IN are reached during the reset sequence. This specification also applies when the PLL has been

DD

disabled and subsequently re-enabled during sleep mode. Also note that HRST_CPU/HRST_CTRL must be held asserted

for a minimum of 255 bus clocks after the PLL-relock time during the reset sequence.

6. DLL_EXTEND is bit 7 of the PMC2 register <72>. N is a non-zero integer (see Figure 7 through Figure 10). T is the period

clk

of one SDRAM_SYNC_OUT clock cycle in ns. T

is the propagation delay of the DLL synchronization feedback loop (PC

loop

board runner) from SDRAM_SYNC_OUT to SDRAM_SYNC_IN in ns; 6.25 inches of loop length (unloaded PC board runner)

corresponds to approximately 1 ns of delay. For details about how Figure 7 through Figure 10 may be used refer to the

Freescale application note AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines, for details on MPC8245

memory clock design.

7. Rise and fall times for the OSC_IN input is guaranteed by design and characterization. OSC_IN input rise and fall times are

not tested.

Figure 6 shows the PCI_SYNC_IN input clock timing diagram with the labeled number items listed in

Table 8.

1

5a

5b

2

3

VM

PCI_SYNC_IN

VM = Midpoint Voltage (1.4 V)

Figure 6. PCI_SYNC_IN Input Clock Timing Diagram

Figure 7 through Figure 10 show the DLL locking range loop delay vs. frequency of operation. These

graphs define the areas of DLL locking for various modes. The gray areas show where the DLL locks.

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

15

Electrical and Thermal Characteristics

Register settings that define each DLL mode are shown in Table 9.

Table 9. DLL Mode Definition

Bit 2 of Configuration

DLL Mode

Bit 7 of Configuration

Register at 0x72

Register at 0x76

Normal tap delay,

No DLL extend

0

1

0

1

0

1

Normal tap delay,

DLL extend

Max tap delay,

No DLL extend

Max tap delay,

DLL extend

The DLL_MAX_DELAY bit can lengthen the amount of time through the delay line by increasing the

time between each of the 128 tap points in the delay line. Although this increased time makes it easier to

guarantee that the reference clock is within the DLL lock range, there may be slightly more jitter in the

output clock of the DLL; that is, the phase comparator shifts the clock between adjacent tap points. Refer

to the Freescale application note AN2164, MPC8245/MPC8241 Memory Clock Design Guidelines:

Part 1, for details on DLL modes and memory design.

The value of the current tap point after the DLL locks can be determined by reading bits 6–0

(DLL_TAP_COUNT) of the DLL tap count register (DTCR, located at offset 0xE3). These bits store the

value (binary 0 through 127) of the current tap point and can indicate whether the DLL advances or

decrements as it maintains the DLL lock. Therefore, for evaluation purposes, DTCR can be read for all

DLL modes that support the T_loopvalue used for the trace length of SDRAM_SYNC_OUT to

SDRAM_SYNC_IN. The DLL mode with the smallest tap point value in the DTCR should be used

because the bigger the tap point value, the more jitter that can be expected for clock signals. Note that

keeping a DLL mode that is locked below tap point decimal 12 is not recommended.

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

16

Freescale Semiconductor

Electrical and Thermal Characteristics

30

27.5

25

22.5

20

17.5

15

12.5

10

7.5

0

1

2

3

4

5

T

Propagation Delay Time (ns)

loop

Figure 7. DLL Locking Range Loop Delay Versus Frequency of Operation for DLL_Extend=0

and Normal Tap Delay

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

17

Electrical and Thermal Characteristics

30

27.5

25

22.5

20

17.5

15

12.5

10

7.5

0

1

2

3

4

5

T

Propagation Delay Time (ns)

loop

Figure 8. DLL Locking Range Loop Delay Versus Frequency of Operation for DLL_Extend=1

and Normal Tap Delay

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

18

Freescale Semiconductor

Electrical and Thermal Characteristics

30

27.5

25

22.5

20

17.5

15

12.5

10

7.5

0

1

2

3

4

5

T

Propagation Delay Time (ns)

loop

Figure 9. DLL Locking Range Loop Delay Versus Frequency of Operation for DLL_Extend=0

and Max Tap Delay

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

19

Electrical and Thermal Characteristics

30

27.5

25

22.5

20

17.5

15

12.5

10

7.5

0

1

2

3

4

5

T

Propagation Delay Time (ns)

loop

Figure 10. DLL Locking Range Loop Delay Versus Frequency of Operation for DLL_Extend=1

and Max Tap Delay

4.5.2

Input AC Timing Specifications

Table 10 provides the input AC timing specifications at recommended operating conditions (see Table 2)

with LV_DD= 3.3 V ± 0.3 V.

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

20

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 10. Input AC Timing Specifications

Characteristic

Num

10a

Min

Max

Unit

Notes

PCI input signals valid to PCI_SYNC_IN (input setup)

Memory input signals valid to sys_logic_clk (input setup)

3.0

—

ns

1, 3

10b

10b0 Tap 0, register offset <0x77>, bits 5–4 = 0b00

10b1 Tap 1, register offset <0x77>, bits 5–4 = 0b01

10b2 Tap 2, register offset <0x77>, bits 5–4 = 0b10 (default)

10b3 Tap 3, register offset <0x77>, bits 5–4 = 0b11

2.6

1.9

1.2

0.5

3.0

—

ns

2, 3, 6

10c

PIC, misc. debug input signals valid to sys_logic_clk

ns

2, 3

(input setup)

2

10d

10e

11

I C input signals valid to sys_logic_clk (input setup)

3.0

—

ns

2, 3

2, 3–5

7

Mode select inputs valid to HRST_CPU/HRST_CTRL (input setup)

9 × t

CLK

T —SDRAM_SYNC_IN to sys_logic_clk offset time

0.4

1.0

os

11a

sys_logic_clk to memory signal inputs invalid (input hold)

11a0 Tap 0, register offset <0x77>, bits 5–4 = 0b00

11a1 Tap 1, register offset <0x77>, bits 5–4 = 0b01

11a2 Tap 2, register offset <0x77>, bits 5–4 = 0b10 (default)

11a3 Tap 3, register offset <0x77>, bits 5–4 = 0b11

0

—

ns

2, 3, 6

0.7

1.4

2.1

0

11b

11c

HRST_CPU/HRST_CTRL to mode select inputs invalid (input hold)

PCI_SYNC_IN to Inputs invalid (input hold)

ns

2, 3, 5

1, 2, 3

1.0

Notes:

1. All PCI signals are measured from OV /2 of the rising edge of PCI_SYNC_IN to 0.4 × OV of the signal in question for

DD

3.3-V PCI signaling levels. See Figure 12.

2. All memory and related interface input signal specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in

question to the VM = 1.4 V of the rising edge of the memory bus clock, sys_logic_clk. sys_logic_clk is the same as

PCI_SYNC_IN in 1:1 mode but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every

rising and falling edge of PCI_SYNC_IN). See Figure 11.

3. Input timings are measured at the pin.

4. t

is the time of one SDRAM_SYNC_IN clock cycle.

CLK

5. All mode select input signals specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the

VM = 1.4 V of the rising edge of the HRST_CPU/HRST_CTRL signal. See Figure 13.

6. The memory interface input setup and hold times are programmable to four possible combinations by programming bits 5–4

of register offset <0x77> to select the desired input setup and hold times.

7. T represents a timing adjustment for SDRAM_SYNC_IN with respect to sys_logic_clk. Due to the internal delay present

os

on the SDRAM_SYNC_IN signal with respect to the sys_logic_clk inputs to the DLL, the resulting SDRAM clocks become

offset by the delay amount. To maintain phase-alignment of the memory clocks with respect to sys_logic_clk, the feedback

trace length of SDRAM_SYNC_OUT to SDRAM_SYNC_IN must be shortened to accommodate this range. The feedback

trace length is relative to the SDRAM clock output trace lengths. We recommend that the length of SDRAM_SYNC_OUT to

SDRAM_SYNC_IN be shortened by 0.7 ns because that is the midpoint of the range of T and allows the impact from the

os

range of T to be reduced. Additional analyses of trace lengths and SDRAM loading must be performed to optimize timing.

os

For details on trace measurements and the problem of T , refer to the Freescale application note AN2164,

os

MPC8245/MPC8241 Memory Clock Design Guidelines.

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

21

Electrical and Thermal Characteristics

Figure 11 and Figure 12 show the input/output timing diagrams referenced to SDRAM_SYNC_IN and

PCI_SYNC_IN, respectively.

VM

PCI_SYNC_IN

VM

sys_logic_clk

VM

T_os

SDRAM_SYNC_IN

(after DLL locks)

VM

Shown in 2:1 Mode

10b-d

13b

14b

11a

12b-d

2.0 V

Memory

Inputs/Outputs

0.8 V

Input Timing

Output Timing

Notes:

VM = Midpoint voltage (1.4 V).

10b-d = Input signals valid timing.

11a = Input hold time of SDRAM_SYNC_IN to memory.

12b-d = sys_logic_clk to output valid timing.

13b = Output hold time for non-PCI signals.

14b = SDRAM-SYNC_IN to output high-impedance timing for non-PCI signals.

T

= Offset timing required to align sys_logic_clk with SDRAM_SYNC_IN. The SDRAM_SYNC_IN signal

is adjusted by the DLL to accommodate for internal delay. This causes SDRAM_SYNC_IN to appear

before sys_logic_clk once the DLL locks.

os

Figure 11. Input/Output Timing Diagram Referenced to SDRAM_SYNC_IN

OV ÷ 2

PCI_SYNC_IN

DD

10a

13a

14a

12a

11c

0.615 × OV_DD

0.285 × OV_DD

PCI

Inputs/Outputs

0.4 × OV_DD

Input Timing

Output Timing

Figure 12. Input/Output Timing Diagram Referenced to PCI_SYNC_IN

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

22

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 13 shows the input timing diagram for mode select signals.

VM

HRST_CPU/HRST_CTRL

10e

11b

2.0 V

0.8 V

Mode Pins

VM = Midpoint Voltage (1.4 V)

Figure 13. Input Timing Diagram for Mode Select Signals

4.5.3

Output AC Timing Specification

Table 11 provides the processor bus AC timing specifications for the MPC8245 at recommended operating

conditions (see Table 2) with LV_DD= 3.3 V ± 0.3 V. See Figure 11 for the input/output timing diagram

referenced to sys_logic_clk. All output timings assume a purely resistive 50-Ω load (see Figure 14 for the

AC test load for the MPC8245). Output timings are measured at the pin; time-of-flight delays must be

added for trace lengths, vias, and connectors in the system. These specifications are for the default driver

strengths indicated in Table 4.

Table 11. Output AC Timing Specifications

Num

Characteristic

Min

Max

Unit

Notes

12a

PCI_SYNC_IN to output valid, see Figure 15

12a0 Tap 0, PCI_HOLD_DEL=00, [MCP,CKE] = 11, 66 MHz PCI (default)

12a1 Tap 1, PCI_HOLD_DEL=01, [MCP,CKE] = 10

—

6.0

6.5

7.0

7.5

4.0

7.0

5.0

6.0

ns

1, 3

12a2 Tap 2, PCI_HOLD_DEL=10, [MCP,CKE] = 01, 33 MHz PCI

12a3 Tap 3, PCI_HOLD_DEL=11, [MCP,CKE] = 00

12b

12c

12d

12e

13a

sys_logic_clk to output valid (memory control, address, and data signals)

sys_logic_clk to output valid (for all others)

ns

2

sys_logic_clk to output valid (for I C)

sys_logic_clk to output valid (ROM/Flash/PortX)

Output hold (PCI), see Figure 15

13a0 Tap 0, PCI_HOLD_DEL=00, [MCP,CKE] = 11, 66-MHz PCI (default)

13a1 Tap 1, PCI_HOLD_DEL=01, [MCP,CKE] = 10

2.0

2.5

3.0

3.5

1.0

—

ns

1, 3, 4

13a2 Tap 2, PCI_HOLD_DEL=10, [MCP,CKE] = 01, 33-MHz PCI

13a3 Tap 3, PCI_HOLD_DEL=11, [MCP,CKE] = 00

—

13b

14a

Output hold (all others)

—

ns

2

PCI_SYNC_IN to output high impedance (for PCI)

14.0

1, 3

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

23

Electrical and Thermal Characteristics

Table 11. Output AC Timing Specifications (continued)

Num

Characteristic

Min

Max

Unit

Notes

14b

sys_logic_clk to output high impedance (for all others)

—

4.0

ns

2

Notes:

1. All PCI signals are measured from GV /2 of the rising edge of PCI_SYNC_IN to 0.285 × OV or 0.615 × OV of the

DD

signal in question for 3.3 V PCI signaling levels. See Figure 12.

2. All memory and related interface output signal specifications are specified from the VM = 1.4 V of the rising edge of the

memory bus clock, sys_logic_clk to the TTL level (0.8 or 2.0 V) of the signal in question. sys_logic_clk is the same as

PCI_SYNC_IN in 1:1 mode, but is twice the frequency in 2:1 mode (processor/memory bus clock rising edges occur on every

rising and falling edge of PCI_SYNC_IN). See Figure 11.

3. PCI bused signals are composed of the following signals: LOCK, IRDY, C/BE[3:0], PAR, TRDY, FRAME, STOP, DEVSEL,

PERR, SERR, AD[31:0], REQ[4:0], GNT[4:0], IDSEL, and INTA.

4. To meet minimum output hold specifications relative to PCI_SYNC_IN for both 33- and 66-MHz PCI systems, the MPC8245

has a programmable output hold delay for PCI signals (the PCI_SYNC_IN to output valid timing is also affected). The initial

value of the output hold delay is determined by the values on the MCP and CKE reset configuration signals; the values on

these two signals are inverted and stored as the initial settings of PCI_HOLD_DEL = PMCR2[5, 4] (power management

configuration register 2 <0x72>), respectively. Since MCP and CKE have internal pull-up resistors, the default value of

PCI_HOLD_DEL after reset is 0b00. Further output hold delay values are available by programming the PCI_HOLD_DEL

value of the PMCR2 configuration register. Figure 15 shows the PCI_HOLD_DEL effect on output valid and hold times.

Figure 14 provides the AC test load for the MPC8245.

Output Measurements are Made at the Device Pin

OV /2 for PCI

DD

Z = 50 Ω

Output

0

GV /2 for Memory

DD

R = 50 Ω

L

Figure 14. AC Test Load for the MPC8245

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

24

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 15 provides the PCI_HOLD_DEL effect on output valid and hold times.

OV /2

DD

PCI_SYNC_IN

12a2, 7.0 ns for 33 MHz PCI

PCI_HOLD_DEL = 10

13a2, 2.1 ns for 33-MHz PCI

PCI_HOLD_DEL = 10

PCI Inputs/Outputs

33 MHz PCI

12a0, 6.0 ns for 66 MHz PCI

PCI_HOLD_DEL = 00

13a0, 1 ns for 66-MHz PCI

PCI_HOLD_DEL = 00

PCI Inputs/Outputs

66 MHz PCI

As PCI_HOLD_DEL

Values Decrease

PCI Inputs

and Outputs

As PCI_HOLD_DEL

Values Increase

Output Valid

Output Hold

Note: Diagram not to scale.

Figure 15. PCI_HOLD_DEL Effect on Output Valid and Hold Times

2

4.6

I C

This section describes the DC and AC electrical characteristics for the I²C interfaces of the MPC8245.

4.6.1

I²C DC Electrical Characteristics

Table 12 provides the DC electrical characteristics for the I²C interfaces.

2

Table 12. I C DC Electrical Characteristics

At recommended operating conditions with OV_DDof 3.3 V ± 5%.

Parameter

Input high voltage level

Symbol

Min

Max

Unit

Notes

V

0.7 × OV

–0.3

OV + 0.3

V

IH

DD

Input low voltage level

Low-level output voltage

V

0.3 × OV

IL

DD

V

0

0.2 × OV

1

OL

DD

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

25

Electrical and Thermal Characteristics

2

Table 12. I C DC Electrical Characteristics

At recommended operating conditions with OV_DDof 3.3 V ± 5%.

Pulse width of spikes which must be suppressed by

the input filter

t

0

50

10

ns

μA

pF

2

3

I2KHKL

Input current each I/O pin (input voltage is between

I

–10

—

I

0.1 × OV and 0.9 × OV (max)

DD

Capacitance for each I/O pin

C

I

Notes:

1. Output voltage (open drain or open collector) condition = 3 mA sink current.

2. Refer to the MPC8245 Integrated Processor Reference Manual for information on the digital filter used.

3. I/O pins obstruct the SDA and SCL lines if the OV is switched off.

DD

4.6.2

I²C AC Electrical Specifications

Table 13 provides the AC timing parameters for the I²C interfaces.

2

Table 13. I C AC Electrical Specifications

All values refer to V_IH(min) and V_IL(max) levels (see Table 12).

1

Parameter

Symbol

Min

Max

Unit

SCL clock frequency

f

0

400

—

kHz

μs

I2C

4

Low period of the SCL clock

High period of the SCL clock

t

1.3

0.6

I2CL

—

μs

I2CH

4

Setup time for a repeated START condition

t

—

μs

I2SVKH

Hold time (repeated) START condition (after this period, the first

clock pulse is generated)

t

—

μs

I2SXKL

4

Data setup time

t

100

—

ns

I2DVKH

Data input hold time:

t

μs

I2DXKL

—

CBUS compatible masters

2

0

I C bus devices

3

Data output delay time:

t

—

0.6

0.9

I2OVKL

Set-up time for STOP condition

t

—

μs

V

I2PVKH

Bus free time between a STOP and START condition

t

1.3

I2KHDX

Noise margin at the LOW level for each connected device (including

hysteresis)

V

0.1 × OV

NL

DD

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

26

Freescale Semiconductor

Electrical and Thermal Characteristics

2

Table 13. I C AC Electrical Specifications (continued)

All values refer to V_IH(min) and V_IL(max) levels (see Table 12).

1

Parameter

Symbol

Min

Max

Unit

Noise margin at the HIGH level for each connected device (including

hysteresis)

V

0.2 × OV

—

V

NH

DD

Note:

1. The symbols used for timing specifications follow the pattern of t

for

(first two letters of functional block)(signal)(state) (reference)(state)

2

inputs and t

for outputs. For example, t

symbolizes I C timing (I2)

(first two letters of functional block)(reference)(state)(signal)(state)

I2DVKH

with respect to the time data input signals (D) reach the valid state (V) relative to the t clock reference (K) going to the high

I2C

2

(H) state or setup time. Also, t

symbolizes I C timing (I2) for the time that the data with respect to the start condition

(S) went invalid (X) relative to the t clock reference (K) going to the low (L) state or hold time. Also, t

I2SXKL

2

symbolizes I C

I2C

I2PVKH

timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid state (V) relative to the t clock

I2C

reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention is used with the appropriate

letter: R (rise) or F (fall).

2. As a transmitter, the MPC8245 provides a delay time of at least 300 ns for the SDA signal (referred to as the Vihmin of the

SCL signal) to bridge the undefined region of the falling edge of SCL to avoid unintended generation of Start or Stop condition.

2

When the MPC8245acts as the I C bus master while transmitting, it drives both SCL and SDA. As long as the load on SCL

and SDA is balanced, the MPC8245 does not cause the unintended generation of a Start or Stop condition. Therefore, the

300 ns SDA output delay time is not a concern. If, under some rare condition, the 300 ns SDA output delay time is required

for the MPC8245 as transmitter, the following setting is recommended for the FDR bit field of the I2CFDR register to ensure

2

both the desired I C SCL clock frequency and SDA output delay time are achieved. It is assumed that the desired I C SCL

clock frequency is 400 KHz and the digital filter sampling rate register (DFFSR bits in I2CFDR) is programmed with its default

setting of 0x10 (decimal 16):

SDRAM Clock Frequency

FDR Bit Setting

100 MHz 133 MHz

0x00

384

0x2A

896

Actual FDR Divider Selected

2

Actual I C SCL Frequency Generated 260.4 KHz 148.4 KHz

2

For details on I C frequency calculation, refer to the application note AN2919 “Determining the I C Frequency Divider Ratio

for SCL”.

3. The maximum t

has only to be met if the device does not stretch the LOW period (t

) of the SCL signal.

I2CL

I2DXKL

4. Guaranteed by design.

Figure 16 provides the AC test load for the I²C.

OV /2

Output

Z = 50 Ω

0

DD

R = 50 Ω

L

2

Figure 16. I C AC Test Load

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

27

Electrical and Thermal Characteristics

Figure 17 shows the AC timing diagram for the I²C bus.

SDA

t

I2CF

I2DVKH

I2KHKL

t

I2CR

I2CL

I2SXKL

SCL

t

I2PVKH

I2SXKL

I2CH

I2SVKH

t

I2DXKL, I2OVKL

S

Sr

P

S

2

Figure 17. I C Bus AC Timing Diagram

4.7

PIC Serial Interrupt Mode AC Timing Specifications

Table 14 provides the PIC serial interrupt mode AC timing specifications for the MPC8245 at

recommended operating conditions (see Table 2) with GV_DD= 3.3 V ± 5% and LV_DD= 3.3 V ± 0.3 V.

Table 14. PIC Serial Interrupt Mode AC Timing Specifications

Num

Characteristic

S_CLK frequency

Min

Max

Unit

Notes

1

1/14 SDRAM_SYNC_IN

1/2 SDRAM_SYNC_IN

MHz

%

1

—

2

S_CLK duty cycle

40

60

3

S_CLK output valid time

—

6

ns

4

Output hold time

0

—

ns

5

S_FRAME, S_RST output valid time

S_INT input setup time to S_CLK

S_INT inputs invalid (hold time) to S_CLK

—

1 sys_logic_clk period + 6

ns

6

1 sys_logic_clk period + 2

—

0

ns

2

7

—

ns

2

Notes:

1. See the MPC8245 Integrated Processor Reference Manual for a description of the PIC interrupt control register (ICR) and

S_CLK frequency programming.

2. S_RST, S_FRAME, and S_INT shown in Figure 18 and Figure 19, depict timing relationships to sys_logic_clk and S_CLK

and do not describe functional relationships between S_RST, S_FRAME, and S_INT. The MPC8245 Integrated Processor

Reference Manual describes the functional relationships between these signals.

3. The sys_logic_clk waveform is the clocking signal of the internal peripheral logic from the output of the peripheral logic PLL;

sys_logic_clk is the same as SDRAM_SYNC_IN when the SDRAM_SYNC_OUT to SDRAM_SYNC_IN feedback loop is

implemented and the DLL is locked. See the MPC8245 Integrated Processor Reference Manual for a complete clocking

description.

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

28

Freescale Semiconductor

Electrical and Thermal Characteristics

VM

sys_logic_clk

3

4

VM

S_CLK

VM

5

4

S_FRAME

S_RST

VM

Figure 18. PIC Serial Interrupt Mode Output Timing Diagram

VM

S_CLK

S_INT

7

6

Figure 19. PIC Serial Interrupt Mode Input Timing Diagram

4.8

IEEE 1149.1 (JTAG) AC Timing Specifications

Table 15 provides the JTAG AC timing specifications for the MPC8245 while in the JTAG operating mode

at recommended operating conditions (see Table 2) with LV_DD= 3.3 V ± 0.3 V. Timings are independent

of the system clock (PCI_SYNC_IN).

Table 15. JTAG AC Timing Specification (Independent of PCI_SYNC_IN)

Num

Characteristic

TCK frequency of operation

Min

Max

Unit

Notes

0

40

20

0

25

—

3

MHz

ns

1

2

TCK cycle time

TCK clock pulse width measured at 1.5 V

TCK rise and fall times

3

4

TRST setup time to TCK falling edge

TRST assert time

10

5

—

30

—

1

5

6

Input data setup time

2

3

7

Input data hold time

15

0

8

TCK to output data valid

TCK to output high impedance

TMS, TDI data setup time

9

0

10

5

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

29

Electrical and Thermal Characteristics

Table 15. JTAG AC Timing Specification (Independent of PCI_SYNC_IN) (continued)

Num

Characteristic

Min

Max

Unit

Notes

11

12

TMS, TDI data hold time

TCK to TDO data valid

15

0

—

15

ns

13

TCK to TDO high impedance

0

Notes:

1. TRST is an asynchronous signal. The setup time is for test purposes only.

2. Nontest (other than TDI and TMS) signal input timing with respect to TCK.

3. Nontest (other than TDO) signal output timing with respect to TCK.

Figure 20 through Figure 23 show the different timing diagrams.

1

2

VM

TCK

3

VM = Midpoint Voltage

Figure 20. JTAG Clock Input Timing Diagram

TCK

4

TRST

5

Figure 21. JTAG TRST Timing Diagram

TCK

6

7

Data Inputs

Data Outputs

Input Data Valid

8

9

Output Data Valid

Figure 22. JTAG Boundary Scan Timing Diagram

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

30

Freescale Semiconductor

Package Description

TCK

10

11

TDI, TMS

Input Data Valid

12

13

TDO

Output Data Valid

Figure 23. Test Access Port Timing Diagram

5 Package Description

This section details package parameters, pin assignments, and dimensions.

5.1

Package Parameters

The MPC8245 uses a 35 mm × 35 mm, cavity-up, 352-pin tape ball grid array (TBGA) package. The

package parameters are as follows.

Package Outline

Interconnects

Pitch

35 mm × 35 mm

352

1.27 mm

Solder Balls

ZU (TBGA package)^—62 Sn/36 Pb/2 Ag

VV (Lead-free version of package)^—95.5 Sn/4.0 Ag/0.5 Cu

Solder Ball Diameter

0.75 mm

1.65 mm

Maximum Module Height

Co-Planarity Specification 0.15 mm

Maximum Force

6.0 lbs. total, uniformly distributed over package (8 grams/ball)

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

31

Package Description

5.2

Pin Assignments and Package Dimensions

Figure 24 shows the top surface, side profile, and pinout of the MPC8245, 352 TBGA package.

– F –

B

CORNER

– E –

– T –

0.150 T

A

MIN

34.8

1.45

.60

MAX

35.2

1.65

.90

A

B

C

D

G

H

K

L

Dot on top indicates

corner of A1 pin on

bottom

Top View

1.27 BASIC

.85 .95

31.75 BASIC

.50 .70

26 24 22 20 18 16 14 12 10 8

25 23 21 19 17 15 13 11

6

4

2

9

7

5

3

1

A

C

E

G

J

B

D

F

H

K

M

P

T

L

N

R

U

W

K

V

Y

AA

C

AB

AC

AD

AE

AF

H

L

Bottom View

G

352X ∅ D

K

Notes:

1. Drawing not to scale.

2. All measurements are in millimeters (mm).

Figure 24. MPC8245 Package Dimensions and Pinout Assignments

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

32

Freescale Semiconductor

Package Description

5.3

Pinout Listings

Table 16 provides the pinout listing for the MPC8245, 352 TBGA package.

Table 16. MPC8245 Pinout Listing

Power

Supply

Output

Driver Type

Name

Pin Numbers

Type

Notes

PCI Interface Signals

C/BE[3:0]

P25 K23 F23 A25

I/O

OV

DRV_PCI

—

6, 15

8, 15

8

DD

DEVSEL

FRAME

IRDY

H26

J24

K25

J26

I/O

LOCK

Input

AD[31:0]

V25 U25 U26 U24 U23 T25 T26

R25 R26 N26 N25 N23 M26 M25

L25 L26 F24 E26 E25 E23 D26

D25 C26 A26 B26 A24 B24 D19

B23 B22 D22 C22

I/O

DRV_PCI

6, 15

PAR

G25

I/O

Output

Input

I/O

OV

DRV_PCI

—

15

6, 15

DD

GNT[3:0]

GNT4/DA5

REQ[3:0]

REQ4/DA4

PERR

W25 W24 W23 V26

W26

7, 15, 14

6, 12

Y25 AA26 AA25 AB26

Y26

G26

F26

H25

K26

AC26

P26

—

12, 14

8, 15, 18

8, 15, 16

8, 15

I/O

DRV_PCI

—

SERR

I/O

STOP

I/O

TRDY

I/O

8, 15

INTA

Output

Input

10, 15, 16

IDSEL

Memory Interface Signals

MDL[0:31]

MDH[0:31]

AD17 AE17 AE15 AF15 AC14

I/O

GV

DRV_STD_MEM

5, 6

DD

AE13 AF13 AF12 AF11 AF10 AF9

AD8 AF8 AF7 AF6 AE5 B1 A1 A3

A4 A5 A6 A7 D7 A8 B8 A10 D10

A12 B11 B12 A14

AC17 AF16 AE16 AE14 AF14

AC13 AE12 AE11 AE10 AE9 AE8

AC7 AE7 AE6 AF5 AC5 E4 A2 B3

D4 B4 B5 D6 C6 B7 C9 A9 B10

A11 A13 B13 A15

I/O

GV

6

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

33

Package Description

Table 16. MPC8245 Pinout Listing (continued)

Power

Output

Driver Type

Name

Pin Numbers

Type

Notes

Supply

DQM[0:7]

AB1 AB2 K3 K2 AC1 AC2 K1 J1

Output

I/O

GV

OV

GV

OV

GV

DRV_MEM_CTRL

6 ohms

6

DD

CS[0:7]

Y4 AA3 AA4 AC4 M2 L2 M1 L1

6

FOE

H1

3, 4

RCS0

N4

Output

I/O

RCS1

N2

RCS2/TRIG_IN

RCS3/TRIG_OUT

SDMA[1:0]

SDMA[11:2]

DRDY

AF20

10, 14

14

AC18

Output

I/O

DRV_MEM_CTRL

—

W1 W2

3, 4, 6

6

N1 R1 R2 T1 T2 U4 U2 U1 V1 V3

Output

Input

I/O

B20

B16

B14

D14

9, 10

10, 14

SDMA12/SRESET

SDMA13/TBEN

DRV_MEM_CTRL

I/O

SDMA14/

I/O

CHKSTOP_IN

SDBA1

SDBA0

PAR[0:7]

SDRAS

SDCAS

CKE

P1

Output

I/O

GV

DRV_MEM_CTRL

DRV_STD_MEM

DRV_MEM_CTRL

DD

P2

AF3 AE3 G4 E2 AE4 AF4 D2 C2

6

3

AD1

AD2

H2

Output

3

3, 4

WE

AA1

Y1

AS

3, 4

PIC Control Signals

IRQ0/S_INT

IRQ1/S_CLK

IRQ2/S_RST

IRQ3/S_FRAME

IRQ4/L_INT

C19

Input

I/O

OV

—

DD

B21

DRV_PCI

AC22

AE24

A23

I/O

2

I C Control Signals

SDA

SCL

AE20

AF21

I/O

OV

DRV_STD_MEM

10, 16

DD

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

34

Freescale Semiconductor

Package Description

Table 16. MPC8245 Pinout Listing (continued)

Power

Output

Driver Type

Name

Pin Numbers

Type

Notes

Supply

DUART Control Signals

SOUT1/PCI_CLK0

SIN1/PCI_CLK1

AC25

AB25

AE26

Output

I/O

GV

DRV_MEM_CTRL

13, 14

13, 14, 26

13, 14

DD

SOUT2/RTS1/

PCI_CLK2

Output

SIN2/CTS1/

PCI_CLK3

AF25

I

GV

DRV_MEM_CTRL

13, 14, 26

DD

Clock-Out Signals

PCI_CLK0/SOUT1

PCI_CLK1/SIN1

AC25

AB25

AE26

Output

GV

DRV_PCI_CLK

13, 14

13, 14, 26

13, 14

DD

PCI_CLK2/RTS1/

SOUT2

PCI_CLK3/CTS1/

SIN2

AF25

Output

GV

DRV_PCI_CLK

13, 14, 26

13, 14

DD

PCI_CLK4/DA3

PCI_SYNC_OUT

PCI_SYNC_IN

AF26

AD25

AB23

Output

Input

GV

DRV_PCI_CLK

—

DD

SDRAM_CLK [0:3]

D1 G1 G2 E1

Output

DRV_MEM_CTRL

or

DRV_MEM_CLK

6, 21

21

SDRAM_SYNC_OUT C1

Output

GV

DRV_MEM_CTRL

or

DD

DRV_MEM_CLK

SDRAM_SYNC_IN

CKO/DA1

H3

Input

Output

Input

GV

OV

—

DRV_STD_MEM

—

DD

B15

AD21

14

19

OSC_IN

Miscellaneous Signals

HRST_CTRL

HRST_CPU

MCP

A20

A19

A17

D16

A18

B16

B14

Input

Output

Input

I/O

OV

GV

—

27

DD

—

DRV_STD_MEM

—

3, 4, 17

NMI

SMI

—

10

SRESET/SDMA12

TBEN/SDMA13

DRV_MEM_CTRL

10, 14

I/O

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

35

Package Description

Table 16. MPC8245 Pinout Listing (continued)

Power

Output

Driver Type

Name

Pin Numbers

Type

Notes

Supply

QACK/DA0

F2

Output

I/O

OV

GV

DRV_STD_MEM

DRV_MEM_CTRL

4, 14, 25

10, 14

DD

CHKSTOP_IN/

SDMA14

D14

DD

TRIG_IN/RCS2

TRIG_OUT/RCS3

MAA[0:2]

AF20

AC18

I/O

OV

GV

OV

—

10, 14

14

DD

Output

DRV_MEM_CTRL

DRV_STD_MEM

—

AF2 AF1 AE1

A16

3, 4, 6

24

MIV

PMAA[0:1]

PMAA[2]

AD18 AF18

AE19

DRV_STD_MEM

3, 4, 6, 15

4, 6, 15

Test/Configuration Signals

PLL_CFG[0:4]/

DA[10:6]

A22 B19 A21 B18 B17

I/O

OV

DRV_STD_MEM

6, 14, 20

DD

TEST0

RTC

TCK

AD22

Y2

Input

Output

Input

OV

GV

OV

—

1, 9

11

DD

AF22

AF23

AC21

AE22

AE23

9, 12

24

TDI

TDO

TMS

TRST

9, 12

Power and Ground Signals

GND

AA2 AA23 AC12 AC15 AC24 AC3

AC6 AC9 AD11 AD14 AD16 AD19

AD23 AD4 AE18 AE2 AE21 AE25

B2 B25 B6 B9 C11 C13 C16 C23

C4 C8 D12 D15 D18 D21 D24 D3

F25 F4 H24 J25 J4 L24 L3 M23

M4 N24 P3 R23 R4 T24 T3 V2

V23 W3

Ground

—

LV

AC20 AC23 D20 D23 G23 P23

Y23

Reference

voltage

3.3 V, 5.0 V

LV

—

DD

GV

OV

AB3 AB4 AC10 AC11 AC8 AD10

AD13 AD15 AD3 AD5 AD7 C10

C12 C3 C5 C7 D13 D5 D9 E3 G3

H4 K4 L4 N3 P4 R3 U3 V4 Y3

Power for

memory drivers

3.3 V

GV

DD

AB24 AD20 AD24 C14 C20 C24

E24 G24 J23 K24 M24 P24 T23

Y24

PCI/Stnd 3.3 V

OV

—

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

36

Freescale Semiconductor

Package Description

Table 16. MPC8245 Pinout Listing (continued)

Power

Output

Driver Type

Name

Pin Numbers

Type

Notes

Supply

V

AA24 AC16 AC19 AD12 AD6 AD9 Power for core

V

—

22

DD

C15 C18 C21 D11 D8 F3 H23 J3

L23 M3 R24 T4 V24 W4

1.8/2.0 V

No Connect

D17

C17

—

23

22

AV

Power for PLL

(CPU core logic)

1.8/2.0 V

AV

DD

AV

2

AF24

Power for PLL

(peripheral

logic)

AV

2

—

22

DD

1.8/2.0 V

Debug/Manufacturing Pins

DA0/QACK

DA1/CKO

DA2

F2

Output

I/O

OV

GV

OV

DRV_STD_MEM

DRV_PCI

4, 10, 25

14

DD

B15

C25

2

DA3/PCI_CLK4

DA4/REQ4

DA5/GNT4

AF26

DRV_PCI_CLK

—

14

Y26

12, 14

7, 15, 14

6, 14, 20

W26

Output

I/O

DRV_PCI

DA[10:6]/

A22 B19 A21 B18 B17

DRV_STD_MEM

PLL_CFG[0:4]

DA[11]

AD26

Output

OV

DRV_PCI

2

DD

DA[12:13]

AF17 AF19

DRV_STD_MEM

2, 6

DD

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

37

Package Description

Table 16. MPC8245 Pinout Listing (continued)

Power

Output

Driver Type

Name

Pin Numbers

Type

Notes

Supply

DA[14:15]

F1 J2

Output

GV

DRV_MEM_CTRL

2, 6

DD

Notes:

1. Place a pull-up resistor of 120 Ω or less on the TEST0 pin.

2. Treat these pins as no connects (NC) unless debug address functionality is used.

3. This pin has an internal pull-up resistor that is enabled only in the reset state. The value of the internal pull-up resistor is not

guaranteed but is sufficient to ensure that a logic 1 is read into configuration bits during reset if the signal is left unterminated.

4. This pin is a reset configuration pin.

5. DL[0] is a reset configuration pin with an internal pull-up resistor that is enabled only in the reset state. The value of the

internal pull-up resistor is not guaranteed but is sufficient to ensure that a logic 1 is read into configuration bits during reset.

6. Multi-pin signals such as AD[31:0] and MDL[0:31] have their physical package pin numbers listed in an order corresponding

to the signal names. Example: AD0 is on pin C22, AD1 is on pin D22, ..., AD31 is on pin V25.

7. GNT4 is a reset configuration pin with an internal pull-up resistor that is enabled only in the reset state.

8. A weak pull-up resistor (2–10 kΩ) should be placed on this PCI control pin to LV

.

DD

9. V and V for these signals are the same as the PCI V and V entries in Table 3.

IH

IL

IH

IL

10. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OV

11. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to GV

.

DD

.

DD

12. This pin has an internal pull-up resistor that is enabled at all times. The value of the internal pull-up resistor is not guaranteed

but is sufficient to prevent unused inputs from floating.

13. An external PCI clocking source or fan-out buffer may be required for the MPC8245 DUART functionality since

PCI_CLK[0:3] are not available in DUART mode. Only PCI_CLK4 is available in DUART mode.

14. This pin is a multiplexed signal and appears more than once in this table.

15. This pin is affected by the programmable PCI_HOLD_DEL parameter.

16. This pin is an open-drain signal.

17. This pin can be programmed as driven (default) or as open-drain (in MIOCR 1).

18. This pin is a sustained three-state pin as defined by the PCI Local Bus Specification.

19. OSC_IN uses the 3.3-V PCI interface driver, which is 5-V tolerant. See Table 2 for details.

20. PLL_CFG signals must be driven on reset and must be held for at least 25 clock cycles after the negation of HRST_CTRL

and HRST_CPU in order to be latched.

21. SDRAM_CLK[0:3] and SDRAM_SYNC_OUT signals use DRV_MEM_CTRL for chip Rev 1.1 (A). These signals use

DRV_MEM_CLK for chip Rev 1.2 (B).

22. The 266- and 300-MHz part offerings can run at a source voltage of 1.8 ± 100 mV or 2.0 ± 100 mV. Source voltage should

be 2.0 ± 100 mV for 333- and 350-MHz parts.

23. This pin is LAVDD on the MPC8240. It is an NC on the MPC8245, which should not pose a problem when an MPC8240 is

replaced with an MPC8245.

24. The driver capability of this pin is hardwired to 40 Ω and cannot be changed.

25. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OV so that a 1 can be detected at reset if an external

DD

memory clock is not used and PLL[0:4] does not select a half-clock frequency ratio.

26. Typically, the serial port has sufficient drivers in the RS232 transceiver to drive the CTS pin actively as an input. No pullups

are needed in this case.

27. HRST_CPU/HRST_CTRL must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN clock cycle for the

device to be in the nonreset state

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

38

Freescale Semiconductor

PLL Configurations

6 PLL Configurations

The internal PLLs are configured by the PLL_CFG[0:4] signals. For a given PCI_SYNC_IN (PCI bus)

frequency, the PLL configuration signals set both the peripheral logic/memory bus PLL (VCO) frequency

of operation for the PCI-to-memory frequency multiplying and the MPC603e CPU PLL (VCO) frequency

of operation for memory-to-CPU frequency multiplying. The PLL configurations are shown in Table 17

and Table 18.

Table 17. PLL Configurations (266- and 300-MHz Parts)

9

266-MHz Part

300-MHz Part

Multipliers

PCI Clock

Input

(PCI_

Periph

Logic/

MemBus

Clock

Range

(MHz)

PCI Clock

Input

(PCI_

Periph

Logic/

MemBus

Clock

Range

(MHz)

PLL_CFG

[0:4]

CPU

Clock

Range

(MHz)

CPU

Clock

Range

(MHz)

PCI-to-

Mem-to-

CPU

(CPU

Ref. No.

10,13

Mem

(Mem

VCO)

SYNC_IN)

1

Range

VCO)

(MHz)

12

5

5,7

0

1

2

3

4

6

00000

25–35

75–105

75–88

50–59

50–66

50–92

Bypass

60–66

188–263

225–264

225–266

100–133

100–184

25–40

75–120

75–99

50–66

50–92

Bypass

60–66

188–300

225–297

3 (2)

1 (4)

2.5 (2)

3 (2)

12

5

00001

25–29

25–33

11

18

5,7

1

18

1

00010

50 –59

50 –66

4.5 (2)

2 (4)

11,14

17

00011

50 –66

100–133 1 (Bypass)

100–184 2 (4)

12

4

00100

25–46

2 (4)

15

00110

Bypass

180–198 1 (Bypass)

14

6

1

6

1

7

00111

60 –66

180–198

60 –66

3 (2)

Rev B

14

7

00111

Not available

Rev D

12

6

1

6

1

8

9

01000

60 –66

60–66

90–132

50–58

68–88

72–92

68–75

60–88

75

180–198

180–264

225–261

204–264

180–230

238–263

180–264

263

60 –66

60–66

90–132

50–66

68–99

72–92

68–85

60–92

75–85

90–132

100–116

90–99

180–198

180–264

225–297

204–297

180–230

238–298

180–276

263–298

180–264

250–290

180–198

1 (4)

2 (2)

3 (2)

2 (2)

12

6

1

01001

45 –66

12

5

A

01010

25–29

25–33

2 (4)

4.5 (2)

3 (2)

12

3

5

4

5

3

1

4

5

4

B

01011

45 –59

45 –66

1.5 (2)

2 (4)

12

6

C

01100

36 –46

2.5 (2)

3.5 (2)

3 (2)

12

3

D

01101

45 –50

45 –57

1.5 (2)

2 (4)

12

6

E

01110

30 –44

30 –46

12

5

F

01111

25

25–28

3 (2)

3.5 (2)

2 (2)

12

6

2,5

6

2

10

11

12

10000

30 –44

90–132

100–106

90–99

180–264

250–266

180–198

30 –44

3 (2)

12

5,7

2

10001

25–26

25–29

4 (2)

2.5 (2)

2 (2)

12

6

1

6

1

10010

60 –66

1.5 (2)

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

39

PLL Configurations

Table 17. PLL Configurations (266- and 300-MHz Parts) (continued)

9

266-MHz Part

300-MHz Part

Multipliers

PCI Clock

Input

(PCI_

Periph

Logic/

MemBus

Clock

Range

(MHz)

PCI Clock

Input

(PCI_

Periph

Logic/

MemBus

Clock

Range

(MHz)

PLL_CFG

[0:4]

CPU

Clock

Range

(MHz)

CPU

Clock

Range

(MHz)

PCI-to-

Mem-to-

CPU

(CPU

Ref. No.

10,13

Mem

(Mem

VCO)

SYNC_IN)

1

Range

VCO)

(MHz)

12

2,7

13

14

15

16

17

18

19

1A

1B

1C

1D

10011

10100

10101

10110

Not available

52–76

25

100

52–84

300

4 (2)

2 (4)

3 (2)

3.5 (2)

4 (2)

2 (2)

3 (2)

2.5 (2)

4 (2)

3 (2)

2.5 (2)

Off

12

6

5

6

5

26 –38

182–266

26 –42

182–294

272–300

200–296

200–264

204–300

180–295

200–264

204–300

198–297

180–248

3

5,7

Not available

50–66

27 –30

68–75

2.5 (2)

2 (4)

5

25–33

200–264

204–264

180–265

200–264

204–264

198–264

180–248

25–37

25–33

50–74

12

5

2

10111

25–33

100–132

68–88

100–132

68–100

72–118

50–66

4 (2)

12

3

5

3

5,7

2

11000

11001

11010

27 –35

27 –40

2.5 (2)

2 (2)

6

36 –53

72–106

50–66

36 –59

18

1

18

1

50 –66

1 (4)

12

3

5

3

5,7

11011

34 –44

68–88

34 –50

68–100

66–99

2 (2)

12

3

5

3

1

11100

44 –59

66–88

44 –66

1.5 (2)

Off

12

6

1

6

1

11101

11110

48 –66

72–99

48 –66

72–99

8

1E

Not usable

Rev B

3

5

3

5

1E

11110

33 –38

66–76

231–266

33 –42

66–84

231–294

2(2)

3.5(2)

Rev D

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

40

Freescale Semiconductor

PLL Configurations

Multipliers

Table 17. PLL Configurations (266- and 300-MHz Parts) (continued)

9

266-MHz Part

300-MHz Part

PCI Clock

Input

(PCI_

Periph

Logic/

MemBus

Clock

Range

(MHz)

PCI Clock

Input

(PCI_

Periph

Logic/

MemBus

Clock

Range

(MHz)

PLL_CFG

[0:4]

CPU

Clock

Range

(MHz)

CPU

Clock

Range

(MHz)

PCI-to-

Mem-to-

CPU

(CPU

Ref. No.

10,13

Mem

(Mem

VCO)

SYNC_IN)

1

Range

VCO)

(MHz)

8

1F

11111

Not usable

Off

Notes:

1. Limited by the maximum PCI input frequency (66 MHz).

Limited by the maximum system memory interface operating frequency (100 MHz @ 300 MHz CPU).

2

3. Limited by the minimum memory VCO frequency (133 MHz).

4. Limited due to the maximum memory VCO frequency (372 MHz).

5. Limited by the maximum CPU operating frequency.

6. Limited by the minimum CPU VCO frequency (360 MHz).

7. Limited by the maximum CPU VCO frequency (maximum marked CPU speed X 2).

8. In clock-off mode, no clocking occurs inside the MPC8245, regardless of the PCI_SYNC_IN input.

9. Range values are rounded down to the nearest whole number (decimal place accuracy removed).

10. PLL_CFG[0:4] settings not listed are reserved.

11. Multiplier ratios for this PLL_CFG[0:4] setting differ from the MPC8240 and are not backward-compatible.

12. PCI_SYNC_IN range for this PLL_CFG[0:4] setting differs from or does not exist on the MPC8240 and may not be fully

backward-compatible.

13. Bits 7–4 of register offset <0xE2> contain the PLL_CFG[0:4] setting value.

14. In PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal processor directly, the peripheral logic PLL is

disabled, and the bus mode is set for 1:1 (PCI:Mem) mode operation. This mode is for hardware modeling. The AC timing

specifications in this document do not apply in PLL bypass mode.

15. In dual PLL bypass mode, the PCI_SYNC_IN input signal clocks the internal peripheral logic directly, the peripheral logic

PLL is disabled, and the bus mode is set for 1:1 (PCI_SYNC_IN:Mem) mode operation. In this mode, the OSC_IN input

signal clocks the internal processor directly in 1:1 (OSC_IN:CPU) mode operation, and the processor PLL is disabled. The

PCI_SYNC_IN and OSC_IN input clocks must be externally synchronized. This mode is for hardware modeling. The AC

timing specifications in this document do not apply in dual PLL bypass mode.

16. Limited by the maximum system memory interface operating frequency (133 MHz @ 266 MHz CPU).

17. Limited by the minimum CPU operating frequency (100 MHz).

18. Limited by the minimum memory bus frequency (50 MHz).

Table 18. PLL Configurations (333- and 350-MHz Parts)

9

333 MHz Part

350 MHz Part

Multipliers

PCI Clock

Input

(PCI_

PCI Clock

Input

(PCI_

Periph

Logic/Mem

Bus Clock

Range

Periph

Logic/Mem

Bus Clock

Range

CPU

Clock

CPU

Clock

Range

(MHz)

PCI-to-

Mem-to-

CPU

(CPU

PLL_

CFG[0:4]

Ref

10,13

Mem

(Mem

VCO)

SYNC_IN)

Range SYNC_IN)

1

Range

(MHz)

Range

(MHz)

VCO)

(MHz)

12

16

0

1

00000

00001

25–44

75–132

75–111

188–330 25–44

225–333

75–132

75–114

188–330

225–342

3 (2)

2.5 (2)

3 (2)

12

5,7

5

25–37

25–38

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

Freescale Semiconductor

41

PLL Configurations

Table 18. PLL Configurations (333- and 350-MHz Parts) (continued)

9

333 MHz Part

350 MHz Part

Multipliers

PCI Clock

Input

(PCI_

PCI Clock

Input

(PCI_

Periph

Logic/Mem

Bus Clock

Range

Periph

Logic/Mem

Bus Clock

Range

CPU

Clock

CPU

Clock

Range

(MHz)

PCI-to-

Mem-to-

CPU

(CPU

PLL_

CFG[0:4]

Ref

10,13

Mem

(Mem

VCO)

SYNC_IN)

Range SYNC_IN)

1

Range

(MHz)

Range

(MHz)

VCO)

(MHz)

11

18

1

18

1

2

3

4

6

00010

50 –66

50–66

50–92

Bypass

60–66

225–297 50 –66

50–66

50–92

Bypass

60–66

225–297

1 (4)

4.5 (2)

2 (4)

11,14

17

00011

50 –66

100–133 50 –66

100–133 1 (Bypass)

100–184 2 (4)

Bypass

180–198 1 (Bypass)

12

4

00100

00110

25–46

100–184

25–46

2 (4)

15

14

6

1

6

1

7

00111

60 –66

180–198 60 –66

3 (2)

Rev B

14

7

00111

Not available

25

100

350

4(2)

3.5(2)

Rev D

12

6

1

6

1

8

9

01000

01001

01010

60 –66

60–66

90–132

50–74

180–198 60 –66

60–66

90–132

50–76

180–198

180–264

225–342

204–297

180–230

238–347

180–276

263–347

180–264

250–330

180–198

300–348

182–329

272–340

200–344

200–264

204–345

180–330

200–264

204–348

198–297

180–248

1 (4)

2 (2)

3 (2)

2 (2)

6

1

6

45 –66

180–264 45 –66

5,7

5

A

25–37

225–333

25–38

2 (4)

4.5 (2)

3 (2)

12

3

1

3

1

4

1

4

B

01011

01100

01101

01110

45 –66

68–99

204–297 45 –66

68–99

1.5 (2)

2 (4)

6

4

6

C

36 –46

72–92

180–230 36 –46

72–92

2.5 (2)

3.5 (2)

3 (2)

3

5,7

3

D

45 –63

68–95

238–333 45 –66

68–99

1.5 (2)

2 (4)

6

4

6

E

30 –46

60–92

180–276 30 –46

60–92

12

5

F

01111

25–31

75–93

263–326

25–33

75–99

3 (2)

3.5 (2)

2 (2)

12

6

2

6

2

10

11

12

13

14

15

16

17

18

19

1A

1B

1C

1D

10000

10001

10010

30 –44

90–132

100–132

90–99

180–264 30 –44

90–132

100–132

90–99

3 (2)

2,16

25–33

250–330 25–33

4 (2)

2.5 (2)

2 (2)

6

1

6

1

60 –66

180–198 60 –66

1.5 (2)

4 (2)

12

5

10011

10100

25–27

100–108

52–94

300–324

25–29

100–116

52–94

3 (2)

6

4

5

6

4

5

26 –47

182–329 26 –47

2 (4)

3.5 (2)

4 (2)

3

10101

10110

27 –33

68–83

272–332 27 –34

68–85

2.5 (2)

2 (4)

12

5

25–41

25–33

50–82

200–328

200–264

25–43

50–86

4 (2)

2

10111

100–132

68–110

72–132

50–66

25–33

100–132

68–115

72–132

50–66

4 (2)

2 (2)

12

3

5

3

5

11000

11001

11010

27 –44

204–330 27 –46

2.5 (2)

2 (2)

3 (2)

6

1

6

1

36 –66

180–330 36 –66

2.5 (2)

4 (2)

18

1

18

1

50 –66

200–264 50 –66

1 (4)

12

3

5

3

5

11011

34 –55

68–110

66–99

204–330 34 –58

68–116

66–99

2 (2)

3 (2)

12

3

1

3

1

11100

44 –66

198–297 44 –66

1.5 (2)

3 (2)

12

6

1

6

1

11101

48 –66

72–99

180–248 48 –66

72–99

2.5(2)

MPC8245 Integrated Processor Hardware Specifications, Rev. 10

42

Freescale Semiconductor

PLL Configurations

Multipliers

Table 18. PLL Configurations (333- and 350-MHz Parts) (continued)

9

333 MHz Part

350 MHz Part

PCI Clock

Input

(PCI_

PCI Clock

Input

(PCI_

Periph

Logic/Mem

Bus Clock

Range

Periph

Logic/Mem

Bus Clock

Range

CPU

Clock

CPU

Clock

Range

(MHz)

PCI-to-

Mem-to-

CPU

(CPU

PLL_

CFG[0:4]

Ref

10,13

Mem

(Mem

VCO)

SYNC_IN)

Range SYNC_IN)

1

Range

(MHz)

Range

(MHz)

VCO)

(MHz)

8

1E

Rev B

11110

Not usable

66–94

Not usable

66–100

Off

2(2)

Off

3.5(2)

Off

3

5

3

2,5,7

1E

Rev D

11110

33 –47

231–329 33 –50

231–350

8

1F

11111

Not usable

Notes:

1. Limited by the maximum PCI input frequency (66 MHz).

2. Limited by the maximum system memory interface operating frequency (100 MHz @ 350 MHz CPU).

3. Limited by the minimum memory VCO frequency (132 MHz).

4. Limited due to the maximum memory VCO frequency (372 MHz).

5. Limited by the maximum CPU operating frequency.

6. Limited by the minimum CPU VCO frequency (360 MHz).

7. Limited by the maximum CPU VCO frequency (Maximum marked CPU speed X 2).

8. In clock-off mode, no clocking occurs inside the MPC8245, regardless of the PCI_SYNC_IN input.

9. Range values are rounded down to the nearest whole number (decimal place accuracy removed).

10. PLL_CFG[0:4] settings not listed are reserved.

11. Multiplier ratios for this PLL_CFG[0:4] setting differ from or do not exist on the MPC8240 and are not backward-compatible.

12. PCI_SYNC_IN range for this PLL_CFG[0:4] setting differs from the MPC8240 and may not be fully backward-compatible.