MPC8250AZQIHBC [NXP]
32-BIT, 200MHz, RISC PROCESSOR, PBGA516, 27 X 27 MM, 1.25 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-516;
| 型号： | MPC8250AZQIHBC |
| 厂家： | 
NXP |
| 描述： | 32-BIT, 200MHz, RISC PROCESSOR, PBGA516, 27 X 27 MM, 1.25 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-516 外围集成电路 |
| 文件： | 总62页 (文件大小：1123K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Document Number: MPC8250EC
Rev. 2, 07/2009
Freescale Semiconductor
MPC8250
Hardware Specifications
Contents
This document contains detailed information on power
1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical and Thermal Characteristics . . . . . . . . . . . . 6
3. Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 20
4. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
5. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 55
6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 59
7. Document Revision History . . . . . . . . . . . . . . . . . . . 59
considerations, DC/AC electrical characteristics, and AC
timing specifications for the MPC8250 PowerQUICC II™
communications processor.
The following topics are addressed:
The MPC8250 is available in two packages—the standard
TBGA package (480 pins) and an alternate PBGA package
(516 pins)—as described in Section 4, “Pinout,” and
Section 5, “Package Description.” For more information on
PBGA packages, contact your Freescale sales office. Note
that throughout this document references to the MPC8250
are inclusive of its PBGA version unless otherwise specified.
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2003, 2005, 2009. All rights reserved.
Features
Figure 1 shows the block diagram for the MPC8250.
16 Kbytes
I-Cache
I-MMU
System Interface Unit
(SIU)
60x Bus
G2 Core
16 Kbytes
D-Cache
Bus Interface Unit
PCI Bus
32 bits, up to 66 MHz
60x-to-PCI
Bridge
D-MMU
or
60x-to-Local
Bridge
Local Bus
32 bits, up to 66 MHz
Communication Processor Module (CPM)
Memory Controller
Clock Counter
Timers
Serial
DMAs
32 Kbytes
Dual-Port RAM
Interrupt
Controller
Parallel I/O
32-bit RISC Microcontroller
and Program ROM
4 Virtual
IDMAs
System Functions
Baud Rate
Generators
I2C
MCC2 FCC1 FCC2 FCC3 SCC1 SCC2 SCC3 SCC4 SMC1 SMC2
SPI
Time Slot Assigner
Serial Interface
Non-Multiplexed
I/O
3 MII
Ports
4 TDM Ports
Figure 1. MPC8250 Block Diagram
1 Features
The major features of the MPC8250 are as follows:
•
•
Footprint-compatible with the MPC8260
Dual-issue integer core
— A core version of the EC603e microprocessor
— System core microprocessor supporting frequencies of 150–200 MHz
— Separate 16-Kbyte data and instruction caches:
– Four-way set associative
– Physically addressed
– LRU replacement algorithm
— PowerPC architecture-compliant memory management unit (MMU)
— Common on-chip processor (COP) test interface
— High-performance (4.4–5.1 SPEC95 benchmark at 200 MHz; 280 Dhrystones MIPS at
200 MHz)
MPC8250 Hardware Specifications, Rev. 2
2
Freescale Semiconductor
Features
— Supports bus snooping for data cache coherency
— Floating-point unit (FPU)
•
•
Separate power supply for internal logic (1.8 V) and for I/O (3.3V)
Separate PLLs for G2 core and for the CPM
— G2 core and CPM can run at different frequencies for power/performance optimization
— Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios
64-bit data and 32-bit address 60x bus
•
— Bus supports multiple master designs
— Supports single- and four-beat burst transfers
— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
— Supports data parity or ECC and address parity
32-bit data and 18-bit address local bus
•
•
— Single-master bus, supports external slaves
— Eight-beat burst transfers
— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller
60x-to-PCI bridge
— Programmable host bridge and agent
— 32-bit data bus, 66 MHz, 3.3 V
— Synchronous and asynchronous 60x and PCI clock modes
— All internal address space available to external PCI host
— DMA for memory block transfers
— PCI-to-60x address remapping
•
•
System interface unit (SIU)
— Clock synthesizer
— Reset controller
— Real-time clock (RTC) register
— Periodic interrupt timer
— Hardware bus monitor and software watchdog timer
— IEEE 1149.1™ JTAG test access port
Twelve-bank memory controller
— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-
definable peripherals
— Byte write enables and selectable parity generation
— 32-bit address decodes with programmable bank size
— Three user programmable machines, general-purpose chip-select machine, and page-mode
pipeline SDRAM machine
— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
3
Features
— Dedicated interface logic for SDRAM
•
•
CPU core can be disabled and the device can be used in slave mode to an external core
Communications processor module (CPM)
— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support
for communications protocols
— Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller
— Serial DMA channels for receive and transmit on all serial channels
— Parallel I/O registers with open-drain and interrupt capability
— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers
— Three fast communications controllers supporting the following protocols:
– 10/100-Mbit Ethernet/IEEE 802.3® CDMA/CS interface through media independent
interface (MII)
– Transparent
– HDLC—Up to T3 rates (clear channel)
— One multichannel controller (MCC2)
– Handles 128 serial, full-duplex, 64-Kbps data channels. The MCC can be split into four
subgroups of 32 channels each.
– Almost any combination of subgroups can be multiplexed to single or multiple TDM
interfaces up to four TDM interfaces per MCC
— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BISYNC) communications
– Transparent
— Two serial management controllers (SMCs), identical to those of the MPC860
– Provide management for BRI devices as general circuit interface (GCI) controllers in time-
division-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
— One serial peripheral interface identical to the MPC860 SPI
2
2
— One inter-integrated circuit (I C) controller (identical to the MPC860 I C controller)
– Microwire compatible
– Multiple-master, single-master, and slave modes
— Up to four TDM interfaces
– Supports one group of four TDM channels
MPC8250 Hardware Specifications, Rev. 2
4
Freescale Semiconductor
Features
– 2,048 bytes of SI RAM
– Bit or byte resolution
– Independent transmit and receive routing, frame synchronization
– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN
primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and
user-defined TDM serial interfaces
— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,
SCCs, SMCs, and serial channels
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
PCI bridge
•
— PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz
— On-chip arbitration
— Support for PCI to 60x memory and 60x memory to PCI streaming
— PCI Host Bridge or Peripheral capabilities
— Includes 4 DMA channels for the following transfers:
– PCI-to-60x to 60x-to-PCI
– 60x-to-PCI to PCI-to-60x
– PCI-to-60x to PCI-to-60x
– 60x-to-PCI to 60x-to-PCI
— Includes all of the configuration registers (which are automatically loaded from the EPROM
and used to configure the MPC8265A) required by the PCI standard as well as message and
doorbell registers
— Supports the I O standard
2
— Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0
August 3, 1998)
— Support for 66 MHz, 3.3 V specification
— 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port
— Makes use of the local bus signals, so there is no need for additional pins
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
5
Electrical and Thermal Characteristics
2 Electrical and Thermal Characteristics
This section provides AC and DC electrical specifications and thermal characteristics for the MPC8250.
2.1
DC Electrical Characteristics
This section describes the DC electrical characteristics for the MPC8250. Table 1 shows the maximum
electrical ratings.
1
Table 1. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
2
Core supply voltage
VDD
VCCSYN
VDDH
VIN
-0.3 – 2.5
-0.3 – 2.5
V
V
2
PLL supply voltage
3
I/O supply voltage
-0.3 – 4.0
V
4
Input voltage
GND(-0.3) – 3.6
120
V
Junction temperature
T
°C
°C
j
Storage temperature range
T
(-55) – (+150)
STG
1
Absolute maximum ratings are stress ratings only; functional operation (see Table 2) at the maximums is not
guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.
2
3
Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset.
Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should
not exceed VDD/VCCSYN by more than 2.5 V during normal operation.
4
Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.
Table 2 lists recommended operational voltage conditions.
1
Table 2. Recommended Operating Conditions
Rating
Symbol
Value
Unit
2
2
3
3
4
Core supply voltage
PLL supply voltage
I/O supply voltage
VDD
VCCSYN
VDDH
VIN
1.7 – 1.9
1.7–2.1
1.7–2.1
1.9 –2.2
1.9–2.2
V
V
4
1.7 – 1.9
3.135 – 3.465
V
Input voltage
GND (-0.3) – 3.465
V
5
Junction temperature (maximum)
Ambient temperature
T
105
°C
°C
j
5
T
0–70
A
1
Caution: These are the recommended and tested operating conditions. Proper device operating outside of these
conditions is not guaranteed.
2
3
4
5
CPU frequency less than or equal to 200 MHz.
CPU frequency greater than 200 MHz but less than 233 MHz.
CPU frequency greater than or equal to 233 MHz.
Note that for extended temperature parts the range is (-40) – 105 .
T
T
j
A
MPC8250 Hardware Specifications, Rev. 2
6
Freescale Semiconductor
Electrical and Thermal Characteristics
NOTE: Core, PLL, and I/O Supply Voltages
VDDH, VCCSYN, and VDD must track each other and both must vary in
the same direction—in the positive direction (+5% and +0.1 Vdc) or in the
negative direction (-5% and -0.1 Vdc).
This device contains circuitry protecting against damage due to high static voltage or electrical fields;
however, it is advised that normal precautions be taken to avoid application of any voltages higher than
maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level (either GND or V ).
CC
Figure 2 shows the undershoot and overshoot voltage of the 60x and local bus memory interface of the
MPC8280. Note that in PCI mode the I/O interface is different.
4 V
GV + 5%
DD
V
V
GV
IH
DD
GND
GND – 0.3 V
IL
GND – 1.0 V
Not to exceed 10%
of t
SDRAM_CLK
Figure 2. Overshoot/Undershoot Voltage
Table 3 shows DC electrical characteristics.
1
Table 3. DC Electrical Characteristics
Characteristic
Symbol
Min
Max
Unit
Input high voltage, all inputs except CLKIN
Input low voltage
V
2.0
GND
2.4
GND
—
3.465
0.8
3.465
0.4
10
V
V
IH
V
IL
CLKIN input high voltage
V
V
IHC
CLKIN input low voltage
V
I
V
ILC
2
Input leakage current, V = VDDH
µA
µA
µA
µA
V
IN
IN
2
Hi-Z (off state) leakage current, V = VDDH
I
—
10
IN
OZ
Signal low input current, V = 0.8 V
I
—
1
IL
L
Signal high input current, V = 2.0 V
I
—
1
IH
H
Output high voltage, I = –2 mA
V
2.4
—
OH
OH
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
7
Electrical and Thermal Characteristics
1
Table 3. DC Electrical Characteristics (continued)
Characteristic
Symbol
Min
Max
Unit
I
= 7.0mA
V
—
0.4
V
OL
OL
BR
BG
ABB/IRQ2
TS
A[0-31]
TT[0-4]
TBST
TSIZE[0–3]
AACK
ARTRY
DBG
DBB/IRQ3
D[0-63]
DP(0)/RSRV/EXT_BR2
DP(1)/IRQ1/EXT_BG2
DP(2)/TLBISYNC/IRQ2/EXT_DBG2
DP(3)/IRQ3/EXT_BR3/CKSTP_OUT
DP(4)/IRQ4/EXT_BG3/CORE_SREST
DP(5)/TBEN/IRQ5/EXT_DBG3
DP(6)/CSE(0)/IRQ6
DP(7)/CSE(1)/IRQ7
PSDVAL
TA
TEA
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5
CPU_DBG
CPU_BR
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
PORESET
HRESET
SRESET
RSTCONF
QREQ
MPC8250 Hardware Specifications, Rev. 2
8
Freescale Semiconductor
Electrical and Thermal Characteristics
1
Table 3. DC Electrical Characteristics (continued)
Characteristic
Symbol
Min
Max
Unit
I
= 5.3mA
V
—
0.4
V
OL
OL
CS[0-9]
CS(10)/BCTL1
CS(11)/AP(0)
BADDR[27–28]
ALE
BCTL0
PWE(0:7)/PSDDQM(0:7)/PBS(0:7)
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LWE[0–3]LSDDQM[0:3]/LBS[0–3]/PCI_CFG[0–3
LSDA10/LGPL0/PCI_MODCKH0
LSDWE/LGPL1/PCI_MODCKH1
LOE/LSDRAS/LGPL2/PCI_MODCKH2
LSDCAS/LGPL3/PCI_MODCKH3
LGTA/LUPMWAIT/LGPL4/LPBS
LSDAMUX/LGPL5/PCI_MODCK
LWR
MODCK1/AP(1)/TC(0)/BNKSEL(0)
MODCK2/AP(2)/TC(1)/BNKSEL(1)
MODCK3/AP(3)/TC(2)/BNKSEL(2)
I
= 3.2mA
OL
L_A14/PAR
L_A15/FRAME/SMI
L_A16/TRDY
L_A17/IRDY/CKSTP_OUT
L_A18/STOP
L_A19/DEVSEL
L_A20/IDSEL
L_A21/PERR
L_A22/SERR
L_A23/REQ0
L_A24/REQ1/HSEJSW
L_A25/GNT0
L_A26/GNT1/HSLED
L_A27/GNT2/HSENUM
L_A28/RST/CORE_SRESET
L_A29/INTA
L_A30/REQ2
L_A31
LCL_D(0-31)/AD(0-31)
LCL_DP(0-3)/C/BE(0-3)
PA[0–31]
PB[4–31]
PC[0–31]
PD[4–31]
TDO
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
9
Electrical and Thermal Characteristics
1
The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive
DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.
2
The leakage current is measured for nominal VDD, VCCSYN, and VDD.
2.2
Thermal Characteristics
Table 4 describes thermal characteristics.
Table 4. Thermal Characteristics
Value
Characteristic
Symbol
Unit
Air Flow
480 TBGA
516 PBGA
Junction to ambient—
single-layer board
13
10
11
8
24
18
16
13
8
Natural convection
1
1 m/s
θ
°C/W
JA
Junction to ambient—
four-layer board
Natural convection
1 m/s
—
2
Junction to board
θ
4
°C/W
°C/W
JB
3
Junction to case
θ
1.1
6
—
JC
1
2
Assumes no thermal vias
Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
3
Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1).
2.3
Power Considerations
The average chip-junction temperature, T , in °C can be obtained from the following:
J
T = T + (P x θJA)
(1)
J
A
D
where
T = ambient temperature °C
A
θJA = package thermal resistance, junction to ambient, °C/W
P = P
+ P
D
INT
I/O
P
P
= I x V Watts (chip internal power)
DD DD
INT
= power dissipation on input and output pins (determined by user)
I/O
For most applications P < 0.3 x P . If P is neglected, an approximate relationship between P and
I/O
INT
I/O
D
T is the following:
J
P = K/(T + 273° C)
(2)
(3)
D
J
Solving equations (1) and (2) for K gives:
2
K = P x (T + 273° C) + θJA x P
D
A
D
MPC8250 Hardware Specifications, Rev. 2
10
Freescale Semiconductor
Electrical and Thermal Characteristics
where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring
P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by
D
A
D
J
solving equations (1) and (2) iteratively for any value of T .
A
2.3.1
Layout Practices
Each V pin should be provided with a low-impedance path to the board’s power supply. Each ground
CC
pin should likewise be provided with a low-impedance path to ground. The power supply pins drive
distinct groups of logic on chip. The V power supply should be bypassed to ground using at least four
CC
0.1 µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads
and associated printed circuit traces connecting to chip V and ground should be kept to less than half an
CC
inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND
planes.
All output pins on the MPC8250 have fast rise and fall times. Printed circuit (PC) trace interconnection
length should be minimized in order to minimize overdamped conditions and reflections caused by these
fast output switching times. This recommendation particularly applies to the address and data buses.
Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all
device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and
bypassing becomes especially critical in systems with higher capacitive loads because these loads create
higher transient currents in the V and GND circuits. Pull up all unused inputs or signals that will be
CC
inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.
Table 5 provides preliminary, estimated power dissipation for various configurations. Note that suitable
thermal management is required for conditions above P = 3W (when the ambient temperature is 70° C or
D
greater) to ensure the junction temperature does not exceed the maximum specified value. Also note that
the I/O power should be included when determining whether to use a heat sink.
1
Table 5. Estimated Power Dissipation for Various Configurations
2
P
(W)
INT
Bus
(MHz)
CPM
Core CPU
CPM
(MHz)
CPU
(MHz)
Vddl 1.8 Volts
Nominal Maximum Nominal Maximum
Vddl 2.0 Volts
Multiplier Multiplier
66.66
66.66
66.66
66.66
83.33
83.33
83.33
2
2.5
3
3
3
133
166
200
200
166
166
208
200
200
266
300
250
250
291
1.2
1.3
—
2
2.1
—
—
—
—
—
1.8
1.9
2.3
2.4
2.2
2.2
2.4
2.3
2.3
2.9
3.1
2.8
2.8
3.1
4
3
4.5
3
—
2
—
2
3
—
2.5
3.5
—
1
2
Test temperature = room temperature (25° C)
= I x V Watts
P
INT
DD
DD
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
11
Electrical and Thermal Characteristics
2.4
AC Electrical Characteristics
The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and
inputs for the 66 MHz MPC8250 device. Note that AC timings are based on a 50-pf load. Typical output
buffer impedances are shown in Table 6.
1
Table 6. Output Buffer Impedances
Output Buffers
60x bus
Typical Impedance (Ω)
40
40
40
46
25
Local bus
Memory controller
Parallel I/O
PCI
1
These are typical values at 65° C. The impedance may vary by
±25% with process and temperature.
Table 7 lists CPM output characteristics.
1
Table 7. AC Characteristics for CPM Outputs
Spec Number
Max Delay (ns) Min Delay (ns)
66 MHz 83 MHz 66 MHz 83 MHz
Characteristic
Max
Min
sp36a
sp36b
sp40
sp37a
sp37b
sp41
FCC outputs—internal clock (NMSI)
FCC outputs—external clock (NMSI)
TDM outputs/SI
6
5.5
12
16
16
16
11
11
1
2
1
1
14
25
19
19
14
14
5
4
sp38a
sp38b
sp42
sp39a
sp39b
sp43
SCC/SMC/SPI/I2C outputs—internal clock (NMSI)
Ex_SCC/SMC/SPI/I2C outputs—external clock (NMSI)
TIMER/IDMA outputs
1
0.5
1
2
1
0.5
0.5
sp42a
sp43a
PIO outputs
0.5
1
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
Table 8 lists CPM input characteristics.
1
Table 8. AC Characteristics for CPM Inputs
Spec Number
Setup (ns)
Hold (ns)
Characteristic
Max
Min
66 MHz 83 MHz 66 MHz 83 MHz
sp16a
sp16b
sp17a
sp17b
FCC inputs—internal clock (NMSI)
FCC inputs—external clock (NMSI)
10
3
8
0
3
0
2
2.5
MPC8250 Hardware Specifications, Rev. 2
12
Freescale Semiconductor
Electrical and Thermal Characteristics
1
Table 8. AC Characteristics for CPM Inputs
Characteristic
Spec Number
Setup (ns)
Hold (ns)
Max
Min
66 MHz 83 MHz 66 MHz 83 MHz
sp20
sp18a
sp18b
sp22
sp21
sp19a
sp19b
sp23
TDM inputs/SI
15
20
5
12
16
4
12
0
10
0
SCC/SMC/SPI/I2C inputs—internal clock (NMSI)
SCC/SMC/SPI/I2C inputs—external clock (NMSI)
PIO/TIMER/IDMA inputs
5
4
10
8
3
3
1
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.
Timings are measured at the pin.
Note that although the specifications generally reference the rising edge of the clock, the following AC
timing diagrams also apply when the falling edge is the active edge.
Figure 3 shows the FCC external clock.
Serial ClKin
sp17b
sp16b
FCC input signals
sp36b/sp37b
FCC output signals
Note: When GFMR[TCI] = 0
sp36b/sp37b
FCC output signals
Note: When GFMR[TCI] = 1
Figure 3. FCC External Clock Diagram
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
13
Electrical and Thermal Characteristics
Figure 4 shows the FCC internal clock.
BRG_OUT
sp17a
sp16a
FCC input signals
sp36a/sp37a
FCC output signals
Note: When GFMR.TCI = 0
sp36a/sp37a
FCC output signals
Note: When GFMR.TCI = 1
Figure 4. FCC Internal Clock Diagram
2
Figure 5 shows the SCC/SMC/SPI/I C external clock.
Serial CLKin
sp19b
sp18b
SCC/SMC/SPI/I2C input signals
(See note.)
sp38b/sp39b
SCC/SMC/SPI/I2C output signals
(See note.)
Note: There are four possible timing conditions for SCC and SPI:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
2
Figure 5. SCC/SMC/SPI/I C External Clock Diagram
MPC8250 Hardware Specifications, Rev. 2
14
Freescale Semiconductor
Electrical and Thermal Characteristics
2
Figure 6 shows the SCC/SMC/SPI/I C internal clock.
BRG_OUT
sp19a
sp18a
SCC/SMC/SPI/I2C input signals
(See note.)
sp38a/sp39a
SCC/SMC/SPI/I2C output signals
(See note.)
Note: There are four possible timing conditions for SCC and SPI:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
2
Figure 6. SCC/SMC/SPI/I C Internal Clock Diagram
Figure 7 shows TDM input and output signals.
Serial CLKin
sp20
sp21
TDM input signals
sp40/sp41
TDM output signals
Note: There are four possible TDM timing conditions:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Figure 7. TDM Signal Diagram
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
15
Electrical and Thermal Characteristics
Figure 8 shows PIO, timer, and DMA signals.
Sys clk
sp23
sp22
PIO/IDMA/TIMER[TGATE assertion] input signals
(See note)
sp23
sp22
TIMER input signal [TGATE deassertion]
(See note)
sp42/sp43
IDMA output signals
sp42/sp43
sp42a/sp43a
TIMER(sp42/43)/ PIO(sp42a/sp43a)
output signals
Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.
Figure 8. PIO, Timer, and DMA Signal Diagram
Table 9 lists SIU input characteristics.
1
Table 9. AC Characteristics for SIU Inputs
Spec Number
Setup (ns)
Hold (ns)
Characteristic
Max
Min
66 MHz 83 MHz 66 MHz 83 MHz
sp11
sp12
sp13
sp14
sp15
sp10
sp10
sp10
sp10
sp10
AACK/ARTRY/TA/TS/TEA/DBG/BG/BR
Data bus in normal mode
Data bus in ECC and PARITY modes
DP pins
6
5
8
7
5
5
4
6
6
4
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
All other pins
1
Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.
Timings are measured at the pin.
MPC8250 Hardware Specifications, Rev. 2
16
Freescale Semiconductor
Electrical and Thermal Characteristics
Table 10 lists SIU output characteristics.
1
Table 10. AC Characteristics for SIU Outputs
Max Delay (ns)
66 MHz 83 MHz 66 MHz 83 MHz
Spec Number
Min Delay (ns)
Characteristic
Max
Min
sp31
sp32
sp30
sp30
sp30
sp30
sp30
sp30
PSDVAL/TEA/TA
7
8
6
6.5
6.5
7
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ADD/ADD_atr./BADDR/CI/GBL/WT
sp33a
sp33b
sp34
Data bus
6.5
8
DP
Memory controller signals/ALE
All other signals
6
5
sp35
6
5.5
1
Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.
Timings are measured at the pin.
NOTE
Activating data pipelining (setting BRx[DR] in the memory controller)
improves the AC timing. When data pipelining is activated, sp12 can be
used for data bus setup even when ECC or PARITY are used. Also, sp33a
can be used as the AC specification for DP signals.
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
17
Electrical and Thermal Characteristics
Figure 9 shows the interaction of several bus signals.
CLKin
sp10
sp10
sp10
sp11
AACK/ARTRY/TA/TS/TEA/
DBG/BG/BR input signals
sp12
DATA bus normal mode
input signal
sp15
All other input signals
sp30
sp31
sp32
PSDVAL/TEA/TA output signals
sp30
sp30
sp30
ADD/ADD_atr/BADDR/CI/
GBL/WT output signals
sp33a
sp35
DATA bus output signals
All other output signals
Figure 9. Bus Signals
Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).
CLKin
sp10
sp13
DATA bus, ECC, and PARITY mode input signals
sp10
sp14
DP mode input signal
sp33b/sp30
DP mode output signal
Figure 10. Parity Mode Diagram
MPC8250 Hardware Specifications, Rev. 2
18
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 11 shows signal behavior in MEMC mode.
CLKin
V_CLK
sp34/sp30
Memory controller signals
Figure 11. MEMC Mode Diagram
NOTE
Generally, all MPC8250 bus and system output signals are driven from the
rising edge of the input clock (CLKin). Memory controller signals,
however, trigger on four points within a CLKin cycle. Each cycle is divided
by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising
edge, and T3 at the falling edge, of CLKin. However, the spacing of T2 and
T4 depends on the PLL clock ratio selected, as shown in Table 11.
Table 11. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
PLL Clock Ratio
T2
T3
T4
1:2, 1:3, 1:4, 1:5, 1:6
1/4 CLKin
1/2 CLKin
3/4 CLKin
1:2.5
1:3.5
3/10 CLKin
4/14 CLKin
1/2 CLKin
1/2 CLKin
8/10 CLKin
11/14 CLKin
Figure 12 is a graphical representation of Table 11.
CLKin
for 1:2, 1:3, 1:4, 1:5, 1:6
T1
T1
T1
T2
T3
T3
T3
T4
CLKin
CLKin
for 1:2.5
T2
T4
for 1:3.5
T2
T4
Figure 12. Internal Tick Spacing for Memory Controller Signals
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
19
Clock Configuration Modes
NOTE
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
3 Clock Configuration Modes
The MPC8250 has three clocking modes: local, PCI host, and PCI agent. The clocking mode is set
according to three input pins—PCI_MODE, PCI_CFG[0], PCI_MODCK—as shown in Table 12.
Table 12. MPC8250 Clocking Modes
Pins
PCI Clock
Frequency Range
(MHZ)
Clocking Mode
Reference
1
PCI_MODE PCI_CFG[0] PCI_MODCK
1
0
0
0
0
—
0
—
0
Local bus
PCI host
—
Table 13 and Table 14
Table 15 and Table 16
50–66
25–50
50–66
25–50
0
1
1
0
PCI agent
Table 17 and Table 18
1
1
1
Determines PCI clock frequency range. Refer to Section 3.2, “PCI Mode.”
In each clocking mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven
bits during the power-up reset—three hardware configuration pins (MODCK[1–3]) and four bits from
hardware configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to
the selected MPC8250 clock operation mode as described in the following sections.
NOTE
Clock configurations change only after POR is asserted.
3.1
Local Bus Mode
Table 13 shows the eight basic clock configurations for the MPC8250. Another 49 configurations are
available by using the configuration pin (RSTCONF) and driving four pins on the data bus.
Table 13. Clock Default Configurations
Input Clock CPM Multiplication
CPM
Frequency
Core Multiplication
Factor
Core
Frequency
MODCK[1–3]
Frequency
Factor
000
001
010
011
33 MHz
33 MHz
33 MHz
33 MHz
3
3
4
4
100 MHz
100 MHz
133 MHz
133 MHz
4
5
4
5
133 MHz
166 MHz
133 MHz
166 MHz
MPC8250 Hardware Specifications, Rev. 2
20
Freescale Semiconductor
Clock Configuration Modes
Table 13. Clock Default Configurations
Input Clock CPM Multiplication
CPM
Frequency
Core Multiplication
Core
Frequency
MODCK[1–3]
Frequency
Factor
Factor
100
101
110
111
66 MHz
66 MHz
66 MHz
66 MHz
2
133 MHz
133 MHz
166 MHz
166 MHz
2.5
3
166 MHz
200 MHz
166 MHz
200 MHz
2
2.5
2.5
2.5
3
Table 14 describes all possible clock configurations when using the hard reset configuration sequence.
Note also that basic modes are shown in boldface type. The frequencies listed are for the purpose of
illustration only. Users must select a mode and input bus frequency so that the resulting configuration does
not exceed the frequency rating of the user’s device.
1
Table 14. Clock Configuration Modes
Input Clock CPM Multiplication
CPM
Frequency
Core Multiplication
Core
Frequency
MODCK_H–MODCK[1–3]
2,3
2
2
2
2
Frequency
Factor
Factor
0001_000
0001_001
0001_010
0001_011
0001_100
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
2
2
2
2
2
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
0001_101
0001_110
0001_111
0010_000
0010_001
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
3
3
3
3
3
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
0010_010
0010_011
0010_100
0010_101
0010_110
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
4
4
4
4
4
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
0010_111
0011_000
0011_001
0011_010
0011_011
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
5
5
5
5
5
166 MHz
166 MHz
166 MHz
166 MHz
166 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
21
Clock Configuration Modes
MODCK_H–MODCK[1–3]
1
Table 14. Clock Configuration Modes (continued)
Input Clock CPM Multiplication
CPM
Frequency
Core Multiplication
Core
Frequency
2,3
2
2
2
2
Frequency
Factor
Factor
0011_100
0011_101
0011_110
0011_111
0100_000
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
6
6
6
6
6
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
4
5
6
7
8
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
0100_001
0100_010
0100_011
0100_100
0100_101
0100_110
Reserved
0100_111
0101_000
0101_001
0101_010
0101_011
0101_100
Reserved
0101_101
0101_110
0101_111
0110_000
0110_001
0110_010
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
2
2
2
2
2
2
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
2
2.5
3
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3.5
4
4.5
0110_011
0110_100
0110_101
0110_110
0110_111
0111_000
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
2.5
2.5
2.5
2.5
2.5
2.5
166 MHz
166 MHz
166 MHz
166 MHz
166 MHz
166 MHz
2
2.5
3
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3.5
4
4.5
MPC8250 Hardware Specifications, Rev. 2
22
Freescale Semiconductor
Clock Configuration Modes
1
Table 14. Clock Configuration Modes (continued)
Input Clock CPM Multiplication
CPM
Frequency
Core Multiplication
Core
Frequency
MODCK_H–MODCK[1–3]
2,3
2
2
2
2
Frequency
Factor
Factor
0111_001
0111_010
0111_011
0111_100
0111_101
0111_110
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3
3
3
3
3
3
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
2
2.5
3
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3.5
4
4.5
0111_111
1000_000
1000_001
1000_010
1000_011
1000_100
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3.5
3.5
3.5
3.5
3.5
3.5
233 MHz
233 MHz
233 MHz
233 MHz
233 MHz
233 MHz
2
2.5
3
133 MHz
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3.5
4
4.5
1
2
Because of speed dependencies, not all of the possible configurations in Table 14 are applicable.
The user should choose the input clock frequency and the multiplication factors such that the frequency of the CPU
is equal to or greater than 133 MHz (150 MHz for extended temperature parts) and the CPM ranges between 66–233
MHz.
3
Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that the
resulting configuration does not exceed the frequency rating of the user’s part.
3.2
PCI Mode
The PCI mode is selected according to three input pins, as shown in Table 12. In addition, note the
following:
NOTE: PCI_MODCK
In PCI mode only, PCI_MODCK comes from the LGPL5 pin and
MODCK_H[0–3] comes from {LGPL0, LGPL1, LGPL2, LGPL3}.
NOTE: Tval (Output Hold)
The minimum Tval = 2 when PCI_MODCK = 1, and the minimum Tval = 1
when PCI_MODCK = 0. Therefore, designers should use clock
configurations that fit this condition to achieve PCI-compliant AC timing.
NOTE
Clock configurations change only after POR is asserted.
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
23
Clock Configuration Modes
3.2.1
PCI Host Mode
The frequencies listed in Table 15 are for the purpose of illustration only. Users must select a mode and
input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s
device.
Table 15. Clock Default Configurations in PCI Host Mode (MODCK_HI = 0000)
Input Clock
MODCK[1–3] Frequency Multiplication
CPM
Core
Multiplication
Factor
CPM
Frequency
Core
Frequency
PCI Division
Factor
PCI
Frequency
1
2
2
(Bus)
Factor
000
001
010
011
100
101
110
111
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
2
2
133 MHz
133 MHz
166 MHz
166 MHz
166 MHz
200 MHz
200 MHz
200 MHz
2.5
3
166 MHz
200 MHz
200 MHz
233 MHz
266 MHz
200 MHz
233 MHz
266 MHz
2/4
2/4
3/6
3/6
3/6
3/6
3/6
3/6
66/33 MHz
66/33 MHz
55/28 MHz
55/28 MHz
55/28 MHz
66/33 MHz
66/33 MHz
66/33 MHz
2.5
2.5
2.5
3
3
3.5
4
3
3
3.5
4
3
1
2
Assumes MODCK_HI = 0000.
The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is
divided by 2 (33 instead of 66 MHz, etc.) Refer to Table 12.
Table 16 describes all possible clock configurations when using the MPC8250’s internal PCI bridge in host
mode.
Table 16. Clock Configuration Modes in PCI Host Mode
MODCK_H
Input Clock
Frequency
(Bus)
CPM
Multiplication
Factor
Core
Multiplication
Factor
–
MODCK[1–
3]
CPM
Frequency
Core
Frequency
PCI Division
Factor
PCI
Frequency
1
2
2
0001_000
0001_001
0001_010
0001_011
33 MHz
33 MHz
33 MHz
33 MHz
3
3
3
3
100 MHz
100 MHz
100 MHz
100 MHz
5
6
7
8
166 MHz
200 MHz
233 MHz
266 MHz
3/6
3/6
3/6
3/6
33/16 MHz
33/16 MHz
33/16 MHz
33/16 MHz
0010_000
0010_001
0010_010
0010_011
33 MHz
33 MHz
33 MHz
33 MHz
4
4
4
4
133 MHz
133 MHz
133 MHz
133 MHz
5
6
7
8
166 MHz
200 MHz
233 MHz
266 MHz
4/8
4/8
4/8
4/8
33/16 MHz
33/16 MHz
33/16 MHz
33/16 MHz
3
0011_000
33 MHz
33 MHz
5
5
166 MHz
166 MHz
5
6
166 MHz
200 MHz
5
5
33 MHz
3
0011_001
33 MHz
MPC8250 Hardware Specifications, Rev. 2
24
Freescale Semiconductor
Clock Configuration Modes
Table 16. Clock Configuration Modes in PCI Host Mode (continued)
MODCK_H
Input Clock
Frequency
(Bus)
CPM
Multiplication
Factor
Core
Multiplication
Factor
–
MODCK[1–
3]
CPM
Frequency
Core
Frequency
PCI Division
Factor
PCI
Frequency
1
2
2
3
0011_010
33 MHz
33 MHz
5
5
166 MHz
166 MHz
7
8
233 MHz
266 MHz
5
5
33 MHz
33 MHz
3
0011_011
3
0100_000
33 MHz
33 MHz
33 MHz
33 MHz
6
6
6
6
200 MHz
200 MHz
200 MHz
200 MHz
5
6
7
8
166 MHz
200 MHz
233 MHz
266 MHz
6
6
6
6
33 MHz
33 MHz
33 MHz
33 MHz
3
0100_001
3
0100_010
3
0100_011
0101_000
0101_001
0101_010
0101_011
0101_100
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
2
2
2
2
2
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
2/4
2/4
2/4
2/4
2/4
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
3.5
4
4.5
0110_000
0110_001
0110_010
0110_011
0110_100
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
2.5
2.5
2.5
2.5
2.5
166 MHz
166 MHz
166 MHz
166 MHz
166 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3/6
3/6
3/6
3/6
3/6
55/28 MHz
55/28 MHz
55/28 MHz
55/28 MHz
55/28 MHz
3.5
4
4.5
0111_000
0111_001
0111_010
0111_011
0111_100
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3
3
3
3
3
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3/6
3/6
3/6
3/6
3/6
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
3.5
4
4.5
1000_000
1000_001
1000_010
1000_011
1000_100
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3
3
3
3
3
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
4/8
4/8
4/8
4/8
4/8
50/25 MHz
50/25 MHz
50/25 MHz
50/25 MHz
50/25 MHz
3.5
4
4.5
1001_000
66 MHz
3.5
233 MHz
2.5
166 MHz
4/8
58/29 MHz
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
25
Clock Configuration Modes
Table 16. Clock Configuration Modes in PCI Host Mode (continued)
MODCK_H
Input Clock
Frequency
(Bus)
CPM
Multiplication
Factor
Core
Multiplication
Factor
–
MODCK[1–
3]
CPM
Frequency
Core
Frequency
PCI Division
Factor
PCI
Frequency
1
2
2
1001_001
1001_010
1001_011
1001_100
66 MHz
66 MHz
66 MHz
66 MHz
3.5
3.5
3.5
3.5
233 MHz
233 MHz
233 MHz
233 MHz
3
200 MHz
233 MHz
266 MHz
300 MHz
4/8
4/8
4/8
4/8
58/29 MHz
58/29 MHz
58/29 MHz
58/29 MHz
3.5
4
4.5
1010_000
1010_001
1010_010
1010_011
1010_100
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
2
2
2
2
2
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
2
2.5
3
200 MHz
250 MHz
300 MHz
350 MHz
400 MHz
3/6
3/6
3/6
3/6
3/6
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
3.5
4
1011_000
1011_001
1011_010
1011_011
1011_100
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
2.5
2.5
2.5
2.5
2.5
250 MHz
250 MHz
250 MHz
250 MHz
250 MHz
2
2.5
3
200 MHz
250 MHz
300 MHz
350 MHz
400 MHz
4/8
4/8
4/8
4/8
4/8
62/31 MHz
62/31MHz
62/31 MHz
62/31 MHz
62/31 MHz
3.5
4
1
Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that
the resulting configuration does not exceed the frequency rating of the user’s part.
2
3
The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is
divided by 2 (33 instead of 66 MHz, etc.). Refer to Table 12
In this mode, PCI_MODCK must be “0”.
3.2.2
PCI Agent Mode
The frequencies listed in Table 17 are for the purpose of illustration only. Users must select a mode and
input bus frequency so that the resulting configuration does not exceed the frequency rating of the user’s
device.
Table 17. Clock Default Configurations in PCI Agent Mode (MODCK_HI = 0000)
Input Clock
CPM
Core
Multiplication
Factor
CPM
Frequency
Core
Frequency
Bus Division 60x Bus
1
MODCK[1–3] Frequency Multiplication
3
4
Factor
Frequency
2
2
(PCI)
Factor
000
001
010
011
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
2/4
2/4
3/6
3/6
133 MHz
133 MHz
200 MHz
200 MHz
2.5
3
166 MHz
200 MHz
200 MHz
266 MHz
2
2
3
3
66 MHz
66 MHz
66 MHz
66 MHz
3
4
MPC8250 Hardware Specifications, Rev. 2
26
Freescale Semiconductor
Clock Configuration Modes
Table 17. Clock Default Configurations in PCI Agent Mode (MODCK_HI = 0000)
Input Clock
CPM
Core
Multiplication
Factor
CPM
Frequency
Core
Frequency
Bus Division 60x Bus
1
MODCK[1–3] Frequency Multiplication
3
4
Factor
Frequency
2
2
(PCI)
Factor
100
101
110
111
66/33 MHz
66/33 MHz
66/33 MHz
66/33 MHz
3/6
3/6
4/8
4/8
200 MHz
200 MHz
266 MHz
266 MHz
3
3.5
3.5
3
240 MHz
280 MHz
300 MHz
300 MHz
2.5
2.5
3
80 MHz
80 MHz
88 MHz
100 MHz
2.5
1
2
Assumes MODCK_HI = 0000.
The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is divided
by 2 (33 instead of 66 MHz, etc.) and the CPM multiplication factor is multiplied by 2. Refer to Table 12
3
4
Core frequency = (60x bus frequency)(core multiplication factor)
Bus frequency = CPM frequency / bus division factor
Table 18 describes all possible clock configurations when using the MPC8250’s internal PCI bridge in
agent mode.
Table 18. Clock Configuration Modes in PCI Agent Mode
MODCK_H
Input Clock
CPM
Core
Multiplication
Factor
–
MODCK[1–
3]
CPM
Frequency
Core
Frequency
Bus Division 60x Bus
Frequency Multiplication
3
4
Factor
Frequency
1, 2
1
(PCI)
Factor
0001_001 66/33 MHz
0001_010 66/33 MHz
0001_011 66/33 MHz
0001_100 66/33 MHz
2/4
2/4
2/4
2/4
133 MHz
133 MHz
133 MHz
133 MHz
5
6
7
8
166 MHz
200 MHz
233 MHz
266 MHz
4
4
4
4
33 MHz
33 MHz
33 MHz
33 MHz
0010_001 50/25 MHz
0010_010 50/25 MHz
0010_011 50/25 MHz
0010_100 50/25 MHz
3/6
3/6
3/6
3/6
150 MHz
150 MHz
150 MHz
150 MHz
3
3.5
4
180 MHz
210 MHz
240 MHz
270 MHz
2.5
2.5
2.5
2.5
60 MHz
60 MHz
60 MHz
60 MHz
4.5
0011_000 66/33 MHz
0011_001 66/33 MHz
0011_010 66/33 MHz
0011_011 66/33 MHz
0011_100 66/33 MHz
2/4
2/4
2/4
2/4
2/4
133 MHz
133 MHz
133 MHz
133 MHz
133 MHz
2.5
3
110MHz
132 MHz
154 MHz
176MHz
198 MHz
3
3
3
3
3
44 MHz
44 MHz
44 MHz
44 MHz
44 MHz
3.5
4
4.5
0100_000 66/33 MHz
0100_001 66/33 MHz
0100_010 66/33 MHz
3/6
3/6
3/6
200 MHz
200 MHz
200 MHz
2.5
3
166 MHz
200 MHz
233 MHz
3
3
3
66 MHz
66 MHz
66 MHz
3.5
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
27
Clock Configuration Modes
Table 18. Clock Configuration Modes in PCI Agent Mode (continued)
MODCK_H
Input Clock
CPM
Core
Multiplication
Factor
–
MODCK[1–
3]
CPM
Frequency
Core
Frequency
Bus Division 60x Bus
Frequency Multiplication
3
4
Factor
Frequency
1, 2
1
(PCI)
Factor
0100_011 66/33 MHz
0100_100 66/33 MHz
3/6
3/6
200 MHz
200 MHz
4
266 MHz
300 MHz
3
3
66 MHz
66 MHz
4.5
5
0101_000
0101_001
0101_010
0101_011
0101_100
33 MHz
33 MHz
33 MHz
33 MHz
33 MHz
5
5
5
5
5
166 MHz
166 MHz
166 MHz
166 MHz
166 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
2.5
2.5
2.5
2.5
2.5
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
5
5
5
5
3.5
4
4.5
0110_000 50/25 MHz
0110_001 50/25 MHz
0110_010 50/25 MHz
0110_011 50/25 MHz
0110_100 50/25 MHz
4/8
4/8
4/8
4/8
4/8
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
3
3
3
3
3
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3.5
4
4.5
0111_000 66/33 MHz
0111_001 66/33 MHz
0111_010 66/33 MHz
0111_011 66/33 MHz
3/6
3/6
3/6
3/6
200 MHz
200 MHz
200 MHz
200 MHz
2
2.5
3
200 MHz
250 MHz
300 MHz
350 MHz
2
2
2
2
100 MHz
100 MHz
100 MHz
100 MHz
3.5
1000_000 66/33 MHz
1000_001 66/33 MHz
1000_010 66/33 MHz
1000_011 66/33 MHz
1000_100 66/33 MHz
1000_101 66/33 MHz
3/6
3/6
3/6
3/6
3/6
3/6
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
200 MHz
2
2.5
3
160 MHz
200 MHz
240 MHz
280 MHz
320 MHz
360 MHz
2.5
2.5
2.5
2.5
2.5
2.5
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
80 MHz
3.5
4
4.5
1001_000 66/33 MHz
1001_001 66/33 MHz
1001_010 66/33 MHz
1001_011 66/33 MHz
1001_100 66/33 MHz
4/8
4/8
4/8
4/8
4/8
266 MHz
266 MHz
266 MHz
266 MHz
266 MHz
2.5
3
166 MHz
200 MHz
233 MHz
266 MHz
300 MHz
4
4
4
4
4
66 MHz
66 MHz
66 MHz
66 MHz
66 MHz
3.5
4
4.5
MPC8250 Hardware Specifications, Rev. 2
28
Freescale Semiconductor
Pinout
Table 18. Clock Configuration Modes in PCI Agent Mode (continued)
MODCK_H
Input Clock
CPM
Core
Multiplication
Factor
–
MODCK[1–
3]
CPM
Frequency
Core
Frequency
Bus Division 60x Bus
Frequency Multiplication
3
4
Factor
Frequency
1, 2
1
(PCI)
Factor
1010_000 66/33 MHz
1010_001 66/33 MHz
1010_010 66/33 MHz
1010_011 66/33 MHz
1010_100 66/33 MHz
4/8
4/8
4/8
4/8
4/8
266 MHz
266 MHz
266 MHz
266 MHz
266 MHz
2.5
3
222 MHz
266 MHz
300 MHz
350 MHz
400 MHz
3
3
3
3
3
88 MHz
88 MHz
88 MHz
88 MHz
88 MHz
3.5
4
4.5
1011_000 66/33 MHz
1011_001 66/33 MHz
1011_010 66/33 MHz
1011_011 66/33 MHz
1011_100 66/33 MHz
4/8
4/8
4/8
4/8
4/8
266 MHz
266 MHz
266 MHz
266 MHz
266 MHz
2
2.5
3
212MHz
265 MHz
318 MHz
371 MHz
424 MHz
2.5
2.5
2.5
2.5
2.5
106 MHz
106 MHz
106 MHz
106 MHz
106 MHz
3.5
4
1
2
The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is
divided by 2 (33 instead of 66 MHz, etc.) and the CPM multiplication factor is multiplied by 2. Refer to Table 12
Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that
the resulting configuration does not exceed the frequency rating of the user’s part.
3
4
5
Core frequency = (60x bus frequency)(core multiplication factor)
Bus frequency = CPM frequency / bus division factor
In this mode, PCI_MODCK must be “1”.
4 Pinout
This section provides the pin assignments and pinout list for the MPC8250.
4.1
TBGA Package
The following figures and table represent the standard 480 TBGA package. For information on the
alternate package, refer to Section 4.2, “PBGA Package.”
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
29
Pinout
4.1.1
TBGA Pin Assignments
Figure 13 shows the pinout of the TBGA package as viewed from the top surface.
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
A
B
A
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
N
M
N
P
P
R
R
T
T
U
U
V
V
W
Y
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
AA
AB
AC
AD
AE
AF
AG
AH
AJ
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29
Not to Scale
Figure 13. Pinout of the 480 TBGA Package as Viewed from the Top Surface
MPC8250 Hardware Specifications, Rev. 2
30
Freescale Semiconductor
Pinout
Figure 14 shows the side profile of the TBGA package to indicate the direction of the top surface view.
View
Pressure Sensitive
Adhesive
Copper Heat Spreader
(Oxidized for Insulation)
Etched
Cavity
Die
Attach
Polymide Tape
Die
Soldermask
Glob-Top Filled Area
Glob-Top Dam
Copper Traces
1.27 mm Pitch
Wire Bonds
Figure 14. Side View of the TBGA Package
Table 20 shows the pinout list of the TBGA package of the MPC8250. Table 19 defines the conventions
and acronyms used in Table 20.
Table 19. Symbol Legend
Symbol
Meaning
OVERBAR
MII
Signals with overbars, such as TA, are active low.
Indicates that a signal is part of the media independent interface.
Table 20. MPC8250 TBGA Package Pinout List
Pin Name
Ball
BR
W5
F4
E2
E3
G1
H5
H2
H1
J5
BG
ABB/IRQ2
TS
A0
A1
A2
A3
A4
A5
J4
A6
J3
A7
J2
A8
J1
A9
K4
K3
K2
K1
A10
A11
A12
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
31
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
A13
L5
L4
A14
A15
L3
A16
L2
A17
L1
A18
M5
N5
N4
N3
N2
N1
P4
P3
P2
P1
R1
R3
R5
R4
F1
G4
G3
G2
F2
D3
C1
E4
D2
F5
F3
E1
V1
V2
B20
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
TT0
TT1
TT2
TT3
TT4
TBST
TSIZ0
TSIZ1
TSIZ2
TSIZ3
AACK
ARTRY
DBG
DBB/IRQ3
D0
D1
MPC8250 Hardware Specifications, Rev. 2
32
Freescale Semiconductor
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
D2
A16
A13
E12
D9
D3
D4
D5
D6
A6
D7
B5
D8
A20
E17
B15
B13
A11
E9
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
B7
B4
D19
D17
D15
C13
B11
A8
A5
C5
C19
C17
C15
D13
C11
B8
A4
E6
E18
B17
A15
A12
D11
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
33
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
D37
C8
E7
D38
D39
A3
D40
D18
A17
A14
B12
A10
D8
D41
D42
D43
D44
D45
D46
B6
D47
C4
D48
C18
E16
B14
C12
B10
A7
D49
D50
D51
D52
D53
D54
C6
D55
D5
D56
B18
B16
E14
D12
C10
E8
D57
D58
D59
D60
D61
D62
D6
D63
C2
DP0/RSRV/EXT_BR2
IRQ1/DP1/EXT_BG2
B22
A22
E21
D21
C21
B21
A21
E20
IRQ2/DP2/TLBISYNC/EXT_DBG2
IRQ3/DP3/CKSTP_OUT/EXT_BR3
IRQ4/DP4/CORE_SRESET/EXT_BG3
IRQ5/DP5/TBEN/EXT_DBG3
IRQ6/DP6/CSE0
IRQ7/DP7/CSE1
MPC8250 Hardware Specifications, Rev. 2
34
Freescale Semiconductor
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
PSDVAL
V3
C22
V5
TA
TEA
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
W1
U2
U3
Y4
CPU_BG/BADDR31/IRQ5
U4
CPU_DBG
R2
CPU_BR
Y3
CS0
F25
C29
E27
E28
F26
F27
F28
G25
D29
E29
F29
G28
T5
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10/BCTL1
CS11/AP0
BADDR27
BADDR28
U1
ALE
T2
BCTL0
A27
C25
E24
D24
C24
B26
A26
B25
A25
E23
PWE0/PSDDQM0/PBS0
PWE1/PSDDQM1/PBS1
PWE2/PSDDQM2/PBS2
PWE3/PSDDQM3/PBS3
PWE4/PSDDQM4/PBS4
PWE5/PSDDQM5/PBS5
PWE6/PSDDQM6/PBS6
PWE7/PSDDQM7/PBS7
PSDA10/PGPL0
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
35
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
PSDWE/PGPL1
B24
A24
B23
A23
D22
H28
H27
H26
G29
D27
C28
E26
D25
C26
B27
D28
N27
T29
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LWE0/LSDDQM0/LBS0/PCI_CFG0
LWE1/LSDDQM1/LBS1/PCI_CFG1
LWE2/LSDDQM2/LBS2/PCI_CFG2
LWE3/LSDDQM3/LBS3/PCI_CFG3
LSDA10/LGPL0/PCI_MODCKH0
LSDWE/LGPL1/PCI_MODCKH1
LOE/LSDRAS/LGPL2/PCI_MODCKH2
LSDCAS/LGPL3/PCI_MODCKH3
LGTA/LUPMWAIT/LGPL4/LPBS
LGPL5/LSDAMUX/PCI_MODCK
LWR
L_A14/PAR
L_A15/FRAME/SMI
L_A16/TRDY
R27
R26
R29
R28
W29
P28
N26
AA27
P29
AA26
N25
AA25
AB29
AB28
P25
AB27
H29
L_A17/IRDY/CKSTP_OUT
L_A18/STOP
L_A19/DEVSEL
L_A20/IDSEL
L_A21/PERR
L_A22/SERR
L_A23/REQ0
L_A24/REQ1/HSEJSW
L_A25/GNT0
L_A26/GNT1/HSLED
L_A27/GNT2/HSENUM
L_A28/RST/CORE_SRESET
L_A29/INTA
L_A30/REQ2
L_A31/DLLOUT
LCL_D0/AD0
MPC8250 Hardware Specifications, Rev. 2
36
Freescale Semiconductor
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
LCL_D1/AD1
J29
J28
LCL_D2/AD2
LCL_D3/AD3
J27
LCL_D4/AD4
J26
LCL_D5/AD5
J25
LCL_D6/AD6
K25
L29
LCL_D7/AD7
LCL_D8/AD8
L27
LCL_D9/AD9
L26
LCL_D10/AD10
LCL_D11/AD11
LCL_D12/AD12
LCL_D13/AD13
LCL_D14/AD14
LCL_D15/AD15
LCL_D16/AD16
LCL_D17/AD17
LCL_D18/AD18
LCL_D19/AD19
LCL_D20/AD20
LCL_D21/AD21
LCL_D22/AD22
LCL_D23/AD23
LCL_D24/AD24
LCL_D25/AD25
LCL_D26/AD26
LCL_D27/AD27
LCL_D28/AD28
LCL_D29/AD29
LCL_D30/AD30
LCL_D31/AD31
LCL_DP0/C0/BE0
LCL_DP1/C1/BE1
LCL_DP2/C2/BE2
LCL_DP3/C3/BE3
L25
M29
M28
M27
M26
N29
T25
U27
U26
U25
V29
V28
V27
V26
W27
W26
W25
Y29
Y28
Y25
AA29
AA28
L28
N28
T28
W28
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
37
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
IRQ0/NMI_OUT
T1
D1
IRQ7/INT_OUT/APE
TRST
AH3
AG5
AJ3
AE6
AF5
AB4
AG6
AH5
AF6
AA3
AJ4
W2
TCK
TMS
TDI
TDO
TRIS
PORESET
HRESET
SRESET
QREQ
RSTCONF
MODCK1/AP1/TC0/BNKSEL0
MODCK2/AP2/TC1/BNKSEL1
MODCK3/AP3/TC2/BNKSEL2
XFC
W3
W4
AB2
AH4
AC29
AC25
AE28
CLKIN1
1
1
1
1
PA0/RESTART1/DREQ3
PA1/REJECT1/DONE3
PA2/CLK20/DACK3
PA3/CLK19/DACK4/L1RXD1A2
PA4/REJECT2/DONE4
PA5/RESTART2/DREQ4
PA6
AG29
AG28
AG26
1
1
1
AE24
AH25
1
PA7/SMSYN2
1
PA8/SMRXD2
AF23
1
PA9/SMTXD2
AH23
AE22
AH22
1
1
PA10/MSNUM5
PA11/MSNUM4
1
PA12/MSNUM3
AJ21
1
PA13/MSNUM2
AH20
AG19
1
PA14/FCC1_RXD3
PA15/FCC1_RXD2
PA16/FCC1_RXD1
1
AF18
AF17
1
MPC8250 Hardware Specifications, Rev. 2
38
Freescale Semiconductor
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
1
PA17/FCC1_RXD0/FCC1_RXD
AE16
1
PA18/FCC1_TXD0/FCC1_TXD
PA19/FCC1_TXD1
AJ16
1
AG15
1
PA20/FCC1_TXD2
AJ13
AE13
AF12
1
1
1
PA21/FCC1_TXD3
PA22
PA23
AG11
1
PA24/MSNUM1
AH9
1
PA25/MSNUM0
AJ8
1
PA26/FCC1_MII_RX_ER
AH7
1
PA27/FCC1_MII_RX_DV
AF7
1
PA28/FCC1_MII_TX_EN
AD5
1
PA29/FCC1_MII_TX_ER
AF1
AD3
1
PA30/FCC1_MII_CRS/FCC1_RTS
PA31/FCC1_MII_COL
1
AB5
1
1
1
1
1
1
PB4/FCC3_TXD3/L1RSYNCA2/FCC3_RTS
PB5/FCC3_TXD2/L1TSYNCA2/L1GNTA2
PB6/FCC3_TXD1/L1RXDA2/L1RXD0A2
PB7/FCC3_TXD0/FCC3_TXD/L1TXDA2/L1TXD0A2
PB8/FCC3_RXD0/FCC3_RXD/TXD3
PB9/FCC3_RXD1/L1TXD2A2
PB10/FCC3_RXD2
AD28
AD26
AD25
AE26
AH27
AG24
AH24
1
1
1
PB11/FCC3_RXD3
AJ24
PB12/FCC3_MII_CRS/TXD2
PB13/FCC3_MII_COL/L1TXD1A2
PB14/FCC3_MII_TX_EN/RXD3
PB15/FCC3_MII_TX_ER/RXD2
PB16/FCC3_MII_RX_ER/CLK18
PB17/FCC3_MII_RX_DV/CLK17
PB18/FCC2_RXD3/L1CLKOD2/L1RXD2A2
PB19/FCC2_RXD2/L1RQD2/L1RXD3A2
PB20/FCC2_RXD1/L1RSYNCD2/L1TXD1A1
PB21/FCC2_RXD0/FCC2_RXD/L1TSYNCD2/L1GNTD2
PB22/FCC2_TXD0/FCC2_TXD/L1RXDD2
PB23/FCC2_TXD1/L1TXDD2
AG22
AH21
AG20
1
1
1
AF19
1
1
1
AJ18
AJ17
AE14
AF13
1
1
AG12
AH11
AH16
1
1
1
AE15
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
39
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
1
PB24/FCC2_TXD2/L1RSYNCC2
AJ9
AE9
1
PB25/FCC2_TXD3/L1TSYNCC2/L1GNTC2
PB26/FCC2_MII_CRS/L1RXDC2
PB27/FCC2_MII_COL/L1TXDC2
PB28/FCC2_MII_RX_ER/FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1
PB29/L1RSYNCB2/FCC2_MII_TX_EN
PB30/FCC2_MII_RX_DV/L1RXDB2
PB31/FCC2_MII_TX_ER/L1TXDB2
PC0/DREQ1/BRGO7/SMSYN2/L1CLKOA2
PC1/DREQ2/BRGO6/L1RQA2
PC2/FCC3_CD/DONE2
1
1
AJ7
AH6
1
AE3
AE2
AC5
AC4
1
1
1
1
1
1
1
AB26
AD29
AE29
AE27
PC3/FCC3_CTS/DACK2/CTS4
PC4/SI2_L1ST4/FCC2_CD
PC5/SI2_L1ST3/FCC2_CTS
PC6/FCC1_CD
1
1
AF27
AF24
1
1
1
AJ26
AJ25
PC7/FCC1_CTS
PC8/CD4/RENA4/SI2_L1ST2/CTS3
PC9/CTS4/CLSN4/SI2_L1ST1/L1TSYNCA2/L1GNTA2
PC10/CD3/RENA3
AF22
AE21
AF20
AE19
AE18
1
1
1
1
1
PC11/CTS3/CLSN3/L1TXD3A2
PC12/CD2/RENA2
PC13/CTS2/CLSN2
AH18
AH17
AG16
1
1
PC14/CD1/RENA1
PC15/CTS1/CLSN1/SMTXD2
PC16/CLK16/TIN4
1
AF15
1
PC17/CLK15/TIN3/BRGO8
PC18/CLK14/TGATE2
AJ15
1
AH14
AG13
AH12
1
1
PC19/CLK13/BRGO7/SPICLK
PC20/CLK12/TGATE1
1
PC21/CLK11/BRGO6
AJ11
1
PC22/CLK10/DONE1
AG10
1
PC23/CLK9/BRGO5/DACK1
PC24/CLK8/TOUT4
AE10
1
AF9
AE8
1
PC25/CLK7/BRGO4
1
PC26/CLK6/TOUT3/TMCLK
AJ6
MPC8250 Hardware Specifications, Rev. 2
40
Freescale Semiconductor
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
1
PC27/FCC3_TXD/FCC3_TXD0/CLK5/BRGO3
AG2
1
PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2
PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1
PC30/CLK2/TOUT1
PC31/CLK1/BRGO1
PD4/BRGO8/FCC3_RTS/SMRXD2
PD5/DONE1
AF3
AF2
1
1
AE1
AD1
1
1
1
AC28
AD27
1
1
1
PD6/DACK1
AF29
AF28
PD7/SMSYN1FCC1_TXCLAV2
PD8/SMRXD1/BRGO5
PD9/SMTXD1/BRGO3
PD10/L1CLKOB2/BRGO4
PD11/L1RQB2
AG25
AH26
1
1
1
1
AJ27
AJ23
PD12
AG23
1
PD13
AJ22
AE20
1
PD14/L1CLKOC2/I2CSCL
PD15/L1RQC2/I2CSDA
PD16/SPIMISO
1
AJ20
1
AG18
AG17
1
PD17/BRGO2/SPIMOSI
PD18/SPICLK
1
AF16
1
PD19/SPISEL/BRGO
PD20/RTS4/TENA4/L1RSYNCA2
PD21/TXD4/L1RXD0A2/L1RXDA2
PD22/RXD4/L1TXD0A2/L1TXDA2
PD23/RTS3/TENA3
PD24/TXD3
AH15
1
AJ14
AH13
1
1
AJ12
1
AE12
AF10
1
1
PD25/RXD3
AG9
AH8
AG7
1
PD26/RTS2/TENA2
PD27/TXD2
1
1
PD28/RXD2
AE4
1
PD29/RTS1/TENA1
PD30/TXD1
AG1
AD4
AD2
1
1
PD31/RXD1
VCCSYN
AB3
B9
VCCSYN1
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
41
Pinout
Table 20. MPC8250 TBGA Package Pinout List (continued)
Pin Name
Ball
GNDSYN
AB1
AE11
U5
CLKIN2
SPARE4
2
3
PCI_MODE
AF25
V4
2
SPARE6
4
THERMAL0
THERMAL1
I/O power
AA1
AG4
4
AG21, AG14, AG8, AJ1, AJ2, AH1,
AH2, AG3, AF4, AE5, AC27, Y27,
T27, P27, K26, G27, AE25, AF26,
AG27, AH28, AH29, AJ28, AJ29,
C7, C14, C16, C20, C23, E10, A28,
A29, B28, B29, C27, D26, E25, H3,
M4, T3, AA4, A1, A2, B1, B2, C3,
D4, E5
Core Power
Ground
U28, U29, K28, K29, A9, A19, B19,
M1, M2, Y1, Y2, AC1, AC2, AH19,
AJ19, AH10, AJ10, AJ5
AA5, AF21, AF14, AF8, AE7, AF11,
AE17, AE23, AC26, AB25, Y26,
V25, T26, R25, P26, M25, K27, H25,
G26, D7, D10, D14, D16, D20, D23,
C9, E11, E13, E15, E19, E22, B3,
G5, H4, K5, M3, P5, T4, Y5, AA2,
AC3
1
The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive
DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.
2
3
4
Must be pulled down or left floating.
If PCI is not desired, this pin should be pulled up or left floating.
For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide (AN2271/D)
available at www.freescale.com.
4.2
PBGA Package
The following figures and table represent the alternate 516 PBGA package. For information on the
standard package for the MPC8250, refer to Section 4.1, “TBGA Package.”
MPC8250 Hardware Specifications, Rev. 2
42
Freescale Semiconductor
Pinout
4.2.1
PBGA Pin Assignments
Figure 15 shows the pinout of the PBGA package as viewed from the top surface.
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
A
B
A
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
K
K
L
L
M
N
M
N
P
P
R
R
T
T
U
U
V
V
W
Y
W
Y
AA
AB
AC
AD
AE
AF
AA
AB
AC
AD
AE
AF
1
2
3
4
5 6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Not to Scale
Figure 15. Pinout of the 516 PBGA Package (View from Top)
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
43
Pinout
Figure 16 shows the side profile of the PBGA package to indicate the direction of the top surface view.
Wire bonds
Ball bond
Die
attach
Transfer molding compound
Screen-printed
solder mask
Plated substrate via
Cu substrate traces
BT resin glass epoxy
DIE
1 mm pitch
Figure 16. Side View of the PBGA Package
Table 22 shows the pinout list of the PBGA package of the MPC8250. Table 21 defines conventions and
acronyms used in Table 22.
Table 21. Symbol Legend
Symbol
Meaning
OVERBAR
MII
Signals with overbars, such as TA, are active low.
Indicates that a signal is part of the media independent interface.
Table 22. MPC8250 PBGA Package Pinout List
Pin Name
Ball
BR
C16
D2
C1
D1
D5
E8
C4
B4
A4
D7
D8
C6
B5
B6
C7
C8
A6
D9
BG
ABB/IRQ2
TS
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
MPC8250 Hardware Specifications, Rev. 2
44
Freescale Semiconductor
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
A14
F11
B7
A15
A16
B8
A17
C9
A18
A7
A19
B9
A20
E11
A8
A21
A22
D11
B10
C11
A9
A23
A24
A25
A26
B11
C12
D12
A10
B12
B13
E7
A27
A28
A29
A30
A31
TT0
TT1
B3
TT2
F8
TT3
A3
TT4
C3
TBST
TSIZ0
TSIZ1
TSIZ2
TSIZ3
AACK
ARTRY
DBG
DBB/IRQ3
D0
F5
E3
E2
E1
E4
D3
C2
A14
C15
W4
Y1
D1
D2
V1
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
45
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
D3
P4
N3
K5
J4
D4
D5
D6
D7
G1
AB1
U4
U2
N6
N1
L1
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
J5
G3
AA2
W1
T3
T1
M2
K2
J1
G4
U5
T5
P5
P3
M3
K3
H2
G5
AA1
V2
U1
P2
M4
K4
MPC8250 Hardware Specifications, Rev. 2
46
Freescale Semiconductor
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
D38
H3
F2
D39
D40
Y2
D41
U3
T2
D42
D43
N2
M5
K1
D44
D45
D46
H4
F1
D47
D48
W2
T4
D49
D50
R3
N4
M1
J2
D51
D52
D53
D54
H5
F3
D55
D56
V3
D57
R5
R2
N5
L2
D58
D59
D60
D61
J3
D62
H1
F4
D63
DP0/RSRV/EXT_BR2
IRQ1/DP1/EXT_BG2
AB3
W5
AC2
AA3
AD1
AC1
AB2
Y3
IRQ2/DP2/TLBISYNC/EXT_DBG2
IRQ3/DP3/CKSTP_OUT/EXT_BR3
IRQ4/DP4/CORE_SRESET/EXT_BG3
IRQ5/DP5/TBEN/EXT_DBG3
IRQ6/DP6/CSE0
IRQ7/DP7/CSE1
PSDVAL
D15
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
47
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
TA
Y4
TEA
D16
E15
D14
E14
A17
B14
F13
B17
AC6
AD6
AE6
AB7
AF7
AC7
AD7
AF8
AE8
AD8
AC8
AB8
C13
A12
D13
AF4
AA5
AE4
AD4
AF3
AB4
AE3
AF2
AD3
AE2
AD2
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5
CPU_DBG
CPU_BR
CS0
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10/BCTL1
CS11/AP0
BADDR27
BADDR28
ALE
BCTL0
PWE0/PSDDQM0/PBS0
PWE1/PSDDQM1/PBS1
PWE2/PSDDQM2/PBS2
PWE3/PSDDQM3/PBS3
PWE4/PSDDQM4/PBS4
PWE5/PSDDQM5/PBS5
PWE6/PSDDQM6/PBS6
PWE7/PSDDQM7/PBS7
PSDA10/PGPL0
PSDWE/PGPL1
MPC8250 Hardware Specifications, Rev. 2
48
Freescale Semiconductor
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
AE1
AC3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
W6
AA4
LWE0/LSDDQM0/LBS0/PCI_CFG0
LWE1/LSDDQM1/LBS1/PCI_CFG1
LWE2/LSDDQM2/LBS2/PCI_CFG2
LWE3/LSDDQM3/LBS3/PCI_CFG3
LSDA10/LGPL0/PCI_MODCKH0
LSDWE/LGPL1/PCI_MODCKH1
LOE/LSDRAS/LGPL2/PCI_MODCKH2
LSDCAS/LGPL3/PCI_MODCKH3
LGTA/LUPMWAIT/LGPL4/LPBS
LGPL5/LSDAMUX/PCI_MODCK
LWR
AC9
AD9
AE9
AF9
AB6
AF5
AE5
AD5
AC5
AB5
AF6
L_A14/PAR
AE13
AD15
AF16
AF15
AE15
AE14
AC17
AD14
AF13
AE20
AC14
AC19
AD13
AF21
AF22
AE21
AB14
AD20
AB9
L_A15/FRAME/SMI
L_A16/TRDY
L_A17/IRDY/CKSTP_OUT
L_A18/STOP
L_A19/DEVSEL
L_A20/IDSEL
L_A21/PERR
L_A22/SERR
L_A23/REQ0
L_A24/REQ1/HSEJSW
L_A25/GNT0
L_A26/GNT1/HSLED
L_A27/GNT2/HSENUM
L_A28/RST/CORE_SRESET
L_A29/INTA
L_A30/REQ2
L_A31/DLLOUT
LCL_D0/AD0
LCL_D1/AD1
AB10
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
49
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
LCL_D2/AD2
AC10
AD10
AE10
AF10
AF11
AB12
AB11
AF12
AE11
AC13
AC12
AB13
AD12
AF14
AF17
AE16
AD16
AC16
AB16
AF18
AE17
AD17
AB17
AE18
AD18
AC18
AE19
AF20
AD19
AB18
AE12
AA13
AC15
AF19
A11
LCL_D3/AD3
LCL_D4/AD4
LCL_D5/AD5
LCL_D6/AD6
LCL_D7/AD7
LCL_D8/AD8
LCL_D9/AD9
LCL_D10/AD10
LCL_D11/AD11
LCL_D12/AD12
LCL_D13/AD13
LCL_D14/AD14
LCL_D15/AD15
LCL_D16/AD16
LCL_D17/AD17
LCL_D18/AD18
LCL_D19/AD19
LCL_D20/AD20
LCL_D21/AD21
LCL_D22/AD22
LCL_D23/AD23
LCL_D24/AD24
LCL_D25/AD25
LCL_D26/AD26
LCL_D27/AD27
LCL_D28/AD28
LCL_D29/AD29
LCL_D30/AD30
LCL_D31/AD31
LCL_DP0/C0/BE0
LCL_DP1/C1/BE1
LCL_DP2/C2/BE2
LCL_DP3/C3/BE3
IRQ0/NMI_OUT
MPC8250 Hardware Specifications, Rev. 2
50
Freescale Semiconductor
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
IRQ7/INT_OUT/APE
TRST
E5
F22
TCK
A24
C24
A25
B24
C19
B25
D24
E23
D18
E24
B16
F16
TMS
TDI
TDO
TRIS
PORESET
HRESET
SRESET
QREQ
RSTCONF
MODCK1/AP1/TC0/BNKSEL0
MODCK2/AP2/TC1/BNKSEL1
MODCK3/AP3/TC2/BNKSEL2
XFC
A15
A18
G22
AC20
AC21
CLKIN1
1
1
PA0/RESTART1/DREQ3
PA1/REJECT1/DONE3
PA2/CLK20/DACK3
PA3/CLK19/DACK4/L1RXD1A2
PA4/REJECT2/DONE4
PA5/RESTART2/DREQ4
PA6
1
1
1
1
AF25
AE24
AA21
AD25
AC24
AA22
AA23
1
1
1
PA7/SMSYN2
PA8/SMRXD2
1
PA9/SMTXD2
Y26
1
1
PA10/MSNUM5
W22
W23
PA11/MSNUM4
1
PA12/MSNUM3
V26
V25
1
PA13/MSNUM2
1
1
1
PA14/FCC1_RXD3
PA15/FCC1_RXD2
PA16/FCC1_RXD1
PA17/FCC1_RXD0/FCC1_RXD
T22
T25
R24
1
P22
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
51
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
1
PA18/FCC1_TXD0/FCC1_TXD
N26
N23
1
PA19/FCC1_TXD1
1
PA20/FCC1_TXD2
K26
1
PA21/FCC1_TXD3
L23
1
PA22
K23
H26
1
PA23
1
PA24/MSNUM1
F25
1
PA25/MSNUM0
D26
D25
C25
C22
1
1
1
PA26/FCC1_MII_RX_ER
PA27/FCC1_MII_RX_DV
PA28/FCC1_MII_TX_EN
1
1
1
PA29/FCC1_MII_TX_ER
B21
A20
A19
PA30/FCC1_MII_CRS/FCC1_RTS
PA31/FCC1_MII_COL
1
PB4/FCC3_TXD3/L1RSYNCA2/ FCC3_RTS
PB5/FCC3_TXD2/L1TSYNCA2/ L1GNTA2
PB6/FCC3_TXD1/L1RXDA2/L1RXD0A2
PB7/FCC3_TXD0/FCC3_TXD/ L1TXDA2/L1TXD0A2
PB8/FCC3_RXD0/FCC3_RXD/TXD3
PB9/FCC3_RXD1/L1TXD2A2
PB10/FCC3_RXD2
AD21
AD22
AC22
AE26
AB23
AC26
AB26
AA25
1
1
1
1
1
1
1
PB11/FCC3_RXD3
1
PB12/FCC3_MII_CRS/TXD2
PB13/FCC3_MII_COL/L1TXD1A2
PB14/FCC3_MII_TX_EN/RXD3
PB15/FCC3_MII_TX_ER/RXD2
PB16/FCC3_MII_RX_ER/CLK18
PB17/FCC3_MII_RX_DV/CLK17
PB18/FCC2_RXD3/L1CLKOD2/ L1RXD2A2
PB19FCC2_RXD2/L1RQD2/L1RXD3A2
PB20/FCC2_RXD1/L1RSYNCD2/ L1TXD1A1
PB21/FCC2_RXD0/FCC2_RXD/ L1TSYNCD2/L1GNTD2
PB22/FCC2_TXD0/FCC2_TXD/ L1RXDD2
PB23/FCC2_TXD1/L1TXDD2
PB24/FCC2_TXD2/L1RSYNCC2
W26
W25
1
1
V24
U24
R22
R23
1
1
1
1
M23
1
L24
K24
1
1
L21
1
P25
N25
1
1
E26
MPC8250 Hardware Specifications, Rev. 2
52
Freescale Semiconductor
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
1
PB25/FCC2_TXD3/L1TSYNCC2/ L1GNTC2
H23
C26
1
PB26/FCC2_MII_CRS/L1RXDC2
PB27/FCC2_MII_COL/L1TXDC2
PB28/FCC2_MII_RX_ER/FCC2_RTS/ L1TSYNCB2/L1GNTB2/TXD1
PB29/L1RSYNCB2/ FCC2_MII_TX_EN
PB30/FCC2_MII_RX_DV/L1RXDB2
PB31/FCC2_MII_TX_ER/L1TXDB2
PC0/DREQ1/BRGO7/SMSYN2/ L1CLKOA2
PC1/DREQ2/BRGO6/L1RQA2
PC2/FCC3_CD/DONE2
1
1
1
1
1
B26
A22
A21
E20
C20
1
1
1
1
1
1
AE22
AA19
AF24
AE25
AB22
PC3/FCC3_CTS/DACK2/CTS4
PC4/SI2_L1ST4/FCC2_CD
PC5/SI2_L1ST3/FCC2_CTS
PC6/FCC1_CD
AC25
AB25
AA24
1
1
PC7/FCC1_CTS
1
PC8/CD4/RENA4/SI2_L1ST2/CTS3
PC9/CTS4/CLSN4/SI2_L1ST1/ L1TSYNCA2/L1GNTA2
PC10/CD3/RENA3
Y24
1
U22
1
V23
U23
1
PC11/CTS3/CLSN3/L1TXD3A2
PC12/CD2/RENA2
1
T26
1
PC13/CTS2/CLSN2
R26
1
PC14/CD1/RENA1
P26
P24
1
1
PC15/CTS1/CLSN1/SMTXD2
PC16/CLK16/TIN4
M26
1
PC17/CLK15/TIN3/BRGO8
PC18/CLK14/TGATE2
L26
1
1
M24
1
PC19/CLK13/BRGO7/SPICLK
PC20/CLK12/TGATE1
L22
K25
1
PC21/CLK11/BRGO6
J25
1
PC22/CLK10/DONE1
G26
1
PC23/CLK9/BRGO5/DACK1
PC24/CLK8/TOUT4
F26
1
G24
1
PC25/CLK7/BRGO4
E25
G23
1
PC26/CLK6/TOUT3/TMCLK
PC27/FCC3_TXD/FCC3_TXD0/CLK5/ BRGO3
1
B23
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
53
Pinout
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
1
PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2
E22
E21
1
PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1
PC30/CLK2/TOUT1
PC31/CLK1/BRGO1
PD4/BRGO8/FCC3_RTS/SMRXD2
PD5/DONE1
1
D21
1
B20
1
1
1
1
AF23
AE23
AB21
PD6/DACK1
PD7/SMSYN1/FCC1_TXCLAV2
PD8/SMRXD1/BRGO5
PD9/SMTXD1/BRGO3
PD10/L1CLKOB2/BRGO4
PD11/L1RQB2
AD23
AD26
1
1
Y22
1
AB24
1
Y23
1
PD12
AA26
1
PD13
W24
1
PD14/L1CLKOC2/I2CSCL
PD15/L1RQC2/I2CSDA
PD16/SPIMISO
V22
U26
1
1
T23
1
PD17/BRGO2/SPIMOSI
PD18/SPICLK
R25
1
P23
N22
1
1
PD19/SPISEL/BRGO1
PD20/RTS4/TENA4/L1RSYNCA2
PD21/TXD4/L1RXD0A2/L1RXDA2
PD22/RXD4L1TXD0A2/L1TXDA2
PD23/RTS3/TENA3
PD24/TXD3
M25
1
L25
1
J26
1
1
K22
G25
1
PD25/RXD3
H24
1
PD26/RTS2/TENA2
PD27/TXD2
F24
H22
1
1
1
PD28/RXD2
B22
PD29/RTS1/TENA1
PD30/TXD1
D22
C21
1
1
PD31/RXD1
E19
VCCSYN
D19
K6
VCCSYN1
GNDSYN
B18
MPC8250 Hardware Specifications, Rev. 2
54
Freescale Semiconductor
Package Description
Table 22. MPC8250 PBGA Package Pinout List (continued)
Pin Name
Ball
CLKIN2
SPARE4
K21
C14
AD24
B15
2
3
PCI_MODE
2
SPARE6
4
THERMAL0
THERMAL1
I/O power
E17
4
C23
E6, F6, H6, L5, L6, P6, T6, U6, V5,
Y5, AA6, AA8, AA10, AA11, AA14,
AA16, AA17, AB19, AB20, W21,
U21, T21, P21, N21, M22, J22,
H21, F21, F19, F17, E16, F14,
E13, E12, F10, E10, E9
Core Power
Ground
L3, V4, W3, AC11, AD11, AB15,
U25, T24, J24, H25, F23, B19,
D17, C17, D10, C10
A2, B1, B2, A5, C5, C18, D4, D6,
G2, L4, P1, R1, R4, AC4, AE7,
AC23, Y25, N24, J23, A23, D23,
D20, E18, A13, A16, K10, K11,
K12, K13, K14, K15, K16, K17,
L10, L11, L12, L13, L14, L15, L16,
L17, M10, M11, M12, M13, M14,
M15, M16, M17, N10, N11, N12,
N13, N14, N15, N16, N17, P10,
P11, P12, P13, P14, P15, P16,
P17, R10, R11,R12, R13, R14,
R15, R16, R17, T10, T11, T12,
T13, T14, T15, T16, T17, U10,
U11, U12, U13, U14, U15, U16,
U17
1
The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive
DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.
2
3
4
Must be pulled down or left floating.
If PCI is not desired, must be pulled up or left floating.
For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide (AN2271/D).
5 Package Description
The following sections provide the package parameters and mechanical dimensions.
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
55
Package Description
5.1
Package Parameters
Package parameters are provided in Table 23.
Table 23. Package Parameters
Outline
(mm)
Pitch
(mm)
Nominal Unmounted
Height (mm)
Package
Devices
MPC8250
Type
Interconnects
ZU
VV
ZO
VR
37.5 × 37.5
TBGA
480
1.27
1.55
TBGA (Pb free)
PBGA
27 × 27
516
1
2.25
PBGA (Pb free)
5.2
Mechanical Dimensions
This section discusses the TBGA and PBGA package dimensions.
MPC8250 Hardware Specifications, Rev. 2
56
Freescale Semiconductor
Package Description
5.2.1
TBGA Package Dimensions
Figure 17 provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA
package.
Notes:
1. Dimensions and Tolerancing per
ASME Y14.5M-1994.
2. Dimensions in millimeters.
3. Dimension b is measured at the
Millimeters
Dim
Min
Max
A
1.45
0.60
0.85
0.25
0.65
1.65
A1
A2
A3
b
0.70
0.95
—
0.85
D
37.50 BSC
35.56 REF
1.27 BSC
37.50 BSC
D1
e
E
Figure 17. Mechanical Dimensions and Bottom Surface Nomenclature—480 TBGA
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
57
Package Description
5.2.2
PBGA Package Dimensions
Figure 18 provides the mechanical dimensions and bottom surface nomenclature of the 516 PBGA
package.
Figure 18. Mechanical Dimensions and Bottom Surface Nomenclature—516 PBGA
MPC8250 Hardware Specifications, Rev. 2
58
Freescale Semiconductor
Ordering Information
6 Ordering Information
Figure 19 provides an example of the Freescale part numbering nomenclature for the MPC8250. In
addition to the processor frequency, the part numbering scheme also consists of a part modifier that
indicates any enhancement(s) in the part from the original production design. Each part number also
contains a revision code that refers to the die mask revision number and is specified in the part numbering
scheme for identification purposes only. For more information, contact your local Freescale sales office.
MPC 8250 A C ZU XXX X
Product Code
Die Revision Level
Device Number
Processor Frequency
(CPU/CPM/Bus)
Process Technology
(A = 0.25 micron)
Package
ZU = 480 TBGA
VV = 480 TBGA (Pb free)
ZO = 516 PBGA
VR = 516 PBGA (Pb free)
Temperature Range
(Blank = 0 to 105 °C
C = –40 to 105 °C)
Figure 19. Freescale Part Number Key
7 Document Revision History
Table 24 provides a revision history for this template.
Table 24. Document Revision History
Substantive Changes
Revision
Date
2
1
7/2009 Updated TBGA and PBGA packaging information.
3/2005 Document template update
0.9
8/2003 • Table 2: Modification to supply voltage ranges reflected in notes 2, 3, and 4
• Addition of VCCSYN to “Note: Core, PLL, and I/O Supply Voltages” following Table 2
• Addition of Figure 2
• Addition of note 1 to Table 3
• Table 4: Changes to θ . Addition of θ and θ
JA
JB
JC
• Table 7, Figure 8: Addition of sp42a/sp43a
• Figure 3 through Figure 8: Addition of notes or modifications
• Table 9: Change to sp10
• Table 14, Table 16, and Table 18: Removal of PLL bypass mode from clock tables
• Table 20 and Table 22: Addition of note 1
• Addition of SPICLK to PC19 in Table 20 and Table 22. It is documented correctly in the
MPC8260 PowerQUICC II™ Family Reference Manual but had previously been omitted from
Table 20 and Table 22.
0.8
0.7
11/2002 Table 22, “VR Pinout”: Addition of C18 to the Ground (GND) pin list (page 53)
10/2002 Table 22, “VR Pinout”: Addition of L3 to the Core (VDDx) pin list (page 53)
MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
59
Document Revision History
Table 24. Document Revision History (continued)
Substantive Changes
Revision
Date
0.6
0.5
0.4
10/2002 Table 22, “VR Pinout”: corrected ball assignment for the following pins—A12–A17, TA, PD5, PC2.
9/2002 Addition of VR (516 PBGA) package information. Refer to sections 2.2, 4.2, and 5.
5/2002 • Table 2: Notes 2 and 3
• Addition of note on page 8:VDDH and VDD tracking
• Table 14: Note 3
• Table 16: Note 1
• Table 18: Note 3
0.3
0.2
3/2002 • Table 20: modified note to pin AF25.
3/2202 • Table 20: modified notes to pins AE11 and AF25.
• Table 20: added note to pins AA1 and AG4 (Therm0 and Therm1).
0.1
2/2002 • Note 2 for Table 4 (changes in italics): “...greater than or equal to 266 MHz, 200 MHz CPM...”
• Table 18: core and bus frequency values for the following ranges of MODCK_HMODCK:
0011_000 to 0011_100 and 1011_000 to 1011_1000
• Table 20: footnotes added to pins at AE11, AF25, U5, and V4.
0
11/2001 Initial version
MPC8250 Hardware Specifications, Rev. 2
60
Freescale Semiconductor
Document Revision History
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MPC8250 Hardware Specifications, Rev. 2
Freescale Semiconductor
61
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© Freescale Semiconductor, Inc., 2003, 2005, 2009.
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Document Number: MPC8250EC
Rev. 2
07/2009
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