MPC8266AVRIFBX_技术文档

Document Number: MPC8260AEC

Rev. 1.1, 03/2006

Freescale Semiconductor

Technical Data

MPC8260A

PowerQUICC™ II Integrated

Communications Processor

Hardware Specifications

Contents

This document contains detailed information on power

1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Electrical and Thermal Characteristics . . . . . . . . . . . . 7

3. Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 23

4. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 46

6. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 48

7. Document Revision History . . . . . . . . . . . . . . . . . . . 48

considerations, DC/AC electrical characteristics, and AC

timing specifications for .25µm (HiP4) devices in the

PowerQUICC II™ MPC8260 communications processor

family. These devices include the MPC8260, the MPC8255,

the MPC8264, the MPC8265, and the MPC8266.

Throughout this document, these devices are collectively

referred to as the MPC826xA.

Features

Figure 1 shows the block diagram for the MPC8266, the HiP4 superset device. Shaded portions indicate

functionality that is not available on all devices; refer to the notes.

16 Kbytes

I-Cache

I-MMU

System Interface Unit

(SIU)

60x Bus

G2 Core

16 Kbytes

D-Cache

Bus Interface Unit

2,3

PCI Bus

32 bits, up to 66 MHz

60x-to-PCI

Bridge^2,3

D-MMU

or

60x-to-Local

Bridge

Local Bus

32 bits, up to 83 MHz

Communication Processor Module (CPM)

Memory Controller

Timers

Serial

DMAs

32 Kbytes

Dual-Port RAM

Interrupt

Controller

Clock Counter

Parallel I/O

32-bit RISC Microcontroller

and Program ROM

4 Virtual

IDMAs

System Functions

Baud Rate

Generators

IMA^1,3

Microcode

4

I²C

MCC1

MCC2 FCC1 FCC2 FCC3

SCC1 SCC2 SCC3 SCC4 SMC1 SMC2

SPI

1,3

TC Layer Hardware

Time Slot Assigner

Serial Interface

Non-Multiplexed

I/O

8 TDM Ports⁵

3 MII

2 UTOPIA

Ports

Ports⁶

Notes:

1

2

3

4

5

6

MPC8264

MPC8265

MPC8266

Not on MPC8255

4 TDM ports on the MPC8255

2 MII ports on the MPC8255

Figure 1. MPC8266 Block Diagram

1 Features

The major features of the MPC826xA family are as follows:

•

Dual-issue integer core

— A core version of the EC603e microprocessor

— System core microprocessor supporting frequencies of 150–300 MHz

— Separate 16-Kbyte data and instruction caches:

– Four-way set associative

– Physically addressed

– LRU replacement algorithm

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

2

Features

— PowerPC architecture-compliant memory management unit (MMU)

— Common on-chip processor (COP) test interface

— High-performance (6.6–7.65 SPEC95 benchmark at 300 MHz; 1.68 MIPs/MHz without

inlining and 1.90 Dhrystones MIPS/MHz with

— Supports bus snooping for data cache coherency

— Floating-point unit (FPU)

•

Separate power supply for internal logic and for I/O

Separate PLLs for G2 core and for the CPM

— G2 core and CPM can run at different frequencies for power/performance optimization

— Internal core/bus clock multiplier that provides 1.5:1, 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios

— Internal CPM/bus clock multiplier that provides 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1 ratios

64-bit data and 32-bit address 60x bus

•

— Bus supports multiple master designs

— Supports single- and four-beat burst transfers

— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

— Supports data parity or ECC and address parity

32-bit data and 18-bit address local bus

•

— Single-master bus, supports external slaves

— Eight-beat burst transfers

— 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

60x-to-PCI bridge (MPC8265 and MPC8266 only)

— Programmable host bridge and agent

— 32-bit data bus, 66 MHz, 3.3 V

— Synchronous and asynchronous 60x and PCI clock modes

— All internal address space available to external PCI host

— DMA for memory block transfers

— PCI-to-60x address remapping

•

System interface unit (SIU)

— Clock synthesizer

— Reset controller

— Real-time clock (RTC) register

— Periodic interrupt timer

— Hardware bus monitor and software watchdog timer

— IEEE 1149.1 JTAG test access port

Twelve-bank memory controller

— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash and other user-

definable peripherals

— Byte write enables and selectable parity generation

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

3

Features

— 32-bit address decodes with programmable bank size

— Three user programmable machines, general-purpose chip-select machine, and page-mode

pipeline SDRAM machine

— Byte selects for 64 bus width (60x) and byte selects for 32 bus width (local)

— Dedicated interface logic for SDRAM

•

CPU core can be disabled and the device can be used in slave mode to an external core

Communications processor module (CPM)

— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support

for communications protocols

— Interfaces to G2 core through on-chip 32-Kbyte dual-port RAM and DMA controller

— Serial DMA channels for receive and transmit on all serial channels

— Parallel I/O registers with open-drain and interrupt capability

— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers

— Three fast communications controllers supporting the following protocols (only FCC1 and

FCC2 on the MPC8255):

– 10/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent

interface (MII)

– ATM—Full-duplex SAR protocols at 155 Mbps, through UTOPIA interface, AAL5, AAL1,

AAL0 protocols, TM 4.0 CBR, VBR, UBR, ABR traffic types, up to 16 K external

connections

– Transparent

– HDLC—Up to T3 rates (clear channel)

— Two multichannel controllers (MCCs) (only MCC2 on the MPC8255)

– Each MCC handles 128 serial, full-duplex, 64-Kbps data channels.Each MCC can be split

into four subgroups of 32 channels each.

– Almost any combination of subgroups can be multiplexed to single or multiple TDM

interfaces up to four TDM interfaces per MCC

— Four serial communications controllers (SCCs) identical to those on the MPC860, supporting

the digital portions of the following protocols:

– Ethernet/IEEE 802.3 CDMA/CS

– HDLC/SDLC and HDLC bus

– Universal asynchronous receiver transmitter (UART)

– Synchronous UART

– Binary synchronous (BISYNC) communications

– Transparent

— Two serial management controllers (SMCs), identical to those of the MPC860

– Provide management for BRI devices as general circuit interface (GCI) controllers in time-

division-multiplexed (TDM) channels

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

4

Freescale Semiconductor

Features

– Transparent

– UART (low-speed operation)

— One serial peripheral interface identical to the MPC860 SPI

2

— One inter-integrated circuit (I C) controller (identical to the MPC860 I C controller)

– Microwire compatible

– Multiple-master, single-master, and slave modes

— Up to eight TDM interfaces (four on the MPC8255)

– Supports two groups of four TDM channels for a total of eight TDMs

– 2,048 bytes of SI RAM

– Bit or byte resolution

– Independent transmit and receive routing, frame synchronization

– Supports T1, CEPT, T1/E1, T3/E3, pulse code modulation highway, ISDN basic rate, ISDN

primary rate, Freescale interchip digital link (IDL), general circuit interface (GCI), and

user-defined TDM serial interfaces

— Eight independent baud rate generators and 20 input clock pins for supplying clocks to FCCs,

SCCs, SMCs, and serial channels

— Four independent 16-bit timers that can be interconnected as two 32-bit timers

Additional features of the MPC826xA family are as follows:

•

CPM

— 32-Kbyte dual-port RAM

— Additional MCC host commands

— Eight transfer transmission convergence (TC) layers between the TDMs and FCC2 to support

inverse multiplexing for ATM capabilities (IMA) (MPC8264 and MPC8266 only)

•

CPM multiplexing

— FCC2 can also be connected to the TC layer.

TC layer (MPC8264 and MPC8266 only)

— Each of the 8 TDM channels is routed in hardware to a TC layer block

– Protocol-specific overhead bits may be discarded or routed to other controllers by the SI

– Performing ATM TC layer functions (according to ITU-T I.432)

– Transmit (Tx) updates

- Cell HEC generation

- Payload scrambling using self synchronizing scrambler (programmable by the user)

- Coset generation (programmable by the user)

- Cell rate by inserting idle/unassigned cells

– Receive (Rx) updates

- Cell delineation using bit by bit HEC checking and programmable ALPHA and DELTA

parameters for the delineation state machine

- Payload descrambling using self synchronizing scrambler (programmable by the user)

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

5

Features

- Coset removing (programmable by the user)

- Filtering idle/unassigned cells (programmable by the user)

- Performing HEC error detection and single bit error correction (programmable by user)

- Generating loss of cell delineation status/interrupt (LOC/LCD)

— Operates with FCC2 (UTOPIA 8)

— Provides serial loop back mode

— Cell echo mode is provided

— Supports both FCC transmit modes

– External rate mode—Idle cells are generated by the FCC (microcode) to control data rate.

– Internal rate mode (sub-rate)—FCC transfers only the data cells using the required data rate.

The TC layer generates idle/unassigned cells to maintain the line bit rate.

— Supports TC-layer and PMD-WIRE interface (according to the ATM-Forum af-phy-0063.000)

— Cell counters for performance monitoring

– 16-bit counters count

- HEC error cells

- HEC single bit error and corrected cells

- Idle/unassigned cells filtered

- Idle/unassigned cells transmitted

- Transmitted ATM cells

- Received ATM cells

– Maskable interrupt is sent to the host when a counter expires

— Overrun (Rx cell FIFO) and underrun (Tx cell FIFO) condition produces maskable interrupt

— May be operated at E1 and DS-1 rates. In addition, xDSL applications at bit rates up to 10 Mbps

are supported

•

PCI bridge (MPC8265 and MPC8266 only)

— PCI Specification Revision 2.2 compliant and supports frequencies up to 66 MHz

— On-chip arbitration

— Support for PCI to 60x memory and 60x memory to PCI streaming

— PCI Host Bridge or Peripheral capabilities

— Includes 4 DMA channels for the following transfers:

– PCI-to-60x to 60x-to-PCI

– 60x-to-PCI to PCI-to-60x

– PCI-to-60x to PCI-to-60x

– 60x-to-PCI to 60x-to-PCI

— Includes all of the configuration registers (which are automatically loaded from the EPROM

and used to configure the MPC8265) required by the PCI standard as well as message and

doorbell registers

— Supports the I O standard

2

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

6

Freescale Semiconductor

Electrical and Thermal Characteristics

— Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0

August 3, 1998)

— Support for 66 MHz, 3.3 V specification

— 60x-PCI bus core logic which uses a buffer pool to allocate buffers for each port

— Makes use of the local bus signals, so there is no need for additional pins

2 Electrical and Thermal Characteristics

This section provides AC and DC electrical specifications and thermal characteristics for the MPC826xA.

2.1

DC Electrical Characteristics

This section describes the DC electrical characteristics for the MPC826xA. Table 1 shows the maximum

electrical ratings.

(1)

Table 1. Absolute Maximum Ratings

Rating

Symbol

Value

Unit

(2)

Core supply voltage

VDD

VCCSYN

VDDH

VIN

-0.3 – 2.5

V

2.

PLL supply voltage

(3)

I/O supply voltage

-0.3 – 4.0

V

(4)

Input voltage

GND(-0.3) – 3.6

120

V

Junction temperature

Storage temperature range

Notes:

T

°C

j

T

(-55) – (+150)

STG

1. Absolute maximum ratings are stress ratings only; functional operation (see Table 2) at the maximums is not

guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.

2. Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset.

3. Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH

should not exceed VDD/VCCSYN by more than 2.5 V during normal operation.

4. Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

7

Electrical and Thermal Characteristics

Table 2 lists recommended operational voltage conditions.

(1)

Table 2. Recommended Operating Conditions

Rating

Symbol

Value

Unit

(2)

2

(3)

(4)

4

Core supply voltage

PLL supply voltage

I/O supply voltage

VDD

VCCSYN

VDDH

VIN

1.7 – 1.9

1.7–2.1

1.9 –2.2

V

3

1.7 – 1.9

1.7–2.1

1.9–2.2

3.135 – 3.465

V

Input voltage

GND (-0.3) – 3.465

V

(5)

Junction temperature (maximum)

T

105

°C

j

5

Ambient temperature

T

0–70

A

Notes:

1. Caution: These are the recommended and tested operating conditions. Proper device operating outside of these

conditions is not guaranteed.

2. CPU frequency less than or equal to 200 MHz.

3. CPU frequency greater than 200 MHz but less than 233 MHz.

4. CPU frequency greater than or equal to 233 MHz.

5. Note that for extended temperature parts the range is (-40) – 105 .

T

j

A

NOTE: Core, PLL, and I/O Supply Voltages

VDDH, VCCSYN, and VDD must track each other and both must vary in

the same direction—in the positive direction (+5% and +0.1 Vdc) or in the

negative direction (-5% and -0.1 Vdc).

This device contains circuitry protecting against damage due to high static voltage or electrical fields;

however, it is advised that normal precautions be taken to avoid application of any voltages higher than

maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused

inputs are tied to an appropriate logic voltage level (either GND or V ).

CC

Figure 2 shows the undershoot and overshoot voltage of the 60x and local bus memory interface of the

MPC8280. Note that in PCI mode the I/O interface is different.

4 V

GV + 5%

DD

V

GV

IH

DD

GND

GND – 0.3 V

IL

GND – 1.0 V

Not to exceed 10%

of t

SDRAM_CLK

Figure 2. Overshoot/Undershoot Voltage

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

8

Electrical and Thermal Characteristics

Table 3 shows DC electrical characteristics.

(1)

Table 3. DC Electrical Characteristics

Characteristic

Symbol

Min

Max

Unit

Input high voltage, all inputs except CLKIN

Input low voltage

V

2.0

GND

2.4

GND

—

3.465

0.8

3.465

0.4

10

V

IH

V

IL

CLKIN input high voltage

V

IHC

CLKIN input low voltage

V

I

V

ILC

IN

(2)

Input leakage current, V = VDDH

µA

V

IN

2

Hi-Z (off state) leakage current, V = VDDH

I

—

10

IN

OZ

Signal low input current, V = 0.8 V

I

—

1

IL

L

Signal high input current, V = 2.0 V

I

—

1

IH

H

Output high voltage, I = –2 mA

V

2.4

—

OH

except XFC, UTOPIA mode, and open drain pins

In UTOPIA mode: I = -8.0mA

OH

PA[0-31]

PB[4-31]

PC[0-31]

PD[4-31]

In UTOPIA mode: I = 8.0mA

V

—

0.5

V

OL

PA[0-31]

PB[4-31]

PC[0-31]

PD[4-31]

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

9

Electrical and Thermal Characteristics

(1)

Table 3. DC Electrical Characteristics (continued)

Characteristic

Symbol

Min

Max

Unit

I

= 7.0mA

V

—

0.4

V

OL

BR

BG

ABB/IRQ2

TS

A[0-31]

TT[0-4]

TBST

TSIZE[0–3]

AACK

ARTRY

DBG

DBB/IRQ3

D[0-63]

DP(0)/RSRV/EXT_BR2

DP(1)/IRQ1/EXT_BG2

DP(2)/TLBISYNC/IRQ2/EXT_DBG2

DP(3)/IRQ3/EXT_BR3/CKSTP_OUT

DP(4)/IRQ4/EXT_BG3/CORE_SREST

DP(5)/TBEN/IRQ5/EXT_DBG3

DP(6)/CSE(0)/IRQ6

DP(7)/CSE(1)/IRQ7

PSDVAL

TA

TEA

GBL/IRQ1

CI/BADDR29/IRQ2

WT/BADDR30/IRQ3

L2_HIT/IRQ4

CPU_BG/BADDR31/IRQ5

CPU_DBG

CPU_BR

IRQ0/NMI_OUT

IRQ7/INT_OUT/APE

PORESET

HRESET

SRESET

RSTCONF

QREQ

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

10

Electrical and Thermal Characteristics

(1)

Table 3. DC Electrical Characteristics (continued)

Characteristic

Symbol

Min

Max

Unit

I

= 5.3mA

V

—

0.4

V

OL

CS[0-9]

CS(10)/BCTL1

CS(11)/AP(0)

BADDR[27–28]

ALE

BCTL0

PWE(0:7)/PSDDQM(0:7)/PBS(0:7)

PSDA10/PGPL0

PSDWE/PGPL1

POE/PSDRAS/PGPL2

PSDCAS/PGPL3

PGTA/PUPMWAIT/PGPL4/PPBS

PSDAMUX/PGPL5

(3)

LWE[0–3]LSDDQM[0–3]/LBS[0–3]/PCI_CFG[0–3

3

LSDA10/LGPL0/PCI_MODCKH0

LSDWE/LGPL1/PCI_MODCKH1

3

LOE/LSDRAS/LGPL2/PCI_MODCKH2

LSDCAS/LGPL3/PCI_MODCKH3

3

LGTA/LUPMWAIT/LGPL4/LPBS

LSDAMUX/LGPL5/PCI_MODCK

3

LWR

MODCK1/AP(1)/TC(0)/BNKSEL(0)

MODCK2/AP(2)/TC(1)/BNKSEL(1)

MODCK3/AP(3)/TC(2)/BNKSEL(2)

I

= 3.2mA

OL

L_A14/PAR

3

L_A15/FRAME /SMI

3

L_A16/TRDY

3

L_A17/IRDY /CKSTP_OUT

3

L_A18/STOP

3

L_A19/DEVSEL

3

L_A20/IDSEL

L_A21/PERR

L_A22/SERR

L_A23/REQ0

3

L_A24/REQ1 /HSEJSW

3

L_A25/GNT0

3

L_A26/GNT1 /HSLED

3

L_A27/GNT2 /HSENUM

3

L_A28/RST /CORE_SRESET

3

L_A29/INTA

3

L_A30/REQ2

L_A31

LCL_D(0-31)/AD(0-31)

3

LCL_DP(0-3)/C/BE(0-3)

PA[0–31]

PB[4–31]

PC[0–31]

PD[4–31]

TDO

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

11

Electrical and Thermal Characteristics

Notes:

1. The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent

excessive DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as

outputs.

2. The leakage current is measured for nominal VDD, VCCSYN, and VDD.

3. MPC8265 and MPC8266 only.

2.2

Thermal Characteristics

Table 4 describes thermal characteristics.

Table 4. Thermal Characteristics for 480 TBGA Package

Characteristics

Junction to ambient

Symbol

Value

Unit

Air Flow

(1)

(2)

13

NC

1

10

1 m/s

NC

θ

°C/W

JA

(3)

11

3

8

1 m/s

—

(4)

Junction to board

θ

4

°C/W

JB

(5)

Junction to case

θ

1.1

—

JC

Notes:

1. Assumes a single layer board with no thermal vias

2. Natural convection

3. Assumes a four layer board

4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature

is measured on the top surface of the board near the package.

5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL

SPEC-883 Method 1012.1).

2.3

Power Considerations

The average chip-junction temperature, T , in °C can be obtained from the following:

J

T = T + (P x θ_JA)

(1)

J

A

D

where

T = ambient temperature °C

A

θ_JA= package thermal resistance, junction to ambient, °C/W

P = P

+ P

I/O

D

INT

P

= I x V Watts (chip internal power)

DD DD

INT

P

= power dissipation on input and output pins (determined by user)

I/O

For most applications P < 0.3 x P . If P is neglected, an approximate relationship between P and

I/O

INT

I/O

D

T is the following:

J

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

12

Electrical and Thermal Characteristics

P = K/(T + 273° C)

(2)

D

J

Solving equations (1) and (2) for K gives:

2

K = P x (T + 273° C) + θ_JAx P

(3)

D

A

D

where K is a constant pertaining to the particular part. K can be determined from equation (3) by measuring

P (at equilibrium) for a known T . Using this value of K, the values of P and T can be obtained by

D

A

D

J

solving equations (1) and (2) iteratively for any value of T .

A

2.3.1

Layout Practices

Each V pin should be provided with a low-impedance path to the board’s power supply. Each ground

CC

pin should likewise be provided with a low-impedance path to ground. The power supply pins drive

distinct groups of logic on chip. The V power supply should be bypassed to ground using at least four

CC

0.1 µF by-pass capacitors located as close as possible to the four sides of the package. The capacitor leads

and associated printed circuit traces connecting to chip V and ground should be kept to less than half an

CC

inch per capacitor lead. A four-layer board is recommended, employing two inner layers as V_CCand GND

planes.

All output pins on the MPC826xA have fast rise and fall times. Printed circuit (PC) trace interconnection

length should be minimized in order to minimize overdamped conditions and reflections caused by these

fast output switching times. This recommendation particularly applies to the address and data buses.

Maximum PC trace lengths of six inches are recommended. Capacitance calculations should consider all

device loads as well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and

bypassing becomes especially critical in systems with higher capacitive loads because these loads create

higher transient currents in the V and GND circuits. Pull up all unused inputs or signals that will be

CC

inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins.

Table 5 provides preliminary, estimated power dissipation for various configurations. Note that suitable

thermal management is required for conditions above P = 3W (when the ambient temperature is 70° C or

D

greater) to ensure the junction temperature does not exceed the maximum specified value. Also note that

the I/O power should be included when determining whether to use a heat sink.

(1)

Table 5. Estimated Power Dissipation for Various Configurations

(2)

P

(W)

INT

Bus

(MHz)

CPM

Core CPU

CPM

(MHz)

CPU

(MHz)

Vddl 1.8 Volts

Nominal Maximum Nominal Maximum

Vddl 2.0 Volts

Multiplier Multiplier

66.66

83.33

2

2.5

3

133

166

200

166

208

200

266

300

250

291

1.2

1.3

—

2

2.1

—

1.8

1.9

2.3

2.4

2.2

2.4

2.3

2.9

3.1

2.8

3.1

4

3

4.5

3

—

2

—

2

3

—

2.5

3.5

—

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

13

Electrical and Thermal Characteristics

Notes:

1. Test temperature = room temperature (25° C)

2. P = I x V Watts

INT

DD

2.4

AC Electrical Characteristics

The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and

inputs for the 66 MHz MPC826xA device. Note that AC timings are based on a 50-pf load. Typical output

buffer impedances are shown in Table 6.

(1)

Table 6. Output Buffer Impedances

Output Buffers

60x bus

Typical Impedance (Ω)

40

46

25

Local bus

Memory controller

Parallel I/O

PCI

Notes:

1. These are typical values at 65° C. The impedance may vary by

25% with process and temperature.

Table 7 lists CPM output characteristics.

(1)

Table 7. AC Characteristics for CPM Outputs

Spec Number

Max Delay (ns) Min Delay (ns)

Characteristic

Max

Min

66 MHz 83 MHz 66 MHz 83 MHz

sp36a

sp36b

sp40

sp37a

sp37b

sp41

FCC outputs—internal clock (NMSI)

FCC outputs—external clock (NMSI)

TDM outputs/SI

6

5.5

12

16

11

1

2

1

14

25

19

14

5

4

sp38a

sp38b

sp42

sp39a

sp39b

sp43

SCC/SMC/SPI/I2C outputs—internal clock (NMSI)

Ex_SCC/SMC/SPI/I2C outputs—external clock (NMSI)

TIMER/IDMA outputs

1

0.5

1

2

1

0.5

sp42a

sp43a

PIO outputs

0.5

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

14

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 8 lists CPM input characteristics.

(1)

Table 8. AC Characteristics for CPM Inputs

Spec Number

Setup (ns)

Hold (ns)

Characteristic

Max

Min

66 MHz 83 MHz 66 MHz 83 MHz

sp16a

sp16b

sp20

sp17a

sp17b

sp21

FCC inputs—internal clock (NMSI)

FCC inputs—external clock (NMSI)

TDM inputs/SI

10

3

8

2.5

12

16

4

0

3

0

2

15

20

5

12

0

10

0

sp18a

sp18b

sp22

sp19a

sp19b

sp23

SCC/SMC/SPI/I2C inputs—internal clock (NMSI)

SCC/SMC/SPI/I2C inputs—external clock (NMSI)

PIO/TIMER/IDMA inputs

5

4

10

8

3

Notes:

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.

Timings are measured at the pin.

Note that although the specifications generally reference the rising edge of the clock, the following AC

timing diagrams also apply when the falling edge is the active edge.

Figure 3 shows the FCC external clock.

Serial ClKin

sp17b

sp16b

FCC input signals

sp36b/sp37b

FCC output signals

Note: When GFMR[TCI] = 0

sp36b/sp37b

FCC output signals

Note: When GFMR[TCI] = 1

Figure 3. FCC External Clock Diagram

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

15

Electrical and Thermal Characteristics

Figure 4 shows the FCC internal clock.

BRG_OUT

sp17a

sp16a

FCC input signals

sp36a/sp37a

FCC output signals

Note: When GFMR[TCI] = 0

sp36a/sp37a

FCC output signals

Note: When GFMR[TCI] = 1

Figure 4. FCC Internal Clock Diagram

2

Figure 5 shows the SCC/SMC/SPI/I C external clock.

Serial CLKin

sp19b

sp18b

SCC/SMC/SPI/I2C input signals

(See note.)

sp38b/sp39b

SCC/SMC/SPI/I2C output signals

(See note.)

Note: There are four possible timing conditions for SCC and SPI:

1. Input sampled on the rising edge and output driven on the rising edge (shown).

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge.

4. Input sampled on the falling edge and output driven on the rising edge.

2

Figure 5. SCC/SMC/SPI/I C External Clock Diagram

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

16

Freescale Semiconductor

Electrical and Thermal Characteristics

2

Figure 6 shows the SCC/SMC/SPI/I C internal clock.

BRG_OUT

sp19a

sp18a

SCC/SMC/SPI/I2C input signals

(See note.)

sp38a/sp39a

SCC/SMC/SPI/I2C output signals

(See note.)

Note: There are four possible timing conditions for SCC and SPI:

1. Input sampled on the rising edge and output driven on the rising edge (shown).

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge.

4. Input sampled on the falling edge and output driven on the rising edge.

2

Figure 6. SCC/SMC/SPI/I C Internal Clock Diagram

Figure 7 shows TDM input and output signals.

Serial CLKin

sp20

sp21

TDM input signals

sp40/sp41

TDM output signals

Note: There are four possible TDM timing conditions:

1. Input sampled on the rising edge and output driven on the rising edge (shown).

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge.

4. Input sampled on the falling edge and output driven on the rising edge.

Figure 7. TDM Signal Diagram

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

17

Electrical and Thermal Characteristics

Figure 8 shows PIO, timer, and DMA signals.

Sys clk

sp23

sp22

PIO/IDMA/TIMER[TGATE assertion] input signals

(See note)

sp23

sp22

TIMER input signal [TGATE deassertion]

(See note)

sp42/sp43

IDMA output signals

sp42/sp43

sp42a/sp43a

TIMER(sp42/43)/ PIO(sp42a/sp43a)

output signals

Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.

Figure 8. PIO, Timer, and DMA Signal Diagram

Table 10 lists SIU input characteristics.

(1)

Table 9. AC Characteristics for SIU Inputs

Spec Number

Setup (ns)

Hold (ns)

Characteristic

Max

Min

66 MHz 83 MHz 66 MHz 83 MHz

sp11

sp12

sp13

sp14

sp15

sp10

AACK/ARTRY/TA/TS/TEA/DBG/BG/BR

Data bus in normal mode

Data bus in ECC and PARITY modes

DP pins

6

5

8

7

5

4

6

4

0.5

All other pins

Notes:

1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN.

Timings are measured at the pin.

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

18

Freescale Semiconductor

Electrical and Thermal Characteristics

Table 10 lists SIU output characteristics.

(1)

Table 10. AC Characteristics for SIU Outputs

Max Delay (ns)

66 MHz 83 MHz 66 MHz 83 MHz

Spec Number

Min Delay (ns)

Characteristic

Max

Min

sp31

sp32

sp30

PSDVAL/TEA/TA

7

8

6

6.5

7

0.5

ADD/ADD_atr./BADDR/CI/GBL/WT

sp33a

sp33b

sp34

Data bus

6.5

8

DP

Memory controller signals/ALE

All other signals

6

5

sp35

6

5.5

Notes:

1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal.

Timings are measured at the pin.

NOTE

Activating data pipelining (setting BRx[DR] in the memory controller)

improves the AC timing. When data pipelining is activated, sp12 can be

used for data bus setup even when ECC or PARITY are used. Also, sp33a

can be used as the AC specification for DP signals.

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

19

Electrical and Thermal Characteristics

Figure 9 shows the interaction of several bus signals.

CLKin

sp10

sp11

AACK/ARTRY/TA/TS/TEA/

DBG/BG/BR input signals

sp12

DATA bus normal mode

input signal

sp15

All other input signals

sp30

sp31

sp32

PSDVAL/TEA/TA output signals

sp30

ADD/ADD_atr/BADDR/CI/

GBL/WT output signals

sp33a

sp35

DATA bus output signals

All other output signals

Figure 9. Bus Signals

Figure 10 shows signal behavior for all parity modes (including ECC, RMW parity, and standard parity).

CLKin

sp10

sp13

DATA bus, ECC, and PARITY mode input signals

sp10

sp14

DP mode input signal

sp33b/sp30

DP mode output signal

Figure 10. Parity Mode Diagram

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

20

Freescale Semiconductor

Electrical and Thermal Characteristics

Figure 11 shows signal behavior in MEMC mode.

CLKin

V_CLK

sp34/sp30

Memory controller signals

Figure 11. MEMC Mode Diagram

NOTE

Generally, all MPC826xA bus and system output signals are driven from the

rising edge of the input clock (CLKin). Memory controller signals,

however, trigger on four points within a CLKin cycle. Each cycle is divided

by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising

edge, and T3 at the falling edge, of CLKin. However, the spacing of T2 and

T4 depends on the PLL clock ratio selected, as shown in Table 11.

Table 11. Tick Spacing for Memory Controller Signals

Tick Spacing (T1 Occurs at the Rising Edge of CLKin)

PLL Clock Ratio

T2

T3

T4

1:2, 1:3, 1:4, 1:5, 1:6

1/4 CLKin

1/2 CLKin

3/4 CLKin

1:2.5

1:3.5

3/10 CLKin

4/14 CLKin

1/2 CLKin

8/10 CLKin

11/14 CLKin

Figure 12 is a graphical representation of Table 11.

CLKin

for 1:2, 1:3, 1:4, 1:5, 1:6

T1

T2

T3

T4

CLKin

for 1:2.5

T2

T4

for 1:3.5

T2

T4

Figure 12. Internal Tick Spacing for Memory Controller Signals

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

21

Electrical and Thermal Characteristics

Table 12 lists the JTAG timings.

1

Table 12. JTAG Timings

2

Parameter

Symbol

Min

Max

Unit

Notes

JTAG external clock frequency of operation

JTAG external clock cycle time

f

t

0

40

20

0

25

—

5

MHz

ns

JTG

JTAG external clock pulse width measured at 1.4V

JTAG external clock rise and fall times

t

ns

JTKHKL

6

t

and

ns

JTGR

t

JTGF

3

6

TRST assert time

Input setup times

t

25

—

ns

,

TRST

4

7

t

4

—

ns

,

Boundary-scan data

TMS, TDI

JTDVKH

t

JTIVKH

Input hold times

4

7

10

—

ns

,

Boundary-scan data

TMS, TDI

JTDXKH

t

JTIXKH

Output valid times

5

7

t

—

25

ns

,

.

Boundary-scan data

TDO

JTKLDV

JTKLOV

Output hold times

5

7

t

1

—

ns

,

Boundary-scan data

TDO

JTKLDX

JTKLOX

JTAG external clock to output high impedance

5

6

t

1

25

ns

,

Boundary-scan data

TDO

JTKLDZ

JTKLOZ

1

All outputs are measured from the midpoint voltage of the falling/rising edge of t

to the midpoint of the signal

TCLK

in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load.

Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.

2

The symbols used for timing specifications herein follow the pattern of t

(first two letters of functional block)(signal)(state)

for inputs and t(

for outputs. For example,

(reference)(state)

(first two letters of functional block)(reference)(state)(signal)(state)

t

symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state

JTDVKH

(V) relative to the t

clock reference (K) going to the high (H) state or setup time. Also, t

symbolizes JTAG

JTG

JTDXKH

timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the t

clock reference (K)

JTG

going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters

representing the clock of a particular functional. For rise and fall times, the latter convention is used with the

appropriate letter: R (rise) or F (fall).

3

4

5

6

7

TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

Non-JTAG signal input timing with respect to t

.

TCLK

Non-JTAG signal output timing with respect to t

Guaranteed by design.

.

TCLK

Guaranteed by design and device characterization.

NOTE

The UPM machine outputs change on the internal tick determined by the

memory controller programming; the AC specifications are relative to the

internal tick. Note that SDRAM and GPCM machine outputs change on

CLKin’s rising edge.

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

22

Freescale Semiconductor

Clock Configuration Modes

3 Clock Configuration Modes

To configure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the

MODCK[1–3] pins are sampled while HRESET is asserted. Table 13 lists the eight basic configuration

modes. Table 14 lists the other modes that are available by using the configuration pin (RSTCONF) and

driving four bits from hardware configuration word on the data bus.

Note that the MPC8265 and the MPC8266 have two additional clocking modes—PCI agent and PCI host.

Refer to Section 3.2, “PCI Mode” on page 26 for information.

NOTE

Clock configurations change only after POR is asserted.

3.1

Local Bus Mode

Table 13 describes default clock modes for the MPC826xA.

Table 13. Clock Default Modes

Input Clock CPM Multiplication

CPM

Frequency

Core Multiplication

Core

Frequency

MODCK[1–3]

Frequency

Factor

000

001

010

011

100

101

110

111

33 MHz

66 MHz

3

100 MHz

133 MHz

166 MHz

4

5

133 MHz

166 MHz

133 MHz

166 MHz

200 MHz

166 MHz

200 MHz

4

5

2

2.5

3

2

2.5

3

Table 14 describes all possible clock configurations when using the hard reset configuration sequence.

Note that basic modes are shown in boldface type. The frequencies listed are for the purpose of illustration

only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed

the frequency rating of the user’s device.

(1)

Table 14. Clock Configuration Modes

Input Clock

CPM Multiplication

CPM

Frequency

Core Multiplication

Core

Frequency

(2)

MODCK_H–MODCK[1–3] Frequency

2

Factor

,(3)

0001_000

0001_001

0001_010

0001_011

0001_100

33 MHz

2

66 MHz

4

5

6

7

8

133 MHz

166 MHz

200 MHz

233 MHz

266 MHz

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

23

Clock Configuration Modes

(1)

Table 14. Clock Configuration Modes (continued)

Input Clock

CPM Multiplication

CPM

Frequency

Core Multiplication

Core

Frequency

(2)

MODCK_H–MODCK[1–3] Frequency

2

Factor

,(3)

0001_101

0001_110

0001_111

0010_000

0010_001

33 MHz

3

100 MHz

4

5

6

7

8

133 MHz

166 MHz

200 MHz

233 MHz

266 MHz

0010_010

0010_011

0010_100

0010_101

0010_110

33 MHz

4

133 MHz

4

5

6

7

8

133 MHz

166 MHz

200 MHz

233 MHz

266 MHz

0010_111

0011_000

0011_001

0011_010

0011_011

33 MHz

5

166 MHz

4

5

6

7

8

133 MHz

166 MHz

200 MHz

233 MHz

266 MHz

0011_100

0011_101

0011_110

0011_111

0100_000

33 MHz

6

200 MHz

4

5

6

7

8

133 MHz

166 MHz

200 MHz

233 MHz

266 MHz

0100_001

0100_010

0100_011

0100_100

0100_101

0100_110

Reserved

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

24

Clock Configuration Modes

(1)

Table 14. Clock Configuration Modes (continued)

Input Clock

CPM Multiplication

CPM

Frequency

Core Multiplication

Core

Frequency

(2)

MODCK_H–MODCK[1–3] Frequency

2

Factor

,(3)

0100_111

0101_000

0101_001

0101_010

0101_011

0101_100

Reserved

0101_101

0101_110

0101_111

0110_000

0110_001

0110_010

66 MHz

2

133 MHz

2

2.5

3

133 MHz

166 MHz

200 MHz

233 MHz

266 MHz

300 MHz

3.5

4

4.5

0110_011

0110_100

0110_101

0110_110

0110_111

0111_000

66 MHz

2.5

166 MHz

2

2.5

3

133 MHz

166 MHz

200 MHz

233 MHz

266 MHz

300 MHz

3.5

4

4.5

0111_001

0111_010

0111_011

0111_100

0111_101

0111_110

66 MHz

3

200 MHz

2

2.5

3

133 MHz

166 MHz

200 MHz

233 MHz

266 MHz

300 MHz

3.5

4

4.5

0111_111

1000_000

66 MHz

3.5

233 MHz

2

133 MHz

166 MHz

2.5

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

25

Clock Configuration Modes

(1)

Table 14. Clock Configuration Modes (continued)

Input Clock

CPM Multiplication

CPM

Frequency

Core Multiplication

Core

Frequency

(2)

MODCK_H–MODCK[1–3] Frequency

2

Factor

,(3)

1000_001

1000_010

1000_011

1000_100

66 MHz

3.5

233 MHz

3

3.5

4

200 MHz

233 MHz

266 MHz

300 MHz

4.5

Notes:

1. Because of speed dependencies, not all of the possible configurations in Table 14 are applicable.

2. The user should choose the input clock frequency and the multiplication factors such that the frequency of the CPU

is equal to or greater than150 MHz and the CPM ranges between 66–233 MHz.

3. Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that

the resulting configuration does not exceed the frequency rating of the user’s part.

3.2

PCI Mode

The MPC8265 and the MPC8266 have three clocking modes: local, PCI host, and PCI agent. The clocking

mode is set according to three input pins—PCI_MODE, PCI_CFG[0], PCI_MODCK—as shown in

Table 15.

Table 15. MPC8265 and MPC8266 Clocking Modes

Pins

PCI Clock

Frequency Range

(MHZ)

Clocking Mode

PCI_MODE PCI_CFG[0] PCI_MODCK

1

0

—

0

—

0

Local bus

PCI host

—

50–66

25–50

50–66

25–50

0

1

0

PCI agent

1

In addition, note the following:

NOTE: PCI_MODCK

In PCI mode only, PCI_MODCK comes from the LGPL5 pin and

MODCK_H[0–3] comes from {LGPL0, LGPL1, LGPL2, LGPL3}.

NOTE: Tval (Output Hold)

The minimum Tval = 2 when PCI_MODCK = 1, and the minimum Tval = 1

when PCI_MODCK = 0. Therefore, designers should use clock

configurations that fit this condition to achieve PCI-compliant AC timing.

NOTE

Clock configurations change only after POR is asserted.

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

26

Freescale Semiconductor

Clock Configuration Modes

3.2.1

PCI Host Mode

The frequencies listed in Table 16 and Table 17 are for the purpose of illustration only. Users must select

a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating

of the user’s device.

I

Table 16. Clock Default Configurations in PCI Host Mode (MODCK_HI = 0000)

Input Clock

Frequency Multiplication

CPM

Core

Multiplication

Factor

MODCK[1–3]

CPM

Frequency

Core

Frequency

PCI Division

Factor

PCI

Frequency

(1)

(2)

2

(Bus)

Factor

000

001

66 MHz

2

133 MHz

166 MHz

200 MHz

2.5

3

166 MHz

200 MHz

233 MHz

266 MHz

200 MHz

233 MHz

266 MHz

2/4

3/6

66/33 MHz

55/28 MHz

66/33 MHz

010

2.5

3

011

3.5

4

100

101

3

110

3

3.5

4

111

3

Notes:

1. Assumes MODCK_HI = 0000.

2. The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is

divided by 2 (33 instead of 66 MHz, etc.) Refer to Table 15.

Table 17 describes all possible clock configurations when using the MPC8265 or the MPC8266’s internal

PCI bridge in host mode.

Table 17. Clock Configuration Modes in PCI Host Mode

Input Clock

Frequency

(Bus)

CPM

Multiplication

Factor

Core

Multiplication

Factor

MODCK_H –

MODCK[1–3]

CPM

Frequency

Core

Frequency

PCI Division

Factor

PCI

Frequency

(1)

(2)

2

0001_000

0001_001

0001_010

0001_011

33 MHz

3

100 MHz

5

6

7

8

166 MHz

200 MHz

233 MHz

266 MHz

3/6

33/16 MHz

0010_000

0010_001

0010_010

0010_011

33 MHz

4

133 MHz

5

6

7

8

166 MHz

200 MHz

233 MHz

266 MHz

4/8

33/16 MHz

(3)

0011_000

33 MHz

5

166 MHz

5

6

166 MHz

200 MHz

5

33 MHz

3

0011_001

33 MHz

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

27

Clock Configuration Modes

Table 17. Clock Configuration Modes in PCI Host Mode (continued)

Input Clock

Frequency

(Bus)

CPM

Multiplication

Factor

Core

Multiplication

Factor

MODCK_H –

MODCK[1–3]

CPM

Frequency

Core

Frequency

PCI Division

Factor

PCI

Frequency

(1)

(2)

2

3

0011_010

33 MHz

5

166 MHz

7

8

233 MHz

266 MHz

5

33 MHz

3

0011_011

3

0100_000

33 MHz

6

200 MHz

5

6

7

8

166 MHz

200 MHz

233 MHz

266 MHz

6

33 MHz

3

0100_001

3

0100_010

3

0100_011

0101_000

0101_001

0101_010

0101_011

0101_100

66 MHz

2

133 MHz

2.5

3

166 MHz

200 MHz

233 MHz

266 MHz

300 MHz

2/4

66/33 MHz

3.5

4

4.5

0110_000

0110_001

0110_010

0110_011

0110_100

66 MHz

2.5

166 MHz

2.5

3

166 MHz

200 MHz

233 MHz

266 MHz

300 MHz

3/6

55/28 MHz

3.5

4

4.5

0111_000

0111_001

0111_010

0111_011

0111_100

66 MHz

3

200 MHz

2.5

3

166 MHz

200 MHz

233 MHz

266 MHz

300 MHz

3/6

66/33 MHz

3.5

4

4.5

1000_000

1000_001

1000_010

1000_011

1000_100

66 MHz

3

200 MHz

2.5

3

166 MHz

200 MHz

233 MHz

266 MHz

300 MHz

4/8

50/25 MHz

3.5

4

4.5

1001_000

66 MHz

3.5

233 MHz

2.5

166 MHz

4/8

58/29 MHz

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

28

Clock Configuration Modes

Table 17. Clock Configuration Modes in PCI Host Mode (continued)

Input Clock

Frequency

(Bus)

CPM

Multiplication

Factor

Core

Multiplication

Factor

MODCK_H –

MODCK[1–3]

CPM

Frequency

Core

Frequency

PCI Division

Factor

PCI

Frequency

(1)

(2)

2

1001_001

1001_010

1001_011

1001_100

66 MHz

3.5

233 MHz

3

200 MHz

233 MHz

266 MHz

300 MHz

4/8

58/29 MHz

3.5

4

4.5

1010_000

1010_001

1010_010

1010_011

1010_100

100 MHz

2

200 MHz

2

2.5

3

200 MHz

250 MHz

300 MHz

350 MHz

400 MHz

3/6

66/33 MHz

3.5

4

1011_000

1011_001

1011_010

1011_011

1011_100

Notes:

100 MHz

2.5

250 MHz

2

2.5

3

200 MHz

250 MHz

300 MHz

350 MHz

400 MHz

4/8

62/31 MHz

62/31MHz

62/31 MHz

3.5

4

1. Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that

the resulting configuration does not exceed the frequency rating of the user’s part.

2. The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is divided

by 2 (33 instead of 66 MHz, etc.). Refer to Table 15.

3. In this mode, PCI_MODCK must be “0”.

3.2.2

PCI Agent Mode

The frequencies listed in Table 18 and Table 19 are for the purpose of illustration only. Users must select

a mode and input bus frequency so that the resulting configuration does not exceed the frequency rating

of the user’s device.

Table 18. Clock Default Configurations in PCI Agent Mode (MODCK_HI = 0000)

Input Clock

CPM

Core

60x Bus

MODCK[1–3]

CPM

Frequency

Bus Division

Factor

Frequency Multiplication

Multiplication Frequency

Frequency

(1)

2

(2)

(3)

(4)

(PCI)

Factor

000

001

010

011

66/33 MHz

2/4

3/6

133 MHz

200 MHz

2.5

3

166 MHz

200 MHz

266 MHz

2

3

66 MHz

3

4

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

29

Clock Configuration Modes

Table 18. Clock Default Configurations in PCI Agent Mode (MODCK_HI = 0000) (continued)

Input Clock

CPM

Core

60x Bus

MODCK[1–3]

CPM

Frequency

Bus Division

Factor

Frequency Multiplication

Multiplication Frequency

Frequency

(1)

2

(2)

(3)

(4)

(PCI)

Factor

100

101

66/33 MHz

3/6

4/8

200 MHz

266 MHz

3

3.5

3

240 MHz

280 MHz

300 MHz

2.5

3

80 MHz

88 MHz

100 MHz

110

111

2.5

Notes:

1. Assumes MODCK_HI = 0000.

2. The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is

divided by 2 (33 instead of 66 MHz, etc.) and the CPM multiplication factor is multiplied by 2. Refer to Table 15.

3. Core frequency = (60x bus frequency)(core multiplication factor)

4. Bus frequency = CPM frequency / bus division factor

Table 19 describes all possible clock configurations when using the MPC8265 or the MPC8266’s internal

PCI bridge in agent mode.

Table 19. Clock Configuration Modes in PCI Agent Mode

Input Clock

CPM

Core

60x Bus

MODCK_H –

MODCK[1–3]

CPM

Frequency

Bus Division

Factor

Frequency Multiplication

Multiplication Frequency

Frequency

(1),(2)

1

(3)

(4)

(PCI)

Factor

0001_001

0001_010

0001_011

0001_100

66/33 MHz

2/4

133 MHz

5

6

7

8

166 MHz

200 MHz

233 MHz

266 MHz

4

33 MHz

0010_001

0010_010

0010_011

0010_100

50/25 MHz

3/6

150 MHz

3

180 MHz

210 MHz

240 MHz

270 MHz

2.5

60 MHz

3.5

4

4.5

0011_000

0011_001

0011_010

0011_011

0011_100

66/33 MHz

2/4

133 MHz

2.5

3

110MHz

132 MHz

154 MHz

176MHz

198 MHz

3

44 MHz

3.5

4

4.5

0100_000

0100_001

0100_010

66/33 MHz

3/6

200 MHz

2.5

3

166 MHz

200 MHz

233 MHz

3

66 MHz

3.5

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

30

Clock Configuration Modes

Table 19. Clock Configuration Modes in PCI Agent Mode (continued)

Input Clock

CPM

Core

60x Bus

MODCK_H –

MODCK[1–3]

CPM

Frequency

Bus Division

Factor

Frequency Multiplication

Multiplication Frequency

Frequency

(1),(2)

1

(3)

(4)

(PCI)

Factor

0100_011

0100_100

66/33 MHz

3/6

200 MHz

4

266 MHz

300 MHz

3

66 MHz

4.5

(5)

0101_000

33 MHz

5

166 MHz

2.5

3

166 MHz

200 MHz

233 MHz

266 MHz

300 MHz

2.5

66 MHz

5

0101_001

5

0101_010

3.5

4

5

0101_011

5

0101_100

4.5

0110_000

0110_001

0110_010

0110_011

0110_100

50/25 MHz

4/8

200 MHz

2.5

3

166 MHz

200 MHz

233 MHz

266 MHz

300 MHz

3

66 MHz

3.5

4

4.5

0111_000

0111_001

0111_010

0111_011

66/33 MHz

3/6

200 MHz

2

200 MHz

250 MHz

300 MHz

350 MHz

2

100 MHz

2.5

3

3.5

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

66/33 MHz

3/6

200 MHz

2

2.5

3

160 MHz

200 MHz

240 MHz

280 MHz

320 MHz

360 MHz

2.5

80 MHz

3.5

4

4.5

1001_000

1001_001

1001_010

1001_011

1001_100

66/33 MHz

4/8

266 MHz

2.5

3

166 MHz

200 MHz

233 MHz

266 MHz

300 MHz

4

66 MHz

3.5

4

4.5

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

31

Clock Configuration Modes

Table 19. Clock Configuration Modes in PCI Agent Mode (continued)

Input Clock

CPM

Core

60x Bus

MODCK_H –

MODCK[1–3]

CPM

Frequency

Bus Division

Factor

Frequency Multiplication

Multiplication Frequency

Frequency

(1),(2)

1

(3)

(4)

(PCI)

Factor

1010_000

1010_001

1010_010

1010_011

1010_100

66/33 MHz

4/8

266 MHz

2.5

3

222 MHz

266 MHz

300 MHz

350 MHz

400 MHz

3

88 MHz

3.5

4

4.5

1011_000

1011_001

1011_010

1011_011

1011_100

Notes:

66/33 MHz

4/8

266 MHz

2

2.5

3

212MHz

265 MHz

318 MHz

371 MHz

424 MHz

2.5

106 MHz

3.5

4

1. The frequency depends on the value of PCI_MODCK. If PCI_MODCK is high (logic ‘1’), the PCI frequency is

divided by 2 (33 instead of 66 MHz, etc.) and the CPM multiplication factor is multiplied by 2. Refer to Table 15.

2. Input clock frequency is given only for the purpose of reference. User should set MODCK_H–MODCK_L so that

the resulting configuration does not exceed the frequency rating of the user’s part.

3. Core frequency = (60x bus frequency)(core multiplication factor)

4. Bus frequency = CPM frequency / bus division factor

5. In this mode, PCI_MODCK must be “1”.

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

32

Freescale Semiconductor

Pinout

4 Pinout

This section provides the pin assignments and pinout list for the MPC826xA.

4.1

Pin Assignments

Figure 13 shows the pinout of the MPC826xA’s 480 TBGA package as viewed from the top surface.

1

2

3

4

5 6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

A

B

A

B

C

D

E

F

G

H

J

K

L

M

N

M

N

P

R

T

U

V

W

Y

W

Y

AA

AB

AC

AD

AE

AF

AG

AH

AJ

AA

AB

AC

AD

AE

AF

AG

AH

AJ

1

2

3

4

5 6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29

Not to Scale

Figure 13. Pinout of the 480 TBGA Package as Viewed from the Top Surface

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

33

Pinout

Figure 14 shows the side profile of the TBGA package to indicate the direction of the top surface view.

View

Pressure Sensitive

Copper Heat Spreader

(Oxidized for Insulation)

Adhesive

Etched

Cavity

Die

Attach

Polymide Tape

Die

Glob-Top Filled Area

Soldermask

Glob-Top Dam

Copper Traces

1.27 mm Pitch

Wire Bonds

Figure 14. Side View of the TBGA Package

Table 20 shows the pinout list of the MPC826xA. Table 21 defines conventions and acronyms used in

Table 20.

Table 20. Pinout List

Pin Name

Ball

BR

W5

F4

E2

E3

G1

H5

H2

H1

J5

BG

ABB/IRQ2

TS

A0

A1

A2

A3

A4

A5

J4

A6

J3

A7

J2

A8

J1

A9

K4

K3

K2

K1

L5

L4

L3

L2

L1

A10

A11

A12

A13

A14

A15

A16

A17

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

34

Pinout

Table 20. Pinout List (continued)

Pin Name

Ball

A18

M5

A19

N5

N4

N3

N2

N1

P4

P3

P2

P1

R1

R3

R5

R4

F1

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

TT0

TT1

G4

G3

G2

F2

TT2

TT3

TT4

TBST

TSIZ0

TSIZ1

TSIZ2

TSIZ3

AACK

ARTRY

DBG

DBB/IRQ3

D0

D3

C1

E4

D2

F5

F3

E1

V1

V2

B20

A18

A16

A13

E12

D9

A6

D1

D2

D3

D4

D5

D6

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

35

Pinout

Table 20. Pinout List (continued)

Pin Name

Ball

D7

B5

D8

A20

E17

B15

B13

A11

E9

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

D41

B7

B4

D19

D17

D15

C13

B11

A8

A5

C5

C19

C17

C15

D13

C11

B8

A4

E6

E18

B17

A15

A12

D11

C8

E7

A3

D18

A17

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

36

Pinout

Table 20. Pinout List (continued)

Pin Name

Ball

D42

A14

D43

B12

A10

D8

D44

D45

D46

B6

D47

C4

D48

C18

E16

B14

C12

B10

A7

D49

D50

D51

D52

D53

D54

C6

D55

D5

D56

B18

B16

E14

D12

C10

E8

D57

D58

D59

D60

D61

D62

D6

D63

C2

DP0/RSRV/EXT_BR2

IRQ1/DP1/EXT_BG2

B22

A22

E21

D21

C21

B21

A21

E20

V3

IRQ2/DP2/TLBISYNC/EXT_DBG2

IRQ3/DP3/CKSTP_OUT/EXT_BR3

IRQ4/DP4/CORE_SRESET/EXT_BG3

IRQ5/DP5/TBEN/EXT_DBG3

IRQ6/DP6/CSE0

IRQ7/DP7/CSE1

PSDVAL

TA

C22

V5

TEA

GBL/IRQ1

W1

U2

CI/BADDR29/IRQ2

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

37

Pinout

Table 20. Pinout List (continued)

Pin Name

Ball

WT/BADDR30/IRQ3

U3

L2_HIT/IRQ4

CPU_BG/BADDR31/IRQ5

CPU_DBG

Y4

U4

R2

CPU_BR

Y3

CS0

F25

C29

E27

E28

F26

F27

F28

G25

D29

E29

F29

G28

T5

CS1

CS2

CS3

CS4

CS5

CS6

CS7

CS8

CS9

CS10/BCTL1

CS11/AP0

BADDR27

BADDR28

U1

ALE

T2

BCTL0

A27

C25

E24

D24

C24

B26

A26

B25

A25

E23

B24

A24

B23

A23

D22

PWE0/PSDDQM0/PBS0

PWE1/PSDDQM1/PBS1

PWE2/PSDDQM2/PBS2

PWE3/PSDDQM3/PBS3

PWE4/PSDDQM4/PBS4

PWE5/PSDDQM5/PBS5

PWE6/PSDDQM6/PBS6

PWE7/PSDDQM7/PBS7

PSDA10/PGPL0

PSDWE/PGPL1

POE/PSDRAS/PGPL2

PSDCAS/PGPL3

PGTA/PUPMWAIT/PGPL4/PPBS

PSDAMUX/PGPL5

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

38

Pinout

Table 20. Pinout List (continued)

Pin Name

Ball

(1)

LWE0/LSDDQM0/LBS0/PCI_CFG0

LWE1/LSDDQM1/LBS1/PCI_CFG1

LWE2/LSDDQM2/LBS2/PCI_CFG2

LWE3/LSDDQM3/LBS3/PCI_CFG3

H28

H27

H26

G29

D27

C28

E26

D25

C26

B27

D28

N27

T29

1

LSDA10/LGPL0/PCI_MODCKH0

1

LSDWE/LGPL1/PCI_MODCKH1

1

LOE/LSDRAS/LGPL2/PCI_MODCKH2

1

LSDCAS/LGPL3/PCI_MODCKH3

LGTA/LUPMWAIT/LGPL4/LPBS

1

LGPL5/LSDAMUX/PCI_MODCK

LWR

1

L_A14/PAR

1

L_A15/FRAME /SMI

1

L_A16/TRDY

R27

R26

R29

R28

W29

P28

N26

AA27

P29

AA26

N25

AA25

AB29

AB28

P25

AB27

H29

J29

1

L_A17/IRDY /CKSTP_OUT

1

L_A18/STOP

1

L_A19/DEVSEL

1

L_A20/IDSEL

1

L_A21/PERR

1

L_A22/SERR

1

L_A23/REQ0

1

L_A24/REQ1 /HSEJSW

1

L_A25/GNT0

1

L_A26/GNT1 /HSLED

1

L_A27/GNT2 /HSENUM

1

L_A28/RST /CORE_SRESET

1

L_A29/INTA

1

L_A30/REQ2

1

L_A31/DLLOUT

1

LCL_D0/AD0

1

LCL_D1/AD1

1

LCL_D2/AD2

J28

1

LCL_D3/AD3

J27

1

LCL_D4/AD4

J26

1

LCL_D5/AD5

J25

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

39

Pinout

Table 20. Pinout List (continued)

Pin Name

Ball

1

LCL_D6/AD6

K25

LCL_D7/AD7

LCL_D8/AD8

LCL_D9/AD9

L29

L27

L26

1

LCL_D10/AD10

LCL_D11/AD11

LCL_D12/AD12

LCL_D13/AD13

LCL_D14/AD14

LCL_D15/AD15

LCL_D16/AD16

LCL_D17/AD17

LCL_D18/AD18

LCL_D19/AD19

LCL_D20/AD20

LCL_D21/AD21

LCL_D22/AD22

LCL_D23/AD23

LCL_D24/AD24

LCL_D25/AD25

LCL_D26/AD26

LCL_D27/AD27

LCL_D28/AD28

LCL_D29/AD29

LCL_D30/AD30

L25

M29

M28

M27

M26

N29

T25

U27

U26

U25

V29

V28

V27

V26

W27

W26

W25

Y29

Y28

Y25

AA29

AA28

L28

LCL_D31/AD31

1

LCL_DP0/C0 /BE0

1

LCL_DP1/C1 /BE1

N28

T28

W28

T1

1

LCL_DP2/C2 /BE2

1

LCL_DP3/C3 /BE3

IRQ0/NMI_OUT

IRQ7/INT_OUT/APE

D1

TRST

TCK

AH3

AG5

AJ3

TMS

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

40

Pinout

Table 20. Pinout List (continued)

Pin Name

Ball

TDI

AE6

TDO

AF5

AB4

AG6

AH5

AF6

AA3

AJ4

TRIS

PORESET

HRESET

SRESET

QREQ

RSTCONF

MODCK1/AP1/TC0/BNKSEL0

MODCK2/AP2/TC1/BNKSEL1

MODCK3/AP3/TC2/BNKSEL2

XFC

W2

W3

W4

AB2

AH4

AC29

AC25

AE28

CLKIN1

(2)

2

PA0/RESTART1/DREQ3/FCC2_UTM_TXADDR2

PA1/REJECT1/FCC2_UTM_TXADDR1/DONE3

PA2/CLK20/FCC2_UTM_TXADDR0/DACK3

2

PA3/CLK19/FCC2_UTM_RXADDR0/DACK4/L1RXD1A2

PA4/REJECT2/FCC2_UTM_RXADDR1/DONE4

PA5/RESTART2/DREQ4/FCC2_UTM_RXADDR2

PA6/L1RSYNCA1

AG29

AG28

AG26

2

AE24

PA7/SMSYN2/L1TSYNCA1/L1GNTA1

AH25

2

PA8/SMRXD2/L1RXD0A1/L1RXDA1

AF23

AH23

2

PA9/SMTXD2/L1TXD0A1

2

PA10/FCC1_UT8_RXD0/FCC1_UT16_RXD8/MSNUM5

PA11/FCC1_UT8_RXD1/FCC1_UT16_RXD9/MSNUM4

PA12/FCC1_UT8_RXD2/FCC1_UT16_RXD10/MSNUM3

PA13/FCC1_UT8_RXD3/FCC1_UT16_RXD11/MSNUM2

PA14/FCC1_UT8_RXD4/FCC1_UT16_RXD12/FCC1_RXD3

PA15/FCC1_UT8_RXD5/FCC1_UT16_RXD13/FCC1_RXD2

PA16/FCC1_UT8_RXD6/FCC1_UT16_RXD14/FCC1_RXD1

PA17/FCC1_UT8_RXD7/FCC1_UT16_RXD15/FCC1_RXD0/FCC1_RXD

PA18/FCC1_UT8_TXD7/FCC1_UT16_TXD15/FCC1_TXD0/FCC1_TXD

PA19/FCC1_UT8_TXD6/FCC1_UT16_TXD14/FCC1_TXD1

PA20/FCC1_UT8_TXD5/FCC1_UT16_TXD13/FCC1_TXD2

PA21/FCC1_UT8_TXD4/FCC1_UT16_TXD12/FCC1_TXD3

AE22

2

AH22

2

AJ21

AH20

AG19

2

AF18

AF17

AE16

2

AJ16

2

AG15

2

AJ13

AE13

2

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

41

Pinout

Table 20. Pinout List (continued)

Pin Name

Ball

2

PA22/FCC1_UT8_TXD3/FCC1_UT16_TXD11

AF12

2

PA23/FCC1_UT8_TXD2/FCC1_UT16_TXD10

AG11

2

PA24/FCC1_UT8_TXD1/FCC1_UT16_TXD9/MSNUM1

PA25/FCC1_UT8_TXD0/FCC1_UT16_TXD8/MSNUM0

PA26/FCC1_UTM_RXCLAV/FCC1_UTS_RXCLAV/FCC1_MII_RX_ER

PA27/FCC1_UT_RXSOC/FCC1_MII_RX_DV

AH9

2

AJ8

2

AH7

2

AF7

2

PA28/FCC1_UTM_RXENB/FCC1_UTS_RXENB/FCC1_MII_TX_EN

PA29/FCC1_UT_TXSOC/FCC1_MII_TX_ER

AD5

2

AF1

2

PA30/FCC1_UTM_TXCLAV/FCC1_UTS_TXCLAV/FCC1_MII_CRS/

FCC1_RTS

AD3

2

PA31/FCC1_UTM_TXENB/FCC1_UTS_TXENB/FCC1_MII_COL

PB4/FCC3_TXD3/FCC2_UT8_RXD0/L1RSYNCA2/FCC3_RTS

PB5/FCC3_TXD2/FCC2_UT8_RXD1/L1TSYNCA2/L1GNTA2

PB6/FCC3_TXD1/FCC2_UT8_RXD2/L1RXDA2/L1RXD0A2

PB7/FCC3_TXD0/FCC3_TXD/FCC2_UT8_RXD3/L1TXDA2/L1TXD0A2

PB8/FCC2_UT8_TXD3/FCC3_RXD0/FCC3_RXD/TXD3/L1RSYNCD1

PB9/FCC2_UT8_TXD2/FCC3_RXD1/L1TXD2A2/L1TSYNCD1/L1GNTD1

PB10/FCC2_UT8_TXD1/FCC3_RXD2/L1RXDD1

AB5

2

AD28

AD26

AD25

2

AE26

AH27

AG24

AH24

2

PB11/FCC3_RXD3/FCC2_UT8_TXD0/L1TXDD1

AJ24

AG22

AH21

AG20

2

PB12/FCC3_MII_CRS/L1CLKOB1/L1RSYNCC1/TXD2

PB13/FCC3_MII_COL/L1RQB1/L1TSYNCC1/L1GNTC1/L1TXD1A2

PB14/FCC3_MII_TX_EN/RXD3/L1RXDC1

2

PB15/FCC3_MII_TX_ER/RXD2/L1TXDC1

AF19

2

PB16/FCC3_MII_RX_ER/L1CLKOA1/CLK18

AJ18

AJ17

AE14

2

PB17/FCC3_MII_RX_DV/L1RQA1/CLK17

2

PB18/FCC2_UT8_RXD4/FCC2_RXD3/L1CLKOD2/L1RXD2A2

PB19/FCC2_UT8_RXD5/FCC2_RXD2/L1RQD2/L1RXD3A2

PB20/FCC2_UT8_RXD6/FCC2_RXD1/L1RSYNCD2/L1TXD1A1

2

AF13

2

AG12

PB21/FCC2_UT8_RXD7/FCC2_RXD0/FCC2_RXD/L1TSYNCD2/L1GNTD2/ AH11

L1TXD2A1

2

PB22/FCC2_UT8_TXD7/FCC2_TXD0/FCC2_TXD/L1RXD1A1/L1RXDD2

PB23/FCC2_UT8_TXD6/FCC2_TXD1/L1RXD2A1/L1TXDD2

PB24/FCC2_UT8_TXD5/FCC2_TXD2/L1RXD3A1/L1RSYNCC2

PB25/FCC2_UT8_TXD4/FCC2_TXD3/L1TSYNCC2/L1GNTC2/L1TXD3A1

PB26/FCC2_MII_CRS/FCC2_UT8_TXD1/L1RXDC2

AH16

2

AE15

2

AJ9

2

AE9

2

AJ7

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

42

Pinout

Table 20. Pinout List (continued)

Pin Name

Ball

2

PB27/FCC2_MII_COL/FCC2_UT8_TXD0/L1TXDC2

AH6

2

PB28/FCC2_MII_RX_ER/FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1

AE3

AE2

PB29/FCC2_UTM_RXCLAV/FCC2_UTS_RXCLAV/L1RSYNCB2/

FCC2_MII_TX_EN

2

PB30/FCC2_MII_RX_DV/FCC2_UT_TXSOC/L1RXDB2

PB31/FCC2_MII_TX_ER/FCC2_UT_RXSOC/L1TXDB2

PC0/DREQ1/BRGO7/SMSYN2/L1CLKOA2

AC5

AC4

2

AB26

PC1/DREQ2/BRGO6/L1RQA2

AD29

2

PC2/FCC3_CD/FCC2_UT8_TXD3/DONE2

AE29

AE27

2

PC3/FCC3_CTS/FCC2_UT8_TXD2/DACK2/CTS4

PC4/FCC2_UTM_RXENB/FCC2_UTS_RXENB/SI2_L1ST4/FCC2_CD

PC5/FCC2_UTM_TXCLAV/FCC2_UTS_TXCLAV/SI2_L1ST3/FCC2_CTS

2

AF27

AF24

2

PC6/FCC1_CD/L1CLKOC1/FCC1_UTM_RXADDR2/FCC1_UTS_RXADDR/ AJ26

FCC1_UTM_RXCLAV1

PC7/FCC1_CTS/L1RQC1/FCC1_UTM_TXADDR2/FCC1_UTS_TXADDR2/ AJ25

FCC1_UTM_TXCLAV1

PC8/CD4/RENA4/FCC1_UT16_TXD0/SI2_L1ST2/CTS3

AF22

2

PC9/CTS4/CLSN4/FCC1_UT16_TXD1/SI2_L1ST1/L1TSYNCA2/L1GNTA2 AE21

2

PC10/CD3/RENA3/FCC1_UT16_TXD2/SI1_L1ST4/FCC2_UT8_RXD3

PC11/CTS3/CLSN3/L1CLKOD1/L1TXD3A2/FCC2_UT8_RXD2

AF20

2

AE19

AE18

2

PC12/CD2/RENA2/SI1_L1ST3/FCC1_UTM_RXADDR1/

FCC1_UTS_RXADDR1

PC13/CTS2/CLSN2/L1RQD1/FCC1_UTM_TXADDR1/

FCC1_UTS_TXADDR1

AH18

2

PC14/CD1/RENA1/FCC1_UTM_RXADDR0/FCC1_UTS_RXADDR0

AH17

AG16

PC15/CTS1/CLSN1/SMTXD2/FCC1_UTM_TXADDR0/

FCC1_UTS_TXADDR0

2

PC16/CLK16/TIN4

AF15

2

PC17/CLK15/TIN3/BRGO8

PC18/CLK14/TGATE2

AJ15

AH14

AG13

AH12

2

PC19/CLK13/BRGO7/SPICLK

PC20/CLK12/TGATE1

2

PC21/CLK11/BRGO6

AJ11

2

PC22/CLK10/DONE1

AG10

2

PC23/CLK9/BRGO5/DACK1

PC24/FCC2_UT8_TXD3/CLK8/TOUT4

PC25/FCC2_UT8_TXD2/CLK7/BRGO4

AE10

2

AF9

2

AE8

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

43

Pinout

Table 20. Pinout List (continued)

Pin Name

Ball

2

PC26/CLK6/TOUT3/TMCLK

AJ6

2

PC27/FCC3_TXD/FCC3_TXD0/CLK5/BRGO3

PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2

PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1

PC30/FCC2_UT8_TXD3/CLK2/TOUT1

PC31/CLK1/BRGO1

AG2

2

AF3

AF2

AE1

2

AD1

2

PD4/BRGO8/L1TSYNCD1/L1GNTD1/FCC3_RTS/SMRXD2

PD5/FCC1_UT16_TXD3/DONE1

AC28

AD27

2

PD6/FCC1_UT16_TXD4/DACK1

AF29

AF28

2

PD7/SMSYN1/FCC1_UTM_TXADDR3/FCC1_UTS_TXADDR3/

FCC2_UTM_TXADDR4/FCC1_TXCLAV2

2

PD8/SMRXD1/FCC2_UT_TXPRTY/BRGO5

PD9/SMTXD1/FCC2_UT_RXPRTY/BRGO3

PD10/L1CLKOB2/FCC2_UT8_RXD1/L1RSYNCB1/BRGO4

PD11/L1RQB2/FCC2_UT8_RXD0/L1TSYNCB1/L1GNTB1

PD12/SI1_L1ST2/L1RXDB1

AG25

AH26

2

AJ27

AJ23

AG23

2

PD13/SI1_L1ST1/L1TXDB1

AJ22

AE20

PD14/FCC1_UT16_RXD0/L1CLKOC2/I2CSCL

PD15/FCC1_UT16_RXD1/L1RQC2/I2CSDA

PD16/FCC1_UT_TXPRTY/L1TSYNCC1/L1GNTC1/SPIMISO

PD17/FCC1_UT_RXPRTY/BRGO2/SPIMOSI

2

AJ20

AG18

AG17

2

PD18/FCC1_UTM_RXADDR4/FCC1_UTS_RXADDR4/

FCC1_UTM_RXCLAV3/FCC2_UTM_RXADDR3/SPICLK

AF16

2

PD19/FCC1_UTM_TXADDR4/FCC1_UTS_TXADDR4/

AH15

FCC1_UTM_TXCLAV3/FCC2_UTM_TXADDR3/SPISEL/BRGO1

2

PD20/RTS4/TENA4/FCC1_UT16_RXD2/L1RSYNCA2

PD21/TXD4/FCC1_UT16_RXD3/L1RXD0A2/L1RXDA2

PD22/RXD4/FCC1_UT16_TXD5/L1TXD0A2/L1TXDA2

PD23/RTS3/TENA3/FCC1_UT16_RXD4/L1RSYNCD1

PD24/TXD3/FCC1_UT16_RXD5/L1RXDD1

AJ14

AH13

2

AJ12

AE12

2

AF10

2

PD25/RXD3/FCC1_UT16_TXD6/L1TXDD1

AG9

AH8

AG7

PD26/RTS2/TENA2/FCC1_UT16_RXD6/L1RSYNCC1

PD27/TXD2/FCC1_UT16_RXD7/L1RXDC1

2

PD28/RXD2/FCC1_UT16_TXD7/L1TXDC1

AE4

2

PD29/RTS1/TENA1/FCC1_UTM_RXADDR3/FCC1_UTS_RXADDR3/

FCC1_UTM_RXCLAV2/FCC2_UTM_RXADDR4

AG1

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

44

Pinout

Table 20. Pinout List (continued)

Pin Name

Ball

2

PD30/FCC2_UTM_TXENB/FCC2_UTS_TXENB/TXD1

AD4

AD2

AB3

B9

PD31/RXD1

VCCSYN

VCCSYN1

GNDSYN

AB1

1,(3)

CLKIN2

AE11

U5

(4)

SPARE4

1,(5)

PCI_MODE

AF25

V4

4

SPARE6

(6)

THERMAL0

AA1

AG4

6

THERMAL1

I/O power

AG21, AG14, AG8, AJ1, AJ2, AH1, AH2,

AG3, AF4, AE5, AC27, Y27, T27, P27,

K26, G27, AE25, AF26, AG27, AH28,

AH29, AJ28, AJ29, C7, C14, C16, C20,

C23, E10, A28, A29, B28, B29, C27,

D26, E25, H3, M4, T3, AA4, A1, A2, B1,

B2, C3, D4, E5

Core Power

Ground

U28, U29, K28, K29, A9, A19, B19, M1,

M2, Y1, Y2, AC1, AC2, AH19, AJ19,

AH10, AJ10, AJ5

AA5, AF21, AF14, AF8, AE7, AF11,

AE17, AE23, AC26, AB25, Y26, V25,

T26, R25, P26, M25, K27, H25, G26,

D7, D10, D14, D16, D20, D23, C9, E11,

E13, E15, E19, E22, B3, G5, H4, K5,

M3, P5, T4, Y5, AA2, AC3

Notes:

1. MPC8265 and MPC8266 only.

2. The default configuration of the CPM pins (PA[0–31], PB[4–31], PC[0–31], PD[4–31]) is input. To prevent excessive

DC current, it is recommended to either pull unused pins to GND or VDDH, or to configure them as outputs.

3. On PCI devices (MPC8265 and MPC8266) this pin should be used as CLKIN2. On non-PCI devices (MPC8260A

and MPC8264) this is a spare pin that must be pulled down or left floating.

4. Must be pulled down or left floating.

5. On PCI devices (MPC8265 and MPC8266) this pin should be asserted if the PCI function is desired or pulled up or

left floating if PCI is not desired. On non-PCI devices (MPC8260A and MPC8264) this is a spare pin that must be pulled

up or left floating.

6. For information on how to use this pin, refer to MPC8260 PowerQUICC II Thermal Resistor Guide available at

www.freescale.com.

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

45

Package Description

Symbols used in Table 20 are described in Table 21.

Table 21. Symbol Legend

Symbol

Meaning

OVERBAR

UTM

Signals with overbars, such as TA, are active low.

Indicates that a signal is part of the UTOPIA master interface.

Indicates that a signal is part of the UTOPIA slave interface.

Indicates that a signal is part of the 8-bit UTOPIA interface.

Indicates that a signal is part of the 16-bit UTOPIA interface.

Indicates that a signal is part of the media independent interface.

UTS

UT8

UT16

MII

5 Package Description

The following sections provide the package parameters and mechanical dimensions for the MPC826xA.

5.1

Package Parameters

Package parameters are provided in Table 22. The package type is a 37.5 x 37.5 mm, 480-lead TBGA.

Table 22. Package Parameters

Parameter

Package Outline

Value

37.5 x 37.5 mm

Interconnects

Pitch

480 (29 x 29 ball array)

1.27 mm

Nominal unmounted package height 1.55 mm

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

46

Freescale Semiconductor

Package Description

5.2

Mechanical Dimensions

Figure 15 provides the mechanical dimensions and bottom surface nomenclature of the 480 TBGA

package.

Notes:

1. Dimensions and Tolerancing per

ASME Y14.5M-1994.

2. Dimensions in millimeters.

3. Dimension b is measured at the

Millimeters

Dim

Min

Max

A

1.45

0.60

0.85

0.25

0.65

1.65

A1

A2

A3

b

0.70

0.95

—

0.85

D

37.50 BSC

35.56 REF

1.27 BSC

37.50 BSC

35 56 REF

D1

e

E

E1

Figure 15. Mechanical Dimensions and Bottom Surface Nomenclature

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

47

Ordering Information

6 Ordering Information

Figure 16 provides an example of the Freescale part numbering nomenclature for the MPC826xA. In

addition to the processor frequency, the part numbering scheme also consists of a part modifier that

indicates any enhancement(s) in the part from the original production design. Each part number also

contains a revision code that refers to the die mask revision number and is specified in the part numbering

scheme for identification purposes only. For more information, contact your local Freescale sales office.

MPC 826X A C ZU XXX X

Product Code

Die Revision Level

Device Number

Process Technology

(None = 0.29 micron

A = 0.25 micron)

Processor Frequency

(CPU/CPM/Bus)

Package

ZU = 480 TBGA

VR = 516 PBGA

Temperature Range

(Blank = 0 to 105 °C

C = -40 to 105 °C

Figure 16. Freescale Part Number Key

7 Document Revision History

Table 23 lists significant changes in each revision of this document.

Table 23. Document Revision History

Revision

Date

Substantive Changes

0

—

Initial version

0.1

0.2

8/2001

• Table 8: Change to sp20/sp21.

11/2001 • Revision of Table 5, “Power Dissipation”

• Modifications to Figure 9, Table 2,Table 10, Table 11, and Table 18

• Modification to pinout diagram, Figure 13

• Additional revisions to text and figures throughout

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

48

Document Revision History

Table 23. Document Revision History (continued)

Substantive Changes

Revision

Date

0.3

11/2001 • Table 1: note 3

• Section 2.1: Removal of “Warning” recommending use of bootstrap diodes. They are not

needed.

• Table 9: Change to sp12.

• Table 10: Change to sp32.

• Note 2 for Table 16 and Table 17

• Addition of note at beginning of Section 3.2

• Note 1 for Table 18 and Table 19

• Table 20: Additions to B27, C28, D25, D27, E26, G29, H26–28, N25, P29, AF25, AA25, AB27

0.4

0.5

2/2002

3/2002

• Note 2 for Table 2 (changes in italics): “...greater than or equal to 266 MHz, 200 MHz CPM...”

• Table 19: Core and bus frequency values for the following ranges of MODCK_HMODCK:

0011_000 to 0011_100 and 1011_000 to 1011_1000

• Table 20: Notes added to pins at AE11, AF25, U5, and V4.

• Table 20: Modified notes to pins AE11 and AF25.

• Table 20: Addition of note to pins AA1 and AG4 (Therm0 and Therm1).

0.6

0.7

3/2002

5/2002

• Table 20: Modified notes to pins AE11 and AF25.

• Section 1, “Features”: minimum supported core frequency of 150 MHz

• Section 1, “Features”: updated performance values (under “Dual-issue integer core”)

• Table 2: Note 2 (changes in italics): “...less than or equal to 233 MHz, 166 MHz CPM...”

• Table 2: Addition of note 3.

0.8

0.9

1/2003

8/2003

• Table 2: Modification to supply voltage ranges reflected in notes 2, 3, and 4.

• Table 4: Addition of θ and θ

.

JB

JC

• Table 7, Figure 8: Addition of sp42a/sp43a.

• Figure 3, Figure 4: Addition of note for FCC output.

• Figure 5, Figure 6, Figure 7: Addition of notes.

• Table 14, Table 17, and Table 19: Removal of PLL bypass mode from clock tables.

• Note: In revision 0.3, sp30 (Table 10) was changed. This change was not previously recorded

in this “Document Revision History” Table.

• Removal of “HiP4 PowerQUICC II Documentation” table. These supplemental specifications

have been replaced by revision 1 of the MPC8260 PowerQUICC II™ Family Reference

Manual.

• Figure 1 and Section 1, “Features”: Addition of MPC8255 notes

• Addition of Figure 2

• Addition of VCCSYN to “Note: Core, PLL, and I/O Supply Voltages” following Table 2

• Addition of note 1 to Table 3

• Table 4: Changes to θ and θ and θ .

JA

JB

JC

• Addition of notes or modifications to Figure 6, Figure 7, and Figure 8

• Table 9: Change of sp10.

• Addition of Table 15.

• Addition of note 2 to Table 20

• Table 20: Addition of FCC2 Rx and Tx [3,4] to CPM pins PD7, PD18, PD19, and PD29. Also,

the addition of SPICLK to PC19. They are documented correctly in the parallel I/O ports

chapter in the MPC8260 PowerQUICC II™ Family Reference Manual but had previously

been omitted from Table 20.

1.0

1.1

9/2005

• Document template update

• Addition of Table 12.

03/2006

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

49

Document Revision History

THIS PAGE INTENTIONALLY LEFT BLANK

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

50

Document Revision History

THIS PAGE INTENTIONALLY LEFT BLANK

MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 1.1

Freescale Semiconductor

51

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Document Number: MPC8260AEC

Rev. 1.1

03/2006


型号：	MPC8266AVRIFBX
厂家：	NXP
描述：	32-BIT, 200MHz, RISC PROCESSOR, PBGA516, PLASTIC, BGA-516 时钟外围集成电路
文件：	总52页 (文件大小：884K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MPC8266AVRIFBX [NXP]

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