MPC8272CZQMIBA_技术文档

Document Number: MPC8272EC

Rev. 3, 09/2011

Freescale Semiconductor

Technical Data

MPC8272

PowerQUICC II Family

Hardware Specifications

Contents

This document contains detailed information about power

1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

2. Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . 7

3. DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . 9

4. Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . 14

5. Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6. AC Electrical Characteristics . . . . . . . . . . . . . . . . . . 18

7. Clock Configuration Modes . . . . . . . . . . . . . . . . . . . 27

8. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

9. Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 56

10. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . 58

11. Document Revision History . . . . . . . . . . . . . . . . . . . 58

considerations, DC/AC electrical characteristics, and AC

timing specifications for .13µm (HiP7) members of the

PowerQUICC II family of integrated communications

processors—the MPC8272, the MPC8248, the MPC8271,

and the MPC8247. They include on a single chip a 32-bit

Power Architecture® core that incorporates memory

management units (MMUs) and instruction and data caches

and that implements the Power Architecture instruction set;

a modified communications processor module (CPM); and

an integrated security engine (SEC) for encryption (the

MPC8272 and the MPC8248 only).

All four devices are collectively referred to throughout this

hardware specification as “the MPC8272” unless otherwise

noted.

Overview

1 Overview

This table shows the functionality supported by each SoC in the MPC8272 family.

Table 1. MPC8272 PowerQUICC II Family Functionality

SoCs

Functionality

MPC8272

MPC8248

MPC8271

MPC8247

1

Package

516 PBGA

Serial communications controllers (SCCs)

QUICC multi-channel controller (QMC)

Fast communication controllers (FCCs)

I-Cache (Kbyte)

3

Yes

2

3

Yes

2

3

Yes

2

3

Yes

2

16

2

16

2

16

2

16

2

D-Cache (Kbyte)

Ethernet (10/100)

UTOPIA II Ports

1

0

1

0

Multi-channel controllers (MCCs)

PCI bridge

0

Yes

—

1

Yes

—

1

Yes

—

1

Yes

—

1

Transmission convergence (TC) layer

Inverse multiplexing for ATM (IMA)

Universal serial bus (USB) 2.0 full/low rate

Security engine (SEC)

Yes

—

1

See Table 2.

Devices in the MPC8272 family are available in two packages—the VR or ZQ package—as shown in .

For package ordering information, see Section 10, “Ordering Information.”

Table 2. MPC8272 PowerQUICC II Device Packages

Code

VR

ZQ

(Package)

(516 PBGA—Lead free)

(516 PBGA—Lead spheres)

MPC8272VR

MPC8248VR

MPC8271VR

MPC8247VR

MPC8272ZQ

MPC8248ZQ

MPC8271ZQ

MPC8247ZQ

Device

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

2

Freescale Semiconductor

Overview

This figure shows the block diagram of the SoC.

16 KB

I-Cache

Security (SEC)1

I-MMU

System Interface Unit

(SIU)

60x Bus

G2_LE Core

16 KB

Bus Interface Unit

D-Cache

PCI Bus

60x-to-PCI

Bridge

D-MMU

32 bits, up to 66 MHz

Memory Controller

Communication Processor Module (CPM)

Clock Counter

16 KB

Data

RAM

4 KB

Instruction

RAM

Timers

Serial

DMA

Interrupt

Controller

System Functions

Parallel I/O

32-bit RISC Microcontroller

and Program ROM

Virtual

IDMAs

Baud Rate

Generators

I²C

USB 2.0

FCC1

FCC2

SCC1

SCC3

SCC4

SMC1

SMC2

SPI

Time Slot Assigner

Serial interface

Serial Interface

Non-Multiplexed

I/O

2 MII/RMII

Ports

1 8-bit Utopia

Port2

2 TDM Ports

Notes:

1 MPC8272/8248 only

2 MPC8272/8271 only

Figure 1. SoC Block Diagram

1.1

Features

The major features of the SoC are as follows:

•

Dual-issue integer (G2_LE) core

— A core version of the MPC603e microprocessor

— System core microprocessor supporting frequencies of 266–400 MHz

— Separate 16 KB data and instruction caches:

– Four-way set associative

– Physically addressed

– LRU replacement algorithm

— Power Architecture®-compliant memory management unit (MMU)

— Common on-chip processor (COP) test interface

— Supports bus snooping for cache coherency

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

3

Overview

— Floating-point unit (FPU) supports floating-point arithmetic

— Support for cache locking

•

Low-power consumption

Separate power supply for internal logic (1.5 V) and for I/O (3.3 V)

Separate PLLs for G2_LE core and for the communications processor module (CPM)

— G2_LE core and CPM can run at different frequencies for power/performance optimization

— Internal core/bus clock multiplier that provides ratios 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 4.5:1, 5:1,

5.5:1, 6:1, 7:1, 8:1

— Internal CPM/bus clock multiplier that provides ratios 2:1, 2.5:1, 3:1, 3.5:1, 4:1, 5:1, 6:1, 8:1

ratios

•

64-bit data and 32-bit address 60x bus

— Bus supports multiple master designs—up to two external masters

— Supports single transfers and burst transfers

— 64-, 32-, 16-, and 8-bit port sizes controlled by on-chip memory controller

60x-to-PCI bridge

— Programmable host bridge and agent

— 32-bit data bus, 66 MHz, 3.3 V

— Synchronous and asynchronous 60x and PCI clock modes

— All internal address space available to external PCI host

— DMA for memory block transfers

– PCI-to-60x address remapping

•

System interface unit (SIU)

— Clock synthesizer

— Reset controller

— Real-time clock (RTC) register

— Periodic interrupt timer

— Hardware bus monitor and software watchdog timer

— IEEE 1149.1 JTAG test access port

Eight bank memory controller

— Glueless interface to SRAM, page mode SDRAM, DRAM, EPROM, Flash, and other

user-definable peripherals

— Byte write enables

— 32-bit address decodes with programmable bank size

— Three user-programmable machines, general-purpose chip-select machine, and page mode

pipeline SDRAM machine

— Byte selects for 64-bit bus width (60x)

— Dedicated interface logic for SDRAM

Disable CPU mode

•

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

4

Freescale Semiconductor

Overview

•

Integrated security engine (SEC) (MPC8272 and MPC8248 only)

— Supports DES, 3DES, MD-5, SHA-1, AES, PKEU, RNG and RC-4 encryption algorithms

in hardware

Communications processor module (CPM)

— Embedded 32-bit communications processor (CP) uses a RISC architecture for flexible support

for communications peripherals

— Interfaces to G2_LE core through on-chip dual-port RAM and DMA controller. (Dual-port

RAM size is 16 KB plus 4 KB dedicated instruction RAM.)

— Microcode tracing capabilities

— Eight CPM trap registers

•

Universal serial bus (USB) controller

— Supports USB 2.0 full/low rate compatible

— USB host mode

– Supports control, bulk, interrupt, and isochronous data transfers

– CRC16 generation and checking

– NRZI encoding/decoding with bit stuffing

– Supports both 12- and 1.5-Mbps data rates (automatic generation of preamble token and

data rate configuration). Note that low-speed operation requires an external hub.

– Flexible data buffers with multiple buffers per frame

– Supports local loopback mode for diagnostics (12 Mbps only)

— Supports USB slave mode

– Four independent endpoints support control, bulk, interrupt, and isochronous data transfers

– CRC16 generation and checking

– CRC5 checking

– NRZI encoding/decoding with bit stuffing

– 12- or 1.5-Mbps data rate

– Flexible data buffers with multiple buffers per frame

– Automatic retransmission upon transmit error

— Serial DMA channels for receive and transmit on all serial channels

— Parallel I/O registers with open-drain and interrupt capability

— Virtual DMA functionality executing memory-to-memory and memory-to-I/O transfers

— Two fast communication controllers (FCCs) supporting the following protocols:

– 10-/100-Mbit Ethernet/IEEE 802.3 CDMA/CS interface through media independent

interface (MII)

– Transparent

– HDLC—up to T3 rates (clear channel)

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

5

Overview

– One of the FCCs supports ATM (MPC8272 and MPC8271 only)—full-duplex SAR at 155

Mbps, 8-bit UTOPIA interface 31 Mphys, AAL5, AAL1, AAL2, AAL0 protocols, TM 4.0

CBR, VBR, UBR, ABR traffic types, up to 64-K external connections

— Three serial communications controllers (SCCs) identical to those on the MPC860 supporting

the digital portions of the following protocols:

– Ethernet/IEEE 802.3 CDMA/CS

– HDLC/SDLC and HDLC bus

– Universal asynchronous receiver transmitter (UART)

– Synchronous UART

– Binary synchronous (BiSync) communications

– Transparent

– QUICC multichannel controller (QMC) up to 64 channels

• Independent transmit and receive routing, frame synchronization.

• Serial-multiplexed (full-duplex) input/output 2048, 1544, and 1536 Kbps PCM

highways

• Compatible with T1/DS1 24-channel and CEPT E1 32-channel PCM highway, ISDN

basic rate, ISDN primary rate, and user defined.

• Subchanneling on each time slot.

• Independent transmit and receive routing, frame synchronization and clocking

• Concatenation of any not necessarily consecutive time slots to channels independently

for receiver/transmitter

• Supports H1,H11, and H12 channels

• Allows dynamic allocation of channels

– SCC3 in NMSI mode is not usable when USB is enabled.

— Two serial management controllers (SMCs), identical to those of the MPC860

– Provides management for BRI devices as general-circuit interface (GCI) controllers in

time-division-multiplexed (TDM) channels

– Transparent

– UART (low-speed operation)

— One serial peripheral interface identical to the MPC860 SPI

2

— One I C controller (identical to the MPC860 I C controller)

– Microwire compatible

– Multiple-master, single-master, and slave modes

— Up to two TDM interfaces

– Supports one groups of two TDM channels

– 1024 bytes of SI RAM

— Eight independent baud rate generators and 14 input clock pins for supplying clocks to FCC,

SCC, SMC, and USB serial channels

— Four independent 16-bit timers that can be interconnected as two 32-bit timers

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

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Freescale Semiconductor

Operating Conditions

•

PCI bridge

— PCI Specification revision 2.2-compliant and supports frequencies up to 66 MHz

— On-chip arbitration

— Support for PCI to 60x memory and 60x memory to PCI streaming

— PCI host bridge or peripheral capabilities

— Includes four DMA channels for the following transfers:

– PCI-to-60x to 60x-to-PCI

– 60x-to-PCI to PCI-to-60x

– PCI-to-60x to PCI-to-60x

– 60x-to-PCI to 60x-to-PCI

— Includes the configuration registers required by the PCI standard (which are automatically

loaded from the EPROM to configure the MPC8272) and message and doorbell registers

— Supports the I O standard

2

— Hot-Swap friendly (supports the Hot Swap Specification as defined by PICMG 2.1 R1.0

August 3, 1998)

— Support for 66 MHz, 3.3 V specification

— 60x-PCI bus core logic, which uses a buffer pool to allocate buffers for each port

2 Operating Conditions

This table shows the maximum electrical ratings.

1

Table 3. Absolute Maximum Ratings

Rating Symbol

Value

Unit

2

Core supply voltage

VDD

VCCSYN

VDDH

VIN

–0.3 – 2.25

–0.3 – 4.0

V

2

PLL supply voltage

3

I/O supply voltage

V

4

Input voltage

GND(–0.3) – 3.6

120

V

Junction temperature

T

°C

j

Storage temperature range

T

(–55) – (+150)

STG

1

Absolute maximum ratings are stress ratings only; functional operation (see Table 4) at the maximums is not

guaranteed. Stress beyond those listed may affect device reliability or cause permanent damage.

Caution: VDD/VCCSYN must not exceed VDDH by more than 0.4 V during normal operation. It is recommended that

VDD/VCCSYN should be raised before or simultaneous with VDDH during power-on reset. VDD/VCCSYN may

exceed VDDH by more than 0.4 V during power-on reset for no more than 100 ms.

Caution: VDDH can exceed VDD/VCCSYN by 3.3 V during power on reset by no more than 100 mSec. VDDH should

not exceed VDD/VCCSYN by more than 2.5 V during normal operation.

Caution: VIN must not exceed VDDH by more than 2.5 V at any time, including during power-on reset.

2

3

4

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

7

Operating Conditions

This table lists recommended operational voltage conditions.

1

Table 4. Recommended Operating Conditions

Rating

Symbol

Value

Unit

Core supply voltage

PLL supply voltage

I/O supply voltage

Input voltage

VDD

VCCSYN

VDDH

VIN

1.425 – 575

V

3.135 – 3.465

V

GND (–0.3) – 3.465

V

2

Junction temperature (maximum)

Ambient temperature

T

105

°C

j

2

T

0–70

A

1

2

Caution: These are the recommended and tested operating conditions. Proper operation outside of these conditions

is not guaranteed.

Note that for extended temperature parts the range is (-40) – 105 .

T

j

A

This SoC contains circuitry protecting against damage due to high static voltage or electrical fields;

however, it is advised that normal precautions be taken to avoid application of any voltages higher than

maximum-rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused

inputs are tied to an appropriate logic voltage level (either GND or V ).

CC

This figure shows the undershoot and overshoot voltage of the 60x bus memory interface of the SoC. Note

that in PCI mode the I/O interface is different.

4 V

GV + 5%

DD

V

GV

IH

DD

GND

GND – 0.3 V

IL

GND – 1.0 V

Not to exceed 10%

of t

SDRAM_CLK

Figure 2. Overshoot/Undershoot Voltage

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

8

Freescale Semiconductor

DC Electrical Characteristics

3 DC Electrical Characteristics

This table shows DC electrical characteristics.

1

Table 5. DC Electrical Characteristics

Characteristic

Symbol

Min

Max

Unit

2

Input high voltage—all inputs except TCK, TRST and PORESET

V

2.0

GND

2.4

GND

—

3.465

0.8

3.465

0.4

10

V

IH

3

Input low voltage

V

IL

CLKIN input high voltage

V

IHC

CLKIN input low voltage

V

I

V

ILC

4

Input leakage current, V = VDDH

µA

V

IN

2

Hi-Z (off state) leakage current, V = VDDH

I

—

10

IN

OZ

Signal low input current, V = 0.8 V

I

—

1

IL

L

Signal high input current, V = 2.0 V

I

—

1

IH

H

Output high voltage, I = –2 mA

V

2.4

—

OH

except UTOPIA mode, and open drain pins

5

In UTOPIA mode (UTOPIA pins only): I = -8.0mA

OH

PA[8–31]

PB[18–31]

PC[0–1,4–29]

PD[7–25, 29–31]

5

In UTOPIA mode (UTOPIA pins only): I = 8.0mA

V

—

0.5

V

OL

PA[8–31]

PB[18–31]

PC[0–1,4–29]

PD[7–25, 29–31]

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

9

DC Electrical Characteristics

1

Table 5. DC Electrical Characteristics (continued)

Characteristic

Symbol

Min

Max

Unit

I

= 6.0mA

V

—

0.4

V

OL

BR

BG/IRQ6

ABB/IRQ2

TS

A[0-31]

TT[0-4]

TBST

TSIZE[0–3]

AACK

ARTRY

DBG/IRQ7

DBB/IRQ3

D[0–63]

IRQ3/CKSTP_OUT/EXT_BR3

IRQ4/CORE_SRESET/EXT_BG3

IRQ5/TBEN/EXT_DBG3/CINT

PSDVAL

TA

TEA

GBL/IRQ1

CI/BADDR29/IRQ2

WT/BADDR30/IRQ3

BADDR31/IRQ5/CINT

CPU_BR/INT_OUT

IRQ0/NMI_OUT

PORESET/PCI_RST

HRESET

SRESET

RSTCONF

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

10

Freescale Semiconductor

DC Electrical Characteristics

1

Table 5. DC Electrical Characteristics (continued)

Characteristic Symbol

Min

Max

Unit

I

= 5.3mA

V

—

0.4

V

OL

CS[0–5]

CS6/BCTL1/SMI

CS7/TLBSYNC

BADDR27/ IRQ1

BADDR28/ IRQ2

ALE/ IRQ4

BCTL0

PWE[0–7]/PSDDQM[0–7]/PBS[0–7]

PSDA10/PGPL0

PSDWE/PGPL1

POE/PSDRAS/PGPL2

PSDCAS/PGPL3

PGTA/PUPMWAIT/PGPL4

PSDAMUX/PGPL5

PCI_CFG0 (PCI_HOST_EN)

PCI_CFG1 (PCI_ARB_EN)

PCI_CFG2 (DLL_ENABLE)

MODCK1/RSRV/TC(0)/BNKSEL(0)

MODCK2/CSE0/TC(1)/BNKSEL(1)

MODCK3CSE1/TC(2)/BNKSEL(2)

I

= 3.2mA

OL

PCI_PAR

PCI_FRAME

PCI_TRDY

PCI_IRDY

PCI_STOP

PCI_DEVSEL

PCI_IDSEL

PCI_PERR

PCI_SERR

PCI_REQ0

PCI_REQ1/ CPI_HS_ES

PCI_GNT0

PCI_GNT1/ CPI_HS_LES

PCI_GNT2/ CPI_HS_ENUM

PCI_RST

PCI_INTA

PCI_REQ2

DLLOUT

PCI_AD(0-31)

PCI_C(0–3)/BE(0-3)

PA[8–31]

PB[18–31]

PC[0–1,4–29]

PD[7–25, 29–31]

TDO

1

The default configuration of the CPM pins (PA[8–31], PB[18–31], PC[0–1,4–29], PD[7–25, 29–31]) is input. To prevent

excessive DC current, it is recommended either to pull unused pins to GND or VDDH, or to configure them as outputs.

TCK, TRST and PORESET have min VIH = 2.5V.

2

3

V

for IIC interface does not match IIC standard, but does meet IIC standard for V and should not cause any compatibility

IL

OL

issue.

4

The leakage current is measured for nominal VDDH,VCCSYN, and VDD.

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

11

DC Electrical Characteristics

5

MPC8272 and MPC8271 only.

Table 6.

Characteristic

Symbol

Min

Max

Unit

1

Input high voltage—all inputs except TCK, TRST and PORESET

Input low voltage

V

2.0

GND

2.4

GND

—

3.465

0.8

3.465

0.4

10

V

IH

V

IL

CLKIN input high voltage

V

IHC

CLKIN input low voltage

V

I

V

ILC

2

Input leakage current, V = VDDH

µA

V

IN

2

Hi-Z (off state) leakage current, V = VDDH

I

—

10

IN

OZ

3

Signal low input current, V = 0.8 V

I

—

1

IL

L

Signal high input current, V = 2.0 V

I

—

1

IH

H

Output high voltage, I = –2 mA

V

2.4

—

OH

except UTOPIA mode, and open drain pins

4

In UTOPIA mode (UTOPIA pins only): I = -8.0mA

OH

4

In UTOPIA mode (UTOPIA pins only): I = 8.0mA

V

—

0.5

0.4

V

OL

I

= 6.0mA

V

OL

BR

BG

ABB/IRQ2

TS

A[0-31]

TT[0-4]

TBST

TSIZE[0–3]

AACK

ARTRY

DBG

DBB/IRQ3

D[0-63]

//EXT_BR3

//EXT_BG3

/TBEN/EXT_DBG3/CINT

PSDVAL

TA

TEA

GBL/IRQ1

CI/BADDR29/IRQ2

WT/BADDR30/IRQ3

BADDR31/IRQ5/CINT

CPU_BR

IRQ0/NMI_OUT

/PCI_RST

HRESET

SRESET

RSTCONF

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

12

Freescale Semiconductor

DC Electrical Characteristics

Table 6.

Characteristic

Symbol

Min

Max

Unit

I

= 5.3mA

V

—

0.4

V

OL

CS[0-9]

CS(10)/BCTL1

CS(11)/AP(0)

BADDR[27–28]

ALE

BCTL0

PWE[0–7]/PSDDQM[0–7]/PBS[0–7]

PSDA10/PGPL0

PSDWE/PGPL1

POE/PSDRAS/PGPL2

PSDCAS/PGPL3

PGTA/PUPMWAIT/PGPL4/PPBS

PSDAMUX/PGPL5

LWE[0–3]LSDDQM[0–3]/LBS[0–3]/PCI_CFG[0–3]

LSDA10/LGPL0/PCI_MODCKH0

LSDWE/LGPL1/PCI_MODCKH1

LOE/LSDRAS/LGPL2/PCI_MODCKH2

LSDCAS/LGPL3/PCI_MODCKH3

LGTA/LUPMWAIT/LGPL4/LPBS

LSDAMUX/LGPL5/PCI_MODCK

LWR

MODCK[1–3]/AP[1–3]/TC[0–2]/BNKSEL[0–2]

I

= 3.2mA

OL

L_A14/PAR

L_A15/FRAME/SMI

L_A16/TRDY

L_A17/IRDY/CKSTP_OUT

L_A18/STOP

L_A19/DEVSEL

L_A20/IDSEL

L_A21/PERR

L_A22/SERR

L_A23/REQ0

L_A24/REQ1/HSEJSW

L_A25/GNT0

L_A26/GNT1/HSLED

L_A27/GNT2/HSENUM

L_A28/RST/CORE_SRESET

L_A29/INTAL_A30/REQ2

L_A31

LCL_D[0-31)]/AD[0-31]

LCL_DP[03]/C/BE[0-3]

PA[0–31]

PB[4–31]

PC[0–31]

PD[4–31]

TDO

QREQ

1

TCK, TRST and PORESET have min VIH = 2.5V.

The leakage current is measured for nominal VDDH,VCCSYN, and VDD.

2

3

V

for IIC interface does not match IIC standard, but does meet IIC standard for V and should not cause any compatibility

IL

OL

issue.

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

13

Thermal Characteristics

4

MPC8280, MPC8275VR, MPC8275ZQ only.

4 Thermal Characteristics

This table describes thermal characteristics. See Table 2 for information on a given SoC’s package.

Discussions of each characteristic are provided in Section 4.1, “Estimation with Junction-to-Ambient

Thermal Resistance,” through Section 4.7, “References.” For the these discussions, P = (V × I ) +

D

DD

PI/O, where PI/O is the power dissipation of the I/O drivers.

Table 7. Thermal Characteristics

Characteristic

Junction-to-ambient—

Symbol

Value

Unit

Air Flow

27

21

19

16

11

8

Natural convection

1

single-layer board

R

°C/W

θJA

1 m/s

Junction-to-ambient—

four-layer board

Natural convection

°C/W

1 m/s

—

2

Junction-to-board

R

°C/W

θJB

3

Junction-to-case

—

θJC

4

Junction-to-package top

R

2

—

θJT

1

2

Assumes no thermal vias

Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is

measured on the top surface of the board near the package.

Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883

Method 1012.1).

Thermal characterization parameter indicating the temperature difference between package top and the junction

temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is

written as Psi-JT.

3

4

4.1

Estimation with Junction-to-Ambient Thermal Resistance

An estimation of the chip junction temperature, T_J, in C can be obtained from the following equation:

T = T + (R × P )

J

A

θJA

D

where:

T = ambient temperature (ºC)

A

R

= package junction-to-ambient thermal resistance (ºC/W)

θJA

P = power dissipation in package

D

The junction-to-ambient thermal resistance is an industry standard value that provides a quick and easy

estimation of thermal performance. However, the answer is only an estimate; test cases have demonstrated

that errors of a factor of two (in the quantity T – T ) are possible.

J

A

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

14

Freescale Semiconductor

Thermal Characteristics

4.2

Estimation with Junction-to-Case Thermal Resistance

Historically, the thermal resistance has frequently been expressed as the sum of a junction-to-case thermal

resistance and a case-to-ambient thermal resistance:

R

= R

+ R

θJC θCA

θJA

where:

R

= junction-to-ambient thermal resistance (ºC/W)

= junction-to-case thermal resistance (ºC/W)

= case-to-ambient thermal resistance (ºC/W)

θJA

θJC

θCA

R

is device related and cannot be influenced by the user. The user adjusts the thermal environment to

θJC

affect the case-to-ambient thermal resistance, R

. For instance, the user can change the air flow around

θCA

the device, add a heat sink, change the mounting arrangement on the printed circuit board, or change the

thermal dissipation on the printed circuit board surrounding the device. This thermal model is most useful

for ceramic packages with heat sinks where some 90% of the heat flows through the case and the heat sink

to the ambient environment. For most packages, a better model is required.

4.3

Estimation with Junction-to-Board Thermal Resistance

A simple package thermal model which has demonstrated reasonable accuracy (about 20%) is a

two-resistor model consisting of a junction-to-board and a junction-to-case thermal resistance. The

junction-to-case thermal resistance covers the situation where a heat sink is used or where a substantial

amount of heat is dissipated from the top of the package. The junction-to-board thermal resistance

describes the thermal performance when most of the heat is conducted to the printed circuit board. It has

been observed that the thermal performance of most plastic packages, especially PBGA packages, is

strongly dependent on the board temperature.

If the board temperature is known, an estimate of the junction temperature in the environment can be made

using the following equation:

T = T + (R

× P )

D

J

B

θJB

where:

R

= junction-to-board thermal resistance (ºC/W)

θJB

T = board temperature (ºC)

B

P = power dissipation in package

D

If the board temperature is known and the heat loss from the package case to the air can be ignored,

acceptable predictions of junction temperature can be made. For this method to work, the board and board

mounting must be similar to the test board used to determine the junction-to-board thermal resistance,

namely a 2s2p (board with a power and a ground plane) and by attaching the thermal balls to the ground

plane.

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

15

Thermal Characteristics

4.4

Estimation Using Simulation

When the board temperature is not known, a thermal simulation of the application is needed. The simple

two-resistor model can be used with the thermal simulation of the application, or a more accurate and

complex model of the package can be used in the thermal simulation.

4.5

Experimental Determination

To determine the junction temperature of the device in the application after prototypes are available, the

thermal characterization parameter (Ψ ) can be used to determine the junction temperature with a

JT

measurement of the temperature at the top center of the package case using the following equation:

T = T + (Ψ × P )

J

T

JT

D

where:

Ψ = thermal characterization parameter

JT

T = thermocouple temperature on top of package

T

P = power dissipation in package

D

The thermal characterization parameter is measured per JEDEC JESD51-2 specification using a 40-gauge

type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned

so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the

thermocouple junction and over 1 mm of wire extending from the junction. The thermocouple wire is

placed flat against the case to avoid measurement errors caused by cooling effects of the thermocouple

wire.

4.6

Layout Practices

Each VDD and VDDH pin should be provided with a low-impedance path to the board’s power supplies.

Each ground pin should likewise be provided with a low-impedance path to ground. The power supply pins

drive distinct groups of logic on chip. The VDD and VDDH power supplies should be bypassed to ground

using bypass capacitors located as close as possible to the four sides of the package. For filtering high

frequency noise, a capacitor of 0.1uF on each VDD and VDDH pin is recommended. Further, for medium

frequency noise, a total of 2 capacitors of 47uF for VDD and 2 capacitors of 47uF for VDDH are also

recommended. The capacitor leads and associated printed circuit traces connecting to chip VDD, VDDH

and ground should be kept to less than half an inch per capacitor lead. Boards should employ separate inner

layers for power and GND planes.

All output pins on the SoC have fast rise and fall times. Printed circuit (PC) trace interconnection length

should be minimized to minimize overdamped conditions and reflections caused by these fast output

switching times. This recommendation particularly applies to the address and data buses. Maximum PC

trace lengths of six inches are recommended. Capacitance calculations should consider all device loads as

well as parasitic capacitances due to the PC traces. Attention to proper PCB layout and bypassing becomes

especially critical in systems with higher capacitive loads because these loads create higher transient

currents in the VDD and GND circuits. Pull up all unused inputs or signals that will be inputs during reset.

Special care should be taken to minimize the noise levels on the PLL supply pins.

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

16

Freescale Semiconductor

Power Dissipation

4.7

References

Semiconductor Equipment and Materials International(415) 964-5111

805 East Middlefield Rd.

Mountain View, CA 94043

MIL-SPEC and EIA/JESD (JEDEC) Specifications800-854-7179 or

(Available from Global Engineering Documents)303-397-7956

JEDEC Specifications

http://www.jedec.org

1. C.E. Triplett and B. Joiner, “An Experimental Characterization of a 272 PBGA Within an

Automotive Engine Controller Module,” Proceedings of SemiTherm, San Diego, 1998, pp. 47–54.

2. B. Joiner and V. Adams, “Measurement and Simulation of Junction to Board Thermal Resistance

and Its Application in Thermal Modeling,” Proceedings of SemiTherm, San Diego, 1999, pp.

212–220.

5 Power Dissipation

This table provides preliminary, estimated power dissipation for various configurations. Note that suitable

thermal management is required to ensure the junction temperature does not exceed the maximum

specified value. Also note that the I/O power should be included when determining whether to use a heat

sink. For a complete list of possible clock configurations, see Section 7, “Clock Configuration Modes.”

1

Table 8. Estimated Power Dissipation for Various Configurations

2,3

P

(W)

INT

CPM

Multiplication

Factor

CPU

Multiplication

Factor

Bus

(MHz)

CPM

(MHz)

CPU

(MHz)

Vddl 1.5 Volts

Nominal

Maximum

66.67

100

3

2

200

267

4

3

4

3

266

300

400

1

1.2

1.3

1.5

1.8

1.1

1.3

1.5

100

133

1

2

3

Test temperature = 105° C

= I x V Watts

Values do not include I/O. Add the following estimates for active I/O based on the following bus speeds:

66.7 MHz = 0.35 W (nominal), 0.4 W (maximum)

P

INT

DD

83.3 MHz = 0.4 W (nominal), 0.5 W (maximum)

100 MHz = 0.5 W (nominal), 0.6 W (maximum)

133 MHz = 0.7 W (nominal), 0.8 W (maximum)

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

17

AC Electrical Characteristics

6 AC Electrical Characteristics

The following sections include illustrations and tables of clock diagrams, signals, and CPM outputs and

inputs for 66.67/83.33/100/133 MHz devices. Note that AC timings are based on a 50-pf load for MAX

Delay and 10-pf load for MIN delay. Typical output buffer impedances are shown in this table.

1

Table 9. Output Buffer Impedances

Output Buffers

Typical Impedance (Ω)

2

60x bus

Memory controller

Parallel I/O

PCI

45 or 27

2

45 or 27

45

27

1

2

These are typical values at 65° C. Impedance may vary by 25% with

process and temperature.

Impedance value is selected through SIUMCR[20,21]. See the SoC

reference manual.

6.1

CPM AC Characteristics

This table lists CPM output characteristics.

1

Table 10. AC Characteristics for CPM Outputs

Spec Number

Value (ns)

66

Maximum Delay

Minimum Delay

83 100 133

Characteristic

Max

Min

66

83

100 133

MHz MHz MHz MHz MHz MHz MHz MHz

sp36a sp37a FCC outputs—internal clock (NMSI)

sp36b sp37b FCC outputs—external clock (NMSI)

sp38a sp39a SCC/SMC/SPI/I2C outputs—internal clock (NMSI)

sp38b sp39b SCC/SMC/SPI/I2C outputs—external clock (NMSI)

sp40 sp41 TDM outputs/SI

6

8

5.5

8

5.5

8

5.5

8

0.5

2

0.5

2

0.5

2

0.5

2

10

8

10

8

10

8

10

8

0

2

11

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

sp42 sp43 TIMER/IDMA outputs

sp42a sp43a PIO outputs

1

Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are

measured at the pin.

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

18

Freescale Semiconductor

AC Electrical Characteristics

This table lists CPM input characteristics.

NOTE: Rise/Fall Time on CPM Input Pins

It is recommended that the rise/fall time on CPM input pins should not

exceed 5 ns. This should be enforced especially on clock signals. Rise time

refers to signal transitions from 10% to 90% of VCC; fall time refers to

transitions from 90% to 10% of VCC.

1

Table 11. AC Characteristics for CPM Inputs

Spec Number

Setup Hold

Value (ns)

Setup

Hold

Characteristic

66

83

100 133

66

83

100 133

MHz MHz MHz MHz MHz MHz MHz MHz

sp16a sp17a FCC inputs—internal clock (NMSI)

sp16b sp17b FCC inputs—external clock (NMSI)

sp18a sp19a SCC/SMC/SPI/I2C inputs—internal clock (NMSI)

sp18b sp19b SCC/SMC/SPI/I2C inputs—external clock (NMSI)

sp20 sp21 TDM inputs/SI

6

2.5

6

2.5

6

2.5

6

2.5

6

0

2

0

2

0

2

0

2

0

4

2

3

2.5

0.5

2.5

0.5

2.5

0.5

2.5

0.5

sp22 sp23 PIO/TIMER/IDMA inputs

8

1

Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are

measured at the pin.

NOTE

Although the specifications generally reference the rising edge of the clock,

the following AC timing diagrams also apply when the falling edge is the

active edge.

This figure shows the FCC internal clock.

BRG_OUT

sp17a

sp16a

FCC input signals

sp36a/sp37a

FCC output signals

Note: When GFMR[TCI] = 0

sp36a/sp37a

FCC output signals

Note: When GFMR.[TCI] = 1

Figure 3. FCC Internal Clock Diagram

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

19

AC Electrical Characteristics

This figure shows the FCC external clock.

Serial ClKin

sp17b

sp16b

FCC input signals

sp36b/sp37b

FCC output signals

Note: When GFMR[TCI] = 0

sp36b/sp37b

FCC output signals

Note: When GFMR[TCI] = 1

Figure 4. FCC External Clock Diagram

2

This figure shows the SCC/SMC/SPI/I C external clock.

Serial CLKin

new CLKin

sp19b

sp18b

SCC/SMC/SPI/I2C input signals

(See note)

sp38b/sp39b

SCC/SMC/SPI/I2C output signals

(See note)

Note: There are four possible timing conditions for SPI:

1. Input sampled on the rising edge and output driven on the rising edge.

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge (shown).

4. Input sampled on the falling edge and output driven on the rising edge.

2

Note: There are two possible timing conditions for SCC/SMC/I C:

1. Input sampled on the falling edge and output driven on the falling edge (shown).

2. Input sampled on the falling edge and output driven on the rising edge.

2

Figure 5. SCC/SMC/SPI/I C External Clock Diagram

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

20

Freescale Semiconductor

AC Electrical Characteristics

2

This figure shows the SCC/SMC/SPI/I C internal clock.

BRG_OUT

sp19a

sp18a

SCC/SMC/SPI/I2C input signals

(See note)

sp38a/sp39a

SCC/SMC/SPI/I2C output signals

(See note)

Note: There are four possible timing conditions for SCC and SPI:

1. Input sampled on the rising edge and output driven on the rising edge (shown).

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge.

4. Input sampled on the falling edge and output driven on the rising edge.

2

Figure 6. SCC/SMC/SPI/I C Internal Clock Diagram

This figure shows TDM input and output signals.

Serial CLKin

sp20

sp21

TDM input signals

sp40/sp41

TDM output signals

Note: There are four possible TDM timing conditions:

1. Input sampled on the rising edge and output driven on the rising edge (shown).

2. Input sampled on the rising edge and output driven on the falling edge.

3. Input sampled on the falling edge and output driven on the falling edge.

4. Input sampled on the falling edge and output driven on the rising edge.

Figure 7. TDM Signal Diagram

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

21

AC Electrical Characteristics

This figure shows PIO and timer signals.

Sys clk

sp23

sp22

PIO/IDMA/TIMER[TGATE assertion] input signals

(See note)

sp23

sp22

TIMER input signal [TGATE deassertion]

(See note)

sp42/sp43

IDMA output signals

sp42/sp43

sp42a/sp43a

TIMER(sp42/43)/ PIO(sp42a/sp43a)

output signals

Note: TGATE is asserted on the rising edge of the clock; it is deasserted on the falling edge.

Figure 8. PIO and Timer Signal Diagram

6.2

SIU AC Characteristics

This table lists SIU input characteristics.

NOTE: CLKIN Jitter and Duty Cycle

The CLKIN input to the SoC should not exceed +/– 150 psec of jitter

(peak-to-peak). This represents total input jitter—the combination of short

term (peak-to-peak) and long term (cumulative). The duty cycle of CLKIN

should not exceed the ratio of 40:60.

NOTE: Spread Spectrum Clocking

Spread spectrum clocking is allowed with 1% input frequency down-spread

at maximum 60 KHz modulation rate regardless of input frequency.

NOTE: PCI AC Timing

The SoC meets the timing requirements of PCI Specification Revision 2.2.

See Section 7, “Clock Configuration Modes,” and “Note: Tval (Output

Hold)” to determine if a specific clock configuration is compliant.

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

22

Freescale Semiconductor

AC Electrical Characteristics

NOTE: Conditions

The following conditions must be met in order to operate the MPC8272

family devices with 133 MHz bus: single PowerQUICC II Bus mode must

be used (no external master, BCR[EBM] = 0); data bus must be in Pipeline

mode (BRx[DR] = 1); internal arbiter and memory controller must be used.

For expected load of above 40 pF, it is recommended that data and address

buses be configured to low (25 Ω) impedance (SIUMCR[HLBE0] = 1,

SIUMCR[HLBE1] = 1).

1

Table 12. AC Characteristics for SIU Inputs

Spec Number

Setup Hold

Value (ns)

Setup

Hold

Characteristic

66

83

100

133

66

83

100

133

MHz MHz MHz MHz MHz MHz MHz MHz

sp11 sp10 AACK/TA/TS/DBG/BG/BR/ARTRY/TEA

sp12 sp10 Data bus in normal mode

6

5

4

3.5

2.5

N/A

1.5

0.5

N/A

0.5

sp13 sp10 Data bus in pipeline mode (without ECC and

PARITY)

N/A

sp15 sp10 All other pins

5

4

3.5

N/A

0.5

N/A

1

Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are

measured at the pin.

This table lists SIU output characteristics.

1

Table 13. AC Characteristics for SIU Outputs

Spec Number

Value (ns)

Maximum Delay

Minimum Delay

Characteristic

Max

Min

66

83

100

133

66

83

100

133

MHz MHz MHz MHz MHz MHz MHz MHz

sp31 sp30 PSDVAL/TEA/TA

7

8

6

5.5

N/A

1

N/A

2

sp32 sp30 ADD/ADD_atr./BADDR/CI/GBL/WT

6.5

5.5

4.5

1

3

sp33 sp30 Data bus

6.5

6

4.5

N/A

0.8

1

0.8

1

0.8

1

sp34 sp30 Memory controller signals/ALE

sp35 sp30 All other signals

6

1

N/A

1

Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are

measured at the pin.

Value is for ADD only; other sp32/sp30 signals are not applicable.

2

3

To achieve 1 ns of hold time at 66.67/83.33/100 MHZ, a minimum loading of 20 pF is required.

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

23

AC Electrical Characteristics

NOTE

Activating data pipelining (setting BRx[DR] in the memory controller)

improves the AC timing.

This figure shows the interaction of several bus signals.

CLKin

sp10

sp11

sp11a

sp12

AACK/TA/TS/

DBG/BG/BR input signals

ARTRY/TEA input signals

DATA bus normal mode

input signal

sp10

sp15

All other input signals

sp30

sp31

sp32

PSDVAL/TEA/TA output signals

sp30

ADD/ADD_atr/BADDR/CI/

GBL/WT output signals

sp33

sp35

DATA bus output signals

All other output signals

(except AP)

sp10

sp13

DATA bus pipeline mode

input signal

Figure 9. Bus Signals

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

24

Freescale Semiconductor

AC Electrical Characteristics

This figure shows signal behavior in MEMC mode.

CLKin

V_CLK

sp34/sp30

Memory controller signals

Figure 10. MEMC Mode Diagram

NOTE

Generally, all SoC bus and system output signals are driven from the rising

edge of the input clock (CLKin). Memory controller signals, however,

trigger on four points within a CLKin cycle. Each cycle is divided by four

internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge, and

T3 at the falling edge, of CLKin. However, the spacing of T2 and T4

depends on the PLL clock ratio selected, as shown in Table 14.

Table 14. Tick Spacing for Memory Controller Signals

Tick Spacing (T1 Occurs at the Rising Edge of CLKin)

PLL Clock Ratio

T2

T3

T4

1:2, 1:3, 1:4, 1:5, 1:6

1/4 CLKin

1/2 CLKin

3/4 CLKin

1:2.5

1:3.5

3/10 CLKin

4/14 CLKin

1/2 CLKin

8/10 CLKin

11/14 CLKin

This table is a representation of the information in Table 14.

CLKin

for 1:2, 1:3, 1:4, 1:5, 1:6

T1

T2

T3

T4

CLKin

for 1:2.5

T2

T4

for 1:3.5

T2

T4

Figure 11. Internal Tick Spacing for Memory Controller Signals

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

25

AC Electrical Characteristics

NOTE

The UPM machine outputs change on the internal tick determined by the

memory controller programming; the AC specifications are relative to the

internal tick. Note that SDRAM and GPCM machine outputs change on

CLKin’s rising edge.

6.3

JTAG Timings

This table lists the JTAG timings.

1

Table 15. JTAG Timings

2

Parameter

Symbol

Min

Max

Unit

Notes

JTAG external clock frequency of operation

JTAG external clock cycle time

f

t

0

30

15

0

33.3

—

MHz

ns

—

JTG

JTAG external clock pulse width measured at 1.4V

JTAG external clock rise and fall times

t

—

ns

—

JTKHKL

6

t

and

5

ns

JTGR

t

JTGF

3

6

TRST assert time

Input setup times

t

25

—

ns

,

TRST

4

7

Boundary-scan data

t

4

—

ns

,

JTDVKH

TMS, TDI

JTIVKH

Input hold times

Output valid times

Output hold times

4

7

Boundary-scan data

TMS, TDI

t

10

—

ns

,

JTDXKH

JTIXKH

5

7

Boundary-scan data

TDO

t

—

10

ns

,

.

JTKLDV

JTKLOV

5

7

Boundary-scan data

TDO

t

1

—

ns

,

JTKLDX

JTKLOX

JTAG external clock to output high impedance

Boundary-scan data

TDO

5

6

t

1

10

ns

,

JTKLDZ

JTKLOZ

1

All outputs are measured from the midpoint voltage of the falling/rising edge of t

to the midpoint of the signal in question.

TCLK

The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load. Time-of-flight delays

must be added for trace lengths, vias, and connectors in the system.

The symbols used for timing specifications herein follow the pattern of t

2

(first two letters of functional block)(signal)(state) (reference)(state)

for inputs and t(

for outputs. For example, t

symbolizes JTAG

(first two letters of functional block)(reference)(state)(signal)(state)

JTDVKH

device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to the t

clock reference

JTG

(K) going to the high (H) state or setup time. Also, t

symbolizes JTAG timing (JT) with respect to the time data input

JTDXKH

signals (D) went invalid (X) relative to the t

clock reference (K) going to the high (H) state. Note that, in general, the clock

JTG

reference symbol representation is based on three letters representing the clock of a particular functional. For rise and fall

times, the latter convention is used with the appropriate letter: R (rise) or F (fall).

TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.

3

4

5

6

7

Non-JTAG signal input timing with respect to t

.

TCLK

Non-JTAG signal output timing with respect to t

Guaranteed by design.

.

TCLK

Guaranteed by design and device characterization.

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

26

Freescale Semiconductor

Clock Configuration Modes

7 Clock Configuration Modes

As shown in this table, the clocking mode is set according to two sources:

•

PCI_CFG[0]— An input signal. Also defined as “PCI_HOST_EN.” See Chapter 6, “External

Signals,” and Chapter 9, “PCI Bridge,” in the SoC reference manual.

PCI_MODCK—Bit 27 in the Hard Reset Configuration Word. See Chapter 5, “Reset,” in the SoC

reference manual.

Table 16. SoC Clocking Modes

Pins

Clocking Mode PCI Clock Frequency Range (MHz)

Reference

1

2

PCI_CFG[0]

PCI_MODCK

0

1

0

1

0

1

PCI host

50–66

25–50

50–66

25–50

Table 17

Table 18

Table 19

Table 20

PCI agent

1

PCI_HOST_EN

Determines PCI clock frequency range.

2

Within each mode, the configuration of bus, core, PCI, and CPM frequencies is determined by seven bits

during the power-on reset—three hardware configuration pins (MODCK[1–3]) and four bits from

hardware configuration word[28–31] (MODCK_H). Both the PLLs and the dividers are set according to

the selected clock operation mode as described in the following sections.

NOTE

Clock configurations change only after PORESET is asserted.

NOTE: Tval (Output Hold)

The minimum Tval = 2 ns when PCI_MODCK = 1, and the minimum

Tval = 1 ns when PCI_MODCK = 0. Therefore, designers should use clock

configurations that fit this condition to achieve PCI-compliant AC timing.

7.1

PCI Host Mode

These tables show configurations for PCI host mode. The frequency values listed are for the purpose of

illustration only. Users must select a mode and input bus frequency so that the resulting configuration does

not exceed the frequency rating of the user’s device. Note that in PCI host mode the input clock is the bus

clock.

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

27

Clock Configuration Modes

1,2

Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=0)

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

3

Mode

CPM

CPU

PCI

Multiplication

Division

Factor

4

5

6

MODCK_H-

MODCK[1-3]

Factor

Low High

Default Modes (MODCK_H=0000)

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

0000_110

0000_111

60.0 66.7

50.0 66.7

60.0 80.0

50.0 66.7

2

120.0 133.3

100.0 133.3

150.0 200.0

2.5

3

150.0 166.7

150.0 200.0

180.0 240.0

210.0 280.0

240.0 320.0

150.0 200.0

175.0 233.3

200.0 266.6

2

3

60.0 66.7

50.0 66.7

2.5

3

3.5

4

3

3.5

3

3.5

4

Full Configuration Modes

0001_000

0001_001

0001_010

0001_011

50.0 66.7

3

150.0 200.0

5

6

7

8

250.0 333.3

300.0 400.0

350.0 466.6

400.0 533.3

3

50.0 66.7

0010_000

0010_001

0010_010

0010_011

50.0 66.7

4

200.0 266.6

5

6

7

8

250.0 333.3

300.0 400.0

350.0 466.6

400.0 533.3

4

50.0 66.7

0010_100

0010_101

0010_110

75.0 100.0

4

300.0 400.0

5

5.5

6

375.0 500.0

412.5 549.9

450.0 599.9

6

50.0 66.7

0011_000

0011_001

0011_010

0011_011

50.0 66.7

5

250.0 333.3

5

6

7

8

250.0 333.3

300.0 400.0

350.0 466.6

400.0 533.3

5

50.0 66.7

0100_000

Reserved

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

28

Freescale Semiconductor

Clock Configuration Modes

1,2

Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=0) (continued)

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

3

Mode

CPM

CPU

PCI

Multiplication

Division

Factor

4

5

6

MODCK_H-

MODCK[1-3]

Factor

Low High

0100_001

0100_010

0100_011

50.0 66.7

6

300.0 400.0

6

7

8

300.0 400.0

350.0 466.6

400.0 533.3

6

50.0 66.7

0101_000

0101_001

0101_010

0101_011

0101_100

60.0 66.7

50.0 66.7

2

120.0 133.3

100.0 133.3

2.5

3

150.0 166.7

150.0 200.0

175.0 233.3

200.0 266.6

225.0 300.0

2

60.0 66.7

50.0 66.7

3.5

4

4.5

0101_101

0101_110

0101_111

83.3 111.1

3

250.0 333.3

3.5

4

291.7 388.9

333.3 444.4

375.0 500.0

5

50.0 66.7

4.5

0110_000

0110_001

0110_010

0110_011

0110_100

0110_101

0110_110

60.0 80.0

2.5

150.0 200.0

2.5

3

150.0 200.0

180.0 240.0

210.0 280.0

240.0 320.0

270.0 360.0

300.0 400.0

360.0 480.0

3

50.0 66.7

3.5

4

4.5

5

6

0111_000

0111_001

0111_010

0111_011

0111_100

Reserved

50.0 66.7

3

150.0 200.0

3

3.5

4

150.0 200.0

175.0 233.3

200.0 266.6

225.0 300.0

3

50.0 66.7

4.5

1000_000

1000_001

Reserved

3

66.7 88.9

3

200.0 266.6

4

50.0 66.7

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

29

Clock Configuration Modes

1,2

Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=0) (continued)

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

3

Mode

CPM

CPU

PCI

Multiplication

Division

Factor

4

5

6

MODCK_H-

MODCK[1-3]

Factor

Low High

1000_010

1000_011

1000_100

1000_101

1000_110

66.7 88.9

3

200.0 266.6

3.5

4

233.3 311.1

266.7 355.5

300.0 400.0

400.0 533.3

433.3 577.7

4

50.0 66.7

4.5

6

6.5

1001_000

1001_001

1001_010

1001_011

1001_100

Reserved

57.1 76.2

3.5

200.0 266.6

3.5

4

200.0 266.6

228.6 304.7

257.1 342.8

4

50.0 66.7

4.5

1001_101

1001_110

1001_111

85.7 114.3

3.5

300.0 400.0

5

5.5

6

428.6 571.4

471.4 628.5

514.3 685.6

6

50.0 66.7

1010_000

1010_001

1010_010

1010_011

1010_100

75.0 100.0

2

150.0 200.0

2

2.5

3

150.0 200.0

187.5 250.0

225.0 300.0

262.5 350.0

300.0 400.0

3

50.0 66.7

3.5

4

1010_101

1010_110

1010_111

100.0 133.3

2

200.0 266.6

2.5

3

250.0 333.3

300.0 400.0

350.0 466.6

4

50.0 66.7

3.5

1011_000

1011_001

1011_010

1011_011

Reserved

80.0 106.7

2.5

200.0 266.6

2.5

3

200.0 266.6

240.0 320.0

280.0 373.3

4

50.0 66.7

3.5

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

30

Freescale Semiconductor

Clock Configuration Modes

1,2

Table 17. Clock Configurations for PCI Host Mode (PCI_MODCK=0) (continued)

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

3

Mode

CPM

CPU

PCI

Multiplication

Division

Factor

4

5

6

MODCK_H-

MODCK[1-3]

Factor

Low High

1011_100

1011_101

80.0 106.7

2.5

200.0 266.6

4

320.0 426.6

360.0 480.0

4

50.0 66.7

4.5

1101_000

1101_001

1101_010

1101_011

1101_100

100.0 133.3

2.5

250.0 333.3

3

3.5

4

300.0 400.0

350.0 466.6

400.0 533.3

450.0 599.9

500.0 666.6

5

50.0 66.7

4.5

5

1101_101

1101_110

125.0 166.7

2

250.0 333.3

3

4

375.0 500.0

500.0 666.6

5

50.0 66.7

1110_000

1110_001

1110_010

1110_011

1110_100

100.0 133.3

3

300.0 400.0

3.5

4

350.0 466.6

400.0 533.3

450.0 599.9

500.0 666.6

550.0 733.3

6

50.0 66.7

4.5

5

5.5

1100_000

1100_001

1100_010

Reserved

1

The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a

table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of

illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed

the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial temperature

devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz.

PCI_MODCK determines the PCI clock frequency range. SeeTable 18 for lower range configurations.

MODCK_H = hard reset configuration word [28–31] (see Section 5.4 in the SoC reference manual). MODCK[1-3] =

three hardware configuration pins.

CPM multiplication factor = CPM clock/bus clock

CPU multiplication factor = Core PLL multiplication factor

CPM_CLK/PCI_CLK ratio. When PCI_MODCK = 0, the ratio of CPM_CLK/PCI_CLK should be calculated from

SCCR[PCIDF] as follows:

2

3

4

5

6

CPM_CLK/PCI_CLK = (PCIDF + 1) / 2.

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

31

Clock Configuration Modes

1,2

Table 18. Clock Configurations for PCI Host Mode (PCI_MODCK=1)

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

3

Mode

CPM

CPU

PCI

Multiplication

Division

Factor

4

5

6

MODCK_H-

MODCK[1-3]

Factor

Low High

Default Modes (MODCK_H=0000)

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

0000_110

0000_111

60.0 100.0

50.0 100.0

60.0 120.0

50.0 100.0

2

120.0 200.0

100.0 200.0

150.0 300.0

2.5

3

150.0 250.0

150.0 300.0

180.0 360.0

210.0 420.0

240.0 480.0

150.0 300.0

175.0 350.0

200.0 400.0

4

6

30.0 50.0

25.0 50.0

2.5

3

3.5

4

3

3.5

4

3

Full Configuration Modes

0001_000

0001_001

0001_010

0001_011

50.0 100.0

3

150.0 300.0

5

6

7

8

250.0 500.0

300.0 600.0

350.0 700.0

400.0 800.0

6

25.0 50.0

0010_000

0010_001

0010_010

0010_011

50.0 100.0

4

200.0 400.0

5

6

7

8

250.0 500.0

300.0 600.0

350.0 700.0

400.0 800.0

8

25.0 50.0

0010_100

0010_101

0010_110

37.5 75.0

4

150.0 300.0

5

5.5

6

187.5 375.0

206.3 412.5

225.0 450.0

6

25.0 50.0

0011_000

0011_001

0011_010

0011_011

30.0 50.0

25.0 50.0

5

150.0 250.0

125.0 250.0

5

6

7

8

150.0 250.0

150.0 300.0

175.0 350.0

200.0 400.0

5

30.0 50.0

25.0 50.0

0100_000

Reserved

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

32

Freescale Semiconductor

Clock Configuration Modes

1,2

Table 18. Clock Configurations for PCI Host Mode (PCI_MODCK=1) (continued)

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

3

Mode

CPM

CPU

PCI

Multiplication

Division

Factor

4

5

6

MODCK_H-

MODCK[1-3]

Factor

Low High

0100_001

0100_010

0100_011

25.0 50.0

6

150.0 300.0

6

7

8

150.0 300.0

175.0 350.0

200.0 400.0

6

25.0 50.0

0101_000

0101_001

0101_010

0101_011

0101_100

60.0 100.0

50.0 100.0

2

120.0 200.0

100.0 200.0

2.5

3

150.0 250.0

150.0 300.0

175.0 350.0

200.0 400.0

225.0 450.0

4

30.0 50.0

25.0 50.0

3.5

4

4.5

0101_101

0101_110

0101_111

42.9 83.3

41.7 83.3

3

128.6 250.0

125.0 250.0

3.5

4

150.0 291.7

166.7 333.3

187.5 375.0

5

25.7 50.0

25.0 50.0

4.5

0110_000

0110_001

0110_010

0110_011

0110_100

0110_101

0110_110

60.0 120.0

2.5

150.0 300.0

2.5

3

150.0 300.0

180.0 360.0

210.0 420.0

240.0 480.0

270.0 540.0

300.0 600.0

360.0 720.0

6

25.0 50.0

3.5

4

4.5

5

6

0111_000

0111_001

0111_010

0111_011

0111_100

Reserved

50.0 100.0

3

150.0 300.0

3

3.5

4

150.0 300.0

175.0 350.0

200.0 400.0

225.0 450.0

6

25.0 50.0

4.5

1000_000

1000_001

Reserved

3

66.7 133.3

3

200.0 400.0

8

25.0 50.0

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

33

Clock Configuration Modes

1,2

Table 18. Clock Configurations for PCI Host Mode (PCI_MODCK=1) (continued)

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

3

Mode

CPM

CPU

PCI

Multiplication

Division

Factor

4

5

6

MODCK_H-

MODCK[1-3]

Factor

Low High

1000_010

1000_011

1000_100

1000_101

1000_110

66.7 133.3

3

200.0 400.0

3.5

4

233.3 466.7

266.7 533.3

300.0 600.0

400.0 800.0

433.3 866.7

8

25.0 50.0

4.5

6

6.5

1001_000

1001_001

1001_010

1001_011

1001_100

1001_101

1001_110

1001_111

Reserved

57.1 114.3

42.9 85.7

3.5

200.0 400.0

150.0 300.0

3.5

4

200.0 400.0

228.6 457.1

257.1 514.3

214.3 428.6

235.7 471.4

257.1 514.3

8

6

25.0 50.0

4.5

5

5.5

6

1010_000

1010_001

1010_010

1010_011

1010_100

75.0 150.0

2

150.0 300.0

2

2.5

3

150.0 300.0

187.5 375.0

225.0 450.0

262.5 525.0

300.0 600.0

6

25.0 50.0

3.5

4

1010_101

1010_110

1010_111

100.0 200.0

2

200.0 400.0

2.5

3

250.0 500.0

300.0 600.0

350.0 700.0

8

25.0 50.0

3.5

1011_000

1011_001

1011_010

1011_011

1011_100

Reserved

80.0 160.0

2.5

200.0 400.0

2.5

3

200.0 400.0

240.0 480.0

280.0 560.0

320.0 640.0

8

25.0 50.0

3.5

4

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

34

Freescale Semiconductor

Clock Configuration Modes

1,2

Table 18. Clock Configurations for PCI Host Mode (PCI_MODCK=1) (continued)

Bus Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

PCI Clock

(MHz)

3

Mode

CPM

CPU

PCI

Multiplication

Division

Factor

4

5

6

MODCK_H-

MODCK[1-3]

Factor

Low High

1011_101

80.0 160.0

2.5

200.0 400.0

4.5

360.0 720.0

8

25.0 50.0

1101_000

1101_001

1101_010

1101_011

1101_100

50.0 100.0

2.5

125.0 250.0

3

3.5

4

150.0 300.0

175.0 350.0

200.0 400.0

225.0 450.0

250.0 500.0

5

25.0 50.0

4.5

5

1101_101

1101_110

62.5 125.0

2

125.0 250.0

3

4

187.5 375.0

250.0 500.0

5

25.0 50.0

1110_000

1110_001

1110_010

1110_011

1110_100

50.0 100.0

3

150.0 300.0

3.5

4

175.0 350.0

200.0 400.0

225.0 450.0

250.0 500.0

275.0 550.0

6

25.0 50.0

4.5

5

5.5

1100_000

1100_001

1100_010

Reserved

1

The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a

table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of

illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed

the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial temperature

devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz.

PCI_MODCK determines the PCI clock frequency range. See Table 17 for higher range configurations.

MODCK_H = hard reset configuration word [28–31] (see Section 5.4 in the SoC reference manual). MODCK[1-3] =

three hardware configuration pins.

2

3

4

5

CPM multiplication factor = CPM clock/bus clock

CPU multiplication factor = Core PLL multiplication factor

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

35

Clock Configuration Modes

6

CPM_CLK/PCI_CLK ratio. When PCI_MODCK = 1, the ratio of CPM_CLK/PCI_CLK should be calculated from

PCIDF as follows:

PCIDF = 3 > CPM_CLK/PCI_CLK = 4

PCIDF = 5 > CPM_CLK/PCI_CLK = 6

PCIDF = 7 > CPM_CLK/PCI_CLK = 8

PCIDF = 9 > CPM_CLK/PCI_CLK = 5

PCIDF = B > CPM_CLK/PCI_CLK = 6

7.2

PCI Agent Mode

These tables show configurations for PCI agent mode. The frequency values listed are for the purpose of

illustration only. Users must select a mode and input bus frequency so that the resulting configuration does

not exceed the frequency rating of the user’s device. Note that in PCI agent mode the input clock is PCI

clock.

1,2

Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=0)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

CPU

Bus

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

Default Modes (MODCK_H=0000)

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

0000_110

0000_111

60.0 66.7

50.0 66.7

2

3

4

120.0 133.3

100.0 133.3

150.0 200.0

200.0 266.6

2.5

3

150.0 166.7

150.0 200.0

200.0 266.6

180.0 240.0

210.0 280.0

233.3 311.1

240.0 320.0

2

60.0 66.7

50.0 66.7

60.0 80.0

66.7 88.9

80.0 106.7

3

4

3

2.5

3

3.5

3

2.5

Full Configuration Modes

0001_001

0001_010

0001_011

0001_100

60.0 66.7

50.0 66.7

2

120.0 133.3

100.0 133.3

5

6

7

8

150.0 166.7

150.0 200.0

175.0 233.3

200.0 266.6

4

30.0 33.3

25.0 33.3

0010_001

0010_010

0010_011

0010_100

50.0 66.7

3

150.0 200.0

3

3.5

4

180.0 240.0

210.0 280.0

240.0 320.0

270.0 360.0

2.5

60.0 80.0

4.5

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

36

Freescale Semiconductor

Clock Configuration Modes

1,2

Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) (continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

CPU

Bus

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

0011_000

0011_001

0011_010

0011_011

0011_100

Reserved

0100_000

0100_001

0100_010

0100_011

0100_100

Reserved

50.0 66.7

3

150.0 200.0

3

3.5

4

150.0 200.0

175.0 200.0

200.0 266.6

225.0 300.0

3

50.0 66.7

4.5

0101_000

0101_001

0101_010

0101_011

0101_100

0101_101

0101_110

50.0 66.7

5

250.0 333.3

2.5

3

250.0 333.3

300.0 400.0

350.0 466.6

400.0 533.3

450.0 599.9

500.0 666.6

550.0 733.3

2.5

100.0 133.3

3.5

4

4.5

5

5.5

0110_000

0110_001

0110_010

0110_011

0110_100

Reserved

50.0 66.7

4

200.0 266.6

3

3.5

4

200.0 266.6

233.3 311.1

266.7 355.5

300.0 400.0

3

66.7 88.9

4.5

0111_000

0111_001

0111_010

0111_011

50.0 66.7

3

150.0 200.0

2

2.5

3

150.0 200.0

187.5 250.0

225.0 300.0

262.5 350.0

2

75.0 100.0

3.5

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

37

Clock Configuration Modes

1,2

Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) (continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

CPU

Bus

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

Reserved

50.0 66.7

3

150.0 200.0

2.5

3

150.0 166.7

180.0 240.0

210.0 280.0

240.0 320.0

270.0 360.0

2.5

60.0 80.0

3.5

4

4.5

1001_000

1001_001

1001_010

1001_011

1001_100

Reserved

4

50.0 66.7

4

200.0 266.6

225.0 300.0

4

50.0 66.7

4.5

1010_000

1010_001

1010_010

1010_011

1010_100

Reserved

50.0 66.7

4

200.0 266.6

3

3.5

4

200.0 266.6

233.3 311.1

266.7 355.5

300.0 400.0

3

66.7 88.9

4.5

1011_000

1011_001

1011_010

1011_011

1011_100

Reserved

50.0 66.7

4

200.0 266.6

2.5

3

200.0 266.6

240.0 320.0

280.0 373.3

320.0 426.6

2.5

80.0 106.7

3.5

4

1011_101

1011_110

1011_111

50.0 66.7

4

200.0 266.6

2.5

3

250.0 333.3

300.0 400.0

350.0 466.6

2

100.0 133.3

3.5

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

38

Freescale Semiconductor

Clock Configuration Modes

1,2

Table 19. Clock Configurations for PCI Agent Mode (PCI_MODCK=0) (continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

CPU

Bus

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

1100_101

1100_110

1100_111

1101_000

50.0 66.7

6

300.0 400.0

4

4.5

5

400.0 533.3

450.0 599.9

500.0 666.6

550.0 733.3

3

100.0 133.3

5.5

1101_001

1101_010

1101_011

1101_100

50.0 66.7

6

300.0 400.0

3.5

4

420.0 559.9

480.0 639.9

540.0 719.9

600.0 799.9

2.5

120.0 160.0

4.5

5

1110_000

1110_001

1110_010

1110_011

50.0 66.7

5

250.0 333.3

2.5

3

312.5 416.6

375.0 500.0

437.5 583.3

500.0 666.6

2

125.0 166.7

3.5

4

1110_100

1110_101

1110_110

1110_111

50.0 66.7

5

250.0 333.3

4

4.5

5

333.3 444.4

375.0 500.0

416.7 555.5

458.3 611.1

3

83.3 111.1

5.5

1100_000

1100_001

1100_010

Reserved

1

The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a

table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of

illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed

the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial temperature

devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz.

PCI_MODCK determines the PCI clock frequency range. See Table 20 for lower range configurations.

MODCK_H = hard reset configuration word [28–31] (see Section 5.4 in the SoC reference manual). MODCK[1-3] =

three hardware configuration pins.

2

3

4

5

CPM multiplication factor = CPM clock/bus clock

CPU multiplication factor = Core PLL multiplication factor

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

39

Clock Configuration Modes

1,2

Table 20. Clock Configurations for PCI Agent Mode (PCI_MODCK=1)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

CPU

Bus

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

Default Modes (MODCK_H=0000)

0000_000

0000_001

0000_010

0000_011

0000_100

0000_101

0000_110

0000_111

30.0 50.0

25.0 50.0

4

6

8

120.0 200.0

100.0 200.0

150.0 300.0

200.0 400.0

2.5

3

150.0 250.0

150.0 300.0

200.0 400.0

180.0 360.0

210.0 420.0

233.3 466.7

240.0 480.0

2

60.0 100.0

50.0 100.0

60.0 120.0

66.7 133.3

80.0 160.0

3

4

3

2.5

3

3.5

3

2.5

Full Configuration Modes

0001_001

0001_010

0001_011

0001_100

30.0 50.0

25.0 50.0

4

120.0 200.0

100.0 200.0

5

6

7

8

150.0 250.0

150.0 300.0

175.0 350.0

200.0 400.0

4

30.0 50.0

25.0 50.0

0010_001

0010_010

0010_011

0010_100

25.0 50.0

6

150.0 300.0

3

3.5

4

180.0 360.0

210.0 420.0

240.0 480.0

270.0 540.0

2.5

60.0 120.0

4.5

0011_000

0011_001

0011_010

0011_011

0011_100

Reserved

37.5 50.0

32.1 50.0

28.1 50.0

25.0 50.0

4

150.0 200.0

128.6 200.0

112.5 200.0

100.0 200.0

3

3.5

4

150.0 200.0

150.0 233.3

150.0 266.7

150.0 300.0

3

50.0 66.7

42.9 66.7

37.5 66.7

33.3 66.7

4.5

0100_000

0100_001

0100_010

0100_011

Reserved

25.0 50.0

6

150.0 300.0

3

3.5

4

150.0 300.0

175.0 350.0

200.0 400.0

3

50.0 100.0

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

40

Freescale Semiconductor

Clock Configuration Modes

1,2

Table 20. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) (continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

CPU

Bus

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

0100_100

25.0 50.0

6

150.0 300.0

4.5

225.0 450.0

3

50.0 100.0

0101_000

0101_001

0101_010

0101_011

0101_100

0101_101

0101_110

30.0 50.0

25.0 50.0

5

150.0 250.0

125.0 250.0

2.5

3

150.0 250.0

150.0 300.0

175.0 350.0

200.0 400.0

225.0 450.0

250.0 500.0

275.0 550.0

2.5

60.0 100.0

50.0 100.0

3.5

4

4.5

5

5.5

0110_000

0110_001

0110_010

0110_011

0110_100

Reserved

25.0 50.0

8

200.0 400.0

3

3.5

4

200.0 400.0

233.3 466.7

266.7 533.3

300.0 600.0

3

66.7 133.3

4.5

0111_000

0111_001

0111_010

0111_011

25.0 50.0

6

150.0 300.0

2

2.5

3

150.0 300.0

187.5 375.0

225.0 450.0

262.5 525.0

2

75.0 150.0

3.5

1000_000

1000_001

1000_010

1000_011

1000_100

1000_101

Reserved

25.0 50.0

6

150.0 300.0

2.5

3

150.0 300.0

180.0 360.0

210.0 420.0

240.0 480.0

270.0 540.0

2.5

60.0 120.0

3.5

4

4.5

1001_000

1001_001

Reserved

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

41

Clock Configuration Modes

1,2

Table 20. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) (continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

CPU

Bus

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

1001_010

1001_011

1001_100

Reserved

25.0 50.0

8

200.0 400.0

4

200.0 400.0

225.0 450.0

4

50.0 100.0

4.5

1010_000

1010_001

1010_010

1010_011

1010_100

Reserved

25.0 50.0

8

200.0 400.0

3

3.5

4

200.0 400.0

233.3 466.7

266.7 533.3

300.0 600.0

3

66.7 133.3

4.5

1011_000

1011_001

1011_010

1011_011

1011_100

Reserved

25.0 50.0

8

200.0 400.0

2.5

3

200.0 400.0

240.0 480.0

280.0 560.0

320.0 640.0

2.5

80.0 160.0

3.5

4

1011_101

1011_110

1011_111

25.0 50.0

8

200.0 400.0

2.5

3

250.0 500.0

300.0 600.0

350.0 700.0

2

100.0 200.0

3.5

1100_101

1100_110

1100_111

1101_000

25.0 50.0

6

150.0 300.0

4

4.5

5

200.0 400.0

225.0 450.0

250.0 500.0

275.0 550.0

3

50.0 100.0

5.5

1101_001

1101_010

1101_011

1101_100

25.0 50.0

6

150.0 300.0

3.5

4

210.0 420.0

240.0 480.0

270.0 540.0

300.0 600.0

2.5

60.0 120.0

4.5

5

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

42

Freescale Semiconductor

Pinout

1,2

Table 20. Clock Configurations for PCI Agent Mode (PCI_MODCK=1) (continued)

PCI Clock

(MHz)

CPM Clock

(MHz)

CPU Clock

(MHz)

Bus Clock

(MHz)

3

Mode

CPM

CPU

Bus

Multiplication

Division

Factor

4

5

MODCK_H-

MODCK[1-3]

Factor

Low High

1110_000

1110_001

1110_010

1110_011

25.0 50.0

28.6 50.0

25.0 50.0

5

125.0 250.0

142.9 250.0

125.0 250.0

2.5

3

156.3 312.5

187.5 375.0

250.0 437.5

250.0 500.0

2

62.5 125.0

71.4 125.0

62.5 125.0

3.5

4

1110_100

1110_101

1110_110

1110_111

25.0 50.0

5

125.0 250.0

4

4.5

5

166.7 333.3

187.5 375.0

208.3 416.7

229.2 458.3

3

41.7 83.3

5.5

1100_000

1100_001

1100_010

Reserved

1

The “low” values are the minimum allowable frequencies for a given clock mode. The minimum bus frequency in a

table entry guarantees only the required minimum CPU operating frequency. The “high” values are for the purpose of

illustration only. Users must select a mode and input bus frequency so that the resulting configuration does not exceed

the frequency rating of the user’s device. The minimum CPU frequency is 150 MHz for commercial temperature

devices and 175 MHz for extended temperature devices. The minimum CPM frequency is 120 MHz.

PCI_MODCK determines the PCI clock frequency range. See Table 19 for higher range configurations.

MODCK_H = hard reset configuration word [28–31] (see Section 5.4 in the SoC reference manual). MODCK[1-3] =

three hardware configuration pins.

2

3

4

5

CPM multiplication factor = CPM clock/bus clock

CPU multiplication factor = Core PLL multiplication factor

8 Pinout

This figure and table show the pin assignments and pinout for the 516 PBGA package.

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

43

Pinout

This figure shows the pinout of the 516 PBGA package as viewed from the top surface.

1

2

3

4

5 6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

A

B

A

B

C

D

E

F

G

H

J

K

L

M

N

M

N

P

R

T

U

V

W

Y

W

Y

AA

AB

AC

AD

AE

AF

AA

AB

AC

AD

AE

AF

1

2

3

4

5 6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26

Not to Scale

Figure 12. Pinout of the 516 PBGA Package (View from Top)

This table lists the pins of the MPC8272. Note that the pins in the “MPC8272/8271 Only” column relate

to Utopia functionality.

Table 21. Pinout

Pin Name

Ball

MPC8272/MPC8248 and

MPC8272/MPC8271 Only

MPC8271/MPC8247

BR

A19

D2

BG/IRQ6

ABB/IRQ2

C1

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

44

Freescale Semiconductor

Pinout

Table 21. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 Only

TS

A0

D1

A3

A1

B5

A2

D8

A3

C6

A4

A5

A6

B6

A7

C7

A8

B7

A9

A7

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

D9

E11

C9

B9

D11

A9

B10

A10

B11

A11

D12

A12

D13

B13

C13

C14

B14

D14

E14

A14

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

45

Pinout

Table 21. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 Only

A30

A31

B15

A15

B3

TT0

TT1

E8

TT2

D7

C4

E7

TT3

TT4

TBST

TSIZ0

TSIZ1

TSIZ2

TSIZ3

AACK

ARTRY

DBG/IRQ7

DBB/IRQ3

D0

E3

E4

E5

C3

D5

D3

C2

F16

D18

AC1

AA1

V3

D1

D2

D3

R5

P4

D4

D5

M4

J4

D6

D7

G1

W6

Y3

D8

D9

D10

V1

D11

N6

P3

D12

D13

M2

J5

D14

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

46

Freescale Semiconductor

Pinout

Table 21. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 Only

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

D27

D28

D29

D30

D31

D32

D33

D34

D35

D36

D37

D38

D39

D40

D41

D42

D43

D44

D45

G3

AB3

Y1

T4

T3

P2

M1

J1

G4

AB2

W4

V2

T1

N5

L1

H1

G5

W5

W2

T5

T2

N1

K3

H2

F1

AA2

W1

U3

R2

N2

L2

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

47

Pinout

Table 21. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 Only

D46

D47

D48

D49

D50

D51

D52

D53

D54

D55

D56

D57

D58

D59

D60

D61

D62

D63

H4

F2

AB1

U4

U1

R3

N3

K2

H5

F4

AA3

U5

U2

P5

M3

K4

H3

E1

IRQ3/CKSTP_OUT/EXT_BR3

B16

C15

Y4

IRQ4/CORE_SRESET/EXT_BG3

IRQ5/TBEN/EXT_DBG3/CINT

PSDVAL

TA

C19

AA4

AB6

D15

D16

C16

E17

B20

AE6

AD7

TEA

GBL/IRQ1

CI/BADDR29/IRQ2

WT/BADDR30/IRQ3

BADDR31/IRQ5/CINT

CPU_BR/INT_OUT

CS0

CS1

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

48

Freescale Semiconductor

Pinout

Table 21. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 Only

CS2

CS3

AF5

AC8

AF6

CS4

CS5

AD8

AC9

AB9

AB8

AC7

AF4

CS6/BCTL1/SMI

CS7/TLBISYNC

BADDR27/IRQ1

BADDR28/IRQ2

ALE/IRQ4

BCTL0

AF3

PWE0/PSDDQM0/PBS0

PWE1/PSDDQM1/PBS1

PWE2/PSDDQM2/PBS2

PWE3/PSDDQM3/PBS3

PWE4/PSDDQM4/PBS4

PWE5/PSDDQM5/PBS5

PWE6/PSDDQM6/PBS6

PWE7/PSDDQM7/PBS7

PSDA10/PGPL0

AD6

AE5

AE3

AF2

AC6

AC5

AD4

AB5

AE2

AD3

AB4

AC3

AD2

AC2

AD22

AC21

AE22

AE23

AF12

AD15

AF16

PSDWE/PGPL1

POE/PSDRAS/PGPL2

PSDCAS/PGPL3

PGTA/PUPMWAIT/PGPL4

PSDAMUX/PGPL5

1

PCI_MODE

PCI_CFG0 (PCI_HOST_EN)

PCI_CFG1 (PCI_ARB_EN)

PCI_CFG2 (DLL_ENABLE)

PCI_ PAR

PCI_FRAME

PCI_TRDY

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

49

Pinout

Table 21. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 Only

PCI_IRDY

PCI_STOP

PCI_DEVSEL

PCI_IDSEL

PCI_PERR

PCI_SERR

PCI_REQ0

AF15

AE15

AE14

AC17

AD14

AD13

AE20

AF14

AD20

AE13

AF21

AF22

AE21

AB14

AC22

AF7

PCI_REQ1/CPCI_HS_ES

PCI_GNT0

PCI_GNT1/CPCI_HS_LED

PCI_GNT2/CPCI_HS_ENUM

PCI_RST

PCI_INTA

PCI_REQ2

DLLOUT

PCI_AD0

PCI_AD1

AE10

AB10

AD10

AE9

PCI_AD2

PCI_AD3

PCI_AD4

PCI_AD5

AF8

PCI_AD6

AC10

AE11

AB11

AF10

AF9

PCI_AD7

PCI_AD8

PCI_AD9

PCI_AD10

PCI_AD11

AB12

AC12

AD12

AF11

AB13

PCI_AD12

PCI_AD13

PCI_AD14

PCI_AD15

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

50

Freescale Semiconductor

Pinout

Table 21. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 Only

PCI_AD16

PCI_AD17

PCI_AD18

PCI_AD19

PCI_AD20

PCI_AD21

PCI_AD22

PCI_AD23

PCI_AD24

PCI_AD25

PCI_AD26

PCI_AD27

PCI_AD28

PCI_AD29

PCI_AD30

PCI_AD31

PCI_C0/BE0

PCI_C1/BE1

PCI_C2/BE2

PCI_C3/BE3

IRQ0/NMI_OUT

AE16

AF17

AD16

AC16

AF18

AB16

AD17

AF19

AB17

AF20

AE19

AC18

AB18

AD19

AD21

AC20

AE12

AF13

AC15

AE18

A17

2

TRST

E21

TCK

TMS

TDI

B22

C23

B24

TDO

A22

TRIS

B23

2

PORESET /PCI_RST

HRESET

C24

D22

SRESET

F22

RSTCONF

A24

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

51

Pinout

Table 21. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 Only

MODCK1/RSRV/TC0/BNKSEL0

A20

C20

MODCK2/CSE0/TC1/BNKSEL1

MODCK3/CSE1/TC2/BNKSEL2

CLKIN1

A21

D21

3

PA8/SMRXD2

AF25

AA22

AB23

PA9/SMTXD2

PA10/MSNUM5

FCC1_UT_RXD0

FCC1_UT_RXD1

FCC1_UT_RXD2

FCC1_UT_RXD3

FCC1_UT_RXD4

FCC1_UT_RXD5

FCC1_UT_RXD6

FCC1_UT_RXD7

PA11/MSNUM4

PA12/MSNUM3

AD26

AD25

AA24

3

PA13/MSNUM2

3

PA14/FCC1_MII_HDLC_RXD3

PA15/FCC1_MII_HDLC_RXD2

PA16/FCC1_MII_HDLC_RXD1

PA17/FCC1_MII_HDLC_RXD0/

W22

3

Y24

3

T22

3

W26

FCC1_MII_TRAN_RXD/FCC1_RMII_RX

D0

3

PA18/FCC1_MII_HDLC_TXD0/FCC1_MII

_TRAN_TXD/

FCC1_UT_TXD7

FCC1_UT_TXD6

V26

R23

FCC1_RMII_TXD0

3

PA19/FCC1_MII_HDLC_TXD1/FCC1_RM

II_TXD1

3

PA20/FCC1_MII_HDLC_TXD2

PA21/FCC1_MII_HDLC_TXD3

PA22

FCC1_UT_TXD5

FCC1_UT_TXD4

FCC1_UT_TXD3

FCC1_UT_TXD2

FCC1_UT_TXD1

FCC1_UT_TXD0

FCC1_UT_RXCLAV

FCC1_UT_RXSOC

P25

N22

N26

N23

H26

PA23

PA24/MSNUM1

PA25/MSNUM0

G25

3

PA26/FCC1_MII_RMIIRX_ER

L22

3

PA27/FCC1_MII_RX_DV/FCC1_RMII_CR

S_DV

G24

3

PA28/FCC1_MII_RMII_TX_EN

PA29/FCC1_MII_TX_ER

FCC1_UT_RXENB

FCC1_UT_TXSOC

FCC1_UT_TXCLAV

G23

3

B26

A25

3

PA30/FCC1_MII_CRS/FCC1_RTS

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

52

Freescale Semiconductor

Pinout

Table 21. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 Only

3

PA31/FCC1_MII_COL

FCC1_UT_TXENB

G22

3

PB18/FCC2_MII_HDLC_RXD3

T25

P22

3

PB19/FCC2_MII_HDLC_RXD2

PB20/FCC2_MII_HDLC_RMII_RXD1

3

L25

3

PB21/FCC2_MII_HDLC_RMII_RXD0/FCC2_TRAN_RXD

J26

3

PB22/FCC2_MII_HDLC_TXD0/FCC2_TRAN_TXD/

FCC2_RMII_TXD0

U23

3

PB23/FCC2_MII_HDLC_TXD1/FCC2_RMII_TXD1

PB24/FCC2_MII_HDLC_TXD2/L1RSYNCB2

PB25/FCC2_MII_HDLC_TXD3/L1TSYNCB2

PB26/FCC2_MII_CRS/L1RXDB2

U26

M24

M23

3

H24

E25

D26

K21

D24

E23

PB27/FCC2_MII_COL/L1TXDB2

PB28/FCC2_MII_RMII_RX_ER/FCC2_RTS/TXD1

PB29/FCC2_MII_RMII_TX_EN

PB30/FCC2_MII_RX_DV/FCC2_RMII_CRS_DV

PB31/FCC2_MII_TX_ER

3

PC0/DREQ3/BRGO7/SMSYN1/L1CLKOA2

PC1/BRGO6/L1RQA2

AF23

AD23

AB22

AE24

3

PC4/SMRXD1/SI2_L1ST4/FCC2_CD

PC5/SMTXD1/SI2_L1ST3/FCC2_CTS

3

PC6/FCC1_CD/SI2_L1ST2

PC7/FCC1_CTS

FCC1_UT_RXADDR2

FCC1_UT_TXADDR2

AF24

AE26

PC8/CD4/RTS1/SI2_L1ST2/CTS3

AC24

AA23

AB25

3

PC9/CTS4/L1TSYNCA2

PC10/CD3/USB_RN

3

PC11/CTS3/USB_RP/L1TXD3A2

V22

3

PC12

FCC1_UT_RXADDR1

FCC1_UT_TXADDR1

FCC1_UT_RXADDR0

FCC1_UT_TXADDR0

AA26

3

PC13/BRGO5

PC14/CD1

V23

3

W24

3

PC15/CTS1

U24

3

PC16/CLK16

T23

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

53

Pinout

Table 21. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 Only

3

PC17/CLK15/BRGO8/DONE2

T26

R26

P24

3

PC18/CLK14/TGATE2

PC19/CLK13/BRGO7/TGATE1

PC20/CLK12/USBOE

3

L26

L24

L23

PC21/CLK11/BRGO6/CP_INT

PC22/CLK10/DONE3

FCC1_UT_TXPRTY

PC23/CLK9/BRGO5/DACK3/CD1

PC24/CLK8/TIN3/TOUT4/DREQ2/BRGO1

PC25/CLK7/BRGO4/DACK2/SPISEL

PC26/CLK6/TOUT3/TMCLK

K24

K23

3

F26

3

H23

K22

D25

3

PC27/CLK5/BRGO3/TOUT1

FCC1_UT_RXPRTY

PC28/CLK4/TIN1/TOUT2/SPICLK

PC29/CLK3/TIN2/BRGO2/CTS1

3

F24

3

PD7/SMSYN2

FCC1_UT_TXADDR3

AB21

AC26

3

PD14/I2CSCL

PD15/I2CSDA

3

Y23

3

PD16/SPIMISO

PD17/BRGO2/SPIMOSI

PD18/SPICLK

FCC1_UT_TXPRTY

FCC1_UT_RXPRTY

FCC1_UT_RXADDR4

FCC1_UT_TXADDR4

AA25

3

Y26

3

W25

3

PD19/SPISEL/BRGO1

V25

R24

P23

N25

K26

K25

3

PD20/RTS4/L1RSYNCA2

PD21/TXD4/L1RXD0A2

PD22/RXD4/L1TXD0A2

PD23/RTS3/USB_TP

PD24/TXD3/USB_TN

PD25/RXD3/USB_RXD

3

J25

3

PD29/RTS1

FCC1_UT_RXADDR3

C26

E24

B25

3

PD30/TXD1

PD31/RXD1

VCCSYN

C18

K6

VCCSYN1

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

54

Freescale Semiconductor

Pinout

Table 21. Pinout (continued)

Pin Name

Ball

MPC8272/MPC8248 and

MPC8271/MPC8247

MPC8272/MPC8271 Only

CLKIN2

No connect

I/O power

C21

4

5

D19 , J3 , AD24

B4, F3, J2, N4, AD1, AD5, AE8,

AC13, AD18, AB24, AB26, W23, R25,

M25, F25, C25, C22, B17, B12, B8,

E6, F6, H6, L5, L6, P6, T6, U6, V5,

Y5, AA6, AA8, AA10, AA11, AA14,

AA16, AA17, AB19, AB20, W21, U21,

T21, P21, N21, M22, J22, H21, F21,

F19, F17, E16, F14, E13, E12, F10,

E10, E9

Core Power

F5, K5, M5, AA5, AB7, AA13, AA19,

AA21, Y22, AC25, U22, R22, L21,

H22, E22, E20, E15, F13, F11, F8,

L3, V4, W3, AC11, AD11, AB15, U25,

T24, J24, H25, F23, B19, D17, C17,

D10, C10

Ground

E19, E2, K1, Y2, AE1, AE4, AD9,

AC14, AE17, AC19, AE25, V24, P26,

M26, G26, E26, B21, C12, C11, C8,

A8, B18, A18, A2, B1, B2, A5, C5, D4,

D6, G2, L4, P1, R1, R4, AC4, AE7,

AC23, Y25, N24, J23, A23, D23, D20,

E18, A13, A16, K10, K11, K12, K13,

K14, K15, K16, K17, L10, L11, L12,

L13, L14, L15, L16, L17, M10, M11,

M12, M13, M14, M15, M16, M17,

N10, N11, N12, N13, N14, N15, N16,

N17, P10, P11, P12, P13, P14, P15,

P16, P17, R10, R11,R12, R13, R14,

R15, R16, R17, T10, T11, T12, T13,

T14, T15, T16, T17, U10, U11, U12,

U13, U14, U15, U16, U17

1

2

3

Must be tied to ground.

Should be tied to VDDH via a 2K Ω external pull-up resistor.

The default configuration of the CPM pins (PA[8–31], PB[18–31], PC[0–1,4–29], PD[7–25, 29–31]) is input. To prevent

excessive DC current, it is recommended either to pull unused pins to GND or VDDH, or to configure them as outputs.

This pin is not connected. It should be left floating.

4

5

Must be pulled down or left floating

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

55

Package Description

9 Package Description

This figure shows the side profile of the PBGA package to indicate the direction of the top surface view.

Wire bonds

Ball bond

Die

attach

Transfer molding compound

Plated substrate via

Screen-printed

solder mask

Cu substrate traces

Resin glass epoxy

DIE

1 mm pitch

Figure 13. Side View of the PBGA Package Remove

9.1

Package Parameters

This table provides package parameters.

Table 22. Package Parameters

Outline

(mm)

Pitch

(mm)

NominalUnmounted

Height (mm)

Code

Type

Interconnects

VR, ZQ

PBGA

27 x 27

516

1

2.25

NOTE: Temperature Reflow for the VR Package

In the VR package, sphere composition is lead-free (see Table 2). This

requires higher temperature reflow than what is required for other

PowerQUICC II packages. Consult “Freescale PowerQUICC II Pb-Free

Packaging Information” (MPC8250PBFREEPKG) available on

www.freescale.com.

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

56

Freescale Semiconductor

Package Description

9.2

Mechanical Dimensions

This figure provides the mechanical dimensions and bottom surface nomenclature of the 516 PBGA

package.

Figure 14. Mechanical Dimensions and Bottom Surface Nomenclature—516 PBGA

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

57

Ordering Information

10 Ordering Information

This figure provides an example of the Freescale part numbering nomenclature for the SoC. In addition to

the processor frequency, the part numbering scheme also consists of a part modifier that indicates any

enhancement(s) in the part from the original production design. Each part number also contains a revision

code that refers to the die mask revision number and is specified in the part numbering scheme for

identification purposes only. For more information, contact your local Freescale sales office.

MPC 82XX C VR XXX X

Die revision level

Product code

Device number

Processor frequency

CPU/CPM/Bus in MHz)

B = 66

E = 100

F = 133

Temperature range

Blank = 0 to 105 °C

C = –40 to 105 °C

I = 200

M = 266

P = 300

Package

ZQ = 516 PBGA (lead spheres)

VR = 516 PBGA (no lead spheres)

T = 400

Figure 15. Freescale Part Number Key

11 Document Revision History

This table summarizes changes to this document.

Table 23. Document Revision History

Substantive Changes

Date

Revision

3

09/2011 In Figure 15, “Freescale Part Number Key,” added speed decoding information below processor

frequency information.

2

12/2008 • Modified Figure 5, “SCC/SMC/SPI/I2C External Clock Diagram,” and added second section of

figure notes.

• In Table 12, modified “Data bus in pipeline mode” row and showed 66 MHz as “N/A.”

• In Section 10, “Ordering Information,” added “F = 133” to CPU/CPM/Bus Frequency.

• Added footnote concerning CPM_CLK/PCI_CLK ratio to column “PCI Division Factor” in

Table 17, “Clock Configurations for PCI Host Mode (PCI_MODCK=0),” and Table 18, “Clock

Configurations for PCI Host Mode (PCI_MODCK=1),.”

• Removed overbar from DLL_ENABLE in Table 21, “Pinout.”

1.5

12/2006 • Section 6, “AC Electrical Characteristics,” removed deratings statement and clarified AC

timing descriptions.

1.4

1.3

05/2006 • Added row for 133 MHz configurations to Table 8.

02/2006 • Inserted Section 6.3, “JTAG Timings.”

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

58

Freescale Semiconductor

Document Revision History

Table 23. Document Revision History (continued)

Substantive Changes

Date

Revision

1.2

09/2005 • Added 133-MHz to the list of frequencies in the opening sentence of Section 6, “AC Electrical

Characteristics”.

• Added 133 MHz columns to Table 9, Table 11, Table 12, and Table 13.

• Added footnote 2 to Table 13.

• Added the conditions note directly above Table 12.

1.1

1.0

01/2005 • Modification for correct display of assertion level (“overbar”) for some signals

12/2004 • Section 1.1: Added 8:1 ratio to Internal CPM/bus clock multiplier values

• Section 2: removed voltage tracking note

• Table 3: Note 2 updated regarding VDD/VCCSYN relationship to VDDH during power-on reset

• Table 4: Updated VDD and VCCSYN to 1.425 V - 1.575 V

• Table 8: Note 2 updated to reflect VIH=2.5 for TCK, TRST, PORESET; request for external

pull-up removed.

• Section 4.6: Updated description of layout practices

• Table 8: Note 3 added regarding IIC compatibility

• Table 8: Updated nominal and maximum power dissipation values

• Table 9: updated PCI impedance to 27Ω, updated 60x and MEMC values and added note to

reflect configurable impedance

• Section 6: Added sentence providing derating factor

• Section 6.1: added Note: Rise/Fall Time on CPM Input Pins

• Table 9: updated values for following specs: sp36b, sp37a, sp38a, sp39a, sp38b, sp40, sp41,

sp42, sp43, sp42a

• Table 11: updated values for following specs: sp16a, sp16b, sp18a, sp18b, sp20, sp21, sp22

• Section 6.2: added spread spectrum clocking note

• Section 6.2: added CLKIN jitter note

• Table 12: combined specs sp11 and sp11a

• Table 13: sp30 Data Bus minimum delay values changed to 0.8

• Section 7: unit of ns added to Tval notes

• Section 7: Updated all notes to reflect updated CPU Fmin of 150 MHz commercial temp

devices, 175 MHz extended temp; CPM Fmin of 120 MHz.

• Section 7, “Clock Configuration Modes”: Updated all table footnotes reflect updated CPU Fmin

of 150 MHz commercial temp devices, 175 MHz extended temp; CPM Fmin of 120 MHz.

• Table 21: correct superscript of footnote number after pin AD22

• Table 21: remove DONE3 from PC12

• Table 21: signals referring to TDMs C2 and D2 removed

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

Freescale Semiconductor

59

Document Revision History

Table 23. Document Revision History (continued)

Substantive Changes

Date

Revision

0.2

12/2003 • Table 1: New

• Table 2: New

• Table 4: Modification of VDD and VCCSYN to 1.45–1.60 V

• Table 8: Addition of note 2 regarding TRST and PORESET (see V row of Table 8)

IH

• Table 8 and Table 21: Addition of muxed signals

CPCI_HS_ES to PCI_REQ1 (AF14)

CPCI_HS_LED to PCI_GNT1 (AE13)

CPCI_HS_ENUM to PCI_GNT2 (AF21)

• Table 8 and Table 21: Modification of PCI signal names for consistency with PCI signal names

on other PowerQUICC II devices:

PCI_CFG0 (PCI_HOST_EN) (AC21)

PCI_CFG1 (PCI_ARB_EN) (AE22)

PCI_CFG2 (DLL_ENABLE) (AE23)

PCI_PAR (AF12)

PCI_FRAME (AD15)

PCI_TRDY(AF16)

PCI_IRDY (AF15)

PCI_STOP (AE15)

DEVSEL (AE14)

PCI_IDSEL (AC17)

PCI_PERR (AD14)

PCI_SERR (AD13)

PCI_REQ0–2 (AAE20, AF14, AB14)

PCI_GNT0–2 (AD20, AE13, AF21)

PCI_RST (AF22)

PCI_INTA (AE21)

PCI_C0-3 (AE12, AF13, AC15, AE18)

PCI_AD0-31

• Table 8 and Table 21: Corrected assertion level (added “ “) PCI_HOST_EN (AC21) and

PCI_ARB_EN (AE22)

• Table 7: Addition of R

and note 4

θJT

• Sections 4.1–4.5 and 4.7 on thermal characteristics: New

• Section 7, “Clock Configuration Modes”: Modification to first paragraph. Note that

PCI_MODCK is a bit in the Hard Reset Configuration Word. It is not an input signal as it is in

the MPC8280 Family and MPC8260 Family.

• Addition of “Note: Temperature Reflow for the VR Package" on page 56

• Table 21: Addition of note 2 to TRST (E21) and PORESET (C24)

• Table 21: Removal of Thermal0 (D19) and Thermal1(J3). These pins are now “No connects.”

Note 4 unchanged.

• Table 21: Removal of Spare0 (AD24). This pin is now a “No connect.” Note 5 unchanged.

• Table 21: Addition of PCI_MODE (AD22). This pin was previously listed as “Ground.” Addition

of note 1.

0.1

9/2003

• Addition of the MPC8271 and the MPC8247 (these devices do not have a security engine)

• Table 8: Addition of note 2 to V

IH

• Table 8: Changed I for 60x signals to 6.0 mA

OL

• Modification of note 1 for Table 17, Table 18, Table 19, and Table 20

• Table 21: Addition of ball AD9 to GND. In rev 0 of this document, AD8 was listed as assigned

to both CS5 and GND. AD8 is only assigned to CS5.

• Table 21: Addition of note 4 to Thermal0 (D19) and Thermal1(J3)

• Addition of ZQ package code to Figure 15

0

5/2003

NDA release

MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3

60

Freescale Semiconductor

How to Reach Us:

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Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

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Document Number: MPC8272EC

Rev. 3

09/2011


型号：	MPC8272CZQMIBA
厂家：	NXP
描述：	RISC MICROCONTROLLER 时钟外围集成电路
文件：	总61页 (文件大小：608K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MPC8272CZQMIBA [NXP]

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