MPC8377CVRALD [NXP]
MICROPROCESSOR;型号: | MPC8377CVRALD |
厂家: | NXP |
描述: | MICROPROCESSOR 外围集成电路 |
文件: | 总127页 (文件大小:2897K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Document Number: MPC8377EEC
Rev. 10, 07/2014
Freescale Semiconductor
Technical Data
MPC8377E
PowerQUICC II Pro Processor
Hardware Specifications
Contents
This document provides an overview of the MPC8377E
PowerQUICC II Pro processor features, including a block
diagram showing the major functional components. This
chip is a cost-effective, low-power, highly integrated host
processor that addresses the requirements of several
printing and imaging, consumer, and industrial
applications, including main CPUs and I/O processors in
printing systems, networking switches and line cards,
wireless LANs (WLANs), network access servers (NAS),
VPN routers, intelligent NIC, and industrial controllers.
This chip extends the PowerQUICC family, adding higher
CPU performance, additional functionality, and faster
interfaces while addressing the requirements related to
time-to-market, price, power consumption, and package
size.
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 7
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 11
4. Clock Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . 13
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . 15
6. DDR1 and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . 16
7. DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
8. Ethernet: Enhanced Three-Speed Ethernet (eTSEC) 23
9. USB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
11. Enhanced Secure Digital Host Controller (eSDHC) 43
12. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
13. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
14. PCI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
15. PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
16. Serial ATA (SATA) . . . . . . . . . . . . . . . . . . . . . . . . . . 68
17. Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
18. GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
19. IPIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
20. SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
21. High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 77
22. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 87
23. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
24. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
25. System Design Information . . . . . . . . . . . . . . . . . . 119
26. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 121
27. Document Revision History . . . . . . . . . . . . . . . . . . 123
1 Overview
This chip incorporates the e300c4s core, which includes
32 KB of L1 instruction and data caches and on-chip
memory management units (MMUs). The device offers
two enhanced three-speed 10, 100, 1000 Mbps Ethernet
interfaces, a DDR1/DDR2 SDRAM memory controller, a
flexible, a 32-bit local bus controller, a 32-bit PCI
controller, an optional dedicated security engine, a USB
2.0 dual-role controller, a programmable interrupt
© 2008-2012, 2014 Freescale Semiconductor, Inc. All rights reserved.
2
controller, dual I C controllers, a 4-channel DMA controller, an enhanced secured digital host controller,
and a general-purpose I/O port. This figure shows the block diagram of the chip.
MPC8377E
DUART
Dual I2C
e300 Core
Timers
GPIO
SPI
Interrupt
Controller
32 KB
32 KB
I-Cache
DDR1/DDR2
SDRAM
Controller
Enhanced
Local Bus
D-Cache
Security
USB 2.0
Hi-Speed
SD/MMC
Controller
PCI
Express
SATA
eTSEC
eTSEC
x1
x2
PHY PHY
RGMII, RMII, RGMII, RMII,
RTBI, MII RTBI, MII
DMA
PCI
Host Device
Figure 1. MPC8377E Block Diagram and Features
The following features are supported in the chip:
•
e300c4s core built on Power Architecture® technology with 32 KB instruction cache and 32 KB
data cache, a floating point unit, and two integer units
•
•
•
•
•
•
DDR1/DDR2 memory controller supporting a 32/64-bit interface
Peripheral interfaces, such as a 32-bit PCI interface with up to 66-MT/s operation
32-bit local bus interface running up to 133-MT/s
USB 2.0 (full/high speed) support
Power management controller for low-power consumption
High degree of software compatibility with previous-generation PowerQUICC processor-based
designs for backward compatibility and easier software migration
•
Optional security engine provides acceleration for control and data plane security protocols
The optional security engine (SEC 3.0) is noted with the extension “E” at the end. It allows CPU-intensive
cryptographic operations to be offloaded from the main CPU core. The security-processing accelerator
provides hardware acceleration for the DES, 3DES, AES, SHA-1, and MD-5 algorithms.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
2
Freescale Semiconductor
In addition to the security engine, new high-speed interfaces, such as PCI Express and SATA are included.
This table compares the differences between MPC837xE derivatives and provides the number of ports
available for each interface.
Table 1. High-Speed Interfaces on the MPC8377E, MPC8378E, and MPC8379E
Descriptions
MPC8377E
MPC8378E
MPC8379E
SGMII
PCI Express®
SATA
0
2
2
2
2
0
0
0
4
1.1
DDR Memory Controller
The DDR1/DDR2 memory controller includes the following features:
•
•
•
•
Single 32- or 64-bit interface supporting both DDR1 and DDR2 SDRAM
Support for up to 400-MT/s data rate
Support up to 4 chip selects
64-Mbit to 2-Gbit (for DDR1) and to 4-Gbit (for DDR2) devices with ×8/×16/×32 data ports (no
direct ×4 support)
•
•
•
•
Support for up to 32 simultaneous open pages
Supports auto refresh
On-the-fly power management using CKE
1.8-/2.5-V SSTL2 compatible I/O
1.2
USB Dual-Role Controller
The USB controller includes the following features:
•
Supports USB on-the-go mode, including both device and host functionality, when using an
external ULPI (UTMI + low-pin interface) PHY
•
•
Complies with USB Specification, Rev. 2.0
Supports operation as a stand-alone USB device
— Supports one upstream facing port
— Supports three programmable USB endpoints
Supports operation as a stand-alone USB host controller
— Supports USB root hub with one downstream-facing port
— Enhanced host controller interface (EHCI) compatible
•
•
•
Supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) operation;
low-speed operation is supported only in host mode
Supports UTMI + low pin interface (ULPI)
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
3
1.3
Dual Enhanced Three-Speed Ethernet Controllers (eTSECs)
The eTSECs include the following features:
•
•
Two enhanced Ethernet interfaces can be used for RGMII/MII/RMII/RTBI
Two controllers conform to IEEE Std 802.3®, IEEE 802.3u, IEEE 802.3x, IEEE 802.3z,
IEEE 802.3au, IEEE 802.3ab, and IEEE Std 1588™ standards
•
•
Support for Wake-on-Magic Packet™, a method to bring the device from standby to full operating
mode
MII management interface for external PHY control and status
1.4
Integrated Programmable Interrupt Controller (IPIC)
The integrated programmable interrupt controller (IPIC) implements the necessary functions to provide a
flexible solution for general-purpose interrupt control. The IPIC programming model is compatible with
the MPC8260 interrupt controller, and it supports 8 external and 34 internal discrete interrupt sources.
Interrupts can also be redirected to an external interrupt controller.
1.5
Power Management Controller (PMC)
The power management controller includes the following features:
•
•
•
•
•
Provides power management when the device is used in both host and agent modes
Supports PCI Power Management 1.2 D0, D1, D2, and D3hot states
Support for PME generation in PCI agent mode, PME detection in PCI host mode
Supports Wake-on-LAN (Magic Packet), USB, GPIO, and PCI (PME input as host)
Supports MPC8349E backward-compatibility mode
1.6
Serial Peripheral Interface (SPI)
The serial peripheral interface (SPI) allows the device to exchange data between other PowerQUICC
family chips, Ethernet PHYs for configuration, and peripheral devices such as EEPROMs, real-time
clocks, A/D converters, and ISDN devices.
The SPI is a full-duplex, synchronous, character-oriented channel that supports a four-wire interface
(receive, transmit, clock, and slave select). The SPI block consists of transmitter and receiver sections, an
independent baud-rate generator, and a control unit.
2
1.7
DMA Controller, Dual I C, DUART, Enhanced Local Bus Controller
(eLBC), and Timers
The device provides an integrated four-channel DMA controller with the following features:
•
Allows chaining (both extended and direct) through local memory-mapped chain descriptors
(accessible by local masters)
•
Supports misaligned transfers
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
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Freescale Semiconductor
2
There are two I C controllers. These synchronous, multi-master buses can be connected to additional
devices for expansion and system development.
The DUART supports full-duplex operation and is compatible with the PC16450 and PC16550
programming models. 16-byte FIFOs are supported for both the transmitter and the receiver.
The main component of the enhanced local bus controller (eLBC) is its memory controller, which provides
a seamless interface to many types of memory devices and peripherals. The memory controller is
responsible for controlling eight memory banks shared by a NAND Flash control machine (FCM), a
general-purpose chip-select machine (GPCM), and up to three user-programmable machines (UPMs). As
such, it supports a minimal glue logic interface to SRAM, EPROM, NOR Flash EPROM, NAND Flash,
EPROM, burstable RAM, regular DRAM devices, extended data output DRAM devices, and other
peripherals. The eLBC external address latch enable (LALE) signal allows multiplexing of addresses with
data signals to reduce the device pin count.
The enhanced local bus controller also includes a number of data checking and protection features, such
as data parity generation and checking, write protection, and a bus monitor to ensure that each bus cycle
is terminated within a user-specified period. The local bus can operate at up to 133 MT/s.
The system timers include the following features: periodic interrupt timer, real time clock, software
watchdog timer, and two general-purpose timer blocks.
1.8
Security Engine
The optional security engine is optimized to handle all the algorithms associated with IPSec,
IEEE 802.11i, and iSCSI. The security engine contains one crypto-channel, a controller, and a set of crypto
execution units (EUs). The execution units are as follows:
•
•
•
Data encryption standard execution unit (DEU), supporting DES and 3DES
Advanced encryption standard unit (AESU), supporting AES
Message digest execution unit (MDEU), supporting MD5, SHA1, SHA-256, and HMAC with any
algorithm
•
One crypto-channel supporting multi-command descriptor chains
1.9
PCI Controller
The PCI controller includes the following features:
•
•
•
•
•
•
PCI Specification Revision 2.3 compatible
Single 32-bit data PCI interface operates at up to 66 MT/s
PCI 3.3-V compatible (not 5-V compatible)
Support for host and agent modes
On-chip arbitration, supporting 5 external masters on PCI
Selectable hardware-enforced coherency
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
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1.10 PCI Express Controller
The PCI Express controller includes the following features:
•
•
•
•
•
•
•
•
•
•
•
PCI Express 1.0a compatible
Two ×1 links or one ×2 link width
Auto-detection of number of connected lanes
Selectable operation as root complex or endpoint
Both 32- and 64-bit addressing
128-byte maximum payload size
Support for MSI and INTx interrupt messages
Virtual channel 0 only
Selectable Traffic Class
Full 64-bit decode with 32-bit wide windows
Dedicated four channel descriptor-based DMA engine per interface
1.11 Serial ATA (SATA) Controllers
The serial ATA (SATA) controllers have the following features:
•
•
•
•
•
•
•
•
•
•
•
•
Supports Serial ATA Rev 2.5 Specification
Spread spectrum clocking on receive
Asynchronous notification
Hot Plug including asynchronous signal recovery
Link power management
Native command queuing
Staggered spin-up and port multiplier support
Port multiplier support
SATA 1.5 and 3.0 Gb/s operation
Interrupt driven
Power management support
Error handling and diagnostic features
— Far end/near end loopback
— Failed CRC error reporting
— Increased ALIGN insertion rates
Scrambling and CONT override
•
1.12 Enhanced Secured Digital Host Controller (eSDHC)
The enhanced SD host controller (eSDHC) has the following features:
•
Conforms to SD Host Controller Standard Specification, Rev 2.0 with Test Event register support.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
6
Freescale Semiconductor
•
•
Compatible with the MMC System Specification, Rev 4.0
Compatible with the SD Memory Card Specification, Rev 2.0, and supports High Capacity SD
memory cards
•
•
Compatible with the SDIO Card Specification Rev, 1.2
Designed to work with SD Memory, miniSD Memory, SDIO, miniSDIO, SD Combo, MMC,
MMCplus, MMC 4x, and RS-MMC cards
•
•
•
SD bus clock frequency up to 50 MT/s
Supports 1-/4-bit SD and SDIO modes, 1-/4-bit MMC modes
Supports internal DMA capabilities
2 Electrical Characteristics
This section provides the AC and DC electrical specifications and thermal characteristics for the chip. The
device is currently targeted to these specifications. Some of these specifications are independent of the I/O
cell, but are included for a more complete reference. These are not purely I/O buffer design specifications.
2.1
Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1
Absolute Maximum Ratings
This table provides the absolute maximum ratings.
1
Table 2. Absolute Maximum Ratings
Characteristic
Symbol
Max Value
Unit
Note
Core supply voltage
VDD
AVDD
GVDD
–0.3 to 1.1
–0.3 to 1.1
V
V
V
—
—
—
PLL supply voltage (e300 core, eLBC, and system)
DDR1 and DDR2 DRAM I/O voltage
–0.3 to 2.75
–0.3 to 1.98
Three-speed Ethernet I/O, MII management voltage
LVDD[1,2]
OVDD
–0.3 to 3.63
–0.3 to 3.63
V
V
—
—
PCI, DUART, system control and power management, I2C, and
JTAG I/O voltage
Local bus
SerDes
LBVDD
L[1,2]_nVDD
MVIN
–0.3 to 3.63
V
V
V
V
V
V
—
6
–0.3 to 1.1
Input voltage
DDR DRAM signals
–0.3 to (GVDD + 0.3)
–0.3 to (GVDD + 0.3)
–0.3 to (LVDD + 0.3)
–0.3 to (OVDD + 0.3)
2, 4
2, 4
—
DDR DRAM reference
Three-speed Ethernet signals
MVREF
LVIN
PCI, DUART, CLKIN, system control and power
management, I2C, and JTAG signals
OVIN
3, 4, 5
Local Bus
LBIN
–0.3 to (LBVDD + 0.3)
V
—
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
7
1
Table 2. Absolute Maximum Ratings (continued)
Characteristic
Symbol
Max Value
–55 to 150
Unit
Note
Storage temperature range
TSTG
°C
—
Notes:
1. Functional and tested operating conditions are given in Table 3. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MVIN must not exceed GVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
3. Caution: OVIN must not exceed OVDD by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
power-on reset and power-down sequences.
4. (M,O)VIN and MVREF may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
5. Overshoot/undershoot by OVIN on the PCI interface does not comply to the PCI Electrical Specification for 3.3-V operation,
as shown in Figure 2.
6. L[1,2]_nVDD includes SDAVDD_0, XCOREVDD, and XPADVDD power inputs.
2.1.2
Power Supply Voltage Specification
This table provides recommended operating conditions for the device. Note that the values in this table are
the recommended and tested operating conditions. Proper device operation outside of these conditions is
not guaranteed.
Table 3. Recommended Operating Conditions
Recommended
Characteristic
Symbol
Unit
Note
Value
Core supply voltage
up to 667 MT/s
800 MT/s
VDD
1.0 50 mV
1.05 50 mV
1.0 50 mV
1.05 50 mV
V
V
V
V
V
1
1
PLL supply voltage (e300 core, eLBC and
system)
up to 667 MT/s
800 MT/s
AVDD
1, 2
1, 2
1
DDR1 and DDR2 DRAM I/O voltage
GVDD
LVDD[1,2]
OVDD
2.5 V 125 mV
1.8 V 90 mV
Three-speed Ethernet I/O, MII management voltage
3.3 V 165 mV
2.5 V 125 mV
V
V
V
—
1
PCI, local bus, DUART, system control and power management, I2C, and
JTAG I/O voltage
3.3 V 165 mV
Local Bus
LBVDD
1.8 V 90 mV
2.5 V 125 mV
3.3 V 165 mV
—
SerDes
up to 667 MT/s
800 MT/s
L[1,2]_nVDD
1.0 50 mV
V
V
1, 3
1, 3
1.05 V 50 mV
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
8
Table 3. Recommended Operating Conditions (continued)
Recommended
Value
Characteristic
Symbol
Unit
Note
Operating temperature range
commerical
Ta
Tj
Ta=0 (min)—
Tj=125 (max)
°C
—
extended temperature
Ta
Tj
Ta=–40 (min)—
Tj=125 (max)
°C
—
Notes:
1. GVDD, OVDD, AVDD, and VDD must track each other and must vary in the same direction—either in the positive or negative
direction.
2. AVDD is the input to the filter discussed in Section 25.1, “PLL Power Supply Filtering,” and is not necessarily the voltage at
the AVDD pin.
3. L[1,2]_nVDD, SDAVDD_0, XCOREVDD, and XPADVDD power inputs.
This figure shows the undershoot and overshoot voltages at the interfaces of the device.
G/L/O/LBVDD + 20%
G/L/O/LBVDD + 5%
G/L/O/LBVDD
VIH
GND
GND – 0.3 V
VIL
GND – 0.7 V
Not to Exceed 10%
of tinterface1
Note:
1. Note that tinterface refers to the clock period associated with the bus clock interface.
2. Note that with the PCI overshoot allowed (as specified above), the device does
not fully comply with the maximum AC ratings and device protection guideline outlined in
the PCI Rev. 2.3 Specification (Section 4.2.2.3).
Figure 2. Overshoot/Undershoot Voltage for GV /LV /OV /LBV
DD
DD
DD
DD
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
9
2.1.3
Output Driver Characteristics
This table provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Table 4. Output Drive Capability
Driver Type1
Local bus interface utilities signals
Output Impedance (Ω)
Supply Voltage
Notes
45
40
25
LBVDD = 2.5 V, 3.3 V
LBVDD = 1.8 V
OVDD = 3.3 V
—
—
—
2
PCI signals
DDR1 signal
18 full-strength mode
36 half-strength mode
GVDD = 2.5 V
DDR2 signal
18 full-strength mode
36 half-strength mode
GVDD = 1.8 V
2
eTSEC 10/100/1000 signals
45
45
45
LVDD = 2.5 V, 3.3 V
OVDD = 3.3 V
—
—
—
DUART, system control, I2C, JTAG, SPI, and USB
GPIO signals
Note:
OVDD = 3.3 V
1. Specialized SerDes output capabilities are described in the relevant sections of these specifications (such as
PCI Express and SATA)
2. 18 ohms output impedance corresponds to full drive strength setting. 36 ohms output impedance corresponds to half
drive strength. DDR automatic hardware calibration is only available for full drive strength.
2.2
Power Sequencing
The device requires its power rails to be applied in a specific sequence in order to ensure proper device
operation. During the power ramp up, before the power supplies are stable and if the I/O voltages are
supplied before the core voltage, there may be a period of time that all input and output pins will actively
be driven and cause contention and excessive current. To avoid actively driving the I/O pins and to
eliminate excessive current draw, apply the core voltages (V and AV ) before the I/O voltages and
DD
DD
assert PORESET before the power supplies fully ramp up. V and AV must reach 90% of their
DD
DD
nominal value before GV , LV , and OV reach 10% of their value, see the following figure. I/O
DD
DD
DD
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
10
voltage supplies—GV , LV , and OV —do not have any ordering requirements with respect to one
DD
DD
DD
another.
I/O Voltage (GVDD, LVDD, and OVDD)
Core Voltage (VDD, AVDD)
V
0.7 V
90%
t
0
Figure 3. Power-Up Sequencing Example
Note that the SerDes power supply (L[1,2]_nV ) should follow the same timing as the core supply
DD
(V ).
DD
The device does not require the core supply voltage and I/O supply voltages to be powered down in any
particular order.
3 Power Characteristics
The estimated typical power dissipation for the chip device is shown in this table.
1
Table 5. Power Dissipation
Core Frequency CSB/DDR Frequency
Sleep Power
Typical Application Typical Application Max Application
at Tj = 125°C (W) 3 at Tj = 125°C (W) 4
(MT/s)
(MT/s)
at Tj = 65°C (W) 2 at Tj = 65°C (W) 2
333
167
400
266
300
225
333
250
355
266
1.45
1.45
1.45
1.45
1.45
1.45
1.45
1.45
1.45
1.45
1.9
1.8
2.0
1.9
2.0
1.9
2.0
1.9
2.0
2.0
3.2
3.0
3.3
3.1
3.2
3.1
3.3
3.2
3.3
3.2
3.8
3.6
4.0
3.8
3.8
3.7
3.9
3.8
4.0
3.9
333
400
450
500
533
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
11
1
Table 5. Power Dissipation (continued)
Core Frequency CSB/DDR Frequency
Sleep Power
Typical Application Typical Application Max Application
(MT/s)
(MT/s)
at Tj = 65°C (W) 2 at Tj = 65°C (W) 2
at Tj = 125°C (W) 3 at Tj = 125°C (W) 4
400
300
333
266
400
1.45
1.45
1.45
1.45
1.45
2.1
2.0
2.1
2.0
2.5
3.4
3.3
3.3
3.3
3.8
4.1
4.0
4.1
3.9
4.3
600
667
800
Notes:
1. The values do not include I/O supply power (OVDD, LVDD, GVDD) or AVDD. For I/O power values, see Table 6.
2. Typical power is based on a voltage of VDD = 1.0 V for core frequencies ≤ 667 MT/s or VDD = 1.05 V for core frequencies of
800 MT/s, and running a Dhrystone benchmark application.
3. Typical power is based on a voltage of VDD = 1.0 V for core frequencies ≤ 667 MT/s or VDD = 1.05 V for core frequencies of
800 MT/s, and running a Dhrystone benchmark application.
4. Maximum power is based on a voltage of VDD = 1.0 V for core frequencies ≤ 667 MT/s or VDD = 1.05 V for core frequencies
of 800 MT/s, worst case process, and running an artificial smoke test.
This table shows the estimated typical I/O power dissipation for the device.
Table 6. Typical I/O Power Dissipation
GVDD
(1.8 V)
GVDD/LBVDD OVDD LVDD LVDD L[1,2]_nVDD
Interface
Parameter
Unit
Comments
(2.5 V)
(3.3 V) (3.3 V) (2.5 V)
(1.0 V)
200 MT/s data
rate, 32-bit
0.28
0.41
0.31
0.46
0.33
0.48
0.35
0.51
0.38
0.35
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
—
200 MT/s data
rate, 64-bit
0.49
0.4
—
—
—
—
—
—
—
—
W
W
W
W
W
W
W
W
266 MT/s data
rate, 32-bit
266 MT/s data
rate, 64-bit
0.56
0.43
0.6
300 MT/s data
rate, 32-bit
DDR I/O
65%
utilization
2 pair of
clocks
300 MT/s data
rate, 64-bit
333 MT/s data
rate, 32-bit
0.45
0.64
—
333 MT/s data
rate, 64-bit
400 MT/s
data rate,
32-bit
400 MT/s
data rate,
64-bit
0.56
—
—
—
—
—
W
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
12
Table 6. Typical I/O Power Dissipation (continued)
GVDD
(1.8 V)
GVDD/LBVDD OVDD LVDD LVDD L[1,2]_nVDD
Interface
Parameter
Unit
Comments
(2.5 V)
(3.3 V) (3.3 V) (2.5 V)
(1.0 V)
PCI I/O
Load =
30 pf
33 MT/s, 32-bit
66 MT/s, 32-bit
—
—
—
—
0.04
0.07
—
—
—
—
—
—
W
W
—
167 MT/s, 32-bit
133 MT/s, 32-bit
83 MT/s, 32-bit
66 MT/s, 32-bit
50 MT/s, 32-bit
MII or RMII
0.09
0.07
0.05
0.04
0.03
—
0.17
0.14
0.09
0.07
0.06
—
0.29
0.24
0.15
0.13
0.1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
W
W
W
W
W
—
Local Bus
I/O
Load =
25 pf
—
—
—
—
0.02
Multiply by
number of
interfaces used.
eTSEC I/O
Load =
25 pf
USB
(60 MT/s
Clock)
RGMII or RTBI
12 Mbps
—
—
—
—
—
—
—
0.01
0.2
—
—
—
0.05
—
—
—
—
W
W
W
—
—
480 Mbps
—
SerDes
per lane
—
—
—
—
—
—
—
—
—
0.029
—
W
W
—
—
Other I/O
0.01
Note: The values given are for typical, and not worst case, switching.
4 Clock Input Timing
This section provides the clock input DC and AC electrical characteristics for the chip. Note that the
PCI_CLK/PCI_SYNC_IN signal or CLKIN signal is used as the PCI input clock depending on whether
the device is configured as a host or agent device. CLKIN is used when the device is in host mode.
4.1
DC Electrical Characteristics
This table provides the clock input (CLKIN/PCI_CLK) DC timing specifications for the device.
Table 7. CLKIN DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
Note
Input high voltage
Input low voltage
—
—
VIH
VIL
IIN
2.7
–0.3
—
OVDD + 0.3
V
V
1
1
0.4
10
30
CLKIN Input current
PCI_CLK Input current
0 V ≤ VIN ≤ OVDD
μA
μA
—
—
0 V ≤ VIN ≤ 0.5 V or
IIN
—
OVDD – 0.5 V ≤ VIN ≤ OVDD
Note:
1. In PCI agent mode, this specification does not comply with PCI 2.3 Specification.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
13
4.2
AC Electrical Characteristics
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. This table provides the clock input
(CLKIN/PCI_CLK) AC timing specifications for the device.
Table 8. CLKIN AC Timing Specifications
Parameter
Symbol
Min
Typical
Max
Unit
Note
CLKIN/PCI_CLK frequency
CLKIN/PCI_CLK cycle time
CLKIN/PCI_CLK rise and fall time
CLKIN/PCI_CLK duty cycle
CLKIN/PCI_CLK jitter
fCLKIN
tCLKIN
25
15
0.6
40
—
—
—
66.666
40
MT/s
ns
1, 6
—
2
tKH, tKL
tKHK/tCLKIN
—
1.0
—
2.3
ns
60
%
3
—
150
ps
4, 5
Notes:
1. Caution: The system, core and security block must not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for CLKIN/PCI_CLK are measured at 0.4 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter-short term and long term-and is guaranteed by design.
5. The CLKIN/PCI_CLK driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low
to allow cascade-connected PLL-based devices to track CLKIN drivers with the specified jitter.
6. Spread spectrum is allowed up to 1% down-spread on CLKIN/PCI_CLK up to 60 KHz.
4.3
eTSEC Gigabit Reference Clock Timing
This table provides the eTSEC gigabit reference clocks (EC_GTX_CLK125) AC timing specifications.
Table 9. EC_GTX_CLK125 AC Timing Specifications
At recommended operating conditions with LVDD = 2.5 0.125 mV/ 3.3 V 165 mV
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Note
EC_GTX_CLK125 frequency
EC_GTX_CLK125 cycle time
EC_GTX_CLK rise and fall time
tG125
tG125
—
—
—
125
8
—
—
MT/s
ns
—
—
1
t
G125R/tG125F
—
ns
LVDD = 2.5 V
LVDD = 3.3 V
0.75
1.0
EC_GTX_CLK125 duty cycle
1000Base-T for RGMII, RTBI
tG125H/tG125
—
—
%
2
2
47
—
53
EC_GTX_CLK125 jitter
—
150
ps
Notes:
1. Rise and fall times for EC_GTX_CLK125 are measured from 0.5 and 2.0 V for LVDD = 2.5 V and from 0.6 and 2.7 V for
LVDD = 3.3 V.
2. EC_GTX_CLK125 is used to generate the GTX clock for the eTSEC transmitter with 2% degradation. The
EC_GTX_CLK125 duty cycle can be loosened from 47%/53% as long as the PHY device can tolerate the duty cycle
generated by the eTSEC GTX_CLK. See Section 8.2.2, “RGMII and RTBI AC Timing Specifications,” for the duty cycle for
10Base-T and 100Base-T reference clock.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
14
Freescale Semiconductor
5 RESET Initialization
This section describes the DC and AC electrical specifications for the reset initialization timing and
electrical requirements of the chip.
5.1
RESET DC Electrical Characteristics
This table provides the DC electrical characteristics for the RESET pins of the device.
Table 10. RESET Pins DC Electrical Characteristics
Characteristic
Input high voltage
Symbol
Condition
Min
Max
Unit
VIH
VIL
—
—
2.0
–0.3
—
OVDD + 0.3
V
V
Input low voltage
Input current
0.8
30
IIN
—
μA
V
Output high voltage
Output low voltage
Output low voltage
Notes:
VOH
VOL
VOL
IOH = –8.0 mA
IOL = 8.0 mA
IOL = 3.2 mA
2.4
—
—
0.5
0.4
V
—
V
• This table applies for pins PORESET and HRESET. The PORESET is input pin, thus stated output voltages are not relevant.
• HRESET and SRESET are open drain pin, thus VOH is not relevant for these pins.
5.2
RESET AC Electrical Characteristics
This table provides the reset initialization AC timing specifications of the device.
Table 11. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Note
Required assertion time of HRESET to activate reset flow
32
32
—
—
tPCI_SYNC_IN
tCLKIN
1
2
Required assertion time of PORESET with stable clock applied to CLKIN when
the device is in PCI host mode
Required assertion time of PORESET with stable clock applied to PCI_CLK when
the device is in PCI agent mode
32
—
tPCI_SYNC_IN
1
HRESET assertion (output)
512
16
4
—
—
—
tPCI_SYNC_IN
tPCI_SYNC_IN
tCLKIN
1
1
2
HRESET negation to negation (output)
Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],
CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET
when the device is in PCI host mode
Input setup time for POR config signals (CFG_RESET_SOURCE[0:3],
CFG_CLKIN_DIV, and CFG_LBMUX) with respect to negation of PORESET
when the device is in PCI agent mode
4
0
—
—
tPCI_SYNC_IN
1
Input hold time for POR config signals with respect to negation of HRESET
ns
—
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
15
Table 11. RESET Initialization Timing Specifications (continued)
Parameter/Condition
Min
Max
Unit
Note
Time for the device to turn off POR config signals with respect to the assertion of
HRESET
—
4
ns
3
Time for the device to start driving functional output signals multiplexed with the
POR configuration signals with respect to the negation of HRESET
1
—
tPCI_SYNC_IN
1, 3
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the primary
clock is applied to the CLKIN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV. See the
MPC8379E Integrated Host Processor Reference Manual for more details.
2. tCLKIN is the clock period of the input clock applied to CLKIN. It is only valid when the device is in PCI host mode. See the
MPC8379E Integrated Host Processor Reference Manual for more details.
3. POR config signals consists of CFG_RESET_SOURCE[0:3], CFG_LBMUX, and CFG_CLKIN_DIV.
Table 12 provides the PLL lock times.
Table 12. PLL Lock Times
Parameter
Min
Max
Unit
Note
PLL lock times
—
100
μs
—
Note:
• The device guarantees the PLL lock if the clock settings are within spec range. The core clock also depends on the core PLL
ratio. See Section 23, “Clocking,” for more information.
6 DDR1 and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the chip.
Note that DDR1 SDRAM is GV (typ) = 2.5 V and DDR2 SDRAM is GV (typ) = 1.8 V.
DD
DD
6.1
DDR1 and DDR2 SDRAM DC Electrical Characteristics
This table provides the recommended operating conditions for the DDR2 SDRAM component(s) of the
device when GV (typ) = 1.8 V.
DD
Table 13. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V
DD
Parameter
I/O supply voltage
Symbol
Min
Max
Unit
Note
GVDD
MVREF
VTT
1.71
0.49 × GVDD
MVREF – 0.04
MVREF + 0.140
–0.3
1.89
0.51 × GVDD
MVREF + 0.04
GVDD + 0.3
MVREF – 0.140
50
V
V
1
2, 5
3
I/O reference voltage
I/O termination voltage
Input high voltage
V
VIH
V
—
—
4
Input low voltage
VIL
V
Output leakage current
Output high current (VOUT = 1.40 V)
IOZ
–50
μA
mA
IOH
–13.4
—
—
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
16
Table 13. DDR2 SDRAM DC Electrical Characteristics for GV (typ) = 1.8 V (continued)
DD
Parameter
Symbol
Min
Max
Unit
Note
Output low current (VOUT = 0.3 V)
IOL
13.4
—
mA
—
Notes:
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed 2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD
5. See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
.
.
Table 14 provides the DDR2 capacitance when GV (typ) = 1.8 V.
DD
Table 14. DDR2 SDRAM Capacitance for GV (typ) = 1.8 V
DD
Parameter
Symbol
Min
Max
Unit
Note
Input/output capacitance: DQ, DQS, DQS
Delta input/output capacitance: DQ, DQS, DQS
Note:
CIO
6
8
pF
pF
1
1
CDIO
—
0.5
1. This parameter is sampled. GVDD = 1.8 V 0.090 V, f = 1 MT/s, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
This table provides the recommended operating conditions for the DDR SDRAM component(s) when
GV (typ) = 2.5 V.
DD
Table 15. DDR SDRAM DC Electrical Characteristics for GV (typ) = 2.5 V
DD
Parameter
I/O supply voltage
Symbol
Min
Max
Unit
Note
GVDD
MVREF
VTT
2.375
0.49 × GVDD
MVREF – 0.04
MVREF + 0.18
–0.3
2.625
0.51 × GVDD
MVREF + 0.04
GVDD + 0.3
MVREF – 0.18
50
V
V
1
2, 5
3
I/O reference voltage
I/O termination voltage
Input high voltage
V
VIH
V
—
—
4
Input low voltage
VIL
V
Output leakage current
Output high current (VOUT = 1.9 V)
Output low current (VOUT = 0.38 V)
Notes:
IOZ
–50
μA
mA
mA
IOH
–15.2
—
—
—
IOL
15.2
—
1. GVDD is expected to be within 50 mV of the DRAM GVDD at all times.
2. MVREF is expected to be equal to 0.5 × GVDD, and to track GVDD DC variations as measured at the receiver. Peak-to-peak
noise on MVREF may not exceed 2% of the DC value.
3. VTT is not applied directly to the device. It is the supply to which far end signal termination is made and is expected to be
equal to MVREF. This rail should track variations in the DC level of MVREF
4. Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GVDD
5. See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
.
.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
17
Table 16 provides the DDR capacitance when GV (typ) = 2.5 V.
DD
Table 16. DDR SDRAM Capacitance for GV (typ) = 2.5 V
DD
Parameter
Symbol
Min
Max
Unit
Note
Input/output capacitance: DQ, DQS
Delta input/output capacitance: DQ, DQS
Note:
CIO
6
8
pF
pF
1
1
CDIO
—
0.5
1. This parameter is sampled. GVDD = 2.5 V 0.125 V, f = 1 MT/s, TA = 25°C, VOUT = GVDD/2, VOUT (peak-to-peak) = 0.2 V.
This table provides the current draw characteristics for MV
.
REF
Table 17. Current Draw Characteristics for MV
REF
Parameter
Symbol
Min
Typ
Max
Unit
Note
Current draw for MVREF
IMVREF
μA
1, 2
DDR1
DDR2
—
—
250
150
600
400
Note:
1. The voltage regulator for MVREF must be able to supply up to the stated maximum current.
2. This current is divided equally between MVREF1 and MVREF2, where half the current flows through each pin.
6.2
DDR1 and DDR2 SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1
DDR1 and DDR2 SDRAM Input AC Timing Specifications
This table provides the input AC timing specifications for the DDR2 SDRAM when GVDD(typ) = 1.8 V.
Table 18. DDR2 SDRAM Input AC Timing Specifications for 1.8-V Interface
Parameter
Symbol
Min
Max
Unit
AC input low voltage
AC input high voltage
VIL
—
MVREF – 0.25
—
V
V
VIH
MVREF + 0.25
This table provides the input AC timing specifications for the DDR1 SDRAM when GV (typ) = 2.5 V.
DD
Table 19. DDR1 SDRAM Input AC Timing Specifications for 2.5-V Interface
Parameter
Symbol
Min
Max
Unit
AC input low voltage
AC input high voltage
VIL
—
MVREF – 0.31
—
V
V
VIH
MVREF + 0.31
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
18
This table provides the input AC timing specifications for the DDR1 and DDR2 SDRAM interface.
Table 20. DDR1 and DDR2 SDRAM Input AC Timing Specifications
Parameter
Symbol
Min
Max
Unit
Note
Controller skew for MDQS-MDQ/MECC/MDM
400 MT/s data rate
tCISKEW
ps
1, 2
3
—
—
–500
–750
–750
500
750
750
333 MT/s data rate
266 MT/s data rate
Note:
1. tCISKEW represents the total amount of skew consumed by the controller between MDQSn and any corresponding bit that
will be captured with MDQSn. This should be subtracted from the total timing budget.
2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called tDISKEW. This can be
determined by the following equation: tDISKEW = [T/4 – ꢀtCISKEWꢀ] where T is the MCK clock period and ꢀtCISKEWꢀ is the
absolute value of tCISKEW
.
3. This specification applies only to DDR2 interface.
6.2.2
DDR1 and DDR2 SDRAM Output AC Timing Specifications
This table shows the DDR1 and DDR2 SDRAM output AC timing specifications.
Table 21. DDR1 and DDR2 SDRAM Output AC Timing Specifications
Parameter
Symbol1
Min
Max
Unit
Note
MCKn cycle time, MCKn/MCKn crossing
tMCK
5
12
ns
ns
2
ADDR/CMD output setup with respect to MCK
400 MT/s data rate
tDDKHAS
3, 7
1.95
2.40
3.15
4.20
—
—
—
—
333 MT/s data rate
266 MT/s data rate
200 MT/s data rate
ADDR/CMD output hold with respect to MCK
400 MT/s data rate
tDDKHAX
tDDKHCS
tDDKHCX
tDDKHMH
ns
ns
ns
ns
3, 7
3, 7
3, 7
4, 8
1.95
2.40
3.15
4.20
—
—
—
—
333 MT/s data rate
266 MT/s data rate
200 MT/s data rate
MCSn output setup with respect to MCK
400 MT/s data rate
1.95
2.40
3.15
4.20
—
—
—
—
333 MT/s data rate
266 MT/s data rate
200 MT/s data rate
MCSn output hold with respect to MCK
400 MT/s data rate
1.95
2.40
3.15
4.20
—
—
—
—
333 MT/s data rate
266 MT/s data rate
200 MT/s data rate
MCK to MDQS skew
–0.6
0.6
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
19
Table 21. DDR1 and DDR2 SDRAM Output AC Timing Specifications (continued)
Parameter
Symbol1
Min
Max
Unit
Note
MDQ//MDM output setup with respect to MDQS
400 MT/s data rate
tDDKHDS,
tDDKLDS
ps
5, 8
550
800
1100
1200
—
—
—
—
333 MT/s data rate
266 MT/s data rate
200 MT/s data rate
MDQ//MDM output hold with respect to MDQS
400 MT/s data rate
tDDKHDX,
tDDKLDX
ps
5, 8
700
800
1100
1200
—
—
—
—
333 MT/s data rate
266 MT/s data rate
200 MT/s data rate
MDQS preamble start
MDQS epilogue end
Notes:
tDDKHMP
tDDKHME
–0.5 × tMCK –0.6
–0.6
–0.5 × tMCK + 0.6
ns
ns
6, 8
6, 8
0.6
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. Output hold time can be read as DDR timing
(DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (AX or DX). For example,
tDDKHAS symbolizes DDR timing (DD) for the time tMCK memory clock reference (K) goes from the high (H) state until
outputs (A) are setup (S) or output valid time. Also, tDDKLDX symbolizes DDR timing (DD) for the time tMCK memory clock
reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2. All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V.
3. ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK, MCS, MODT, and MDQ/MDM/MDQS.
4. Note that tDDKHMH follows the symbol conventions described in Note 1. For example, tDDKHMH describes the DDR timing
(DD) from the rising edge of the MCK[n] clock (KH) until the MDQS signal is valid (MH). tDDKHMH can be modified through
control of the DQSS override bits in the TIMING_CFG_2 register. This will typically be set to the same delay as the clock
adjust in the CLK_CNTL register. The timing parameters listed in the table assume that these 2 parameters have been set
to the same adjustment value. See the MPC8379E PowerQUICC II Pro Host Processor Reference Manual for a description
and understanding of the timing modifications enabled by use of these bits.
5. Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data MDQ, ECC, or
data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the microprocessor.
6. All outputs are referenced to the rising edge of MCKn at the pins of the microprocessor. Note that tDDKHMP follows the
symbol conventions described in Note 1.
7. Clock Control register is set to adjust the memory clocks by 1/2 the applied cycle.
8. See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
The minimum frequency for DDR2 is 250 MT/s data rate (125 MT/s clock), 167 MT/s data rate (83 MT/s
clock) for DDR1. This figure shows the DDR1 and DDR2 SDRAM output timing for the MCK to MDQS
skew measurement (t
).
DDKHMH
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
20
MCK[n]
MCK[n]
tMCK
tDDKHMHmax) = 0.6 ns
MDQS
MDQS
tDDKHMH(min) = –0.6 ns
Figure 4. DDR Timing Diagram for t
DDKHMH
This figure shows the DDR1 and DDR2 SDRAM output timing diagram.
MCK[n]
MCK[n]
tMCK
tDDKHAS ,tDDKHCS
tDDKHAX ,tDDKHCX
ADDR/CMD
Write A0
tDDKHMP
NOOP
tDDKHMH
MDQS[n]
MDQ[x]
tDDKHDS
tDDKHME
tDDKLDS
D0
D1
tDDKLDX
tDDKHDX
Figure 5. DDR1 and DDR2 SDRAM Output Timing Diagram
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
21
This figure provides AC test load for the DDR bus.
GVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
Figure 6. DDR AC Test Load
7 DUART
This section describes the DC and AC electrical specifications for the DUART interface of the chip.
7.1
DUART DC Electrical Characteristics
This table provides the DC electrical characteristics for the DUART interface of the device.
Table 22. DUART DC Electrical Characteristics
Parameter
High-level input voltage
Symbol
Min
Max
Unit
VIH
VIL
2
OVDD + 0.3
V
V
V
Low-level input voltage OVDD
–0.3
0.8
—
High-level output voltage,
VOH
OVDD – 0.2
IOH = –100 μA
Low-level output voltage,
IOL = 100 μA
VOL
—
0.2
30
V
Input current,
IIN
—
μA
(0 V ≤VIN ≤ OVDD
)
Note: The symbol VIN, in this case, represents the OVIN symbol referenced in Table 2.
7.2
DUART AC Electrical Specifications
this table provides the AC timing parameters for the DUART interface of the device.
Table 23. DUART AC Timing Specifications
Parameter
Value
Unit
Note
Minimum baud rate
Maximum baud rate
Oversample rate
Notes:
256
> 1,000,000
16
baud
baud
—
—
1
2
1. Actual attainable baud rate will be limited by the latency of interrupt processing.
2. The middle of a start bit is detected as the 8th sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are
sampled each 16th sample.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
22
Freescale Semiconductor
8 Ethernet: Enhanced Three-Speed Ethernet (eTSEC)
This section provides the AC and DC electrical characteristics for the enhanced three-speed Ethernet
controller.
8.1
Enhanced Three-Speed Ethernet Controller (eTSEC)
(10/100/1000 Mbps)—MII/RGMII/RTBI/RMII DC Electrical
Characteristics
The electrical characteristics specified here apply to media independent interface (MII), reduced gigabit
media independent interface (RGMII), reduced ten-bit interface (RTBI), reduced media independent
interface (RMII) signals, management data input/output (MDIO) and management data clock (MDC).
The MII and RMII interfaces are defined for 3.3 V, while the RGMII and RTBI interfaces can be operated
at 2.5 V. The RGMII and RTBI interfaces follow the Reduced Gigabit Media-Independent Interface
(RGMII) Specification Version 1.3. The RMII interface follows the RMII Consortium RMII Specification
Version 1.2.
8.1.1
MII, RMII, RGMII, and RTBI DC Electrical Characteristics
MII and RMII drivers and receivers comply with the DC parametric attributes specified in Table 24 and
Table 25. The RGMII and RTBI signals in Table 25 are based on a 2.5 V CMOS interface voltage as
defined by JEDEC EIA/JESD8-5.
Table 24. MII and RMII DC Electrical Characteristics
Parameter
Supply voltage 3.3 V
Symbol
Min
Max
Unit
Note
LVDD1
LVDD2
3.13
3.47
V
1
Output high voltage
(LVDD1/LVDD2 = Min, IOH = –4.0 mA)
VOH
2.40
LVDD1/LVDD2 + 0.3
0.50
V
V
—
—
Output low voltage
VOL
GND
(LVDD1/LVDD2 = Min, IOL = 4.0 mA)
Input high voltage
Input low voltage
Input high current
VIH
VIL
IIH
2.0
–0.3
—
LVDD1/LVDD2 + 0.3
V
V
—
—
1
0.90
30
μA
(VIN = LVDD1, VIN = LVDD2
)
Input low current
(VIN = GND)
IIL
–600
—
μA
—
Notes:
1. LVDD1 supports eTSEC 1. LVDD2 supports eTSEC 2.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
23
Table 25. RGMII and RTBI DC Electrical Characteristics
Parameter
Supply voltage 2.5 V
Symbol
Min
Max
Unit
Note
LVDD1
LVDD2
2.37
2.63
V
1
Output high voltage
(LVDD1/LVDD2 = Min, IOH = –1.0 mA)
VOH
2.00
LVDD1/LVDD2 + 0.3
0.40
V
V
—
—
Output low voltage
VOL
GND – 0.3
(LVDD1/LVDD2 = Min, IOL = 1.0 mA)
Input high voltage
Input low voltage
Input high current
VIH
VIL
IIH
1.7
–0.3
—
LVDD1/LVDD2 + 0.3
V
V
—
—
1
0.70
–20
μA
(VIN = LVDD1, VIN = LVDD2
)
Input low current
(VIN = GND)
IIL
–20
—
μA
—
Notes:
1. LVDD1 supports eTSEC 1. LVDD2 supports eTSEC 2.
8.2
MII, RGMII, RMII, and RTBI AC Timing Specifications
The AC timing specifications for MII, RGMII, RMII, and RTBI are presented in this section.
8.2.1
MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
8.2.1.1
MII Transmit AC Timing Specifications
This table provides the MII transmit AC timing specifications.
Table 26. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%.
Parameter
Symbol1
Min
Typical
Max
Unit
TX_CLK clock period 10 Mbps
TX_CLK clock period 100 Mbps
TX_CLK duty cycle
tMTX
tMTX
MTXH/tMTX
tMTKHDX
—
—
35
1
400
40
—
5
—
—
65
15
ns
ns
%
t
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
ns
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
24
Table 26. MII Transmit AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 3.3 V 5%.
Parameter
Symbol1
Min
Typical
Max
Unit
TX_CLK data clock rise (20%–80%)
TX_CLK data clock fall (80%–20%)
Note:
tMTXR
tMTXF
1.0
1.0
—
—
4.0
4.0
ns
ns
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII
transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
This figure shows the MII transmit AC timing diagram.
tMTXR
tMTX
TX_CLK
tMTXF
tMTXH
TXD[3:0]
TX_EN
TX_ER
tMTKHDX
Figure 7. MII Transmit AC Timing Diagram
8.2.1.2
MII Receive AC Timing Specifications
This table provides the MII receive AC timing specifications.
Table 27. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%.
Parameter
Symbol1
Min
Typical
Max
Unit
Input low voltage
VIL
VIH
—
1.9
—
—
—
0.7
—
—
—
65
—
—
V
Input high voltage
V
RX_CLK clock period 10 Mbps
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
tMRX
400
40
—
ns
ns
%
ns
ns
tMRX
—
tMRXH/tMRX
tMRDVKH
tMRDXKH
35
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
10.0
10.0
—
—
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
25
Table 27. MII Receive AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 3.3 V 5%.
Parameter
Symbol1
Min
Typical
Max
Unit
RX_CLK clock rise time (20%–80%)
RX_CLK clock fall time (80%–20%)
Note:
tMRXR
tMRXF
1.0
1.0
—
—
4.0
4.0
ns
ns
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH
symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the
t
MRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with
respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state
or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock
of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall).
This figure provides the AC test load for eTSEC.
Output
LVDD/2
Z0 = 50 Ω
RL = 50 Ω
Figure 8. eTSEC AC Test Load
This figure shows the MII receive AC timing diagram.
tMRX
tMRXR
RX_CLK
tMRXF
Valid Data
tMRXH
RXD[3:0]
RX_DV
RX_ER
tMRDVKH
tMRDXKL
Figure 9. MII Receive AC Timing Diagram
8.2.2
RGMII and RTBI AC Timing Specifications
This table presents the RGMII and RTBI AC timing specifications.
Table 28. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V 5%.
Parameter
Symbol1
Min
Typical
Max
Unit
Note
Data to clock output skew (at transmitter)
Data to clock input skew (at receiver)
Clock period
tSKRGT
tSKRGT
tRGT
–600
1.0
0
600
2.8
8.8
ps
ns
ns
—
2
—
7.2
8.0
3
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
26
Table 28. RGMII and RTBI AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 2.5 V 5%.
Parameter
Symbol1
Min
Typical
Max
Unit
Note
Duty cycle for 1000Base-T
tRGTH/tRGT
tRGTH/tRGT
tRGTR
45
40
—
—
—
47
50
50
—
55
60
%
%
4
3, 4
—
—
5
Duty cycle for 10BASE-T and 100BASE-TX
Rise time (20%–80%)
0.75
0.75
—
ns
ns
ns
%
Fall time (20%–80%)
tRGTF
—
EC_GTX_CLK125 reference clock period
tG12
8.0
—
EC_GTX_CLK125 reference clock duty cycle
tG125H/tG125
53
—
measured at 0.5 × LVDD1
Notes:
1. Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to represent
RGMII and RTBI timing. Note also that the notation for rise (R) and fall (F) times follows the clock symbol that is being
represented. For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2. This implies that PC board design will require clocks to be routed such that an additional trace delay of greater than 1.5 ns
will be added to the associated clock signal.
3. For 10 and 100 Mbps, tRGT scales to 400 ns 40 ns and 40 ns 4 ns, respectively.
4. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains as
long as the minimum duty cycle is not violated and stretching occurs for no more than three tRGT of the lowest speed
transitioned between
5. This symbol represents the external EC_GTX_CLK125 and does not follow the original signal naming convention.
This figure provides the AC test load for eTSEC.
Output
LVDD/2
Z0 = 50 Ω
RL = 50 Ω
Figure 10. eTSEC AC Test Load
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
27
This figure shows the RGMII and RTBI AC timing and multiplexing diagrams.
tRGT
tRGTH
GTX_CLK
(At Transmitter)
tSKRGT_TX
TXD[8:5][3:0]
TXD[7:4][3:0]
TXD[8:5]
TXD[7:4]
TXD[3:0]
TXD[9]
TXERR
TXD[4]
TXEN
TX_CTL
tSKRGT_RX
TX_CLK
(At PHY)
RXD[8:5][3:0]
RXD[7:4][3:0]
RXD[8:5]
RXD[7:4]
RXD[3:0]
tSKRGT_TX
RXD[9]
RXERR
RXD[4]
RXDV
RX_CTL
tSKRGT_RX
RX_CLK
(At PHY)
Figure 11. RGMII and RTBI AC Timing and Multiplexing Diagrams
8.2.3
RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
8.2.3.1
RMII Transmit AC Timing Specifications
This table shows the RMII transmit AC timing specifications.
Table 29. RMII Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%.
Parameter
Symbol1
Min
Typical
Max
Unit
REF_CLK clock period
tRMT
tRMTH
tRMTJ
tRMTR
15.0
35
20.0
50
25.0
65
ns
%
REF_CLK duty cycle
REF_CLK peak-to-peak jitter
Rise time REF_CLK (20%–80%)
—
—
250
2.0
ps
ns
1.0
—
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
28
Table 29. RMII Transmit AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 3.3 V 5%.
Parameter
Symbol1
Min
Typical
Max
Unit
Fall time REF_CLK (80%–20%)
REF_CLK to RMII data TXD[1:0], TX_EN delay
Note:
tRMTF
1.0
2.0
—
—
2.0
ns
ns
tRMTDX
10.0
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state)
for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMTKHDX symbolizes MII
transmit timing (MT) for the time tMTX clock reference (K) going high (H) until data outputs (D) are invalid (X). Note that, in
general, the clock reference symbol representation is based on two to three letters representing the clock of a particular
functional. For example, the subscript of tMTX represents the MII(M) transmit (TX) clock. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
This figure shows the RMII transmit AC timing diagram.
tRMTR
tRMT
REF_CLK
tRMTF
tRMTH
TXD[1:0]
TX_EN
TX_ER
tRMTDX
Figure 12. RMII Transmit AC Timing Diagram
8.2.3.2
RMII Receive AC Timing Specifications
This table shows the RMII receive AC timing specifications.
Table 30. RMII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%.
Parameter/Condition
Symbol1
Min
Typical
Max
Unit
Input low voltage at 3.3 LVDD
Input high voltage at 3.3 LVDD
REF_CLK clock period
VIL
—
2.0
15.0
35
—
—
0.8
—
V
VIH
V
tRMR
tRMRH
tRMRJ
tRMRR
tRMRF
20.0
50
—
25.0
65
ns
%
ps
ns
ns
REF_CLK duty cycle
REF_CLK peak-to-peak jitter
Rise time REF_CLK (20%–80%)
Fall time REF_CLK (80%–20%)
—
250
2.0
2.0
1.0
1.0
—
—
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
29
Table 30. RMII Receive AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 3.3 V 5%.
Parameter/Condition
Symbol1
Min
Typical
Max
Unit
RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge
RXD[1:0], CRS_DV, RX_ER hold time to REF_CLK rising edge
Note:
tRMRDV
tRMRDX
4.0
2.0
—
—
—
—
ns
ns
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMRDVKH
symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to the
tMRX clock reference (K) going to the high (H) state or setup time. Also, tMRDXKL symbolizes MII receive timing (GR) with
respect to the time data input signals (D) went invalid (X) relative to the tMRX clock reference (K) going to the low (L) state
or hold time. Note that, in general, the clock reference symbol representation is based on three letters representing the clock
of a particular functional. For example, the subscript of tMRX represents the MII (M) receive (RX) clock. For rise and fall times,
the latter convention is used with the appropriate letter: R (rise) or F (fall).
This figure provides the AC test load for eTSEC.
Output
LVDD/2
Z0 = 50 Ω
RL = 50 Ω
Figure 13. eTSEC AC Test Load
This figure shows the RMII receive AC timing diagram.
tRMR
tRMRR
REF_CLK
tRMRF
Valid Data
tRMRH
RXD[1:0]
CRS_DV
RX_ER
tRMRDV
tRMRDX
Figure 14. RMII Receive AC Timing Diagram
8.3
Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock).
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
30
Freescale Semiconductor
This figure provides the AC test load for eTSEC.
LVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
Figure 15. eTSEC AC Test Load
8.3.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 2.5 V or 3.3 V. The DC electrical
characteristics for MDIO and MDC are provided in Table 31 and Table 32.
Table 31. MII Management DC Electrical Characteristics When Powered at 2.5 V
Parameter
Conditions
Symbol
Min
Max
Unit
Supply voltage (2.5 V)
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
—
LVDD1
VOH
VOL
VIH
VIL
2.37
2.00
2.63
V
V
IOH = –1.0 mA
LVDD1 = Min
LVDD1 + 0.3
IOL = 1.0 mA
LVDD1 = Min
LVDD1 = Min
LVDD1 = Min
GND – 0.3
1.7
0.40
—
V
—
—
V
–0.3
0.70
20
V
VIN = LVDD1
VIN = LVDD1
IIH
—
μA
μA
IIL
–15
—
Table 32. MII Management DC Electrical Characteristics When Powered at 3.3 V
Parameter
Conditions
Symbol
Min
Max
Unit
Supply voltage (3.3 V)
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
—
LVDD1
VOH
VOL
VIH
VIL
3.135
2.10
GND
2.00
—
3.465
V
V
IOH = –1.0 mA
IOL = 1.0 mA
LVDD1 = Min
LVDD1 = Min
LVDD1 + 0.3
0.50
—
V
—
—
V
0.80
30
V
LVDD1 = Max
LVDD1 = Max
VIN 1 = 2.1 V
VIN = 0.5 V
IIH
—
μA
μA
IIL
–600
—
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
31
8.3.2
MII Management AC Electrical Specifications
This table provides the MII management AC timing specifications.
Table 33. MII Management AC Timing Specifications
Parameter
MDC frequency
Symbol1
Min
Typical
Max
Unit
Note
fMDC
tMDC
—
2.5
—
—
—
—
—
—
—
—
—
MT/s
ns
2
—
—
4
MDC period
80
400
MDC clock pulse width high
MDC to MDIO valid
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time (20%–80%)
MDC fall time (80%–20%)
Notes:
tMDCH
32
—
ns
tMDKHDV
tMDKHDX
tMDDVKH
tMDDXKH
tMDCR
2 × (tplb_clk × 8)
—
ns
10
5
2 × (tplb_clk × 8)
ns
2, 4
—
—
3
—
—
10
10
ns
0
ns
—
—
ns
tMDCF
ns
3
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX
symbolizes management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are
invalid (X) or data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input
signals (D) reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For
rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the system clock speed.
3. Guaranteed by design.
4. tplb_clk is the platform (CSB) clock divided according to the SCCR[TSEC1CM].
This figure shows the MII management AC timing diagram.
tMDCR
tMDC
MDC
tMDCF
tMDCH
MDIO
(Input)
tMDDVKH
tMDDXKH
MDIO
(Output)
tMDKHDX
Figure 16. MII Management Interface Timing Diagram
9 USB
This section provides the AC and DC electrical characteristics for the USB dual-role controllers.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
32
Freescale Semiconductor
9.1
USB DC Electrical Characteristics
This table provides the DC electrical characteristics for the ULPI interface at recommended
OV = 3.3 V ± 165 mV.
DD
Table 34. USB DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Note
High-level input voltage
Low-level input voltage
Input current
VIH
VIL
2
–0.3
OVDD + 0.3
V
V
1
1
0.8
30
IIN
—
μA
V
2
High-level output voltage, IOH = –100 μA
Low-level output voltage, IOL = 100 μA
Notes:
VOH
VOL
OVDD – 0.2
—
—
—
—
0.2
V
1. The minimum VIL and maximum VIH values are based on the respective minimum and maximum OVIN values found in
Table 3.
2. The symbol OVIN represents the input voltage of the supply and is referenced in Table 3.
9.2
USB AC Electrical Specifications
This table describes the general timing parameters of the USB interface of the device.
Table 35. USB General Timing Parameters (ULPI Mode Only)
Parameter
Symbol 1
Min
Max
Unit
Note
USB clock cycle time
tUSCK
tUSIVKH
tUSIXKH
tUSKHOV
tUSKHOX
15
4
—
—
—
7
ns
ns
ns
ns
ns
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
2, 3, 4, 5
Input setup to USB clock—all inputs
Input hold to USB clock—all inputs
USB clock to output valid—all outputs
Output hold from USB clock—all outputs
Notes:
1
—
2
—
1. The symbols for timing specifications follow the pattern of t(First two letters of functional block)(signal)(state) (reference)(state) for inputs
and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing (US)
for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX symbolizes
USB timing (US) for the USB clock reference (K) to go high (H) with respect to the output (O) going invalid (X) or output hold
time.
2. All timings are in reference to the USB clock, USBDR_CLK.
3. All signals are measured from OVDD/2 of the rising edge of the USB clock to 0.5 × OVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5. For active/float timing measurements, the high impedance or off state is defined to be when the total current delivered
through the component pin is less than or equal to that of the leakage current specification.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
33
These two figures provide the AC test load and signals for the USB, respectively.
OVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
Figure 17. USB AC Test Load
USBDR_CLK
tUSIXKH
tUSIVKH
Input Signals
tUSKHOX
tUSKHOV
Output Signals
Figure 18. USB Interface Timing Diagram
10 Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the chip.
10.1 Local Bus DC Electrical Characteristics
This tables provide the DC electrical characteristics for the local bus interface.
Table 36. Local Bus DC Electrical Characteristics (LBV = 3.3 V)
DD
At recommended operating conditions with LBVDD = 3.3 V.
Parameter
Conditions
Symbol
Min
Max
Unit
Supply voltage 3.3 V
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
—
LBVDD
VOH
VOL
VIH
3.135
2.40
—
3.465
V
V
IOH = –4.0 mA
LBVDD = Min
—
0.50
IOL = 4.0 mA
LBVDD = Min
V
—
—
—
—
2.0
LBVDD + 0.3
0.90
V
VIL
–0.3
—
V
VIN 1 = LBVDD
VIN 1 = GND
IIH
30
μA
μA
IIL
–30
—
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
34
Table 37. Local Bus DC Electrical Characteristics (LBV = 2.5 V)
DD
At recommended operating conditions with LBVDD = 2.5 V.
Parameter
Conditions
Symbol
Min
Max
Unit
Supply voltage 2.5 V
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
—
LBVDD
VOH
VOL
VIH
2.37
2.00
—
2.73
V
V
IOH = –1.0 mA
LBVDD = Min
LBVDD = Min
LBVDD = Min
LBVDD = Min
—
0.40
IOL = 1.0 mA
V
—
—
1.7
LBVDD + 0.3
0.70
V
VIL
–0.3
—
V
VIN 1 = LBVDD
VIN 1 = GND
IIH
20
μA
μA
IIL
–20
—
Table 38. Local Bus DC Electrical Characteristics (LBV = 1.8 V)
DD
At recommended operating conditions with LBVDD = 1.8 V.
Parameter
Conditions
Symbol
Min
Max
Unit
Supply voltage 1.8 V
Output high voltage
Output low voltage
Input high voltage
Input low voltage
Input high current
Input low current
—
LBVDD
VOH
VOL
VIH
1.71
1.89
V
V
IOH = –1.0 mA
LBVDD = Min
LBVDD = Min
LBVDD = Min
LBVDD = Min
LBVDD – 0.45
—
0.45
IOL = 1.0 mA
—
0.65 × LBVDD
–0.3
V
—
—
LBVDD + 0.3
0.35 × LBVDD
10
V
VIL
V
VIN 1 = LBVDD
VIN 1 = GND
IIH
—
μA
μA
IIL
–10
—
10.2 Local Bus AC Electrical Specifications
This table describes the general timing parameters of the local bus interface of the device when in PLL
enable mode.
Table 39. Local Bus General Timing Parameters—PLL Enable Mode
Parameter
Symbol1
Min
Max
Unit
Note
Local bus cycle time
tLBK
7.5
1.5
1.0
1.5
1.5
3
15
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
3, 4
3, 4
3, 4
5
Input setup to local bus clock (except LUPWAIT/LGTA)
Input hold from local bus clock
tLBIVKH
tLBIXKH
—
LUPWAIT/LGTA input setup to local bus clock
LALE output fall to LAD output transition (LATCH hold time)
LALE output fall to LAD output transition (LATCH hold time)
LALE output fall to LAD output transition (LATCH hold time)
Local bus clock to LALE rise
tLBIVKH1
tLBOTOT1
tLBOTOT2
tLBOTOT3
tLBKHLR
tLBKHOV
—
—
—
6
2.5
—
—
7
4.5
4.5
—
3
Local bus clock to output valid (except LALE)
—
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
35
Table 39. Local Bus General Timing Parameters—PLL Enable Mode (continued)
Parameter
Symbol1
Min
Max
Unit
Note
Local bus clock to output high impedance for LAD/LDP
Output hold from local bus clock for LAD/LDP
Notes:
tLBKHOZ
tLBKHOX
—
1
3.8
—
ns
ns
3, 8
3
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes
high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go
high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to rising edge of LSYNC_IN at LBVDD/2 and the 0.5 × LBVDD of the signal in question.
3. All signals are measured from LBVDD/2 of the rising/falling edge of LSYNC_IN to 0.5 × LBVDD of the signal in question.
4. Input timings are measured at the pin.
5. tLBOTOT1 should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on
LAD output pins.
6. tLBOTOT2 should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load
on LAD output pins.
7. tLBOTOT3 should be used when LBCR[AHD] is not set and the load on LALE output pin equals to the load on LAD output pins.
8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
36
Freescale Semiconductor
This table describes the general timing parameters of the local bus interface of the device when in PLL
bypass mode.
Table 40. Local Bus General Timing Parameters—PLL Bypass Mode
Parameter
Symbol1
Min
Max
Unit
Note
Local bus cycle time
tLBK
15
7.0
1.0
1.5
3.0
2.5
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
3, 4
3, 4
5
Input setup to local bus clock
tLBIVKH
Input hold from local bus clock
tLBIXKH
—
LALE output fall to LAD output transition (LATCH hold time)
LALE output fall to LAD output transition (LATCH hold time)
LALE output fall to LAD output transition (LATCH hold time)
Local bus clock to LALE rise
tLBOTOT1
tLBOTOT2
tLBOTOT3
tLBKHLR
tLBKHOV
tLBKHOZ
—
—
6
—
7
4.5
3.0
4.0
—
3
Local bus clock to output valid
—
Local bus clock to output high impedance for LAD/LDP
Notes:
—
3, 8
1. The symbols used for timing specifications herein follow the pattern of t(First two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(First two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1
symbolizes local bus timing (LB) for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes
high (H), in this case for clock one(1). Also, tLBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go
high (H), with respect to the output (O) going invalid (X) or output hold time.
2. All timings are in reference to falling edge of LCLK0 (for all outputs and for LGTA and LUPWAIT inputs) or rising edge of
LCLK0 (for all other inputs).
3. All signals are measured from LBVDD/2 of the rising/falling edge of LCLK0 to 0.5 × LBVDD of the signal in question for 3.3-V
signaling levels.
4. Input timings are measured at the pin.
5. tLBOTOT1 should be used when LBCR[AHD] is set and the load on LALE output pin is at least 10pF less than the load on
LAD output pins.
6. tLBOTOT2 should be used when LBCR[AHD] is not set and the load on LALE output pin is at least 10pF less than the load
on LAD output pins.
7. tLBOTOT3 should be used when LBCR[AHD] is not set and the load on LALE output pin equals to the load on LAD output pins.
8. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
This figure provides the AC test load for the local bus.
OVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
Figure 19. Local Bus AC Test Load
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
37
This figures show the local bus signals.
LSYNC_IN
tLBIXKH
tLBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
tLBIXKH
tLBIVKH
Input Signal:
LGTA
Output Signals:
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
tLBKHOX
tLBKHOV
LA[27:31]/LBCTL/LBCKE/LOE
tLBKHOZ
tLBKHOX
tLBKHOV
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
tLBKHOZ
tLBKHOX
tLBKHOV
Output (Address) Signal:
LAD[0:31]
tLBOTOT
tLBKHLR
LALE
Figure 20. Local Bus Signals, Non-special Signals Only (PLL Enable Mode)
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
38
LCLK[n]
tLBIXKH
tLBIVKH
Input Signals:
LAD[0:31]
tLBIXKH
tLBIVKH
Input Signal:
LGTA
Output Signals:
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
tLBKHOV
LA[27:31]/LBCTL/LBCKE/LOE
tLBKHOZ
tLBKHOV
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
tLBKHOZ
tLBKHOV
Output (Address) Signal:
LAD[0:31]
tLBOTOT
tLBKHLR
LALE
Figure 21. Local Bus Signals, Non-special Signals Only (PLL Bypass Mode)
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
39
LSYNC_IN
T1
T3
tLBKHOV
tLBKHOX
GPCM Mode Output Signals:
LCS[0:7]/LWE[0:3]
tLBIXKH
tLBIVKH
tLBIVKH
tLBKHOX
UPM Mode Input Signal:
LUPWAIT
tLBIXKH
Input Signals:
LAD[0:31]/LDP[0:3]
tLBKHOV
UPM Mode Output Signals:
LCS[0:7]/LBS[0:1]/LGPL[0:5]
tLBKHOZ
tLBKHOX
tLBKHOV
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
tLBKHOZ
tLBKHOX
tLBKHOV
Output (Address) Signal:
LAD[0:31]
Figure 22. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (PLL Enable Mode)
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
40
LCLK
T1
T3
tLBKHOZ
tLBKHOV
GPCM Mode Output Signals:
LCS[0:7]/LWE[0:3]
tLBIXKH
tLBIVKH
UPM Mode Input Signal:
LUPWAIT
tLBIXKH
tLBIVKH
Input Signals:
LAD[0:31]/LDP[0:3]
tLBKHOV
UPM Mode Output Signals:
LCS[0:7]/LBS[0:1]/LGPL[0:5]
tLBKHOZ
tLBKHOV
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
tLBKHOZ
tLBKHOV
Output (Address) Signal:
LAD[0:31]
Figure 23. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (PLL Bypass Mode)
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
41
LSYNC_IN
T1
T2
T3
T4
tLBKHOZ
tLBKHOV
GPCM Mode Output Signals:
LCS[0:7]/LWE[0:3]
tLBIXKH
tLBIVKH
UPM Mode Input Signal:
LUPWAIT
tLBIXKH
tLBIVKH
Input Signals:
LAD[0:31]
tLBKHOX
tLBKHOV
UPM Mode Output Signals:
LCS[0:7]/LBS[0:1]/LGPL[0:5]
tLBKHOZ
tLBKHOX
tLBKHOV
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
tLBKHOZ
tLBKHOX
tLBKHOV
Output (Address) Signal:
LAD[0:31]
Figure 24. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (PLL Enable Mode)
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
42
LCLK
T1
T2
T3
T4
tLBKHOZ
tLBKHOV
GPCM Mode Output Signals:
LCS[0:7]/LWE[0:3]
tLBIXKH
tLBIVKH
UPM Mode Input Signal:
LUPWAIT
tLBIXKH
tLBIVKH
Input Signals:
LAD[0:31]
tLBKHOV
UPM Mode Output Signals:
LCS[0:7]/LBS[0:1]/LGPL[0:5]
tLBKHOZ
tLBKHOV
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
tLBKHOZ
tLBKHOV
Output (Address) Signal:
LAD[0:31]
Figure 25. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (PLL Bypass Mode)
11 Enhanced Secure Digital Host Controller (eSDHC)
This section describes the DC and AC electrical specifications for the eSDHC (SD/MMC) interface of the
chip.
The eSDHC controller always uses the falling edge of the SD_CLK in order to drive the
SD_DAT[0:3]/CMD as outputs and sample the SD_DAT[0:3] as inputs. This behavior is true for both full-
and high-speed modes.
Note that this is a non-standard implementation, as the SD card specification assumes that in high-speed
mode, data is driven at the rising edge of the clock.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
43
Due to the special implementation of the eSDHC, there are constraints regarding the clock and data signals
propagation delay on the user board. The constraints are for minimum and maximum delays, as well as
skew between the CLK and DAT/CMD signals.
In full speed mode, there is no need to add special delay on the data or clock signals. The user should make
sure to meet the timing requirements as described further within this document.
If the system is designed to support both high-speed and full-speed cards, the high-speed constraints
should be fulfilled. If the systems is designed to operate up to 25 MT/s only, full-speed mode is
recommended.
11.1 eSDHC DC Electrical Characteristics
This table provides the DC electrical characteristics for the eSDHC (SD/MMC) interface of the device.
Table 41. eSDHC interface DC Electrical Characteristics
Parameter
Input high voltage
Symbol
Condition
Min
Max
Unit
VIH
VIL
—
—
—
0.625 × OVDD
–0.3
OVDD + 0.3
V
V
Input low voltage
Input current
0.25 × OVDD
IIN
—
30
—
μA
V
Output high voltage
VOH
IOH = –100 uA,
at OVDD(min)
0.75 × OVDD
Output low voltage
VOL
IOL = +100 uA,
at OVDD(min)
—
0.125 × OVDD
V
11.2 eSDHC AC Timing Specifications (Full-Speed Mode)
This section describes the AC electrical specifications for the eSDHC (SD/MMC) interface of the device.
This table provides the eSDHC AC timing specifications for full-speed mode as defined in Figure 27 and
Figure 28.
Table 42. eSDHC AC Timing Specifications for Full-Speed Mode
At recommended operating conditions OVDD = 3.3 V 165 mV.
Parameter
Symbol1
Min
Max
Unit
Note
SD_CLK clock frequency—full speed mode
SD_CLK clock cycle
fSFSCK
tSFSCK
fSIDCK
0
25
—
MT/s
ns
—
—
—
2
40
0
SD_CLK clock frequency—identification mode
SD_CLK clock low time
400
—
KHz
ns
tSFSCKL
tSFSCKH
tSFSCKR
15
15
—
SD_CLK clock high time
—
ns
2
SD_CLK clock rise and fall times
/
5
ns
2
tSFSCKF
Input setup times: SD_CMD, SD_DATx, SD_CD to
SD_CLK
tSFSIVKH
5
—
ns
2
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
44
Table 42. eSDHC AC Timing Specifications for Full-Speed Mode (continued)
At recommended operating conditions OVDD = 3.3 V 165 mV.
Parameter
Symbol1
Min
Max
Unit
Note
Input hold times: SD_CMD, SD_DATx, SD_CD to
tSFSIXKH
0
—
ns
2
SD_CLK
SD_CLK delay within device
Output valid: SD_CLK to SD_CMD, SD_DATx valid
Output hold: SD_CLK to SD_CMD, SD_DATx valid
SD card input setup
tINT_CLK_DLY
tSFSKHOV
tSFSKHOX
tISU
1.5
—
0
—
4
ns
ns
—
ns
ns
ns
ns
4
2
—
—
—
14
—
—
3
5
SD card input hold
tIH
5
3
SD card output valid
tODLY
—
0
3
SD card output hold
tOH
3
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSFSIXKH
symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K)
going to high (H). Also tSFSKHOV symbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with
respect to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol
representation is based on five letters representing the clock of a particular functional. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. Measured at capacitive load of 40 pF.
3. For reference only, according to the SD card specifications.
4. Average, for reference only.
This figure provides the eSDHC clock input timing diagram.
eSDHC
External Clock
VM
VM
VM
operational mode
tSFSCKL
tSFSCKH
tSFSCK
tSFSCKF
tSFSCKR
VM = Midpoint Voltage (OVDD/2)
Figure 26. eSDHC Clock Input Timing Diagram
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
45
11.2.1 Full-Speed Output Path (Write)
This figure provides the data and command output timing diagram.
tSFSCK (clock cycle)
SD CLK at the
Driving
MPC8377E pin
Edge
tCLK_DELAY
SD CLK at
the card pin
Sampling
edge
Output valid time: tSFSKHOV
Output hold time: tSFSKHOX
Output from the
tSFSCKL
MPC8377E Pins
Input at the
MPC8377E pins
tDATA_DELAY
tIH (5 ns)
tISU (5 ns)
Figure 27. Full Speed Output Path
11.2.1.1 Full-Speed Write Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
No clock delay:
t
+ t
+ t
< t
SFSCKL
Eqn. 1
SFSKHOV
DATA_DELAY
ISU
With clock delay:
t
+ t
+ t
< t
+ t
CLK_DELAY
Eqn. 2
Eqn. 3
SFSKHOV
DATA_DELAY
ISU
SFSCKL
t
+ t
< t
+ t
– t
– t
ISU SFSKHOV
DATA_DELAY
SFSCKL
SFSCK
CLK_DELAY
This means that data can be delayed versus clock up to 11 ns in ideal case of t
= 20 ns:
SFSCKL
t
t
+ 20 < 40 + t
– 5 – 4
DATA_DELAY
CLK_DELAY
< 11 + t
DATA_DELAY
CLK_DELAY
11.2.1.2 Full-Speed Write Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
t
< t
+ t
+ t
– t
IH
Eqn. 4
CLK_DELAY
SFSCKL
SFSKHOX
DATA_DELAY
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
46
t
+ t – t
< t + t
SFSCKL DATA_DELAY
Eqn. 5
CLK_DELAY
IH
SFSKHOX
This means that clock can be delayed versus data up to 15 ns (external delay line) in ideal case of
t
= 20 ns:
SFSCLKL
t
t
+ 5 – 0 < 20 + t
CLK_DELAY
DATA_DELAY
< 15 + t
CLK_DELAY
DATA_DELAY
11.2.1.3 Full-Speed Write Combined Formula
The following equation is the combined formula to calculate the allowed skew range between the
SD_CLK and SD_DAT/CMD signals on the PCB.
t
+ t – t
< t
+ t
< t
+ t
– t
– t
SFSKHOV
Eqn. 6
CLK_DELAY
IH
SFSKHOX
SFSCKL
DATA_DELAY
SFSCK CLK_DELAY
ISU
11.2.2 Full-Speed Input Path (Read)
This figure provides the data and command input timing diagram.
tSFSCK (clock cycle)
SD CLK at the
MPC8377E pin
Sampling
edge
tCLK_DELAY
SD CLK at
the card pin
Driving
edge
tDATA_DELAY
tODLY
tOH
Output from the
SD card pins
Input at the
MPC8377E pins
(MPC8377E input hold)
tSFSIXKH
tSFSIVKH
Figure 28. Full Speed Input Path
11.2.2.1 Full-Speed Read Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
t
+ t
+ t
+ t
< t
SFSCK
Eqn. 7
Eqn. 8
CLK_DELAY
DATA_DELAY
ODLY
SFSIVKH
t
+ t
< t
– t
– t
– t
CLK_DELAY
DATA_DELAY
SFSCK
ODLY
SFSIVKH INT_CLK_DLY
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
47
11.2.2.2 Full-Speed Read Meeting Hold (Minimum Delay)
There is no minimum delay constraint due to the full clock cycle between the driving and sampling of data.
t
+ t + t
> t
SFSIXKH
Eqn. 9
CLK_DELAY
OH
DATA_DELAY
This means that Data + Clock delay must be greater than –2 ns. This is always fulfilled.
11.3 eSDHC AC Timing Specifications (High-Speed Mode)
This table provides the eSDHC AC timing specifications for high-speed mode as defined in Figure 30 and
Figure 31.
Table 43. eSDHC AC Timing Specifications for High-Speed Mode
At recommended operating conditions OVDD = 3.3 V 165 mV.
Parameter
Symbol1
Min
Max
Unit
Note
SD_CLK clock frequency—high speed mode
SD_CLK clock cycle
fSHSCK
tSHSCK
fSIDCK
0
20
0
50
—
MT/s
ns
—
—
—
2
SD_CLK clock frequency—identification mode
SD_CLK clock low time
400
—
KHz
ns
tSHSCKL
tSHSCKH
tSHSCKR/
7
SD_CLK clock high time
7
—
ns
2
SD_CLK clock rise and fall times
—
3
ns
2
tSHSCKF
Input setup times: SD_CMD, SD_DATx, SD_CD to
SD_CLK
tSHSIVKH
5
—
ns
2
Input hold times: SD_CMD, SD_DATx, SD_CD to SD_CLK
Output delay time: SD_CLK to SD_CMD, SD_DATx valid
Output Hold time: SD_CLK to SD_CMD, SD_DATx invalid
SD_CLK delay within device
tSHSIXKH
tSHSKHOV
tSHSKHOX
tINT_CLK_DLY
tISU
0
—
0
—
4
ns
ns
ns
ns
ns
ns
ns
ns
2
2
2
4
3
3
3
3
—
—
—
—
14
—
1.5
6
SD Card Input Setup
SD Card Input Hold
tIH
2
SD Card Output Valid
tODLY
—
2.5
SD Card Output Hold
tOH
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first three letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first three letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tSFSIXKH
symbolizes eSDHC full mode speed device timing (SFS) input (I) to go invalid (X) with respect to the clock reference (K)
going to high (H). Also tSFSKHOV symbolizes eSDHC full speed timing (SFS) for the clock reference (K) to go high (H), with
respect to the output (O) going valid (V) or data output valid time. Note that, in general, the clock reference symbol
representation is based on five letters representing the clock of a particular functional. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. Measured at capacitive load of 40 pF.
3. For reference only, according to the SD card specifications.
4. Average, for reference only.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
48
Freescale Semiconductor
This figure provides the eSDHC clock input timing diagram.
eSDHC
External Clock
VM
VM
VM
operational mode
tSHSCKL
tSHSCKH
tSHSCK
tSHSCKF
tSHSCKR
VM = Midpoint Voltage (OVDD/2)
Figure 29. eSDHC Clock Input Timing Diagram
11.3.1 High-Speed Output Path (Write)
This figure provides the data and command output timing diagram.
tSHSCK (clock cycle)
SD CLK at the
Driving
MPC8377E pin
Edge
tCLK_DELAY
SD CLK at
the card Pin
Sampling
edge
Output valid time: tSHSKHOV
Output hold time: tSHSKHOX
tSHSCKL
Output from the
MPC8377E pins
Input at the
SD card pins
tDATA_DELAY
tIH (2 ns)
tISU (6 ns)
Figure 30. High Speed Output Path
11.3.1.1 High-Speed Write Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
Zero clock delay:
t
+ t
+ t
< t
SHSCKL
Eqn. 10
SHSKHOV
DATA_DELAY
ISU
With clock delay:
t
+ t
+ t
< t
+ t
CLK_DELAY
Eqn. 11
Eqn. 12
SHSKHOV
DATA_DELAY
ISU
SHSCKL
t
– t
< t
– t
– t
DATA_DELAY
CLK_DELAY
SHSCKL
ISU SHSKHOV
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
49
This means that data delay should be equal or less than the clock delay in the ideal case where
= 10 ns:
t
SHSCLKL
t – t
DATA_DELAY CLK_DELAY
< 10 – 6 – 4
t – t
DATA_DELAY CLK_DELAY
< 0
11.3.1.2 High-Speed Write Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed skew range between the SD_CLK and
SD_DAT/CMD signals on the PCB.
t
< t
+ t
+ t
– t
Eqn. 13
Eqn. 14
CLK_DELAY
SHSCKL
SHSKHOX
DATA_DELAY
IH
t
– t
< t
+ t
– t
CLK_DELAY
DATA_DELAY
SHSCKL
SHSKHOX
IH
This means that clock can be delayed versus data up to 8 ns (external delay line) in ideal case of
= 10 ns:
t
SHSCLKL
t – t
CLK_DELAY DATA_DELAY
< 10 + 0 – 2
t – t
CLK_DELAY DATA_DELAY
< 8
11.3.2 High-Speed Input Path (Read)
This figure provides the data and command input timing diagram.
tSHSCK (Clock Cycle)
1/2 Cycle
Wrong Edge
Right Edge
SD CLK at the
MPC8377E Pin
Sampling
Edge
tCLK_DELAY
Driving
Edge
SD CLK at
the Card Pin
tODLY
tOH
tDATA_DELAY
Output from the
SD Card Pins
Input at the
MPC8377E Pins
tSHSIVKH
(MPC8377E Input Setup)
(MPC8377E Input Hold)
tSHSIXKH
Figure 31. High-Speed Input Path
For the input path, the device eSDHC expects to sample the data 1.5 internal clock cycles after it was
driven by the SD card. Since in this mode the SD card drives the data at the rising edge of the clock, a
sufficient delay to the clock and the data must exist to ensure it will not be sampled at the wrong internal
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50
Freescale Semiconductor
clock falling edge. Note that the internal clock which is guaranteed to be 50% duty cycle is used to sample
the data, and therefore used in the equations.
11.3.2.1 High-Speed Read Meeting Setup (Maximum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
t
+ t
+ t
+ t
< 1.5 × t
Eqn. 15
Eqn. 16
CLK_DELAY
DATA_DELAY
ODLY
SHSIVKH
SHSCK
t
+ t
< 1.5 × t
– t
– t
ODLY SHSIVKH
CLK_DELAY
DATA_DELAY
SHSCK
This means that Data + Clock delay can be up to 11 ns for a 20 ns clock cycle:
t
t
+ t
+ t
< 30 – 14 – 5
CLK_DELAY
DATA_DELAY
DATA_DELAY
< 11
CLK_DELAY
11.3.2.2 High-Speed Read Meeting Hold (Minimum Delay)
The following equations show how to calculate the allowed combined propagation delay range of the
SD_CLK and SD_DAT/CMD signals on the PCB.
0.5 × t
0.5 × t
< t
+ t
+ t – t
+ t
INT_CLK_DLY
Eqn. 17
Eqn. 18
SHSCK
CLK_DELAY
DATA_DELAY
OH
SHSIXKH
– t
+ t
– t
< t
+ t
CLK_DELAY DATA_DELAY
SHSCK
OH
SHSIXKH
INT_CLK_DLY
This means that Data + Clock delay must be greater than ~6 ns for a 20 ns clock cycle:
10 – 2.5 + (–1.5) < t + t
CLK_DELAY
DATA_DELAY
6 < t
+ t
DATA_DELAY
CLK_DELAY
11.3.2.3 High-Speed Read Combined Formula
The following equation is the combined formula to calculate the propagation delay range of the SD_CLK
and SD_DAT/CMD signals on the PCB.
0.5 × t
– t
+ t
< t
+ t
< 1.5 × t
– t
– t
SHSIVKH
Eqn. 19
SHSCK
OH
SHSIXKH
CLK_DELAY
DATA_DELAY
SHSCK
ODLY
12 JTAG
This section describes the DC and AC electrical specifications for the IEEE 1149.1 (JTAG) interface of
the chip.
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51
12.1 JTAG DC Electrical Characteristics
This table provides the DC electrical characteristics for the IEEE 1149.1 (JTAG) interface of the chip.
Table 44. JTAG interface DC Electrical Characteristics
Parameter
Input high voltage
Symbol
Condition
Min
Max
Unit
VIH
VIL
—
—
2.5
–0.3
—
OVDD + 0.3
V
V
Input low voltage
Input current
0.8
30
IIN
—
μA
V
Output high voltage
Output low voltage
Output low voltage
VOH
VOL
IOH = –8.0 mA
IOL = 8.0 mA
2.4
—
—
0.5
0.4
V
V
I
= 3.2 mA
OL
—
V
OL
12.2 JTAG AC Timing Specifications
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the device.
This table provides the JTAG AC timing specifications as defined in Figure 33 through Figure 36.
1
Table 45. JTAG AC Timing Specifications (Independent of CLKIN)
Parameter
Symbol2
Min
Max
Unit
Note
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
fJTG
t JTG
0
33.3
—
—
2
MT/s
ns
—
—
—
—
3
30
15
0
tJTKHKL
tJTGR & tJTGF
tTRST
ns
ns
25
—
ns
Input setup times:
ns
Boundary-scan data
tJTDVKH
tJTIVKH
4
4
—
—
4
4
TMS, TDI
Input hold times:
Valid times:
ns
ns
ns
Boundary-scan data
TMS, TDI
tJTDXKH
tJTIXKH
10
10
—
—
Boundary-scan data
TDO
tJTKLDV
tJTKLOV
2
2
11
11
—
—
Output hold times:
Boundary-scan data
TDO
tJTKLDX
tJTKLOX
2
2
—
—
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52
1
Table 45. JTAG AC Timing Specifications (Independent of CLKIN) (continued)
Parameter
Symbol2
Min
Max
Unit
Note
JTAG external clock to output high impedance:
ns
Boundary-scan data
TDO
tJTKLDZ
tJTKLOZ
2
2
19
9
5
Notes:
1. All outputs are measured from the midpoint voltage of the falling/rising edge of tTCLK to the midpoint of the signal in
question. The output timings are measured at the pins. All output timings assume a purely resistive 50 Ω load (see
Figure 17). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tJTDVKH
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state (V) relative to
the tJTG clock reference (K) going to the high (H) state or setup time. Also, tJTDXKH symbolizes JTAG timing (JT) with respect
to the time data input signals (D) went invalid (X) relative to the tJTG clock reference (K) going to the high (H) state. Note
that, in general, the clock reference symbol representation is based on three letters representing the clock of a particular
functional. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
3. TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4. Non-JTAG signal input timing with respect to tTCLK
.
5. Non-JTAG signal output timing with respect to tTCLK
.
This figure provides the AC test load for TDO and the boundary-scan outputs of the device.
Z0 = 50 Ω
OVDD/2
Output
RL = 50 Ω
Figure 32. AC Test Load for the JTAG Interface
This figure provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
tJTKHKL
VM
VM
tJTGR
tJTGF
tJTG
VM = Midpoint Voltage (OVDD/2)
Figure 33. JTAG Clock Input Timing Diagram
This figure provides the TRST timing diagram.
TRST
VM
VM
tTRST
VM = Midpoint Voltage (OVDD/2)
Figure 34. TRST Timing Diagram
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Freescale Semiconductor
53
This figure provides the boundary-scan timing diagram.
JTAG
VM
VM
External Clock
tJTDVKH
tJTDXKH
Boundary
Data Inputs
Input
Data Valid
tJTKLDV
tJTKLDX
Boundary
Data Outputs
Output Data Valid
tJTKLDZ
Output Data Valid
Boundary
Data Outputs
VM = Midpoint Voltage (OVDD/2)
Figure 35. Boundary-Scan Timing Diagram
This figure provides the test access port timing diagram.
JTAG
VM
VM
External Clock
tJTIVKH
tJTIXKH
Input
TDI, TMS
TDO
Data Valid
tJTKLOV
tJTKLOX
Output Data Valid
tJTKLOZ
Output Data Valid
TDO
VM = Midpoint Voltage (OVDD/2)
Figure 36. Test Access Port Timing Diagram
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54
13 I2C
2
This section describes the DC and AC electrical characteristics for the I C interface of the chip.
2
13.1 I C DC Electrical Characteristics
2
This table provides the DC electrical characteristics for the I C interface of the chip.
2
Table 46. I C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V 165 mV.
Parameter
Symbol
Min
Max
Unit
Note
Input high voltage level
Input low voltage level
Low level output voltage
VIH
VIL
0.7 × OVDD
OVDD + 0.3
0.3 × OVDD
0.2 × OVDD
250
V
V
—
—
1
–0.3
0
VOL
V
Output fall time from VIH(min) to VIL(max) with a bus capacitance
from 10 to 400 pF
t
20 + 0.1 × CB
ns
2
I2KLKV
Pulse width of spikes which must be suppressed by the input filter tI2KHKL
0
50
10
30
ns
pF
μA
3
—
4
Capacitance for each I/O pin
CI
—
—
Input current
IIN
(0 V ≤ VIN ≤ OVDD
)
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. CB = capacitance of one bus line in pF.
3. Refer to the MPC8379E PowerQUICC II Pro Integrated Host Processor Reference Manual for information on the digital filter
used.
4. I/O pins will obstruct the SDA and SCL lines if OVDD is switched off.
2
13.2 I C AC Electrical Specifications
2
This table provides the AC timing parameters for the I C interface of the device.
2
Table 47. I C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 46).
Parameter
Symbol1
Min
Max
Unit
Note
SCL clock frequency
fI2C
tI2CL
0
400
—
kHz
μs
—
—
—
—
—
Low period of the SCL clock
High period of the SCL clock
1.3
0.6
0.6
0.6
tI2CH
—
μs
Setup time for a repeated START condition
tI2SVKH
tI2SXKL
—
μs
Hold time (repeated) START condition (after this period, the first
clock pulse is generated)
—
μs
Data setup time
tI2DVKH
100
—
ns
—
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Freescale Semiconductor
55
2
Table 47. I C AC Electrical Specifications (continued)
All values refer to VIH (min) and VIL (max) levels (see Table 46).
Parameter
Symbol1
Min
Max
Unit
Note
Data hold time
tI2DXKL
μs
2, 3
CBUS compatible masters
I2C bus devices
—
0
—
0.9
Setup time for STOP condition
t
0.6
1.3
—
—
—
μs
μs
V
—
—
—
I2PVKH
Bus free time between a STOP and START condition
tI2KHDX
VNL
Noise margin at the LOW level for each connected device (including
hysteresis)
0.1 × OVDD
Noise margin at the HIGH level for each connected device (including
hysteresis)
VNH
0.2 × OVDD
—
V
—
Notes:
1. The symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tI2DVKH
symbolizes I2C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the tI2C clock
reference (K) going to the high (H) state or setup time. Also, tI2SXKL symbolizes I2C timing (I2) for the time that the data with
respect to the start condition (S) went invalid (X) relative to the tI2C clock reference (K) going to the low (L) state or hold time.
Also, tI2PVKH symbolizes I2C timing (I2) for the time that the data with respect to the stop condition (P) reaching the valid
state (V) relative to the tI2C clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter
convention is used with the appropriate letter: R (rise) or F (fall).
2. This chip provides a hold time of at least 300 ns for the SDA signal (referred to the VIHmin of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
3. The maximum tI2DVKH has only to be met if the device does not stretch the LOW period (tI2CL) of the SCL signal.
2
This figure provides the AC test load for the I C.
Output
OVDD/2
Z0 = 50 Ω
RL = 50 Ω
2
Figure 37. I C AC Test Load
2
This figure shows the AC timing diagram for the I C bus.
SDA
tI2CF
tI2CL
tI2DVKH
tI2KHKL
tI2CF
tI2SXKL
tI2CR
SCL
tI2SXKL
tI2CH
tI2SVKH
tI2PVKH
tI2DXKL
S
Sr
P
S
2
Figure 38. I C Bus AC Timing Diagram
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
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56
14 PCI
This section describes the DC and AC electrical specifications for the PCI bus of the chip.
14.1 PCI DC Electrical Characteristics
This table provides the DC electrical characteristics for the PCI interface of the device. The DC
characteristics of the PORESET signal, which can be used as PCI RST in applications where the device is
a PCI agent, deviates from the standard PCI levels.
Table 48. PCI DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
High-level input voltage
Low-level input voltage
High-level output voltage
Low-level output voltage
Input current
VOUT ≥ VOH (min) or
VOUT ≤ VOL (max)
IOH = –500 μA
VIH
VIL
2.0
–0.5
OVDD + 0.5
0.3 × OVDD
—
V
V
VOH
VOL
IIN
0.9 × OVDD
—
V
I
OL = 1500 μA
0.1 × OVDD
30
V
0 V ≤ VIN ≤ OVDD
—
μA
Note:
• The symbol VIN, in this case, represents the OVIN symbol referenced in Table 2.
14.2 PCI AC Electrical Specifications
This section describes the general AC timing parameters of the PCI bus of the device. Note that the
PCI_CLK/PCI_SYNC_IN or CLKIN signal is used as the PCI input clock depending on whether the chip
is configured as a host or agent device. CLKIN is used when the device is in host mode.
This table shows the PCI AC timing specifications at 66 MT/s.
.
Table 49. PCI AC Timing Specifications at 66 MT/s
PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1 × OVDD, VIH = 0.7 × OVDD
.
Parameter
Clock to output valid
Symbol1
Min
Max
Unit
Note
tPCKHOV
tPCKHOX
tPCKHOZ
tPCIVKH
—
1
6.0
—
ns
ns
ns
ns
2
Output hold from clock
Clock to output high impedance
Input setup to clock
2
—
3.0
14
—
2, 3
2, 4
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Freescale Semiconductor
57
Table 49. PCI AC Timing Specifications at 66 MT/s (continued)
PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1 × OVDD, VIH = 0.7 × OVDD
.
Parameter
Input hold from cock
Symbol1
Min
Max
Unit
Note
tPCIXKH
tPCKOSK
0.25
—
—
ns
ns
2, 4, 6
5
Output clock skew
0.5
Notes:
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the
PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC)
with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. PCI specifications allows 1 ns skew for 66 MT/s but includes the total allowed skew, board, connectors, etc.
6. Value does not comply with the PCI 2.3 Local Bus Specifications.
This table shows the PCI AC timing specifications at 33 MT/s.
Table 50. PCI AC Timing Specifications at 33 MT/s
PCI_SYNC_IN clock input levels are with next levels: VIL = 0.1 × OVDD, VIH = 0.7 × OVDD
.
Parameter
Clock to output valid
Symbol1
Min
Max
Unit
Note
t
—
2
11
—
ns
ns
ns
ns
ns
ns
2
2
PCKHOV
Output hold from clock
Clock to output high impedance
Input setup to clock
Input hold from clock
Output clock skew
Notes:
t
PCKHOX
tPCKHOZ
tPCIVKH
tPCIXKH
tPCKOSK
—
14
—
2, 3
2, 4
2, 4, 6
5
3.0
0.25
—
—
0.5
1. Note that the symbols used for timing specifications herein follow the pattern of t(first two letters of functional block)(signal)(state)
(reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tPCIVKH
symbolizes PCI timing (PC) with respect to the time the input signals (I) reach the valid state (V) relative to the
PCI_SYNC_IN clock, tSYS, reference (K) going to the high (H) state or setup time. Also, tPCRHFV symbolizes PCI timing (PC)
with respect to the time hard reset (R) went high (H) relative to the frame signal (F) going to the valid (V) state.
2. See the timing measurement conditions in the PCI 2.3 Local Bus Specifications.
3. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
4. Input timings are measured at the pin.
5. PCI specifications allows 2 ns skew for 33 MT/s but includes the total allowed skew, board, connectors, etc.
6. Value does not comply with the PCI 2.3 Local Bus Specifications.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
58
Freescale Semiconductor
This figure provides the AC test load for PCI.
OVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
Figure 39. PCI AC Test Load
This figure shows the PCI input AC timing conditions.
CLK
tPCIVKH
tPCIXKH
Input
Figure 40. PCI Input AC Timing Measurement Conditions
This figure shows the PCI output AC timing conditions.
CLK
tPCKHOV
tPCKHOX
Output Delay
tPCKHOZ
High-Impedance
Output
Figure 41. PCI Output AC Timing Measurement Condition
15 PCI Express
This section describes the DC and AC electrical specifications for the PCI Express bus.
15.1 DC Requirements for PCI Express SD_REF_CLK and
SD_REF_CLK
For more information see Section 21, “High-Speed Serial Interfaces (HSSI).”
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
59
15.2 AC Requirements for PCI Express SerDes Clocks
This table lists the PCI Express SerDes clock AC requirements.
Table 51. SD_REF_CLK and SD_REF_CLK AC Requirements
Parameter
Symbol
Min
Typical
Max
Unit
Note
REFCLK cycle time
tREF
—
—
10
—
—
ns
ps
—
—
REFCLK cycle-to-cycle jitter. Difference in the period of any
two adjacent REFCLK cycles.
tREFCJ
100
REFCLK phase jitter peak-to-peak. Deviation in edge
location with respect to mean edge location.
tREFPJ
–50
—
+50
ps
—
SD_REF_CLK/_B cycle to cycle clock jitter (period jitter)
tCKCJ
tCKPJ
—
—
—
100
+50
ps
ps
—
SD_REF_CLK/_B phase jitter peak-to-peak. Deviation in
edge location with respect to mean edge location.
–50
2, 3
Notes:
1. All options provide serial interface bit rate of 1.5 and 3.0 Gbps.
2. In a frequency band from 150 kHz to 15 MT/s, at BER of 10-12
.
3. Total peak-to-peak Deterministic Jitter “JD” should be less than or equal to 50 ps.
15.3 Clocking Dependencies
The ports on the two ends of a link must transmit data at a rate that is within 600 parts per million (ppm)
of each other at all times. This is specified to allow bit rate clock sources with a ±300 ppm tolerance.
15.4 Physical Layer Specifications
Following is a summary of the specifications for the physical layer of PCI Express on this device. For
further details as well as the specifications of the transport and data link layer, use the PCI Express Base
Specification, Rev. 1.0a.
NOTE
The voltage levels of the transmitter and the receiver depend on the SerDes
control registers which should be programmed at the recommended values
for PCI Express protocol (that is, L1_nV = 1.0 V).
DD
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Freescale Semiconductor
15.4.1 Differential Transmitter (Tx) Output
This table defines the specifications for the differential output at all transmitters. The parameters are
specified at the component pins.
Table 52. Differential Transmitter (Tx) Output Specifications
Parameter
Unit interval
Conditions
Symbol
Min
Typical
Max
Units
Note
Each UPETX is 400 ps 300
ppm. UPETX does not account
for Spread Spectrum Clock
dictated variations.
UI
399.88
400
400.12
ps
1
Differential
peak-to-peak output
voltage
V
PEDPPTX = 2 × ꢀVTX-D+
–
VTX-DIFFp-p
0.8
—
1.2
V
2
2
VTX-D-
ꢀ
De-emphasized
differential output
voltage (ratio)
Ratio of the VPEDPPTX of the
second and following bits after
a transition divided by the
VPEDPPTX of the first bit after a
transition.
VTX-DE-RATIO
–3.0
–3.5
–4.0
dB
Minimum Tx eye width The maximum transmitter
jitter can be derived as
TTX-EYE
0.70
—
—
—
—
UI
UI
2, 3
2, 3
TTX-MAX-JITTER = 1 –
UPEEWTX= 0.3 UI.
Maximumtimebetween Jitter is defined as the
TTX-EYE-MEDIAN-to-
0.15
the jitter median and
maximum deviation
from the median
measurement variation of the
crossing points (VPEDPPTX = 0
V) in relation to a recovered Tx
UI. A recovered Tx UI is
calculated over 3500
MAX-JITTER
consecutive unit intervals of
sample data. Jitter is
measured using all edges of
the 250 consecutive UI in the
center of the 3500 UI used for
calculating the Tx UI.
D+/D– Tx output
rise/fall time
—
TTX-RISE, TTX-FALL
0.125
—
—
—
—
UI
2, 5
2
RMS AC peak common VPEACPCMTX = RMS(ꢀVTXD+
–
VTX-CM-ACp
20
mV
mode output voltage
VTXD-ꢀ/2 – VTX-CM-DC)
VTX-CM-DC = DC(avg) of
ꢀVTX-D+ – VTX-D-ꢀ/2
Absolute delta of DC
ꢀVTX-CM-DC (during LO)
–
VTX-CM-DC- ACTIVE-
0
—
100
mV
2
common mode voltage VTX-CM-Idle-DC (During Electrical
during LO and electrical Idle)ꢀ<=100 mV
IDLE-DELTA
idle
VTX-CM-DC = DC(avg) of
ꢀVTX-D+ – VTX-D-ꢀ/2 [LO]
VTX-CM-Idle-DC = DC(avg) of
ꢀVTX-D+ – VTX-D-ꢀ/2 [Electrical
Idle]
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
61
Table 52. Differential Transmitter (Tx) Output Specifications (continued)
Parameter
Conditions
Symbol
Min
Typical
Max
Units
Note
Absolute delta of DC
common mode
ꢀVTX-CM-DC-D+ – VTX-CM-DC-D-
≤ 25 mV
ꢀ
VTX-CM-DC-LINE-
0
—
25
mV
2
DELTA
between D+ and D–
VTX-CM-DC-D+ = DC(avg) of
ꢀVTX-D+ꢀ
VTX-CM-DC-D- = DC(avg) of
ꢀVTX-D-
ꢀ
Electrical idle
differential peak output -VTX-IDLE-D-ꢀ ≤ 20 mV
voltage
V
PEEIDPTX = ꢀVTX-IDLE-D+
VTX-IDLE-DIFFp
0
—
20
mV
mV
2
6
Amount of voltage
The total amount of voltage
VTX-RCV-DETECT
—
XPADVDD/2
600
change allowed during change that a transmitter can
receiver detection
apply to sense whether a low
impedance receiver is
present.
Tx DC common mode The allowed DC common
VTX-DC-CM
0
XPADVDD/2
—
90
—
V
6
voltage
mode voltage under any
conditions.
Tx short circuit current The total current the
limit transmitter can provide when
shorted to its ground
ITX-SHORT
—
50
—
—
mA
UI
—
—
Minimum time spent in Minimum time a transmitter
TTX-IDLE-MIN
electrical idle
must be in electrical idle.
Utilized by the receiver to start
looking for an electrical idle
exit after successfully
receiving an electrical idle
ordered set.
Maximum time to
transition to a valid
electrical idle after
sending an electrical
idle ordered set
After sending an electrical idle TTX-IDLE-SET-TO-IDLE
ordered set, the transmitter
must meet all electrical idle
specifications within this time.
This is considered a
—
—
20
UI
—
debounce time for the
transmitter to meet electrical
idle after transitioning from
LO.
Maximum time to
transition to valid Tx
specifications after
Maximum time to meet all Tx TTX-IDLE-TO-DIFF-DATA
specifications when
transitioning from electrical
—
—
20
UI
—
leaving anelectrical idle idle to sending differential
condition
data. This is considered a
debounce time for the Tx to
meet all Tx specifications after
leaving electrical idle
Differential return loss Measured over 50 MT/s to
1.25 GHz.
RLTX-DIFF
12
—
—
dB
4
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
62
Table 52. Differential Transmitter (Tx) Output Specifications (continued)
Parameter
Conditions
Symbol
Min
Typical
Max
Units
Note
Common mode return Measured over 50 MT/s to
RLTX-CM
6
—
—
dB
4
loss
1.25 GHz.
DC differential Tx
impedance
Tx DC differential mode low
impedance
ZTX-DIFF-DC
80
40
100
—
120
—
Ω
Ω
—
—
Transmitter DC
impedance
Required Tx D+ as well as D–
DC impedance during all
states
ZTX-DC
Lane-to-Lane output
skew
Static skew between any two
transmitter lanes within a
single link
LTX-SKEW
—
—
—
500 +
2 UI
ps
—
—
AC coupling capacitor All transmitters should be AC
coupled. The AC coupling is
CTX
75
200
nF
required either within the
media or within the
transmitting component itself.
Crosslink random
timeout
This random timeout helps
resolve conflicts in crosslink
configuration by eventually
resulting in only one
Tcrosslink
0
—
1
ms
7
downstream and one
upstream port.
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point into a timing and voltage compliance test load as shown in Figure 44 and measured
over any 250 consecutive Tx UIs. (Also refer to the transmitter compliance eye diagram shown in Figure 42.)
3. A TTX-EYE = 0.70 UI provides for a total sum of deterministic and random jitter budget of TTX-JITTER-MAX = 0.30 UI for the
transmitter collected over any 250 consecutive Tx UIs. The TTX-EYE-MEDIAN-to-MAX-JITTER median is less than half of the total
Tx jitter budget collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean.
The jitter median describes the point in time where the number of jitter points on either side is approximately equal as
opposed to the averaged time value.
4. The transmitter input impedance will result in a differential return loss greater than or equal to 12 dB and a common mode
return loss greater than or equal to 6 dB over a frequency range of 50 MT/s to 1.25 GHz. This input impedance requirement
applies to all valid input levels. The reference impedance for return loss measurements is 50 Ω to ground for both the D+
and D– line (that is, as measured by a vector network analyzer with 50-Ω probes, see Figure 44). Note that the series
capacitors, CTX, is optional for the return loss measurement.
5. Measured between 20%–80% at transmitter package pins into a test load as shown in Figure 44 for both VTX-D+ and VTX-D-
6. See Section 4.3.1.8 of the PCI Express Base Specifications, Rev 1.0a.
.
7. See Section 4.2.6.3 of the PCI Express Base Specifications, Rev 1.0a.
15.4.2 Transmitter Compliance Eye Diagrams
The Tx eye diagram in Figure 42 is specified using the passive compliance/test measurement load (see
Figure 44) in place of any real PCI Express interconnect + Rx component. There are two eye diagrams that
must be met for the transmitter. Both diagrams must be aligned in time using the jitter median to locate the
center of the eye diagram. The different eye diagrams differ in voltage depending on whether it is a
transition bit or a de-emphasized bit. The exact reduced voltage level of the de-emphasized bit is always
relative to the transition bit.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
63
The eye diagram must be valid for any 250 consecutive UIs.
A recovered Tx UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the Tx
UI.
NOTE
It is recommended that the recovered Tx UI be calculated using all edges in
the 3500 consecutive UI interval with a fit algorithm using a minimization
merit function (that is, least squares and median deviation fits).
VTX-DIFF = 0 mV
VTX-DIFF = 0 mV
(D+ D– Crossing Point)
(D+ D– Crossing Point)
[Transition Bit]
TX-DIFFp-p-MIN = 800 mV
V
[De-emphasized Bit]
566 mV (3 dB) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB)
0.7 UI = UI – 0.3 UI(JTX-TOTAL-MAX
[Transition Bit]
)
VTX-DIFFp-p-MIN = 800 mV
Figure 42. Minimum Transmitter Timing and Voltage Output Compliance Specifications
15.4.3 Differential Receiver (Rx) Input Specifications
This table defines the specifications for the differential input at all receivers. The parameters are specified
at the component pins.
Table 53. Differential Receiver (Rx) Input Specifications
Parameter
Unit interval
Comments
Symbol
Min
Typical
Max
Units
Note
Each UPERX is 400 ps 300
ppm. UPERX does not account
for Spread Spectrum Clock
dictated variations.
UI
399.88
400
400.12
ps
1
Differential peak-to-peak VPEDPPRX = 2 × ꢀVRX-D+
output voltage VRX-D-
–
VRX-DIFFp-p
0.175
—
1.200
V
2
ꢀ
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
64
Table 53. Differential Receiver (Rx) Input Specifications (continued)
Parameter
Comments
Symbol
Min
Typical
Max
Units
Note
Minimum receiver eye
width
The maximum interconnect
media and transmitter jitter that
can be tolerated by the receiver
can be derived as
TRX-EYE
0.4
—
—
UI
2, 3
TRX-MAX-JITTER = 1 –
UPEEWRX = 0.6 UI.
Maximum time between Jitter is defined as the
the jitter median and measurement variation of the
maximum deviation from crossing points (VPEDPPRX = 0
TRX-EYE-MEDIAN-to
—
—
0.3
UI
2, 3, 7
-MAX-JITTER
the median.
V) in relation to a recovered Tx
UI. A recovered Tx UI is
calculated over 3500
consecutive unit intervals of
sample data. Jitter is measured
using all edges of the 250
consecutive UI in the center of
the 3500 UI used for calculating
the Tx UI.
AC peak common mode VPEACPCMRX = ꢀVRXD+
–
VRX-CM-ACp
RLRX-DIFF
RLRX-CM
—
10
6
—
—
—
150
—
mV
dB
dB
2
4
4
input voltage
VRXD-ꢀ/2 – VRX-CM-DC
VRX-CM-DC = DC(avg) of ꢀVRX-D+
– VRX-D-ꢀ/2
Differential return loss
Measured over 50 MT/s to 1.25
GHz with the D+ and D– lines
biased at +300 mV and –300
mV, respectively.
Common mode return
loss
Measured over 50 MT/s to 1.25
GHz with the D+ and D– lines
biased at 0 V.
—
DC differential input
impedance
RX DC differential mode
impedance.
ZRX-DIFF-DC
80
40
100
50
120
60
Ω
Ω
5
DC Input Impedance
Required RX D+ as well as D-
DC impedance (50 20%
tolerance).
ZRX-DC
2, 5
Powered down DC input Required RX D+ as well as D– ZRX-HIGH-IMP-DC
200 k
65
—
—
—
Ω
6
impedance
DC impedance when the
receiver terminations do not
have power.
Electrical idle detect
threshold
VPEEIDT = 2 × ꢀVRX-D+ -VRX-D-
Measured at the package pins
ꢀ
VRX-IDLE-DET-DIFF
175
mV
—
p-p
of the receiver
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
65
Table 53. Differential Receiver (Rx) Input Specifications (continued)
Parameter
Comments
Symbol
Min
Typical
Max
Units
Note
Unexpected Electrical Idle An unexpected electrical idle
TRX-IDLE-DET-DIFF-
—
—
10
ms
—
Enter Detect Threshold
Integration Time
(Vrx-diffp-p <
ENTERTIME
Vrx-idle-det-diffp-p) must be
recognized no longer than
Trx-idle-det-diff-entertime to
signal an unexpected idle
condition.
Total Skew
Skew across all lanes on a link.
This includes variation in the
length of SKP ordered set (e.g.
COM and one to five SKP
LRX-SKEW
—
—
20
ns
—
Symbols) at the Rx as well as
any delay differences arising
from the interconnect itself.
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 44 should be used
as the Rx device when taking measurements (also refer to the receiver compliance eye diagram shown in Figure 43). If the
clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500 consecutive UI must
be used as a reference for the eye diagram.
3. A TRx-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the transmitter and
interconnect collected any 250 consecutive UIs. The TRx-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget
collected over any 250 consecutive Tx UIs. It should be noted that the median is not the same as the mean. The jitter median
describes the point in time where the number of jitter points on either side is approximately equal as opposed to the averaged
time value. If the clocks to the Rx and Tx are not derived from the same reference clock, the Tx UI recovered from 3500
consecutive UI must be used as the reference for the eye diagram.
4. The receiver input impedance will result in a differential return loss greater than or equal to 10 dB with the D+ line biased to
300 mV and the D– line biased to –300 mV and a common mode return loss greater than or equal to 6 dB (no bias required)
over a frequency range of 50 MT/s to 1.25 GHz. This input impedance requirement applies to all valid input levels. The
reference impedance for return loss measurements for is 50 Ω to ground for both the D+ and D– line (that is, as measured
by a vector network analyzer with 50-Ω probes, see Figure 44). Note that the series capacitors, CTx, is optional for the return
loss measurement.
5. Impedance during all LTSSM states. When transitioning from a fundamental reset to detect (the initial state of the LTSSM)
there is a 5 ms transition time before receiver termination values must be met on all unconfigured lanes of a port.
6. The Rx DC common mode impedance that exists when no power is present or fundamental reset is asserted. This helps
ensure that the receiver detect circuit does not falsely assume a receiver is powered on when it is not. This term must be
measured at 300 mV above the Rx ground.
7. It is recommended that the recovered Tx UI is calculated using all edges in the 3500 consecutive UI interval with a fit algorithm
using a minimization merit function. Least squares and median deviation fits have worked well with experimental and
simulated data.
15.5 Receiver Compliance Eye Diagrams
The Rx eye diagram in Figure 43 is specified using the passive compliance/test measurement load (see
Figure 44) in place of any real PCI Express Rx component. In general, the minimum receiver eye diagram
measured with the compliance/test measurement load (see Figure 44) is larger than the minimum receiver
eye diagram measured over a range of systems at the input receiver of any real PCI Express component.
The degraded eye diagram at the input receiver is due to traces internal to the package as well as silicon
parasitic characteristics that cause the real PCI Express component to vary in impedance from the
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
66
Freescale Semiconductor
compliance/test measurement load. The input receiver eye diagram is implementation specific and is not
specified. Rx component designer should provide additional margin to adequately compensate for the
degraded minimum receiver eye diagram (shown in Figure 43) expected at the input receiver based on an
adequate combination of system simulations and the return loss measured looking into the Rx package and
silicon. The Rx eye diagram must be aligned in time using the jitter median to locate the center of the eye
diagram.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered Tx UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the Tx
UI.
NOTE
The reference impedance for return loss measurements is 50 Ω to ground for
both the D+ and D– line (that is, as measured by a Vector Network Analyzer
with 50 Ω probes—see Figure 44). Note that the series capacitors,
C
, are optional for the return loss measurement.
PEACCTX
VRX-DIFF = 0 mV
VRX-DIFF = 0 mV
(D+ D– Crossing Point)
(D+ D– Crossing Point)
VRX-DIFFp-p-MIN > 175 mV
0.4 UI = TRX-EYE-MIN
Figure 43. Minimum Receiver Eye Timing and Voltage Compliance Specification
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
67
15.5.1 Compliance Test and Measurement Load
The AC timing and voltage parameters must be verified at the measurement point, as specified within
0.2 inches of the package pins, into a test/measurement load shown in Figure 44.
NOTE
The allowance of the measurement point to be within 0.2 inches of the
package pins is meant to acknowledge that package/board routing may
benefit from D+ and D– not being exactly matched in length at the package
pin boundary. If the vendor does not explicitly state where the measurement
point is located, the measurement point is assumed to be the D+ and D–
package pins.
D+ Package Pin
C = CTX
TX Silicon +
Package
C = CTX
R = 50 Ω
R = 50 Ω
D– Package Pin
Figure 44. Compliance Test/Measurement Load
16 Serial ATA (SATA)
This section describes the DC and AC electrical specifications for the serial ATA (SATA) of the
MPC8377E. Note that the external cabled applications or long backplane applications (Gen1x and Gen2x)
are not supported.
16.1 Requirements for SATA REF_CLK
The reference clock is a single ended input clock required for the SATA interface operation. The AC
requirements for the SATA reference clock are listed in the Table 54.
Table 54. SATA Reference Clock Input Requirements
Parameter
Condition
Symbol
Min
Typical
Max
Unit
Note
SD_REF_CLK/ SD_REF_CLK
frequency range
—
tCLK_REF
—
100/125/150
—
MT/s
1
SD_REF_CLK/ SD_REF_CLK
clock frequency tolerance
—
tCLK_TOL
–350
40
0
+350
60
ppm
%
—
—
SD_REF_CLK/ SD_REF_CLK
reference clock duty cycle
Measured at 1.6V
tCLK_DUTY
50
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
68
Table 54. SATA Reference Clock Input Requirements (continued)
Parameter
Condition
Symbol
Min
Typical
Max
Unit
Note
SD_REF_CLK/ SD_REF_CLK
cycle to cycle Clock jitter (period
jitter)
Cycle-to-cycle at
ref clock input
tCLK_CJ
—
—
100
ps
—
SD_REF_CLK/ SD_REF_CLK total Peak-to-peak jitter
tCLK_PJ
–50
—
+50
ps
2, 3
reference clock jitter, phase jitter
(peak-peak)
at ref clock input
Notes:
1. Only 100/125/150 MT/s have been tested, other in between values will not work correctly with the rest of the system.
2. In a frequency band from 150 kHz to 15 MT/s at BER of 10-12
.
3. Total peak to peak Deterministic Jitter "DJ" should be less than or equal to 50 ps.
This figure shows the SATA reference clock timing waveform.
TH
Ref_CLK
TL
Figure 45. SATA Reference Clock Timing Waveform
16.2 Transmitter (Tx) Output Characteristics
This section discusses the Gen1i/1.5G and Gen2i/3G transmitter output characteristics for the SATA
interface.
16.2.1 Gen1i/1.5G Transmitter Specifications
This table provides the DC differential transmitter output DC characteristics for the SATA interface at
Gen1i or 1.5 Gbits/s transmission.
Table 55. Gen1i/1.5G Transmitter (Tx) DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Note
Tx differential output voltage
Tx differential pair impedance
VSATA_TXDIFF
400
85
500
100
600
115
mVp-p
1
ZSATA_TXDIFFIM
Ω
—
Note:
1. Terminated by 50 Ω load.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
69
This table provides the differential transmitter output AC characteristics for the SATA interface at Gen1i
or 1.5 Gbits/s transmission.
Table 56. Gen1i/1.5G Transmitter AC Specifications
Parameter
Channel speed
Symbol
Min
Typical
Max
Units
Note
tCH_SPEED
TUI
—
666.4333
—
1.5
666.667
—
—
Gbps
ps
—
—
1
Unit interval
670.2333
0.355
Total jitter, data-data
5 UI
USATA_TXTJ5UI
UIp-p
Total jitter, data-data
250 UI
USATA_TXTJ250UI
USATA_TXDJ5UI
USATA_TXDJ250UI
—
—
—
—
—
—
0.47
0.175
0.22
UIp-p
UIp-p
UIp-p
1
1
1
Deterministic jitter, data-data
5 UI
Deterministic jitter, data-data
250 UI
Note:
1. Measured at Tx output pins peak to peak phase variation, random data pattern.
16.2.2 Gen2i/3G Transmitter Specifications
This table provides the differential transmitter output DC characteristics for the SATA interface at Gen2i
or 3.0 Gbits/s transmission.
Table 57. Gen 2i/3G Transmitter DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Note
Tx differential output voltage
Tx differential pair impedance
VSATA_TXDIFF
400
85
550
100
700
115
mVp-p
1
ZSATA_TXDIFFIM
Ω
—
Note:
1. Terminated by 50 Ω load.
This table provides the differential transmitter output AC characteristics for the SATA interface at Gen2i
or 3.0 Gbits/s transmission.
Table 58. Gen 2i/3G Transmitter AC Specifications
Parameter
Channel speed
Symbol
Min
Typical
Max
Units
Note
tCH_SPEED
TUI
—
333.2
—
3.0
333.33
—
—
335.11
0.3
Gbps
ps
—
—
1
Unit interval
Total jitter
USATA_TXTJfB/10
UIp-p
fC3dB=fBAUD/10
Total jitter
USATA_TXTJfB/500
—
—
0.37
UIp-p
1
fC3dB = fBAUD/500
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
70
Table 58. Gen 2i/3G Transmitter AC Specifications (continued)
Parameter
Symbol
Min
Typical
Max
Units
Note
Total jitter
USATA_TXTJfB/1667
—
—
0.55
UIp-p
1
fC3dB = fBAUD/1667
Deterministic jitter
fC3dB = fBAUD/10
USATA_TXDJfB/10
USATA_TXDJfB/500
USATA_TXDJfB/1667
—
—
—
—
—
—
0.17
0.19
0.35
UIp-p
UIp-p
UIp-p
1
1
1
Deterministic jitter
fC3dB = fBAUD/500
Deterministic jitter
fC3dB = fBAUD/1667
Note:
1. Measured at Tx output pins peak to peak phase variation, random data pattern.
16.3 Differential Receiver (Rx) Input Characteristics
This section discusses the Gen1i/1.5G and Gen2i/3G differential receiver input AC characteristics.
16.3.1 Gen1i/1.5G Receiver Specifications
This table provides the Gen1i or 1.5 Gbits/s differential receiver input DC characteristics for the SATA
interface.
Table 59. Gen1i/1.5G Receiver Input DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Note
Differential input voltage
Differential Rx input impedance
Note:
VSATA_RXDIFF
ZSATA_RXSEIM
240
85
500
100
600
115
mVp-p
1
Ω
—
1. Voltage relative to common of either signal comprising a differential pair.
This table provides the Gen1i or 1.5 Gbits/s differential receiver input AC characteristics for the SATA
interface.
Table 60. Gen 1i/1.5G Receiver AC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Note
Unit interval
TUI
666.4333
—
666.667
—
670.2333
0.43
ps
—
1
Total jitter, data-data
5 UI
USATA_TXTJ5UI
UIp-p
Total jitter, data-data
250 UI
USATA_TXTJ250UI
—
—
—
—
0.60
0.25
UIp-p
UIp-p
1
1
Deterministic jitter, data-data
5 UI
USATA_TXDJ5UI
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
71
Table 60. Gen 1i/1.5G Receiver AC Specifications (continued)
Parameter
Symbol
Min
Typical
Max
Units
Note
Deterministic jitter, data-data
250 UI
USATA_TXDJ250UI
—
—
0.35
UIp-p
1
Note:
1. Measured at Tx output pins peak to peak phase variation, random data pattern.
16.3.2 Gen2i/3G Receiver (Rx) Specifications
This table provides the Gen2i or 3 Gbits/s differential receiver input DC characteristics for the SATA
interface.
Table 61. Gen2i/3G Receiver Input DC Specifications
Parameter
Symbol
Min
Typical
Max
Units
Note
Differential input voltage
Differential RX input impedance
Note:
VSATA_RXDIFF
ZSATA_RXSEIM
275
85
500
100
750
115
mVp-p
1
Ω
—
1. Voltage relative to common of either signal comprising a differential pair.
This table provides the differential receiver output AC characteristics for the SATA interface at Gen2i or
3.0 Gbits/s transmission.
Table 62. Gen 2i/3G Receiver AC Specifications
Parameter
Channel Speed
Symbol
Min
Typical
Max
Units
Note
tCH_SPEED
TUI
—
333.2
—
3.0
333.33
—
—
Gbps
ps
—
—
1
Unit Interval
335.11
0.46
Total jitter
USATA_TXTJfB/10
UIp-p
fC3dB = fBAUD/10
Total jitter
fC3dB = fBAUD/500
USATA_TXTJfB/500
USATA_TXTJfB/1667
USATA_TXDJfB/10
USATA_TXDJfB/500
USATA_TXDJfB/1667
—
—
—
—
—
—
—
—
—
—
0.60
0.65
0.35
0.42
0.35
UIp-p
UIp-p
UIp-p
UIp-p
UIp-p
1
1
1
1
1
Total jitter
fC3dB = fBAUD/1667
Deterministic jitter
fC3dB = fBAUD/10
Deterministic jitter
fC3dB = fBAUD/500
Deterministic jitter
fC3dB = fBAUD/1667
Note:
1. Measured at Tx output pins peak to peak phase variation, random data pattern.
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17 Timers
This section describes the DC and AC electrical specifications for the timers of the chip.
17.1 Timers DC Electrical Characteristics
This table provides the DC electrical characteristics for the device timers pins, including TIN, TOUT,
TGATE, and RTC_CLK.
Table 63. Timers DC Electrical Characteristics
Parameter
Output high voltage
Condition
Symbol
Min
Max
Unit
IOH = –6.0 mA
IOL = 6.0 mA
VOH
VOL
2.4
—
—
0.5
V
V
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
I
= 3.2 mA
V
—
0.4
V
OL
OL
—
—
VIH
VIL
IIN
2.0
–0.3
—
OVDD + 0.3
0.8
V
V
0 V ≤ VIN ≤ OVDD
30
μA
17.2 Timers AC Timing Specifications
This table provides the timers input and output AC timing specifications.
1
Table 64. Timers Input AC Timing Specifications
Parameter
Symbol 2
tTIWID
Min
Unit
Timers inputs—minimum pulse width
Notes:
20
ns
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
measured at the pin.
2. Timers inputs and outputs are asynchronous to any visible clock. Timers outputs should be synchronized before use by any
external synchronous logic. Timers inputs are required to be valid for at least tTIWID ns to ensure proper operation
This figure provides the AC test load for the timers.
Output
OVDD/2
Z0 = 50 Ω
RL = 50 Ω
Figure 46. Timers AC Test Load
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18 GPIO
This section describes the DC and AC electrical specifications for the GPIO of the chip.
18.1 GPIO DC Electrical Characteristics
This table provides the DC electrical characteristics for the device GPIO.
Table 65. GPIO DC Electrical Characteristics
This specification applies when operating at 3.3 V 165 mV supply.
Parameter
Output high voltage
Condition
Symbol
Min
Max
Unit
IOH = –6.0 mA
IOL = 6.0 mA
VOH
VOL
2.4
—
—
0.5
V
V
Output low voltage
Output low voltage
Input high voltage
Input low voltage
Input current
I
= 3.2 mA
V
—
0.4
V
OL
OL
—
—
VIH
VIL
IIN
2.0
–0.3
—
OVDD + 0.3
0.8
V
V
0 V ≤ VIN ≤ OVDD
30
μA
18.2 GPIO AC Timing Specifications
This table provides the GPIO input and output AC timing specifications.
Table 66. GPIO Input AC Timing Specifications
Parameter
Symbol
Min
20
Unit
ns
GPIO inputs—minimum pulse width
Notes:
tPIWID
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of SYS_CLKIN. Timings
are measured at the pin.
2. GPIO inputs and outputs are asynchronous to any visible clock. GPIO outputs should be synchronized before use by any
external synchronous logic. GPIO inputs are required to be valid for at least tPIWID ns to ensure proper operation.
This figure provides the AC test load for the GPIO.
OVDD/2
Output
Z0 = 50 Ω
RL = 50 Ω
Figure 47. GPIO AC Test Load
19 IPIC
This section describes the DC and AC electrical specifications for the external interrupt pins of the chip.
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19.1 IPIC DC Electrical Characteristics
This table provides the DC electrical characteristics for the external interrupt pins of the chip.
Table 67. IPIC DC Electrical Characteristics
Parameter
Input high voltage
Condition
Symbol
Min
Max
Unit
—
VIH
VIL
IIN
2.0
–0.3
—
OVDD + 0.3
V
V
Input low voltage
Input current
—
—
0.8
30
μA
V
Output low voltage
Output low voltage
Note:
IOL = 6.0 mA
VOL
—
0.5
0.4
I
= 3.2 mA
V
—
V
OL
OL
1. This table applies for pins IRQ[0:7], IRQ_OUT, MCP_OUT.
2. IRQ_OUT and MCP_OUT are open drain pins, thus VOH is not relevant for those pins.
19.2 IPIC AC Timing Specifications
This table provides the IPIC input and output AC timing specifications.
Table 68. IPIC Input AC Timing Specifications
Parameter
Symbol
Min
Unit
IPIC inputs—minimum pulse width
tPIWID
20
ns
Note:
1. Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of CLKIN. Timings are
measured at the pin.
2. IPIC inputs and outputs are asynchronous to any visible clock. IPIC outputs should be synchronized before use by any
external synchronous logic. IPIC inputs are required to be valid for at least tPIWID ns to ensure proper operation when working
in edge triggered mode.
20 SPI
This section describes the DC and AC electrical specifications for the SPI of the chip.
20.1 SPI DC Electrical Characteristics
This table provides the DC electrical characteristics for the device SPI.
Table 69. SPI DC Electrical Characteristics
Parameter
Input high voltage
Condition
Symbol
Min
Max
Unit
—
VIH
VIL
2.0
–0.3
—
OVDD + 0.3
V
V
Input low voltage
Input current
—
—
0.8
30
—
IIN
μA
V
Output high voltage
IOH = –8.0 mA
VOH
2.4
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Table 69. SPI DC Electrical Characteristics (continued)
Parameter
Condition
Symbol
Min
Max
Unit
Output low voltage
Output low voltage
IOL = 8.0 mA
VOL
—
—
0.5
0.4
V
V
I
= 3.2 mA
V
OL
OL
20.2 SPI AC Timing Specifications
This table provides the SPI input and output AC timing specifications.
Table 70. SPI AC Timing Specifications
Parameter
Symbol1
Min
Max
Unit
SPI outputs—Master mode (internal clock) delay
SPI outputs—Slave mode (external clock) delay
SPI inputs—Master mode (internal clock) input setup time
SPI inputs—Master mode (internal clock) input hold time
SPI inputs—Slave mode (external clock) input setup time
SPI inputs—Slave mode (external clock) input hold time
Notes:
tNIKHOV
tNEKHOV
tNIIVKH
0.5
2
6
ns
ns
ns
ns
ns
ns
8
4
—
—
—
—
tNIIXKH
0
tNEIVKH
tNEIXKH
4
2
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the internal
timing (NI) for the time SPICLK clock reference (K) goes to the high state (H) until outputs (O) are invalid (X).
2. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin. The maximum SPICLK input frequency is 66.666 MT/s.
This figure provides the AC test load for the SPI.
Output
OVDD/2
Z0 = 50 Ω
RL = 50 Ω
Figure 48. SPI AC Test Load
These figures represent the AC timing from Table 70. Note that although the specifications generally
reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge is the
active edge.
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This figure shows the SPI timing in slave mode (external clock).
SPICLK (input)
tNEIXKH
tNEIVKH
Input Signals:
SPIMOSI
(See Note)
tNEKHOV
Output Signals:
SPIMISO
(See Note)
Note: The clock edge is selectable on SPI.
Figure 49. SPI AC Timing in Slave Mode (External Clock) Diagram
This figure shows the SPI timing in master mode (internal clock).
SPICLK (output)
tNIIXKH
tNIIVKH
Input Signals:
SPIMISO
(See Note)
tNIKHOV
Output Signals:
SPIMOSI
(See Note)
Note: The clock edge is selectable on SPI.
Figure 50. SPI AC Timing in Master Mode (Internal Clock) Diagram
21 High-Speed Serial Interfaces (HSSI)
This chip features two serializer/deserializer (SerDes) interfaces to be used for high-speed serial
interconnect applications. See Table 1 for the interfaces supported.
This section describes the common portion of SerDes DC electrical specifications, which is the DC
requirement for SerDes reference clocks. The SerDes data lane’s transmitter and receiver reference circuits
are also shown.
21.1 Signal Terms Definition
The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms
used in the description and specification of differential signals.
Figure 51 shows how the signals are defined. For illustration purpose, only one SerDes lane is used for
description. The figure shows waveform for either a transmitter output (SDn_TX and SDn_TX) or a
receiver input (SDn_RX and SDn_RX). Each signal swings between A volts and B volts where A > B.
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Using this waveform, the definitions are as follows. To simplify illustration, the following definitions
assume that the SerDes transmitter and receiver operate in a fully symmetrical differential signaling
environment.
•
•
•
Single-Ended Swing
The transmitter output signals and the receiver input signals SDn_TX, SDn_TX, SDn_RX and
SDn_RX each have a peak-to-peak swing of A – B volts. This is also referred as each signal wire’s
single-ended swing.
Differential Output Voltage, V (or Differential Output Swing):
OD
The differential output voltage (or swing) of the transmitter, V , is defined as the difference of
the two complimentary output voltages: V
or negative.
OD
– V
. The V value can be either positive
SDn_TX
SDn_TX OD
Differential Input Voltage, V (or Differential Input Swing):
ID
The differential input voltage (or swing) of the receiver, V , is defined as the difference of the two
ID
complimentary input voltages: V
negative.
– V
The V value can be either positive or
SDn_RX
SDn_RX. ID
•
•
Differential Peak Voltage, V
DIFFp
The peak value of the differential transmitter output signal or the differential receiver input signal
is defined as differential peak voltage, V = |A – B| volts.
DIFFp
Differential Peak-to-Peak, V
DIFFp-p
Since the differential output signal of the transmitter and the differential input signal of the receiver
each range from A – B to –(A – B) volts, the peak-to-peak value of the differential transmitter
output signal or the differential receiver input signal is defined as differential peak-to-peak voltage,
V
= 2 × V
= 2 × |(A – B)| volts, which is twice of differential swing in amplitude, or
DIFFp-p
DIFFp
twice of the differential peak. For example, the output differential peak-peak voltage can also be
calculated as V = 2 × |V |.
TX-DIFFp-p
OD
•
•
Differential Waveform
The differential waveform is constructed by subtracting the inverting signal (SDn_TX, for
example) from the non-inverting signal (SDn_TX, for example) within a differential pair. There is
only one signal trace curve in a differential waveform. The voltage represented in the differential
waveform is not referenced to ground. Refer to Figure 60 as an example for differential waveform.
Common Mode Voltage, V
cm
The common mode voltage is equal to one half of the sum of the voltages between each conductor
of a balanced interchange circuit and ground. In this example, for SerDes output,
V
= (V
+ V
) ÷ 2 = (A + B) ÷ 2, which is the arithmetic mean of the two
cm_out
SDn_TX
SDn_TX
complimentary output voltages within a differential pair. In a system, the common mode voltage
may often differ from one component’s output to the other’s input. Sometimes it may be even
different between the receiver input and driver output circuits within the same component. It is also
referred as the DC offset in some occasion.
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SDn_TX or
SDn_RX
A Volts
B Volts
Vcm = (A + B)/2
SDn_TXor
SDn_RX
Differential Swing, VID or VOD = A – B
Differential Peak Voltage, VDIFFp = ꢀA – Bꢀ
Differential Peak-Peak Voltage, VDIFFpp = 2 × VDIFFp (not shown)
Figure 51. Differential Voltage Definitions for Transmitter or Receiver
To illustrate these definitions using real values, consider the case of a CML (Current Mode Logic)
transmitter that has a common mode voltage of 2.25 V and each of its outputs, TD and TD, has a swing
that goes between 2.5 V and 2.0 V. Using these values, the peak-to-peak voltage swing of each signal (TD
or TD) is 500 mV , which is referred as the single-ended swing for each signal. In this example, since
p-p
the differential signaling environment is fully symmetrical, the transmitter output’s differential swing
(V ) has the same amplitude as each signal’s single-ended swing. The differential output signal ranges
OD
between 500 mV and –500 mV, in other words, V is 500 mV in one phase and –500 mV in the other
OD
phase. The peak differential voltage (V
) is 500 mV. The peak-to-peak differential voltage (V
)
DIFFp
DIFFp-p
is 1000 mV
.
p-p
21.2 SerDes Reference Clocks
The SerDes reference clock inputs are applied to an internal PLL whose output creates the clock used by
the corresponding SerDes lanes. The SerDes reference clocks inputs are SD1_REF_CLK and
SD1_REF_CLK for both lanes of SerDes1, and SD2_REF_CLK and SD2_REF_CLK for both lanes of
SerDes2.
The following sections describe the SerDes reference clock requirements and some application
information.
21.2.1 SerDes Reference Clock Receiver Characteristics
Figure 52 shows a receiver reference diagram of the SerDes reference clocks.
•
SerDes Reference Clock Receiver Reference Circuit Structure
— The SDn_REF_CLK and SDn_REF_CLK are internally AC-coupled differential inputs as
shown in Figure 52. Each differential clock input (SDn_REF_CLK or SDn_REF_CLK) has a
50 Ω termination to SGND_SRDSn (xcorevss) followed by on-chip AC-coupling.
— The external reference clock driver must be able to drive this termination.
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— The SerDes reference clock input can be either differential or single-ended. Refer to the
Differential Mode and Single-ended Mode description below for further detailed requirements.
•
The maximum average current requirement that also determines the common mode voltage range
— When the SerDes reference clock differential inputs are DC coupled externally with the clock
driver chip, the maximum average current allowed for each input pin is 8 mA. In this case, the
exact common mode input voltage is not critical as long as it is within the range allowed by the
maximum average current of 8 mA (refer to the following bullet for more detail), since the
input is AC-coupled on-chip.
— This current limitation sets the maximum common mode input voltage to be less than 0.4 V
(0.4 V ÷ 50 = 8 mA) while the minimum common mode input level is 0.1 V above
SGND_SRDSn (xcorevss). For example, a clock with a 50/50 duty cycle can be produced by
a clock driver with output driven by its current source from 0 mA to 16 mA (0–0.8 V), such
that each phase of the differential input has a single-ended swing from 0 V to 800 mV with the
common mode voltage at 400 mV.
— If the device driving the SDn_REF_CLK and SDn_REF_CLK inputs cannot drive 50 Ω to
SGND_SRDSn (xcorevss) DC, or it exceeds the maximum input current limitations, then it
must be AC-coupled off-chip.
•
The input amplitude requirement
— This requirement is described in detail in the following sections.
50 Ω
SDn_REF_CLK
Input
Amp
SDn_REF_CLK
50 Ω
Figure 52. Receiver of SerDes Reference Clocks
21.2.2 DC Level Requirement for SerDes Reference Clocks
The DC level requirement for the device SerDes reference clock inputs is different depending on the
signaling mode used to connect the clock driver chip and SerDes reference clock inputs as described
below.
•
Differential Mode
— The input amplitude of the differential clock must be between 400 mV and 1600 mV
differential peak-peak (or between 200 mV and 800 mV differential peak). In other words,
each signal wire of the differential pair must have a single-ended swing less than 800 mV and
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greater than 200 mV. This requirement is the same for both external DC-coupled or
AC-coupled connection.
— For external DC-coupled connection, as described in Section 21.2.1, “SerDes Reference
Clock Receiver Characteristics,” the maximum average current requirements sets the
requirement for average voltage (common mode voltage) to be between 100 mV and 400 mV.
Figure 53 shows the SerDes reference clock input requirement for DC-coupled connection
scheme.
— For external AC-coupled connection, there is no common mode voltage requirement for the
clock driver. Since the external AC-coupling capacitor blocks the DC level, the clock driver
and the SerDes reference clock receiver operate in different command mode voltages. The
SerDes reference clock receiver in this connection scheme has its common mode voltage set to
SGND_SRDSn. Each signal wire of the differential inputs is allowed to swing below and above
the command mode voltage (SGND_SRDSn). Figure 54 shows the SerDes reference clock
input requirement for AC-coupled connection scheme.
•
Single-ended Mode
— The reference clock can also be single-ended. The SD _REF_CLK input amplitude
(single-ended swing) must be between 400 mV and 800 mV (from V to V ) with
p-p
min
max
SDn_REF_CLK either left unconnected or tied to ground.
— The SDn_REF_CLK input average voltage must be between 200 mV and 400 mV. Figure 55
shows the SerDes reference clock input requirement for single-ended signaling mode.
— To meet the input amplitude requirement, the reference clock inputs might need to be DC or
AC-coupled externally. For the best noise performance, the reference of the clock could be DC
or AC-coupled into the unused phase (SDn_REF_CLK) through the same source impedance as
the clock input (SDn_REF_CLK) in use.
200 mV < Input Amplitude or Differential Peak < 800 mV
SDn_REF_CLK
Vmax < 800 mV
100 mV < Vcm < 400 mV
Vmin > 0 V
SDn_REF_CLK
Figure 53. Differential Reference Clock Input DC Requirements (External DC-Coupled)
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200 mV < Input Amplitude or Differential Peak < 800 mV
SDn_REF_CLK
SDn_REF_CLK
150
fdafdVmax < Vcm + 400 mV
Vmax < Vcm + 400 mV
Vcm
Vmin > Vcm – 400m V
Figure 54. Differential Reference Clock Input DC Requirements (External AC-Coupled)
400 mV < SDn_REF_CLK Input Amplitude < 800 mV
SDn_REF_CLK
0 V
SDn_REF_CLK
Figure 55. Single-Ended Reference Clock Input DC Requirements
21.2.3 Interfacing With Other Differential Signaling Levels
The following list provides information about interfacing with other differential signaling levels.
•
With on-chip termination to SGND_SRDSn (xcorevss), the differential reference clocks inputs are
HCSL (high-speed current steering logic) compatible DC-coupled.
•
Many other low voltage differential type outputs like LVDS (low voltage differential signaling) can
be used but may need to be AC-coupled due to the limited common mode input range allowed
(100 mV to 400 mV) for DC-coupled connection.
•
LVPECL outputs can produce signal with too large amplitude and may need to be DC-biased at
clock driver output first, then followed with series attenuation resistor to reduce the amplitude, in
addition to AC-coupling.
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NOTE
Figure 56 to Figure 59 below are for conceptual reference only. Due to the
fact that clock driver chip's internal structure, output impedance, and
termination requirements are different between various clock driver chip
manufacturers, it is very possible that the clock circuit reference designs
provided by the clock driver chip vendor are different from what is shown
below. They might also vary from one vendor to the other. Therefore,
Freescale Semiconductor can neither provide the optimal clock driver
reference circuits, nor guarantee the correctness of the following clock
driver connection reference circuits. The system designer is recommended
to contact the selected clock driver chip vendor for the optimal reference
circuits with the device SerDes reference clock receiver requirement
provided in this document.
This figure shows the SerDes reference clock connection reference circuits for HCSL type clock driver. It
assumes that the DC levels of the clock driver chip is compatible with device SerDes reference clock
input’s DC requirement.
Chip
HCSL CLK Driver Chip
50 Ω
SDn_REF_CLK
CLK_Out
33 Ω
33 Ω
SerDes Refer.
CLK Receiver
100 Ω differential PWB trace
Clock Driver
CLK_Out
SDn_REF_CLK
50 Ω
Clock driver vendor dependent
source termination resistor
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
Figure 56. DC-Coupled Differential Connection with HCSL Clock Driver (Reference Only)
This figure shows the SerDes reference clock connection reference circuits for LVDS type clock driver.
Since LVDS clock driver’s common-mode voltage is higher than the device SerDes reference clock input’s
allowed range (100 to 400 mV), AC-coupled connection scheme must be used. It assumes the LVDS
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output driver features a 50-Ω termination resistor. It also assumes that the LVDS transmitter establishes its
own common mode level without relying on the receiver or other external component.
Chip
LVDS CLK Driver Chip
50
Ω
SDn_REF_CLK
SDn_REF_CLK
10 nF
CLK_Out
SerDes Refer.
CLK Receiver
100 Ω differential PWB trace
Clock Driver
CLK_Out
10 nF
50 Ω
Figure 57. AC-Coupled Differential Connection with LVDS Clock Driver (Reference Only)
Figure 58 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.
Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with
device SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 58 assumes
that the LVPECL clock driver’s output impedance is 50 Ω. R1 is used to DC-bias the LVPECL outputs
prior to AC-coupling. Its value could be ranged from 140 Ω to 240 Ω depending on clock driver vendor’s
requirement. R2 is used together with the SerDes reference clock receiver’s 50 Ω termination resistor to
attenuate the LVPECL output’s differential peak level such that it meets the device SerDes reference
clock’s differential input amplitude requirement (between 200 mV and 800 mV differential peak). For
example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock input
amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires R2 = 25 Ω. Consult clock
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driver chip manufacturer to verify whether this connection scheme is compatible with a particular clock
driver chip.
Chip
LVPECL CLK Driver Chip
50 Ω
SDn_REF_CLK
CLK_Out
10 nF
R2
SerDes Refer.
CLK Receiver
R1
R1
100 Ω differential PWB trace
10 nF
Clock Driver
R2
SDn_REF_CLK
CLK_Out
50 Ω
Figure 58. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)
This figure shows the SerDes reference clock connection reference circuits for a single-ended clock driver.
It assumes the DC levels of the clock driver are compatible with device SerDes reference clock input’s DC
requirement.
Single-Ended CLK
Driver Chip
Chip
Total 50 Ω. Assume clock driver’s
output impedance is about 16 Ω.
50 Ω
SDn_REF_CLK
33 Ω
Clock Driver
CLK_Out
SerDes Refer.
CLK Receiver
100 Ω differential PWB trace
SDn_REF_CLK
50 Ω
50 Ω
Figure 59. Single-Ended Connection (Reference Only)
21.2.4 AC Requirements for SerDes Reference Clocks
The clock driver selected should provide a high quality reference clock with low phase noise and
cycle-to-cycle jitter. Phase noise less than 100 KHz can be tracked by the PLL and data recovery loops and
is less of a problem. Phase noise above 15 MT/s is filtered by the PLL. The most problematic phase noise
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occurs in the 1–15 MT/s range. The source impedance of the clock driver should be 50 Ω to match the
transmission line and reduce reflections which are a source of noise to the system.
This table describes some AC parameters for PCI Express .
Table 71. SerDes Reference Clock Common AC Parameters
At recommended operating conditions with XVDD_SRDS or XVDD_SRDS = 1.0 V 5%.
Parameter
Symbol
Min
Max
Unit
Note
Rising Edge Rate
Falling Edge Rate
Rise Edge Rate
Fall Edge Rate
VIH
1.0
1.0
200
—
4.0
4.0
—
V/ns
V/ns
mV
mV
%
2, 3
2, 3
2
Differential Input High Voltage
Differential Input Low Voltage
VIL
–200
20
2
Rising edge rate (SDn_REF_CLK) to falling edge rate
(SDn_REF_CLK) matching
Rise-Fall Matching
—
1, 4
Notes:
1. Measurement taken from single ended waveform.
2. Measurement taken from differential waveform.
3. Measured from –200 mV to +200 mV on the differential waveform (derived from SDn_REF_CLK minus SDn_REF_CLK).
The signal must be monotonic through the measurement region for rise and fall time. The 400 mV measurement window is
centered on the differential zero crossing. See Figure 60.
4. Matching applies to rising edge rate for SDn_REF_CLK and falling edge rate for SDn_REF_CLK. It is measured using a
200 mV window centered on the median cross point where SDn_REF_CLK rising meets SDn_REF_CLK falling. The
median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations. The
Rise Edge Rate of SDn_REF_CLK should be compared to the Fall Edge Rate of SDn_REF_CLK, the maximum allowed
difference should not exceed 20% of the slowest edge rate. See Figure 61.
Rise Edge Rate
Fall Edge Rate
VIH = +200 mV
0.0 V
VIL = –200 mV
SDn_REF_CLK
Minus
SDn_REF_CLK
Figure 60. Differential Measurement Points for Rise and Fall Time
TFALL TRISE
SDn_REF_CLK
SDn_REF_CLK
VCROSS MEDIAN +100 mV
VCROSS MEDIAN
VCROSS MEDIAN
VCROSS MEDIAN –100 mV
SDn_REF_CLK
SDn_REF_CLK
Figure 61. Single-Ended Measurement Points for Rise and Fall Time Matching
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21.3 SerDes Transmitter and Receiver Reference Circuits
This figure shows the reference circuits for SerDes data lane’s transmitter and receiver.
SD1_RXn or
SD2_RXn
SD1_TXn or
SD2_TXn
50
50
Ω
Ω
50 Ω
50 Ω
Receiver
Transmitter
SD1_TXn or
SD2_TXn
SD1_RXn or
SD2_RXn
Figure 62. SerDes Transmitter and Receiver Reference Circuits
The DC and AC specification of SerDes data lanes are defined in each interface protocol section below in
this document based on the application usage:
•
•
•
Section 8, “Ethernet: Enhanced Three-Speed Ethernet (eTSEC)”
Section 15, “PCI Express”
Section 16, “Serial ATA (SATA)”
Note that an external AC coupling capacitor is required for the above three serial transmission protocols
with the capacitor value defined in specification of each protocol section.
22 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions.
22.1 Package Parameters for the MPC8377E TePBGA II
The package parameters are provided in the following list. The package type is 31 mm × 31 mm,
689 plastic ball grid array (TePBGA II).
Package outline
Interconnects
31 mm × 31 mm
689
Pitch
1.00 mm
Module height (typical)
Solder Balls
2.0 mm to 2.46 mm (maximum)
3.5% Ag, 96.5% Sn
0.60 mm
Ball diameter (typical)
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This figure shows the mechanical dimensions and bottom surface nomenclature of the TEPBGA II
package.
Figure 63. Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II
Note:
1
All dimensions are in millimeters.
2
Dimensioning and tolerancing per ASME Y14. 5M-1994.
3
Maximum solder ball diameter measured parallel to Datum A.
4
Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
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Freescale Semiconductor
5
Parallelism measurement should exclude any effect of mark on top surface of package.
22.2 Pinout Listings
This table provides the pinout listing for the TePBGA II package.
Table 72. TePBGA II Pinout Listing
Signal
Package Pin Number
Clock Signals
Pin Type
Power Supply
Note
CLKIN
PCI_CLK/PCI_SYNC_IN
PCI_SYNC_OUT
PCI_CLK0
K24
C10
N24
L24
I
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
3
I
O
O
O
O
O
O
I
—
—
—
—
—
—
PCI_CLK1
M24
M25
M26
L26
PCI_CLK2
PCI_CLK3
PCI_CLK4
RTC/PIT_CLOCK
AF11
DDR SDRAM Memory Interface
MA0
MA1
U3
U1
T5
T3
T2
T1
R1
P2
P1
N4
V3
M5
N1
M2
M1
U5
U4
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
MBA0
MBA1
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Table 72. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Note
MBA2
MCAS_B
MCK_B0
MCK_B1
MCK_B2
MCK_B3
MCK_B4
MCK_B5
MCK0
M3
W5
H1
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
O
O
O
O
O
O
O
O
O
I/O
I/O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
3
K1
V1
W2
AA1
AB2
J1
MCK1
L1
MCK2
V2
MCK3
W1
Y1
MCK4
MCK5
AB1
M4
R5
MCKE0
MCKE1
MCS_B0
MCS_B1
MCS_B2
MCS_B3
MDIC0
MDIC1
MDM0
3
W3
P3
—
—
—
—
9
T4
R4
AH8
AJ8
B6
9
—
—
—
—
—
—
—
—
—
11
11
MDM1
B2
MDM2
E2
MDM3
E1
MDM4
Y6
MDM5
AC6
AE6
AJ4
L6
MDM6
MDM7
MDM8
MDQ0
A8
MDQ1
A6
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Table 72. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Note
MDQ2
MDQ3
C7
D8
A7
A5
A3
C6
D7
E8
B1
D5
B3
D6
C3
C2
D4
E6
F6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
MDQ4
MDQ5
MDQ6
MDQ7
MDQ8
MDQ9
MDQ10
MDQ11
MDQ12
MDQ13
MDQ14
MDQ15
MDQ16
MDQ17
MDQ18
MDQ19
MDQ20
MDQ21
MDQ22
MDQ23
MDQ24
MDQ25
MDQ26
MDQ27
MDQ28
MDQ29
MDQ30
MDQ31
MDQ32
MDQ33
MDQ34
G4
F8
E4
C1
G6
F2
G5
H6
H4
D1
G3
H5
F1
W6
AC1
AC3
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Table 72. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Note
MDQ35
MDQ36
MDQ37
MDQ38
MDQ39
MDQ40
MDQ41
MDQ42
MDQ43
MDQ44
MDQ45
MDQ46
MDQ47
MDQ48
MDQ49
MDQ50
MDQ51
MDQ52
MDQ53
MDQ54
MDQ55
MDQ56
MDQ57
MDQ58
MDQ59
MDQ60
MDQ61
MDQ62
MDQ63
MDQS0
MDQS1
MDQS2
MDQS3
AE1
V6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
11
Y5
AA4
AB6
AD3
AC4
AD4
AF1
AE4
AC5
AE2
AE3
AG1
AG2
AG3
AF5
AE5
AD7
AH2
AG4
AH3
AG5
AF8
AJ5
AF6
AF7
AH6
AH7
C8
C4
E3
G2
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Table 72. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Note
MDQS4
MDQS5
AB5
AD1
AH1
AJ3
G1
J6
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
GVDD
11
11
11
11
11
—
—
—
—
—
—
—
—
6
MDQS6
MDQS7
MDQS8
MECC0/MSRCID0
MECC1/MSRCID1
MECC2/MSRCID2
MECC3/MSRCID3
MECC4/MSRCID4
MECC5/MDVAL
MECC6
J3
K2
K3
J5
J2
L5
MECC7
L2
MODT0
N5
U6
M6
P6
MODT1
O
6
MODT2
O
6
MODT3
O
6
MRAS_B
AA3
K4
O
—
11
11
—
MVREF1
I
MVREF2
W4
Y2
I
MWE_B
O
DUART Interface
UART_SIN1/
MSRCID2/LSRCID2
L28
L27
K26
I/O
O
OVDD
OVDD
OVDD
—
—
—
UART_SOUT1/
MSRCID0/LSRCID0
UART_CTS_B[1]/
I/O
MSRCID4/LSRCID4
UART_RTS_B1
N27
K27
O
OVDD
OVDD
—
—
UART_SIN2/
I/O
MSRCID3/LSRCID3
UART_SOUT2/
MSRCID1/LSRCID1
K28
K29
O
OVDD
OVDD
—
—
UART_CTS_B[2]/
MDVAL/LDVAL
I/O
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Freescale Semiconductor
93
Table 72. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Note
UART_RTS_B[2]
L29
O
OVDD
—
Enhanced Local Bus Controller (eLBC) Interface
LAD0
LAD1
E24
G28
H25
F26
C26
J28
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
LAD2
LAD3
LAD4
LAD5
LAD6
F21
F23
E25
E26
A23
F24
G24
F25
H28
G25
F27
B21
A25
C28
H24
E23
B28
D28
A27
C25
B27
H27
E21
F20
LAD7
LAD8
LAD9
LAD10
LAD11
LAD12
LAD13
LAD14
LAD15
LA11/LAD16
LA12/LAD17
LA13/LAD18
LA14/LAD19
LA15/LAD20
LA16/LAD21
LA17/LAD22
LA18/LAD23
LA19/LAD24
LA20/LAD25
LA21/LAD26
LA22/LAD27
LA23/LAD28
LA24/LAD29
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Table 72. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Note
LA25/LAD30
LA26/LAD31
LA27
D29
E20
H26
C29
E28
B26
J25
I/O
I/O
O
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
16
LA28
O
LA29
O
LA30
O
LA31
O
LA10/LALE
LBCTL
H29
A22
B22
C23
B23
D25
F19
C27
D24
C24
B29
E29
F29
D21
A26
F22
C21
J29
O
O
LCLK0
O
LCLK1
O
LCLK2
O
LCS_B0
O
LCS_B1
O
LCS_B2
O
LCS_B3
O
LCS_B4/LDP0
LCS_B5/LDP1
LA7/LCS_B6/LDP2
LA8/LCS_B7/LDP3
LFCLE/LGPL0
LFALE/LGPL1
LFRE_B/LGPL2/LOE_B
LFWP_B/LGPL3
I/O
I/O
I/O
I/O
O
O
O
O
LGPL4/LFRB_B/LGTA_B/
LUPWAIT/LPBSE
I/O
LA9/LGPL5
G29
A21
D23
E22
B25
E27
F28
O
I
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
LBVDD
—
—
—
—
—
—
—
LSYNC_IN
LSYNC_OUT
O
O
O
O
O
LWE_B0/LFWE0/LBS_B0
LWE_B1/LFWE1/LBS_B1
LWE_B2/LFWE2/LBS_B2
LWE_B3/LFWE3/LBS_B3
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Table 72. TePBGA II Pinout Listing (continued)
Package Pin Number Pin Type
eTSEC1/GPIO1/GPIO2/CFG_RESET Interface
I/O
Signal
Power Supply
Note
TSEC1_COL/GPIO2[20]
TSEC1_CRS/GPIO2[21]
TSEC1_GTX_CLK
TSEC1_RX_CLK
AF22
AE20
AJ25
AG22
AD19
AD20
AD22
AE21
AE22
AD21
AJ22
AG23
AH22
AD23
LVDD1
LVDD1
LVDD1
LVDD1
LVDD1
LVDD1
LVDD1
LVDD1
LVDD1
LVDD1
LVDD1
LVDD1
LVDD1
LVDD1
16
16
16
16
16
16
16
16
16
16
16
16
16
16
I/O
O
I
TSEC1_RX_DV
I
TSEC1_RX_ER/GPIO2[25]
TSEC1_RXD0
I/O
I
TSEC1_RXD1
I
I
TSEC1_RXD2
TSEC1_RXD3
I
TSEC1_TX_CLK
I
TSEC1_TX_EN
O
I/O
I/O
TSEC1_TX_ER/CFG_LBMUX
TSEC1_TXD0/
CFG_RESET_SOURCE[0]
TSEC1_TXD1/
CFG_RESET_SOURCE[1]
AE23
AF23
AJ24
I/O
I/O
I/O
LVDD1
LVDD1
LVDD1
16
16
16
TSEC1_TXD2/
CFG_RESET_SOURCE[2]
TSEC1_TXD3/
CFG_RESET_SOURCE[3]
EC_GTX_CLK125
EC_MDC/CFG_CLKIN_DIV
EC_MDIO
AH24
AJ21
AH21
I
LVDD1
LVDD1
LVDD1
16
16
16
I/O
I/O
eTSEC2/GPIO1 Interface
TSEC2_COL/GPIO1[21]/
TSEC1_TMR_TRIG1
AJ27
I/O
I/O
LVDD2
LVDD2
16
16
TSEC2_CRS/GPIO1[22]/
TSEC1_TMR_TRIG2
AG29
TSEC2_GTX_CLK
AF28
AF25
O
I
LVDD2
LVDD2
16
16
TSEC2_RX_CLK/
TSEC1_TMR_CLK
TSEC2_RX_DV/GPIO1[23]
TSEC2_RX_ER/GPIO1[25]
AF26
AG25
I/O
I/O
LVDD2
LVDD2
16
16
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Freescale Semiconductor
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Table 72. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Note
TSEC2_RXD0/GPIO1[16]
TSEC2_RXD1/GPIO1[15]
TSEC2_RXD2/GPIO1[14]
TSEC2_RXD3/GPIO1[13]
AE28
AE29
AH26
AH25
AG28
I/O
I/O
I/O
I/O
I/O
LVDD2
LVDD2
LVDD2
LVDD2
LVDD2
16
16
16
16
16
TSEC2_TX_CLK/GPIO2[24]/
TSEC1_TMR_GCLK
TSEC2_TX_EN/GPIO1[12]/
TSEC1_TMR_ALARM2
AJ26
I/O
I/O
LVDD2
LVDD2
16
16
TSEC2_TX_ER/GPIO1[24]/
TSEC1_TMR_ALARM1
AG26
TSEC2_TXD0/GPIO1[20]
AH28
AF27
I/O
I/O
LVDD2
LVDD2
16
16
TSEC2_TXD1/GPIO1[19]/
TSEC1_TMR_PP1
TSEC2_TXD2/GPIO1[18]/
TSEC1_TMR_PP2
AJ28
AF29
I/O
I/O
LVDD2
LVDD2
16
16
TSEC2_TXD3/GPIO1[17]/
TSEC1_TMR_PP3
GPIO1 Interface
GPIO1[0]/GTM1_TIN1/
GTM2_TIN2/DREQ0_B
P25
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
—
—
—
—
—
—
GPIO1[1]/GTM1_TGATE1_B/
GTM2_TGATE2_B/DACK0_B
N25
N26
B9
GPIO1[2]/GTM1_TOUT1_B/
DDONE0_B
GPIO1[3]/GTM1_TIN2/
GTM2_TIN1/DREQ1_B
GPIO1[4]/GTM1_TGATE2_B/
GTM2_TGATE1_B/DACK1_B
N29
M29
A9
GPIO1[5]/GTM1_TOUT2_B/
GTM2_TOUT1_B/DDONE1_B
GPIO1[6]/GTM1_TIN3/
GTM2_TIN4/DREQ2_B
GPIO1[7]/GTM1_TGATE3_B/
GTM2_TGATE4_B/DACK2_B
B10
J26
J24
GPIO1[8]/GTM1_TOUT3_B/
DDONE2_B
GPIO1[9]/GTM1_TIN4/
GTM2_TIN3/DREQ3_B
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Freescale Semiconductor
97
Table 72. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Note
GPIO1[10]/GTM1_TGATE4_B/
GTM2_TGATE3_B/DACK3_B
J27
I/O
OVDD
—
GPIO1[11]/GTM1_TOUT4_B/
GTM2_TOUT3_B/DDONE3_B
P24
I/O
OVDD
—
USB/GPIO2 Interface
USBDR_CLK/GPIO2[23]
AJ11
I/O
I/O
OVDD
OVDD
—
—
USBDR_DIR_DPPULLUP/
GPIO2[9]
AG12
USBDR_NXT/GPIO2[8]
AJ10
AF10
I/O
I/O
OVDD
OVDD
—
—
USBDR_PCTL0/GPIO2[11]/
SD_DAT2
USBDR_PCTL1/GPIO2[22]/
SD_DAT3
AE9
I/O
I/O
OVDD
OVDD
—
—
USBDR_PWRFAULT/
GPIO2[10]/SD_DAT1
AG13
USBDR_STP_SUSPEND
AH12
AG10
O
OVDD
OVDD
12
—
USBDR_D0_ENABLEN/
GPIO2[0]
I/O
USBDR_D1_SER_TXD/
GPIO2[1]
AF13
AG11
I/O
I/O
OVDD
OVDD
—
—
USBDR_D2_VMO_SE0/
GPIO2[2]
USBDR_D3_SPEED/GPIO2[3]
USBDR_D4_DP/GPIO2[4]
USBDR_D5_DM/GPIO2[5]
AH11
AG9
I/O
I/O
I/O
I/O
OVDD
OVDD
OVDD
OVDD
—
—
—
—
AF9
USBDR_D6_SER_RCV/
GPIO2[6]
AH13
USBDR_D7_DRVVBUS/
GPIO2[7]
AH10
I/O
OVDD
—
I2C Interface
IIC1_SCL
IIC1_SDA
IIC2_SCL
IIC2_SDA
C12
B12
A10
A12
I/O
I/O
I/O
I/O
OVDD
OVDD
OVDD
OVDD
2
2
2
2
JTAG Interface
B13
TCK
I
OVDD
—
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
98
Table 72. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Note
TDI
TDO
E14
C13
A13
E11
I
O
I
OVDD
OVDD
OVDD
OVDD
4
3
4
4
TMS
TRST_B
I
PCI Signals
PCI_AD0
PCI_AD1
PCI_AD2
PCI_AD3
PCI_AD4
PCI_AD5
PCI_AD6
PCI_AD7
PCI_AD8
PCI_AD9
PCI_AD10
PCI_AD11
PCI_AD12
PCI_AD13
PCI_AD14
PCI_AD15
PCI_AD16
PCI_AD17
PCI_AD18
PCI_AD19
PCI_AD20
PCI_AD21
PCI_AD22
PCI_AD23
PCI_AD24
PCI_AD25
PCI_AD26
P26
N28
P29
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
P27
R26
R29
T24
T25
R27
P28
U25
R28
U26
U24
T29
V24
Y26
V28
AA25
AA26
W29
AA24
AA27
AC26
AB25
AB24
AA28
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
99
Table 72. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Note
PCI_AD27
PCI_AD28
AA29
AC24
AC25
AB28
AE24
T26
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
—
—
—
—
—
—
—
5
PCI_AD29
PCI_AD30
PCI_AD31
PCI_C_BE_B0
PCI_C_BE_B1
PCI_C_BE_B2
PCI_C_BE_B3
PCI_DEVSEL_B
PCI_FRAME_B
PCI_GNT_B0
T28
V29
Y29
U28
V27
—
—
—
AE27
AC28
PCI_GNT_B[1]/
CPCI_HS_LED
PCI_GNT_B[2]/
AD27
O
OVDD
—
CPCI_HS_ENUM
PCI_GNT_B[3]/PCI_PME
PCI_GNT_B[4]
PCI_IDSEL
AC27
AE25
W28
AD29
U29
O
O
I
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
—
—
5
PCI_INTA_B/IRQ_OUT_B
PCI_IRDY_B
O
I/O
I/O
I/O
I/O
I
2
5
PCI_PAR
V25
—
5
PCI_PERR_B
Y25
PCI_REQ_B0
AE26
AC29
AB29
AD26
W27
AD28
V26
—
—
—
—
—
—
5
PCI_REQ_B[1]/CPCI_HS_ES
PCI_REQ_B2
I
PCI_REQ_B3
I
PCI_REQ_B4
I
PCI_RESET_OUT_B
PCI_SERR_B
O
I/O
I/O
I/O
I
PCI_STOP_B
W26
Y24
5
PCI_TRDY_B
5
M66EN
AD15
—
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
100
Table 72. TePBGA II Pinout Listing (continued)
Package Pin Number Pin Type
Programmable Interrupt Controller (PIC) Interface
Signal
Power Supply
Note
MCP_OUT_B
IRQ_B0/MCP_IN_B/GPIO2[12]
IRQ_B1/GPIO2[13]
AD14
F9
O
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
2
I/O
I/O
I/O
I/O
I/O
I/O
—
—
—
—
—
—
E9
IRQ_B2/GPIO2[14]
F10
D9
IRQ_B3/GPIO2[15]
IRQ_B4/GPIO2[16]/SD_WP
C9
IRQ_B5/GPIO2[17]/
USBDR_PWRFAULT
AE10
IRQ_B6/GPIO2[18]
IRQ_B7/GPIO2[19]
AD10
AD9
I/O
I/O
OVDD
OVDD
—
—
PMC Interface
QUIESCE_B
D13
O
OVDD
—
SerDes1 Interface
L1_SD_IMP_CAL_RX
L1_SD_IMP_CAL_TX
L1_SD_REF_CLK
L1_SD_REF_CLK_B
L1_SD_RXA_N
L1_SD_RXA_P
AJ14
AG19
AJ17
AH17
AJ15
AH15
AJ19
AH19
AF15
AE15
AF18
AE18
AJ18
I
I
L1_XPADVDD
L1_XPADVDD
L1_XPADVDD
L1_XPADVDD
L1_XPADVDD
L1_XPADVDD
L1_XPADVDD
L1_XPADVDD
L1_XPADVDD
L1_XPADVDD
L1_XPADVDD
L1_XPADVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
I
I
I
L1_SD_RXE_N
L1_SD_RXE_P
I
I
L1_SD_TXA_N
O
O
O
O
L1_SD_TXA_P
L1_SD_TXE_N
L1_SD_TXE_P
L1_SDAVDD_0
SerDes PLL
Power
(1.0 or 1.05 V)
L1_SDAVSS_0
L1_XCOREVDD
AG17
SerDes PLL
GND
—
—
—
—
AH14, AJ16, AF17, AH20, AJ20
SerDes Core
Power
(1.0 or 1.05 V)
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
101
Table 72. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Note
L1_XCOREVSS
AG14, AG15, AG16, AH16, AG18, AG20
SerDes Core
GND
—
—
L1_XPADVDD
L1_XPADVSS
AE16, AF16, AD18, AE19, AF19
SerDes I/O
Power (1.0 or
1.05 V)
—
—
—
—
AF14, AE17, AF20
SerDes I/O
GND
SerDes2 Interface
L2_SD_IMP_CAL_RX
L2_SD_IMP_CAL_TX
L2_SD_REF_CLK
L2_SD_REF_CLK_B
L2_SD_RXA_N
L2_SD_RXA_P
C19
C15
B17
A17
A19
B19
A15
B15
D18
E18
D15
E15
A16
I
I
L2_XPADVDD
L2_XPADVDD
L2_XPADVDD
L2_XPADVDD
L2_XPADVDD
L2_XPADVDD
L2_XPADVDD
L2_XPADVDD
L2_XPADVDD
L2_XPADVDD
L2_XPADVDD
L2_XPADVDD
—
—
—
—
—
—
—
—
—
—
—
—
—
—
I
I
I
I
L2_SD_RXE_N
L2_SD_RXE_P
I
I
L2_SD_TXA_N
O
O
O
O
L2_SD_TXA_P
L2_SD_TXE_N
L2_SD_TXE_P
L2_SDAVDD_0
SerDes PLL
Power
(1.0 or 1.05 V)
L2_SDAVSS_0
L2_XCOREVDD
C17
SerDes PLL
GND
—
—
—
—
A14, B14, D17, B18, B20
SerDes Core
Power
(1.0 or 1.05 V)
L2_XCOREVSS
L2_XPADVDD
C14, C16, A18, C18, A20, C20
D14, E16, F18, D19, E19
SerDes Core
GND
—
—
—
—
SerDes I/O
Power (1.0 or
1.05 V)
L2_XPADVSS
D16, E17, D20
SerDes I/O
GND
—
—
—
SPI Interface
SPICLK/SD_CLK
AH9
I/O
OVDD
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
102
Table 72. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Note
SPIMISO/SD_DAT0
SPIMOSI/SD_CMD
SPISEL_B/SD_CD
AD11
AJ9
I/O
I/O
I
OVDD
OVDD
OVDD
—
—
—
AE11
System Control Interface
SRESET_B
HRESET_B
PORESET_B
AD12
AE12
AE14
I/O
I/O
I
OVDD
OVDD
OVDD
2
1
—
Test Interface
TEST
E10
D10
D12
I
I
I
OVDD
OVDD
OVDD
10
13
13
TEST_SEL0
TEST_SEL1
Thermal Management
F15
Reserved
LVDD1
LVDD2
LBVDD
VDD
I
—
14
—
—
—
—
Power Supply Signals
AC21, AG21, AH23
Power for
eTSEC 1 I/O
(2.5 V, 3.3 V)
LVDD1
LVDD2
LBVDD
VDD
AG24, AH27, AH29
Power for
eTSEC 2 I/O
(2.5 V, 3.3 V)
G20, D22, A24, G26, D27, A28
Power for eLBC
(3.3, 2.5, or
1.8 V)
K10, L10, M10, N10, P10, R10, T10, U10,
Power for Core
V10, W10, Y10, K11, R11, Y11, K12, Y12, (1.0 V or 1.5 V)
K13, Y13, K14, Y14, K15, L15, W15, Y15,
K16, Y16, K17, Y17, K18, Y18, K19, R19,
Y19, K20, L20, M20, N20, P20, R20, T20,
U20, V20, W20, Y20
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
103
Table 72. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Note
GND
(VSS)
A1, AJ1, H2, N2, AA2, AD2, D3, R3, AF3, A4,
F4, J4, L4, V4, Y4, AB4, B5, E5, P5, AH5, K6,
T6, AA6, AD6, AG6, F7, J7, Y7, AJ7, B8,
AE8, AG8, G9, AC9,B11, D11, F11, L11,
M11, N11, P11, T11, U11, V11, W11,L12,
M12, N12, P12, R12, T12, U12, V12, W12,
E12, E13, L13, M13, N13, P13, R13, T13,
U13, V13, W13, AE13, AJ13, F14, L14, M14,
N14, P14, R14, T14, U14, V14, W14, M15,
N15, P15, R15, T15, U15, V15, L16, M16,
N16, P16, R16, T16, U16, V16, W16, L17,
M17, N17, P17, R17, T17, U17, V17, W17,
L18, M18, N18, P18, R18, T18, U18, V18,
W18, L19, M19, N19, P19, T19, U19, V19,
W19, AC20, G21, AF21, C22, J23, AA23,
AJ23, B24, W24, AF24, K25, R25, AD25,
D26, G27, M27, T27, Y27, AB27, AG27, A29,
AJ29
—
—
—
AVDD_C
AVDD_L
AVDD_P
GVDD
AD13
Power for e300
core PLL (1.0 V
or 1.05 V)
—
—
15
15
15
—
F13
Power for eLBC
PLL (1.0 V or
1.05 V)
F12
Power for
system PLL
(1.0 V or 1.05 V)
—
A2, D2, R2, U2, AC2, AF2, AJ2, F3, H3, L3, Power for DDR
N3, Y3, AB3, B4, P4, AF4, AH4, C5, F5, K5, SDRAM I/O
V5, AA5, AD5, N6, R6, AJ6, B7, E7, K7, AA7, Voltage (2.5 or
AE7, AG7, AD8 1.8 V)
GVDD
OVDD
NC
AC10, AF12, AJ12, K23, Y23, R24, AD24, PCI, USB, and
L25, W25, AB26, U27, M28, Y28, G10, A11, other Standard
OVDD
—
8
C11
(3.3 V)
No Connect
F16, F17, AD16, AD17
—
—
Pull Down
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
104
Table 72. TePBGA II Pinout Listing (continued)
Signal
Package Pin Number
Pin Type
Power Supply
Note
Pull Down
B16, AH18
—
—
7
Notes:
1. This pin is an open drain signal. A weak pull-up resistor (1 kΩ) should be placed on this pin to OVDD.
2. This pin is an open drain signal. A weak pull-up resistor (2–10 kΩ) should be placed on this pin to OVDD.
3. This output is actively driven during reset rather than being released to high impedance during reset.
4. These JTAG pins have weak internal pull-up P-FETs that are always enabled.
5. This pin should have a weak pull up if the chip is in PCI host mode. Follow PCI Specification recommendation and see
AN3665, “MPC837xE Design Checklist,” for more details.
6. These are On Die Termination pins, used to control DDR2 memories internal termination resistance.
7. This pin must always be tied to GND using a 0 Ω resistor.
8. This pin must always be left not connected.
9. For DDR2 operation, it is recommended that MDIC0 be tied to GND using an 18.2 Ω resistor and MDIC1 be tied to DDR
power using an 18.2 Ω resistor.
10.This pin must always be tied low. If it is left floating it may cause the device to malfunction.
11.See AN3665, “MPC837xE Design Checklist,” for proper DDR termination.
12.This pin must not be pulled down during PORESET.
13.This pin must always be tied to OVDD.
14.Open or tie to GND.
15.Voltage settings are dependent on the frequency used; see Table 3.
16.See AN3665, “MPC837xE Design Checklist,” for proper termination.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
105
23 Clocking
This figure shows the internal distribution of clocks within this chip.
e300 core
core_clk
Core PLL
csb_clk
to DDR
memory
controller
6
6
DDR
DDR
Memory
Device
MCK[0:5]
MCK[0:5]
Clock
Div
/2
ddr_clk
lbiu_clk
Clock
Unit
System PLL
/n
LCLK[0:2]
to local bus
memory
Local Bus
Memory
Device
LBIU
DLL
LSYNC_OUT
LSYNC_IN
controller
csb_clk to rest
of the device
PCI_CLK/
PCI_SYNC_IN
CFG_CLKIN_DIV
CLKIN
PCI_SYNC_OUT
PCI_CLK[0:4]
PCI Clock
Divider
5
Figure 64. Clock Subsystem
The primary clock source for the device can be one of two inputs, CLKIN or PCI_CLK, depending on
whether the device is configured in PCI host or PCI agent mode. When the device is configured as a PCI
host device, CLKIN is its primary input clock. CLKIN feeds the PCI clock divider (÷2) and the
multiplexors for PCI_SYNC_OUT and PCI_CLK_OUT. The CFG_CLKIN_DIV configuration input
selects whether CLKIN or CLKIN/2 is driven out on the PCI_SYNC_OUT signal. The OCCR[PCICOEn]
parameters select whether CFG_CLKIN_DIV is driven out on the PCI_CLK_OUTn signals.
PCI_SYNC_OUT is connected externally to PCI_SYNC_IN to allow the internal clock subsystem to
synchronize to the system PCI clocks. PCI_SYNC_OUT must be connected properly to PCI_SYNC_IN,
with equal delay to all PCI agent devices in the system, to allow the device to function. When the device
is configured as a PCI agent device, PCI_CLK is the primary input clock. When the device is configured
as a PCI agent device the CLKIN signal should be tied to GND.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
106
Freescale Semiconductor
As shown in Figure 64, the primary clock input (frequency) is multiplied up by the system phase-locked
loop (PLL) and the clock unit to create the coherent system bus clock (csb_clk), the internal clock for the
DDR controller (ddr_clk), and the internal clock for the local bus interface unit (lbiu_clk).
The csb_clk frequency is derived from a complex set of factors that can be simplified into the following
equation:
csb_clk = {PCI_SYNC_IN × (1 + CFG_CLKIN_DIV)} × SPMF
Eqn. 20
In PCI host mode, PCI_SYNC_IN × (1 + CFG_CLKIN_DIV) is the CLKIN frequency.
The csb_clk serves as the clock input to the e300 core. A second PLL inside the e300 core multiplies up
the csb_clk frequency to create the internal clock for the e300 core (core_clk). The system and core PLL
multipliers are selected by the SPMF and COREPLL fields in the reset configuration word low register
(RCWLR) which is loaded at power-on reset or by one of the hard-coded reset options. See Chapter 4,
“Reset, Clocking, and Initialization,” in the MPC8379E Reference Manual for more information on the
clock subsystem.
The internal ddr_clk frequency is determined by the following equation:
ddr_clk = csb_clk × (1 + RCWLR[DDRCM])
Eqn. 21
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The internal lbiu_clk frequency is determined by the following equation:
lbiu_clk = csb_clk × (1 + RCWLR[LBCM])
Eqn. 22
Note that lbiu_clk is not the external local bus frequency; lbiu_clk passes through the LBIU clock divider
to create the external local bus clock outputs (LCLK[0:2]). The eLBC clock divider ratio is controlled by
LCRR[CLKDIV].
Some of the internal units may be required to be shut off or operate at lower frequency than the csb_clk
frequency. Those units have a default clock ratio that can be configured by a memory mapped register after
the device comes out of reset. Table 73 specifies which units have a configurable clock frequency.
Table 73. Configurable Clock Units
Unit
eTSEC1, eTSEC2
Default Frequency
Options
csb_clk/3
csb_clk/3
csb_clk/3
csb_clk/3
csb_clk
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk
eSDHC and I2C11
Security block
USB DR
PCI and DMA complex
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
107
Table 73. Configurable Clock Units (continued)
Default Frequency
Unit
Options
PCI Express1, 2
SATA1, 2
csb_clk/3
csb_clk/3
Off, csb_clk, csb_clk/2, csb_clk/3
Off, csb_clk
1
This only applies to I2C1 (I2C2 clock is not configurable).
This table provides the operating frequencies for the TePBGA II package under recommended operating
conditions (see Table 3).
Table 74. Operating Frequencies for TePBGA II
Minimum Operating
Frequency (MT/s)
Maximum Operating
Frequency (MT/s)
Parameter1
e300 core frequency (core_clk)
333
133
125
83
800
400
200
167
133
400
66
Coherent system bus frequency (csb_clk)
DDR2 memory bus frequency (MCK)1
DDR1 memory bus frequency (MCK) 2
Local bus frequency (LCLKn)1
Local bus controller frequency (lbc_clk)
PCI input frequency (CLKIN or PCI_CLK)
eTSEC frequency
—
—
25
133
—
400
200
200
200
400
200
Security encryption controller frequency
USB controller frequency
—
eSDHC controller frequency
—
PCI Express controller frequency
SATA controller frequency
—
—
Notes:
1. The CLKIN frequency, RCWLR[SPMF], and RCWLR[COREPLL] settings must be chosen such that the resulting csb_clk,
MCK, LCLK[0:2], and core_clk frequencies do not exceed their respective maximum or minimum operating frequencies.
The value of SCCR[xCM] must be programmed such that the maximum internal operating frequency of the Security core,
USB modules, SATA, and eSDHC will not exceed their respective value listed in this table.
2. The DDR data rate is 2× the DDR memory bus frequency.
3. The local bus frequency is ½, ¼, or 1/8 of the lbiu_clk frequency (depending on LCRR[CLKDIV]) which is in turn 1× or 2×
the csb_clk frequency (depending on RCWLR[LBCM]).
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
108
Freescale Semiconductor
23.1 System PLL Configuration
The system PLL is controlled by the RCWLR[SPMF] parameter. The system PLL VCO frequency
depends on RCWLR[DDRCM] and RCWLR[LBCM]. Table 75 shows the multiplication factor encodings
for the system PLL.
NOTE
If RCWLR[DDRCM] and RCWLR[LBCM] are both cleared, the system
PLL VCO frequency = (CSB frequency) × (System PLL VCO Divider).
If either RCWLR[DDRCM] or RCWLR[LBCM] are set, the system PLL
VCO frequency = 2 × (CSB frequency) × (System PLL VCO Divider).
The VCO divider needs to be set properly so that the System PLL VCO
frequency is in the range of 400–800 MT/s.
Table 75. System PLL Multiplication Factors
RCWLR[SPMF]
System PLL Multiplication Factor
0000
0001
Reserved
Reserved
× 2
0010
0011
× 3
0100
× 4
0101
× 5
0110
× 6
0111–1111
× 7 to × 15
As described in Section 23, “Clocking,” The LBIUCM, DDRCM, and SPMF parameters in the reset
configuration word low and the CFG_CLKIN_DIV configuration input signal select the ratio between the
primary clock input (CLKIN or PCI_CLK) and the internal coherent system bus clock (csb_clk). Table 77
and Table 78 show the expected frequency values for the CSB frequency for select csb_clk to
CLKIN/PCI_SYNC_IN ratios.
The RCWLR[SVCOD] denotes the system PLL VCO internal frequency as shown in Table 76.
Table 76. System PLL VCO Divider
RCWLR[SVCOD]
VCO Division Factor
00
01
10
11
4
8
2
1
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
109
Table 77. CSB Frequency Options for Host Mode
Input Clock Frequency (MT/s)2
CFG_CLKIN_DIV
at Reset1
csb_clk :
SPMF
25
33.33
66.67
Input Clock Ratio1
csb_clk Frequency (MT/s)
High
High
High
High
High
High
High
High
High
High
High
High
High
High
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
2 : 1
3 : 1
133
200
267
333
400
4 : 1
133
167
200
233
267
300
333
367
400
5 : 1
6 : 1
150
175
200
225
250
275
300
325
350
375
7 : 1
8 : 1
9 : 1
10 : 1
11 : 1
12 : 1
13 : 1
14 : 1
15 : 1
Notes:
1. CFG_CLKIN_DIV select the ratio between CLKIN and PCI_SYNC_OUT.
2. CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
Table 78. CSB Frequency Options for Agent Mode
Input Clock Frequency (MT/s)2
CFG_CLKIN_DIV
at reset1
csb_clk :
SPMF
25
33.33
66.67
Input Clock Ratio1
csb_clk Frequency (MT/s)
Low
Low
Low
Low
Low
0010
0011
0100
0101
0110
2 : 1
3 : 1
4 : 1
5 : 1
6 : 1
133
200
267
333
400
133
167
200
150
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
110
Table 78. CSB Frequency Options for Agent Mode (continued)
Input Clock Frequency (MT/s)2
CFG_CLKIN_DIV
at reset1
csb_clk :
SPMF
25
33.33
66.67
Input Clock Ratio1
csb_clk Frequency (MT/s)
Low
Low
Low
Low
Low
Low
Low
Low
Low
0111
1000
1001
1010
1011
1100
1101
1110
1111
7 : 1
8 : 1
175
200
225
250
275
300
325
350
375
233
267
300
333
367
400
9 : 1
10 : 1
11 : 1
12 : 1
13 : 1
14 : 1
15 : 1
Notes:
1. CFG_CLKIN_DIV doubles csb_clk if set high.
2. CLKIN is the input clock in host mode; PCI_CLK is the input clock in agent mode.
23.2 Core PLL Configuration
RCWLR[COREPLL] selects the ratio between the internal coherent system bus clock (csb_clk) and the
e300 core clock (core_clk). Table 79 shows the encodings for RCWLR[COREPLL]. COREPLL values
that are not listed in Table 79 should be considered as reserved.
NOTE
Core VCO frequency = core frequency × VCO divider
VCO divider has to be set properly so that the core VCO frequency is in the
range of 800–1600 MT/s.
Table 79. e300 Core PLL Configuration
RCWLR[COREPLL]
core_clk : csb_clk Ratio
VCO Divider 1
0–1
nn
2–5
6
0000
0
PLL bypassed
(PLL off, csb_clk clocks core directly)
PLL bypassed
(PLL off, csb_clk clocks core
directly)
11
00
01
10
00
nnnn
0001
0001
0001
0001
n
0
0
0
1
n/a
1:1
n/a
2
1:1
4
1:1
8
1.5:1
2
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
111
Table 79. e300 Core PLL Configuration (continued)
RCWLR[COREPLL]
core_clk : csb_clk Ratio
VCO Divider 1
0–1
2–5
6
01
10
00
01
10
00
01
10
00
01
10
00
01
10
00
01
10
0001
0001
0010
0010
0010
0010
0010
0010
0011
0011
0011
0011
0011
0011
0100
0100
0100
1
1
0
0
0
1
1
1
0
0
0
1
1
1
0
0
0
1.5:1
1.5:1
2:1
4
8
2
4
8
2
4
8
2
4
8
2
4
8
2
4
8
2:1
2:1
2.5:1
2.5:1
2.5:1
3:1
3:1
3:1
3.5:1
3.5:1
3.5:1
4:1
4:1
4:1
Notes:
1. Core VCO frequency = Core frequency × VCO divider. Note that VCO divider has to be set properly so that the core VCO
frequency is in the range of 800–1600 MT/s.
23.3 Suggested PLL Configurations
This table shows suggested PLL configurations for different input clocks (LBCM = 0).
Table 80. Example Clock Frequency Combinations
1
1
eLBC
/4
e300 Core
Sys
VCO
DDRdata
rate
1
1
,3
Ref
LBCM DDRCM SVCOD SPMF
CSB
/2
/8
× 1 × 1.5 × 2 × 2.5 × 3
1,
1,
4
2
25.0
25.0
33.3
33.3
0
0
0
0
1
1
1
1
2
2
2
2
5
6
5
4
500
600
667
533
125
150
167
133
250
62.5 31.3 15.6
75 6 37.5 18.8
83.3 6 41.6 20.8
66.7 33.3 16.7
—
—
—
—
—
—
—
—
—
—
—
375
300
333
267
375 450
333 416 500
333 400
—
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
112
Table 80. Example Clock Frequency Combinations (continued)
1
1
eLBC
e300 Core
Sys
VCO
DDRdata
rate
1
1
,3
Ref
LBCM DDRCM SVCOD SPMF
CSB
/2
/4
/8
× 1 × 1.5 × 2 × 2.5 × 3
1,
1,
4
2
48.0
66.7
25.0
33.3
50.0
50.0
66.7
66.7
66.7
Notes:
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
2
2
4
2
4
2
2
2
2
3
2
8
8
4
8
4
5
6
576
533
800
533
800
800
533
667
800
144
133
200
288
72 6
36
18
—
—
—
—
—
—
—
—
—
—
—
—
360 432
333 400
266
200
267
200
66.7 33.3 16.7
100 6
50 25
133 6 66.7 33.3
400 500 600
266.7
200
400 533 667 800
400 500 600
600 800
400 533 667 800
100 6
—
50
25
—
400
400 5
267
100 6 50
—
—
266.7
333
133 6 66.7 33.3
333
—
—
83.3 6 41.6 333 500 667
100 6 50
400 600 800
—
—
—
—
400
400 5
1. Values in MT/s.
2. System PLL VCO range: 400–800 MT/s.
3. CSB frequencies less than 133 MT/s will not support Gigabit Ethernet rates.
4. Minimum data rate for DDR2 is 250 MT/s and for DDR1 is 167 MT/s.
5. Applies to DDR2 only.
6. Applies to eLBC PLL-enabled mode only.
24 Thermal
This section describes the thermal specifications of this chip.
24.1 Thermal Characteristics
This table provides the package thermal characteristics for the 689 31 × 31mm TePBGA II package.
Table 81. Package Thermal Characteristics for TePBGA II
Parameter
Symbol
Value
Unit
Note
Junction-to-ambient natural convection on single layer board (1s)
Junction-to-ambient natural convection on four layer board (2s2p)
Junction-to-ambient (at 200 ft/min) on single layer board (1s)
Junction-to-ambient (at 200 ft/min) on four layer board (2s2p)
Junction-to-board thermal
RθJA
RθJA
21
15
16
12
8
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
1, 2
1, 2, 3
1, 3
1, 3
4
RθJMA
RθJMA
RθJB
Junction-to-case thermal
RθJC
6
5
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
113
Table 81. Package Thermal Characteristics for TePBGA II (continued)
Parameter
Symbol
Value
Unit
Note
Junction-to-package natural convection on top
ψJT
6
°C/W
6
Notes:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per JEDEC JESD51-2 with the single layer board horizontal. Board meets JESD51-9 specification.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured
on the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction
temperature per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written
as Psi-JT.
24.2 Thermal Management Information
For the following sections, P = (V
× I ) + P where P is the power dissipation of the I/O drivers.
DD I/O I/O
D
DD
24.2.1 Estimation of Junction Temperature with Junction-to-Ambient
Thermal Resistance
An estimation of the chip junction temperature, T , can be obtained from the equation:
J
TJ = TA + (RθJA × PD)
where:
TJ = junction temperature (°C)
TA = ambient temperature for the package (°C)
RθJA = junction to ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The junction to ambient thermal resistance is an industry-standard value that provides a quick and easy
estimation of thermal performance. Generally, the value obtained on a single layer board is appropriate for
a tightly packed printed circuit board. The value obtained on the board with the internal planes is usually
appropriate if the board has low power dissipation and the components are well separated. Test cases have
demonstrated that errors of a factor of two (in the quantity T – T ) are possible.
J
A
24.2.2 Estimation of Junction Temperature with Junction-to-Board
Thermal Resistance
NOTE
The heat sink cannot be mounted on the package.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
114
Freescale Semiconductor
The thermal performance of a device cannot be adequately predicted from the junction to ambient thermal
resistance. The thermal performance of any component is strongly dependent on the power dissipation of
surrounding components. In addition, the ambient temperature varies widely within the application. For
many natural convection and especially closed box applications, the board temperature at the perimeter
(edge) of the package is approximately the same as the local air temperature near the device. Specifying
the local ambient conditions explicitly as the board temperature provides a more precise description of the
local ambient conditions that determine the temperature of the device.
At a known board temperature, the junction temperature is estimated using the following equation:
TJ = TA + (RθJB × PD)
where:
TA = ambient temperature for the package (°C)
RθJB = junction to board thermal resistance (°C/W) per JESD51-8
PD = power dissipation in the package (W)
When the heat loss from the package case to the air can be ignored, acceptable predictions of junction
temperature can be made. The application board should be similar to the thermal test condition: the
component is soldered to a board with internal planes.
24.2.3 Experimental Determination of Junction Temperature
NOTE
The heat sink cannot be mounted on the package.
To determine the junction temperature of the device in the application after prototypes are available, use
the thermal characterization parameter (Ψ ) to determine the junction temperature and a measure of the
JT
temperature at the top center of the package case using the following equation:
TJ = TT + (ΨJT × PD)
where:
TJ = junction temperature (°C)
TT = thermocouple temperature on top of package (°C)
ΨJT = junction to ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The thermal characterization parameter is measured per the JESD51-2 specification using a 40 gauge type
T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so
that the thermocouple junction rests on the package. A small amount of epoxy is placed over the
thermocouple junction and over about 1 mm of wire extending from the junction. The thermocouple wire
is placed flat against the package case to avoid measurement errors caused by cooling effects of the
thermocouple wire.
24.2.4 Heat Sinks and Junction-to-Case Thermal Resistance
For the power values the device is expected to operate at, it is anticipated that a heat sink will be required.
A preliminary estimate of heat sink performance can be obtained from the following first-cut approach.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
115
The thermal resistance is expressed as the sum of a junction to case thermal resistance and a
case-to-ambient thermal resistance:
RθJA = RθJC + RθCA
where:
RθJA = junction to ambient thermal resistance (°C/W)
RθJC = junction to case thermal resistance (°C/W)
RθCA = case to ambient thermal resistance (°C/W)
RθJC is device-related and cannot be influenced by the user. The user controls the thermal environment to
change the case to ambient thermal resistance, RθCA. For instance, the user can change the size of the heat
sink, the air flow around the device, the interface material, the mounting arrangement on printed circuit
board, or change the thermal dissipation on the printed circuit board surrounding the device.
This first-cut approach overestimates the heat sink size required, since heat flow through the board is not
accounted for, which can be as much as one-third to one-half of the power generated in the package.
Accurate thermal design requires thermal modeling of the application environment using computational
fluid dynamics software which can model both the conduction cooling through the package and board and
the convection cooling due to the air moving through the application. Simplified thermal models of the
packages can be assembled using the junction-to-case and junction-to-board thermal resistances listed in
the thermal resistance table. More detailed thermal models can be made available on request.
The thermal performance of devices with heat sinks has been simulated with a few commercially available
heat sinks. The heat sink choice is determined by the application environment (temperature, air flow,
adjacent component power dissipation) and the physical space available. Because of the wide variety of
application environments, a single standard heat sink applicable to all cannot be specified.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
116
Freescale Semiconductor
This table shows the heat sink thermal resistance for TePBGA II package with heat sinks, simulated in a
standard JEDEC environment, per JESD 51-6.
Table 82. Thermal Resistance with Heat Sink in Open Flow (TePBGA II)
Thermal Resistance
Heat Sink Assuming Thermal Grease
Air Flow
(°/W)
AAVID 30 × 30 × 9.4 mm Pin Fin
Natural Convection
0.5 m/s
13.1
10.6
9.3
8.2
7.5
11.1
8.5
7.7
7.2
6.8
11.3
9.0
7.8
7.0
6.5
9.7
7.7
6.8
6.4
6.1
1 m/s
2 m/s
4 m/s
AAVID 31 × 35 × 23 mm Pin Fin
AAVID 43× 41× 16.5mm Pin Fin
Wakefield, 53 × 53 × 25 mm Pin Fin
Natural Convection
0.5 m/s
1 m/s
2 m/s
4 m/s
Natural Convection
0.5 m/s
1 m/s
2 m/s
4 m/s
Natural Convection
0.5 m/s
1 m/s
2 m/s
4 m/s
Heat sink vendors include the following:
Aavid Thermalloy
www.aavidthermalloy.com
Alpha Novatech
www.alphanovatech.com
International Electronic Research Corporation (IERC)
www.ctscorp.com
Millennium Electronics (MEI)
www.mei-thermal.com
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
117
Tyco Electronics
Chip Coolers™
www.chipcoolers.com
Wakefield Engineering
www.wakefield.com
Interface material vendors include the following:
Chomerics, Inc.
www.chomerics.com
Dow-Corning Corporation
Dow-Corning Electronic Materials
www.dowcorning.com
Shin-Etsu MicroSi, Inc.
www.microsi.com
The Bergquist Company
www.bergquistcompany.com
24.3 Heat Sink Attachment
The device requires the use of heat sinks. When heat sinks are attached, an interface material is required,
preferably thermal grease and a spring clip. The spring clip should connect to the printed circuit board,
either to the board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces
that can lift the edge of the package or peel the package from the board. Such peeling forces reduce the
solder joint lifetime of the package. The recommended maximum compressive force on the top of the
package is 10 lb force (4.5 kg force). Any adhesive attachment should attach to painted or plastic surfaces,
and its performance should be verified under the application requirements.
24.3.1 Experimental Determination of the Junction Temperature with a
Heat Sink
When a heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimize the size of the clearance to minimize the change in thermal
performance caused by removing part of the thermal interface to the heat sink. Because of the experimental
difficulties with this technique, many engineers measure the heat sink temperature and then back calculate
the case temperature using a separate measurement of the thermal resistance of the interface. From this
case temperature, the junction temperature is determined from the junction to case thermal resistance.
TJ = TC + (RθJC × PD)
where:
TJ = junction temperature (°C)
TC = case temperature of the package (°C)
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
118
Freescale Semiconductor
RθJC = junction to case thermal resistance (°C/W)
PD = power dissipation (W)
25 System Design Information
This section provides electrical and thermal design recommendations for successful application of this
chip.
25.1 PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins. The AV
DD
DD
level should always be equivalent to V , and preferably these voltages will be derived directly from V
DD
through a low frequency filter scheme.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide five independent filter circuits as illustrated in Figure 65, one to each of the five AV pins. By
DD
providing independent filters to each PLL, the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MT/s
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize
DD
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of package, without the inductance of vias.
DD
This figure shows the PLL power supply filter circuit.
10 Ω
VDD
AVDD (or L2AVDD)
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 65. PLL Power Supply Filter Circuit
25.2 Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the device can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the device system, and the device itself
requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer
place at least one decoupling capacitor at each VDD, OVDD, GVDD, and LVDD pins of the device. These
decoupling capacitors should receive their power from separate VDD, OVDD, GVDD, LVDD, and GND
power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may be placed directly
under the device using a standard escape pattern. Others may surround the part.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
119
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the VDD, OVDD, GVDD, and LVDD planes, to enable quick recharging of the smaller chip
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through two
vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo
OSCON).
25.3 Connection Recommendations
To ensure reliable operation, it is highly recommended that unused inputs be connected to an appropriate
signal level. Unused active low inputs should be tied to OVDD, GVDD, or LVDD as required. Unused
active high inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external VDD, GVDD, LVDD, OVDD, and GND pins
of the device.
25.4 Output Buffer DC Impedance
The device drivers are characterized over process, voltage, and temperature. For all buses, the driver is a
2
push-pull single-ended driver type (open drain for I C).
To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to OVDD
0
or GND. Then, the value of each resistor is varied until the pad voltage is OV /2 (see Figure 66). The
DD
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
When data is held high, SW1 is closed (SW2 is open) and R is trimmed until the voltage at the pad equals
P
OV /2. R then becomes the resistance of the pull-up devices. R and R are designed to be close to each
DD
P
P
N
other in value. Then, Z = (R + R )/2.
0
P
N
OVDD
RN
SW2
SW1
Pad
Data
RP
OGND
Figure 66. Driver Impedance Measurement
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
120
The value of this resistance and the strength of the driver’s current source can be found by making two
measurements. First, the output voltage is measured while driving logic 1 without an external differential
termination resistor. The measured voltage is V = R
while driving logic 1 with an external precision differential termination resistor of value R . The
× I
. Second, the output voltage is measured
1
source
source
term
measured voltage is V = (1/(1/R + 1/R )) × I
. Solving for the output impedance gives R
=
2
1
2
source
source
R
× (V /V – 1). The drive current is then I
= V /R
.
term
1
2
source
1
source
This table summarizes the signal impedance targets. The driver impedance are targeted at minimum V
,
DD
nominal OV , 105°C.
DD
Table 83. Impedance Characteristics
Local Bus, Ethernet,
PCI Signals
(not including PCI
output clocks)
PCI Output Clocks
(including
PCI_SYNC_OUT)
DUART, Control,
Configuration, Power
Management
Impedance
DDR DRAM Symbol
Unit
R
R
42 Target
42 Target
NA
25 Target
25 Target
NA
42 Target
42 Target
NA
20 Target
20 Target
NA
Z0
Z0
W
W
W
N
P
Differential
ZDIFF
Note: Nominal supply voltages. See Table 2, Tj = 105°C.
25.5 Configuration Pin Muxing
The device provides the user with power-on configuration options which can be set through the use of
external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration
pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when PORESET deasserts, at which time the input receiver is
disabled and the I/O circuit takes on its normal function. Careful board layout with stubless connections
to these pull-up/pull-down resistors coupled with the large value of the pull-up/pull-down resistor should
minimize the disruption of signal quality or speed for output pins thus configured.
25.6 Pull-Up Resistor Requirements
The device requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type pins
2
including I C pins and IPIC interrupt pins.
For more information on required pull-up resistors and the connections required for the JTAG interface,
see AN3665, “MPC837xE Design Checklist.”
26 Ordering Information
Ordering information for the parts fully covered by this specification document is provided in
Section 26.1, “Part Numbers Fully Addressed by This Document.”
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
Freescale Semiconductor
121
26.1 Part Numbers Fully Addressed by This Document
Table 84 provides the Freescale part numbering nomenclature for this chip. Note that the individual part
numbers correspond to a maximum processor core frequency. For available frequencies, contact your local
Freescale sales office. In addition to the processor frequency, the part numbering scheme also includes an
application modifier which may specify special application conditions. Each part number also contains a
revision code which refers to the die mask revision number.
Table 84. Part Numbering Nomenclature
MPC 8377
ZQ
AF
D
A
E
C
Encryption
Acceleratio
n
Product
Code Identifier
Part
Temperature
Range 1
e300 core
DDR
Data Rate
Revision
Level 4
Package 2
Frequency 3
MPC
8377
Blank = Not Blank = 0°C (Ta) VR = Pb-free AN = 800 MT/s G = 400 MT/s Blank = Freescale
included to 125°C (Tj) 689 TePBGA II AL = 667 MT/s F = 333 MT/s ATMC fab
E = included C = –40°C (Ta)
AJ = 533 MT/s D = 266 MT/s A =
to 125°C (Tj)
AG =
GlobalFoundries
fab
400 MT/s
Note:
1
Contact local Freescale office on availability of parts with an extended temperature range.
2
3
See Section 22, “Package and Pin Listings,” for more information on the available package type.
Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. Additionally, parts addressed by Part Number Specifications may support
other maximum core frequencies.
4
No design changes occurred between initial parts and the revision “A” parts. Only the fab source has changed in moving
to revision “A” parts. Initial revision parts and revision “A” parts are form, fit, function, and reliability equivalent.
This table lists the available core and DDR data rate frequency combinations.
Table 85. Available Parts (Core/DDR Data Rate)
MPC8377E
MPC8378E
MPC8379E
800 MT/s/400 MT/s
667 MT/s/400 MT/s
533 MT/s/333 MT/s
400 MT/s/266 MT/s
800 MT/s/400 MT/s
667 MT/s/400 MT/s
533 MT/s/333 MT/s
400 MT/s/266 MT/s
800 MT/s/400 MT/s
667 MT/s/400 MT/s
533 MT/s/333 MT/s
400 MT/s/266 MT/s
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
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122
This table shows the SVR and PVR settings by device.
Table 86. SVR and PVR Settings by Product Revision
SVR
PVR
Device
Package
Rev 1.0
Rev. 2.1
Rev. 1.0
Rev. 2.1
MPC8377
MPC8377E
MPC8378
MPC8378E
MPC8379
MPC8379E
0x80C7_0010
0x80C6_0010
0x80C5_0010
0x80C4_0010
0x80C3_0010
0x80C2_0010
0x80C7_0021
0x80C6_0021
0x80C5_0021
0x80C4_0021
0x80C3_0021
0x80C2_0021
TePBGA II
0x8086_1010
0x8086_1011
26.2 Part Marking
Parts are marked as in the example as shown in this figure.
MPCnnnnetppaaar
core/platform MT/s
ATWLYYWW
CCCCC
*MMMMM
YWWLAZ
TePBGA II
Notes:
ATWLYYWW is the traceability code.
CCCCC is the country code.
MMMMM is the mask number.
YWWLAZ is the assembly traceability code.
Figure 67. Freescale Part Marking for TePBGA II Devices
27 Document Revision History
This table provides a revision history for this document.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
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123
Table 87. Document Revision History
Substantive Change(s)
Revision Date
10
07/2014 • In Table 4, “Output Drive Capability,“ updated the output impedance cell for DDR 1 and DDR 2 to “18
full-strength mode, 36 half-strength mode.” Added notes column to table.
• In Table 21, “DDR1 and DDR2 SDRAM Output AC Timing Specifications,” updated the max value for
MCKn cycle time, MCKn/MCKn crossing, added note 7 to rows MCSn output setup with respect to MCK
and MCSn output hold with respect to MCK, and updated note 3 to ADDR/CMD includes all DDR
SDRAM output signals except MCK/MCK, MCS, MODT, and MDQ/MDM/MDQS.
• In Table 35, “USB General Timing Parameters (ULPI Mode Only),” updated note 3 as follows: “All signals
are measured from OVDD/2 of the rising edge of the USB clock to 0.5 × OVDD of the signal in question
for 3.3-V signaling levels.”
• In Table 39, “Local Bus General Timing Parameters—PLL Enable Mode,” updated note 2 as follows: “All
timings are in reference to rising edge of LSYNC_IN at LBVDD/2 and the 0.5 × LBVDD of the signal in
question.”
• In Table 40, “Local Bus General Timing Parameters—PLL Bypass Mode,” updated note 3 as follows: “All
signals are measured from LBVDD/2 of the rising/falling edge of LCLK0 to 0.5 × LBVDD of the signal in
question for 3.3-V signaling levels.”
• In Table 74, “Operating Frequencies for TePBGA II,” updated the min and max values for DDR1 and
DDR2 memory bus frequency (MCK) parameters.
• Throughout document, updated MHz data rate to MT/s data rate.
9
8
03/2014 In Table 4, added Note 2.
05/2012 In Table 15, “DDR SDRAM DC Electrical Characteristics for GVDD (typ) = 2.5 V,” updated Output leakage
current (IOZ) min and max values.
7
10/2011 • In Table 84, “Part Numbering Nomenclature,” updated “Revision Level description”and added footnote
4.In Section 21.2.4, “AC Requirements for SerDes Reference Clocks,” modified the introductory
sentence for Table 71, “SerDes Reference Clock Common AC Parameters.”
6
5
07/2011 In Section 2.2, “Power Sequencing,” updated power down sequencing information.
07/2011 • In Table 2, “Absolute Maximum Ratings1,” removed footnote 5 from LBIN to OVIN. Also, corrected
footnote 5.
• In Table 3, “Recommended Operating Conditions,” added footnote 2 to AVDD
.
• In Figure 2, “Overshoot/Undershoot Voltage for GVDD/LVDD/OVDD/LBVDD,” added LBVDD
.
• In Table 13, “DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V,” updated IOZ min/max
to –50/50.
• In Figure 11, “RGMII and RTBI AC Timing and Multiplexing Diagrams,” added distinction between
tSKRGT_RX and tSKRGT_TX signals.
• In Table 33, “MII Management AC Timing Specifications,” updated MDC frequency—removed Min and
Max values, added Typical value. Also, updated footnote 2 and removed footnote 3.
• In Table 48, “PCI DC Electrical Characteristics,” updated VIH min value to 2.0.
• In Table 72, “TePBGA II Pinout Listing,” added Note to LGPL4/LFRB_B/LGTA_B/LUPWAIT/LPBSE (to
be consistent with AN3665, “MPC837xE Design Checklist.”
• In Table 74, “Operating Frequencies for TePBGA II,” added Minimum Operating Frequency for eTSEC,
and corrected DDR2 Minimum and Maximum Operating Frequency values.
4
11/2010 • In Table 25, “RGMII and RTBI DC Electrical Characteristics,” updated VIH min value to 1.7.
• In Table 40, “Local Bus General Timing Parameters—PLL Bypass Mode,” added row for tLBKHLR
.
• In Section 10.2, “Local Bus AC Electrical Specifications,” and in Section 23, “Clocking,” updated LCCR
to LCRR.
• In Table 72, “TePBGA II Pinout Listing,” added SD_WP to pin C9. Also clarified TEST_SEL0 and
TEST_SEL1 pins—no change in functionality.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
124
Freescale Semiconductor
Table 87. Document Revision History (continued)
Substantive Change(s)
Revision Date
3
03/2010 • Added Section 4.3, “eTSEC Gigabit Reference Clock Timing.”
• In Table 34, “USB DC Electrical Characteristics,” and Table 35, “USB General Timing Parameters (ULPI
Mode Only),” added table footnotes .
• In Table 39, “Local Bus General Timing Parameters—PLL Enable Mode,” and Table 40, “Local Bus
General Timing Parameters—PLL Bypass Mode,” corrected footnotes for tLBOTOT1, tLBOTOT2, tLBOTOT3
• In Figure 22, “Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 2 (PLL Enable Mode),” and
Figure 24, “Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV] = 4 (PLL Enable Mode),” shifted
“Input Signals: LAD[0:31]/LDP[0:3]” from the falling edge to the rising edge of LSYNC_IN.
• In Figure 63, “Mechanical Dimensions and Bottom Surface Nomenclature of the TEPBGA II,” added
heat spreader.
.
• In Section 25.6, “Pull-Up Resistor Requirements,” removed “Ethernet Management MDIO pin” from list
of open drain type pins.
• In Table 72, “TePBGA II Pinout Listing,” updated the Pin Type column for AVDD_C, AVDD_L, and
AVDD_P pins.
• in Table 72, “TePBGA II Pinout Listing,” added Note 16 to eTSEC pins.
• In Table 77, “CSB Frequency Options for Host Mode,” and Table 78, “CSB Frequency Options for Agent
Mode,” updated csb_clk frequencies available.
• In Table 84, “Part Numbering Nomenclature,” removed footnote to “e300 core Frequency.”
2
10/2009 • In Table 3, “Recommended Operating Conditions,” added “Operating temperature range” values.
• In Table 5, “Power Dissipation 1,” corrected maximal application for 800/400 MHz to 4.3 W.
• In Table 5, “Power Dissipation 1,” added a column for “Typical Application at Tj = 65°C (W)”.
• In Table 5, “Power Dissipation 1,” added a column for “Sleep Power at Tj = 65°C (W)”.
• In Table 11, removed overbar from CFG_CLKIN_DIV.
• In Table 17, “Current Draw Characteristics for MVREF,” updated IMVREF maximum value for both DDR1
and DDR2 to 600 and 400 μA, respectively. Also, updated Note 1 and added Note 2.
• In Table 20, “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” column headings renamed to
“Min” and “Max”. Footnote 2 updated to state “T is the MCK clock period”.
• In Table 20, “DDR1 and DDR2 SDRAM Input AC Timing Specifications,” and Table 21, “DDR1 and
DDR2 SDRAM Output AC Timing Specifications,” clarified that the frequency parameters are data rates.
• In Table 29, “RMII Transmit AC Timing Specifications,” updated tRMTDXI to 2.0 ns.
• In Table 60, Gen 1i/1.5G Transmitter AC Specifications,” and Table 62, Gen 2i/3G Transmitter AC
Specifications,” corrected titles from “Transmitter” to “Receiver”.
• In Table 72, “TePBGA II Pinout Listing,” removed pin THERM0; it is now Reserved. Also added 1.05 V
to VDD pin.
• In Table 74, “Operating Frequencies for TePBGA II,” corrected “DDR2 memory bus frequency (MCK)”
range to 125–200.
• In Table 79, “e300 Core PLL Configuration,” added 3.5:1 and 4:1 core_clk: csb_clk ratio options.
• In Table 80, “Example Clock Frequency Combinations,” updated column heading to “DDR data rate” .
• In Section 20.2, “SPI AC Timing Specifications,” corrected tNIKHOX and tNEKHOX to tNIKHOV and tNEKHOV
,
respectively.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
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125
Table 87. Document Revision History (continued)
Substantive Change(s)
Revision Date
1
02/2009 • In Table 3, “Recommended Operating Conditions,” added two new rows for 800 MHz, and created two
rows for SerDes. In addition, changed 666 to 667 MHz.
• In Table 5, “Power Dissipation 1,” added Notes 4 and 5. In addition, changed 666 to 667 MHz.
• In Table 13, “DDR2 SDRAM DC Electrical Characteristics for GVDD(typ) = 1.8 V,” Table 21, “DDR1 and
DDR2 SDRAM Output AC Timing Specifications,” and Table 72, “TePBGA II Pinout Listing,” added
footnote to references to MVREF, MDQ, and MDQS, referencing AN3665, MPC837xE Design Checklist.
• In Table 21, updated tDDKHCX minimum value for 333 MHz to 2.40.
• In Table 72, “TePBGA II Pinout Listing,” added footnote to USBDR_STP_SUSPEND and modified
footnote 10 and added footnote 14.
• In Table 74, “Operating Frequencies for TePBGA II,” changed 667 to 800 MHz for core_clk.
• In Table 80, “Example Clock Frequency Combinations,” added 800 MHz cells for e300 core.
• Updated part numbering information in AF column in Table 84, “Part Numbering Nomenclature.” In
addition, modified extended temperature information in notes 1 and 4.
• In Table 85, “Available Parts (Core/DDR Data Rate),” added new row for 800/400 MHz.
0
12/2008 Initial public release.
MPC8377E PowerQUICC II Pro Processor Hardware Specifications, Rev. 10
126
Freescale Semiconductor
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Document Number: MPC8377EEC
Rev. 10
07/2014
相关型号:
MPC8377CVRANGA
800MHz, MICROPROCESSOR, PBGA689, 31 X 31 MM, 2.46 MM HEIGHT, 1 MM PITCH, LEAD FREE, PLASTIC, TEBGAII-689
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