MPC8560CPX667JB [NXP]
Integrated Processor Hardware Specifications;
| 型号： | MPC8560CPX667JB |
| 厂家： | 
NXP |
| 描述： | Integrated Processor Hardware Specifications |
| 文件： | 总108页 (文件大小：1644K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC8560EC
Rev. 4.2, 1/2008
Freescale Semiconductor
Technical Data
MPC8560
Integrated Processor
Hardware Specifications
Contents
The MPC8560 integrates a PowerPC™ processor core built
1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . 8
3. Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 13
4. Clock Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5. RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 17
6. DDR SDRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7. Ethernet: Three-Speed, MII Management . . . . . . . . 23
8. Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9. CPM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10. JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11. I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
12. PCI/PCI-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
13. RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
14. Package and Pin Listings . . . . . . . . . . . . . . . . . . . . . 70
15. Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
16. Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
17. System Design Information . . . . . . . . . . . . . . . . . . . 92
18. Document Revision History . . . . . . . . . . . . . . . . . . . 99
19. Device Nomenclature . . . . . . . . . . . . . . . . . . . . . . . 104
on Power Architecture™ technology with system logic
required for networking, telecommunications, and wireless
infrastructure applications. The MPC8560 is a member of
the PowerQUICC™ III family of devices that combine
system-level support for industry-standard interfaces with
processors that implement the embedded category of the
Power Architecture technology. For functional
characteristics of the processor, refer to the MPC8560
PowerQUICC III Integrated Communications Processor
Reference Manual.
To locate any published errata or updates for this document,
contact your Freescale sales office.
© Freescale Semiconductor, Inc., 2008. All rights reserved.
Overview
1 Overview
The following section provides a high-level overview of the MPC8560 features. Figure 1 shows the major
functional units within the MPC8560.
256KB
DDR
SDRAM
DDR SDRAM Controller
L2-Cache/
SRAM
e500 Core
2
I C Controller
e500
Coherency
Module
32 KB L1
I Cache
32 KB L1
D Cache
GPIO
32b
Local Bus Controller
Core Complex Bus
Programmable
Interrupt Controller
IRQs
Serial
RapidIO-8
16 Gb/s
CPM
DMA
RapidIO Controller
PCI Controller
MPHY
UTOPIAs
MCC
ROM
MCC
OCeaN
PCI 64b
133 MHz
FCC
I-Memory
FCC
MIIs,
RMIIs
DMA Controller
FCC
DPRAM
SCC
TDMs
I/Os
SCC
SCC
SCC
SPI
RISC
10/100/1000 MAC
10/100/1000 MAC
Engine
MII, GMII, TBI,
RTBI, RGMIIs
Parallel I/O
Baud Rate
Generators
I2C
Timers
CPM
Interrupt
Controller
Figure 1. MPC8560 Block Diagram
1.1 Key Features
The following lists an overview of the MPC8560 feature set.
•
High-performance, 32-bit Book E–enhanced core that implements the Power Architecture
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can
be locked entirely or on a per-line basis. Separate locking for instructions and data
— Memory management unit (MMU) especially designed for embedded applications
— Enhanced hardware and software debug support
— Performance monitor facility (similar to but different from the MPC8560 performance monitor
described in Chapter 18, “Performance Monitor.”
•
High-performance RISC CPM operating at up to 333 MHz
— CPM software compatibility with previous PowerQUICC families
— One instruction per clock
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
2
Freescale Semiconductor
Overview
— Executes code from internal ROM or instruction RAM
— 32-bit RISC architecture
— Tuned for communication environments: instruction set supports CRC computation and bit
manipulation.
— Internal timer
— Interfaces with the embedded e500 core processor through a 32-Kbyte dual-port RAM and
virtual DMA channels for each peripheral controller
— Handles serial protocols and virtual DMA.
— Three full-duplex fast serial communications controllers (FCCs) that support the following
protocols:
– ATM protocol through UTOPIA interface (FCC1 and FCC2 only)
– IEEE Std 802.3™/Fast Ethernet
– HDLC
– Totally transparent operation
— Two multi-channel controllers (MCCs) that together can handle up to 256 HDLC/transparent
channels at 64 Kbps each, multiplexed on up to 8 TDM interfaces
— Four full-duplex serial communications controllers (SCCs) that support the following
protocols:
– High level/synchronous data link control (HDLC/SDLC)
– LocalTalk (HDLC-based local area network protocol)
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART (1x clock mode)
– Binary synchronous communication (BISYNC)
– Totally transparent operation
— Serial peripheral interface (SPI) support for master or slave
2
— I C bus controller
— Time-slot assigner supports multiplexing of data from any of the SCCs and FCCs onto eight
time-division multiplexed (TDM) interfaces. The time-slot assigner supports the following
TDM formats:
– T1/CEPT lines
– T3/E3
– Pulse code modulation (PCM) highway interface
– ISDN primary rate
– Freescale interchip digital link (IDL)
– General circuit interface (GCI)
— User-defined interfaces
— Eight independent baud rate generators (BRGs)
— Four general-purpose 16-bit timers or two 32-bit timers
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
3
Overview
— General-purpose parallel ports—16 parallel I/O lines with interrupt capability
— Supports inverse muxing of ATM cells (IMA)
256 Kbyte L2 cache/SRAM
•
— Can be configured as follows
– Full cache mode (256-Kbyte cache).
– Full memory-mapped SRAM mode (256-Kbyte SRAM mapped as a single 256-Kbyte
block or two 128-Kbyte blocks)
– Half SRAM and half cache mode (128-Kbyte cache and 128-Kbyte memory-mapped
SRAM)
— Full ECC support on 64-bit boundary in both cache and SRAM modes
— Cache mode supports instruction caching, data caching, or both
— External masters can force data to be allocated into the cache through programmed memory
ranges or special transaction types (stashing)
— Eight-way set-associative cache organization (1024 sets of 32-byte cache lines)
— Supports locking the entire cache or selected lines. Individual line locks are set and cleared
through Book E instructions or by externally mastered transactions
— Global locking and flash clearing done through writes to L2 configuration registers
— Instruction and data locks can be flash cleared separately
— Read and write buffering for internal bus accesses
— SRAM features include the following:
– I/O devices access SRAM regions by marking transactions as snoopable (global)
– Regions can reside at any aligned location in the memory map
– Byte accessible ECC is protected using read-modify-write transactions accesses for smaller
than cache-line accesses.
•
•
Address translation and mapping unit (ATMU)
— Eight local access windows define mapping within local 32-bit address space
— Inbound and outbound ATMUs map to larger external address spaces
– Three inbound windows plus a configuration window on PCI/PCI-X
– Four inbound windows plus a default and configuration window on RapidIO
– Four outbound windows plus default translation for PCI
– Eight outbound windows plus default translation for RapidIO
DDR memory controller
— Programmable timing supporting DDR-1 SDRAM
— 64-bit data interface, up to 333-MHz data rate
— Four banks of memory supported, each up to 1 Gbyte
— DRAM chip configurations from 64 Mbits to 1 Gbit with x8/x16 data ports
— Full ECC support
— Page mode support (up to 16 simultaneous open pages)
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
4
Freescale Semiconductor
Overview
— Contiguous or discontiguous memory mapping
— Read-modify-write support for RapidIO atomic increment, decrement, set, and clear
transactions
— Sleep mode support for self refresh SDRAM
— Supports auto refreshing
— On-the-fly power management using CKE signal
— Registered DIMM support
— Fast memory access via JTAG port
— 2.5-V SSTL2 compatible I/O
•
RapidIO interface unit
— 8-bit RapidIO I/O and messaging protocols
— Source-synchronous double data rate (DDR) interfaces
— Supports small type systems (small domain, 8-bit device ID)
— Supports four priority levels (ordering within a level)
— Reordering across priority levels
— Maximum data payload of 256 bytes per packet
— Packet pacing support at the physical layer
— CRC protection for packets
— Supports atomic operations increment, decrement, set, and clear
— LVDS signaling
•
•
RapidIO–compliant message unit
— One inbound data message structure (inbox)
— One outbound data message structure (outbox)
— Supports chaining and direct modes in the outbox
— Support of up to 16 packets per message
— Support of up to 256 bytes per packet and up to 4 Kbytes of data per message
— Supports one inbound doorbell message structure
Programmable interrupt controller (PIC)
— Programming model is compliant with the OpenPIC architecture
— Supports 16 programmable interrupt and processor task priority levels
— Supports 12 discrete external interrupts
— Supports 4 message interrupts with 32-bit messages
— Supports connection of an external interrupt controller such as the 8259 programmable
interrupt controller
— Four global high resolution timers/counters that can generate interrupts
— Supports 22 other internal interrupt sources
— Supports fully nested interrupt delivery
— Interrupts can be routed to external pin for external processing
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
5
Overview
— Interrupts can be routed to the e500 core’s standard or critical interrupt inputs
— Interrupt summary registers allow fast identification of interrupt source
2
•
I C controller
— Two-wire interface
— Multiple master support
2
— Master or slave I C mode support
— On-chip digital filtering rejects spikes on the bus
Boot sequencer
•
•
2
— Optionally loads configuration data from serial ROM at reset via the I C interface
— Can be used to initialize configuration registers and/or memory
2
— Supports extended I C addressing mode
— Data integrity checked with preamble signature and CRC
Local bus controller (LBC)
— Multiplexed 32-bit address and data operating at up to 166 MHz
— Eight chip selects support eight external slaves
— Up to eight-beat burst transfers
— The 32-, 16-, and 8-bit port sizes are controlled by an on-chip memory controller
— Three protocol engines available on a per chip select basis:
– General purpose chip select machine (GPCM)
– Three user programmable machines (UPMs)
– Dedicated single data rate SDRAM controller
— Parity support
— Default boot ROM chip select with configurable bus width (8-,16-, or 32-bit)
Two three-speed (10/100/1Gb) Ethernet controllers (TSECs)
— Dual IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers
— Support for different Ethernet physical interfaces:
– 10/100/1Gb Mbps IEEE 802.3 GMII
•
– 10/100 Mbps IEEE 802.3 MII
– 10 Mbps IEEE 802.3 MII
– 1000 Mbps IEEE 802.3z TBI
– 10/100/1Gb Mbps RGMII/RTBI
— Full- and half-duplex support
— Buffer descriptors are backward compatible with MPC8260 and MPC860T 10/100
programming models
— 9.6-Kbyte jumbo frame support
— RMON statistics support
— 2-Kbyte internal transmit and receive FIFOs
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
6
Freescale Semiconductor
Overview
— MII management interface for control and status
— Programmable CRC generation and checking
— Ability to force allocation of header information and buffer descriptors into L2 cache.
OCeaN switch fabric
•
•
— Four-port crossbar packet switch
— Reorders packets from a source based on priorities
— Reorders packets to bypass blocked packets
— Implements starvation avoidance algorithms
— Supports packets with payloads of up to 256 bytes
Integrated DMA controller
— Four-channel controller
— All channels accessible by both the local and remote masters
— Extended DMA functions (advanced chaining and striding capability)
— Support for scatter and gather transfers
— Misaligned transfer capability
— Interrupt on completed segment, link, list, and error
— Supports transfers to or from any local memory or I/O port
— Selectable hardware-enforced coherency (snoop/no-snoop)
— Ability to start and flow control each DMA channel from external 3-pin interface
— Ability to launch DMA from single write transaction
PCI/PCI-X controller
•
— PCI 2.2 and PCI-X 1.0 compatible
— 64- or 32-bit PCI port supports at 16 to 66 MHz
— 64-bit PCI-X support up to 133 MHz
— Host and agent mode support
— 64-bit dual address cycle (DAC) support
— PCI-X supports multiple split transactions
— Supports PCI-to-memory and memory-to-PCI streaming
— Memory prefetching of PCI read accesses
— Supports posting of processor-to-PCI and PCI-to-memory writes
— PCI 3.3-V compatible
— Selectable hardware-enforced coherency
Power management
•
— Fully static 1.2-V CMOS design with 3.3- and 2.5-V I/O
— Supports power saving modes: doze, nap, and sleep
— Employs dynamic power management, which automatically minimizes power consumption of
blocks when they are idle.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
7
Electrical Characteristics
•
System performance monitor
— Supports eight 32-bit counters that count the occurrence of selected events
— Ability to count up to 512 counter-specific events
— Supports 64 reference events that can be counted on any of the 8 counters
— Supports duration and quantity threshold counting
— Burstiness feature that permits counting of burst events with a programmable time between
bursts
— Triggering and chaining capability
— Ability to generate an interrupt on overflow
System access port
•
— Uses JTAG interface and a TAP controller to access entire system memory map
— Supports 32-bit accesses to configuration registers
— Supports cache-line burst accesses to main memory
— Supports large block (4-Kbyte) uploads and downloads
— Supports continuous bit streaming of entire block for fast upload and download
IEEE Std 1149.1™-compliant, JTAG boundary scan
783 FC-PBGA package
•
•
2 Electrical Characteristics
This section provides the electrical specifications and thermal characteristics for the MPC8560. The
MPC8560 is currently targeted to these specifications. Some of these specifications are independent of the
I/O cell, but are included for a more complete reference. These are not purely I/O buffer design
specifications.
2.1 Overall DC Electrical Characteristics
This section covers the ratings, conditions, and other characteristics.
2.1.1 Absolute Maximum Ratings
Table 1 provides the absolute maximum ratings.
1
Table 1. Absolute Maximum Ratings
Characteristic
Symbol
Max Value
Unit
Notes
Core supply voltage
PLL supply voltage
V
V
—
DD
–0.3 to 1.32
–0.3 to 1.43
For devices rated at 667 and 833 MHz
For devices rated at 1 GHz
AV
V
—
DD
–0.3 to 1.32
–0.3 to 1.43
For devices rated at 667 and 833 MHz
For devices rated at 1 GHz
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
8
Freescale Semiconductor
Electrical Characteristics
1
Table 1. Absolute Maximum Ratings (continued)
Characteristic Symbol Max Value
Unit
Notes
DDR DRAM I/O voltage
GV
–0.3 to 3.63
V
V
—
—
DD
Three-speed Ethernet I/O voltage
LV
–0.3 to 3.63
–0.3 to 2.75
DD
CPM, PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet,MII
OV
–0.3 to 3.63
V
3
DD
management, DUART, system control and power management,
2
I C, and JTAG I/O voltage
Input voltage
DDR DRAM signals
MV
–0.3 to (GV + 0.3)
V
V
V
V
2, 5
2, 5
4, 5
5
IN
DD
DDR DRAM reference
Three-speed Ethernet signals
MV
–0.3 to (GV + 0.3)
DD
REF
LV
–0.3 to (LV + 0.3)
DD
IN
CPM, Local bus, RapidIO, 10/100
Ethernet, SYSCLK, system
OV
–0.3 to (OV + 0.3)
DD
IN
control and power management,
2
I C, and JTAG signals
PCI/PCI-X
OV
–0.3 to (OV + 0.3)
V
6
IN
DD
Storage temperature range
T
–55 to 150
°C
—
STG
Notes:
1. Functional and tested operating conditions are given in Table 2. Absolute maximum ratings are stress ratings only, and
functional operation at the maximums is not guaranteed. Stresses beyond those listed may affect device reliability or cause
permanent damage to the device.
2. Caution: MV must not exceed GV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
IN
DD
power-on reset and power-down sequences.
3. Caution: OV must not exceed OV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
IN
DD
power-on reset and power-down sequences.
4. Caution: LV must not exceed LV by more than 0.3 V. This limit may be exceeded for a maximum of 20 ms during
IN
DD
power-on reset and power-down sequences.
5. (M,L,O)V and MV may overshoot/undershoot to a voltage and for a maximum duration as shown in Figure 2.
IN
REF
6. OV on the PCI interface may overshoot/undershoot according to the PCI Electrical Specification for 3.3-V operation, as
IN
shown in Figure 3.
2.1.2 Power Sequencing
The MPC8560 requires its power rails to be applied in a specific sequence in order to ensure proper device
operation. These requirements are as follows for power up:
1. V , AV
DD
DD
2. GV , LV , OV (I/O supplies)
DD
DD
DD
Items on the same line have no ordering requirement with respect to one another. Items on separate lines
must be ordered sequentially such that voltage rails on a previous step must reach 90 percent of their value
before the voltage rails on the current step reach 10 percent of theirs.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
9
Electrical Characteristics
NOTE
If the items on line 2 must precede items on line 1, please ensure that the
delay will not exceed 500 ms and the power sequence is not done greater
than once per day in production environment.
NOTE
From a system standpoint, if the I/O power supplies ramp prior to the V
DD
core supply, the I/Os on the MPC8560 may drive a logic one or zero during
power-up.
2.1.3 Recommended Operating Conditions
Table 2 provides the recommended operating conditions for the MPC8560. Note that the values in Table 2
are the recommended and tested operating conditions. Proper device operation outside of these conditions
is not guaranteed.
Table 2. Recommended Operating Conditions
Recommended
Characteristic
Symbol
Unit
Value
Core supply voltage
PLL supply voltage
V
V
DD
1.2 V 60 mV
1.3 V 50 mV
For devices rated at 667 and 833 MHz
For devices rated at 1 GHz
AV
V
DD
1.2 V 60 mV
1.3 V 50 mV
For devices rated at 667 and 833 MHz
For devices rated at 1 GHz
DDR DRAM I/O voltage
GV
2.5 V 125 mV
V
V
DD
Three-speed Ethernet I/O voltage
LV
3.3 V 165 mV
2.5 V 125 mV
DD
CPM, PCI/PCI-X, local bus, RapidIO, 10/100 Ethernet, MII management,
DUART, system control and power management, I C, and JTAG I/O voltage
OV
3.3 V 165 mV
V
DD
2
Input voltage
DDR DRAM signals
MV
GND to GV
V
V
V
V
IN
DD
DDR DRAM reference
Three-speed Ethernet signals
MV
GND to GV
DD/2
REF
LV
GND to LV
DD
IN
CPM, PCI/PCI-X, local bus,
RapidIO, 10/100 Ethernet, MII
management, DUART, SYSCLK,
system control and power
OV
GND to OV
DD
IN
2
management, I C, and JTAG
signals
Die-junction temperature
T
0 to 105
°C
j
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
10
Freescale Semiconductor
Electrical Characteristics
Figure 2 shows the undershoot and overshoot voltages at the interfaces of the MPC8560.
G/L/OV + 20%
DD
G/L/OV + 5%
DD
G/L/OV
V
DD
IH
GND
GND – 0.3 V
V
IL
GND – 0.7 V
Not to Exceed 10%
1
of t
SYS
Note:
SYS
t
refers to the clock period associated with the SYSCLK signal.
Figure 2. Overshoot/Undershoot Voltage for GV /OV /LV
DD
DD
DD
The MPC8560 core voltage must always be provided at nominal 1.2 V (see Table 2 for actual
recommended core voltage). Voltage to the processor interface I/Os are provided through separate sets of
supply pins and must be provided at the voltages shown in Table 2. The input voltage threshold scales with
respect to the associated I/O supply voltage. OV and LV based receivers are simple CMOS I/O
DD
DD
circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM interface uses a
single-ended differential receiver referenced the externally supplied MV signal (nominally set to
REF
GV /2) as is appropriate for the SSTL2 electrical signaling standard.
DD
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
11
Electrical Characteristics
Figure 3 shows the undershoot and overshoot voltage of the PCI interface of the MPC8560 for the 3.3-V
signals, respectively.
11 ns
(Min)
+7.1 V
Overvoltage
Waveform
7.1 V p-to-p
(Min)
0 V
4 ns
(Max)
4 ns
(Max)
62.5 ns
+3.6 V
Undervoltage
Waveform
7.1 V p-to-p
(Min)
–3.5 V
Figure 3. Maximum AC Waveforms on PCI interface for 3.3-V Signaling
2.1.4 Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
Table 3. Output Drive Capability
Programmable Output
Driver Type
Supply Voltage
OV = 3.3 V
Notes
Impedance (Ω)
Local bus interface utilities signals
25
1
DD
42 (default)
PCI signals
25
2
42 (default)
DDR signal
20
42
GV = 2.5 V
—
—
—
—
—
DD
CPM PA, PB, PC, and PD signals
TSEC/10/100 signals
DUART, system control, I2C, JTAG
RapidIO N/A (LVDS signaling)
Notes:
OV = 3.3 V
DD
42
LV = 2.5/3.3 V
DD
42
OV = 3.3 V
DD
N/A
1. The drive strength of the local bus interface is determined by the configuration of the appropriate bits in
PORIMPSCR.
2. The drive strength of the PCI interface is determined by the setting of the PCI_GNT1 signal at reset.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
12
Freescale Semiconductor
Power Characteristics
3 Power Characteristics
The estimated power dissipation on the V supply for the MPC8560 is shown in Table 4.
DD
1,2
Table 4. MPC8560 V Power Dissipation
DD
3,4
5
CCB Frequency (MHz) Core Frequency (MHz) Typical Power
Maximum Power
Unit
200
267
333
400
500
600
533
667
800
667
833
1000
5.1
5.4
5.8
6.0
6.4
6.9
6.8
7.4
11.9
7.7
8.0
W
8.4
8.7
W
W
9.2
10.7
9.8
11.4
16.5
6
Notes:
1. The values do not include I/O supply power (OV , LV , GV ) or AV .
DD
DD
DD
DD
2. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance,
mounting site (board) temperature, air flow, power dissipation of other components on the board, and
board thermal resistance. Any customer design must take these considerations into account to ensure
the maximum 105 °C junction temperature is not exceeded on this device.
3. Typical Power is based on a nominal voltage of V = 1.2 V, a nominal process, a junction temperature
DD
of T = 105 °C, and a Dhrystone 2.1 benchmark application.
j
4. Thermal solutions will likely need to design to a number higher than Typical Power based on the end
application, T target, and I/O power.
A
5. Maximum power is based on a nominal voltage of V = 1.2 V, worst case process, a junction
DD
temperature of T = 105 °C, and an artificial smoke test.
j
6. The nominal recommended V is 1.3 V for this speed grade.
DD
The estimated power dissipation on the AV supplies for the MPC8560 PLLs is shown in Table 5.
DD
Table 5. MPC8560 AV Power Dissipation
DD
1
AV
n
Typical
Unit
DD
AV
AV
AV
1
2
3
0.007
0.014
0.004
W
W
W
DD
DD
DD
Notes:
1. V = 1.2 V(1.3 V for 1.0 GHz device), T = 105°C
DD
J
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
13
Power Characteristics
Table 6 provides estimated I/O power numbers for each block: DDR, PCI, Local Bus, RapidIO, TSEC, and
CPM.
Table 6. Estimated Typical I/O Power Consumption
Interface
Parameter
GV (2.5 V) OV (3.3 V) LV (3.3 V) LV (2.5 V)
Units
Notes
DD
DD
DD
DD
DDR I/O
CCB = 200 MHz
CCB = 266 MHz
CCB = 300 MHz
CCB = 333 MHz
32-bit, 33 MHz
32-bit 66 MHz
64-bit, 66 MHz
64-bit, 133 MHz
32-bit, 33 MHz
32-bit, 66 MHz
32-bit, 133 MHz
32-bit, 167 MHz
500 MHz data rate
MII
0.46
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
W
1
0.59
0.66
0.73
—
—
—
—
PCI/PCI-X I/O
Local Bus I/O
0.04
0.07
0.14
0.25
0.07
0.13
0.24
0.30
0.96
—
W
W
2
3
—
—
—
—
—
—
—
RapidIO I/O
TSEC I/O
—
W
4
—
10
—
70
—
—
—
—
—
—
—
—
—
mW
5, 6
GMII, TBI (2.5 V)
GMII, TBI (3.3 V)
RGMII, RTBI
—
—
40
—
40
—
—
—
—
—
—
—
—
—
—
—
—
CPM-FCC
MII
—
15
mW
7
RMII
—
13
HDLC 16 Mbps
UTOPIA-8 SPHY
UTOPIA-8 MPHY
UTOPIA-16 SPHY
UTOPIA-16 MPHY
HDLC 16 Mbps
—
9
—
60
—
100
94
—
—
135
4
CPM-SCC
—
mW
7
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
14
Freescale Semiconductor
Clock Timing
Table 6. Estimated Typical I/O Power Consumption (continued)
Interface
Parameter
GV (2.5 V) OV (3.3 V) LV (3.3 V) LV (2.5 V)
Units
Notes
DD
DD
DD
DD
TDMA or TDMB
Nibble mode
Per channel
—
10
—
—
—
—
mW
7
—
5
Notes:
1. GV =2.5, ECC enabled, 66% bus utilization, 33% write cycles, 10pF load on data, 10pF load on address/command, 10pF
DD
load on clock
2. OV =3.3, 30pF load per pin, 54% bus utilization, 33% write cycles
DD
3. OV =3.3, 25pF load per pin, 5pF load on clock, 40% bus utilization, 33% write cycles
DD
4. V =1.2, OV =3.3
DD
DD
5. LVDD=2.5/3.3, 15pF load per pin, 25% bus utilization
6. Power dissipation for one TSEC only
7. OV =3.3, 10pF load per pin, 50% bus utilization
DD
4 Clock Timing
4.1 System Clock Timing
Table 7 provides the system clock (SYSCLK) AC timing specifications for the MPC8560.
Table 7. SYSCLK AC Timing Specifications
Parameter/Condition
SYSCLK frequency
Symbol
Min
Typical
Max
Unit
Notes
f
—
6.0
0.6
40
—
—
—
166
—
MHz
ns
1
—
2
SYSCLK
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle
SYSCLK jitter
t
SYSCLK
t
, t
1.0
—
1.2
ns
KH KL
t
/t
60
%
3
KHKL SYSCLK
—
—
+/- 150
ps
4, 5
Notes:
1.Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to Section 15.2, “Platform/System PLL Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio
settings.
2. Rise and fall times for SYSCLK are measured at 0.6 V and 2.7 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. For spread spectrum clocking, guidelines are +/-1% of the input frequency with a maximum of 60 kHz of modulation
regardless of the input frequency.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
15
Clock Timing
4.2 TSEC Gigabit Reference Clock Timing
Table 7 provides the TSEC gigabit reference clock (EC_GTX_CLK125) AC timing specifications for the
MPC8560.
Table 8. EC_GTX_CLK125 AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
EC_GTX_CLK125 frequency
EC_GTX_CLK125 cycle time
EC_GTX_CLK125 rise and fall time
f
t
—
—
—
125
8
—
—
MHz
ns
—
—
2
G125
G125
t
, t
—
ns
G125R G125F
0.75
1
LV =2.5
DD
LV =3.3
DD
EC_GTX_CLK125 duty cycle
t
/t
—
%
1, 3
G125H G125
45
47
55
53
GMII, TBI
RGMII, RTBI
Notes:
1. Timing is guaranteed by design and characterization.
2. Rise and fall times for EC_GTX_CLK125 are measured from 0.5V and 2.0V for LV =2.5V, and from 0.6 and 2.7V for
DD
LV =3.3V.
DD
3. EC_GTX_CLK125 is used to generate GTX clock for TSEC transmitter with 2% degradation EC_GTX_CLK125 duty cycle
can be loosened from 47/53% as long as PHY device can tolerate the duty cycle generated by GTX_CLK of TSEC.
4.3 RapidIO Transmit Clock Input Timing
Table 9 provides the RapidIO transmit clock input (RIO_TX_CLK_IN) AC timing specifications for the
MPC8560.
Table 9. RIO_TX_CLK_IN AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Notes
RIO_TX_CLK_IN frequency
RIO_TX_CLK_IN cycle time
RIO_TX_CLK_IN duty cycle
Notes:
f
t
125
—
—
—
—
—
8
MHz
ns
—
—
1
RCLK
RCLK
t
/t
48
52
%
RCLKH RCLK
1. Requires 100 ppm long term frequency stability. Timing is guaranteed by design and characterization.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
16
Freescale Semiconductor
RESET Initialization
4.4 Real Time Clock Timing
Table 10 provides the real time clock (RTC) AC timing specifications for the MPC8560.
Table 10. RTC AC Timing Specifications
Parameter/Condition
RTC clock high time
Symbol
Min
Typical
Max
Unit
Notes
t
2 x
—
—
ns
—
RTCH
t
t
CCB_CLK
RTC clock low time
t
2 x
—
—
ns
—
RTCL
CCB_CLK
5 RESET Initialization
This section describes the AC electrical specifications for the RESET initialization timing requirements of
the MPC8560. Table 7 provides the RESET initialization AC timing specifications for the MPC8560.
Table 11. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Notes
Required assertion time of HRESET
Minimum assertion time for SRESET
100
512
100
—
—
—
μs
SYSCLKs
μs
—
1
PLL input setup time with stable SYSCLK before
HRESET negation
—
Input setup time for POR configs (other than PLL config)
with respect to negation of HRESET
4
2
—
—
5
SYSCLKs
SYSCLKs
SYSCLKs
1
1
1
Input hold time for POR configs (including PLL config)
with respect to negation of HRESET
Maximum valid-to-high impedance time for actively
driven POR configs with respect to negation of HRESET
—
Notes:
1.SYSCLK is identical to the PCI_CLK signal and is the primary clock input for the MPC8560. See the MPC8560
PowerQUICC III™ Integrated Communications Processor Preliminary Reference Manual for more details.
Table 12 provides the PLL and DLL lock times.
Table 12. PLL and DLL Lock Times
Parameter/Condition
Min
Max
Unit
Notes
PLL lock times
DLL lock times
Notes:
—
100
μs
—
7680
122,880
CCB Clocks
1, 2
1.DLL lock times are a function of the ratio between the output clock and the platform (or CCB) clock. A 2:1 ratio
results in the minimum and an 8:1 ratio results in the maximum.
2. The CCB clock is determined by the SYSCLK × platform PLL ratio.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
17
DDR SDRAM
6 DDR SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface of the
MPC8560.
6.1 DDR SDRAM DC Electrical Characteristics
Table 13 provides the recommended operating conditions for the DDR SDRAM component(s) of the
MPC8560.
Table 13. DDR SDRAM DC Electrical Characteristics
Parameter/Condition
I/O supply voltage
Symbol
Min
Max
Unit
Notes
GV
MV
2.375
2.625
V
V
1
2
DD
I/O reference voltage
I/O termination voltage
Input high voltage
0.49 × GV
0.51 × GV
DD
REF
TT
DD
V
MV
– 0.04
+ 0.18
MV
+ 0.04
REF
V
3
REF
REF
V
MV
GV + 0.3
V
4
IH
DD
Input low voltage
V
I
–0.3
MV
– 0.18
REF
V
4
IL
Output leakage current
–10
–15.2
15.2
—
10
μA
mA
mA
μA
5
OZ
OH
Output high current (V
= 1.95 V)
I
—
—
—
—
—
OUT
Output low current (V
= 0.35 V)
I
OL
OUT
MV
input leakage current
I
100
REF
VREF
Notes:
1.GV is expected to be within 50 mV of the DRAM GV at all times.
DD
DD
2.MV
is expected to be equal to 0.5 × GV , and to track GV DC variations as measured at the receiver.
DD DD
REF
Peak-to-peak noise on MV
may not exceed 2% of the DC value.
REF
3.V is not applied directly to the device. It is the supply to which far end signal termination is made and is expected
TT
to be equal to MV
. This rail should track variations in the DC level of MV
.
REF
REF
4.V can tolerate an overshoot of 1.2V over GV for a pulse width of ≤3 ns, and the pulse width cannot be greater
IH
DD
than t
. V can tolerate an undershoot of 1.2V below GND for a pulse width of ≤3 ns, and the pulse width
MCK
IL
cannot be greater than t
.
MCK
5.Output leakage is measured with all outputs disabled, 0 V ≤ VOUT ≤ GV
.
DD
Table 14 provides the DDR capacitance.
Table 14. DDR SDRAM Capacitance
Parameter/Condition
Symbol
Min
Max
Unit
Notes
Input/output capacitance: DQ, DQS, MSYNC_IN
Delta input/output capacitance: DQ, DQS
Note:
C
6
8
pF
pF
1
1
IO
C
—
0.5
DIO
1.This parameter is sampled. GV = 2.5 V 0.125 V, f = 1 MHz, T = 25°C, V
= GV /2, V (peak to peak) = 0.2 V.
OUT
DD
A
OUT
DD
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
18
Freescale Semiconductor
DDR SDRAM
6.2 DDR SDRAM AC Electrical Characteristics
This section provides the AC electrical characteristics for the DDR SDRAM interface.
6.2.1 DDR SDRAM Input AC Timing Specifications
Table 15 provides the input AC timing specifications for the DDR SDRAM interface.
Table 15. DDR SDRAM Input AC Timing Specifications
At recommended operating conditions with GVDD of 2.5 V 5%.
Parameter
AC input low voltage
Symbol
Min
Max
– 0.31
REF
Unit
Notes
V
—
MV
V
V
—
—
IL
AC input high voltage
V
MV
+ 0.31
GV + 0.3
IH
REF
DD
MDQS—MDQ/MECC input skew per byte
t
ps
1, 2
DISKEW
-750
-1125
750
1125
For DDR = 333 MHz
For DDR ≤ 266 MHz
Note:
1.Maximum possible skew between a data strobe (MDQS[n]) and any corresponding bit of data (MDQ[8n + {0...7}] if
0 ≤ n ≤ 7) or ECC (MECC[{0...7}] if n=8).
2.For timing budget analysis, the MPC8560 consumes 550 ps of the total budget.
MDQS[n]
MDQ[n]
t
t
DISKEW
DISKEW
Figure 4. DDR SDRAM Interface Input Timing
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
19
DDR SDRAM
6.2.2 DDR SDRAM Output AC Timing Specifications
For chip selects MCS1 and MCS2, there will always be at least 200 DDR memory clocks coming out of
self-refresh after an HRESET before a precharge occurs. This will not necessarily be the case for chip
selects MCS0 and MCS3.
6.2.2.1 DLL Enabled Mode
Table 16 and Table 17 provide the output AC timing specifications and measurement conditions for the
DDR SDRAM interface with the DDR DLL enabled.
Table 16. DDR SDRAM Output AC Timing Specifications–DLL Mode
At recommended operating conditions with GVDD of 2.5 V 5%.
1
Parameter
Symbol
Min
Max
Unit
Notes
MCK[n] cycle time, (MCK[n]/MCK[n] crossing)
On chip Clock Skew
t
6
—
45
—
1
10
150
55
3
ns
ps
%
2
MCK
t
3, 8
8
MCKSKEW
MCK[n] duty cycle
t
/t
MCKH MCK
ADDR/CMD output valid
t
t
ns
ns
ns
ps
4, 9
4, 9
5
DDKHOV
DDKHOX
DDSHMH
DDKHDS,
ADDR/CMD output invalid
—
Write CMD to first MDQS capture edge
t
t
+ 1.5
t
+ 4.0
MCK
MCK
MDQ/MECC/MDM output setup with respect to
MDQS
t
t
t
—
—
6, 9
t
DDKLDS
900
1100
1200
333 MHz
266 MHz
200 MHz
MDQ/MECC/MDM output hold with respect to
MDQS
ps
ns
6, 9
7, 8
DDKHDX,
t
DDKLDX
900
1100
1200
333 MHz
266 MHz
200 MHz
MDQS preamble start
0.75 × t
+ 1.5
0.75 × t
+ 4.0
MCK
DDSHMP
MCK
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
20
Freescale Semiconductor
DDR SDRAM
Table 16. DDR SDRAM Output AC Timing Specifications–DLL Mode (continued)
At recommended operating conditions with GVDD of 2.5 V 5%.
1
Parameter Symbol
Min
Max
Unit
Notes
MDQS epilogue end
Notes:
1.The symbols used for timing specifications follow the pattern of t
t
1.5
4.0
ns
7, 8
DDSHME
for
(first two letters of functional block)(signal)(state) (reference)(state)
inputs and t
for outputs. Output hold time can be read as DDR
(first two letters of functional block)(reference)(state)(signal)(state)
timing (DD) from the rising or falling edge of the reference clock (KH or KL) until the output went invalid (OX or DX). For
example, t symbolizes DDR timing (DD) for the time t memory clock reference (K) goes from the high (H)
DDKHOV
MCK
state until outputs (O) are valid (V) or output valid time. Also, t
symbolizes DDR timing (DD) for the time t
MCK
DDKLDX
memory clock reference (K) goes low (L) until data outputs (D) are invalid (X) or data output hold time.
2.All MCK/MCK referenced measurements are made from the crossing of the two signals 0.1 V.
3.Maximum possible clock skew between a clock MCK[n] and its relative inverse clock MCK[n], or between a clock MCK[n]
and a relative clock MCK[m] or MSYNC_OUT. Skew measured between complementary signals at GV /2.
DD
4.ADDR/CMD includes all DDR SDRAM output signals except MCK/MCK and MDQ/MECC/MDM/MDQS.
5.Note that t
follows the symbol conventions described in note 1. For example, t
describes the DDR timing
DDSHMH
DDSHMH
(DD) from the rising edge of the MSYNC_IN clock (SH) until the MDQS signal is valid (MH). t
can be modified
DDSHMH
through control of the DQSS override bits in the TIMING_CFG_2 register. These controls allow the relationship between
the synchronous clock control timing and the source-synchronous DQS domain to be modified by the user. For best
turnaround times, these may need to be set to delay t
an additional 0.25t
. This will also affect t
and
DDSHMH
MCK
DDSHMP
t
accordingly. See the MPC8560 PowerQUICC III Integrated Communications Processor Reference Manual for
DDSHME
a description and understanding of the timing modifications enabled by use of these bits.
6.Determined by maximum possible skew between a data strobe (MDQS) and any corresponding bit of data (MDQ), ECC
(MECC), or data mask (MDM). The data strobe should be centered inside of the data eye at the pins of the MPC8560.
7.All outputs are referenced to the rising edge of MSYNC_IN (S) at the pins of the MPC8560. Note that t
follows the
DDSHMP
symbol conventions described in note 1. For example, t
describes the DDR timing (DD) from the rising edge of
DDSHMP
the MSYNC_IN clock (SH) for the duration of the MDQS signal precharge period (MP).
8.Guaranteed by design.
9.Guaranteed by characterization.
Figure 5 provides the AC test load for the DDR bus.
Output
GV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 5. DDR AC Test Load
Table 17. DDR SDRAM Measurement Conditions
Symbol
DDR
Unit
Notes
V
MV
0.31 V
V
V
1
2
TH
REF
V
0.5 × GV
DD
OUT
Notes:
1.Data input threshold measurement point.
2.Data output measurement point.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
21
DDR SDRAM
Figure 6 shows the DDR SDRAM output timing diagram.
MCK[n]
MCK[n]
tt
t
MCK
MCKH
MSYNC_OUT
DLL Phase Alignment
MSYNC_IN
t
DDKHOV
t
DDKHOX
ADDR/CMD
MDQS[n]
Write A0
NOOP
t
DDSHMH
t
t
t
DDSHME
DDSHMP
DDKHDS
t
DDKLDS
MDQ[x]
D0
D1
t
DDKLDX
t
DDKHDX
Figure 6. DDR SDRAM Output Timing Diagram
6.2.2.2 Load Effects on Address/Command Bus
Table 18 provides approximate delay information that can be expected for the address and command
signals of the DDR controller for various loadings. These numbers are the result of simulations for one
topology. The delay numbers will strongly depend on the topology used. These delay numbers show the
total delay for the address and command to arrive at the DRAM devices. The actual delay could be
different than the delays seen in simulation, depending on the system topology. If a heavily loaded system
is used, the DLL loop may need to be adjusted to meet setup requirements at the DRAM.
Table 18. Expected Delays for Address/Command
Load
Delay
Unit
4 devices (12 pF)
9 devices (27 pF)
3.0
3.6
5.0
5.2
ns
ns
ns
ns
36 devices (108 pF) + 40 pF compensation capacitor
36 devices (108 pF) + 80 pF compensation capacitor
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
22
Freescale Semiconductor
Ethernet: Three-Speed, MII Management
7 Ethernet: Three-Speed, MII Management
This section provides the AC and DC electrical characteristics for three-speed and MII management.
7.1 Three-Speed Ethernet Controller (TSEC)
(10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI Electrical
Characteristics
The electrical characteristics specified here apply to all GMII (gigabit media independent interface), MII
(media independent interface), TBI (ten-bit interface), RGMII (reduced gigabit media independent
interface), and RTBI (reduced ten-bit interface) signals except MDIO (management data input/output) and
MDC (management data clock). The RGMII and RTBI interfaces are defined for 2.5 V, while the GMII,
MII, and TBI interfaces can be operated at 3.3 or 2.5 V. Whether the GMII, MII, or TBI interface is
operated at 3.3 or 2.5 V, the timing is compliant with the IEEE 802.3 standard. The RGMII and RTBI
interfaces follow the Hewlett-Packard reduced pin-count interface for Gigabit Ethernet Physical Layer
Device Specification Version 1.2a (9/22/2000). The electrical characteristics for MDIO and MDC are
specified in Section 7.3, “Ethernet Management Interface Electrical Characteristics.”
7.1.1 TSEC DC Electrical Characteristics
All GMII,MII, TBI, RGMII, and RTBI drivers and receivers comply with the DC parametric attributes
specified in Table 19 and Table 20. The potential applied to the input of a GMII,MII, TBI, RGMII, or RTBI
receiver may exceed the potential of the receiver’s power supply (i.e., a GMII driver powered from a 3.6
V supply driving V into a GMII receiver powered from a 2.5 V supply). Tolerance for dissimilar GMII
OH
driver and receiver supply potentials is implicit in these specifications. The RGMII and RTBI signals are
based on a 2.5 V CMOS interface voltage as defined by JEDEC EIA/JESD8-5.
Table 19. GMII, MII, and TBI DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
Supply voltage 3.3 V
Output high voltage (LV = Min, I = –4.0 mA)
LV
3.13
2.40
GND
1.70
–0.3
—
3.47
V
V
DD
V
LV + 0.3
DD
OH
OH
DD
Output low voltage (LV = Min, I = 4.0 mA)
V
OL
0.50
V
DD
OL
Input high voltage
Input low voltage
V
LV + 0.3
V
IH
DD
V
I
0.90
40
V
IL
1
Input high current (V
Input low current (V
= LV
)
μA
μA
IN
DD
IH
1
= GND)
I
–600
—
IN
IL
Note:
1.The symbol V , in this case, represents the LV symbol referenced in Table 1 and Table 2.
IN
IN
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
23
Ethernet: Three-Speed, MII Management
Table 20. GMII, MII, RGMII, RTBI, and TBI DC Electrical Characteristics
Parameters
Symbol
Min
Max
Unit
Supply voltage 2.5 V
Output high voltage (LV = Min, I
LV
2.37
2.00
2.63
V
V
DD
= –1.0 mA)
V
LV + 0.3
DD
OH
OH
DD
Output low voltage (LV = Min, I = 1.0 mA)
V
OL
GND – 0.3
1.70
0.40
V
DD
OL
Input high voltage
Input low voltage
V
LV + 0.3
V
IH
DD
V
I
–0.3
0.70
10
V
IL
1
Input high current (V
Input low current (V
= LV
)
—
μA
μA
IN
DD
IH
1
= GND)
I
–15
—
IN
IL
Note:
1.Note that the symbol V , in this case, represents the LV symbol referenced in Table 1and Table 2.
IN
IN
7.2 GMII, MII, TBI, RGMII, and RTBI AC Timing Specifications
The AC timing specifications for GMII, MII, TBI, RGMII, and RTBI are presented in this section.
7.2.1 GMII AC Timing Specifications
This section describes the GMII transmit and receive AC timing specifications.
7.2.1.1 GMII Transmit AC Timing Specifications
Table 21 provides the GMII transmit AC timing specifications.
Table 21. GMII Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%, or LVDD=2.5V 5%.
1
Parameter/Condition
GTX_CLK clock period
Symbol
Min
Typ
Max
Unit
t
—
40
8.0
—
—
—
—
60
—
ns
%
GTX
GTX_CLK duty cycle
t
/t
GTXH GTX
GMII data TXD[7:0], TX_ER, TX_EN setup time
GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay
t
2.5
0.5
ns
ns
GTKHDV
3
t
5.0
GTKHDX
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
24
Freescale Semiconductor
Ethernet: Three-Speed, MII Management
Table 21. GMII Transmit AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 3.3 V 5%, or LVDD=2.5V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
2,4
GTX_CLK data clock rise and fall time
t
, t
—
—
1.0
ns
GTXR GTXF
Notes:
1. The symbols used for timing specifications herein follow the pattern t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
GTKHDV
symbolizes GMII transmit timing (GT) with respect to the t
clock reference (K) going to the high state (H) relative
GTX
to the time date input signals (D) reaching the valid state (V) to state or setup time. Also, t
symbolizes GMII
GTKHDX
transmit timing (GT) with respect to the t
clock reference (K) going to the high state (H) relative to the time date
GTX
input signals (D) going invalid (X) or hold time. Note that, in general, the clock reference symbol representation is
based on three letters representing the clock of a particular functional. For example, the subscript of t represents
GTX
the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R
(rise) or F (fall).
2.Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3.Guaranteed by characterization.
4.Guaranteed by design.
Figure 7 shows the GMII transmit AC timing diagram.
t
t
GTXR
GTX
GTX_CLK
t
t
GTXH
GTXF
TXD[7:0]
TX_EN
TX_ER
t
GTKHDX
t
GTKHDV
Figure 7. GMII Transmit AC Timing Diagram
7.2.1.2 GMII Receive AC Timing Specifications
Table 22 provides the GMII receive AC timing specifications.
Table 22. GMII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%, or LVDD=2.5V 5%.
1
Parameter/Condition
RX_CLK clock period
Symbol
Min
Typ
Max
Unit
t
—
40
8.0
—
—
—
—
60
—
—
ns
ns
ns
ns
GRX
RX_CLK duty cycle
t
/t
GRXH GRX
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
t
t
2.0
0.5
GRDVKH
GRDXKH
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
25
Ethernet: Three-Speed, MII Management
Table 22. GMII Receive AC Timing Specifications (continued)
At recommended operating conditions with LVDD of 3.3 V 5%, or LVDD=2.5V 5%.
1
Parameter/Condition
Symbol
, t
Min
Typ
Max
Unit
2,3
RX_CLK clock rise and fall time
Note:
1.The symbols used for timing specifications herein follow the pattern of t
t
—
—
1.0
ns
GRXR GRXF
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
GRDVKH
symbolizes GMII receive timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative
to the t clock reference (K) going to the high state (H) or setup time. Also, t symbolizes GMII receive timing
RX
GRDXKL
(GR) with respect to the time data input signals (D) went invalid (X) relative to the t
clock reference (K) going to
GRX
the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters
representing the clock of a particular functional. For example, the subscript of t represents the GMII (G) receive
GRX
(RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3.Guaranteed by design.
Figure 8 provides the AC test load for TSEC.
LV /2
Output
Z = 50 Ω
DD
0
R = 50 Ω
L
Figure 8. TSEC AC Test Load
Figure 9 shows the GMII receive AC timing diagram.
t
t
GRXR
GRX
RX_CLK
t
t
GRXF
GRXH
RXD[7:0]
RX_DV
RX_ER
t
GRDXKH
t
GRDVKH
Figure 9. GMII Receive AC Timing Diagram
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
26
Freescale Semiconductor
Ethernet: Three-Speed, MII Management
7.2.2 MII AC Timing Specifications
This section describes the MII transmit and receive AC timing specifications.
7.2.2.1 MII Transmit AC Timing Specifications
Table 23 provides the MII transmit AC timing specifications.
Table 23. MII Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%, or LVDD=2.5V 5%.
1
Parameter/Condition
TX_CLK clock period 10 Mbps
Symbol
Min
Typ
Max
Unit
2
t
—
—
35
1
400
40
—
5
—
—
ns
ns
%
MTX
TX_CLK clock period 100 Mbps
TX_CLK duty cycle
t
MTX
t
t
65
15
4.0
MTXH/ MTX
TX_CLK to MII data TXD[3:0], TX_ER, TX_EN delay
TX_CLK data clock rise and fall time
Note:
t
ns
ns
MTKHDX
2,3
t
, t
1.0
—
MTXR MTXF
1.The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
MTKHDX
symbolizes MII transmit timing (MT) for the time t
clock reference (K) going high (H) until data outputs (D) are
MTX
invalid (X). Note that, in general, the clock reference symbol representation is based on two to three letters
representing the clock of a particular functional. For example, the subscript of t represents the MII(M) transmit
MTX
(TX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3.Guaranteed by design.
Figure 10 shows the MII transmit AC timing diagram.
t
t
MTXR
MTX
TX_CLK
t
t
MTXH
MTXF
TXD[3:0]
TX_EN
TX_ER
t
MTKHDX
Figure 10. MII Transmit AC Timing Diagram
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
27
Ethernet: Three-Speed, MII Management
7.2.2.2 MII Receive AC Timing Specifications
Table 24 provides the MII receive AC timing specifications.
Table 24. MII Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%, or LVDD=2.5V 5%.
1
Parameter/Condition
RX_CLK clock period 10 Mbps
Symbol
Min
Typ
Max
Unit
3
t
—
—
400
40
—
—
—
ns
ns
%
MRX
RX_CLK clock period 100 Mbps
RX_CLK duty cycle
t
MRX
t
/t
35
65
—
MRXH MRX
RXD[3:0], RX_DV, RX_ER setup time to RX_CLK
RXD[3:0], RX_DV, RX_ER hold time to RX_CLK
RX_CLK clock rise and fall time
Note:
t
t
10.0
10.0
1.0
—
ns
ns
ns
MRDVKH
MRDXKH
—
—
2,3
t
, t
—
4.0
MRXR MRXF
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
MRDVKH
symbolizes MII receive timing (MR) with respect to the time data input signals (D) reach the valid state (V) relative to
the t clock reference (K) going to the high (H) state or setup time. Also, t symbolizes MII receive timing
MRX
MRDXKL
(GR) with respect to the time data input signals (D) went invalid (X) relative to the t
clock reference (K) going to
MRX
the low (L) state or hold time. Note that, in general, the clock reference symbol representation is based on three letters
representing the clock of a particular functional. For example, the subscript of t represents the MII (M) receive
MRX
(RX) clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3.Guaranteed by design.
Figure 11 shows the MII receive AC timing diagram.
t
t
MRXR
MRX
RX_CLK
t
t
MRXH
MRXF
RXD[3:0]
RX_DV
RX_ER
Valid Data
t
MRDVKH
t
MRDXKH
Figure 11. MII Receive AC Timing Diagram
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
28
Freescale Semiconductor
Ethernet: Three-Speed, MII Management
7.2.3 TBI AC Timing Specifications
This section describes the TBI transmit and receive AC timing specifications.
7.2.3.1 TBI Transmit AC Timing Specifications
Table 25 provides the TBI transmit AC timing specifications.
Table 25. TBI Transmit AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%, or LVDD=2.5V 5%.
1
Parameter/Condition
GTX_CLK clock period
Symbol
Min
Typ
Max
Unit
t
—
40
2.0
1.0
—
8.0
—
—
—
—
—
60
—
ns
%
TTX
GTX_CLK duty cycle
t
/t
TTXH TTX
TCG[9:0] setup time GTX_CLK going high
TCG[9:0] hold time from GTX_CLK going high
GTX_CLK clock rise and fall time
Notes:
t
t
ns
ns
ns
TTKHDV
TTKHDX
—
2,3
t
, t
1.0
TTXR TTXF
1.The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state
for inputs and t
for outputs. For example, t
)(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
TTKHDV
symbolizes the TBI transmit timing (TT) with respect to the time from t
(K) going high (H) until the referenced data
TTX
signals (D) reach the valid state (V) or setup time. Also, t
symbolizes the TBI transmit timing (TT) with respect
TTKHDX
to the time from t
(K) going high (H) until the referenced data signals (D) reach the invalid state (X) or hold time.
TTX
Note that, in general, the clock reference symbol representation is based on three letters representing the clock of a
particular functional. For example, the subscript of t represents the TBI (T) transmit (TX) clock. For rise and fall
TTX
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3.Guaranteed by design.
Figure 12 shows the TBI transmit AC timing diagram.
t
t
TTXR
TTX
GTX_CLK
TCG[9:0]
t
TTXH
t
TTXF
t
TTKHDV
t
TTKHDX
Figure 12. TBI Transmit AC Timing Diagram
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
29
Ethernet: Three-Speed, MII Management
7.2.3.2 TBI Receive AC Timing Specifications
Table 26 provides the TBI receive AC timing specifications.
Table 26. TBI Receive AC Timing Specifications
At recommended operating conditions with LVDD of 3.3 V 5%, or LVDD=2.5V 5%.
1
Parameter/Condition
RX_CLK clock period
Symbol
Min
Typ
Max
Unit
t
16.0
—
ns
ns
%
TRX
RX_CLK skew
t
7.5
40
8.5
60
—
SKTRX
RX_CLK duty cycle
t
/t
—
TRXH TRX
RCG[9:0] setup time to rising RX_CLK
RCG[9:0] hold time to rising RX_CLK
RX_CLK clock rise time and fall time
Note:
t
2.5
1.5
0.7
—
ns
ns
ns
TRDVKH
TRDXKH
t
—
—
2,3
t
, t
—
2.4
TRXR TRXF
1.The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
TRDVKH
symbolizes TBI receive timing (TR) with respect to the time data input signals (D) reach the valid state (V) relative to
the t clock reference (K) going to the high (H) state or setup time. Also, t symbolizes TBI receive timing
TRX
TRDXKH
(TR) with respect to the time data input signals (D) went invalid (X) relative to the t
clock reference (K) going to
TRX
the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters
representing the clock of a particular functional. For example, the subscript of t represents the TBI (T) receive (RX)
TRX
clock. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall). For symbols
representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX).
2.Signal timings are measured at 0.7 V and 1.9 V voltage levels.
3.Guaranteed by design.
Figure 13 shows the TBI receive AC timing diagram.
t
t
TRXR
TRX
RX_CLK1
RCG[9:0]
t
t
TRXH
TRXF
Valid Data
Valid Data
t
TRDVKH
t
t
SKTRX
TRDXKH
RX_CLK0
t
t
TRXH
TRDXKH
t
TRDVKH
Figure 13. TBI Receive AC Timing Diagram
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
30
Freescale Semiconductor
Ethernet: Three-Speed, MII Management
7.2.4 RGMII and RTBI AC Timing Specifications
Table 27 presents the RGMII and RTBI AC timing specifications.
Table 27. RGMII and RTBI AC Timing Specifications
At recommended operating conditions with LVDD of 2.5 V 5%.
1
Parameter/Condition
Symbol
Min
Typ
Max
Unit
5
Data to clock output skew (at transmitter)
t
–500
1.0
7.2
45
0
500
2.8
8.8
55
ps
ns
ns
%
SKRGT
2
Data to clock input skew (at receiver)
t
—
SKRGT
6
3
Clock period
t
8.0
50
50
—
RGT
4
6
Duty cycle for 1000Base-T
t
t
/t
RGTH RGT
3
6
Duty cycle for 10BASE-T and 100BASE-TX
/t
40
60
%
RGTH RGT
6,7
Rise and fall time
t
, t
—
0.75
ns
RGTR RGTF
Notes:
1.Note that, in general, the clock reference symbol representation for this section is based on the symbols RGT to
represent RGMII and RTBI timing. For example, the subscript of t represents the TBI (T) receive (RX) clock. Note
RGT
also that the notation for rise (R) and fall (F) times follows the clock symbol that is being represented. For symbols
representing skews, the subscript is skew (SK) followed by the clock that is being skewed (RGT).
2.The RGMII specification requires that PC board designer add 1.5 ns or greater in trace delay to the RX_CLK in order to
meet this specification. However, as stated above, this device will function with only 1.0 ns of delay.
3.For 10 and 100 Mbps, t
scales to 400 ns 40 ns and 40 ns 4 ns, respectively.
RGT
4.Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domains
as long as the minimum duty cycle is not violated and stretching occurs for no more than three t
speed transitioned between.
of the lowest
RGT
5.Guaranteed by characterization.
6.Guaranteed by design.
7.Signal timings are measured at 0.5 V and 2.0 V voltage levels.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
31
Ethernet: Three-Speed, MII Management
Figure 14 shows the RGMII and RTBI AC timing and multiplexing diagrams.
t
RGT
t
RGTH
GTX_CLK
(At Transmitter)
t
SKRGT
TXD[8:5][3:0]
TXD[7:4][3:0]
TXD[8:5]
TXD[7:4]
TXD[3:0]
TXD[9]
TXERR
TXD[4]
TXEN
TX_CTL
t
SKRGT
TX_CLK
(At PHY)
RXD[8:5][3:0]
RXD[7:4][3:0]
RXD[8:5]
RXD[7:4]
RXD[3:0]
t
SKRGT
RXD[9]
RXERR
RXD[4]
RXDV
RX_CTL
t
SKRGT
RX_CLK
(At PHY)
Figure 14. RGMII and RTBI AC Timing and Multiplexing Diagrams
7.3 Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock). The electrical characteristics for
GMII, RGMII, TBI and RTBI are specified in Section 7.1, “Three-Speed Ethernet Controller (TSEC)
(10/100/1Gb Mbps)—GMII/MII/TBI/RGMII/RTBI Electrical Characteristics.”
7.3.1 MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. The DC electrical characteristics
for MDIO and MDC are provided in Table 28.
Table 28. MII Management DC Electrical Characteristics
Parameter
Symbol
OV
Min
Max
Unit
Supply voltage (3.3 V)
Output high voltage (OV = Min, I = –1.0 mA)
3.13
2.10
GND
1.70
—
3.47
V
V
V
V
V
DD
V
OV + 0.3
DD
OH
OH
DD
Output low voltage (OV = Min, I = 1.0 mA)
V
OL
0.50
—
DD
OL
Input high voltage
Input low voltage
V
IH
V
0.90
IL
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
32
Freescale Semiconductor
Ethernet: Three-Speed, MII Management
Table 28. MII Management DC Electrical Characteristics (continued)
Parameter
Symbol
Min
Max
Unit
1
Input high current (OV = Max, V
= 2.1 V)
I
—
40
—
μA
μA
DD
IN
IH
Input low current (OV = Max, V = 0.5 V)
I
–600
DD
IN
IL
Note:
1.Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
7.3.2 MII Management AC Electrical Specifications
Table 29 provides the MII management AC timing specifications.
Table 29. MII Management AC Timing Specifications
At recommended operating conditions with OVDD is 3.3 V 5%.
1
Parameter/Condition
MDC frequency
Symbol
Min
Typ
Max
Unit
Notes
f
t
0.893
96
—
—
—
10.4
1120
—
MHz
ns
2, 4
MDC
MDC period
MDC
MDC clock pulse width high
MDC to MDIO valid
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
t
32
ns
MDCH
t
2*[1/(f
/8)]
/8)]
ns
3
3
MDKHDV
MDKHDX
ccb_clk
t
10
5
—
—
—
—
—
2*[1/(f
ns
ccb_clk
t
—
ns
MDDVKH
MDDXKH
t
0
—
10
10
ns
t
—
—
ns
4
4
MDCR
MDC fall time
t
ns
MDHF
Notes:
1.The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
MDKHDX
symbolizes management data timing (MD) for the time t
from clock reference (K) high (H) until data outputs (D) are
MDC
invalid (X) or data hold time. Also, t
symbolizes management data timing (MD) with respect to the time data
MDDVKH
input signals (D) reach the valid state (V) relative to the t
clock reference (K) going to the high (H) state or setup
MDC
time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the maximum frequency is
8.3 MHz and the minimum frequency is 1.2 MHz; for a CCB clock of 333 MHz, the maximum frequency is 10.4 MHz
and the minimum frequency is 1.5 MHz).
3.This parameter is dependent on the CCB clock speed (that is, for a CCB clock of 267 MHz, the delay is 60 ns and for a
CCB clock of 333 MHz, the delay is 48 ns).
4.Guaranteed by design.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
33
Local Bus
Figure 15 shows the MII management AC timing diagram.
t
t
MDCR
MDC
MDC
t
t
MDCF
MDCH
MDIO
(Input)
t
MDDVKH
t
t
MDDXKH
MDKHDV
MDIO
(Output)
t
MDKHDX
Figure 15. MII Management Interface Timing Diagram
8 Local Bus
This section describes the DC and AC electrical specifications for the local bus interface of the MPC8560.
8.1 Local Bus DC Electrical Characteristics
Table 30 provides the DC electrical characteristics for the local bus interface.
Table 30. Local Bus DC Electrical Characteristics
Parameter
High-level input voltage
Symbol
Min
Max
Unit
V
2
OV + 0.3
V
V
IH
DD
Low-level input voltage
V
I
–0.3
—
0.8
5
IL
1
Input current (V
= 0 V or V = V
)
μA
V
IN
IN
DD
IN
High-level output voltage (OV = min, I = –2 mA)
V
OV - 0.2
—
0.2
DD
OH
OH
DD
Low-level output voltage (OV = min, I = 2 mA)
V
OL
—
V
DD
OL
Note:
1.Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
8.2 Local Bus AC Electrical Specifications
Table 31 describes the general timing parameters of the local bus interface of the MPC8560 with the DLL
enabled.
Table 31. Local Bus General Timing Parameters—DLL Enabled
1
Parameter
POR Configuration
Symbol
Min
Max
Unit
Notes
Local bus cycle time
LCLK[n] skew to LCLK[m] or LSYNC_OUT
—
—
t
6.0
—
—
ns
ps
2
LBK
t
150
3, 9
LBKSKEW
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
34
Freescale Semiconductor
Local Bus
Table 31. Local Bus General Timing Parameters—DLL Enabled (continued)
1
Parameter
POR Configuration
Symbol
Min
Max
Unit
Notes
Input setup to local bus clock (except
LUPWAIT)
—
t
1.8
—
ns
4, 5, 8
LBIVKH1
LUPWAIT input setup to local bus clock
—
—
t
t
1.7
0.5
—
—
ns
ns
4, 5
LBIVKH2
LBIXKH1
Input hold from local bus clock (except
LUPWAIT)
4, 5, 8
LUPWAIT input hold from local bus clock
—
—
t
1.0
1.5
—
—
ns
ns
4, 5
6
LBIXKH2
LALE output transition to LAD/LDP output
transition (LATCH hold time)
t
LBOTOT
Local bus clock to output valid (except
LAD/LDP and LALE)
TSEC2_TXD[6:5] = 00
t
t
t
—
—
—
2.0
3.5
ns
ns
ns
4, 8
4, 8
4, 8
LBKHOV1
LBKHOV2
LBKHOV3
TSEC2_TXD[6:5] = 11
(default)
Local bus clock to data valid for LAD/LDP
Local bus clock to address valid for LAD
Local bus clock to LALE assertion
TSEC2_TXD[6:5] = 00
2.2
3.7
TSEC2_TXD[6:5] = 11
(default)
TSEC2_TXD[6:5] = 00
2.3
3.8
TSEC2_TXD[6:5] = 11
(default)
t
t
—
0.7
1.6
2.3
—
ns
ns
4, 8
4, 8
LBKHOV4
Output hold from local bus clock (except
LAD/LDP and LALE)
TSEC2_TXD[6:5] = 00
LBKHOX1
TSEC2_TXD[6:5] = 11
(default)
Output hold from local bus clock for
LAD/LDP
TSEC2_TXD[6:5] = 00
t
t
0.7
1.6
—
ns
ns
4, 8
7, 9
LBKHOX2
TSEC2_TXD[6:5] = 11
(default)
Local bus clock to output high Impedance
(except LAD/LDP and LALE)
TSEC2_TXD[6:5] = 00
—
2.5
3.8
LBKHOZ1
TSEC2_TXD[6:5] = 11
(default)
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
35
Local Bus
Table 31. Local Bus General Timing Parameters—DLL Enabled (continued)
1
Parameter
POR Configuration
Symbol
Min
Max
Unit
Notes
Local bus clock to output high impedance
for LAD/LDP
TSEC2_TXD[6:5] = 00
t
—
2.5
3.8
ns
7, 9
LBKHOZ2
TSEC2_TXD[6:5] = 11
(default)
Notes:
1.The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes local
(First two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes high (H), in this
LBK
case for clock one(1). Also, t
symbolizes local bus timing (LB) for the t
clock reference (K) to go high (H), with
LBKHOX
LBK
respect to the output (O) going invalid (X) or output hold time.
2.All timings are in reference to LSYNC_IN for DLL enabled mode.
3.Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at OV /2.
DD
4.All signals are measured from OV /2 of the rising edge of LSYNC_IN for DLL enabled to 0.4 × OV of the signal in question
DD
DD
for 3.3-V signaling levels.
5.Input timings are measured at the pin.
6.The value of t is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local
LBOTOT
bus buffer delays used as programmed at power-on reset with configuration pins TSEC2_TXD[6:5].
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
8.Guaranteed by characterization.
9.Guaranteed by design.
Table 32 describes the general timing parameters of the local bus interface of the MPC8560 with the DLL
bypassed.
Table 32. Local Bus General Timing Parameters—DLL Bypassed
1
Parameter
Local bus cycle time
POR Configuration
Symbol
Min
Max
Unit
Notes
—
—
—
—
t
6.0
2.3
—
—
3.9
150
—
ns
ns
ps
ns
2
LBK
Internal launch/capture clock to LCLK delay
LCLK[n] skew to LCLK[m] or LSYNC_OUT
t
8
LBKHKT
t
3, 9
4, 5
LBKSKEW
Input setup to local bus clock (except
LUPWAIT)
t
5.7
LBIVKH1
LUPWAIT input setup to local bus clock
—
—
t
t
5.6
—
—
ns
ns
4, 5
4, 5
LBIVKH2
Input hold from local bus clock (except
LUPWAIT)
-1.8
LBIXKH1
LUPWAIT input hold from local bus clock
—
—
t
-1.3
1.5
—
—
ns
ns
4, 5
6
LBIXKH2
LALE output transition to LAD/LDP output
transition (LATCH hold time)
t
LBOTOT
Local bus clock to output valid (except
LAD/LDP and LALE)
TSEC2_TXD[6:5] = 00
t
—
-0.3
1.2
ns
4
LBKLOV1
TSEC2_TXD[6:5] = 11
(default)
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
36
Freescale Semiconductor
Local Bus
Table 32. Local Bus General Timing Parameters—DLL Bypassed (continued)
1
Parameter
POR Configuration
Symbol
Min
Max
Unit
Notes
Local bus clock to data valid for LAD/LDP
TSEC2_TXD[6:5] = 00
t
t
—
-0.1
1.4
ns
4
LBKLOV2
TSEC2_TXD[6:5] = 11
(default)
Local bus clock to address valid for LAD
TSEC2_TXD[6:5] = 00
—
0
ns
4
LBKLOV3
TSEC2_TXD[6:5] = 11
(default)
1.5
Local bus clock to LALE assertion
t
—
0
ns
ns
4
4
LBKHOV4
Output hold from local bus clock (except
LAD/LDP and LALE)
TSEC2_TXD[6:5] = 00
t
-3.2
-2.3
—
LBKLOX1
LBKLOX2
LBKLOZ1
LBKLOZ2
TSEC2_TXD[6:5] = 11
(default)
Output hold from local bus clock for
LAD/LDP
TSEC2_TXD[6:5] = 00
t
t
t
-3.2
-2.3
—
ns
ns
ns
4
7
7
TSEC2_TXD[6:5] = 11
(default)
Local bus clock to output high Impedance
(except LAD/LDP and LALE)
TSEC2_TXD[6:5] = 00
—
—
0.2
1.5
TSEC2_TXD[6:5] = 11
(default)
Local bus clock to output high impedance
for LAD/LDP
TSEC2_TXD[6:5] = 00
0.2
1.5
TSEC2_TXD[6:5] = 11
(default)
Notes:
1.The symbols used for timing specifications herein follow the pattern of t
(First two letters of functional block)(signal)(state) (reference)(state)
for inputs and t
for outputs. For example, t
symbolizes local
(First two letters of functional block)(reference)(state)(signal)(state)
LBIXKH1
bus timing (LB) for the input (I) to go invalid (X) with respect to the time the t
clock reference (K) goes high (H), in this
LBK
case for clock one(1). Also, t
symbolizes local bus timing (LB) for the t
clock reference (K) to go high (H), with
LBKHOX
LBK
respect to the output (O) going invalid (X) or output hold time.
2.All timings are in reference to local bus clock for DLL bypass mode. Timings may be negative with respect to the local bus
clock because the actual launch and capture of signals is done with the internal launch/capture clock, which precedes
LCLK by t
.
LBKHKT
3.Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between
complementary signals at OV /2.
DD
4.All signals are measured from OV /2 of the rising edge of local bus clock for DLL bypass mode to 0.4 × OV of the signal
DD
DD
in question for 3.3-V signaling levels.
5.Input timings are measured at the pin.
6.The value of t
is defined as the sum of 1/2 or 1 ccb_clk cycle as programmed by LBCR[AHD], and the number of local
LBOTOT
bus buffer delays used as programmed at power-on reset with configuration pins TSEC2_TXD[6:5].
7.For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
8.Guaranteed by characterization.
9.Guaranteed by design.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
37
Local Bus
Figure 16 provides the AC test load for the local bus.
Output
OV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 16. Local Bus AC Test Load
Figure 17 through Figure 22 show the local bus signals.
LSYNC_IN
t
t
LBIXKH1
t
t
t
t
t
LBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
LBIXKH2
LBIVKH2
Input Signal:
LGTA
t
LBKHOZ1
LBKHOX1
t
t
LBKHOV1
LBKHOV2
Output Signals:
LA[27:31]/LBCTL/LBCKE/LOE/
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
t
LBKHOZ2
LBKHOX2
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOZ2
t
LBKHOX2
LBKHOV3
Output (Address) Signal:
LAD[0:31]
t
LBOTOT
t
LBKHOV4
LALE
Figure 17. Local Bus Signals, Nonspecial Signals Only (DLL Enabled)
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
38
Freescale Semiconductor
Local Bus
Internal launch/capture clock
LCLK[n]
t
LBKHKT
t
LBIVKH1
t
LBIXKH1
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBIVKH2
Input Signal:
LGTA
t
LBIXKH2
t
LBKLOV1
t
t
LBKLOZ1
t
LBKLOX1
Output Signals:
LA[27:31]/LBCTL/LBCKE/LOE/
LSDA10/LSDWE/LSDRAS/
LSDCAS/LSDDQM[0:3]
t
LBKLOZ2
LBKLOV2
Output (Data) Signals:
LAD[0:31]/LDP[0:3]
t
t
LBKLOX2
LBKLOV3
Output (Address) Signal:
LAD[0:31]
t
t
LBKLOV4
LBOTOT
LALE
Figure 18. Local Bus Signals (DLL Bypass Mode)
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
39
Local Bus
LSYNC_IN
T1
T3
t
LBKHOZ1
t
LBKHOV1
GPCM Mode Output Signals:
LCS[0:7]/LWE
t
t
LBIXKH2
t
t
LBIVKH2
UPM Mode Input Signal:
LUPWAIT
LBIXKH1
LBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
t
LBKHOZ1
t
LBKHOV1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 19. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Enabled)
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
40
Freescale Semiconductor
Local Bus
t
Internal launch/capture clock
LBKHKT
T1
T3
LCLK
t
t
LBKLOX1
LBKLOV1
GPCM Mode Output Signals:
LCS[0:7]/LWE
t
LBKLOZ1
t
LBIVKH2
t
t
LBIXKH2
UPM Mode Input Signal:
LUPWAIT
t
LBIVKH1
LBIXKH1
Input Signals:
LAD[0:31]/LDP[0:3]
(DLL Bypass Mode)
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 20. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 2 (DLL Bypass Mode)
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
41
Local Bus
LSYNC_IN
T1
T2
T3
T4
t
LBKHOZ1
t
LBKHOV1
GPCM Mode Output Signals:
LCS[0:7]/LWE
t
LBIXKH2
t
LBIVKH2
UPM Mode Input Signal:
LUPWAIT
t
LBIXKH1
t
LBIVKH1
Input Signals:
LAD[0:31]/LDP[0:3]
(DLL Bypass Mode)
t
LBKHOZ1
t
LBKHOV1
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 21. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 or 8 (DLL Enabled)
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
42
Freescale Semiconductor
CPM
t
Internal launch/capture clock
LBKHKT
T1
T2
T3
T4
LCLK
t
t
LBKLOX1
LBKLOV1
GPCM Mode Output Signals:
LCS[0:7]/LWE
t
LBKLOZ1
t
LBIVKH2
t
t
LBIXKH2
UPM Mode Input Signal:
LUPWAIT
t
LBIVKH1
LBIXKH1
Input Signals:
LAD[0:31]/LDP[0:3]
(DLL Bypass Mode)
UPM Mode Output Signals:
LCS[0:7]/LBS[0:3]/LGPL[0:5]
Figure 22. Local Bus Signals, GPCM/UPM Signals for LCCR[CLKDIV] = 4 or 8 (DLL Bypass Mode)
9 CPM
This section describes the DC and AC electrical specifications for the CPM of the MPC8560.
9.1 CPM DC Electrical Characteristics
Table 33 provides the DC electrical characteristics for the MPC8560 CPM.
Table 33. CPM DC Electrical Characteristics
Characteristic
Symbol
Min
Max
Unit
Notes
Input high voltage
Input low voltage
Output high voltage (I = –8.0 mA)
V
2.0
GND
2.4
3.465
0.8
V
V
V
V
1
1, 2
1
IH
V
IL
V
—
OH
OH
Output low voltage (I = 8.0 mA)
V
—
0.5
1
OL
OL
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
43
CPM
Table 33. CPM DC Electrical Characteristics (continued)
Characteristic
Output high voltage (I = –2.0 mA)
Symbol
Min
Max
Unit
Notes
V
V
2.4
—
—
V
V
1
1
OH
OH
Output low voltage (I = 3.2 mA)
OL
0.4
OL
Note:
1. This specification applies to the following pins: PA[0–31], PB[4–31], PC[0–31], and PD[4–31].
2. V (max) for the IIC interface is 0.8 V rather than the 1.5 V specified in the IIC standard
IL
9.2 CPM AC Timing Specifications
Table 34 and Table 35 provide the CPM input and output AC timing specifications, respectively.
NOTE: Rise/Fall Time on CPM Input Pins
It is recommended that the rise/fall time on CPM input pins should not
exceed 5 ns. This should be enforced especially on clock signals. Rise time
refers to signal transitions from 10% to 90% of VCC; fall time refers to
transitions from 90% to 10% of VCC.
1
Table 34. CPM Input AC Timing Specifications
2
3
Characteristic
Symbol
Min
Unit
FCC inputs—internal clock (NMSI) input setup time
FCC inputs—internal clock (NMSI) hold time
FCC inputs—external clock (NMSI) input setup time
FCC inputs—external clock (NMSI) hold time
SCC/SPI inputs—internal clock (NMSI) input setup time
SCC/SPI inputs—internal clock (NMSI) input hold time
SCC/SPI inputs—external clock (NMSI) input setup time
SCC/SPI inputs—external clock (NMSI) input hold time
TDM inputs/SI—input setup time
t
t
6
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
FIIVKH
FIIXKH
t
2.5
2
FEIVKH
t
b
FEIXKH
t
t
6
NIIVKH
NIIXKH
0
t
4
NEIVKH
t
2
NEIXKH
TDIVKH
TDIXKH
t
4
TDM inputs/SI—hold time
t
3
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
44
Freescale Semiconductor
CPM
1
Table 34. CPM Input AC Timing Specifications (continued)
2
3
Characteristic
Symbol
Min
Unit
COL/CRS width high (FCC)
Notes:
t
1.5
CLK
FCCH
1.Input specifications are measured from the 50% level of the signal to the 50% level of the rising edge of
Serial Clock. Timings are measured at the pin.
2.The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional
for inputs and t
for
block)(signal)(state) (reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
outputs. For example, t
symbolizes the FCC inputs internal timing (FI) with respect to the time the
FIIVKH
input signals (I) reaching the valid state (V) relative to the reference clock t
(K) going to the high (H)
FCC
state or setup time. And t
symbolizes the TDM timing (TD) with respect to the time the input
TDIXKH
signals (I) reach the invalid state (X) relative to the reference clock t
or hold time.
(K) going to the high (H) state
FCC
3.PIO and TIMER inputs and outputs are asynchronous to SYSCLK or any other externally visible clock.
PIO/TIMER inputs are internally synchronized to the CPM internal clock. PIO/TIMER outputs should be
treated as asynchronous.
1
Table 35. CPM Output AC Timing Specifications
2
Characteristic
Symbol
Min
Max
Unit
FCC outputs—internal clock (NMSI) delay
FCC outputs—external clock (NMSI) delay
SCC/SPI outputs—internal clock (NMSI) delay
SCC outputs—external clock (NMSI) delay
SPI output—external clock (NMSI) delay
TDM outputs/SI delay
t
1
2
5.5
8
ns
ns
ns
ns
ns
ns
FIKHOX
t
FEKHOX
t
0.5
2
10
8
NIKHOX
NEKHOX
SEKHOX
TDKHOX
t
t
t
2
11
11
2.5
Notes:
1.Output specifications are measured from the 50% level of the rising edge of Serial Clock to the 50% level of the
signal. Timings are measured at the pin.
2.The symbols used for timing specifications follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example,
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
t
symbolizes the FCC inputs internal timing (FI) for the time t
memory clock reference (K) goes from the
FIKHOX
FCC
high state (H) until outputs (O) are invalid (X).
Figure 16 provides the AC test load for the CPM.
OV /2
Output
Z = 50 Ω
DD
0
R = 50 Ω
L
Figure 23. CPM AC Test Load
Figure 24 through Figure 29 represent the AC timing from Table 34 and Table 35. Note that although the
specifications generally reference the rising edge of the clock, these AC timing diagrams also apply when
the falling edge is the active edge.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
45
CPM
Figure 24 shows the FCC internal clock.
BRG_OUT
t
FIIXKH
t
FIIVKH
FCC Input Signals
t
FIKHOX
FCC Output Signals
(When GFMR TCI = 0)
t
FIKHOX
FCC Output Signals
(When GFMR TCI = 1)
Figure 24. FCC Internal AC Timing Clock Diagram
Figure 25 shows the FCC external clock.
Serial Clock In
t
FEIXKH
t
FEIVKH
FCC Input Signals
t
FEKHOX
FCC Output Signals
(When GFMR TCI = 0)
t
FEKHOX
FCC Output Signals
(When GFMR TCI = 1)
Figure 25. FCC External AC Timing Clock Diagram
Figure 26 shows Ethernet collision timing on FCCs.
COL/CRS
(Input)
t
FCCH
Figure 26. Ethernet Collision AC Timing Diagram (FCC)
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
46
Freescale Semiconductor
CPM
Figure 27 shows the SCC/SPI external clock.
Serial Clock In
t
NEIXKH
t
NEIVKH
Input Signals:
SCC/SPI
(See Note)
t
NEKHOX
Output Signals:
SCC
(See Note)
t
SEKHOX
Output Signals:
SPI
(See Note)
Note: The clock edge is selectable on SCC and SPI.
Figure 27. SCC/SPI AC Timing External Clock Diagram
Figure 28 shows the SCC/SPI internal clock.
BRG_OUT
t
NIIXKH
t
NIIVKH
Input Signals:
SCC/SPI
(See Note)
t
NIKHOX
Output Signals:
SCC/SPI
(See Note)
Note: The clock edge is selectable on SCC and SPI.
Figure 28. SCC/SPI AC Timing Internal Clock Diagram
Figure 29 shows TDM input and output signals.
Serial Clock In
t
TDIXKH
t
TDIVKH
TDM Input Signals
t
TDKHOX
TDM Output Signals
Note: There are 4 possible TDM timing conditions:
1. Input sampled on the rising edge and output driven on the rising edge (shown).
2. Input sampled on the rising edge and output driven on the falling edge.
3. Input sampled on the falling edge and output driven on the falling edge.
4. Input sampled on the falling edge and output driven on the rising edge.
Figure 29. TDM Signal AC Timing Diagram
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
47
CPM
2
Table 36 shows CPM I C AC Timing.
2
Table 36. CPM I C AC Timing
Characteristic
Symbol
Min
Max
Unit
1
SCL clock frequency (slave)
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
f
f
0
F
Hz
Hz
s
SCL
SCL
MAX
BRGCLK/16512
BRGCLK/48
t
t
t
t
1/(2.2 * f
1/(2.2 * f
1/(2.2 * f
)
)
)
—
—
—
—
—
—
—
SDHDL
SCLCH
SCHCL
SCHDL
SCL
SCL
SCL
s
High period of SCL
s
2
Start condition setup time
2/(divider * f
3/(divider * f
2/(divider * f
3/(divider * f
—
)
)
)
)
s
SCL
SCL
SCL
SCL
2
Start condition hold time
t
s
SDLCL
SCLDX
SDVCH
2
Data hold time
t
s
2
Data setup time
t
s
SDA/SCL rise time
SDA/SCL fall time
Stop condition setup time
Notes:
t
1/(10 * f
1/(33 * f
—
)
)
s
SRISE
SCL
t
—
s
SFALL
SCL
t
2/(divider * f
)
s
SCHDH
SCL
1.F
= BRGCLK/(min_divider*prescaler). Where prescaler=25-I2MODE[PDIV]; and min_divider=12 if digital filter
MAX
disabled and 18 if enabled.
Example #1: if I2MODE[PDIV]=11 (prescaler=4) and I2MODE[FLT]=0 (digital filter disabled) then
FMAX=BRGCLK/48
Example #2: if I2MODE[PDIV]=00 (prescaler=32) and I2MODE[FLT]=1 (digital filter enabled) then
FMAX=BRGCLK/576
2.divider = f
/prescaler.
SCL
In master mode: divider = BRGCLK/(f
*prescaler) = 2*(I2BRG[DIV]+3)
SCL
In slave mode: divider = BRGCLK/(f
*prescaler)
SCL
2
Figure 30 is a a diagram of CPM I C Bus Timing.
SDA
t
t
SCHCL
t
SCLCH
SDHDL
t
t
SDVCH
t
SCLDX
SCHDL
SCL
t
t
t
t
SCHDH
SDLCL
SRISE
SFALL
2
Figure 30. CPM I C Bus Timing Diagram
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
48
Freescale Semiconductor
CPM
2
2
Table 37 and Table 38 are examples of I C AC parameters at I C clock value of 100 kHz and 400 kHz
respectively.
2
Table 37. CPM I C AC Timing (f
= 100 kHz)
SCL
Characteristic
Symbol
Min
Max
Unit
SCL clock frequency (slave)
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
f
f
—
—
4.7
4.7
4
100
100
—
KHz
KHz
μs
SCL
SCL
t
t
t
t
SDHDL
SCLCH
SCHCL
SCHDL
—
μs
High period of SCL
—
μs
2
Start condition setup time
2
—
μs
2
Start condition hold time
t
t
3
—
μs
SDLCL
2
Data hold time
2
—
μs
SCLDX
SDVCH
2
Data setup time
t
3
—
μs
SDA/SCL rise time
t
—
—
2
1
μs
SRISE
SDA/SCL fall time
t
303
—
ns
SFALL
Stop condition setup time
t
μs
SCHDH
2
Table 38. CPM I C AC Timing (f
= 400 kHz)
SCL
Characteristic
Symbol
Min
Max
Unit
SCL clock frequency (slave)
SCL clock frequency (master)
Bus free time between transmissions
Low period of SCL
f
f
—
—
400
400
—
KHz
KHz
μs
μs
μs
ns
SCL
SCL
t
t
t
t
1.2
1.2
1
SDHDL
SCLCH
SCHCL
SCHDL
—
High period of SCL
—
2
Start condition setup time
420
630
420
630
—
—
2
Start condition hold time
t
—
ns
SDLCL
SCLDX
SDVCH
2
Data hold time
t
—
ns
2
Data setup time
t
—
ns
SDA/SCL rise time
t
250
75
—
ns
SRISE
SDA/SCL fall time
t
—
ns
SFALL
Stop condition setup time
t
420
ns
SCHDH
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
49
JTAG
10 JTAG
This section describes the AC electrical specifications for the IEEE 1149.1 (JTAG) interface of the
MPC8560.
Table 39 provides the JTAG AC timing specifications as defined in Figure 32 through Figure 35.
1
Table 39. JTAG AC Timing Specifications (Independent of SYSCLK)
At recommended operating conditions (see Table 2).
2
Parameter
Symbol
Min
Max
Unit
Notes
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4 V
JTAG external clock rise and fall times
TRST assert time
f
0
33.3
—
MHz
ns
—
—
—
6
JTG
t
30
15
0
JTG
t
—
ns
JTKHKL
t
& t
2
ns
JTGR
JTGF
t
25
—
ns
3
TRST
Input setup times:
ns
t
t
4
0
—
—
4
4
Boundary-scan data
TMS, TDI
JTDVKH
t
JTIVKH
Input hold times:
ns
ns
ns
ns
20
25
—
—
Boundary-scan data
TMS, TDI
JTDXKH
t
JTIXKH
Valid times:
t
t
4
4
20
25
5
Boundary-scan data
TDO
JTKLDV
JTKLOV
Output hold times:
—
t
t
5
Boundary-scan data
TDO
JTKLDX
JTKLOX
JTAG external clock to output high impedance:
t
t
3
3
19
9
5, 6
Boundary-scan data
TDO
JTKLDZ
JTKLOZ
Notes:
1.All outputs are measured from the midpoint voltage of the falling/rising edge of t
to the midpoint of the signal in
TCLK
question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load
(see Figure 31). Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
2.The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example,
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
t
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state
JTDVKH
(V) relative to the t
clock reference (K) going to the high (H) state or setup time. Also, t
symbolizes JTAG
JTG
JTDXKH
timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the t
clock reference (K)
JTG
going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three
letters representing the clock of a particular functional. For rise and fall times, the latter convention is used with
the appropriate letter: R (rise) or F (fall).
3.TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
4.Non-JTAG signal input timing with respect to t
.
TCLK
5.Non-JTAG signal output timing with respect to t
6.Guaranteed by design.
.
TCLK
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
50
Freescale Semiconductor
JTAG
Figure 31 provides the AC test load for TDO and the boundary-scan outputs of the MPC8560.
Z = 50 Ω
OV /2
Output
0
DD
R = 50 Ω
L
Figure 31. AC Test Load for the JTAG Interface
Figure 32 provides the JTAG clock input timing diagram.
JTAG
External Clock
VM
t
VM
VM
t
JTGR
JTKHKL
t
t
JTG
JTGF
VM = Midpoint Voltage (OV /2)
DD
Figure 32. JTAG Clock Input Timing Diagram
Figure 33 provides the TRST timing diagram.
TRST
VM
VM
t
TRST
VM = Midpoint Voltage (OV /2)
DD
Figure 33. TRST Timing Diagram
Figure 34 provides the boundary-scan timing diagram.
JTAG
VM
VM
External Clock
t
JTDVKH
t
JTDXKH
Boundary
Data Inputs
Input
Data Valid
t
JTKLDV
t
JTKLDX
Boundary
Data Outputs
Output Data Valid
t
JTKLDZ
Boundary
Data Outputs
Output Data Valid
VM = Midpoint Voltage (OV /2)
DD
Figure 34. Boundary-Scan Timing Diagram
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
51
I2C
Figure 35 provides the test access port timing diagram.
JTAG
VM
VM
External Clock
t
JTIVKH
t
JTIXKH
Input
TDI, TMS
TDO
Data Valid
t
JTKLOV
t
JTKLOX
Output Data Valid
t
JTKLOZ
TDO
Output Data Valid
VM = Midpoint Voltage (OV /2)
DD
Figure 35. Test Access Port Timing Diagram
11 I2C
2
This section describes the DC and AC electrical characteristics for the I C interface of the MPC8560.
2
11.1 I C DC Electrical Characteristics
Table 40 provides the DC electrical characteristics for the I C interface of the MPC8560.
2
2
Table 40. I C DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V 5%.
Parameter
Input high voltage level
Symbol
Min
Max
Unit
Notes
V
0.7 × OV
OV + 0.3
V
V
—
—
1
IH
DD
DD
Input low voltage level
Low level output voltage
V
–0.3
0
0.3 × OV
IL
DD
V
0.2 × OV
V
OL
DD
Pulse width of spikes which must be suppressed
by the input filter
t
0
50
10
10
ns
2
I2KHKL
Input current each I/O pin (input voltage is
I
–10
—
μA
3
I
between 0.1 × OV and 0.9 × OV (max)
DD
DD
Capacitance for each I/O pin
C
pF
—
I
Notes:
1.Output voltage (open drain or open collector) condition = 3 mA sink current.
2.Refer to the MPC8560 PowerQUICC III Integrated Communications Processor Preliminary Reference Manual for
information on the digital filter used.
3.I/O pins will obstruct the SDA and SCL lines if OV is switched off.
DD
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
52
Freescale Semiconductor
I2C
2
11.2 I C AC Electrical Specifications
2
Table 41 provides the AC timing parameters for the I C interface of the MPC8560.
2
Table 41. I C AC Electrical Specifications
All values refer to VIH (min) and VIL (max) levels (see Table 40).
1
Parameter
Symbol
Min
Max
Unit
SCL clock frequency
f
0
400
—
kHz
μs
I2C
6
6
Low period of the SCL clock
t
t
1.3
0.6
0.6
0.6
I2CL
High period of the SCL clock
—
μs
I2CH
6
6
Setup time for a repeated START condition
t
—
μs
I2SVKH
Hold time (repeated) START condition (after this period, the
first clock pulse is generated)
t
—
μs
I2SXKL
6
Data setup time
t
100
—
ns
I2DVKH
Data hold time:
t
μs
I2DXKL
—
0
—
0.9
CBUS compatible masters
2
3
2
I C bus devices
Set-up time for STOP condition
t
0.6
1.3
—
—
—
μs
μs
V
I2PVKH
Bus free time between a STOP and START condition
t
I2KHDX
Noise margin at the LOW level for each connected device
(including hysteresis)
V
0.1 × OV
NL
DD
DD
Noise margin at the HIGH level for each connected device
(including hysteresis)
V
0.2 × OV
—
V
NH
Notes:
1.The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state)
for inputs and t
for outputs. For example, t
(reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
I2DVKH
2
symbolizes I C timing (I2) with respect to the time data input signals (D) reach the valid state (V) relative to the t
clock reference (K) going to the high (H) state or setup time. Also, t
I2C
2
symbolizes I C timing (I2) for the time that
I2SXKL
the data with respect to the start condition (S) went invalid (X) relative to the t
clock reference (K) going to the low
I2C
2
(L) state or hold time. Also, t
symbolizes I C timing (I2) for the time that the data with respect to the stop
I2PVKH
condition (P) reaching the valid state (V) relative to the t
clock reference (K) going to the high (H) state or setup
I2C
time. For rise and fall times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2.MPC8560 provides a hold time of at least 300 ns for the SDA signal (referred to the V
the undefined region of the falling edge of SCL.
of the SCL signal) to bridge
IHmin
3.The maximum t
has only to be met if the device does not stretch the LOW period (t
) of the SCL signal.
I2DVKH
I2CL
4.C = capacitance of one bus line in pF.
B
6.Guaranteed by design.
2
Figure 16 provides the AC test load for the I C.
Output
OV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
2
Figure 36. I C AC Test Load
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
53
PCI/PCI-X
2
Figure 37 shows the AC timing diagram for the I C bus.
SDA
t
t
t
t
I2CF
I2CF
I2DVKH
I2KHKL
t
t
t
I2CR
I2CL
I2SXKL
SCL
t
t
t
t
I2PVKH
I2SXKL
I2CH
I2SVKH
t
I2DXKL
S
Sr
P
S
2
Figure 37. I C Bus AC Timing Diagram
12 PCI/PCI-X
This section describes the DC and AC electrical specifications for the PCI/PCI-X bus of the MPC8560.
12.1 PCI/PCI-X DC Electrical Characteristics
Table 42 provides the DC electrical characteristics for the PCI/PCI-X interface of the MPC8560.
1
Table 42. PCI/PCI-X DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
Low-level input voltage
V
2
OV + 0.3
V
V
IH
DD
V
I
–0.3
—
0.8
5
IL
Input current
μA
IN
2
(V
= 0 V or V = V
)
DD
IN
IN
High-level output voltage
(OV = min, I = –100 μA)
V
OV – 0.2
—
V
V
OH
DD
DD
OH
Low-level output voltage
V
—
0.2
OL
(OV = min, I = 100 μA)
DD
OL
Notes:
1.Ranges listed do not meet the full range of the DC specifications of the PCI 2.2 Local Bus Specifications.
2.Note that the symbol V , in this case, represents the OV symbol referenced in Table 1 and Table 2.
IN
IN
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
54
Freescale Semiconductor
PCI/PCI-X
12.2 PCI/PCI-X AC Electrical Specifications
This section describes the general AC timing parameters of the PCI/PCI-X bus of the MPC8560. Note that
the SYSCLK signal is used as the PCI input clock. Table 43 provides the PCI AC timing specifications at
66 MHz.
Table 43. PCI AC Timing Specifications at 66 MHz
1
Parameter
SYSCLK to output valid
Symbol
Min
Max
Unit
Notes
t
—
2.0
6.0
—
14
—
—
—
50
—
ns
ns
2
PCKHOV
Output hold from SYSCLK
SYSCLK to output high impedance
Input setup to SYSCLK
t
2, 9
PCKHOX
PCKHOZ
t
—
ns
2, 3, 10
2, 4, 9
2, 4, 9
5, 6, 10
6, 10
t
3.0
ns
PCIVKH
PCIXKH
PCRVRH
PCRHRX
Input hold from SYSCLK
t
0
ns
9
REQ64 to HRESET setup time
t
t
10 × t
clocks
ns
SYS
HRESET to REQ64 hold time
HRESET high to first FRAME assertion
Notes:
0
t
10
clocks
7, 10
PCRHFV
1.Note that the symbols used for timing specifications herein follow the pattern of t
(first two letters of functional
for inputs and t
for outputs.
block)(signal)(state) (reference)(state)
(first two letters of functional block)(reference)(state)(signal)(state)
For example, t
symbolizes PCI/PCI-X timing (PC) with respect to the time the input signals (I) reach the
PCIVKH
valid state (V) relative to the SYSCLK clock, t
, reference (K) going to the high (H) state or setup time. Also,
SYS
t
symbolizes PCI/PCI-X timing (PC) with respect to the time hard reset (R) went high (H) relative to the
PCRHFV
frame signal (F) going to the valid (V) state.
2.See the timing measurement conditions in the PCI 2.2 Local Bus Specifications.
3.For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
4.Input timings are measured at the pin.
5.The timing parameter t
indicates the minimum and maximum CLK cycle times for the various specified
SYS
frequencies. The system clock period must be kept within the minimum and maximum defined ranges. For values
see Section 15, “Clocking.”
6.The setup and hold time is with respect to the rising edge of HRESET.
7.The timing parameter t
Bus Specifications.
is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI 2.2 Local
PCRHFV
8.The reset assertion timing requirement for HRESET is 100 μs.
9.Guaranteed by characterization.
10.Guaranteed by design.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
55
PCI/PCI-X
Figure 16 provides the AC test load for PCI and PCI-X.
Output
OV /2
DD
Z = 50 Ω
0
R = 50 Ω
L
Figure 38. PCI/PCI-X AC Test Load
Figure 39 shows the PCI/PCI-X input AC timing conditions.
CLK
t
PCIVKH
t
PCIXKH
Input
Figure 39. PCI-PCI-X Input AC Timing Measurement Conditions
Figure 40 shows the PCI/PCI-X output AC timing conditions.
CLK
t
PCKHOV
Output Delay
t
PCKHOZ
High-Impedance
Output
Figure 40. PCI-PCI-X Output AC Timing Measurement Condition
Table 44 provides the PCI-X AC timing specifications at 66 MHz.
Table 44. PCI-X AC Timing Specifications at 66 MHz
Parameter
SYSCLK to signal valid delay
Symbol
Min
Max
Unit
Notes
t
—
3.8
ns
1, 2, 3,
7, 8
PCKHOV
Output hold from SYSCLK
t
0.7
—
—
7
ns
ns
1, 10
1, 4, 8, 11
3, 5
PCKHOX
PCKHOZ
SYSCLK to output high impedance
Input setup time to SYSCLK
t
t
1.7
0.5
10
0
—
—
—
50
—
ns
PCIVKH
Input hold time from SYSCLK
REQ64 to HRESET setup time
HRESET to REQ64 hold time
HRESET high to first FRAME assertion
t
ns
10
PCIXKH
PCRVRH
PCRHRX
t
t
clocks
ns
11
11
t
10
clocks
9, 11
PCRHFV
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
56
Freescale Semiconductor
PCI/PCI-X
Notes
Table 44. PCI-X AC Timing Specifications at 66 MHz (continued)
Parameter
Symbol
Min
Max
Unit
PCI-X initialization pattern to HRESET setup time
HRESET to PCI-X initialization pattern hold time
Notes:
t
10
0
—
clocks
ns
11
PCIVRH
t
50
6, 11
PCRHIX
1.See the timing measurement conditions in the PCI-X 1.0a Specification.
2.Minimum times are measured at the package pin (not the test point). Maximum times are measured with the test point and
load circuit.
3.Setup time for point-to-point signals applies to REQ and GNT only. All other signals are bused.
4.For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
5.Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same time.
6.Maximum value is also limited by delay to the first transaction (time for HRESET high to first configuration access, t
).
PCRHFV
The PCI-X initialization pattern control signals after the rising edge of HRESET must be negated no later than two clocks
before the first FRAME and must be floated no later than one clock before FRAME is asserted.
7.A PCI-X device is permitted to have the minimum values shown for t
and t
only in PCI-X mode. In conventional
CYC
PCKHOV
mode, the device must meet the requirements specified in PCI 2.2 for the appropriate clock frequency.
8.Device must meet this specification independent of how many outputs switch simultaneously.
9.The timing parameter t
is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI-X 1.0a Specification.
PCRHFV
10.Guaranteed by characterization.
11.Guaranteed by design.
Table 45 provides the PCI-X AC timing specifications at 133 MHz.
Table 45. PCI-X AC Timing Specifications at 133 MHz
Parameter
SYSCLK to signal valid delay
Symbol
Min
Max
Unit
Notes
t
—
3.8
ns
1, 2, 3,
7, 8
PCKHOV
Output hold from SYSCLK
t
0.7
—
—
7
ns
ns
1, 11
PCKHOX
PCKHOZ
SYSCLK to output high impedance
t
1, 4, 8,
12
Input setup time to SYSCLK
t
1.4
—
ns
3, 5, 9,
11
PCIVKH
Input hold time from SYSCLK
t
0.5
10
0
—
—
50
—
—
ns
11
12
PCIXKH
PCRVRH
PCRHRX
REQ64 to HRESET setup time
t
clocks
ns
HRESET to REQ64 hold time
t
12
HRESET high to first FRAME assertion
PCI-X initialization pattern to HRESET setup time
t
10
10
clocks
clocks
10, 12
12
PCRHFV
PCIVRH
t
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
57
RapidIO
Table 45. PCI-X AC Timing Specifications at 133 MHz (continued)
Parameter
Symbol
Min
Max
Unit
Notes
HRESET to PCI-X initialization pattern hold time
t
0
50
ns
6, 12
PCRHIX
Notes:
1.See the timing measurement conditions in the PCI-X 1.0a Specification.
2.Minimum times are measured at the package pin (not the test point). Maximum times are measured with the test
point and load circuit.
3.Setup time for point-to-point signals applies to REQ and GNT only. All other signals are bused.
4.For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current
delivered through the component pin is less than or equal to the leakage current specification.
5.Setup time applies only when the device is not driving the pin. Devices cannot drive and receive signals at the same
time.
6.Maximum value is also limited by delay to the first transaction (time for HRESET high to first configuration access,
t
). The PCI-X initialization pattern control signals after the rising edge of HRESET must be negated no
PCRHFV
later than two clocks before the first FRAME and must be floated no later than one clock before FRAME is
asserted.
7.A PCI-X device is permitted to have the minimum values shown for t
PCKHOV
and t
only in PCI-X mode. In
CYC
conventional mode, the device must meet the requirements specified in PCI 2.2 for the appropriate clock
frequency.
8.Device must meet this specification independent of how many outputs switch simultaneously.
9.The timing parameter t
Specification.
is a minimum of 1.4 ns rather than the minimum of 1.2 ns in the PCI-X 1.0a
PCIVKH
10.The timing parameter t
Specification.
is a minimum of 10 clocks rather than the minimum of 5 clocks in the PCI-X 1.0a
PCRHFV
11.Guaranteed by characterization.
12.Guaranteed by design.
13 RapidIO
This section describes the DC and AC electrical specifications for the RapidIO interface of the MPC8560.
13.1 RapidIO DC Electrical Characteristics
RapidIO driver and receiver DC electrical characteristics are provided in Table 46 and Table 47,
respectively.
Table 46. RapidIO 8/16 LP-LVDS Driver DC Electrical Characteristics
At recommended operating conditions with OVDD of 3.3 V 5%.
Characteristic
Symbol
Min
Max
Unit
Notes
Differential output high voltage
Differential output low voltage
Differential offset voltage
V
247
–454
—
454
–247
50
mV
mV
mV
V
1, 2
1, 2
1,3
OHD
V
OLD
ΔV
OSD
Output high common mode voltage
Output low common mode voltage
V
1.125
1.125
1.375
1.375
1, 4
1, 5
OHCM
V
V
OLCM
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
58
Freescale Semiconductor
RapidIO
Table 46. RapidIO 8/16 LP-LVDS Driver DC Electrical Characteristics (continued)
At recommended operating conditions with OVDD of 3.3 V 5%.
Characteristic
Symbol
Min
Max
Unit
Notes
Common mode offset voltage
Differential termination
ΔV
—
90
—
—
50
220
24
mV
W
1, 6
—
7
OSCM
R
TERM
Short circuit current (either output)
Bridged short circuit current
|I
|
|
mA
mA
SS
|I
12
8
SB
Notes:
1.Bridged 100-Ω load.
2.See Figure 41(a).
3.Differential offset voltage = |V
+V
|. See Figure 41(b).
OHD
OLD
4.V
5.V
= (V + V )/2 when measuring V
.
OHCM
OA
OB
OHD
= (V + V )/2 when measuring V .
OLD
OLCM
OA
OB
6.Common mode offset ΔV
= |V
– V |. See Figure 41(c).
OLCM
OSCM
OHCM
7.Outputs shorted to V or GND.
DD
8.Outputs shorted together.
Table 47. RapidIO 8/16 LP-LVDS Receiver DC Electrical Characteristics
Characteristic
Voltage at either input
Symbol
Min
Max
Unit
Notes
V
0
2.4
600
V
mV
mV
V
—
1
I
Differential input high voltage
Differential input low voltage
V
100
IHD
V
–600
0.050
–100
2.350
1
ILD
Common mode input range (referenced to receiver
ground)
V
2
ICM
Input differential resistance
R
90
110
W
—
IN
Notes:
1.Over the common mode range.
2.Limited by V . See Figure 48.
I
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
59
RapidIO
Figure 41 shows the DC driver signal levels.
V
OA
R
TERM
100 Ω
(no m)
V
V
= V – V
OD OA OB
V
(a)
OB
V
= V – V
V
= (V + V )/2
OD
OA
OB
OSCM OA OB
ΔV
OS
454 mV
247 mV
1.375 V
1.125 V
V
OHCM
V
V
V
OHD
V
OLCM
–247 mV
–454 mV
–V + ΔV
–V – ΔV
OD
–V
0
OLD
OD
Differential Specifications
Common-Mode Specifications
(b)
(c)
Note: V refers to voltage at output A; V refers to voltage at output B.
OA
OB
Figure 41. DC Driver Signal Levels
13.2 RapidIO AC Electrical Specifications
This section contains the AC electrical specifications for a RapidIO 8/16 LP-LVDS device. The interface
defined is a parallel differential low-power high-speed signal interface. Note that the source of the transmit
clock on the RapidIO interface is dependent on the settings of the LGPL[0:1] signals at reset. Note that the
default setting makes the core complex bus (CCB) clock the source of the transmit clock. See Chapter 4
of the Reference Manual for more details on reset configuration settings.
13.3 RapidIO Concepts and Definitions
This section specifies signals using differential voltages. Figure 42 shows how the signals are defined. The
figure shows waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD). Each
signal swings between A volts and B volts where A > B. Using these waveforms, the definitions are as
follows:
•
The transmitter output and receiver input signals TD, TD, RD, and RD each have a peak-to-peak
swing of A-B volts.
•
•
•
The differential output signal of the transmitter, V , is defined as V – V
.
OD
TD
TD
The differential input signal of the receiver, V , is defined as V – V .
RD
ID
RD
The differential output signal of the transmitter or input signal of the receiver, ranges from
A – B volts to – (A – B) volts.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
60
Freescale Semiconductor
RapidIO
•
•
The peak differential signal of the transmitter output or receiver input, is A – B volts.
The peak-to-peak differential signal of the transmitter output or receiver input, is 2 × (A – B) volts.
TD or RD
A V
TD or RD
B V
Figure 42. Differential Peak-to-Peak Voltage of Transmitter or Receiver
To illustrate these definitions using numerical values, consider the case where a LVDS transmitter has a
common mode voltage of 1.2 V and each signal has a swing that goes between 1.4 and 1.0 V. Using these
values, the peak-to-peak voltage swing of the signals TD, TD, RD, and RD is 400 mV. The differential
signal ranges between 400 and –400 mV. The peak differential signal is 400 mV, and the peak-to-peak
differential signal is 800 mV.
A timing edge is the zero-crossing of a differential signal. Each skew timing parameter on a parallel bus
is synchronously measured on two signals relative to each other in the same cycle, such as data to data,
data to clock, or clock to clock. A skew timing parameter may be relative to the edge of a signal or to the
middle of two sequential edges.
Static skew represents the timing difference between signals that does not vary over time regardless of
system activity or data pattern. Path length differences are a primary source of static skew.
Dynamic skew represents the amount of timing difference between signals that is dependent on the activity
of other signals and varies over time. Crosstalk between signals is a source of dynamic skew.
Eye diagrams and compliance masks are a useful way to visualize and specify driver and receiver
performance. This technique is used in several serial bus specifications. An example compliance mask is
shown in Figure 43. The key difference in the application of this technique for a parallel bus is that the data
is source synchronous to its bus clock while serial data is referenced to its embedded clock. Eye diagrams
reveal the quality (cleanness, openness, goodness) of a driver output or receiver input. An advantage of
using an eye diagram and a compliance mask is that it allows specifying the quality of a signal without
requiring separate specifications for effects such as rise time, duty cycle distortion, data dependent
dynamic skew, random dynamic skew, etc. This allows the individual semiconductor manufacturer
maximum flexibility to trade off various performance criteria while keeping the system performance
constant.
In using the eye pattern and compliance mask approach, the quality of the signal is specified by the
compliance mask. The mask specifies the maximum permissible magnitude of the signal and the minimum
permissible eye opening. The eye diagram for the signal under test is generated according to the
specification. Compliance is determined by whether the compliance mask can be positioned over the eye
diagram such that the eye pattern falls entirely within the unshaded portion of the mask.
Serial specifications have clock encoded with the data, but the LP-LVDS physical layer defined by
RapidIO is a source synchronous parallel port so additional specifications to include effects that are not
found in serial links are required. Specifications for the effect of bit to bit timing differences caused by
static skew have been added and the eye diagrams specified are measured relative to the associated clock
in order to include clock to data effects. With the transmit output (or receiver input) eye diagram, the user
can determine if the transmitter output (or receiver input) is compliant with an oscilloscope with the
appropriate software.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
61
RapidIO
Z
Y
0
–Y
–Z
DV
0
X1 X2
1–X2 1–X1
1
Time (UI)
Figure 43. Example Compliance Mask
Y = minimum data valid amplitude
Z = maximum amplitude
1 UI = 1 unit interval = 1/baud rate
X1 = end of zero crossing region
X2 = beginning of data valid window
DV = data valid window = 1 – 2 × X2
The waveform of the signal under test must fall within the unshaded area of the mask to be compliant.
Different masks are used for the driver output and the receiver input allowing each to be separately
specified.
13.3.1 RapidIO Driver AC Timing Specifications
Driver AC timing specifications are provided in Table 48, Table 49, and Table 50. A driver shall comply
with the specifications for each data rate/frequency for which operation of the driver is specified. Unless
otherwise specified, these specifications are subject to the following conditions.
•
The specifications apply over the supply voltage and ambient temperature ranges specified by the
device vendor.
•
•
•
•
The specifications apply for any combination of data patterns on the data signals.
The output of a driver shall be connected to a 100 Ω, ±1%, differential (bridged) resistive load.
Clock specifications apply only to clock signals.
Data specifications apply only to data signals (FRAME, D[0:7]).
Table 48. RapidIO Driver AC Timing Specifications—500 Mbps Data Rate
Range
Characteristic
Symbol
Unit
Notes
Min
Max
Differential output high voltage
Differential output low voltage
V
200
540
mV
mV
1
1
OHD
V
–540
–200
OLD
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
62
Freescale Semiconductor
RapidIO
Table 48. RapidIO Driver AC Timing Specifications—500 Mbps Data Rate (continued)
Range
Characteristic
Symbol
Unit
Notes
Min
Max
Duty cycle
rise time, 20%–80% of peak-to-peak
DC
48
52
—
%
2, 6
3, 6
V
t
t
200
ps
OD
FALL
differential signal swing
V
fall time, 20%–80% of peak-to-peak
200
—
ps
6
OD
RISE
differential signal swing
Data valid
DV
1260
—
—
ps
ps
ps
Skew of any two data outputs
Skew of single data outputs to associated clock
t
180
180
4, 6
5, 6
DPAIR
SKEW,PAIR
t
–180
Notes:
1.See Figure 44.
2.Requires 100 ppm long term frequency stability.
3.Measured at V = 0 V.
OD
4.Measured using the RapidIO transmit mask shown in Figure 44.
5.See Figure 49.
6.Guaranteed by design.
Table 49. RapidIO Driver AC Timing Specifications—750 Mbps Data Rate
Range
Characteristic
Symbol
Unit
Notes
Min
Max
Differential output high voltage
Differential output low voltage
Duty cycle
V
200
–540
48
540
–200
52
mV
mV
%
1
OHD
V
1
OLD
DC
2, 6
3, 6
V
rise time, 20%–80% of peak-to-peak
t
t
133
—
ps
OD
FALL
differential signal swing
V
fall time, 20%–80% of peak-to-peak
133
—
ps
6
OD
RISE
differential signal swing
Data valid
DV
800
—
—
ps
ps
ps
6
Skew of any two data outputs
Skew of single data outputs to associated clock
t
133
133
4, 6
5, 6
DPAIR
SKEW,PAIR
t
–133
Notes:
1.See Figure 44.
2.Requires 100 ppm long term frequency stability.
3.Measured at V = 0 V.
OD
4.Measured using the RapidIO transmit mask shown in Figure 44.
5.See Figure 49.
6.Guaranteed by design.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
63
RapidIO
Table 50. RapidIO Driver AC Timing Specifications—1 Gbps Data Rate
Range
Characteristic
Symbol
Unit
Notes
Min
Max
Differential output high voltage
Differential output low voltage
Duty cycle
V
200
–540
48
540
–200
52
mV
mV
%
1
OHD
V
1
OLD
DC
2, 6
3, 6
V
rise time, 20%–80% of peak to peak
t
t
100
—
ps
OD
FALL
differential signal swing
V
fall time, 20%–80% of peak to peak
100
—
ps
6
OD
RISE
differential signal swing
Data valid
DV
575
—
—
ps
ps
ps
6
Skew of any two data outputs
Skew of single data outputs to associated clock
t
100
100
4, 6
5, 6
DPAIR
SKEW,PAIR
t
–100
Notes:
1.See Figure 44.
2.Requires 100 ppm long term frequency stability.
3.Measured at V = 0 V.
OD
4.Measured using the RapidIO transmit mask shown in Figure 44.
5.See Figure 49.
6.Guaranteed by design.
The compliance of driver output signals TD[0:15] and TFRAME with their minimum data valid window
(DV) specification shall be determined by generating an eye pattern for each of the data signals and
comparing the eye pattern of each data signal with the RapidIO transmit mask shown in Figure 44. The
value of X2 used to construct the mask shall be (1 – DV )/2. A signal is compliant with the data valid
min
window specification if the transmit mask can be positioned on the signal’s eye pattern such that the eye
pattern falls entirely within the unshaded portion of the mask.
V
OHDmax
V
OHDmin
0
V
OLDmax
DV
V
OLDmin
0
X2
1–X2
1
Time (UI)
Figure 44. RapidIO Transmit Mask
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
64
Freescale Semiconductor
RapidIO
The eye pattern for a data signal is generated by making a large number of recordings of the signal and
then overlaying the recordings. The number of recordings used to generate the eye shall be large enough
that further increasing the number of recordings used does not cause the resulting eye pattern to change
from one that complies with the RapidIO transmit mask to one that does not. Each data signal in the
interface shall be carrying random or pseudo-random data when the recordings are made. If
pseudo-random data is used, the length of the pseudo-random sequence (repeat length) shall be long
enough that increasing the length of the sequence does not cause the resulting eye pattern to change from
one that complies with the RapidIO transmit mask to one that does not comply with the mask. The data
carried by any given data signal in the interface may not be correlated with the data carried by any other
data signal in the interface. The zero-crossings of the clock associated with a data signal shall be used as
the timing reference for aligning the multiple recordings of the data signal when the recordings are
overlaid.
While the method used to make the recordings and overlay them to form the eye pattern is not specified,
the method used shall be demonstrably equivalent to the following method. The signal under test is
repeatedly recorded with a digital oscilloscope in infinite persistence mode. Each recording is triggered by
a zero-crossing of the clock associated with the data signal under test. Roughly half of the recordings are
triggered by positive-going clock zero-crossings and roughly half are triggered by negative-going clock
zero-crossings. Each recording is at least 1.9 UI in length (to ensure that at least one complete eye is
formed) and begins 0.5 UI before the trigger point (0.5 UI before the associated clock zero-crossing).
Depending on the length of the individual recordings used to generate the eye pattern, one or more
complete eyes will be formed. Regardless of the number of eyes, the eye whose center is immediately to
the right of the trigger point is the eye used for compliance testing.
An example of an eye pattern generated using the above method with recordings 3 UI in length is shown
in Figure 45. In this example, there is no skew between the signal under test and the associated clock used
to trigger the recordings. If skew was present, the eye pattern would be shifted to the left or right relative
to the oscilloscope trigger point.
.
0.5 UI
1.0 UI
1.0 UI
+
0
–
Oscilloscope
(Recording)
Trigger Point
Eye Used for
Compliance
Testing
Eye Pattern
Figure 45. Example Driver Output Eye Pattern
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
65
RapidIO
13.3.2 RapidIO Receiver AC Timing Specifications
The RapidIO receiver AC timing specifications are provided in Table 51. A receiver shall comply with the
specifications for each data rate/frequency for which operation of the receiver is specified. Unless
otherwise specified, these specifications are subject to the following conditions.
•
The specifications apply over the supply voltage and ambient temperature ranges specified by the
device vendor.
•
•
•
•
The specifications apply for any combination of data patterns on the data signals.
The specifications apply over the receiver common mode and differential input voltage ranges.
Clock specifications apply only to clock signals.
Data specifications apply only to data signals (FRAME, D[0:7])
Table 51. RapidIO Receiver AC Timing Specifications—500 Mbps Data Rate
Range
Characteristic
Symbol
Unit
Notes
Min
Max
Duty cycle of the clock input
Data valid
DC
DV
47
1080
—
53
%
ps
ps
1, 5
2
Allowable static skew between any two data inputs
within a 8-/9-bit group
t
380
300
3
DPAIR
Allowable static skew of data inputs to associated clock
t
–300
ps
4
SKEW,PAIR
Notes:
1.Measured at V = 0 V.
ID
2.Measured using the RapidIO receive mask shown in Figure 46.
3.See Figure 49.
4.See Figure 48 and Figure 49.
5.Guaranteed by design.
Table 52. RapidIO Receiver AC Timing Specifications—750 Mbps Data Rate
Range
Characteristic
Symbol
Unit
Notes
Min
Max
Duty cycle of the clock input
DC
DV
47
600
—
53
—
%
ps
ps
1, 5
2
Data valid
Allowable static skew between any two data inputs
within a 8-/9-bit group
t
400
3
DPAIR
Allowable static skew of data inputs to associated clock
t
–267
267
ps
4
SKEW,PAIR
Notes:
1.Measured at V = 0 V.
ID
2.Measured using the RapidIO receive mask shown in Figure 46.
3.See Figure 49.
4.See Figure 48 and Figure 49.
5.Guaranteed by design.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
66
Freescale Semiconductor
RapidIO
Table 53. RapidIO Receiver AC Timing Specifications—1 Gbps Data Rate
Range
Characteristic
Symbol
Unit
Notes
Min
Max
Duty cycle of the clock input
DC
DV
47
425
—
53
—
%
ps
ps
1, 5
2
Data valid
Allowable static skew between any two data inputs
within a 8-/9-bit group
t
300
3
DPAIR
Allowable static skew of data inputs to associated clock
t
–200
200
ps
4
SKEW,PAIR
Notes:
1.Measured at V = 0 V.
ID
2.Measured using the RapidIO receive mask shown in Figure 46.
3.See Figure 49.
4.See Figure 48 and Figure 49.
5.Guaranteed by design.
The compliance of receiver input signals RD[0:15] and RFRAME with their minimum data valid window
(DV) specification shall be determined by generating an eye pattern for each of the data signals and
comparing the eye pattern of each data signal with the RapidIO receive mask shown in Figure 46. The
value of X2 used to construct the mask shall be (1 – DV )/2. The ±100 mV minimum data valid and
min
±600 mV maximum input voltage values are from the DC specification. A signal is compliant with the data
valid window specification if and only if the receive mask can be positioned on the signal’s eye pattern
such that the eye pattern falls entirely within the unshaded portion of the mask.
600
100
0
–100
DV
–600
0
X2
1–X2
1
Time (UI)
Figure 46. RapidIO Receive Mask
The eye pattern for a data signal is generated by making a large number of recordings of the signal and
then overlaying the recordings. The number of recordings used to generate the eye shall be large enough
that further increasing the number of recordings used does not cause the resulting eye pattern to change
from one that complies with the RapidIO receive mask to one that does not. Each data signal in the
interface shall be carrying random or pseudo-random data when the recordings are made. If
pseudo-random data is used, the length of the pseudo-random sequence (repeat length) shall be long
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
67
RapidIO
enough that increasing the length of the sequence does not cause the resulting eye pattern to change from
one that complies with the RapidIO receive mask to one that does not comply with the mask. The data
carried by any given data signal in the interface may not be correlated with the data carried by any other
data signal in the interface. The zero-crossings of the clock associated with a data signal shall be used as
the timing reference for aligning the multiple recordings of the data signal when the recordings are
overlaid.
While the method used to make the recordings and overlay them to form the eye pattern is not specified,
the method used shall be demonstrably equivalent to the following method. The signal under test is
repeatedly recorded with a digital oscilloscope in infinite persistence mode. Each recording is triggered by
a zero-crossing of the clock associated with the data signal under test. Roughly half of the recordings are
triggered by positive-going clock zero-crossings and roughly half are triggered by negative-going clock
zero-crossings. Each recording is at least 1.9 UI in length (to ensure that at least one complete eye is
formed) and begins 0.5 UI before the trigger point (0.5 UI before the associated clock zero-crossing).
Depending on the length of the individual recordings used to generate the eye pattern, one or more
complete eyes will be formed. Regardless of the number of eyes, the eye whose center is immediately to
the right of the trigger point is the eye used for compliance testing.
An example of an eye pattern generated using the above method with recordings 3 UI in length is shown
in Figure 47. In this example, there is no skew between the signal under test and the associated clock used
to trigger the recordings. If skew was present, the eye pattern would be shifted to the left or right relative
to the oscilloscope trigger point.
0.5 UI
1.0 UI
1.0 UI
+
0
–
Oscilloscope
(Recording)
Trigger Point
Eye Used for
Compliance
Testing
Eye Pattern
Figure 47. Example Receiver Input Eye Pattern
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
68
Freescale Semiconductor
RapidIO
Figure 48 shows the definitions of the data to clock static skew parameter t
and the data valid
SKEW,PAIR
window parameter DV. The data and frame bits are those that are associated with the clock. The figure
applies for all zero-crossings of the clock. All of the signals are differential signals. V represents V for
D
OD
the transmitter and V for the receiver. The center of the eye is defined as the midpoint of the region in
ID
which the magnitude of the signal voltage is greater than or equal to the minimum DV voltage.
V
V
Clock x
Clock x
V
V
= 0 V
= 0 V
D
D
D
D
1.0 UI Nominal
0.5 UI
t
SKEW,PAIR
0.5 DV
Eye Opening
DV
Figure 48. Data to Clock Skew
0.5 DV
V
HDmim
D[0:7]/D[8:15], FRAME
V
HDmim
Figure 49 shows the definition of the data to data static skew parameter t
parameters are applied.
and how the skew
DPAIR
1.0 UI Nominal
0.5 UI
Center Point for Clock
CLK0 (CLK1)
Center point of the
data valid window of
the earliest allowed data
bit for data grouped
late with respect
to clock
Center point of the
data valid window of
the latest allowed data
bit for data grouped
late with respect
to clock
D[0:7]/D[8:15], FRAME
t
DPAIR
t
SKEW,PAIR
Figure 49. Static Skew Diagram
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
69
Package and Pin Listings
14 Package and Pin Listings
This section details package parameters, pin assignments, and dimensions.
14.1 Package Parameters for the MPC8560 FC-PBGA
The package parameters are as provided in the following list. The package type is 29 mm × 29 mm, 783
flip chip plastic ball grid array (FC-PBGA).
Die size
12.2 mm × 9.5 mm
29 mm × 29 mm
783
Package outline
Interconnects
Pitch
1 mm
Minimum module height
Maximum module height
Solder Balls
3.07 mm
3.75 mm
62 Sn/36 Pb/2 Ag
0.5 mm
Ball diameter (typical)
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
70
Freescale Semiconductor
Package and Pin Listings
14.2 Mechanical Dimensions of the MPC8560 FC-PBGA
Figure 50 the mechanical dimensions and bottom surface nomenclature of the MPC8560, 783 FC-PBGA
package.
Figure 50. Mechanical Dimensions and Bottom Surface Nomenclature of the MPC8560 FC-PBGA
NOTES
1. All dimensions are in millimeters.
2. Dimensions and tolerances per ASME Y14.5M-1994.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
71
Package and Pin Listings
3. Maximum solder ball diameter measured parallel to datum A.
4. Datum A, the seating plane, is defined by the spherical crowns of the solder balls.
5. Capacitors may not be present on all devices.
6. Caution must be taken not to short capacitors or exposed metal capacitor pads on package top.
7. The socket lid must always be oriented to A1.
14.3 Pinout Listings
Table 54 provides the pin-out listing for the MPC8560, 783 FC-PBGA package.
Table 54. MPC8560 Pinout Listing
Power
Supply
Signal
Package Pin Number
PCI/PCI-X
Pin Type
Notes
PCI_AD[63:0]
AA14, AB14, AC14, AD14, AE14, AF14, AG14, AH14,
V15, W15, Y15, AA15, AB15, AC15, AD15, AG15,
AH15, V16, W16, AB16, AC16, AD16, AE16, AF16,
V17, W17, Y17, AA17, AB17, AE17, AF17, AF18, AH6,
AD7, AE7, AH7, AB8, AC8, AF8, AG8, AD9, AE9, AF9,
AG9, AH9, W10, Y10, AA10, AE11, AF11, AG11,
AH11, V12, W12, Y12, AB12, AD12, AE12, AG12,
AH12, V13, Y13, AB13, AC13
I/O
OV
17
DD
PCI_C_BE[7:0]
PCI_PAR
AG13, AH13, V14, W14, AH8, AB10, AD11, AC12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
17
—
—
2
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
AA11
PCI_PAR64
PCI_FRAME
PCI_TRDY
Y14
AC10
AG10
2
PCI_IRDY
AD10
2
PCI_STOP
PCI_DEVSEL
PCI_IDSEL
PCI_REQ64
PCI_ACK64
PCI_PERR
PCI_SERR
PCI_REQ0
PCI_REQ[1:4]
PCI_GNT[0]
PCI_GNT[1:4]
V11
2
AH10
2
AA9
—
5, 10
2
AE13
I/O
I/O
I/O
I/O
I/O
I
AD13
W11
2
Y11
AF5
2, 4
—
—
—
5, 9
AF3, AE4, AG4, AE5
AE6
I/O
O
AG5, AH5, AF6, AG6
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
72
Freescale Semiconductor
Package and Pin Listings
Table 54. MPC8560 Pinout Listing (continued)
Package Pin Number
Power
Notes
Signal
Pin Type
Supply
DDR SDRAM Memory Interface
MDQ[0:63]
M26, L27, L22, K24, M24, M23, K27, K26, K22, J28,
F26, E27, J26, J23, H26, G26, C26, E25, C24, E23,
D26, C25, A24, D23, B23, F22, J21, G21, G22, D22,
H21, E21, N18, J18, D18, L17, M18, L18, C18, A18,
K17, K16, C16, B16, G17, L16, A16, L15, G15, E15,
C14, K13, C15, D15, E14, D14, D13, E13, D12, A11,
F13, H13, A13, B12
I/O
GV
—
DD
MECC[0:7]
MDM[0:8]
MDQS[0:8]
MBA[0:1]
MA[0:14]
N20, M20, L19, E19, C21, A21, G19, A19
L24, H28, F24, L21, E18, E16, G14, B13, M19
L26, J25, D25, A22, H18, F16, F14, C13, C20
B18, B19
I/O
O
GV
GV
GV
GV
GV
—
—
—
—
—
DD
DD
DD
DD
DD
I/O
O
N19, B21, F21, K21, M21, C23, A23, B24, H23, G24,
K19, B25, D27, J14, J13
O
MWE
D17
O
O
O
O
O
O
O
I
GV
GV
GV
GV
GV
GV
GV
GV
GV
—
—
—
—
11
—
—
—
—
DD
DD
DD
DD
DD
DD
DD
DD
DD
MRAS
F17
MCAS
J16
H16, G16, J15, H15
E26, E28
MCS[0:3]
MCKE[0:1]
MCK[0:5]
MCK[0:5]
J20, H25, A15, D20, F28, K14
F20, G27, B15, E20, F27, L14
M28
MSYNC_IN
MSYNC_OUT
N28
O
Local Bus Controller Interface
LA[27]
U18
O
O
OV
OV
OV
5, 9
7, 9
—
DD
DD
DD
LA[28:31]
LAD[0:31]
T18, T19, T20, T21
AD26, AD27, AD28, AC26, AC27, AC28, AA22, AA23,
AA26, Y21, Y22, Y26, W20, W22, W26, V19, T22, R24,
R23, R22, R21, R18, P26, P25, P20, P19, P18, N22,
N23, N24, N25, N26
I/O
LALE
V21
O
O
OV
OV
OV
OV
OV
OV
8, 9
9
DD
DD
DD
DD
DD
DD
LBCTL
V20
U23
LCKE
O
—
—
18
1
LCLK[0:2]
LCS[0:4]
LCS5/DMA_DREQ2
U27, U28, V18
Y27, Y28, W27, W28, R27
R28
O
O
I/O
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
73
Package and Pin Listings
Table 54. MPC8560 Pinout Listing (continued)
Package Pin Number
Power
Supply
Signal
Pin Type
Notes
LCS6/DMA_DACK2
LCS7/DMA_DDONE2
LDP[0:3]
P27
O
O
OV
OV
OV
OV
OV
OV
OV
OV
1
1
DD
DD
DD
DD
DD
DD
DD
DD
P28
AA27, AA28, T26, P21
I/O
O
LGPL0/LSDA10
LGPL1/LSDWE
U19
U22
V28
V27
V23
5, 9
5, 9
8, 9
5, 9
22
O
LGPL2/LOE/LSDRAS
LGPL3/LSDCAS
O
O
LGPL4/LGTA/LUPWAIT/
LPBSE
I/O
LGPL5
V22
T27
O
I
OV
OV
OV
OV
5, 9
—
DD
DD
DD
DD
LSYNC_IN
LSYNC_OUT
T28
O
O
—
LWE[0:1]/LSDDQM[0:1]/LBS
[0:1]
AB28, AB27
1, 5, 9
LWE[2:3]/LSDDQM[2:3]/LBS
[2:3]
T23, P24
O
OV
1, 5, 9
DD
DMA
DMA_DREQ[0:1]
DMA_DACK[0:1]
DMA_DDONE[0:1]
H5, G4
H6, G5
H7, G6
I
OV
OV
OV
—
—
—
DD
DD
DD
O
O
Programmable Interrupt Controller
MCP
AG17
I
OV
OV
OV
OV
OV
OV
OV
OV
—
—
—
9
DD
DD
DD
DD
DD
DD
DD
DD
UDE
AG16
I
I
IRQ[0:7]
AA18, Y18, AB18, AG24, AA21, Y19, AA19, AG25
IRQ8
AB20
Y20
I
IRQ9/DMA_DREQ3
IRQ10/DMA_DACK3
IRQ11/DMA_DDONE3
IRQ_OUT
I
1
AF26
AH24
AB21
I/O
I/O
O
1
1
2, 4
Ethernet Management Interface
EC_MDC
EC_MDIO
F1
E1
O
OV
OV
5, 9
—
DD
DD
I/O
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
74
Freescale Semiconductor
Package and Pin Listings
Table 54. MPC8560 Pinout Listing (continued)
Package Pin Number
Power
Notes
Signal
Pin Type
Supply
Gigabit Reference Clock
EC_GTX_CLK125
E2
I
LV
—
DD
Three-Speed Ethernet Controller (Gigabit Ethernet 1)
TSEC1_TXD[7:4]
TSEC1_TXD[3:0]
TSEC1_TX_EN
TSEC1_TX_ER
TSEC1_TX_CLK
TSEC1_GTX_CLK
TSEC1_CRS
A6, F7, D7, C7
O
O
O
O
I
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
5, 9
9, 19
11
—
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
B7, A7, G8, E8
C8
B8
C6
—
B6
O
I
18
—
C3
TSEC1_COL
G7
I
—
TSEC1_RXD[7:0]
TSEC1_RX_DV
TSEC1_RX_ER
TSEC1_RX_CLK
D4, B4, D3, D5, B5, A5, F6, E6
I
—
D2
E5
D6
I
—
I
—
I
—
Three-Speed Ethernet Controller (Gigabit Ethernet 2)
TSEC2_TXD[7:2]
TSEC2_TXD[1:0]
TSEC2_TX_EN
TSEC2_TX_ER
TSEC2_TX_CLK
TSEC2_GTX_CLK
TSEC2_CRS
B10, A10, J10, K11,J11, H11
O
O
O
O
I
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
LV
5, 9
—
11
—
—
18
—
—
—
—
—
—
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
G11, E11
B11
D11
D10
C10
O
I
D9
TSEC2_COL
F8
I
TSEC2_RXD[7:0]
TSEC2_RX_DV
TSEC2_RX_ER
TSEC2_RX_CLK
F9, E9, C9, B9, A9, H9, G10, F10
I
H8
A8
I
I
E10
I
RapidIO Interface
RIO_RCLK
RIO_RCLK
Y25
Y24
I
I
OV
OV
—
—
DD
DD
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
75
Package and Pin Listings
Table 54. MPC8560 Pinout Listing (continued)
Package Pin Number
Power
Supply
Signal
Pin Type
Notes
RIO_RD[0:7]
RIO_RD[0:7]
RIO_RFRAME
RIO_RFRAME
RIO_TCLK
T25, U25, V25, W25, AA25, AB25, AC25, AD25
I
I
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
OV
—
—
—
—
11
11
—
—
—
—
—
—
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
T24, U24, V24, W24, AA24, AB24, AC24, AD24
AE27
I
AE26
I
AC20
O
O
O
O
O
O
I
RIO_TCLK
AE21
RIO_TD[0:7]
RIO_TD[0:7]
RIO_TFRAME
RIO_TFRAME
RIO_TX_CLK_IN
RIO_TX_CLK_IN
AE18, AC18, AD19, AE20, AD21, AE22, AC22, AD23
AD18, AE19, AC19, AD20, AC21, AD22, AE23, AC23
AE24
AE25
AF24
AF25
I
2
I C interface
IIC_SDA
IIC_SCL
AH22
AH23
I/O
I/O
OV
OV
4, 20
4, 20
DD
DD
System Control
AH16
HRESET
I
O
I
OV
OV
OV
OV
OV
—
—
DD
DD
DD
DD
DD
HRESET_REQ
SRESET
AG20
AF20
—
CKSTP_IN
CKSTP_OUT
M11
I
—
G1
O
2, 4
Debug
TRIG_IN
N12
G2
I
OV
OV
OV
OV
OV
—
6, 9, 19
5, 6, 9
6
DD
DD
DD
DD
DD
TRIG_OUT/READY
MSRCID[0:1]
MSRCID[2:4]
MDVAL
O
O
O
O
J9, G3
F3, F5, F2
F4
6
Clock
SYSCLK
RTC
AH21
AB23
AF22
I
I
OV
OV
OV
—
—
11
DD
DD
DD
CLK_OUT
O
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
76
Freescale Semiconductor
Package and Pin Listings
Table 54. MPC8560 Pinout Listing (continued)
Power
Notes
Signal
Package Pin Number
JTAG
Pin Type
Supply
TCK
TDI
AF21
AG21
AF19
AF23
AG23
I
I
OV
OV
OV
OV
OV
—
12
11
12
12
DD
DD
DD
DD
DD
TDO
TMS
TRST
O
I
I
DFT
LSSD_MODE
L1_TSTCLK
L2_TSTCLK
TEST_SEL
AG19
AB22
AG22
AH20
I
I
I
I
OV
OV
OV
OV
21
21
21
3
DD
DD
DD
DD
Thermal Management
THERM0
THERM1
AG2
AH3
I
I
—
14
14
—
Power Management
AG18
ASLEEP
I/O
9, 19
Power and Ground Signals
AV
AV
AV
1
2
3
AH19
AH18
AH17
Power for e500 PLL AV
(1.2 V)
1
2
3
—
—
—
—
DD
DD
DD
DD
DD
DD
Power for CCB PLL AV
(1.2 V)
Power for CPM PLL AV
(1.2 V)
GND
A12, A17, B3, B14, B20, B26, B27, C2, C4, C11,C17,
C19, C22, C27, D8, E3, E12, E24, F11, F18, F23, G9,
G12, G25, H4, H12, H14, H17, H20, H22, H27, J19,
J24, K5, K9, K18, K23, K28, L6, L20, L25, M4, M12,
M14, M16, M22, M27, N2, N13, N15, N17, P12, P14,
P16, P23, R13, R15, R17, R20, R26, T3, T8, T10, T12,
T14, T16, U6, U13, U15, U16, U17, U21, V7, V10, V26,
W5, W18, W23, Y8, Y16, AA6, AA13, AB4, AB11,
AB19, AC6, AC9, AD3, AD8, AD17, AF2, AF4, AF10,
AF13, AF15, AF27, AG3, AG7, AG26
—
—
GV
A14, A20, A25, A26, A27, A28, B17, B22, B28, C12,
Power for DDR
GV
—
DD
DD
C28, D16, D19, D21, D24, D28, E17, E22, F12, F15, DRAM I/O Voltage
F19, F25, G13, G18, G20, G23, G28, H19, H24, J12,
J17, J22, J27, K15, K20, K25, L13, L23, L28, M25, N21
(2.5 V)
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
77
Package and Pin Listings
Table 54. MPC8560 Pinout Listing (continued)
Package Pin Number
Power
Supply
Signal
Pin Type
Notes
—
LV
A4, C5, E7, H10
Reference Voltage; LV
Three-Speed
DD
DD
Ethernet I/O (2.5 V,
3.3 V)
MV
N27
Reference Voltage MV
Signal; DDR
—
16
—
REF
REF
No Connects
AH26, AH27, AH28, AG28, AF28, AE28,
AH1, AG1, AH2, B1, B2, A2, A3, AH25
—
—
OV
D1, E4, H3, K4, K10, L7, M5, N3, P22, R19, R25, T2,
T7, U5, U20, U26, V8, W4, W13, W19, W21, Y7, Y23,
PCI/PCI-X,
OV
DD
DD
RapidIO, 10/100
AA5, AA12, AA16, AA20, AB7, AB9, AB26, AC5, AC11, Ethernet, and other
AC17, AD4, AE1, AE8, AE10, AE15, AF7, AF12, AG27,
AH4
Standard
(3.3 V)
RESERVED
SENSEVDD
C1, T11, U11, AF1
L12
—
—
15
13
Power for Core
(1.2 V)
V
DD
SENSEVSS
K12
—
—
13
V
M13, M15, M17, N14, N16, P13, P15, P17, R12, R14,
R16, T13, T15, T17, U12, U14
Power for Core
(1.2 V)
V
—
DD
DD
CPM
PA[0:31]
PB[4:31]
PC[0:31]
H1, H2, J1, J2, J3, J4, J5, J6, J7, J8, K8, K7, K6, K3,
K2, K1, L1, L2, L3, L4, L5, L8, L9, L10, L11, M10, M9,
M8, M7, M6, M3, M2
I/0
I/0
I/0
OV
—
—
—
DD
DD
DD
M1, N1, N4, N5, N6, N7, N8, N9, N10, N11, P11, P10,
P9, P8, P7, P6, P5, P4, P3, P2, P1, R1, R2, R3, R4, R5,
R6, R7
OV
OV
R8, R9, R10, R11, T9, T6, T5, T4, T1, U1, U2, U3, U4,
U7, U8, U9, U10, V9, V6, V5, V4, V3, V2, V1, W1, W2,
W3, W6, W7, W8, W9, Y9
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
78
Freescale Semiconductor
Package and Pin Listings
Table 54. MPC8560 Pinout Listing (continued)
Package Pin Number
Power
Notes
Signal
Pin Type
Supply
PD[4:31]
Y1, Y2, Y3, Y4, Y5, Y6, AA8, AA7, AA4, AA3, AA2,
AA1, AB1, AB2, AB3, AB5, AB6, AC7, AC4, AC3, AC2,
AC1, AD1, AD2, AD5, AD6, AE3, AE2
I/0
OV
—
DD
Notes:
1.All multiplexed signals are listed only once and do not re-occur. For example, LCS5/DMA_REQ2 is listed only once in the
Local Bus Controller Interface section, and is not mentioned in the DMA section even though the pin also functions as
DMA_REQ2.
2.Recommend a weak pull-up resistor (2–10 kΩ) be placed on this pin to OV
.
DD
3.This pin must always be pulled up to OV
4.This pin is an open drain signal.
.
DD
5.This pin is a reset configuration pin. It has a weak internal pull-up P-FET which is enabled only when the MPC8560 is in the
reset state. This pull-up is designed such that it can be overpowered by an external 4.7-kΩ pull-down resistor. If an external
device connected to this pin might pull it down during reset, then a pull-up or active driver is needed if the signal is intended
to be high during reset.
6.Treat these pins as no connects (NC) unless using debug address functionality.
7.The value of LA[28:31] during reset sets the CCB clock to SYSCLK PLL ratio. These pins require 4.7-kΩ pull-up or pull-down
resistors. See Section 15.2, “Platform/System PLL Ratio.”
8.The value of LALE and LGPL2 at reset set the e500 core clock to CCB Clock PLL ratio. These pins require 4.7-kΩ pull-up or
pull-down resistors. See the Section 15.3, “e500 Core PLL Ratio.”
9.Functionally, this pin is an output, but structurally it is an I/O because it either samples configuration input during reset or
because it has other manufacturing test functions. This pin will therefore be described as an I/O for boundary scan.
10.This pin functionally requires a pull-up resistor, but during reset it is a configuration input that controls 32- vs. 64-bit PCI
operation. Therefore, it must be actively driven low during reset by reset logic if the device is to be configured to be a 64-bit
PCI device. Refer to the PCI Specification.
11.This output is actively driven during reset rather than being three-stated during reset.
12.These JTAG pins have weak internal pull-up P-FETs that are always enabled.
13.These pins are connected to the V /GND planes internally and may be used by the core power supply to improve tracking
DD
and regulation.
14.Internal thermally sensitive resistor.
15.No connections should be made to these pins.
16.These pins are not connected for any functional use.
17.PCI specifications recommend that a weak pull-up resistor (2–10 kΩ) be placed on the higher order pins to OV when using
DD
64-bit buffer mode (pins PCI_AD[63:32] and PCI_C_BE[7:4]).
18.Note that these signals are POR configurations for Rev. 1.x and notes 5 and 9 apply to these signals in Rev. 1.x but not in
later revisions.
19 If this pin is connected to a device that pulls down during reset, an external pull-up is required to drive this pin to a logic –1
state during reset.
20.Recommend a pull-up resistor (~1 KΩ) b placed on this pin to OV
.
DD
21.These are test signals for factory use only and must be pulled up (100 Ω - 1 kΩ) to OVDD for normal machine operation.
22.If this signal is used as both an input and an output, a weak pull-up (~10 kΩ) is required on this pin.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
79
Clocking
15 Clocking
This section describes the PLL configuration of the MPC8560. Note that the platform clock is identical to
the CCB clock.
15.1 Clock Ranges
Table 55 provides the clocking specifications for the processor core and Table 56 provides the clocking
specifications for the memory bus.
Table 55. Processor Core Clocking Specifications
Maximum Processor Core Frequency
Characteristic
667 MHz
833 MHz
1 GHz
Unit
Notes
Min
400
Max
Min
400
Max
Min
Max
e500 core processor frequency
667
833
400
1000
MHz
1, 2, 3
Notes:
1.Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to Section 15.2, “Platform/System PLL Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio
settings.
2.)The minimum e500 core frequency is based on the minimum platform frequency of 200 MHz.
3.)The 1.0 GHz core frequency is based on a 1.3 V VDD supply voltage.
Table 56. Memory Bus Clocking Specifications
Maximum Processor Core Frequency
Characteristic
667 MHz
833 MHz
1 GHz
Unit
Notes
Min
100
Max
Min
100
Max
Min
Max
Memory bus frequency
166
166
100
166
MHz
1, 2, 3
Notes:
1.Caution: The CCB to SYSCLK ratio and e500 core to CCB ratio settings must be chosen such that the resulting SYSCLK
frequency, e500 (core) frequency, and CCB frequency do not exceed their respective maximum or minimum operating
frequencies. Refer to Section 15.2, “Platform/System PLL Ratio,” and Section 15.3, “e500 Core PLL Ratio,” for ratio
settings.
2.The memory bus speed is half of the DDR data rate, hence, half of the platform clock frequency.
3.)The 1.0 GHz core frequency is based on a 1.3 V VDD supply voltage.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
80
Freescale Semiconductor
Clocking
15.2 Platform/System PLL Ratio
The platform clock is the clock that drives the L2 cache, the DDR SDRAM data rate, and the e500 core
complex bus (CCB), and is also called the CCB clock. The values are determined by the binary value on
LA[28:31] at power up, as shown in Table 57.
There is no default for this PLL ratio; these signals must be pulled to the desired values.
Table 57. CCB Clock Ratio
Binary Value of LA[28:31] Signals
Ratio Description
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
16:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
2:1 ratio CCB clock: SYSCLK (PCI bus)
3:1 ratio CCB clock: SYSCLK (PCI bus)
4:1 ratio CCB clock: SYSCLK (PCI bus)
5:1 ratio CCB clock: SYSCLK (PCI bus)
6:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
8:1 ratio CCB clock: SYSCLK (PCI bus)
9:1 ratio CCB clock: SYSCLK (PCI bus)
10:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
12:1 ratio CCB clock: SYSCLK (PCI bus)
Reserved
Reserved
Reserved
15.3 e500 Core PLL Ratio
Table 58 describes the clock ratio between the e500 core complex bus (CCB) and the e500 core clock. This
ratio is determined by the binary value of LALE and LGPL2 at power up, as shown in Table 58.
Table 58. e500 Core to CCB Ratio
Binary Value of LALE, LGPL2 Signals
Ratio Description
00
01
10
11
2:1 e500 core:CCB
5:2 e500 core:CCB
3:1 e500 core:CCB
7:2 e500 core:CCB
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
81
Thermal
15.4 Frequency Options
Table 59 shows the expected frequency values for the platform frequency when using a CCB to SYSCLK
ratio in comparison to the memory bus speed.
Table 59. Frequency Options with Respect to Memory Bus Speeds
CCB to
SYSCLK
Ratio
SYSCLK (MHz)
66.67
16.67
25
33.33
41.63
83
100
111
133.33
Platform/CCB Frequency (MHz)
2
3
200
300
222
333
267
200
267
333
250
333
4
5
208
250
333
6
200
267
300
333
8
200
225
250
300
9
10
12
16
200
267
16 Thermal
This section describes the thermal specifications of the MPC8560.
16.1 Thermal Characteristics
Table 60 provides the package thermal characteristics for the MPC8560.
Table 60. Package Thermal Characteristics
Characteristic
Symbol
Value
Unit
Notes
Junction-to-ambient Natural Convection on four layer board (2s2p)
Junction-to-ambient (@100 ft/min or 0.5 m/s) on four layer board (2s2p)
Junction-to-ambient (@200 ft/min or 1 m/s) on four layer board (2s2p)
Junction-to-board thermal
R
R
R
16
14
12
7.5
°C/W
°C/W
°C/W
°C/W
1, 2
1, 2
1, 2
3
θJMA
θJMA
θJMA
R
θJB
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
82
Freescale Semiconductor
Thermal
Table 60. Package Thermal Characteristics (continued)
Characteristic
Symbol
Value
Unit
Notes
Junction-to-case thermal
R
0.8
°C/W
4
θJC
Notes
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site
(board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
board thermal resistance
2. Per JEDEC JESD51-6 with the board horizontal.
3. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is
measured on the top surface of the board near the package.
4. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883
Method 1012.1). Cold plate temperature is used for case temperature; measured value includes the thermal
resistance of the interface layer.
16.2 Thermal Management Information
This section provides thermal management information for the flip chip plastic ball grid array (FC-PBGA)
package for air-cooled applications. Proper thermal control design is primarily dependent on the
system-level design—the heat sink, airflow, and thermal interface material. The recommended attachment
method to the heat sink is illustrated in Figure 51. The heat sink should be attached to the printed-circuit
board with the spring force centered over the die. This spring force should not exceed 10 pounds force.
FC-PBGA Package
Heat Sink
Heat Sink
Clip
Adhesive or
Thermal Interface Material
Lid
Die
Printed-Circuit Board
Figure 51. Package Exploded Cross-Sectional View with Several Heat Sink Options
The system board designer can choose between several types of heat sinks to place on the MPC8560. There
are several commercially-available heat sinks from the following vendors:
Aavid Thermalloy
603-224-9988
80 Commercial St.
Concord, NH 03301
Internet: www.aavidthermalloy.com
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
83
Thermal
Alpha Novatech
408-749-7601
473 Sapena Ct. #15
Santa Clara, CA 95054
Internet: www.alphanovatech.com
International Electronic Research Corporation (IERC) 818-842-7277
413 North Moss St.
Burbank, CA 91502
Internet: www.ctscorp.com
Millennium Electronics (MEI)
Loroco Sites
671 East Brokaw Road
San Jose, CA 95112
408-436-8770
800-522-6752
603-635-5102
Internet: www.mei-millennium.com
Tyco Electronics
Chip Coolers™
P.O. Box 3668
Harrisburg, PA 17105-3668
Internet: www.chipcoolers.com
Wakefield Engineering
33 Bridge St.
Pelham, NH 03076
Internet: www.wakefield.com
Ultimately, the final selection of an appropriate heat sink depends on many factors, such as thermal
performance at a given air velocity, spatial volume, mass, attachment method, assembly, and cost. Several
heat sinks offered by Aavid Thermalloy, Alpha Novatech, IERC, Chip Coolers, Millennium Electronics,
and Wakefield Engineering offer different heat sink-to-ambient thermal resistances, that will allow the
MPC8560 to function in various environments.
16.2.1 Recommended Thermal Model
For system thermal modeling, the MPC8560 thermal model is shown in Figure 52. Five cuboids are used
to represent this device. To simplify the model, the solder balls and substrate are modeled as a single block
29x29x1.47 mm with the conductivity adjusted accordingly. For modeling, the planar dimensions of the
die are rounded to the nearest mm, so the die is modeled as 10x12 mm at a thickness of 0.76 mm. The
bump/underfill layer is modeled as a collapsed resistance between the die and substrate assuming a
conductivity of 0.6 in-plane and 1.9 W/m•K in the thickness dimension of 0.76 mm. The lid attach
adhesive is also modeled as a collapsed resistance with dimensions of 10x12x0.050 mm and the
conductivity of 1 W/m•K. The nickel plated copper lid is modeled as 12x14x1 mm. Note that the die and
lid are not centered on the substrate; there is a 1.5 mm offset documented in the case outline drawing in
Figure 50.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
84
Freescale Semiconductor
Thermal
Conductivity
Value
Unit
Lid
(12 × 14 × 1 mm)
Adhesive
Bump/underfill
k
k
k
360
360
360
W/(m × K)
Lid
x
y
z
Die
z
Substrate and solder balls
Lid Adhesive—Collapsed resistance
(10 × 12 × 0.050 mm)
Side View of Model (Not to Scale)
k
k
k
1
1
1
x
y
z
x
Die
(10 × 12 × 0.76 mm)
Substrate
Bump/Underfill—Collapsed resistance
(10 × 12 × 0.070 mm)
Heat Source
k
k
k
0.6
0.6
1.9
x
y
z
Substrate and Solder Balls
y
(29 × 29 × 1.47 mm)
Top View of Model (Not to Scale)
k
k
k
10.2
10.2
1.6
x
y
z
Figure 52. MPC8560 Thermal Model
16.2.2 Internal Package Conduction Resistance
For the packaging technology, shown in Table 60, the intrinsic internal conduction thermal resistance paths
are as follows:
•
•
The die junction-to-case thermal resistance
The die junction-to-board thermal resistance
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
85
Thermal
Figure 53 depicts the primary heat transfer path for a package with an attached heat sink mounted to a
printed-circuit board.
External Resistance
Radiation
Convection
Heat Sink
Thermal Interface Material
Die/Package
Die Junction
Package/Leads
Internal Resistance
Printed-Circuit Board
Radiation
Convection
External Resistance
(Note the internal versus external package resistance)
Figure 53. Package with Heat Sink Mounted to a Printed-Circuit Board
The heat sink removes most of the heat from the device. Heat generated on the active side of the chip is
conducted through the silicon and through the lid, then through the heat sink attach material (or thermal
interface material), and finally to the heat sink. The junction-to-case thermal resistance is low enough that
the heat sink attach material and heat sink thermal resistance are the dominant terms.
16.2.3 Thermal Interface Materials
A thermal interface material is required at the package-to-heat sink interface to minimize the thermal
contact resistance. For those applications where the heat sink is attached by spring clip mechanism,
Figure 54 shows the thermal performance of three thin-sheet thermal-interface materials (silicone,
graphite/oil, floroether oil), a bare joint, and a joint with thermal grease as a function of contact pressure.
As shown, the performance of these thermal interface materials improves with increasing contact pressure.
The use of thermal grease significantly reduces the interface thermal resistance. The bare joint results in a
thermal resistance approximately six times greater than the thermal grease joint.
Heat sinks are attached to the package by means of a spring clip to holes in the printed-circuit board (see
Figure 51). Therefore, the synthetic grease offers the best thermal performance, especially at the low
interface pressure.
When removing the heat sink for re-work, it is preferable to slide the heat sink off slowly until the thermal
interface material loses its grip. If the support fixture around the package prevents sliding off the heat sink,
the heat sink should be slowly removed. Heating the heat sink to 40-50°C with an air gun can soften the
interface material and make the removal easier. The use of an adhesive for heat sink attach is not
recommended.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
86
Freescale Semiconductor
Thermal
Silicone Sheet (0.006 in.)
Bare Joint
2
Floroether Oil Sheet (0.007 in.)
Graphite/Oil Sheet (0.005 in.)
Synthetic Grease
1.5
1
0.5
0
0
10
20
30
Contact Pressure (psi)
Figure 54. Thermal Performance of Select Thermal Interface Materials
40
50
60
70
80
The system board designer can choose between several types of thermal interface. There are several
commercially-available thermal interfaces provided by the following vendors:
Chomerics, Inc.
781-935-4850
77 Dragon Ct.
Woburn, MA 01888-4014
Internet: www.chomerics.com
Dow-Corning Corporation
Dow-Corning Electronic Materials
2200 W. Salzburg Rd.
800-248-2481
Midland, MI 48686-0997
Internet: www.dowcorning.com
Shin-Etsu MicroSi, Inc.
10028 S. 51st St.
Phoenix, AZ 85044
888-642-7674
800-347-4572
Internet: www.microsi.com
The Bergquist Company
th
18930 West 78 St.
Chanhassen, MN 55317
Internet: www.bergquistcompany.com
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
87
Thermal
Thermagon Inc.
888-246-9050
4707 Detroit Ave.
Cleveland, OH 44102
Internet: www.thermagon.com
16.2.4 Heat Sink Selection Examples
The following section provides a heat sink selection example using one of the commercially available heat
sinks.
16.2.4.1 Case 1
For preliminary heat sink sizing, the die-junction temperature can be expressed as follows:
T = T + T + (θ + θ
+ θ ) × P
SA D
J
I
R
JC
INT
where
T is the die-junction temperature
J
T is the inlet cabinet ambient temperature
I
T is the air temperature rise within the computer cabinet
R
θ
θ
θ
is the junction-to-case thermal resistance
JC
is the adhesive or interface material thermal resistance
INT
is the heat sink base-to-ambient thermal resistance
SA
P is the power dissipated by the device
D
During operation the die-junction temperatures (T ) should be maintained within the range specified in
J
Table 2. The temperature of air cooling the component greatly depends on the ambient inlet air temperature
and the air temperature rise within the electronic cabinet. An electronic cabinet inlet-air temperature (T )
A
may range from 30° to 40°C. The air temperature rise within a cabinet (T ) may be in the range of 5° to
R
10°C. The thermal resistance of some thermal interface material (θ ) may be about 1°C/W. Assuming a
INT
T of 30°C, a T of 5°C, a FC-PBGA package θ = 0.8, and a power consumption (P ) of 7.0 W, the
I
R
JC
D
following expression for T is obtained:
J
Die-junction temperature: T = 30°C + 5°C + (0.8°C/W + 1.0°C/W + θ ) × 7.0 W
J
SA
The heat sink-to-ambient thermal resistance (θ ) versus airflow velocity for a Thermalloy heat sink
SA
#2328B is shown in Figure 55.
Assuming an air velocity of 2 m/s, we have an effective θ
of about 3.3°C/W, thus
SA+
T = 30°C + 5°C + (0.8°C/W +1.0°C/W + 3.3°C/W) × 7.0 W,
J
resulting in a die-junction temperature of approximately 71°C which is well within the maximum
operating temperature of the component.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
88
Freescale Semiconductor
Thermal
8
7
6
5
4
3
2
1
Thermalloy #2328B Pin-fin Heat Sink
(25 × 28 × 15 mm)
0
0.5
1
1.5
Approach Air Velocity (m/s)
Figure 55. Thermalloy #2328B Heat Sink-to-Ambient Thermal Resistance Versus Airflow Velocity
2
2.5
3
3.5
16.2.4.2 Case 2
Every system application has different conditions that the thermal management solution must solve. As an
alternate example, assume that the air reaching the component is 85 °C with an approach velocity of 1
m/sec. For a maximum junction temperature of 105 °C at 7 W, the total thermal resistance of junction to
case thermal resistance plus thermal interface material plus heat sink thermal resistance must be less than
2.8 °C/W. The value of the junction to case thermal resistance in Table 60 includes the thermal interface
resistance of a thin layer of thermal grease as documented in footnote 4 of the table. Assuming that the
heat sink is flat enough to allow a thin layer of grease or phase change material, then the heat sink must be
less than 2 °C/W.
Millennium Electronics (MEI) has tooled a heat sink MTHERM-1051 for this requirement assuming a
compactPCI environment at 1 m/sec and a heat sink height of 12 mm. The MEI solution is illustrated in
Figure 56 and Figure 57. This design has several significant advantages:
•
•
•
The heat sink is clipped to a plastic frame attached to the application board with screws or plastic
inserts at the corners away from the primary signal routing areas.
The heat sink clip is designed to apply the force holding the heat sink in place directly above the
die at a maximum force of less than 10 lbs.
For applications with significant vibration requirements, silicone damping material can be applied
between the heat sink and plastic frame.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
89
Thermal
The spring mounting should be designed to apply the force only directly above the die. By localizing the
force, rocking of the heat sink is minimized. One suggested mounting method attaches a plastic fence to
the board to provide the structure on which the heat sink spring clips. The plastic fence also provides the
opportunity to minimize the holes in the printed-circuit board and to locate them at the corners of the
package. Figure 56 and Figure 57 provide exploded views of the plastic fence, heat sink, and spring clip.
Figure 56. Exploded Views (1) of a Heat Sink Attachment using a Plastic Force
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
90
Freescale Semiconductor
Thermal
Figure 57. Exploded Views (2) of a Heat Sink Attachment using a Plastic Fence
The die junction-to-ambient and the heat sink-to-ambient thermal resistances are common figure-of-merits
used for comparing the thermal performance of various microelectronic packaging technologies, one
should exercise caution when only using this metric in determining thermal management because no single
parameter can adequately describe three-dimensional heat flow. The final die-junction operating
temperature is not only a function of the component-level thermal resistance, but the system level design
and its operating conditions. In addition to the component’s power consumption, a number of factors affect
the final operating die-junction temperature: airflow, board population (local heat flux of adjacent
components), system air temperature rise, altitude, etc.
Due to the complexity and the many variations of system-level boundary conditions for today’s
microelectronic equipment, the combined effects of the heat transfer mechanisms (radiation convection
and conduction) may vary widely. For these reasons, we recommend using conjugate heat transfer models
for the boards, as well as, system-level designs.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
91
System Design Information
17 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8560.
17.1 System Clocking
The MPC8560 includes three PLLs.
1. The platform PLL generates the platform clock from the externally supplied SYSCLK input. The
frequency ratio between the platform and SYSCLK is selected using the platform PLL ratio
configuration bits as described in Section 15.2, “Platform/System PLL Ratio.”
2. The e500 Core PLL generates the core clock as a slave to the platform clock. The frequency ratio
between the e500 core clock and the platform clock is selected using the e500 PLL ratio
configuration bits as described in Section 15.3, “e500 Core PLL Ratio.”
3. The CPM PLL is slaved to the platform clock and is used to generate clocks used internally by the
CPM block. The ratio between the CPM PLL and the platform clock is fixed and not under user
control.
17.2 PLL Power Supply Filtering
Each of the PLLs listed above is provided with power through independent power supply pins (AV 1,
DD
AV 2, and AV 3, respectively). The AV level should always be equivalent to V , and preferably
DD
DD
DD
DD
these voltages will be derived directly from V through a low frequency filter scheme such as the
DD
following.
There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to
provide three independent filter circuits as illustrated in Figure 58, one to each of the three AV pins. By
DD
providing independent filters to each PLL the opportunity to cause noise injection from one PLL to the
other is reduced.
This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz
range. It should be built with surface mount capacitors with minimum Effective Series Inductance (ESL).
Consistent with the recommendations of Dr. Howard Johnson in High Speed Digital Design: A Handbook
of Black Magic (Prentice Hall, 1993), multiple small capacitors of equal value are recommended over a
single large value capacitor.
Each circuit should be placed as close as possible to the specific AV pin being supplied to minimize
DD
noise coupled from nearby circuits. It should be possible to route directly from the capacitors to the AV
pin, which is on the periphery of the 783 FC-PBGA footprint, without the inductance of vias.
DD
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
92
Freescale Semiconductor
System Design Information
Figure 58 shows the PLL power supply filter circuit.
10 Ω
V
AV (or L2AV
)
DD
DD
DD
2.2 µF
2.2 µF
Low ESL Surface Mount Capacitors
GND
Figure 58. PLL Power Supply Filter Circuit
17.3 Decoupling Recommendations
Due to large address and data buses, and high operating frequencies, the MPC8560 can generate transient
power surges and high frequency noise in its power supply, especially while driving large capacitive loads.
This noise must be prevented from reaching other components in the MPC8560 system, and the MPC8560
itself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system
designer place at least one decoupling capacitor at each V , OV , GV , and LV pins of the
DD
DD
DD
DD
MPC8560. These decoupling capacitors should receive their power from separate V , OV , GV ,
DD
DD
DD
LV , and GND power planes in the PCB, utilizing short traces to minimize inductance. Capacitors may
DD
be placed directly under the device using a standard escape pattern. Others may surround the part.
These capacitors should have a value of 0.01 or 0.1 µF. Only ceramic SMT (surface mount technology)
capacitors should be used to minimize lead inductance, preferably 0402 or 0603 sizes.
In addition, it is recommended that there be several bulk storage capacitors distributed around the PCB,
feeding the V , OV , GV , and LV planes, to enable quick recharging of the smaller chip
DD
DD
DD
DD
capacitors. These bulk capacitors should have a low ESR (equivalent series resistance) rating to ensure the
quick response time necessary. They should also be connected to the power and ground planes through two
vias to minimize inductance. Suggested bulk capacitors—100–330 µF (AVX TPS tantalum or Sanyo
OSCON).
17.4 Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. Unused active low inputs should be tied to OV , GV , or LV as required. Unused active high
DD
DD
DD
inputs should be connected to GND. All NC (no-connect) signals must remain unconnected.
Power and ground connections must be made to all external V , GV , LV , OV , and GND pins of
DD
DD
DD
DD
the MPC8560.
17.5 Output Buffer DC Impedance
The MPC8560 drivers are characterized over process, voltage, and temperature. There are two driver
2
types: a push-pull single-ended driver (open drain for I C) for all buses except RapidIO, and a
current-steering differential driver for the RapidIO port.
To measure Z for the single-ended drivers, an external resistor is connected from the chip pad to OV
0
DD
or GND. Then, the value of each resistor is varied until the pad voltage is OV /2 (see Figure 59). The
DD
output impedance is the average of two components, the resistances of the pull-up and pull-down devices.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
93
System Design Information
When data is held high, SW1 is closed (SW2 is open) and R is trimmed until the voltage at the pad equals
P
OV /2. R then becomes the resistance of the pull-up devices. R and R are designed to be close to each
DD
P
P
N
other in value. Then, Z = (R + R )/2.
0
P
N
OV
DD
R
N
SW2
SW1
Pad
Data
R
P
OGND
Figure 59. Driver Impedance Measurement
The output impedance of the RapidIO port drivers targets 200-Ω differential resistance. The value of this
resistance and the strength of the driver’s current source can be found by making two measurements. First,
the output voltage is measured while driving logic 1 without an external differential termination resistor.
The measured voltage is V = R
1 with an external precision differential termination resistor of value R . The measured voltage is
× I
. Second, the output voltage is measured while driving logic
1
source
source
term
V = 1/(1/R + 1/R )) × I
. Solving for the output impedance gives R
= R
× (V /V – 1). The
2
1
2
source
source
term 1 2
drive current is then I
= V /R
.
source
1
source
Table 61 summarizes the signal impedance targets. The driver impedance are targeted at minimum V
,
DD
nominal OV , 105°C.
DD
Table 61. Impedance Characteristics
Local Bus, Ethernet, DUART, Control,
Configuration, Power Management
Impedance
PCI/PCI-X DDR DRAM RapidIO Symbol
Unit
R
N
43 Target
43 Target
NA
25 Target
25 Target
NA
20 Target
20 Target
NA
NA
NA
Z
Z
W
W
W
0
0
R
P
Differential
200 Target
Z
DIFF
Note: Nominal supply voltages. See Table 1, T = 105°C.
j
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
94
Freescale Semiconductor
System Design Information
17.6 Configuration Pin Muxing
The MPC8560 provides the user with power-on configuration options which can be set through the use of
external pull-up or pull-down resistors of 4.7 kΩ on certain output pins (see customer visible configuration
pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these pins
while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is disabled
and the I/O circuit takes on its normal function. Most of these sampled configuration pins are equipped
with an on-chip gated resistor of approximately 20 kΩ. This value should permit the 4.7-kΩ resistor to pull
the configuration pin to a valid logic low level. The pull-up resistor is enabled only during HRESET (and
for platform/system clocks after HRESET deassertion to ensure capture of the reset value). When the input
receiver is disabled the pull-up is also, thus allowing functional operation of the pin as an output with
minimal signal quality or delay disruption. The default value for all configuration bits treated this way has
been encoded such that a high voltage level puts the device into the default state and external resistors are
needed only when non-default settings are required by the user.
Careful board layout with stubless connections to these pull-down resistors coupled with the large value
of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus
configured.
The platform PLL ratio and e500 PLL ratio configuration pins are not equipped with these default pull-up
devices.
17.7 Pull-Up Resistor Requirements
The MPC8560 requires high resistance pull-up resistors (10 kΩ is recommended) on open drain type pins
2
including EPIC interrupt pins. I C open drain type pins should be pulled up with ~1 kΩ resistors.
Correct operation of the JTAG interface requires configuration of a group of system control pins as
demonstrated in Figure 61. Care must be taken to ensure that these pins are maintained at a valid deasserted
state under normal operating conditions as most have asynchronous behavior and spurious assertion will
give unpredictable results.
TSEC1_TXD[3:0] must not be pulled low during reset. Some PHY chips have internal pulldowns that
could cause this to happen. If such PHY chips are used, then a pullup must be placed on these signals strong
enough to restore these signals to a logical 1 during reset.
Three test pins also require pull-up resistors (100 Ω - 1 kΩ). These pins are L1_TSTCLK, L2_TSTCLK,
and LSSD_MODE. These signals are for factory use only and must be pulled up to OVDD for normal
machine operation.
Refer to the PCI 2.2 specification for all pull-ups required for PCI.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
95
System Design Information
17.8 JTAG Configuration Signals
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the Power Architecture. The
device requires TRST to be asserted during reset conditions to ensure the JTAG boundary logic does not
interfere with normal chip operation. While it is possible to force the TAP controller to the reset state using
only the TCK and TMS signals, generally systems will assert TRST during the power-on reset flow.
Simply tying TRST to HRESET is not practical because the JTAG interface is also used for accessing the
common on-chip processor (COP) function.
The COP function of these processors allow a remote computer system (typically, a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The COP
interface connects primarily through the JTAG port of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order
to fully control the processor. If the target system has independent reset sources, such as voltage monitors,
watchdog timers, power supply failures, or push-button switches, then the COP reset signals must be
merged into these signals with logic.
The arrangement shown in Figure 60 allows the COP port to independently assert HRESET or TRST,
while ensuring that the target can drive HRESET as well.
The COP interface has a standard header, shown in Figure 60, for connection to the target system, and is
based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header). The
connector typically has pin 14 removed as a connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory
examination/modification, and other standard debugger features. An inexpensive option can be to leave
the COP header unpopulated until needed.
There is no standardized way to number the COP header; consequently, many different pin numbers have
been observed from emulator vendors. Some are numbered top-to-bottom then left-to-right, while others
use left-to-right then top-to-bottom, while still others number the pins counter clockwise from pin 1 (as
with an IC). Regardless of the numbering, the signal placement recommended in Figure 60 is common to
all known emulators.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
96
Freescale Semiconductor
System Design Information
1
3
2
4
COP_TDO
COP_TDI
NC
COP_TRST
COP_VDD_SENSE
COP_CHKSTP_IN
NC
5
7
6
8
COP_TCK
COP_TMS
COP_SRESET
9
10
12
NC
NC
11
KEY
13
15
COP_HRESET
No pin
GND
COP_CHKSTP_OUT
16
Figure 60. COP Connector Physical Pinout
17.8.1 Termination of Unused Signals
If the JTAG interface and COP header will not be used, Freescale recommends the following connections:
•
TRST should be tied to HRESET through a 0 kΩ isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
the power-on reset flow. Freescale recommends that the COP header be designed into the system
as shown in Figure 61. If this is not possible, the isolation resistor will allow future access to TRST
in case a JTAG interface may need to be wired onto the system in future debug situations.
•
•
Tie TCK to OV through a 10 kΩ resistor. This will prevent TCK from changing state and
DD
reading incorrect data into the device.
No connection is required for TDI, TMS, or TDO.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
97
System Design Information
OV
DD
10 kΩ
10 kΩ
6
1
SRESET
SRESET
HRESET
From Target
Board Sources
(if any)
HRESET
COP_HRESET
13
11
10 kΩ
10 kΩ
10 kΩ
10 kΩ
COP_SRESET
5
1
TRST
COP_TRST
4
2
1
3
2
10 Ω
4
COP_VDD_SENSE
NC
6
5
5
7
6
8
COP_CHKSTP_OUT
CKSTP_OUT
15
10 kΩ
9
10
12
3
14
11
10 kΩ
KEY
13
15
COP_CHKSTP_IN
COP_TMS
No pin
CKSTP_IN
TMS
8
9
1
16
COP_TDO
COP_TDI
COP_TCK
COP Connector
Physical Pinout
TDO
3
TDI
7
2
TCK
10 kΩ
NC
NC
10
4
12
16
Notes:
1. The COP port and target board should be able to independently assert HRESET and TRST to the processor
in order to fully control the processor as shown here.
2. Populate this with a 10 Ω resistor for short-circuit/current-limiting protection.
3. The KEY location (pin 14) is not physically present on the COP header.
4. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for
improved signal integrity.
5. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid
accidentally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed.
6. Asserting SRESET causes a machine check interrupt to the e500 core.
Figure 61. JTAG Interface Connection
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
98
Freescale Semiconductor
Document Revision History
18 Document Revision History
Table 62 provides a revision history for this hardware specification.
Table 62. Document Revision History
Rev. No.
Substantive Change(s)
4.2
Added “Note: Rise/Fall Time on CPM Input Pins” and following note text to Section 9.2, “CPM AC Timing
Specifications.”
4.1
4
Inserted Figure 3 and paragraph above it.
Added PCI/PCI-X row to Input Voltage characteristic and added footnote 6 to Table 1.
Updated Section 2.1.2, “Power Sequencing.”
Updated back page information.
3.5
3.4
Updated Section 2.1.2, “Power Sequencing.”
Updated MV
Updated MV
Max Value in Table 1.
Max Value in Table 2.
REF
REF
Added new revision level information to Table 63
3.3
Updated MV Max Value in Table 1.
REF
Removed Figure 3.
In Table 4, replaced TBD with power numbers and added footnote.
Updated specs and footnotes in Table 8.
Corrected max number for MV
in Table 13.
REF
Changed parameter “Clock cycle duration” to “Clock period” in Table 27.
Added note 4 to t and removed LALE reference from t in Table 31 and Table 32.
LBKHOV1
LBKHOV3
Updated LALE signal in Figure 17 and Figure 18.
Modified Figure 21.
Modified Figure 61.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
99
Document Revision History
Rev. No.
Table 62. Document Revision History (continued)
Substantive Change(s)
3.2
Updated Table 1 and Table 2 with 1.0 GHz device parameter requirements.
Added Section 2.1.2, “Power Sequencing”.
Added CPM port signal drive strength to Table 3.
Updated Table 4 with Maximum power data.
Updated Table 4 and Table 5 with 1 GHz speed grade information.
Updated Table 6 with corrected typical I/O power numbers.
Updated Table 7 Note 2 lower voltage measurement point.
Replaced Table 7 Note 5 with spread spectrum clocking guidelines.
Added to Table 8 rise and fall time information.
Added Section 4.4, “Real Time Clock Timing”.
Added precharge information to Section 6.2.2, “DDR SDRAM Output AC Timing Specifications”.
Removed V and V references from Table 21, Table 22, Table 23, and Table 24.
IL
IH
Added reference level note to Table 21, Table 22, Table 23, Table 24, Table 25, Table 26, and Table 27.
Updated TXD references to TCG in Section 7.2.3.1, “TBI Transmit AC Timing Specifications”.
Updated t
value in Table 25.
TTKHDX
Updated PMA_RX_CLK references to RX_CLK in Section 7.2.3.2, “TBI Receive AC Timing
Specifications”.
Updated RXD references to RCG in Section 7.2.3.2, “TBI Receive AC Timing Specifications”.
Updated Table 27 Note 2.
Corrected Table 29 f
and t
to reflect the correct minimum operating frequency.
MDC
MDC
Updated Table 29 t
and t
values for clarification.
MDKHDX
MDKHDV
Added t
and updated Note 2 in Table 32.
LBKHKT
Corrected LGTA timing references in Figure 17.
Updated Figure 18, Figure 20, and Figure 22.
Corrected FCC output timing reference labels in Figure 24 and Figure 25.
Updated Figure 50.
Clarified Table 54 Note 5.
Updated Table 55 and Table 56 with 1 GHz information.
Added heat sink removal discussion to Section 16.2.3, “Thermal Interface Materials”.
Corrected and added 1 GHz part number to Table 63.
3.1
Updated Table 4 and Table 5.
Added Table 6.
Added MCK duty cycle to Table 16.
Updated f
, t
, t
, and t
parameters in Table 29.
MDC MDC MDKHDV
MDKHDX
Added LALE to t
parameter in Table 31 and Table 32, and updated Figure 17.
LBKHOV3
Corrected active level designations of some of the pins in Table 54.
Updated Table 63.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
100
Freescale Semiconductor
Document Revision History
Table 62. Document Revision History (continued)
Substantive Change(s)
Rev. No.
3.0
Table 1—Corrected MII management voltage reference
Section 2.1.3—New
Table 2—Corrected MII management voltage reference
Table 5—Removed ‘minimum’ column
Table 5—Added AV power table
DD
Table 8—New
Table 9—New
Table 9—New
Table 13—Added overshoot/undershoot note.
Figure 4—New
Table 16—Restated t
as t
, removed t
; added speed-specific minimum
MCKSKEW2
MCKSKEW1
MCKSKEW
values for 333, 266, and 200 MHz; updated t
values.
DDSHME
Updated chapter to reflect that GMII, MII and TBI can be run with 2.5V signalling.
Table 29—Added MDIO output valid timing
Table 31—Updated t
Table 32—New
, t
, and t
.
LBIVKH1 LBIXKH1
LBOTOT
Figure 20, Figure 22—Updated clock reference
Table 34—Updated t
Table 35—Updated t
TDIVKH
TDKHOX
2
Added tables and figures for CPM I C
Table 45—Updated t
PCIVKH
Section 14.1— Changed minimum height from 2.22 to 3.07 and maximum from 2.76 to 3.75
Table 54.—Updated MII management voltage reference and added note 20.
Section 16.2.4.1—Changed θ from 0.3 to 0.8; changed die-junction temperature from 67° to 71°
JC
Section 17.7—Added paragraph that begins “TSEC1_TXD[3:0]...”
2.1
Section 2.1.3—New
Table 16—Added speed-specific minimum values for 333, 266, and 200 MHz
Table 31—Replaced all references to TSEC1_TXD[6:5] to TSEC2_TXD[6:5]
Table 31—Added t
and note 3
LBSKEW
Table 31—Added comment about rev. 2.x devices to note 5
Section 14.1— Changed minimum height from 2.22 to 3.07 and maximum from 2.76 to 3.75
Section 16.2.4.1—Changed θ from 0.3 to 0.8; changed die-junction temperature from 67° to 71°
JC
Section 17.7—Added paragraph that begins “TSEC1_TXD[3:0]...”
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
101
Document Revision History
Rev. No.
Table 62. Document Revision History (continued)
Substantive Change(s)
2.0
Section 1.1—Updated features list to coincide with latest version of the reference manual
Table 1 and Table 2— Addition of CPM to OV and OV ; Addition of SYSCLK to OV
IN
DD
IN
Table 2—Addition of notes 1 and 2
Table 3—Addition of note 1
Table 5—New
Section 4—New
Table 13—Addition of I
VREF
Table 15—Modified maximum values for t
DISKEW
Table 16—Added MSYNC_OUT to t
Figure 5—New
MCKSKEW2
Section 6.2.1—Removed Figure 4, "DDR SDRAM Input Timing Diagram"
Section 7.1—Removed references to 2.5 V from first paragraph
Figure 8—New
Table 19 and Table 20—Modified “conditions” for I and I
IH
IL
Table 21—Addition of min and max for GTX_CLK125 reference clock duty cycle
Table 25—Addition of min and max for GTX_CLK125 reference clock duty cycle
Table 27—Addition of min and max for GTX_CLK125 reference clock duty cycle
Figure 17 and Figure 19—Changed LSYNC_IN to Internal clock at top of each figure
Table 34—Modified values for t
Table 35—Modified values for t
Figure 16—New
t
, and t
; addition of t
and t
.
PIIXKH
FIIVKH, NIIVKH
TDIVKH
PIIVKH
t
t
t
; addition of t
FEKHOX, NIKHOX, NEKHOX, TDKHOX PIKHOX.
Figure 30—New
Figure 16—New
Figure 16—New
Table 31—Removed row for t
LBKHOX3
Table 44—New (AC timing of PCI-X at 66 MHz)
Table 54—Addition of note 19
Figure 61—Addition of jumper and note at top of diagram
Table 56—Changed max bus freq for 667 core to 166
Section 16.2.1—Modified first paragraph
Figure 52—Modified
Figure 53—New
Table 60—Modified thermal resistance data
Section 16.2.4.2—Modified first and second paragraphs
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
102
Freescale Semiconductor
Document Revision History
Table 62. Document Revision History (continued)
Substantive Change(s)
Rev. No.
1.2
Section 1.1.1—Updated feature list.
Section 1.2.1.1—Updated notes for Table 1.
Section 1.2.1.2—Removed 5-V PCI interface overshoot and undershoot figure.
Section 1.2.1.3—Added this section to summarize impedance driver settings for various interfaces.
Section 1.4—Updated rows in Reset Initialization timing specifications table. Added a table with DLL and
PLL timing specifications.
Section 1.5.2.2—Updated note 6 of DDR SDRAM Output AC Timing Specifications table.
Section 1.7—Changed the minimum input low current from -600 to -15 μA for the RGMII DC electrical
characteristics.
Section 1.7.2—Changed LCS[3:4] to TSEC1_TXD[6:5]. Updated notes regarding LCS[3:4].
Section 1.13.2—Updated the mechanical dimensions diagram for the package.
Section 1.13.3—Updated the notes for LBCTL, TRIG_OUT, and ASLEEP. Corrected pin assignments
for IIC_SDA and IIC_SCL. Corrected reserved pin assignment of V11 to U11. V11 is actually PCI_STOP.
Section 1.14.1—Updated the table for frequency options with respect to platform/CCB frequencies.
Section 1.14.4—Edited Frequency options with respect to memory bus speeds.
1.1
Made updates throughout document.
Section 1.6.1—Added symbols and note for the GTX_CLK125 timing parameters.
Section 1.11.3—Updated pin list table: LGPL5/LSDAMUX to LGPL5, LA[27:29] and LA[30:31] to
LA[27:31], TRST to TRST, added GBE Clocking section and EC_GTX_CLK125 signal.
Figure 50—Updated pin 2 connection information.
1
Original Customer Version.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
103
Device Nomenclature
19 Device Nomenclature
Ordering information for the parts fully covered by this specification document is provided in
Section 19.1, “Part Numbers Fully Addressed by this Document.”
19.1 Part Numbers Fully Addressed by this Document
Table 63 provides the Freescale part numbering nomenclature for the MPC8560. Note that the individual
part numbers correspond to a maximum processor core frequency. For available frequencies, contact your
local Freescale sales office. In addition to the processor frequency, the part numbering scheme also
includes an application modifier which may specify special application conditions. Each part number also
contains a revision code which refers to the die mask revision number.
Table 63. Part Numbering Nomenclature
MPC
nnnn
t
pp
ff(f)
c
r
Product
Code
Part
Identifier
Temperature
Processor
Frequency
Platform
Frequency
2
Package
Revision Level
1
3, 4
Range
MPC
MPC
8560
8560
Blank = 0 to 105°C
C= -40 to 105°C
PX = FC-PBGA 833 = 833 MHz L = 333 MHz B = Rev. 2.0
VT = FC-PBGA 667 = 667 MHz J= 266 MHz
(Pb-free)
(SVR = 0x80700020)
C = Rev. 2.1
(SVR = 0x80700021)
Blank = 0 to 105°C
C = –40 to 105°C
PX = FC-PBGA AQ = 1.0 GHz
VT = FC-PBGA
F = 333 MHz B = Rev. 2.0
(SVR = 0x80700020)
C = Rev. 2.1
(Pb-free)
(SVR = 0x80700021)
Notes:
1.For Temperature Range=C, Processor Frequency is limited to 667 MHz.
2.See Section 14, “Package and Pin Listings” for more information on available package types.
3.Processor core frequencies supported by parts addressed by this specification only. Not all parts described in this
specification support all core frequencies. The core must be clocked at a minimum frequency of 400 MHz. A device
must not be used beyond the core frequency or platform frequency indicated on the device.
4. Designers should use the maximum power value corresponding to the core and platform frequency grades indicated on
the device. A lower maximum power value should not be assumed for design purposes even when running at a lower
frequency.
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
104
Freescale Semiconductor
Device Nomenclature
19.2 Part Marking
Parts are marked as the example shown in Figure 62.
MPCnnnntppfffcr
ATWLYYWWA
MMMMMCCCCC
YWWLAZ
FC-PBGA
Notes:
MMMMM is the 5-digit mask number.
ATWLYYWWA is the traceability code.
CCCCC is the country of assembly. This space is left blank if parts are assembled in the United States.
YWWLAZ is the assembly traceability code.
Figure 62. Part Marking for FC-PBGA Device
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
105
Device Nomenclature
THIS PAGE INTENTIONALLY LEFT BLANK
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
106
Freescale Semiconductor
Device Nomenclature
THIS PAGE INTENTIONALLY LEFT BLANK
MPC8560 Integrated Processor Hardware Specifications, Rev. 4.2
Freescale Semiconductor
107
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Document Number: MPC8560EC
Rev. 4.2
1/2008
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