MPC9230ACR2 [NXP]
750MHz, OTHER CLOCK GENERATOR, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BBA, LQFP-32;
| 型号： | MPC9230ACR2 |
| 厂家： | 
NXP |
| 描述： | 750MHz, OTHER CLOCK GENERATOR, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, LEAD FREE, MS-026BBA, LQFP-32 时钟 外围集成电路 晶体 |
| 文件： | 总16页 (文件大小：375K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC9230
Rev. 5, 08/2005
Freescale Semiconductor
Technical Data
800 MHz Low Voltage PECL
Clock Synthesizer
MPC9230
The MPC9230 is a 3.3 V compatible, PLL based clock synthesizer targeted for
high performance clock generation in mid-range to high-performance telecom,
networking and computing applications. With output frequencies from 50 MHz to
800 MHz(1) and the support of differential PECL output signals the device meets
the needs of the most demanding clock applications.
800 MHz LOW VOLTAGE
CLOCK SYNTHESIZER
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
50 MHz to 800 MHz(1) synthesized clock output signal
FN SUFFIX
28-LEAD PLCC PACKAGE
Differential PECL output
CASE 776-02
LVCMOS compatible control inputs
On-chip crystal oscillator for reference frequency generation
Alternative LVCMOS compatible reference clock input
3.3 V power supply
EI SUFFIX
28-LEAD PLCC PACKAGE
Pb-FREE PACKAGE
CASE 776-02
Fully integrated PLL
Minimal frequency overshoot
Serial 3-wire programming interface
Parallel programming interface for power-up
32-lead LQFP and 28-lead PLCC packaging
32-lead and 28-lead Pb-free package available
SiGe Technology
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-04
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-04
Ambient temperature range -40°C to +85°C
Pin and function compatible to the MC12430
Functional Description
The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. The frequency of the
internal crystal oscillator is divided by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 800
to 1600 MHz.(1) Its output is scaled by a divider that is configured by either the serial or parallel interfaces. The crystal oscillator
frequency fXTAL, the PLL feedback-divider M and the PLL post-divider N determine the output frequency.
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be 8⋅M times the reference frequency
by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase
lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1600 MHz(1)). The M-value
must be programmed by the serial or parallel interface.
The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division
ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven
differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 Ω to VCC – 2.0 V. The
positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize
noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes
valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs and prevent the LVCMOS compatible control
inputs from floating.
The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See the program-
ming section for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0] bits in
the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.
1. The VCO frequency range of 800–1600 MHz is available at an ambient temperature range of 0 to 70°C. At –40 to +85°C, the VCO frequency
(output frequency) is limited to max. 1500 MHz (750 MHz).
© Freescale Semiconductor, Inc., 2005. All rights reserved.
XTAL_IN
XTAL_OUT
XTAL
÷1
÷2
÷4
÷8
VCO
÷
11
00
01
10
2
Ref
÷
16
10 – 20 MHz
FOUT
FOUT
PLL
OE
800 – 1800 MHz
FREF_EXT
FB
VCC
÷0 TO ÷511
9-BIT M-Divider
Test
Test
÷
2
XTAL_SEL
3
2
9
VCC
M-Latch
N-Latch
T-Latch
LE
P_LOAD
S_LOAD
P/S
0
1
0
1
Bits 3-4
Bits 5-13
Bits 0-2
S_DATA
S_CLOCK
14-Bit Shift Register
VCC
M[0:8]
N[1:0]
OE
Figure 1. MPC9230 Logic Diagram
24 23 22 21 20 19 18 17
25
24
23
22
21
20 19
S_CLOCK
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
NC
GND
TEST
VCC
N[1]
N[0]
M[8]
M[7]
M[6]
M[5]
M[4]
26
27
18
17
16
15
14
M[3]
S_DATA
S_LOAD
M[2]
28
1
VCC
M[1]
MPC9230
VCC_PLL
MPC9230
GND
FOUT
M[0]
FREF_EXT
XTAL_SEL
XTAL_IN
2
3
4
P_LOAD
OE
13
12
FOUT
VCC
XTAL_OUT
1
2
3
4
5
6
7
8
5
6
7
8
9
10 11
Figure 2. MPC9230 28-Lead PLCC Pinout
Figure 3. MPC9230 32-Lead Package Pinout
(Top View)
(Top View)
MPC9230
Advanced Clock Drivers Devices
Freescale Semiconductor
2
Table 1. Pin Configurations
Pin
XTAL_IN, XTAL_OUT
FREF_EXT
FOUT, FOUT
TEST
I/O
Default
Type
Function
Analog
Crystal oscillator interface
Input
Output
Output
Input
0
LVCMOS Alternative PLL reference input
LVPECL Differential clock output
LVCMOS Test and device diagnosis output
LVCMOS PLL reference select input
LVCMOS Serial configuration control input
XTAL_SEL
S_LOAD
1
0
Input
This input controls the loading of the configuration latches with the contents of the
shift register. The latches will be transparent when this signal is high, thus the data
must be stable on the high-to-low transition.
P_LOAD
Input
1
LVCMOS Parallel configuration control input.
This input controls the loading of the configuration latches with the content of the
parallel inputs (M and N). The latches will be transparent when this signal is low,
thus the parallel data must be stable on the low-to-high transition of P_LOAD.
P_LOAD is state sensitive.
S_DATA
S_CLOCK
M[0:8]
Input
Input
Input
0
0
1
LVCMOS Serial configuration data input
LVCMOS Serial configuration clock input
LVCMOS Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD
N[1:0]
OE
Input
Input
1
1
LVCMOS Parallel configuration for Post-PLL divider (N).
N is sampled on the low-to-high transition of P_LOAD
LVCMOS Output enable (active high)
The output enable is synchronous to the output clock to eliminate the possibility of
runt pulses on the FOUT output
GND
VCC
Supply
Supply
Ground
VCC
Negative power supply (GND)
Positive power supply for I/O and core. All VCC pins must be connected to the
positive power supply for correct operation
VCC_PLL
Supply
VCC
PLL positive power supply (analog power supply)
Table 2. Output Frequency Range and PLL Post-Divider N
N
Output Frequency Range
for TA = 0°C to +70°C
Output Frequency Range
for TA = –40°C to +85°C
Output Division
1
0
0
1
1
0
0
1
0
1
2
4
8
1
200 – 400 MHz
100 – 200 MHz
50 – 100 MHz
400 – 800 MHz
200 – 375 MHz
100 – 187.5 MHz
50 – 93.75 MHz
400 – 750 MHz
Table 3. Function Table
Input
XTAL_SEL
OE
0
1
FREF_EXT
XTAL interface
Outputs enabled
Outputs disabled. FOUT is stopped in the logic low state
(FOUT = L, FOUT = H)
MPC9230
Advanced Clock Drivers Devices
Freescale Semiconductor
3
Table 4. General Specifications
Symbol
VTT
Characteristics
Min
Typ
Max
Unit
V
Condition
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch-Up Immunity
VCC – 2
MM
200
2000
200
V
HBM
LU
V
mA
pF
CIN
Input Capacitance
4.0
Inputs
θJA
LQFP 32 Thermal Resistance Junction to Ambient
JESD 51-3, single layer test board
83.1
73.3
68.9
63.8
57.4
86.0
75.4
70.9
65.3
59.6
°C/W Natural convection
°C/W 100 ft/min
°C/W 200 ft/min
°C/W 400 ft/min
°C/W 800 ft/min
JESD 51-6, 2S2P multilayer test board
59.0
54.4
52.5
50.4
47.8
60.6
55.7
53.8
51.5
48.8
°C/W Natural convection
°C/W 100 ft/min
°C/W 200 ft/min
°C/W 400 ft/min
°C/W 800 ft/min
θJC
LQFP 32 Thermal Resistance Junction to Case
23.0
26.3
°C/W MIL-SPEC 883E
Method 1012.1
Table 5. Absolute Maximum Ratings(1)
Symbol
VCC
VIN
Characteristics
Min
–0.3
–0.3
–0.3
Max
4.6
Unit
V
Condition
Supply Voltage
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
VCC + 0.3
VCC + 0.3
±20
V
VOUT
IIN
IOUT
TS
V
mA
mA
°C
±50
–65
125
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 6. DC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS Control Inputs (FREF_EXT, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1]. OE)
VIH
VIL
IIN
Input High Voltage
Input Low Voltage
2.0
VCC + 0.3
0.8
V
V
LVCMOS
LVCMOS
Input Current(1)
±200
µA
VIN = VCC or GND
(2)
Differential Clock Output FOUT
VOH
VOL
Output High Voltage
Output Low Voltage
VCC–1.02
VCC–1.95
VCC–0.74
VCC–1.60
V
V
LVPECL
LVPECL
Test and Diagnosis Output TEST
VOH
VOL
Output High Voltage
Output Low Voltage
VCC–1.02
VCC–1.95
VCC–0.74
VCC–1.60
V
V
LVPECL
LVPECL
Supply Current
ICC_PLL Maximum PLL Supply Current
ICC Maximum Supply Current
20
mA VCC_PLL Pins
mA All VCC Pins
110
1. Inputs have pull-down resistors affecting the input current.
2. Outputs terminated 50 Ω to VTT = VCC – 2 V.
MPC9230
Advanced Clock Drivers Devices
Freescale Semiconductor
4
Table 7. AC Characteristics (VCC = 3.3 V ± 5%, TA = –40°C to +85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS Control Inputs (FREF_EXT, XTAL_SEL, P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1]. OE)
VIH
VIL
IIN
Input High Voltage
Input Low Voltage
2.0
VCC + 0.3
0.8
V
V
LVCMOS
LVCMOS
Input Current(1)
±200
µA
VIN = VCC or GND
(2)
Differential Clock Output FOUT
VOH
VOL
Output High Voltage
Output Low Voltage
VCC–1.1
VCC–0.74
VCC–1.65
V
V
LVPECL
LVPECL
VCC–1.95
Test and Diagnosis Output TEST
VOH
VOL
Output High Voltage
Output Low Voltage
VCC–1.1
VCC–0.74
VCC–1.65
V
V
LVPECL
LVPECL
VCC–1.95
Supply Current
ICC_PLL Maximum PLL Supply Current
ICC Maximum Supply Current
20
mA VCC_PLL Pins
mA All VCC Pins
110
1. Inputs have pull-down resistors affecting the input current.
2. Outputs terminated 50 Ω to VTT = VCC – 2 V.
MPC9230
Advanced Clock Drivers Devices
Freescale Semiconductor
5
Table 8. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)(1)
Symbol
fXTAL
fREF
Characteristics
Crystal Interface Frequency Range
FREF_EXT Reference Frequency Range
VCO Frequency Range(3)
Min
10
Typ
Max
Unit
Condition
20
MHz
10
(fVCO,MAX÷M)⋅4(2) MHz
fVCO
800
1600
MHz
fMAX
Output Frequency
N = 11 (÷1)
N = 00 (÷2)
N = 01 (÷4)
N = 10 (÷8)
400
200
100
50
800
400
200
100
MHz
MHz
MHz
MHz
fS_CLOCK Serial Interface Programming Clock Frequency(4)
0
50
10
MHz
ns
tP,MIN
DC
tr, tf
tS
Minimum Pulse Width
Output Duty Cycle
Output Rise/Fall Time
Setup Time
(S_LOAD, P_LOAD)
45
50
55
%
0.05
0.3
ns
20% to 80%
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
20
ns
ns
ns
tH
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
20
ns
ns
tJIT(CC)
Cycle-to-Cycle Jitter
N = 11 (÷1)
N = 00 (÷2)
N = 01 (÷4)
N = 10 (÷8)
80
90
130
160
ps
ps
ps
ps
tJIT(PER)
Period Jitter
N = 11 (÷1)
N = 00 (÷2)
N = 01 (÷4)
N = 10 (÷8)
60
70
120
140
ps
ps
ps
ps
tLOCK
Maximum PLL Lock Time
10
ms
1. AC characteristics apply for parallel output termination of 50 Ω to VTT
.
2. The maximum frequency on FREF_EXT is a function of the max. VCO frequency and the M counter. M should be higher than 160 for stable
PLL operation.
3. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL ⋅ M ÷ 4.
4. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used
as test clock in test mode 6. See APPLICATIONS INFORMATION for more details.
MPC9230
Advanced Clock Drivers Devices
6
Freescale Semiconductor
Table 9. AC Characteristics (VCC = 3.3 V ± 5%, TA = –40°C to +85°C)(1)
Symbol
fXTAL
fREF
Characteristics
Crystal Interface Frequency Range
FREF_EXT Reference Frequency Range
VCO Frequency Range(3)
Min
10
Typ
Max
20
Unit
MHz
MHz
MHz
Condition
10
(fVCO,MAX÷M)·4(2)
fVCO
800
1500
fMAX
Output Frequency
N = 11 (÷1)
N = 00 (÷2)
N = 01 (÷4)
N = 10 (÷8)
400
200
100
50
750.00
375.00
187.50
93.75
MHz
MHz
MHz
MHz
fS_CLOCK Serial Interface Programming Clock Frequency(4)
0
50
10
MHz
ns
tP,MIN
DC
tr, tf
tS
Minimum Pulse Width
Output Duty Cycle
Output Rise/Fall Time
Setup Time
(S_LOAD, P_LOAD)
45
50
55
%
0.05
0.3
ns
20% to 80%
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
20
ns
ns
ns
tH
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
20
ns
ns
tJIT(CC) Cycle-to-Cycle Jitter
N = 11 (÷1)
N = 00 (÷2)
N = 01 (÷4)
N = 10 (÷8)
80
90
130
160
ps
ps
ps
ps
tJIT(CC) Period Jitter
N = 11 (÷1)
N = 00 (÷2)
N = 01 (÷4)
N = 10 (÷8)
60
70
120
140
ps
ps
ps
ps
tLOCK
Maximum PLL Lock Time
10
ms
1. AC characteristics apply for parallel output termination of 50 Ω to VTT.
2. The maximum frequency on FREF_EXT is a function of the max. VCO frequency and the M counter. M should be higher than 160 for stable
PLL operation.
3. The input frequency fXTAL and the PLL feedback divider M must match the VCO frequency range: fVCO = fXTAL ⋅ M ÷ 4.
4. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used
as test clock in test mode 6. See APPLICATIONS INFORMATION for more details.
MPC9230
Advanced Clock Drivers Devices
Freescale Semiconductor
7
PROGRAMMING INTERFACE
match the VCO frequency range of 800 to 1600 MHz in order
Programming the MPC9230
to achieve stable PLL operation:
MMIN = 4⋅fVCO,MIN ÷ fXTAL and
MMAX = 4⋅fVCO,MAX ÷ fXTAL
Programming the MPC9230 amounts to properly
configuring the internal PLL dividers to produce the desired
synthesized frequency at the output. The output frequency
can be represented by this formula:
(3)
(4)
For instance, the use of a 16 MHz input frequency requires
the configuration of the PLL feedback divider between
M = 200 and M = 400. Table 10 shows the usable VCO
frequency and M divider range for other example input
frequencies. Assuming that a 16 MHz input frequency is
used, equation (2) reduces to:
FOUT = (fXTAL ÷ 16) ⋅ (4 ⋅ M) ÷ (2 ⋅ N) or
FOUT = (fXTAL ÷ 8) ⋅ M ÷ N
(1)
(2)
where fXTAL is the crystal frequency, M is the PLL feedback-
divider and N is the PLL post-divider. The input frequency and
the selection of the feedback divider M is limited by the
VCO-frequency range. fXTAL and M must be configured to
FOUT = 2 ⋅ M ÷ N
(5)
Table 10. MPC9230 Frequency Operating Range
Output frequency for fXTAL=16 MHz and for N =
VCO frequency for an crystal interface frequency of [MHz]
M
M[8:0]
10
12
14
16
18
20
800
1
2
4
8
160 010100000
170 010101010
180 010110100
190 010111110
200 011001000
210 011010010
220 011011100
230 011100110
240 011110000
250 011111010
260 100000100
270 100001110
280 100011000
290 100100010
300 100101100
310 100110110
320 101000000
330 101001010
340 101010100
350 101011110
360 101101000
370 101110010
380 101111100
390 110000110
400 110010000
410 110011010
420 110100100
430 110101110
440 110111000
450 111000010
850
810
855
900
950
800
840
900
1000
1050
1100
1150
1200
1250
1300
1350
1400
1450
1500
1550(1)
1600(1)
400
420
440
460
480
500
520
540
560
580
600
620
640
660
680
700
720
740
760(2)
780(2)
800(2)
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
360
370
380(2)
390(2)
400(2)
100
105
110
115
120
125
130
135
140
145
150
155
160
165
170
175
180
185
190(2)
195(2)
200(2)
50
52.5
55
945
880
990
805
840
920
1035
1080
1125
1170
1215
1260
1305
1350
1395
1440
1485
1530(1)
1575(1)
57.5
60
960
875
100
62.5
65
910
1040
1080
1120
1160
1200
1240
1280
1320
1360
1400
1440
1480
1520(1)
1560(1)
1600(1)
810
840
945
67.5
70
980
870
1015
1050
1085
1120
1155
1190
1225
1260
1295
1330
1365
1400
1435
1470
1505(1)
1540(1)
1575(1)
72.5
75
900
930
77.5
80
800
825
960
990
82.5
85
850
1020
1050
1080
1110
1140
1170
1200
1230
1260
1290
1320
1350
875
87.5
90
900
925
92.5
95(2)
97.5(2)
100(2)
950
975
1000
1025
1050
1075
1100
1125
1. This VCO frequency is only available at the 0°C to +70°C temperature range.
2. This output frequency is only available at the 0°C to +70°C temperature range.
MPC9230
Advanced Clock Drivers Devices
Freescale Semiconductor
8
Substituting N for the four available values for N (1, 2, 4, 8)
yields:
Example Frequency Calculation for an 16 MHz Input
Frequency
If an output frequency of 131 MHz was desired, the
following steps would be taken to identify the appropriate M
and N values. According to Table 11, 131 MHz falls in the
frequency set by a value of 4, so N[1:0] = 01. For N = 4, the
output frequency is FOUT = M ÷ 2 and M = FOUT x 2.
Therefore M = 2 x 131 = 262, so M[8:0] = 010000011.
Following this procedure a user can generate any whole
frequency between 50 MHz and 800 MHz. Note than for
N > 2 fractional values of can be realized. The size of the
programmable frequency steps (and thus the indicator of the
fractional output frequencies achievable) will be equal to:
Table 11. Output Frequency Range for fXTAL = 16 MHz
N
Output
Output
Frequency
Range for
A = 0°C to 70°C TA = –40°C to 85°C
Frequency
Range for
FOUT
Step
FOUT
1 0 Value
T
0 0
0 1
1 0
1 1
2
4
8
1
M
200 – 400 MHz 200 – 375 MHz
1 MHz
M÷2 100 – 200 MHz
M÷4 50 – 100 MHz
2 ⋅ M 400 – 800 MHz
100 – 187.5 MHz 500 kHz
50 – 93.75 MHz 250 kHz
400 – 750 MHz
2 MHz
fSTEP = fXTAL ÷ 8 ÷ N
APPLICATIONS INFORMATION
itself; however, the PLL bypass mode may be of interest at
Using the Parallel and Serial Interface
the board level for functional debug. When T[2:0] is set to 110
the MPC9230 is placed in PLL bypass mode. In this mode the
S_CLOCK input is fed directly into the M and N dividers. The
N divider drives the FOUT differential pair and the M counter
drives the TEST output pin. In this mode the S_CLOCK input
could be used for low speed board level functional test or
debug. Bypassing the PLL and driving FOUT directly gives the
user more control on the test clocks sent through the clock
tree. Table 12 shows the functional setup of the PLL bypass
mode. Because the S_CLOCK is a CMOS level, the input
frequency is limited to 200 MHz. This means the fastest the
FOUT pin can be toggled via the S_CLOCK is 50 MHz as the
divide ratio of the Post-PLL divider is 4 (if N = 1). Note that the
M counter output on the TEST output will not be a 50% duty
cycle.
The M and N counters can be loaded either through a
parallel or serial interface. The parallel interface is controlled
via the P_LOAD signal such that a LOW to HIGH transition
will latch the information present on the M[8:0] and N[1:0]
inputs into the M and N counters. When the P_LOAD signal
is LOW, the input latches will be transparent and any changes
on the M[8:0] and N[1:0] inputs will affect the FOUT output
pair. To use the serial port, the S_CLOCK signal samples the
information on the S_DATA line and loads it into a 14 bit shift
register. Note that the P_LOAD signal must be HIGH for the
serial load operation to function. The Test register is loaded
with the first three bits, the N register with the next two and
the M register with the final eight bits of the data stream on
the S_DATA input. For each register the most significant bit is
loaded first (T2, N1 and M8). A pulse on the S_LOAD pin after
the shift register is fully loaded will transfer the divide values
into the counters. The HIGH to LOW transition on the
Table 12. Test and Debug Configuration for TEST
S_LOAD input will latch the new divide values into the
counters. Figure 4 illustrates the timing diagram for both a
parallel and a serial load of the MPC9230 synthesizer. M[8:0]
and N[1:0] are normally specified once at power-up through
the parallel interface, and then possibly again through the
serial interface. This approach allows the application to come
up at one frequency and then change or fine-tune the clock
as the ability to control the serial interface becomes available.
T[2:0]
TEST Output
T2
0
T1
0
T0
0
14-bit shift register out(1)
0
0
1
Logic 1
0
1
0
fXTAL ÷ 16
0
1
1
M-Counter out
1
0
0
FOUT
Using the Test and Diagnosis Output TEST
1
0
1
Logic 0
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the
parallel interface. Although it is possible to select the node
that represents FOUT, the LVPECL compatible TEST output is
not able to toggle fast enough for higher output frequencies
and should only be used for test and diagnosis. The T2, T1
and T0 control bits are preset to ‘000' when P_LOAD is LOW
so that the LVPECL compatible FOUT outputs are as jitter-free
as possible. Any active signal on the TEST output pin will
have detrimental affects on the jitter of the PECL output pair.
In normal operations, jitter specifications are only guaranteed
if the TEST output is static. The serial configuration port can
be used to select one of the alternate functions for this pin.
Most of the signals available on the TEST output pin are
useful only for performance verification of the MPC9230
1
1
0
M-Counter out in PLL-bypass mode
1
1
1
FOUT ÷ 4
1. Clocked out at this rate of S_CLOCK.
Table 13. Debug Configuration for PLL Bypass(1)
Output
FOUT
Configuration
S_CLOCK ÷ N
M-Counter out(2)
TEST
1. T[2:0]=110. AC specifications do not apply in PLL bypass mode.
2. Clocked out at the rate of S_CLOCK÷(2⋅N).
MPC9230
Advanced Clock Drivers Devices
Freescale Semiconductor
9
S_CLOCK
S_DATA
S_LOAD
M0
T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1
First
Last
Bit
Bit
M[8:0]
N[1:0]
M, N
P_LOAD
Figure 4. Serial Interface Timing Diagram
Power Supply Filtering
RF = 10-15 Ω
VCC_PLL
MPC9230
VCC
The MPC9230 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise
on the VCC_PLL pin impacts the device characteristics. The
MPC9230 provides separate power supplies for the digital
circuitry (VCC) and the internal PLL (VCC_PLL) of the device.
The purpose of this design technique is to try and isolate the
high switching noise digital outputs from the relatively
sensitive internal analog phase-locked loop. In a controlled
environment such as an evaluation board, this level of
isolation is sufficient; however, in a digital system
environment where it is more difficult to minimize noise on the
power supplies, a second level of isolation may be required.
The simplest form of isolation is a power supply filter on the
VCC_PLL pin for the MPC9230. Figure 5 illustrates a typical
power supply filter scheme. The MPC9230 is most
susceptible to noise with spectral content in the 1 kHz to
1 MHz range. Therefore, the filter should be designed to
target this range. The key parameter that needs to be met in
the final filter design is the DC voltage drop that will be seen
between the VCC supply and the MPC9230 pin of the
MPC9230. From the data sheet, the VCC_PLL current (the
current sourced through the VCC_PLL pin) is maximum
20 mA, assuming that a minimum of 2.835 V must be
maintained on the VCC_PLL pin. The resistor shown in
Figure 5 must have a resistance of 10–15 Ω to meet the
voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20 kHz. As the noise
frequency crosses the series resonant point of an individual
capacitor, its overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL. Generally, the resistor/capacitor filter
will be cheaper, easier to implement and provide an adequate
level of supply filtering. A higher level of attenuation can be
achieved by replacing the resistor with an appropriate valued
inductor. A 1000 µH choke will show a significant impedance
at 10 kHz frequencies and above. Because of the current
draw and the voltage that must be maintained on the VCC_PLL
pin, a low DC resistance inductor is required (less than 15 Ω).
C2
CF = 22 µF
VCC
C1, C2 = 0.01...0.1 µF
C1
Figure 5. VCC_PLL Power Supply Filter
Layout Recommendations
The MPC9230 provides sub-nanosecond output edge
rates and thus a good power supply bypassing scheme is a
must. Figure 6 shows a representative board layout for the
MPC9230. There exists many different potential board
layouts, and the one pictured is but one. The important
aspect of the layout in Figure 6 is the low impedance
connections between VCC and GND for the bypass
capacitors. Combining good quality general purpose chip
capacitors with good PCB layout techniques will produce
effective capacitor resonances at frequencies adequate to
supply the instantaneous switching current for the MPC9230
outputs. It is imperative that low inductance chip capacitors
are used; it is equally important that the board layout does not
reintroduce all of the inductance saved by using the leadless
capacitors. Thin interconnect traces between the capacitor
and the power plane should be avoided, and multiple large
vias should be used to tie the capacitors to the buried power
planes. Fat interconnect and large vias will help to minimize
layout induced inductance and thus maximize the series
resonant point of the bypass capacitors. Note the dotted lines
circling the crystal oscillator connection to the device. The
oscillator is a series resonant circuit, and the voltage
amplitude across the crystal is relatively small. It is imperative
that no actively switching signals cross under the crystal, as
crosstalk energy coupled to these lines could significantly
impact the jitter of the device. Special attention should be
paid to the layout of the crystal to ensure a stable, jitter free
interface between the crystal and the on-board oscillator.
Although the MPC9230 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL), there still may
be applications in which overall performance is being
MPC9230
Advanced Clock Drivers Devices
Freescale Semiconductor
10
degraded due to system power supply noise. The power
supply filter and bypass schemes discussed in this section
should be adequate to eliminate power supply noise related
problems in most designs.
required. Because the series resonant design is affected by
capacitive loading on the XTAL terminals, loading variation
introduced by crystals from different vendors could be a
potential issue. For crystals with a higher shunt capacitance,
it may be required to place a resistance across the terminals
to suppress the third harmonic. Although typically not
required, it is a good idea to layout the PCB with the provision
of adding this external resistor. The resistor value will typically
be between 500 and 1 KΩ.
C1
C1
The oscillator circuit is a series resonant circuit and thus
for optimum performance a series resonant crystal should be
used. Unfortunately, most crystals are characterized in a
parallel resonant mode. Fortunately, there is no physical
difference between a series resonant and a parallel resonant
crystal. The difference is purely in the way the devices are
characterized. As a result, a parallel resonant crystal can be
used with the MPC9230 with only a minor error in the desired
frequency. A parallel resonant mode crystal used in a series
resonant circuit will exhibit a frequency of oscillation a few
hundred ppm lower than specified; a few hundred ppm
translates to kHz inaccuracies. In a general, computer
application at this level of inaccuracy is immaterial. Table 14
below specifies the performance requirements of the crystals
to be used with the MPC9230.
1
CF
C2
XTAL
= VCC
= GND
= Via
Table 14. Recommended Crystal Specifications
Figure 6. PCB Board Layout Recommendation for
the PLCC28 Package
Parameter
Value
Fundamental AT Cut
Series Resonance(1)
±75 ppm at 25°C
±150 pm 0 to 70°C
0 to 70°C
Crystal Cut
Resonance
Using the On-Board Crystal Oscillator
The MPC9230 features a fully integrated on-board crystal
oscillator to minimize system implementation costs. The
oscillator is a series resonant, multivibrator type design as
opposed to the more common parallel resonant oscillator
design. The series resonant design provides better stability
and eliminates the need for large on-chip capacitors. The
oscillator is totally self contained so that the only external
component required is the crystal. As the oscillator is
somewhat sensitive to loading on its inputs, the user is
advised to mount the crystal as close to the MPC9230 as
possible to avoid any board level parasitics. To facilitate co-
location, surface mount crystals are recommended but not
Frequency Tolerance
Frequency/Temperature Stability
Operating Range
Shunt Capacitance
5–7 pF
Equivalent Series Resistance (ESR)
Correlation Drive Level
Aging
50 to 80 Ω
100 µΩ
5 ppm/Yr (First 3 Years)
1. See accompanying text for series versus parallel resonant
discussion.
MPC9230
11
Advanced Clock Drivers Devices
Freescale Semiconductor
PACKAGE DIMENSIONS
M
S
S
S
0.007 (0.180)
T
L-M
N
B
Y BRK
D
-N-
M
S
N
0.007 (0.180)
T L-M
U
Z
-M-
-L-
W
D
S
S
S
N
0.010 (0.250)
T L-M
X
G1
V
28
1
VIEW D-D
M
S
S
N
A
0.007 (0.180)
0.007 (0.180)
T L-M
M
S
S
N
0.007 (0.180)
T
L-M
H
Z
M
S
S
N
T
L-M
R
C
K1
E
0.004 (0.100)
G
K
SEATING
PLANE
-T-
J
M
S
S
N
0.007 (0.180)
VIEW S
T L-M
F
VIEW S
G1
S
S
S
N
0.010 (0.250)
T L-M
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXISTS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DEMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASITC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
INCHES
MILLIMETERS
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
MIN
MAX MIN
0.495 12.32
0.495 12.32
MAX
12.57
12.57
4.57
0.485
0.485
0.165
0.090
0.013
0.180
0.110
0.019
4.20
2.29
0.33
2.79
0.48
0.050 BSC
1.27 BSC
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
---
0.032
---
0.66
0.51
0.64
0.81
---
---
---
0.456 11.43
0.456 11.43
11.58
11.58
1.21
1.21
1.42
0.50
10˚
0.048
0.048
0.056
0.020
10˚
1.07
1.07
1.07
---
2˚
2˚
0.410
0.040
0.430 10.42
--- 1.02
10.92
---
CASE 776-02
ISSUE D
28-LEAD PLCC PACKAGE
MPC9230
Advanced Clock Drivers Devices
Freescale Semiconductor
12
PACKAGE DIMENSIONS
PAGE 1 OF 3
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
MPC9230
13
Advanced Clock Drivers Devices
Freescale Semiconductor
PACKAGE DIMENSIONS
PAGE 2 OF 3
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
MPC9230
Advanced Clock Drivers Devices
Freescale Semiconductor
14
PACKAGE DIMENSIONS
PAGE 3 OF 3
CASE 873A-04
ISSUE C
32-LEAD LQFP PACKAGE
MPC9230
15
Advanced Clock Drivers Devices
Freescale Semiconductor
How to Reach Us:
Home Page:
www.freescale.com
E-mail:
support@freescale.com
USA/Europe or Locations Not Listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
support@freescale.com
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GmbH
Technical Information Center
Schatzbogen 7
81829 Muenchen, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
support@freescale.com
Information in this document is provided solely to enable system and software
implementers to use Freescale Semiconductor products. There are no express or
implied copyright licenses granted hereunder to design or fabricate any integrated
circuits or integrated circuits based on the information in this document.
Freescale Semiconductor reserves the right to make changes without further notice to
any products herein. Freescale Semiconductor makes no warranty, representation or
guarantee regarding the suitability of its products for any particular purpose, nor does
Freescale Semiconductor assume any liability arising out of the application or use of any
product or circuit, and specifically disclaims any and all liability, including without
limitation consequential or incidental damages. “Typical” parameters that may be
provided in Freescale Semiconductor data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by
customer’s technical experts. Freescale Semiconductor does not convey any license
under its patent rights nor the rights of others. Freescale Semiconductor products are
not designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Freescale Semiconductor product
could create a situation where personal injury or death may occur. Should Buyer
purchase or use Freescale Semiconductor products for any such unintended or
unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and
its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that Freescale
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064
Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T., Hong Kong
+800 2666 8080
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Semiconductor was negligent regarding the design or manufacture of the part.
Denver, Colorado 80217
Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc.
All other product or service names are the property of their respective owners.
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
© Freescale Semiconductor, Inc. 2005. All rights reserved.
LDCForFreescaleSemiconductor@hibbertgroup.com
MPC9230
Rev. 5
08/2005
相关型号：
©2020 ICPDF网 联系我们和版权申明