MPC92429ACR2 [NXP]
400MHz, OTHER CLOCK GENERATOR, PQFP32, LEAD FREE, LQFP-32;
| 型号： | MPC92429ACR2 |
| 厂家： | 
NXP |
| 描述： | 400MHz, OTHER CLOCK GENERATOR, PQFP32, LEAD FREE, LQFP-32 时钟 外围集成电路 晶体 |
| 文件： | 总12页 (文件大小：292K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC92429
Rev 3, 05/2005
Freescale Semiconductor
Technical Data
400 MHz Low Voltage PECL
Clock Synthesizer
MPC92429
The MPC92429 is a 3.3 V compatible, PLL based clock synthesizer targeted
for high performance clock generation in mid-range to high-performance
telecom, networking and computing applications. With output frequencies from
25 MHz to 400 MHz and the support of differential PECL output signals the
device meets the needs of the most demanding clock applications.
400 MHZ LOW VOLTAGE
CLOCK SYNTHESIZER
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
25 MHz to 400 MHz synthesized clock output signal
Differential PECL output
LVCMOS compatible control inputs
On-chip crystal oscillator for reference frequency generation
3.3 V power supply
FN SUFFIX
28-LEAD PLCC PACKAGE
CASE 776-02
Fully integrated PLL
Minimal frequency overshoot
EI SUFFIX
28-LEAD PLCC PACKAGE
Pb-FREE PACKAGE
CASE 776-02
Serial 3-wire programming interface
Parallel programming interface for power-up
32-lead LQFP and 28-PLCC packaging
32-lead and 28-lead Pb-free package available
SiGe Technology
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A-03
Ambient temperature range 0°C to +70°C
Pin and function compatible to the MC12429 and MPC9229
AC SUFFIX
32-LEAD LQFP PACKAGE
Pb-FREE PACKAGE
CASE 873A-03
Functional Description
The internal crystal oscillator uses the external quartz crystal as the basis of
its frequency reference. The frequency of the internal crystal oscillator is divided
by 16 and then multiplied by the PLL. The VCO within the PLL operates over a range of 800 to 1600 MHz. Its output is scaled by
a divider that is configured by either the serial or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL feedback-
divider M and the PLL post-divider N determine the output frequency.
The feedback path of the PLL is internal. The PLL adjusts the VCO output frequency to be 4 x M times the reference frequency
by adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve phase
lock. The PLL will be stable if the VCO frequency is within the specified VCO frequency range (800 to 1600 MHz). The M-value
must be programmed by the serial or parallel interface.
The PLL post-divider N is configured through either the serial or the parallel interfaces, and can provide one of four division
ratios (1, 2, 4, or 8). This divider extends performance of the part while providing a 50% duty cycle. The output driver is driven
differentially from the output divider, and is capable of driving a pair of transmission lines terminated 50 Ω to VCC – 2.0 V. The
positive supply voltage for the internal PLL is separated from the power supply for the core logic and output drivers to minimize
noise induced jitter.
The configuration logic has two sections: serial and parallel. The parallel interface uses the values at the M[8:0] and N[1:0]
inputs to configure the internal counters. It is recommended on system reset to hold the P_LOAD input LOW until power becomes
valid. On the LOW-to-HIGH transition of P_LOAD, the parallel inputs are captured. The parallel interface has priority over the
serial interface. Internal pullup resistors are provided on the M[8:0] and N[1:0] inputs prevent the LVCMOS compatible control
inputs from floating.
The serial interface centers on a fourteen bit shift register. The shift register shifts once per rising edge of the S_CLOCK input.
The serial input S_DATA must meet setup and hold timing as specified in the AC Characteristics section of this document. The
configuration latches will capture the value of the shift register on the HIGH-to-LOW edge of the S_LOAD input. See PROGRAM-
MING INTERFACE for more information. The TEST output reflects various internal node values, and is controlled by the T[2:0]
bits in the serial data stream. In order to minimize the PLL jitter, it is recommended to avoid active signal on the TEST output.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
XTAL_IN
XTAL_OUT
Ref
÷1
÷2
÷4
÷8
VCO
XTAL
÷16
00
01
10
11
FOUT
FOUT
10 – 20 MHz
PLL
OE
200 – 400 MHz
FB
SYNC
÷0 TO ÷511
9-BIT M-DIVIDER
TEST
TEST
3
2
9
V
CC
M-LATCH
N-LATCH
T-LATCH
LE
P/S
P_LOAD
S_LOAD
0
1
0
1
BITS 3-4
BITS 5-13
BITS 0-2
S_DATA
S_CLOCK
14-BIT SHIFT REGISTER
V
CC
M[0:8]
N[1:0]
OE
Figure 1. MPC92429 Logic Diagram
24 23 22 21 20 19 18 17
25
26
24
23 22
21
20 19
S_CLOCK
N[1]
N[0]
M[8]
M[7]
18
17
16
15
14
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
NC
GND
M[3]
TEST
S_DATA
S_LOAD
27
V
V
M[2]
CC
CC
28
1
M[1]
V
MPC92429
CC_PLL
MPC92429
GND
M[0]
NC
NC
M[6]
M[5]
M[4]
2
3
FOUT
P_LOAD
OE
13
12
FOUT
XTAL_IN
4
V
XTAL_OUT
CC
1
2
3
4
5
6
7
8
5
6
7
8
9
10 11
Figure 2. MPC92429 28-Lead PLCC Pinout
Figure 3. MPC92429 32-Lead Package Pinout
(Top View)
(Top View)
MPC92429
Product Group
Freescale Semiconductor
2
Table 1. Pin Configurations
Pin
XTAL_IN, XTAL_OUT
FOUT, FOUT
TEST
I/O
Default
Type
Function
Analog
Crystal oscillator interface.
Output
Output
Input
LVPECL Differential clock output.
LVCMOS Test and device diagnosis output.
S_LOAD
0
1
LVCMOS Serial configuration control input.
This inputs controls the loading of the configuration latches with the contents of the
shift register. The latches will be transparent when this signal is high, thus the data
must be stable on the high-to-low transition.
P_LOAD
Input
LVCMOS Parallel configuration control input.
This input controls the loading of the configuration latches with the content of the
parallel inputs (M and N). The latches will be transparent when this signal is low,
thus the parallel data must be stable on the low-to-high transition of P_LOAD.
P_LOAD is state sensitive.
S_DATA
S_CLOCK
M[0:8]
Input
Input
Input
0
0
1
LVCMOS Serial configuration data input.
LVCMOS Serial configuration clock input.
LVCMOS Parallel configuration for PLL feedback divider (M).
M is sampled on the low-to-high transition of P_LOAD.
N[1:0]
OE
Input
Input
1
1
LVCMOS Parallel configuration for Post-PLL divider (N).
N is sampled on the low-to-high transition of P_LOAD.
LVCMOS Output enable (active high).
The output enable is synchronous to the output clock to eliminate the possibility
of runt pulses on the F
output. OE = L low stops F
in the logic low state
OUT
OUT
(F
= L, FOUT = H).
OUT
GND
Supply
Supply
Supply
Supply
Ground
Negative power supply (GND).
V
V
Positive power supply for I/O and core. All V pins must be connected to the
CC
CC
CC
positive power supply for correct operation.
V
Supply
Supply
V
PLL positive power supply (analog power supply).
CC_PLL
CC
Table 2. Output Frequency Range and PLL Post-Divider N
N
Output Division
Output Frequency Range
1
0
0
1
1
0
0
1
0
1
1
2
4
8
200 – 400 MHz
100 – 200 MHz
50 – 100 MHz
25 – 50 MHz
MPC92429
Product Group
Freescale Semiconductor
3
Table 3. General Specifications
Symbol
Characteristics
Min
Typ
– 2
Max
Unit
V
Condition
V
Output Termination Voltage
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch-Up Immunity
V
TT
CC
MM
HBM
LU
200
2000
200
V
V
mA
pF
C
Input Capacitance
4.0
Inputs
IN
θ
LQFP 32 Thermal Resistance Junction to Ambient
JESD 51-3, single layer test board
JA
83.1
73.3
68.9
63.8
57.4
86.0
75.4
70.9
65.3
59.6
°C/W Natural convection
°C/W 100 ft/min
°C/W 200 ft/min
°C/W 400 ft/min
°C/W 800 ft/min
JESD 51-6, 2S2P multilayer test board
59.0
54.4
52.5
50.4
47.8
60.6
55.7
53.8
51.5
48.8
°C/W Natural convection
°C/W 100 ft/min
°C/W 200 ft/min
°C/W 400 ft/min
°C/W 800 ft/min
θ
LQFP 32 Thermal Resistance Junction to Case
23.0
26.3
°C/W MIL-SPEC 883E
JC
Method 1012.1
Table 4. Absolute Maximum Ratings(1)
Symbol
Characteristics
Min
–0.3
–0.3
–0.3
Max
Unit
V
Condition
V
Supply Voltage
3.9
CC
V
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage Temperature
V
V
+ 0.3
V
IN
CC
CC
V
+ 0.3
V
OUT
I
±20
mA
mA
°C
IN
I
±50
OUT
T
–65
125
S
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 5. DC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS Control Inputs (P_LOAD, S_LOAD, S_DATA, S_CLOCK, M[0:8], N[0:1], OE)
V
Input High Voltage
Input Low Voltage
2.0
V
+ 0.3
V
V
LVCMOS
LVCMOS
= V or GND
IH
CC
V
I
0.8
IL
(1)
Input Current
±200
µA
V
IN
IN
CC
(2)
Differential Clock Output F
OUT
(3)
V
Output High Voltage
V
V
–1.02
V
V
–0.74
V
V
LVPECL
LVPECL
OH
CC
CC
CC
(3)
V
Output Low Voltage
–1.95
–1.60
OL
CC
Test and Diagnosis Output TEST
(3)
V
Output High Voltage
2.0
V
V
I
I
= –0.8 mA
= 0.8 mA
OH
OH
OH
(3)
V
Output Low Voltage
0.55
OL
Supply Current
I
Maximum PLL Supply Current
Maximum Supply Current
20
mA
V
Pins
CC_PLL
CC_PLL
I
100
mA All V Pins
CC
CC
1. Inputs have pull-down resistors affecting the input current.
2. Outputs terminated 50 Ω to V = V – 2 V.
TT
CC
3. The MPC92429 TEST output levels are compatible to the MC12429 output levels.
MPC92429
Product Group
Freescale Semiconductor
4
Table 6. AC Characteristics (VCC = 3.3 V ± 5%, TA = 0°C to +70°C)(1)
Symbol
Characteristics
Min
10
Typ
Max
20
Unit
MHz
MHz
Condition
f
Crystal Interface Frequency Range
XTAL
(2)
f
VCO Frequency Range
200
400
VCO
MAX
f
Output Frequency
N = 00 (÷1)
N = 01 (÷2)
N = 10 (÷4)
N = 11 (÷8)
200
100
50
400
200
100
50
MHz
MHz
MHz
MHz
25
DC
Output Duty Cycle
45
0.05
0
50
55
0.3
10
%
ns
t , t
Output Rise/Fall Time
20% to 80%
r
f
(3)
f
Serial Interface Programming Clock Frequency
MHz
ns
S_CLOCK
t
Minimum Pulse Width
Setup Time
(S_LOAD, P_LOAD)
50
P,MIN
t
t
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to P_LOAD
20
20
20
ns
ns
ns
S
S
Hold Time
S_DATA to S_CLOCK
M, N to P_LOAD
20
20
ns
ns
t
Cycle-to-Cycle Jitter
N = 00 (÷1)
N = 01 (÷2)
N = 10 (÷4)
N = 11 (÷8)
90
ps
ps
ps
ps
JIT(CC)
130
160
190
t
Period Jitter
N = 00 (÷1)
N = 01 (÷2)
N = 10 (÷4)
N = 11 (÷8)
70
ps
ps
ps
ps
JIT(PER)
120
140
170
t
Maximum PLL Lock Time
10
ms
LOCK
1. AC characteristics apply for parallel output termination of 50 Ω to V
.
TT
2. The input frequency f
and the PLL feedback divider M must match the VCO frequency range: f
= f
x M.
XTAL
XTAL
VCO
3. The frequency of S_CLOCK is limited to 10 MHz in serial programming mode. S_CLOCK can be switched at higher frequencies when used
as test clock in test mode 6. See APPLICATIONS INFORMATION for more details.
MPC92429
Product Group
Freescale Semiconductor
5
PROGRAMMING INTERFACE
match the VCO frequency range of 200 to 400 MHz in order
Programming the MPC92429
to achieve stable PLL operation:
Programming the MPC92429 amounts to properly
configuring the internal PLL dividers to produce the desired
synthesized frequency at the output. The output frequency
can be represented by this formula:
MMIN = fVCO,MIN ÷ fXTAL and
(2)
(3)
MMAX = fVCO,MAX ÷ fXTAL
For instance, the use of a 16 MHz input frequency requires
the configuration of the PLL feedback divider between
M = 200 and M = 400. Table 7 shows the usable VCO
frequency and M divider range for other example input
frequencies. Assuming that a 16 MHz input frequency is
used, equation 1 reduces to:
FOUT = (fXTAL ÷ 16) x (M) ÷ (N)
(1)
where fXTAL is the crystal frequency, M is the PLL feedback-
divider and N is the PLL post-divider. The input frequency and
the selection of the feedback divider M is limited by the
VCO-frequency range. fXTAL and M must be configured to
F
OUT = M ÷ N
(4)
Table 7. MPC92429 Frequency Operating Range
VCO frequency for an crystal interface frequency of
Output frequency for f
= 16 MHz and for N =
XTAL
M
M[8:0]
10
12
14
16
18
20
1
2
4
8
160 010100000
170 010101010
180 010110100
190 010111110
200 011001000
210 011010010
220 011011100
230 011100110
240 011110000
250 011111010
260 100000100
270 100001110
280 100011000
290 100100010
300 100101100
310 100110110
320 101000000
200
212.5
225
202.5
213.75
225
237.5
250
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
360
370
380
390
400
200
210
220
230
240
250
260
270
280
290
300
310
320
330
340
350
360
370
380
390
400
100
105
110
115
120
125
130
135
140
145
150
155
160
165
170
175
180
185
190
195
200
50
52.5
55
25
236.25
247.5
258.75
270
262.5
275
26.25
27.5
28.75
30
201.25
210
287.5
300
57.5
60
218.75
227.5
236.25
245
281.25
292.5
303.75
315
312.5
325
62.5
65
31.25
32.5
33.75
35
202.5
210
337.5
350
67.5
70
217.5
225
253.75
262.5
271.25
280
326.25
337.5
348.75
360
362.5
375
72.5
75
36.25
37.5
38.75
40
232.5
240
387.5
400
77.5
80
200
330 101001010 206.25
340 101010100 212.5
350 101011110 218.75
360 101101000 225
370 101110010 231.25
380 101111100 237.5
390 110000110 243.75
400 110010000 250
410 110011010 256.25
420 110100100 262.5
430 110101110 268.75
440 110111000 275
247.5
255
288.75
297.5
306.25
315
371.25
382.5
393.75
82.5
85
41.25
42.5
43.75
45
262.5
270
87.5
90
277.5
285
323.75
332.5
341.25
350
92.5
95
46.25
47.5
48.75
50
292.5
300
97.5
100
307.5
315
358.75
367.5
376.25
385
322.5
330
450 111000010 281.25
510 111111110 318.75
337.5
382.5
393.75
MPC92429
Product Group
Freescale Semiconductor
6
Substituting N for the four available values for N (1, 2, 4, 8)
yields:
Example Frequency Calculation for an 16 MHz Input
Frequency
If an output frequency of 131 MHz was desired the
following steps would be taken to identify the appropriate M
and N values. According to Table 8, 131 MHz falls in the
frequency set by an value of 2 so N[1:0] = 01. For N = 2 the
output frequency is FOUT = M ÷ 2 and M = FOUT x 2.
Therefore M = 2 x 131 = 262, so M[8:0] = 100000110.
Following this procedure a user can generate any whole
frequency between 25 MHz and 400 MHz. Note than for
N > 2 fractional values of can be realized. The size of the
programmable frequency steps (and thus the indicator of the
fractional output frequencies achievable) will be equal to:
Table 8. Output Frequency Range for fXTAL = 16 MHz
N
F
F
Range
F
Step
OUT
OUT
OUT
1
0
0
1
1
0
0
1
0
1
Value
1
2
4
8
M
200 – 400 MHz
100 – 200 MHz
50 – 100 MHz
25 – 50 MHz
1 MHz
M÷2
M÷4
M÷8
500 kHz
250 kHz
125 kHz
fSTEP = fXTAL ÷ 16 ÷ N
(5)
APPLICATIONS INFORMATION
performance verification of the MPC92429 itself. However
Using the Parallel and Serial Interface
the PLL bypass mode may be of interest at the board level for
functional debug. When T[2:0] is set to 110 the MPC92429 is
placed in PLL bypass mode. In this mode the S_CLOCK input
is fed directly into the M and N dividers. The N divider drives
the FOUT differential pair and the M counter drives the TEST
output pin. In this mode the S_CLOCK input could be used for
low speed board level functional test or debug. Bypassing the
PLL and driving FOUT directly gives the user more control on
the test clocks sent through the clock tree. Figure 6 shows
the functional setup of the PLL bypass mode. Because the
S_CLOCK is a CMOS level the input frequency is limited to
200 MHz. This means the fastest the FOUT pin can be toggled
via the S_CLOCK is 100 MHz as the divide ratio of the
Post-PLL divider is 2 (if N = 1). Note that the M counter output
on the TEST output will not be a 50% duty cycle.
The M and N counters can be loaded either through a
parallel or serial interface. The parallel interface is controlled
via the P_LOAD signal such that a LOW-to-HIGH transition
will latch the information present on the M[8:0] and N[1:0]
inputs into the M and N counters. When the P_LOAD signal
is LOW the input latches will be transparent and any changes
on the M[8:0] and N[1:0] inputs will affect the FOUT output
pair. To use the serial port the S_CLOCK signal samples the
information on the S_DATA line and loads it into a 14 bit shift
register. Note that the P_LOAD signal must be HIGH for the
serial load operation to function. The Test register is loaded
with the first three bits, the N register with the next two and
the M register with the final eight bits of the data stream on
the S_DATA input. For each register the most significant bit is
loaded first (T2, N1 and M8). A pulse on the S_LOAD pin after
the shift register is fully loaded will transfer the divide values
into the counters. The HIGH-to-LOW transition on the
S_LOAD input will latch the new divide values into the
counters. Figure 4 illustrates the timing diagram for both a
parallel and a serial load of the MPC92429 synthesizer.
M[8:0] and N[1:0] are normally specified once at power-up
through the parallel interface, and then possibly again
through the serial interface. This approach allows the
application to come up at one frequency and then change or
fine-tune the clock as the ability to control the serial interface
becomes available.
Table 9. Test and Debug Configuration for TEST
T[2:0]
TEST Output
T2
0
T1
0
T0
0
(1)
14-bit shift register out
Logic 1
0
0
1
0
1
0
f
÷ 16
XTAL
0
1
1
M-Counter out
FOUT
1
0
0
1
0
1
Logic 0
Using the Test and Diagnosis Output TEST
1
1
0
M-Counter out in PLL-bypass mode
The TEST output provides visibility for one of the several
internal nodes as determined by the T[2:0] bits in the serial
configuration stream. It is not configurable through the
parallel interface. Although it is possible to select the node
that represents FOUT, the CMOS output is not able to toggle
fast enough for higher output frequencies and should only be
used for test and diagnosis. The T2, T1 and T0 control bits
are preset to ‘000' when P_LOAD is LOW so that the PECL
FOUT outputs are as jitter-free as possible. Any active signal
on the TEST output pin will have detrimental affects on the
jitter of the PECL output pair. In normal operations, jitter
specifications are only guaranteed if the TEST output is
static. The serial configuration port can be used to select one
of the alternate functions for this pin. Most of the signals
available on the TEST output pin are useful only for
1
1
1
FOUT ÷ 4
1. Clocked out at the rate of S_CLOCK.
Table 10. Debug Configuration for PLL Bypass(1)
Output
Configuration
F
S_CLOCK ÷ N
OUT
(2)
TEST
M-Counter out
1. T[2:0] = 110. AC specifications do not apply in PLL bypass
mode.
2. Clocked out at the rate of S_CLOCK÷(4⋅N)
MPC92429
Product Group
Freescale Semiconductor
7
S_CLOCK
S_DATA
S_LOAD
M0
T2 T1 T0 N1 N0 M8 M7 M6 M5 M4 M3 M2 M1
First
Last
Bit
Bit
M[8:0]
N[1:0]
M,
N
P_LOAD
Figure 4. Serial Interface Timing Diagram
Power Supply Filtering
R
= 10-15 Ω
The MPC92429 is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Random noise on the VCC_PLL pin impacts the device
characteristics. The MPC92429 provides separate power
supplies for the digital circuitry (VCC) and the internal PLL
(VCC_PLL) of the device. The purpose of this design technique
is to try and isolate the high switching noise digital outputs
from the relatively sensitive internal analog phase-locked
loop. In a controlled environment such as an evaluation
board, this level of isolation is sufficient. However, in a digital
system environment where it is more difficult to minimize
noise on the power supplies a second level of isolation may
be required. The simplest form of isolation is a power supply
filter on the VCC_PLL pin for the MPC92429. Figure 5
illustrates a typical power supply filter scheme. The
MPC92429 is most susceptible to noise with spectral content
in the 1 kHz to 1 MHz range. Therefore, the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop that
will be seen between the VCC supply and the MPC92429 pin
of the MPC92429. From the data sheet, the VCC_PLL current
(the current sourced through the VCC_PLL pin) is maximum
20 mA, assuming that a minimum of 2.835 V must be
maintained on the VCC_PLL pin. The resistor shown in
Figure 5 must have a resistance of 10-15 Ω to meet the
voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20 kHz. As the noise
frequency crosses the series resonant point of an individual
capacitor its overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
F
V
V
CC_PLL
CC
C
C
= 22 µF
2
F
MPC92429
V
CC
C , C = 0.01...0.1 µF
C
1
2
1
Figure 5. VCC_PLL Power Supply Filter
Layout Recommendations
The MPC92429 provides sub-nanosecond output edge
rates and thus a good power supply bypassing scheme is a
must. Figure 6 shows a representative board layout for the
MPC92429. There exists many different potential board
layouts and the one pictured is but one. The important aspect
of the layout in Figure 6 is the low impedance connections
between VCC and GND for the bypass capacitors. Combining
good quality general purpose chip capacitors with good PCB
layout techniques will produce effective capacitor resonances
at frequencies adequate to supply the instantaneous
switching current for the MPC92429 outputs. It is imperative
that low inductance chip capacitors are used; it is equally
important that the board layout does not introduce back all of
the inductance saved by using the leadless capacitors. Thin
interconnect traces between the capacitor and the power
plane should be avoided and multiple large vias should be
used to tie the capacitors to the buried power planes. Fat
interconnect and large vias will help to minimize layout
induced inductance and thus maximize the series resonant
point of the bypass capacitors. Note the dotted lines circling
the crystal oscillator connection to the device. The oscillator
is a series resonant circuit and the voltage amplitude across
the crystal is relatively small. It is imperative that no actively
switching signals cross under the crystal as crosstalk energy
coupled to these lines could significantly impact the jitter of
the device. Special attention should be paid to the layout of
the crystal to ensure a stable, jitter free interface between the
crystal and the on-board oscillator. Although the MPC92429
has several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL), there still may be applications in which
bandwidth of the PLL. Generally, the resistor/capacitor filter
will be cheaper, easier to implement and provide an adequate
level of supply filtering. A higher level of attenuation can be
achieved by replacing the resistor with an appropriate valued
inductor. A 1000 µH choke will show a significant impedance
at 10 kHz frequencies and above. Because of the current
draw and the voltage that must be maintained on the VCC_PLL
pin, a low DC resistance inductor is required (less than 15 Ω).
MPC92429
Product Group
8
Freescale Semiconductor
overall performance is being degraded due to system power
supply noise. The power supply filter and bypass schemes
discussed in this section should be adequate to eliminate
power supply noise related problems in most designs.
XTAL_IN and XTAL_OUT pins to reduce crosstalk of active
signals into the oscillator. Short and wide traces further
reduce parasitic inductance and resistance. It is further
recommended to guard the crystal circuit by placing a ground
ring around the traces and oscillator components. See
Table 11 for recommended crystal specifications.
C1
C1
Table 11. Recommended Crystal Specifications
Parameter
Value
Fundamental AT Cut
Parallel
Crystal Cut
Resonance Mode
Crystal Frequency
Shunt Capacitance C
10–20 MHz
5–7 pF
1
0
CF
C2
Load Capacitance C
10 pF
L
Equivalent Series Resistance ESR
20–60 Ω
As an alternative to parallel resonance mode crystals, the
oscillator also works with crystals specified in the series
resonance mode. With series resonance crystals, the
oscillator frequency and the synthesized output frequency of
the MPC92429 will be a approximately 350-400 ppm higher
than using crystals specified for parallel frequency mode.
This is applicable to applications using the MPC92429 in
sockets designed for the pin and function compatible
MC12429 synthesizer, which has an oscillator using the
crystal in its series resonance mode. Table 12 shows the
recommended specifications for series resonance mode
crystals.
XTAL
= V
CC
= GND
= Via
Figure 6. PCB Board Layout Recommendation
for the PLCC28 Package
The On-Chip Crystal Oscillator
The MPC92429 features an integrated on-chip crystal
oscillator to minimize system implementation cost. The
integrated oscillator is a Pierce-type that uses the crystal in
its parallel resonance mode. It is recommended to use a 10
to 20 MHz crystal with a load specification of CL = 10 pF.
Crystals with a load specification of CL = 20 pF may be used
at the expense of an slightly higher frequency than specified
for the crystal. Externally connected capacitors on both the
XTAL_IN and XTAL_OUT pins are not required but can be
used to fine-tune the crystal frequency as desired.
Table 12. Alternative Crystal Specifications
Parameter
Value
Fundamental AT Cut
Series
Crystal Cut
Resonance Mode
Crystal Frequency
Shunt Capacitance C
10–20 MHz
5–7 pF
0
The crystal, the trace and optional capacitors should be
placed on the board as close as possible to the MPC92429
Equivalent Series Resistance ESR
50–80 Ω
MPC92429
Product Group
Freescale Semiconductor
9
PACKAGE DIMENSIONS
M
S
S
S
0.007 (0.180)
T
L-M
N
B
Y BRK
D
-N-
M
S
N
0.007 (0.180)
T L-M
U
Z
-M-
-L-
W
D
S
S
S
N
0.010 (0.250)
T L-M
X
G1
V
28
1
VIEW D-D
M
S
S
N
A
0.007 (0.180)
0.007 (0.180)
T L-M
M
S
S
N
0.007 (0.180)
T
L-M
H
Z
M
S
S
N
T
L-M
R
C
K1
E
0.004 (0.100)
K
G
SEATING
PLANE
-T-
J
M
S
S
N
0.007 (0.180)
VIEW S
T L-M
F
VIEW S
G1
S
S
S
N
0.010 (0.250)
T L-M
NOTES:
1. DATUMS -L-, -M-, AND -N- DETERMINED
WHERE TOP OF LEAD SHOULDER EXISTS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DEMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASITC BODY.
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
INCHES
MILLIMETERS
DIM
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
G1
K1
MIN
MAX MIN
0.495 12.32
0.495 12.32
MAX
12.57
12.57
4.57
0.485
0.485
0.165
0.090
0.013
0.180
0.110
0.019
4.20
2.29
0.33
2.79
0.48
0.050 BSC
1.27 BSC
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
---
0.032
---
0.66
0.51
0.64
0.81
---
---
---
0.456 11.43
0.456 11.43
11.58
11.58
1.21
1.21
1.42
0.50
10˚
0.048
0.048
0.056
0.020
10˚
1.07
1.07
1.07
---
2˚
2˚
0.410
0.040
0.430 10.42
--- 1.02
10.92
---
CASE 776-02
ISSUE D
28-LEAD PLCC PACKAGE
MPC92429
Product Group
Freescale Semiconductor
10
PACKAGE DIMENSIONS
4X
0.20
H
A-B D
6
D1
3
A, B, D
e/2
D1/2
32
PIN 1 INDEX
1
25
F
F
A
B
E1/2
6
E1
E
4
DETAIL G
E/2
DETAIL G
8
17
NOTES:
9
7
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
D
4
D/2
4X
D
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
0.20
C
A-B D
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08-mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07-mm.
H
28X e
32X
0.1 C
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1-mm AND
0.25-mm FROM THE LEAD TIP.
SEATING
PLANE
C
DETAIL AD
BASE
METAL
PLATING
b1
c
c1
MILLIMETERS
DIM
A
A1
A2
b
b1
c
c1
D
MIN
1.40
0.05
1.35
0.30
0.30
0.09
0.09
MAX
1.60
0.15
1.45
0.45
0.40
0.20
0.16
b
5
8
8X (θ1˚)
M
0.20
C
A-B
D
R R2
SECTION F-F
R R1
9.00 BSC
D1
e
E
E1
L
L1
q
q1
R1
R2
S
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
A2
A
0.25
GAUGE PLANE
0.50
1.00 REF
0˚ 7˚
12 REF
0.70
(S)
A1
L
θ˚
0.08
0.08
0.20
---
(L1)
0.20 REF
DETAIL AD
CASE 873A-03
ISSUE B
32-LEAD LQFP PACKAGE
MPC92429
Product Group
Freescale Semiconductor
11
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MPC92429
Rev. 3
05/2005
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