MPC92433FAR2_技术文档

MPC92433

Rev 2, 06/2005

Freescale Semiconductor

Technical Data

1428 MHz Dual Output LVPECL

Clock Synthesizer

MPC92433

The MPC92433 is a 3.3 V compatible, PLL based clock synthesizer targeted

for high performance clock generation in mid-range to high-performance

telecom, networking, and computing applications. With output frequencies from

42.50 MHz to 1428 MHz and the support of two differential PECL output signals,

the device meets the needs of the most demanding clock applications.

1428 MHz LOW VOLTAGE

CLOCK SYNTHESIZER

Features

•

42.50 MHz to 1428 MHz synthesized clock output signal

Two differential, LVPECL-compatible high-frequency outputs

Output frequency programmable through 2-wire I2C bus or parallel interface

On-chip crystal oscillator for reference frequency generation

Alternative LVCMOS compatible reference clock input

Synchronous clock stop functionality for both outputs

LOCK indicator output (LVCMOS)

(1)

FA SUFFIX

48-LEAD LQFP PACKAGE

CASE 932-03

LVCMOS compatible control inputs

Fully integrated PLL

3.3 V power supply

48-lead LQFP

(2)

AE SUFFIX

48-lead Pb-free package available

48-LEAD LQFP PACKAGE

Pb-FREE PACKAGE

CASE 932-03

SiGe Technology

Ambient temperature range: –40°C to +85°C

Typical Applications

•

Programmable clock source for server, computing, and telecommunication systems

Frequency margining

Oscillator replacement

The MPC92433 is a programmable high-frequency clock source (clock synthesizer). The internal PLL generates a high-

frequency output signal based on a low-frequency reference signal. The frequency of the output signal is programmable and can

be changed on the fly for frequency margining purposes.

The internal crystal oscillator uses the external quartz crystal as the basis of its frequency reference. Alternatively, a LVCMOS

compatible clock signal can be used as a PLL reference signal. The frequency of the internal crystal oscillator is divided by a

selectable divider and then multiplied by the PLL. The VCO within the PLL operates over a range of 1360 to 2856 MHz. Its output

is scaled by a divider that is configured by either the I²C or parallel interfaces. The crystal oscillator frequency fXTAL, the PLL

pre-divider P, the feedback-divider M, and the PLL post-divider N determine the output frequency. The feedback path of the PLL

is internal.

The PLL post-divider N is configured through either the I²C or the parallel interfaces, and can provide one of seven division

ratios (2, 4, 6, 8, 12, 16, 32). This divider extends the performance of the part while providing a 50 Ω duty cycle. The high-

frequency outputs, Q_Aand Q_B, are differential and are capable of driving a pair of transmission lines terminated 50 Ω to

V_CC– 2.0 V. The second high-frequency output, Q_B, can be configured to run at either 1x or 1/2x of the clock frequency or the

first output (Q_A). The positive supply voltage for the internal PLL is separated from the power supply for the core logic and output

drivers to minimize noise induced jitter.

The configuration logic has two sections: I²C and parallel. The parallel interface uses the values at the M[9:0], NA[2:0], NB,

and P parallel inputs to configure the internal PLL dividers. The parallel programming interface has priority over the serial I²C

interface. The serial interface is I²C compatible and provides read and write access to the internal PLL configuration registers.

The lock state of the PLL is indicated by the LVCMOS-compatible LOCK output.

1. FA suffix: leaded terminations.

2. AE suffix: lead-free, EPP and RoHS-compliant.

f

QA

QB

÷NA

f

VCO

REF_CLK

XTAL1

PLL

÷M

÷P

f

REF

XTAL

f

XTAL2

REF_SEL

TEST_EN

QB

÷NB

SDA

SCL

PLL

Configuration

Registers

ADR[1:0]

PLOAD

2

LOCK

I C Control

M[9:0]

NA[2:0]

NB

P

CLK_STOPx

BYPASS

MR

Figure 1. MPC92433–Generic Logic Diagram

36 35 34

33 32 31 30 29 28

27 26 25

24

23

22

21

20

19

18

GND

NA2

M9

37

38

39

40

41

M8

M7

M6

M5

NA1

NA0

PLOAD

V

42

43

44

GND

M4

CC

MPC92433

MR

17

16

15

14

SDA

SCL

M3

M2

45

ADR1

ADR0

P

M1

M0

46

47

48

13

V

CC

1

2

3

4

5

6

7

8

9

10 11 12

It is recommended to use an external

RC filter for the analog V supply

CC_PLL

pin. Please see the application section

for details.

Figure 2. 48-Lead Package Pinout (Top View)

MPC92433

Advanced Clock Drivers Devices

Freescale Semiconductor

2

Table 1. Signal Configuration

XTAL1, XTAL2

REF_CLK

REF_SEL

QA

I/O

Input

Type

Function

Analog

Crystal oscillator interface

PLL external reference input

Selects the reference clock input

High frequency clock output

PLL lock indicator

Input

Output

Input

I/O

LVCMOS

Differential LVPECL

LVCMOS

QB

LOCK

M[9:0]

LVCMOS

PLL feedback divider configuration

PLL post-divider configuration for output QA

PLL post-divider configuration for output QB

PLL pre-divider configuration

NA[2:0]

NB

LVCMOS

P

LVCMOS

P_LOAD

SDA

LVCMOS

Selects the programming interface

2

LVCMOS

I C data

2

SCL

Input

LVCMOS

I C clock

2

ADR[1:0]

BYPASS

Selectable two bits of the I C slave address

Selects the static circuit bypass mode

Factory test mode enable. This input must be set to logic low level in all

applications of the device.

TEST_EN

Input

LVCMOS

CLK_STOPx

MR

Input

LVCMOS

Ground

Output Qx disable in logic low state

Device master reset

Input

GND

Supply

Negative power supply

Positive power supply for the PLL (analog power supply). It is recommended

V

Supply

CC_PLL

CC

to use an external RC filter for the analog power supply pin V

.

CC_PLL

V

Positive power supply for I/O and core

CC

MPC92433

Advanced Clock Drivers Devices

Freescale Semiconductor

3

Table 2. Function Table

(1)

Control

Inputs

0

1

Default

REF_SEL

1

Selects REF_CLK input as PLL reference clock

Selects the XTAL interface as PLL reference

clock

(2)

M[9:0]

PLL feedback divider (10-bit) parallel programming interface

01 1111 0100b

NA[2:0]

NB

010

0

PLL post-divider parallel programming interface. See Table 9

PLL pre-divider parallel programming interface. See Table 8

P

1

2

PLOAD

0

Selects the parallel programming interface. The

internal PLL divider settings (M, NA, NB and P) are

equal to the setting of the hardware pins. Leaving the

M, NA, NB and P pins open (floating) results in a

Selects the serial (I C) programming interface.

The internal PLL divider settings (M, NA, NB and

P) are set and read through the serial interface.

default PLL configuration with f

= 250 MHz. See

OUT

application/programming section.

ADR[1:0]

SDA, SCL

BYPASS

00

1

Address bit = 0

Address bit = 1

See Programming the MPC92433

PLL function bypassed

PLL function enabled

f

=f

÷ N and

f

= (f

÷ P) · M ÷ N and

A

QA REF

A

QA

QB

REF

f

=f

÷ (N · N )

f

= (f

÷ P) · M ÷ (N · N )

A B

QB REF

A

B

TEST_EN

0

1

Application mode. Test mode disabled.

Factory test mode is enabled

CLK_STOPx

Output Qx is disabled in logic low state. Synchronous Output Qx is synchronously enabled

disable is only guaranteed if NB = 0.

MR

The device is reset. The output frequency is zero and The PLL attempts to lock to the reference signal.

the outputs are asynchronously forced to logic low

state.

The t

specification applies.

LOCK

After releasing reset (upon the rising edge of MR and

independent on the state of PLOAD), the MPC92433

reads the parallel interface (M, NA, NB and P) to

acquire a valid startup frequency configuration. See

application/programming section.

Outputs

LOCK

PLL is not locked

PLL is frequency locked

1. Default states are set by internal input pull-up or pull-down resistors of 75 kΩ.

2. If f = 16 MHz, the default configuration will result in an output frequency of 250 MHz.

REF

MPC92433

Advanced Clock Drivers Devices

Freescale Semiconductor

4

Table 3. General Specifications

Symbol

Characteristics

Min

Typ

– 2

Max

Unit

V

Condition

V

Output Termination Voltage

ESD Protection (Machine Model)

ESD Protection (Human Body Model)

Latch-Up Immunity

V

TT

CC

MM

HBM

LU

200

2000

200

V

mA

pF

C

Input Capacitance

4.0

Inputs

IN

θ

LQFP 48 Thermal Resistance Junction to Ambient

JESD 51-3, single layer test board

JA

69

64

°C/W Natural convection

°C/W 200 ft/min

JESD 51-6, 2S2P multilayer test board

53

50

°C/W Natural convection

°C/W 200 ft/min

θ

LQFP 48 Thermal Resistance Junction to Case

TBD

°C/W MIL-SPEC 883E

JC

Method 1012.1

Table 4. Absolute Maximum Ratings⁽¹⁾

Symbol

Characteristics

Min

–0.3

Max

Unit

V

Condition

V

Supply Voltage

3.9

CC

(2)

V

DC Input Voltage

V

+ 0.3

V

IN

CC

V

DC Output Voltage

DC Input Current

+ 0.3

V

OUT

I

±20

mA

°C

IN

I

DC Output Current

Storage Temperature

±50

OUT

T

–65

125

S

1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these

conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated

conditions is not implied.

2. All input pins including SDA and SCL pins.

MPC92433

Advanced Clock Drivers Devices

Freescale Semiconductor

5

Table 5. DC Characteristics (V_CC= 3.3 V ± 5%, T_J= –40°C to +85°C)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

LVCMOS Control Inputs (M[9:0], N[2:0], ADDR[1:0], NB, P, CLK_STOPx, BYPASS, MR, REF_SEL, TEST_EN, PLOAD)

V

Input High Voltage

Input Low Voltage

2.0

—

V

+ 0.3

CC

V

LVCMOS

= V or GND

IH

V

0.8

±200

IL

(1)

I

—

µA

V

IN

Input Current

CC

2

I C Inputs (SCL, SDA)

V

Input High Voltage

Input Low Voltage

Input Current

2.0

—

+ 0.3

CC

V

LVCMOS

IH

V

0.8

IL

I

—

±10

µA

IN

LVCMOS Output (LOCK)

V

Output High Voltage

Output Low Voltage

2.4

—

V

I

= –4 mA

= 4 mA

OH

OL

V

0.4

OL

2

I C Open-Drain Output (SDA)

Input Low Voltage

V

—

0.4

V

I

= 4 mA

OL

(2)

Differential Clock Output QA, QB

V

Output High Voltage

Output Low Voltage

V

– 1.05

—

V

– 0.74

V

LVPECL

OH

CC

V

– 1.95

V

– 1.60

OL

CC

V

Output Peak-to-Peak Voltage

0.5

0.6

1.0

O(P-P)

Supply current

I

Maximum PLL Supply Current

Maximum Supply Current

—

10

mA

V

Pins

CC_PLL

I

150

All V Pins

CC

1. Inputs have pull-down resistors affecting the input current.

2. Outputs terminated 50 Ω to V = V – 2 V.

TT

CC

MPC92433

Advanced Clock Drivers Devices

Freescale Semiconductor

6

Table 6. AC Characteristics (V_CC= 3.3 V ± 5%, T_J= –40°C to +85°C^{(1) (2)}

Symbol

Characteristics

Min

15

Typ

Max

20

Unit

MHz

Condition

f

Crystal Interface Frequency Range

FREF_EXT Reference Frequency Range

16

XTAL

f

15

20

REF

VCO

MAX

(3)

f

VCO Frequency Range

1360

2856

(4)

f

Output Frequency

N= ÷2

N= ÷4

N= ÷6

680

340

226.67

170

113.30

178.50

42.50

1428

714

476

357

238

MHz

N= ÷8

N= ÷12

N= ÷16

N= ÷32

178.50

89.25

2

f

Serial Interface (I C) Clock Frequency

0

0.4

MHz

ns

SCL

t

Minimum Pulse Width

Output Duty Cycle

(P_LOAD)

50

45

P,MIN

DC

50

55

%

t

Output-to-Output Skew

NB=0 (f = f )

QB

38

96

ps

SK(O)

QA

NB=1 (f = 2· f

)

QA

QB

t , t

Output Rise/Fall Time (QA, QB)

0.05

0.3

ns

20% to 80%

C = 400 pF

r

f

t , t

Output Rise/Fall Time (SDA)

250

r

f

L

t

Output Enable Time (CLKSTOPx to QA, QB)

0

2 · T

T

= Output period

P_EN

Qx

t

Output Disable Time (CLKSTOPx to QA, QB)

1.5 · T

T

P_DIS

Qx

(5)

t

Cycle-to-Cycle Jitter (RMS)

N= ÷2, ÷4, ÷6, ÷8

N= ÷12

15

20

30

ps

JIT(CC)

N= ÷16, ÷32

(6)

t

Period Jitter (RMS)

N= ÷2

N= ÷4

N= ÷6

8

ps

JIT(PER)

10

12

13

17

23

29

N= ÷8

N= ÷12

N= ÷16

N= ÷32

N

Number of missing reference clock cycles to

declare an out of LOCK condition

2

REF(UNLOCK)

(7)

t

Maximum PLL Lock Time

10

ms

LOCK

1. AC specifications are subject to change.

2. AC characteristics apply for parallel output termination of 50 Ω to V

.

TT

3. The input frequency f

, the PLL divider M and P must match the VCO frequency range: f

= f

· M ÷ P. The feedback divider M is

XTAL

VCO

XTAL

limited to 170 <= M <= 357 (for P=2) and 340 <= M <= 714 (for P=4) for stable PLL operation.

4. Output frequency for Q , Q if N =0. With N =1 the Q output frequency is half of the Q output frequency.

A

B

A

5. Maximum cycle jitter measured at the lowest VCO frequency. Refer to Figure 8 for the cycle jitter vs. frequency characterisitics.

6. Maximum period jitter measured at the lowest VCO frequency. Refer to Figure 9 for the period jitter vs. frequency characterisitics.

7. See the LOCK Detect section on page 13.

MPC92433

Advanced Clock Drivers Devices

Freescale Semiconductor

7

Output Frequency Configuration

The MPC92433 is a programmable frequency source

(synthesizer) and supports an output frequency range of

42.5 – 1428 MHz. The output frequency f_OUTis a function of

the reference frequency f_REFand the three internal PLL

dividers P, M, and N. f_OUTcan be represented by this formula:

Table 7. Frequency Ranges (f_REF=16 MHz)

f

(Q ) [MHz]

N

A

M

P

2

4

2

4

2

4

2

4

2

4

2

4

2

4

G [MHz]

4

OUT

A

170-357

340-714

170-357

340-714

170-357

340-714

170-357

340-714

170-357

340-714

170-357

340-714

170-357

340-714

N =2

680–1428

340–714

A

2

N =4

f

_OUT= (f_REF÷ P) · M ÷ (N_A, _B)

(1)

A

1

1.33

0.66

1

The M, N and P dividers require a configuration by the user

to achieve the desired output frequency. The output divider,

N_A,determines the achievable output frequency range (see

Table 7). The PLL feedback-divider M is the frequency

multiplication factor and the main variable for frequency

synthesis. For a given reference frequency f_REF, the PLL

feedback-divider M must be configured to match the

specified VCO frequency range in order to achieve a valid

PLL configuration:

N =6

226.67–476

170–357

A

N =8

A

0.5

0.66

0.33

0.5

N =12

113.33–238

85–178.5

A

N =16

A

0.25

0.125

f

_VCO= (f_REF÷ P) · M and

(2)

(3)

N =32

42.5–89.25

A

1360 ≤ f_VCO≤ 2856

Example Output Frequency Configuration

The output frequency may be changed at any time by

changing the value of the PLL feedback divider M. The

smallest possible output frequency change is the synthesizer

granularity G (difference in f_OUTwhen incrementing or

decrementing M). At a given reference frequency, G is a

function of the PLL pre-divider P and post-divider N:

If a reference frequency of 16 MHz is available, an output

frequency at Q_Aof 250 MHz and a small frequency

granularity is desired, the following steps would be taken to

identify the appropriate P, M, and N configuration:

1. Use Table 7 to select the output divider, N_A, that

matches the desired output frequency or frequency

range. According to Table 7, a target output frequency

of 250 MHz falls in the f_OUTrange of 170 to 357 MHz

G = f_REF÷ (P · N_A,B

)

(4)

The N_Bdivider configuration determines if the output Q_B

and requires to set N_A= 8

generates a 1:1 or 2:1 frequency copy of the Q_Aoutput signal.

The purpose of the PLL pre-divider P is to situated the PLL

into the specified VCO frequency range f_VCO(in combination

with M). For a given output frequency, P = 4 results in a

smaller output frequency granularity G, P = 2 results a larger

output frequency granularity G and also increases the PLL

bandwidth compared to the P = 2 setting.

The following example illustrates the output frequency

range of the MPC92433 using a 16-MHz reference

frequency.

2. Calculate the VCO frequency f_VCO= f_OUT· N_A, which is

2000 MHz in this example.

3. Determine the PLL feedback divider: M = f_VCO÷ P.

The smallest possible output granularity in this example

calculation is 500 kHz (set P = 4). M calculates to a

value of 2000 ÷ 4 = 500.

4. Configure the MPC92433 with the obtained settings:

M[9:0] = 0111110100b (binary number for M=500)

N_A[2:0] = 010

P = 1

(÷8 divider, see Table 9)

(÷4 divider, see Table 8)

N_B= 0

(f_{OUT, QB}= f_{OUT, QA})

5. Use either parallel or serial interface to apply the

setting. The I²C configuration bytes for this example

are:

PLL_H=01010010b and PLL_L=11110100b.

See Table 13 and Table 14 for register maps.

MPC92433

Advanced Clock Drivers Devices

Freescale Semiconductor

8

PLL Divider Configuration

Table 8. Pre-PLL Divider P

Upon startup, when the device reset signal is released

(rising edge of the MR signal), the device reads its startup

configuration through the parallel interface and independent

on the state of PLOAD. It is recommended to provide a valid

PLL configuration for startup. If the parallel interface pins are

left open, a default PLL configuration will be loaded. After the

low-to-high transition of PLOAD, the configuration pins have

no more effect and the configuration registers are made

accessible through the serial interface.

P

Value

0

f

÷ 2

REF

1

÷ 4

Table 9. Post-PLL Divider N_Aand N_B

Table 10. Feedback Divider Configuration

N

f

(Q )

f

(Q )

A2

A1

A0

B

OUT

A

OUT

B

Feedback

Divider M

9

8

7

6

5

4

3

2

1

0

f

÷ 2

÷ 32

÷ 8

f

÷ 2

÷ 32

÷ 8

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

VCO

0

1

VCO

M9 M8 M7 M6 M5 M4 M3 M2 M1 M0

f

VCO

Default

0

1

0

1

0

÷ 12

÷ 4

÷ 12

÷ 4

VCO

f

VCO

f

÷ 6

f

÷ 6

VCO

Table 11. PLL Pre/Post Divider Configuration (N, P)

f

÷ 16

f

÷ 16

VCO

Post-D.

NA

2

1

0

Post-D. NB

NB

Pre-D.

P

n/a

f

÷ 2

f

÷ 4

VCO

NA2 NA1 NA0

NB

0

P

1

n/a

Default

0

1

0

Default

f

÷ 8

f

÷ 16

VCO

Using the I²C Interface

n/a

f

÷ 4

÷ 6

f

÷ 8

VCO

PLOAD = 1 enables the programming and monitoring of

the internal registers through the I²C interface. Device

register access (write and read) is possible through the 2-wire

interface using SDA (configuration data) and SCL

(configuration clock) signals. The MPC92433 acts as a slave

device at the I²C bus. For further information on I²C it is

recommended to refer to the I²C bus specification (version

2.1).

f

÷ 12

÷ 32

VCO

f

÷ 16

f

VCO

n/a

Programming the MPC92433

The MPC92433 has a parallel and a serial configuration

interface. The purpose of the parallel interface is to directly

configure the PLL dividers through hardware pins without the

overhead of a serial protocol. At device startup, the device

always obtains an initial PLL frequency configuration through

the parallel interface. The parallel interface does not support

reading the PLL configuration.

PLOAD = 0 disables the I²C-write-access to the configura-

tion registers and any data written into the register is ignored.

However, the MPC92433 is still visible at the I²C interface

and I²C transfers are acknowledged by the device. Read-ac-

cess to the internal registers during PLOAD = 0 (parallel pro-

gramming mode) is supported.

Note that the device automatically obtains a configuration

using the parallel interface upon the release of the device

reset (rising edge of MR) and independent on the state of

PLOAD. Changing the state of the PLOAD input is not

supported when the device performs any transactions on the

I²C interface.

The serial interface is I²C compatible. It allows reading and

writing devices settings by accessing internal device

registers. The serial interface is designed for host-controller

access to the synthesizer frequency settings for instance in

frequency-margining applications.

Programming Model and Register Set

Using the Parallel Interface

The synthesizer contains two fully accessible configuration

registers (PLL_L and PLL_H) and a write-only command

register (CMD). Programming the synthesizer frequency

through the I²C interface requires two steps: 1) writing a valid

PLL configuration to the configuration registers and 2)

loading the registers into the PLL by an I²C command. The

PLL frequency is affected as a result of the second step.

This two-step procedure can be performed by a single I²C

transaction or by multiple, independent I²C transactions. An

alternative way to achieve small PLL frequency changes is to

use the increment or decrement commands of the

The parallel interface supports write-access to the PLL

frequency setting directly through 15 configuration pins (P,

M[9:0], NA[2:0], and NB). The parallel interface must be

enabled by setting PLOAD to logic low level. During

PLOAD = 0, any change of the logical state of the P, M[9:0],

NA[2:0], and NB pins will immediately affect the internal PLL

divider settings, resulting in a change of the internal VCO-

frequency and the output frequency. The parallel interface

mode disables the I²C write-access to the internal registers;

however, I²C read-access to the internal configuration

registers is enabled.

MPC92433

Advanced Clock Drivers Devices

Freescale Semiconductor

9

synthesizer, which have an immediate effect on the PLL

frequency.

Register Maps

Table 12. Configuration Registers

Address Name

Content

PLL_L Least significant 8 bits of M

PLL_H Most significant 2 bits of M, P, N ,

Access

R/W

Synthesizer – PLL

0x00

0x01

Configuration Latches

P

N

M

R/W

A

LOAD/GET

N , and lock state

B

0xF0

CMD Command register (write only)

W only

2

PLL_L (R/W) PLL_H (R/W) CMD (W)

0x00 0x01 0xF0

I C Registers

Register 0x00 (PLL_L) contains the least significant bits of

the PLL feedback divider M.

2

I C Access

Table 13. PLL_L (0x00, R/W) Register

Figure 3. I²C Mode Register Set

Bit

7

6

5

4

3

2

1

0

Name M7

M6

M5

M4

M3

M2

M1

M0

Figure 3 illustrates the synthesizer register set. PLL_L and

PLL_H store a PLL configuration and are fully accessible

(Read/Write) by the I²C bus. CMD (Write only) accepts

commands (LOAD, GET, INC, DEC) to update registers and

for direct PLL frequency changes.

Register content:

M[7:0] PLL feedback-divider M, bits 7–0

Register 0x01 (PLL_H) contains the two most significant

bits of the PLL feedback divider M, four bits to control the PLL

post-dividers N and the PLL pre-divider P. The bit 0 in PLL_H

register indicates the lock condition of the PLL and is set by

the synthesizer automatically. The LOCK state is a copy of

the PLL lock signal output (LOCK). A write-access to LOCK

has no effect.

Set the synthesizer frequency:

1) Write the PLL_L and PLL_H registers with a new

configuration (see Table 13 and Table 14 for register

maps)

2) Write the LOAD command to update the PLL dividers

by the current PLL_L, PLL_H content.

Table 14. PLL_H (0x01, R/W) Register

Bit

7

6

5

4

3

2

1

0

Read the synthesizer frequency:

Name M9

M8

NA2 NA1 NA0

NB

P

LOCK

1) Write the GET commands to update the PLL_L,

PLL_H registers by the PLL divider setting

Register content:

M[9:8]

2) Read the PLL_L, PLL_H registers through I²C

PLL feedback-divider M, bits 9–8

NA[2:0] PLL post-divider N_A, see Table 9

Change the synthesizer frequency in small steps:

NB

PLL post-divider N_B, see Table 9

PLL pre-divider P, see Table 8

P

1) Write the INC or DEC command to change the PLL

frequency immediately. Repeat at any time if desired.

LOCK

Copy of LOCK output signal (read-only)

Note that the LOAD command is required to update the

PLL dividers by the content of both PLL_L and PLL_H

registers.

LOAD and GET are inverse command to each other.

LOAD updates the PLL dividers and GET updates the

configuration registers. A fast and convenient way to change

the PLL frequency is to use the INC (increment M) and DEC

(decrement M) commands of the synthesizer. INC (DEC)

directly increments (decrements) the PLL-feedback divider M

and immediately changes the PLL frequency by the smallest

step G (see Table 7 for the frequency granularity G). The INC

and DEC commands are designed for multiple and rapid PLL

frequency changes as required in frequency margining

applications. INC and DEC do not require the user to update

the PLL dividers by the LOAD command, INC and DEC do

not update the PLL_L and PLL_H registers either (use LOAD

for an initial PLL divider setting and, if desired, use GET to

read the PLL configuration). Note that the synthesizer does

not check any boundary conditions such as the VCO

frequency range. Applying the INC and DEC commands

could result in invalid VCO frequencies (VCO frequency

beyond lock range).

Register 0xF0 (CMD) is a write-only command register.

The purpose of CMD is to provide a fast way to increase or

decrease the PLL frequency and to update the registers. The

register accepts four commands, INC (increment M), DEC

(decrement M), LOAD and GET (update registers). It is

recommended to write the INC, DEC commands only after a

valid PLL configuration is achieved. INC and DEC only affect

the M-divider of the PLL (PLL feedback). Applying INC and

DEC commands can result in a PLL configuration beyond the

specified lock range and the PLL may lose lock. The

MPC92433 does not verify the validity of any commands

such as LOAD, INC, and DEC. The INC and DEC commands

change the PLL feedback divider without updating PLL_L

and PLL_H.

MPC92433

Advanced Clock Drivers Devices

Freescale Semiconductor

10

Table 16. PLL Configuration in Parallel and Serial Modes

Table 15. CMD (0xF0): PLL Command (Write-Only)

PLL

Configuration

Serial (Registers

PLL_L, PLL_H)

Command

Op-Code

Description

Parallel

INC

xxxx0001b

(0x01)

Increase internal PLL frequency

M:=M+1

M[9:0]

NA[2:0]

NB

Set pins M9–M0

Set pins NA2...NA0

Set pin NB

M[9:0] (R/W)

NA[2:0] (R/W)

NB (R/W)

DEC

LOAD

GET

xxxx0010b

(0x02)

Decrease internal PLL frequency

M:=M-1

xxxx0100b

(0x04)

Update the PLL divider config.

PLL divider M, N, P:=PLL_L, PLL_H

P

Set pin P

P (R/W)

LOCK status

LOCK pin 26

LOCK (Read only)

xxxx1000b

(0x08)

Update the configuration registers

PLL_L, PLL_H:=PLL divider M, N, P

Programming the I²C Interface

I²C — Register Access in Parallel Mode

Table 17. I²C Slave Address

The MPC92433 supports the configuration of the

synthesizer through the parallel interlace (PLOAD = 0) and

serial interface (PLOAD = 1). Register contents and the

divider configurations are not changed when the user

switches from parallel mode to serial mode. However, when

switching from serial mode to parallel mode, the PLL dividers

immediately reflect the logical state of the hardware pins

M[9:0], NA[2:0], NB, and P.

Applications using the parallel interface to obtain a PLL

configuration can use the serial interface to verify the divider

settings. In parallel mode (PLOAD = 0), the MPC92433

allows read-access to PLL_L and PLL_H through I²C (if

PLOAD = 0, the current PLL configuration is stored in PLL_L,

PLL_H. The GET command is not necessary and also not

supported in parallel mode). After changing from parallel to

serial mode (PLOAD = 1), the last PLL configuration is still

stored in PLL_L, PLL_H. The user now has full write and read

access to both configuration registers through the I²C bus

and can change the configuration at any time.

Bit

7

1

6

0

5

1

4

1

3

0

2

1

0

Value

R/W

ADR1 ADR0

The 7-bit I²C slave address of the MPC92433 synthesizer

is a combination of a 5-bit fixed addresses and two variable

bits which are set by the hardware pins ADR[1:0]. Bit 0 of the

MPC92433 slave address is used by the bus controller to

select either the read or write mode. ’0’ indicates a

transmission (I²C-WRITE) to the MPC92433. ’1’ indicates a

request for data (I²C-READ) from the synthesizer. The

hardware pins ADR1 and ADR0 and should be individually

set by the user to avoid address conflicts of multiple

MPC92433 devices on the same I²C bus.

Write Mode (R/W = 0)

The configuration registers are written by the bus

controller by the initiation of a write transfer with the

MPC92433 slave address (first byte), followed by the address

of the configuration register (second byte: 0x00, 0x01 or

0xF0), and the configuration data byte (third byte). This

transfer may be followed by writing more registers by sending

the configuration register address followed by one data byte.

Each byte sent by the bus controller is acknowledged by the

MPC92433. The transfer ends by a stop bit sent by the bus

controller. The number of configuration data bytes and the

write sequence are not restricted.

Table 18. Complete Configuration Register Write Transfer

1 bit

7 bits

1 bit

8 bits

&PLL_H

0x01

1 bit

8 bits

1 bit

8 bits

&PLL_L

0x00

1 bit

8 bits

1 bit

Start

Slave address R/W ACK

ACK Config-Byte 1 ACK

Data

ACK Config-Byte 2 ACK Stop

Data

(1)

0

10110xx

Master

Mast Slave

Master

Slave

Master

Slave

Master

Slave

Master

Slave Mast

1. xx = state of ADR1, ADR0 pins

MPC92433

Advanced Clock Drivers Devices

Freescale Semiconductor

11

Read Mode (R/W = 1)

command (loads the current configuration into PLL_L,

PLL_H) and read PLL_L, PLL_H again. Note that the PLL_L,

PLL_H registers and divider settings may not be equivalent

after the following cases:

The configuration registers are read by the bus controller

by the initiation of a read transfer. The MPC92433 supports

read transfers immediately after the first byte without a

change in the transfer direction. Immediately after the bus

controller sends the slave address, the MPC92433

acknowledges and then sends both configuration register

PLL_L and PLL_H (back-to-back) to the bus controller. The

CMD register cannot be read. In order to read the two

synthesizer registers and the current PLL configuration

setting, the user can 1) read PLL_L, PLL_H, write the GET

a. Writing the INC command

b. Writing the DEC command

c. Writing PLL_L, PLL_H registers with a new

configuration and not writing the LOAD command.

Table 19. Configuration Register Read Transfer

1 bit

7 bits

1 bit

R/W

1

1 bit

ACK

8 bits

PLL_L

Data

1 bit

ACK

8 bits

PLL_H

Data

1 bit

ACK

1 bit

Stop

Start

Slave address

(1)

10110xx

Master

Mast

Slave

Mast

Slave

Master

Slave

1. xx = state of ADR1, ADR0 pins

Device Startup

Start-Up Using the Serial (I²C) Interface

General Device Configuration

V

CC

It is recommended to reset the MPC92433 during or

immediately after the system powers up (MR = 0). The device

acquires an initial PLL divider configuration through the

parallel interface pins M[9:0], NA[2:0], N, and P⁽¹⁾with the

low-to-high transition of MR⁽²⁾. PLL frequency lock is

achieved within the specified lock time (t_LOCK) and is

indicated by an assertion of the LOCK signal which

completes the startup procedure. It is recommended to

disable the outputs (CLK_STOPx = 0) until PLL lock is

achieved to suppress output frequency transitions. The

output frequency can be reconfigured at any time through

either the parallel or the serial interface.

MR

Stable & Valid

P, M, N

PLOAD

2

Selects I C

Acquiring Lock

LOCK

PLL Lock

CLK_STOPx

QA, QB

Disabled (Low)

Note that a PLL configuration obtained by the parallel

interface can be read through I²C independent on the current

programming mode (parallel or serial). Refer to the I2C —

Register Access in Parallel Mode section for additional

information on how to read a PLL startup configuration

through the I²C interface.

t

Active

PLH

Figure 4. Start-Up Using I²C Interface

Set PLOAD = 1, CLK_STOPx = L and leave the parallel

interface pins (M[9:0], NA[2:0], N, and P) open. The PLL

dividers are configured by the default configuration at the low-

to-high transition of MR. This initial PLL configuration can be

re-programmed to the final VCO frequency at any time

through the serial interface. After the PLL achieved lock at the

desired VCO frequency, enable the outputs by setting

CLK_STOPx = H. PLL lock and re-lock (after any

configuration change through M or P) is indicated by LOCK

being asserted.

Starting-Up Using the Parallel Interface

The simplest way to use the MPC92433 is through the

parallel interface. The serial interface pins (SDA, SDL) and

ADDR[1:0]) can be left open and PLOAD is set to logic low.

After the release of MR and at any other time the PLL/output

frequency configuration is directly set to through the M[9:0],

NA[2:0], NB, and P pins.

1. The parallel interface pins M[9:0], NA[2:0], N, and P may be left open (floating). In this case the initial PLL configuration will have the default

setting of M = 500, P = 1, NA[2:0] = 010, NB = 0, resulting in an internal VCO frequency of 2000 MHz (f = 16 MHz) and an output frequency

ref

of 250 MHz.

2. The initial PLL configuration is independent on the selected programming mode (PLOAD low or high)

MPC92433

Advanced Clock Drivers Devices

12

Freescale Semiconductor

LOCK Detect

Output Clock Stop

The LOCK detect circuitry indicates the frequency-lock

status of the PLL by setting and resetting the pin LOCK and

register bit LOCK simultaneously. After acquiring an internal

frequency lock state, the assertion of the LOCK signal is

delayed at least 256 reference clock cycles to prevent

signaling temporary PLL locks during frequency transitions.

The LOCK signal is deasserted when the PLL lost lock, for

instance when the reference clock is removed: the LOCK

signal goes low after missing at least two f_refclock cycles

(N_REF(UNLOCK)). The PLL may also lose lock when the PLL

feedback-divider M or pre-divider P is changed or the

DEC/INC command is issued. The PLL may not lose lock as

a result of slow reference frequency changes. In any case of

losing LOCK, the PLL attempts to re-lock to the reference

frequency.

Asserting CLK_STOPx will stop the respective output

clock in logic low state. The CLK_STOPx control is internally

synchronized to the output clock signal, therefore, enabling

and disabling outputs does not produce runt pulses. See

Figure 5.The clock stop controls of the QA and QB outputs

are independent on each other. If the QB runs at half of the

QA output frequency and both outputs are enabled at the

same time, the first clock pulse of QA may not appear at the

same time of the first QB output. (See Figure 6.) Concident

rising edges of QA and QB stay synchronous after the

assertion and de-assertion of the CLK_STOPx controls.

Asserting MR always resets the output divider to a logic low

output state, with the risk of producing an output runt pulse.

(Disable)

(Enable)

CLK_STOPx

Qx

(Enable)

t

P_EN

P_DIS

Figure 5. Clock Stop Timing for NB = 0 (f_QA= f_QB

)

CLK_STOPA,B

(Disable)

(Enable)

QA

QB

Figure 6. Clock Stop Timing for NB = 1 (f_QA= 2 f_QB

)

MPC92433

Advanced Clock Drivers Devices

Freescale Semiconductor

13

Frequency Operating Range

Table 20. MPC92433 Frequency Operating Range for P=2

f

[MHz] (parameter: f

in MHz)

Output frequency for f

=16 MHz (parameter N)

VCO

REF

XTAL

M

M[9:0]

15

16

18

20

2

4

6

8

12

16

85

32

170

180

190

200

210

220

230

240

250

260

270

280

290

300

310

320

330

340

350

357

0010101010

0010110100

0010111110

0011001000

0011010010

0011011100

0011100110

0011110000

0011111010

0100000100

0100001110

0100011000

0100100010

0100101100

0100110110

0101000000

0101001010

0101010100

0101011110

1360

1440

1520

1600

1680

1760

1840

1920

2000

2080

2160

2240

2320

2400

2480

2560

2640

2720

2800

2856

1530

1620

1710

1800

1890

1980

2070

2160

2250

2340

2430

2520

2610

2700

2790

1700

1800

1900

2000

2100

2200

2300

2400

2500

2600

2700

2800

680

340

360

380

400

420

440

460

480

500

520

540

560

580

600

620

640

660

680

700

714

226.67

240.00

253.33

266.67

280.00

293.33

306.67

320.00

333.33

346.67

360.00

373.33

386.67

400.00

413.33

426.67

440.00

453.33

466.67

476.00

170

180

190

200

210

220

230

240

250

260

270

280

290

300

310

320

330

340

350

357

113.33

120.00

126.67

133.33

140.00

146.67

153.33

160.00

166.67

173.33

180.00

186.67

193.33

200.00

206.67

213.33

220.00

226.67

233.33

238.00

42.50

45.00

47.50

50.00

52.50

55.00

57.50

60.00

62.50

65.00

67.50

70.00

72.50

75.00

77.50

80.00

82.50

85.00

87.50

89.25

720

90

1425

1500

1575

1650

1725

1800

1875

1950

2025

2100

2175

2250

2325

2400

2475

2550

2625

760

95

800

100

105

110

115

120

125

130

135

140

145

150

155

160

165

170

175

178.50

840

880

920

960

1000

1040

1080

1120

1160

1200

1240

1280

1320

1360

1400

1428

0101100101 2667.5

MPC92433

Advanced Clock Drivers Devices

Freescale Semiconductor

14

Table 21. MPC92433 Frequency Operating Range for P=4

f

[MHz] (parameter: f

in MHz)

Output frequency for f

=16 MHz (parameter N)

VCO

REF

XTAL

M

M[9:0]

15

16

18

20

2

4

6

8

12

16

32

340

350

360

370

380

390

400

410

420

430

440

450

460

470

480

490

500

510

520

530

540

550

560

570

580

590

600

610

620

630

640

650

660

670

680

690

700

714

0101010100

0101011110

0101101000

1360

1400

1440

1480

1520

1560

1600

1640

1680

1720

1760

1800

1840

1880

1920

1960

2000

2040

2080

2120

2160

2200

2240

2280

2320

2360

2400

2440

2480

2520

2560

2600

2640

2680

2720

2760

2800

2856

1530

1575

1620

1665

1710

1755

1800

1845

1890

1935

1980

2025

2070

2115

2160

2205

2250

2295

2340

2475

2520

2565

2610

2565

2610

2655

2700

2745

2790

2835

1700

1750

1800

1850

1900

1950

2000

2050

2100

2150

2200

2250

2300

2350

2400

2450

2500

2550

2600

2650

2700

2750

2800

2850

680

340

350

360

370

380

390

400

410

420

430

440

450

460

470

480

490

500

510

520

530

540

550

560

570

580

590

600

610

620

630

640

650

660

670

680

690

700

714

226.67

233.33

240.00

246.67

253.33

260.00

266.67

273.33

280.00

286.67

293.33

300.00

306.67

313.33

320.00

326.67

333.33

340.00

346.67

353.33

360.00

366.67

373.33

380.00

386.67

393.33

400.00

406.67

413.33

420.00

426.67

433.33

440.00

446.67

453.33

460.00

466.67

476.00

170

175

180

185

190

195

200

205

210

215

220

225

230

235

240

245

250

255

260

265

270

275

280

285

290

295

300

305

310

315

320

325

330

335

340

345

350

357

113.33

116.67

120.00

123.33

126.67

130.00

133.33

136.67

140.00

143.33

146.67

150.00

153.33

156.67

160.00

163.33

166.67

170.00

173.33

176.67

180.00

183.33

186.67

190.00

193.33

196.67

200.00

203.33

206.67

210.00

213.33

216.67

220.00

223.33

226.67

230.00

233.33

238.00

85.0

42.50

43.75

45.00

46.25

47.50

48.75

50.00

51.25

52.50

53.75

55.00

56.25

57.50

58.75

60.00

61.25

62.50

63.75

65.00

66.25

67.50

68.75

70.00

71.25

72.50

73.75

75.00

76.25

77.50

78.75^

80.00

81.25

82.5

700

87.5

720

90.0

0101110010 1387.5

0101111100 1425.0

0110000110 1462.5

0110010000 1500.0

0110110010 1537.5

0110100100 1575.0

0110101110 1612.5

0110111000 1650.0

0111000010 1687.5

0111001100 1725.0

0111010110 1762.5

0111100000 1800.0

0111101010 1837.5

0111110100 1875.0

740

92.5

760

95.0

780

97.5

800

100.0

102.5

105.0

107.5

110.0

112.5

115.0

117.5

120.0

122.5

125.0

127.5

130.0

132.5

135.0

137.5

140.0

142.5

145.0

147.5

150.0

152.5

155.0

157.5

160.0

162.5

165

820

840

860

880

900

920

940

960

980

1000

1020

1040

1060

1080

1100

1120

1140

1160

1180

1200

1220

1240

1260

1280

1300

1320

1340

1360

1380

1400

1428

0111111110

1912.5

1000001000 1950.0

1000010010 1987.5

1000011100 2025.0

1000100110 2062.5

1000110000

2100

1000111010 2137.5

1001000100 2175.0

1001001110 2212.5

1001011000 2250.0

1001100010 2287.5

1001101100 2325.0

1001110110 2362.5

1010000000 2400.0

1010001010 2437.5

1010010100 2475.0

1010011110 2512.5

1010101000 2550.0

1010110010 2587.5

1010111100 2625.0

1011001010 2677.5

167.5

170.0

172.5

175.0

178.5

83.75

85.00

86.25

87.50

89.25

MPC92433

Advanced Clock Drivers Devices

Freescale Semiconductor

15

V_{CC_PLL}Filter

filter should provide an attenuation greater than 40 dB for

noise whose spectral content is above 100 kHz. In the

recommended filter shown in Figure 7 the filter cut-off

frequency is around 3.0–4.5 kHz and the noise attenuation at

100 kHz is better than 42 dB.

As the noise frequency crosses the series resonant point

of an individual capacitor its overall impedance begins to look

inductive and thus increases with increasing frequency. The

parallel capacitor combination shown ensures that a low

impedance path to ground exists for frequencies well above

the bandwidth of the PLL.

The MPC92433 is a mixed analog/digital product. Its

analog circuitry is naturally susceptible to random noise,

especially if this noise is seen on the power supply pins.

Random noise on the V_{CC_PLL}pin impacts the device AC

characteristics. The MPC92433 provides separate power

supplies for the digital circuitry (V_CC) and the internal PLL

(V_{CC_PLL}) of the device. The purpose of this design

technique is to isolate the high switching noise digital outputs

from the relatively sensitive internal analog phase-locked

loop. In digital system environments where it is more difficult

to minimize noise on the power supplies a second level of

isolation is recommended: a power supply filter on the

V_{CC_PLL}pin for the MPC92433.

The On-Chip Crystal Oscillator

The MPC92433 features an integrated on-chip crystal

oscillator to minimize system implementation cost. The

integrated oscillator is a Pierce-type that uses the crystal in

its parallel resonance mode. It is recommended to use a 15

to 20 MHz crystal with a load specification of C_L= 10 pF.

Crystals with a load specification of C_L= 20 pF may be used

at the expense of an resulting slightly higher frequency than

specified for the crystal. Externally connected capacitors on

both the XTAL_IN and XTAL_OUT pins are not required but

can be used to fine-tune the crystal frequency as desired.

The crystal, the trace and optional capacitors should be

placed on the board as close as possible to the MPC92433

XTAL_IN and XTAL_OUT pins to reduce crosstalk of active

signals into the oscillator. Short and wide traces further

reduce parasitic inductance and resistance. It is further

recommended to guard the crystal circuit by placing a ground

ring around the traces and oscillator components.

R

= 10–15 Ω

F

V

CC

CC_PLL

C

= 22 µF

10 nF

F

MPC92433

V

CC

7

33...100 nF

Figure 7. V_{CC_PLL}Power Supply Filter

Figure 7 illustrates a recommended power supply filter

scheme.

The MPC92433 is most susceptible to noise with spectral

content in the 100 kHz to 1 MHz range. Therefore, the filter

should be designed to target this range. The key parameter

that needs to be met in the final filter design is the DC voltage

drop that will be seen between the V_CCsupply and the

V_{CC_PLL}pin of the MPC92433. From the data sheet, the

V_{CC_PLL}current (the current sourced through the V_{CC_PLL}

pin) is maximum 10 mA, assuming that a minimum of 2.985 V

must be maintained on the V_{CC_PLL}pin. The resistor shown

in Figure 7 must have a resistance of 10–15 Ω to meet the

voltage drop criteria. The minimum values for R_Fand the filter

capacitor C_Fare defined by the filter characteristics: the RC

Table 22. Recommended Crystal Specifications

Parameter

Value

Fundamental AT Cut

Parallel

Crystal Cut

Resonance Mode

Crystal Frequency

Shunt Capacitance C

Load Capacitance C

16–20 MHz

5–7 pF

0

10 pF

L

MPC92433

Advanced Clock Drivers Devices

Freescale Semiconductor

16

Jitter Performance of the MPC92433

Figure 8 and Figure 9 illustrate the RMS jitter performance

of the MPC92433 across its specified VCO frequency range.

For some output dividers N, the cycle-to-cycle and period

jitter is a function of the VCO frequency and the output divider

N. The general trend is that as the output frequency

increases (higher VCO frequency and lower N-divider) the

MPC92433 output jitter decreases. Optimum jitter

performance can be achieved at higher VCO and output

frequencies.

For the output dividers of N=2, 4 and 6 the cycle-to-cycle

jitter does not depend on the VCO frequency. For the output

dividers of 2, 4 and 8 the period jitter does not depend on the

VCO frequency. The maximum cycle-to-cycle and period jitter

published in Table 6 (AC characteristics) correspond to the

jitter performance at the lowest VCO frequency limit. The

VCO frequency can be calculated using formula (2).

AC Test Reference and Output Termination

The MPC92433 LVPECL outputs are designed to drive

50 transmission lines and require a DC termination to

V_TT= V_CC– 2 V. Figure 10 illustrates the AC test reference

for the MPC92433 as used in characterization and test of this

circuit. If a separate termination voltage (V_TT) is not available,

applications may use alternative output termination methods

such as shown in Figure 11 and Figure 12.

Figure 8. MPC92433 Cycle-to-Cycle Jitter

The high-speed differential output signals of the

MPC92433 are incompatible to single-ended LVCMOS

signals. In order to use the synthesizer in LVCMOS clock

signal environments, the dual-channel translator device

MC100ES60T23 provides the necessary level conversion.

The MC100ES60T23 has been specifically designed to

interface with the MPC92433 and supports clock frequencies

up to 300 MHz.

Figure 9. MPC92433 Period Jitter

.

Z = 50 Ω

QA

Z = 50Ω

Pulse

Generator

Z = 50 Ω

QB

f

= 16 MHz

REF

Synthesizer

R

= 50 Ω

T

R = 50 Ω

T

DUT MPC92433

V

TT

Figure 10. MPC92433 AC Test Reference

MPC92433

Advanced Clock Drivers Devices

Freescale Semiconductor

17

V

TT

V

CC

130 Ω

50 Ω

QA

QB

Qx

Z = 50 Ω

MPC92433

82 Ω

Figure 11. Thevenin Termination

MPC92433

MC100ES60T23

V

TT

Figure 13. Interfacing with LVCMOS Logic

for f < 300 MHz

Qx

Z = 50 Ω

MPC92433

50 Ω

46.4 Ω

SMD Resistor Network

Figure 12. Resistor Network Termination

MPC92433

18

Advanced Clock Drivers Devices

Freescale Semiconductor

OUTLINE DIMENSIONS

4X

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5m, 1994.

0.200 AB T-U

Z

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLAN AB IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

4. DATUMS T, U, AND Z TO BE DETERMINED AT

DATAUM PLANE AB.

DETAILY

P

9

A

A1

48

37

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE AC.

36

1

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 PER SIDE. DIMENSIONS A AND B DO

INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE AB.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE D DIMENSION TO EXCEED

0.350.

T

U

B

V

AE

B1

V1

8. MINIMUM SOLDER PLATE THICKNESS SHALL BE

0.0076.

9. EXACT SHAPE OF EACH CORNER IS OPTIONAL.

12

25

13

MILLIMETERS

24

DIM MIN

MAX

7.000 BSC

3.500 BSC

Z

A

A1

B

B1

C

S1

7.000 BSC

3.500 BSC

1.400

T, U, Z

DETAILY

1.600

0.270

1.450

0.230

S

D

E

F

0.170

1.350

0.170

4X

0.200 AC T-U

Z

G

H

J

K

L

M

N

P

0.500 BSC

0.050

0.090

0.500

0˚

0.150

0.200

0.700

7˚

0.080 AC

12˚ REF

G

AB

AC

0.090

0.150

0.160

0.250 BSC

R

0.250

S

S1

V

V1

W

AA

9.000 BSC

4.500 BSC

9.000 BSC

4.500 BSC

0.200 REF

1.000 REF

AD

M˚

BASE METAL

TOP & BOTTOM

R

N

J

E

C

F

D

M

0.080

AC T- U Z

SECTION AE-AE

W

H

L˚

K

DETAIL AD

AA

FA SUFFIX

48-LEAD LQFP PACKAGE

CASE 932-03

ISSUE F

MPC92433

Advanced Clock Drivers Devices

Freescale Semiconductor

19

How to Reach Us:

Home Page:

www.freescale.com

E-mail:

support@freescale.com

USA/Europe or Locations Not Listed:

Freescale Semiconductor

Technical Information Center, CH370

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Chandler, Arizona 85224

+1-800-521-6274 or +1-480-768-2130

support@freescale.com

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Technical Information Center

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81829 Muenchen, Germany

+44 1296 380 456 (English)

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support@freescale.com

Information in this document is provided solely to enable system and software

implementers to use Freescale Semiconductor products. There are no express or

implied copyright licenses granted hereunder to design or fabricate any integrated

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Freescale Semiconductor reserves the right to make changes without further notice to

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1-800-441-2447 or 303-675-2140

Fax: 303-675-2150

LDCForFreescaleSemiconductor@hibbertgroup.com

MPC92433

Rev. 2

06/2005


型号：	MPC92433FAR2
厂家：	NXP
描述：	1428MHz, OTHER CLOCK GENERATOR, PQFP48, LQFP-48 时钟外围集成电路晶体
文件：	总20页 (文件大小：412K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MPC92433FAR2 [NXP]

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