MPC9443AE_技术文档

Freescale Semiconductor, Inc.

MOTOROLA

Order number: MPC9443

Rev 4, 07/2004

SEMICONDUCTOR TECHNICAL DATA

MPC9443

2.5 V and 3.3 V LVCMOS Clock

Fanout Buffer

The MPC9443 is a 2.5 V and 3.3 V compatible 1:16 clock distribution buffer

designed for low-voltage high-performance telecom, networking and computing

applications. The device supports 3.3 V, 2.5 V and dual supply voltage

(mixed-voltage) applications. The MPC9443 offers 16 low-skew outputs which

are divided into 4 individually configurable banks. Each output bank can be

individually supplied by 2.5 V or 3.3 V, individually set to run at 1X or 1/2X of

the input clock frequency or be disabled (logic low output state). Two selectable

LVPECL compatible inputs support differential clock distribution systems. In

addition, one selectable LVCMOS input is provided for LVCMOS clock

distribution systems. The MPC9443 is specified for the extended temperature

range of –40 to +85°C.

LOW VOLTAGE SUPPLY

2.5 V AND 3.3 V LVCMOS

CLOCK FANOUT BUFFER

SCALE 2:1

Features

•

Configurable 16 outputs LVCMOS clock distribution buffer

Compatible to single, dual and mixed 3.3 V / 2.5 V voltage supply

Output clock frequency up to 350 MHz

FA SUFFIX

48-LEAD LQFP PACKAGE

CASE 932-03

Designed for high-performance telecom, networking and computer

applications

•

Supports applications requiring clock redundancy

Max. output skew of 250 ps (125 ps within one bank)

Selectable output configurations per output bank

Individually per-bank high-impedance tristate

Output disable (stop in logic low state) control

48-lead LQFP package

32-lead Pb-free Package Available

Ambient operating temperature range of –40 to 85°C

Functional Description

The MPC9443 is a full static design supporting clock frequencies up to 350 MHz. The signals are generated and retimed on-chip

to ensure minimal skew between the four output banks.

Two independent LVPECL compatible clock inputs are available. This feature supports redundant differential clock sources.

In addition, the MPC9443 supports single-ended LVCMOS clock distribution systems. Each of the four output banks can be individu-

ally supplied by 2.5 V or 3.3 V, supporting mixed voltage applications. The FSELx pins choose between division of the input reference

frequency by one or two. The frequency divider can be set individually for each output bank. The MPC9443 output banks are in

high-impedance state by deasserting the OE_Npins. Asserting OE_Nwill the enable output banks. Please see Table 4. Output

High-Impedance Control (OE_N) for details. The outputs can be synchronously stopped (logic low state). The outputs provide

LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines. For series terminated transmission lines,

each of the MPC9443 outputs can drive one or two traces giving the devices an effective fanout of 1:32 at V_CC= 3.3 V. The device is

packaged in a 7x7 mm²48-lead LQFP package.

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MPC9443

(PULLDOWN)

PCLK0

PCLK1

BANK A

0

1

QA0

QA1

QA2

QA3

(PULLUP)

(PULLDOWN)

CLK

0

1

0

1

(PULLUP)

CLK ÷ 2

TCLK

(PULLDOWN)

QA4

PCLK_SEL

TCLK_SEL

(PULLDOWN)

BANK B

QB0

QB1

QB2

0

1

FSEL_A

(PULLDOWN)

FSEL_B

FSEL_C

FSEL_D

BANK C

QC0

0

1

QC1

QC2

QD0

QD1

BANK D

0

QD2

QD3

1

CLK_STOP

(PULLDOWN)

QD4

OE₀

OE₁

(PULLDOWN)

5

Figure 1. MPC9443 Logic Diagram

36 35 34 33 32 31 30 29 28 27 26 25

V_CC

QA4

V_CCD

QD0

37

24

23

22

21

20

19

18

17

16

15

14

13

38

39

40

41

42

43

44

45

46

QA3

QD1

QA2

QD2

GND

QA1

GND

QD3

MPC9443

QA0

QD4

V_CCA

FSEL_A

FSEL_B

FSEL_C

GND

V_CCD

CLK_STOP

OE₀

OE₁

47

48

GND

1

2

3

4

5

6

7

8

9 10 11 12

Figure 2. 48-Lead Package Pinout (Top View)

TIMING SOLUTIONS

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MPC9443

Table 1. Pin Configuration

I/O

Type

LVCMOS

Function

CCLK

Input

LVCMOS clock inputs

PCLK0, PCLK0

LVCMOS

LVPECL differential clock input

Output bank divide select input

PCLK1, PCLK1

FSEL_A, FSEL_B, FSEL_C, FSEL_D

CCLK_SEL

PCLK_SEL

OE₀, OE₁

Input

LVCMOS

LVCMOS/LVPECL clock input select

PCLK0/PCLK1 clock input select

Output tristate control

CLK_STOP

Input

LVCMOS

Supply

Synchronous output enable/disable (clock stop) control

Negative voltage supply

GND

V_CCA, V_CCB, V_CCC, V_CCD

Supply

Positive voltage supply output bank (V_CC)

V_CC

Supply

Positive voltage supply core (V_CC)

QA0 to QA4

QB0 to QB2

QC0 to QC2

QD0 to QD4

Output

LVCMOS

Bank A outputs

Bank B outputs

Bank C outputs

Bank D outputs

Table 2. Supported Single and Dual Supply Configurations

Supply Voltage

Configuration

1

2

3

4

5

GND

V_CC

V_CCA

V_CCB

V_CCC

V_CCD

3.3 V Supply

3.3 V

2.5 V

3.3 V

3.3 V or 2.5 V

2.5 V

3.3 V

3.3 V or 2.5 V

2.5 V

3.3 V

3.3 V or 2.5 V

2.5 V

3.3 V

0 V

Mixed Mode Supply

2.5 V Supply

3.3 V or 2.5 V

2.5 V

1. V_CCis the positive power supply of the device core and input circuitry. V_CCvoltage defines the input threshold and levels.

2. V_CCAis the positive power supply of the bank A outputs. V_CCAvoltage defines bank A output levels.

3. V_CCBis the positive power supply of the bank B outputs. V_CCBvoltage defines bank B output levels.

4. V_CCCis the positive power supply of the bank C outputs. V_CCCvoltage defines bank C output levels.

5. V_CCDis the positive power supply of the bank D outputs. V_CCDvoltage defines bank D output levels.

Table 3. Function Table (Controls)

Control

CCLK_SEL

PCLK_SEL

FSEL_A

Default

0

PCLK or PCLK1 active (LVPECL clock mode)

PCLK0 active, PCLK1 inactive

f_QA0:4= f_REF

1

CCLK active (LVCMOS clock mode)

PCLK1 active, PCLK0 inactive

f_QA0:4= f_REF÷ 2

0

FSEL_B

0

f_QB0:2= f_REF

f_QC0:2= f_REF

f_QD0:4= f_REF

Normal operation

f_QB0:2= f_REF÷ 2

f_QC0:2= f_REF÷ 2

f_QD0:4= f_REF÷ 2

FSEL_C

FSEL_D

CLK_STOP

Outputs are synchronously disabled (stopped) in logic

low state

OE₀, OE₁

00

Asynchronous output enable control. See Table 4. Output High-Impedance Control (OE_N)

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MPC9443

Table 4. Output High-Impedance Control (OE_N)¹

Total Number of

Enabled Outputs

OE₀

OE₁

QA0 to QA4

Enabled

QB0 to QB2

Enabled

QC0 to QC2

Enabled

QD0 to QD4

Enabled

0

1

0

1

0

1

16

10

8

Enabled

Disabled (tristate)

Enabled

Disabled (tristate)

Enabled

Disabled (tristate)

0

1. OE_Nwill tristate (high impedance) output banks independent on the logic state of the output and the status of CLK_STOP.

Table 5. Absolute Maximum Ratings¹

Symbol

Characteristics

Min

Max

Unit

Condition

V_CC

Supply Voltage

–0.3

3.6

V

V_IN

V_OUT

I_IN

DC Input Voltage

DC Output Voltage

DC Input Current

DC Output Current

Storage Temperature

–0.3

V_CC+ 0.3

±20

V

mA

°C

I_OUT

T_S

±50

–65

125

1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions

or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not

implied.

Table 6. General Specifications

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

V_TT

Output Termination Voltage

V

_CC÷ 2

V

MM

HBM

LU

ESD Protection (Machine model)

ESD Protection (Human body model)

Latch-Up Immunity

200

2000

200

V

mA

pF

C_PD

Power Dissipation Capacitance

10

Per output

C_IN

Input Capacitance

4.0

pF

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MPC9443

Table 7. DC Characteristics (V_CC= V_CCA= V_CCB= V_CCC= V_CCD= 3.3 V ± 5%, T_A= –40 to +85°C)

Symbol

V_IH

Characteristics

Input High Voltage

Min

2.0

Typ

Max

V_CC+ 0.3

Unit

V

Condition

LVCMOS

V_IL

Input Low Voltage

–0.3

250

1.1

0.8

V

mV

V

LVCMOS

LVPECL

V_PP

Peak-to-Peak Input Voltage

Common Mode Range

PCLK0, 1

1

V_CC– 0.6

200

V_CMR

Input Current²

Output High Voltage

I_IN

µA

V_IN= GND or V_IN= V_CC

I_OH= –24 mA³

V_OH

2.4

V

I_OL= 24 mA³

I_OL= 12 mA

V_OL

Output Low Voltage

0.55

0.30

V

Z_OUT

Output Impedance

19

Ω

4

Maximum Quiescent Supply Current

3.0

mA

All V_CCPins

I_CCQ

1. V_CMR(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V_CMRrange and the

input swing lies within the V_PP(DC) specification.

2. Input pull-up / pull-down resistors influence input current.

3. The MPC9443 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission

line to a termination voltage of V_TT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines (for V_CC=3.3 V) or one

50 Ω series terminated transmission line (for V_CC= 2.5 V).

4. I_CCQis the DC current consumption of the device with all outputs open and the input in its default state or open.

Table 8. AC Characteristics (V_CC= V_CCA= V_CCB= V_CCC= V_CCD= 3.3 V ± 5%, T_A= –40 to +85°C)¹

Symbol

f_ref

Characteristics

Min

0

Typ

Max

350

Unit

MHz

Condition

FSELx = 0

FSELx = 1

LVPECL

Input Frequency

f_MAX

Maximum Output Frequency

÷1 output

÷2 output

PCLK0,1

0

500

350

175

1000

MHz

mV

V_PP

Peak-to-Peak Input Voltage

Common Mode Range

2

PCLK0,1

1.3

1.4

V_CC– 0.8

V

LVPECL

V_CMR

t_{P, REF}

t_r, t_f

Reference Input Pulse Width

CCLK Input Rise/Fall Time

Propagation Delay

ns

1.0³

5.0

5.2

4.2

4.6

10

0.8 to 2.0 V

t_PLH

t_PHL

t_PLH

t_PHL

PCLK0,1 to any Q

CCLK to any Q

2.5

2.4

2.1

1.9

ns

t_{PLZ, HZ}Output Disable Time

t_{PZL, LZ}Output Enable Time

10

ns

ps

t_S, t_H

Setup, Hold Time (reference clock to CLK_STOP)

Output-to-Output Skew⁴

Within one bank

500

t_{sk(LH, HL)}

125

225

250

ps

Any output, same output divider

Any output, any output divider

Device-to-Device Skew (LH)⁵

Using PCLK0,1

Using CCLK

t_sk(PP)

2.5

2.1

2.8

2.7

ns

Device-to-Device Skew (LH, HL)⁶Using PCLK0,1

Using CCLK

Output Pulse Skew⁷

Using PCLK0,1

Using CCLK

t_SK(P)

DC_Q

300

400

55

ps

%

DC_REF= 50%

0.55 to 2.4 V

Output Duty Cycle f_Q<140 MHz and using CCLK

f_Q<250 MHz and using PCLK0,1

Output Rise/Fall Time

45

50

55

t_r, t_f

0.1

1.0

ns

1. AC characteristics apply for parallel output termination of 50 Ω to V_TT

.

2. V_CMR(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V_CMRrange and the

input swing lies within the V_PP(AC) specification.

3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse

width, output duty cycle and maximum frequency specifications.

4.

t_{sk(LH, HL)}includes both device skew referenced to the rising output edge and device skew referenced to the falling output edge.

5. Device-to-device skew referenced to the rising output edge.

6. Device-to-device skew referenced to the rising output edge or referenced to the falling output edge.

7. Output pulse skew is the absolute difference of the propagation delay times: | t_PLH– t_PHL

|

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MPC9443

Table 9. DC Characteristics (V_CC= V_CCA= V_CCB= V_CCC= V_CCD= 2.5 V ± 5%, T_A= –40 to +85°C)

Symbol

V_IH

Characteristics

Input High Voltage

Min

1.7

Typ

Max

V_CC+ 0.3

Unit

V

Condition

LVCMOS

V_IL

Input Low Voltage

–0.3

250

1.1

0.7

V

mV

V

LVCMOS

LVPECL

V_PP

Peak-to-Peak Input Voltage

Common Mode Range

PCLK0, 1

1

V_CC– 0.7

200

V_CMR

Input Current²

Output High Voltage

I_IN

µA

V_IN= GND or V_IN= V_CC

I_OH= –15 mA³

V_OH

1.8

V

I_OL= 15 mA³

V_OL

Output Low Voltage

0.6

3.0

V

Z_OUT

Output Impedance

22

Ω

4

Maximum Quiescent Supply Current

mA

All V_CCPins

I_CCQ

1. V_CMR(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V_CMRrange and the

input swing lies within the V_PP(DC) specification.

2. Input pull-up / pull-down resistors influence input current.

3. The MPC9443 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission

line to a termination voltage of V_TT. Alternatively, the device drives up to one 50 Ω series terminated transmission line at V_CC=2.5 V.

4. I_CCQis the DC current consumption of the device with all outputs open and the input in its default state or open.

Table 10. AC Characteristics (V_CC= V_CCA= V_CCB= V_CCC= V_CCD= 2.5 V ± 5%, T_A= –40 to +85°C)¹

Symbol

f_ref

Characteristics

Min

0

Typ

Max

350

Unit

MHz

Condition

FSELx = 0

FSELx = 1

LVPECL

Input Frequency

f_MAX

Maximum Output Frequency

÷1 output

÷2 output

PCLK0,1

0

500

350

175

1000

MHz

mV

V_PP

Peak-to-Peak Input Voltage

Common Mode Range

2

PCLK0,1

1.3

1.4

V_CC– 0.7

V

LVPECL

V_CMR

t_{P, REF}

t_r, t_f

Reference Input Pulse Width

CCLK Input Rise/Fall Time

Propagation Delay

ns

1.0³

6.0

6.2

5.3

5.5

0.8 to 2.0 V

t_PLH

t_PHL

t_PLH

t_PHL

PCLK0,1 to any Q

CCLK to any Q

2.5

2.4

2.1

1.9

ns

t_{PLZ, HZ}Output Disable Time

t_{PZL, LZ}Output Enable Time

t_S, t_HSetup, Hold Time (reference clock to CLK_STOP)

Output-to-Output Skew⁴

Within one bank

10

ns

ps

500

t_{sk(LH, HL)}

125

225

250

ps

Any output, same output divider

Any output, any output divider

Device-to-Device Skew (LH)⁵

Using PCLK0,1

Using CCLK

t_sk(PP)

3.2

3.1

3.5

3.4

ns

Device-to-Device Skew (LH, HL)⁶Using PCLK0,1

Using CCLK

Output Pulse Skew⁷

Using PCLK0,1

Using CCLK

t_SK(P)

DC_Q

300

400

55

ps

%

DC_REF= 50%

0.55 to 2.4 V

45

50

Output Duty Cycle f_Q<140 MHz and using CCLK

f_Q<140 MHz and using PCLK0,1

Output Rise/Fall Time

55

t_r, t_f

0.1

1.0

ns

1. AC characteristics apply for parallel output termination of 50 Ω to V_TT

.

2. V_CMR(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V_CMRrange and the

input swing lies within the V_PP(AC) specification.

3. Violation of the 1.0 ns maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse

width, output duty cycle and maximum frequency specifications.

4.

t_{sk(LH, HL)}includes both device skew referenced to the rising output edge and device skew referenced to the falling output edge.

5. Device-to-device skew referenced to the rising output edge.

6. Device-to-device skew referenced to the rising output edge or referenced to the falling output edge.

7. Output pulse skew is the absolute difference of the propagation delay times: | t_PLH– t_PHL

|

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Table 11. DC Characteristics (V_CC= 3.3 V ± 5%, any V_CCA,B,C,D= 2.5 V ± 5% or 3.3 V ± 5% (mixed), T_A= –40 to +85°C)

Symbol

Characteristics

Input High Voltage

Min

Typ

Max

Unit

Condition

LVCMOS

V_IH

2.0

V_CC+ 0.3

V

V_IL

I_IN

Input Low Voltage

–0.3

0.8

V

µA

V

LVCMOS

Input Current¹

200

I_OH= –15 mA²

I_OH= 24 mA²

V_OH

Output High Voltage

2.5 V output

3.3 V output

1.7

2.0

I_OL= 15 mA²

I_OL= 24 mA²

V_OL

Output Low Voltage

2.5 V output

3.3 V output

0.6

0.55

V

V_PP

Peak-to-Peak Input Voltage

Common Mode Range

PCLK0,1

PCLK0, 1

250

1.1

mV

V

LVPECL

3

V_CC– 0.6

V_CMR

Z_OUT

Output Impedance

2.5 V output

3.3 V output

22

19

Ω

C_PD

Power Dissipation Capacitance

10

pF

Per Output

4

Maximum Quiescent Supply Current

3.0

mA

All V_CCPins

I_CCQ

1. Input pull-up / pull-down resistors influence input current.

2. The MPC9443 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission

line to a termination voltage of V_TT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines (for V_CC= 3.3 V) or one

50 Ω series terminated transmission line (for V_CC=2.5 V).

3. V_CMR(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V_CMRrange and the

input swing lies within the V_PP(DC) specification.

4. I_CCQis the DC current consumption of the device with all outputs open and the input in its default state or open.

Table 12. AC Characteristics (V_CC= 3.3 V ± 5%, any V_CCA,B,C,D= 2.5 V ± 5% or 3.3 V ± 5% (mixed), T_A= –40 to +85°C)^{1 2}

Symbol

Characteristics

Output-to-Output Skew³

Min

Typ

Max

Unit

Condition

t_{sk(LH, HL)}

275

350

ps

Any output, same output divider

Any output, any output divider

t_sk(PP)

Device-to-Device Skew

See Table 8 (3.3 V AC Characteristics)

t_{PLH, HL}Propagation Delay

t_SK(P)

Output Pulse Skew⁴

Using PCLK0,1

Using CCLK

400

500

ps

DC_REF= 50%

45

50

55

%

DC_Q

Output Duty Cycle f_Q<140 MHz and using CCLK

f_Q<250 MHz and using PCLK0,1

1. AC characteristics apply for parallel output termination of 50 Ω to V_TT

.

2. This table only specifies AC parameter in mixed voltage supply conditions that vary from the corresponding AC tables. For all other parameters,

see Table 8 (for 3.3 V outputs) or Table 10 (for 2.5 V outputs)

3.

t_{sk(LH, HL)}includes both device skew referenced to the rising output edge and device skew referenced to the falling output edge.

4. Output pulse skew is the absolute difference of the propagation delay times: | t_PLH– t_PHL

|

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APPLICATIONS INFORMATION

Driving Transmission Lines

match the parallel combination of the line impedances. The

voltage wave launched down the two lines will equal:

The MPC9443 clock driver was designed to drive high speed

signals in a terminated transmission line environment. To

provide the optimum flexibility to the user the output drivers

were designed to exhibit the lowest impedance possible. With

an output impedance of less than 20 Ω the drivers can drive

either parallel or series terminated transmission lines at

V_CC= 3.3 V. For more information on transmission lines the

reader is referred to application note AN1091. In most high

performance clock networks point-to-point distribution of

signals is the method of choice. In a point-to-point scheme

either series terminated or parallel terminated transmission

lines can be used. The parallel technique terminates the signal

at the end of the line with a 50 Ω resistance to V_CC÷2.

This technique draws a fairly high level of DC current and

thus only a single terminated line can be driven by each output

of the MPC9443 clock driver. For the series terminated case

however there is no DC current draw, thus the outputs can drive

multiple series terminated lines. Figure 3. Single versus Dual

Transmission Lines illustrates an output driving a single series

terminated line versus two series terminated lines in parallel.

When taken to its extreme the fanout of the MPC9443 clock

driver is effectively doubled due to its capability to drive multiple

lines (at V_CC= 3.3 V).

V_L= V_S(Z₀÷ (R_S+ R₀+ Z₀))

Z₀= 50 Ω || 50 Ω

R_S= 31 Ω || 31 Ω

R₀= 19 Ω

V_L= 3.0 (25 ÷ (15.5 + 19 + 25)

= 1.26V

At the load end the voltage will double, due to the near unity

reflection coefficient, to 2.52 V. It will then increment towards

the quiescent 3.0 V in steps separated by one round trip delay

(in this case 4.0 ns).

3.0

OutA

t_D= 3.8956

OutB

t_D= 3.9386

2.5

2.0

1.5

1.0

0.5

0

In

MPC9443

OUTPUT

BUFFER

Z_O= 50 Ω

R_S= 31 Ω

19Ω

OutA

IN

2

4

6

8

10

12

14

TIME (ns)

MPC9443

OUTPUT

BUFFER

Figure 4. Single versus Dual Waveforms

Z_O= 50 Ω

R_S= 31 Ω

OutB0

OutB1

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines the situation

in Figure 5. Optimized Dual Line Termination should be

used. In this case the series terminating resistors are reduced

such that when the parallel combination is added to the output

buffer impedance the line impedance is perfectly matched.

19Ω

Figure 3. Single versus Dual Transmission Lines

The waveform plots in Figure 4. Single versus Dual

Waveforms show the simulation results of an output driving a

single line versus two lines. In both cases the drive capability of

the MPC9443 output buffer is more than sufficient to drive 50 Ω

transmission lines on the incident edge. Note from the delay

measurements in the simulations a delta of only 43 ps exists

between the two differently loaded outputs. This suggests that

the dual line driving need not be used exclusively to maintain

the tight output-to-output skew of the MPC9443. The output

waveform in Figure 4. Single versus Dual Waveforms shows

a step in the waveform, this step is caused by the impedance

mismatch seen looking into the driver. The parallel combination

of the 31 Ω series resistor plus the output impedance does not

MPC9443

OUTPUT

BUFFER

Z_O= 50 Ω

R_S= 12 Ω

19Ω

19Ω + 12Ω || 12Ω = 50Ω || 50Ω

25Ω = 25Ω

Figure 5. Optimized Dual Line Termination

TIMING SOLUTIONS

MOTOROLA

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MPC9443

Power Consumption of the MPC9443

and Thermal Management

In equation 2, P stands for the number of outputs with a

parallel or thevenin termination, V_OL, I_OL, V_OHand I_OHare a

function of the output termination technique and DC_Qis the

clock signal duty cycle. If transmission lines are used ΣC_Lis

zero in equation 2 and can be eliminated. In general, the use of

controlled transmission line techniques eliminates the impact of

the lumped capacitive loads at the end lines and greatly

reduces the power dissipation of the device. Equation 3

describes the die junction temperature T_Jas a function of the

power consumption.

Where R_thjais the thermal impedance of the package

(junction to ambient) and T_Ais the ambient temperature.

According to Table 13, the junction temperature can be used to

estimate the long-term device reliability. Further, combining

equation 1 and equation 2 results in a maximum operating

frequency for the MPC9443 in a series terminated transmission

line system.

The MPC9443 AC specification is guaranteed for the entire

operating frequency range up to 350 MHz. The MPC9443

power consumption and the associated long-term reliability

may decrease the maximum frequency limit, depending on

operating conditions such as clock frequency, supply voltage,

output loading, ambient temperature, vertical convection and

thermal conductivity of package and board. This section

describes the impact of these parameters on the junction

temperature and gives a guideline to estimate the MPC9443 die

junction temperature and the associated device reliability. For a

complete analysis of power consumption as a function of

operating conditions and associated long term device reliability

please refer to the application note AN1545. According the

AN1545, the long-term device reliability is a function of the die

junction temperature.

T_J,MAXshould be selected according to the MTBF system

requirements and Table 13. R_thjacan be derived from

Table 14. The R_thjarepresent data based on 1S2P boards,

using 2S2P boards will result in a lower thermal impedance

than indicated below.

Table 13. Die Junction Temperature and MTFBF

Junction Temperature (°C)

MTBF (Years)

100

110

120

130

20.4

9.1

4.2

2.0

Table 14. Thermal Package Impedance of the 48 ld LQFP

R_thja(1P2S board),

K/W

R_thja(2P2S board),

K/W

Convection,

LFPM

Increased power consumption will increase the die junction

temperature and impact the device reliability (MTBF).

According to the system-defined tolerable MTBF, the die

junction temperature of the MPC9443 needs to be controlled

and the thermal impedance of the board/package should be

optimized. The power dissipated in the MPC9443 is

represented in equation 1.

Still air

69

53

100 lfpm

200 lfpm

300 lfpm

400 lfpm

500 lfpm

64

50

Where I_CCQis the static current consumption of the

MPC9443, C_PDis the power dissipation capacitance per output,

(Μ)ΣC_Lrepresents the external capacitive output load, N is the

number of active outputs (N is always 16 in case of the

MPC9443). The MPC9443 supports driving transmission lines

to maintain high signal integrity and tight timing parameters.

Any transmission line will hide the lumped capacitive load at the

end of the board trace, therefore, ΣC_Lis zero for controlled

transmission line systems and can be eliminated from

equation 1. Using parallel termination output termination results

in equation 2 for power dissipation.

If the calculated maximum frequency is below 250 MHz, it

becomes the upper clock speed limit for the given application

conditions. The following eight derating charts describe the safe

frequency operation range for the MPC9443. The charts were

calculated for a maximum tolerable die junction temperature of

110°C (120°C), corresponding to an estimated MTBF of 9.1

years (4 years), a supply voltage of 3.3 V and series terminated

transmission line or capacitive loading. Depending on a given

set of these operating conditions and the available device

convection a decision on the maximum operating frequency

can be made.

Equation 1

P_TOT= [ I_CCQ+ V_CC· f_CLOCK· ( N · C_PD+ Σ C_L) ] · V_CC

M

P_TOT= V_CC· [ I_CCQ+ V_CC· f_CLOCK· ( N · C_PD+ Σ C_L) ] + Σ [ DC_Q· I_OH· (V_CC– V_OH) + (1 – DC_Q) · I_OL· V_OL]

Equation 2

Equation 3

M

P

T_J= T_A+ P_TOT· R_thja

T_j,MAX– T_A

1

– (I_CCQ· V_CC

)

]

Equation 4

f_CLOCK,MAX

=

·

[

C_PD· N · V²

R_thja

CC

MOTOROLA

TIMING SOLUTIONS

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MPC9443

Figure 6. Maximum MPC9443 frequency, V_CC= 3.3 V,

Figure 7. Maximum MPC9443 Frequency, V_CC= 3.3 V,

MTBF 9.1 Years, Driving Series Terminated

Transmission Lines

MTBF 9.1 Years, 4 pF Load per Line

Figure 8. Maximum MPC9443 Frequency, V_CC= 3.3 V,

Figure 9. Maximum MPC9443 Frequency, V_CC= 3.3 V,

MTBF 4 Years, 4 pF Load per Line

MTBF 4 Years, Driving Series Terminated

Transmission Lines

TIMING SOLUTIONS

10

MOTOROLA

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MPC9443

MPC9443 DUT

Pulse

Generator

Z = 50 Ω

Z_O= 50 Ω

R_T= 50 Ω

Z_O= 50 Ω

R_T= 50 Ω

V_TT

Figure 10. CCLK MPC9443 AC Test Reference for V_cc= 3.3 V and V_cc= 2.5 V

MPC9443 DUT

Z_O= 50 Ω

Differential Pulse

Generator

Z_O= 50 Ω

Z = 50 Ω

R_T= 50 Ω

V_TT

Figure 11. PCLK MPC9443 AC Test Reference

PCLK

V_CC

CCLK

V_CMR

V_CC÷2

V_PP

GND

V_CC

V

_CC÷ 2

V_CC÷2

Q_X

GND

t_P(LH)

t_P(HL)

t_P(LH)

t_P(HL)

Figure 12. Propagation Delay (t_PD) Test Reference

Figure 13. Propagation Delay (t_PD) Test Reference

V_CC

V

_CC÷2

CCLK

Q_X

V_CC÷2

GND

V_CC

GND

V_CC

V

_CC÷2

V

_CC÷2

GND

t_SK(LH)

t_SK(HL)

t_P(LH)

t_P(HL)

The pin-to-pin skew is defined as the worst case differ-

ence in propagation delay between any similar delay

path within a single device

t_SK(P)= | t_PLH– t_PHL

|

Figure 14. Output-to-Output Skew t_{SK(LH, HL)}

Figure 15. Output Pulse Skew (t_SK(P)) Test Reference

MOTOROLA

11

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MPC9443

V_CC

V

_CC÷2

GND

V_CC= 3.3 V V_CC= 2.5 V

t_P

2.4

1.8 V

T₀

0.55

0.6 V

DC = (t_{P ?}T₀x 100%)

t_F

t_R

The time from the PLL controlled edge to the non-controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

Figure 16. Output Duty Cycle (DC)

Figure 17. Output Transition Time Test Reference

V_CC

CCLK

PCLK

V_CC÷2

GND

V_CC

T_JIT(CC)= |T_N-T_N+1

|

T_N+1

T_N

V

_CC÷2

CLK_STOP

The variation in cycle time of a signal between adjacent

cycles, over a random sample of adjacent cycle pairs

GND

t_S

t_H

Figure 19. Setup and Hold Time (t_S, t_H) Test Reference

Figure 18. Cycle-to-Cycle Jitter

TIMING SOLUTIONS

12

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MPC9443

OUTLINE DIMENSIONS

FA SUFFIX

LQFP PACKAGE

CASE 932-03

ISSUE F

4X

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5m, 1994.

0.200 AB T-U

Z

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLAN AB IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

4. DATUMS T, U, AND Z TO BE DETERMINED AT

DATAUM PLANE AB.

DETAILY

9

A

P

A1

48

37

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE AC.

36

1

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 PER SIDE. DIMENSIONS A AND B DO

INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE AB.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE D DIMENSION TO EXCEED

0.350.

T

U

B

V

AE

B1

V1

8. MINIMUM SOLDER PLATE THICKNESS SHALL BE

0.0076.

9. EXACT SHAPE OF EACH CORNER IS OPTIONAL.

12

25

13

MILLIMETERS

24

DIM MIN

MAX

7.000 BSC

3.500 BSC

Z

A

A1

B

B1

C

S1

7.000 BSC

3.500 BSC

T, U, Z

1.400

1.600

0.270

1.450

0.230

S

D

E

F

0.170

1.350

0.170

DETAILY

4X

0.200 AC T-U

Z

G

H

J

K

L

M

N

P

0.500 BSC

0.050

0.090

0.500

0˚

0.150

0.200

0.700

7˚

0.080 AC

12˚ REF

G

AB

AC

0.090

0.150

0.160

0.250 BSC

R

0.250

S

S1

V

V1

W

AA

9.000 BSC

4.500 BSC

9.000 BSC

4.500 BSC

0.200 REF

1.000 REF

AD

M˚

BASE METAL

TOP & BOTTOM

R

N

J

E

C

F

D

M

0.080

AC T- U Z

SECTION AE-AE

W

H

L˚

K

DETAIL AD

AA

CASE 932-03

ISSUE F

MOTOROLA

13

TIMING SOLUTIONS

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MPC9443

NOTES

TIMING SOLUTIONS

14

MOTOROLA

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MPC9443

NOTES

MOTOROLA

15

TIMING SOLUTIONS

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Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied

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Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee

regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product

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provided in Motorola data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating

parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. Motorola does not convey any license

under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for

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MPC9443

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型号：	MPC9443AE
厂家：	NXP
描述：	9443 SERIES, LOW SKEW CLOCK DRIVER, 16 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48, 7 X 7 MM, PLASTIC, LQFP-48 驱动输出元件逻辑集成电路
文件：	总16页 (文件大小：336K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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