MPC9446ACR2 [NXP]
9446 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MS-026BBA, LQFP-32;
| 型号： | MPC9446ACR2 |
| 厂家： | 
NXP |
| 描述： | 9446 SERIES, LOW SKEW CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, 0.80 MM PITCH, LEAD FREE, MS-026BBA, LQFP-32 驱动 输出元件 逻辑集成电路 |
| 文件： | 总8页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MPC946/D
The MPC946 is a low voltage CMOS, 1:10 clock buffer. The 10 outputs
can be configured into a standard fanout buffer or into 1X and 1/2X
combinations. The ten outputs were designed and optimized to drive 50Ω
series or parallel terminated transmission lines. With output to output
skews of 350ps the MPC946 is an ideal clock distribution chip for
synchronous systems which need a tight level of skew from a large
number of outputs. For a similar product with more outputs consult the
MPC949 data sheet.
LOW VOLTAGE
1:10 CMOS CLOCK DRIVER
• 2 Selectable LVCMOS/LVTTL Clock Inputs
• 350ps Output to Output Skew
• Drives up to 20 Series Terminated Independent Clock Lines
• Maximum Input/Output Frequency of 150MHz
• Tristatable Outputs
• 32–Lead LQFP Packaging
• 3.3V VCC Supply
With an output impedance of approximately 7Ω, in both the HIGH and
the LOW logic states, the output buffers of the MPC946 are ideal for
driving series terminated transmission lines. More specifically each of the
10 MPC946 outputs can drive two series terminated transmission lines.
With this capability, the MPC946 has an effective fanout of 1:20 in
applications using point–to–point distribution schemes.
FA SUFFIX
LQFP PACKAGE
CASE 873A–02
The MPC946 has the capability of generating 1X and 1/2X signals from
a 1X source. The design is fully static, the signals are generated and
retimed inside the chip to ensure minimal skew between the 1X and 1/2X
signals. The device features selectability to allow the user to select the
ratio of 1X outputs to 1/2X outputs.
Two independent LVCMOS/LVTTL compatible clock inputs are available. Designers can take advantage of this feature to
provide redundant clock sources or the addition of a test clock into the system design. With the TCLK_Sel input pulled HIGH the
TCLK1 input is selected.
All of the control inputs are LVCMOS/LVTTL compatible. The Dsel pins choose between 1X and 1/2X outputs. A LOW on the
Dsel pins will select the 1X output. The MR/Tristate input will reset the internal flip flops and tristate the outputs when it is forced
HIGH.
The MPC946 is fully 3.3V compatible. The 32–lead LQFP package was chosen to optimize performance, board space and
cost of the device. The 32–lead LQFP has a 7x7mm body size with a conservative 0.8mm pin spacing.
06/00
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Freescale Semiconductor, Inc.
MPC946
LOGIC DIAGRAM
(Int Pull Down)
TCLK_Sel
(Int Pull Up)
(Int Pull Up)
÷1
÷2
TCLK0
TCLK1
0
1
0
1
3
3
Qa0:2
Qb0:2
R
(Int Pull Down)
Dsela
0
1
(Int Pull Down)
Dselb
0
1
4
Qc0:3
(Int Pull Down)
(Int Pull Down)
Dselc
MR/OE
Pinout: 32–Lead TQFP (Top View)
FUNCTION TABLES
24 23 22 21 20 19 18 17
VCCa
Qa2
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
Qc3
TCLK_Sel
Input
GNDc
Qc2
0
1
TCLK0
TCLK1
GNDa
Qa1
Dselx
Outputs
VCCc
Qc1
MPC946
0
1
1x
1/2x
VCCa
Qa0
GNDc
Qc0
MR/OE
Outputs
GNDa
MR/OE
0
1
Enabled
Hi–Z
VCCc
1
2
3
4
5
6
7
8
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MPC946
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
–0.3
–0.3
Max
Unit
V
V
V
Supply Voltage
Input Voltage
Input Current
4.6
CC
V
+ 0.3
V
I
DD
I
IN
(CMOS Inputs)
±20
mA
°C
T
Stor
Storage Temperature Range
–40
125
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
DC CHARACTERISTICS (T = 0° to 70°C, V
CC
= 3.3V ±0.3V)
A
Symbol
Characteristic
Input HIGH Voltage
Min
Typ
Max
3.6
Unit
V
Condition
V
V
V
V
2.0
2.5
IH
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input Current
0.8
V
IL
1
= –20mA
V
I
I
OH
OL
OH
1
= 20mA
0.4
±120
85
V
OL
I
I
µA
mA
pF
pF
Note 2.
IN
Maximum Quiescent Supply Current
Input Capacitance
70
25
CC
C
C
4
IN
Power Dissipation Capacitance
Per Output
pd
1. The MPC946 can drive 50Ω transmission lines on the incident edge. Each output can drive one 50Ω parallel terminated transmission line to
the termination voltage of V = V /2. Alternately, the device drives up to two 50Ω series terminated transmission lines.
TT CC
2. I current is a result of internal pull–up/pull–down resistors.
IN
AC CHARACTERISTICS (T = 0° to 70°C, V
CC
= 3.3V ±0.3V)
A
Symbol
Characteristic
Maximum Input Frequency
Propagation Delay
Min
Typ
Max
Unit
MHz
ns
Condition
Note 1.
F
150
max
t
t
,
TCLK to Q
5.0
4.5
8.0
7.5
12.0
11.5
Note 1., 3.
PLH
PHL
t
Output–to–Output Skew
ps
Note 1., 3.
sk(o)
Same Frequency Outputs
Different Frequency Outputs
Same Frequency Outputs
Different Frequency Outputs
350
350
350
450
F
max
F
max
F
max
F
max
< 100MHz
< 100MHz
> 100MHz
> 100MHz
t
t
t
Part–to–Part Skew
2.0
3
4.5
11
ns
ns
ns
ns
Note 2.
sk(pp)
, t
PZL PZH
Output Enable Time
Output Disable Time
Output Rise/Fall Time
Note 3.
, t
PLZ PHZ
3
11
Note 3.
t , t
r f
0.1
0.5
1.0
0.8V to 2.0V, Note 3.
1. Driving 50Ω transmission lines.
2. Part–to–part skew at a given temperature and voltage.
3. Termination is 50Ω to V /2.
CC
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MPC946
APPLICATIONS INFORMATION
Driving Transmission Lines
line impedances. The voltage wave launched down the two
lines will equal:
The MPC946 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of approximately 10Ω
the drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
VL = VS ( Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.8V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
3.0
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC946 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 1 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC946 clock
driver is effectively doubled due to its capability to drive
multiple lines.
OutA
= 3.8956
OutB
= 3.9386
t
D
2.5
2.0
1.5
1.0
0.5
0
t
D
In
2
4
6
8
10
12
14
TIME (nS)
MPC946
OUTPUT
BUFFER
Figure 2. Single versus Dual Waveforms
Z
= 50Ω
O
R = 43Ω
S
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 3 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
7Ω
IN
IN
OutA
MPC946
OUTPUT
BUFFER
Z
O
= 50Ω
= 50Ω
R = 43Ω
S
OutB0
OutB1
7Ω
Z
O
R = 43Ω
S
MPC946
OUTPUT
Z
O
= 50Ω
= 50Ω
R = 36Ω
S
BUFFER
7Ω
Figure 1. Single versus Dual Transmission Lines
Z
O
R = 36Ω
S
The waveform plots of Figure 2 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC946 output buffers is
more than sufficient to drive 50Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC946. The output waveform
in Figure 2 shows a step in the waveform, this step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 43Ω series resistor plus the output
impedance does not match the parallel combination of the
7Ω + 36Ω 36Ω = 50Ω 50Ω
25Ω = 25Ω
Figure 3. Optimized Dual Line Termination
SPICE level output buffer models are available for
engineers who want to simulate their specific interconnect
schemes. In addition IV characteristics are in the process of
being generated to support the other board level simulators in
general use.
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MPC946
OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 873A-02
ISSUE A
4X
A
A1
0.20 (0.008) AB T–U
Z
32
25
1
–U–
V
–T–
B
AE
AE
P
B1
DETAIL Y
–Z–
V1
17
8
DETAIL Y
9
4X
0.20 (0.008) AC T–U
Z
9
NOTES:
S1
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
DETAIL AD
G
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
–AB–
–AC–
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
SEATING
PLANE
0.10 (0.004) AC
BASE
METAL
N
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
F
D
8X M
MILLIMETERS
DIM MIN MAX
7.000 BSC
INCHES
MIN MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
R
J
A
A1
B
3.500 BSC
7.000 BSC
3.500 BSC
1.400 1.600 0.055 0.063
0.300 0.450 0.012 0.018
1.350 1.450 0.053 0.057
0.300 0.400 0.012 0.016
SECTION AE–AE
E
C
B1
C
D
E
F
W
G
H
J
K
M
N
P
0.800 BSC
0.031 BSC
Q
H
K
X
0.050 0.150 0.002 0.006
0.090 0.200 0.004 0.008
0.500 0.700 0.020 0.028
12 REF
0.090 0.160 0.004 0.006
0.400 BSC 0.016 BSC
12 REF
DETAIL AD
Q
R
1
5
1
5
0.150 0.250 0.006 0.010
S
9.000 BSC
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.354 BSC
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
S1
V
V1
W
X
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MPC946
NOTES
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6
TIMING SOLUTIONS
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Freescale Semiconductor, Inc.
MPC946
NOTES
For More Information On This Product,
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MPC946
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MPC946/D
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