MPC950FA_技术文档

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SEMICONDUCTOR TECHNICAL DATA

The MPC950 is a 3.3V compatible, PLL based clock driver device

targeted for high performance clock tree designs. With output frequencies

of up to 180MHz and output skews of 375ps the MPC950 is ideal for the

most demanding clock tree designs. The devices employ a fully

differential PLL design to minimize cycle–to–cycle and long term jitter.

This parameter is of significant importance when the clock driver is

providing the reference clock for PLL’s on board today’s microprocessors

and ASiC’s. The devices offer 9 low skew outputs, the outputs are

configurable to support the clocking needs of the various high

performance microprocessors.

LOW VOLTAGE

PLL CLOCK DRIVER

• Fully Integrated PLL

• Oscillator or Crystal Reference Input

• Output Frequency up to 180MHz

• Outputs Disable in High Impedance

• Compatible with PowerPC , Intel and High Performance RISC

Microprocessors

• LQFP Packaging

FA SUFFIX

32–LEAD LQFP PACKAGE

CASE 873A–02

• Output Frequency Configurable

• ±100ps Typical Cycle–to–Cycle Jitter

Two selectable feedback division ratios are available on the MPC950

to provide input reference clock flexibility. The FBSEL pin will choose

between a divide by 8 or a divide by 16 of the VCO frequency to be

compared with the input reference to the MPC950. The internal VCO is

running at either 2x or 4x the high speed output, depending on

configuration, so that the input reference will be either one half, one fourth

or one eighth the high speed output.

The MPC950 provides an external test clock input for scan clock distribution or system diagnostics. In addition the REF_SEL

pin allows the user to select between a crystal input to an on–board oscillator for the reference or to chose a TTL level oscillator

input directly. The on–board crystal oscillator requires no external components beyond a series resonant crystal.

The MPC950 is fully 3.3V compatible and require no external loop filter components. All inputs accept LVCMOS or LVTTL

compatible levels while the outputs provide LVCMOS levels with the capability to drive terminated 50Ω transmission lines. Select

inputs do not have internal pull–up/pull–down resistors and thus must be set externally. For series terminated 50Ω lines, each of

the MPC950 outputs can drive two traces giving the device an effective fanout of 1:18. The device is packaged in a 7x7mm

32–lead LQFP package to provide the optimum combination of board density and performance.

PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.

06/00

REV 7

1

Motorola, Inc. 2000

MPC950

MPC950 LOGIC DIAGRAM

fsela

PLL_En

Tclk

Ref_Sel

Qa

Qb

PHASE

DETECTOR

VCO

200–480MHz

xtal1

xtal2

÷2/÷4

÷4/÷8

xtal

OSC

LPF

÷8/÷16

(Pull Down)

FBsel

fselb

Qc0

Qc1

fselc

MR/OE

Qd0

Qd1

Qd2

Qd3

Qd4

POWER–ON RESET

÷4/÷8

fseld

FUNCTION TABLES

Ref_Sel

Function

1

0

TCLK

XTAL_OSC

24 23 22 21 20 19 18 17

GNDO

Qb

25

26

27

28

29

30

31

32

16

15

14

13

12

11

10

9

Qd2

PLL_En

Function

VCCO

Qd3

1

0

PLL Enabled

PLL Bypass

VCCO

Qa

GNDO

Qd4

FBsel

Function

MPC950

GNDO

TCLK

PLL_En

Ref_Sel

1

0

÷8

÷16

VCCO

MR/OE

xtal2

MR/OE

Function

1

0

Outputs Disabled

Outputs Enabled

1

2

3

4

5

6

7

8

fseln

Function

1

0

Qa = ÷4; Qb:d = ÷8

Qa = ÷2; Qb:d = ÷4

MOTOROLA

2

TIMING SOLUTIONS

MPC950

FUNCTION TABLE – MPC950

INPUTS

OUTPUTS

TOTALS

Total x

fsela

fselb

fselc

fseld

Qa(1)

Qb(1)

Qc(2)

Qd(5)

Total 2x

Total x/2

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2x

x

x/2

x

x/2

x

x/2

x

x/2

x

x/2

x

x/2

x

x/2

x

x/2

x

x/2

1

0

8

3

6

1

7

2

3

0

9

4

7

2

8

3

6

1

0

5

2

7

1

6

5

8

0

5

2

7

1

6

3

8

x

x/2

x

x/2

x

x/2

x

x/2

x

x/2

x

NOTE: x = f

/4; 200MHz < f

VCO

< 480MHz.

VCO

ABSOLUTE MAXIMUM RATINGS*

Symbol

Parameter

Min

–0.3

Max

Unit

V

Supply Voltage

Input Voltage

Input Current

4.6

CC

V

+ 0.3

V

I

CC

±20

125

I

IN

mA

°C

T

Stor

Storage Temperature Range

–40

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or

conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is

not implied.

THERMAL CHARACTERISTICS

Proper thermal management is critical for reliable system operation. This is especially true for high fanout and high drive

capability products. Generic thermal information is available for the Motorola Clock Driver products. The means of calculating die

power, the corresponding die temperature and the relationship to longterm reliability is addressed in the Motorola application

note AN1545.

DC CHARACTERISTICS (T = 0° to 70°C, V

CC

= 3.3V ±5%)

A

Symbol

Characteristic

Input HIGH Voltage

Min

Typ

Max

3.6

Unit

V

Condition

V

LVCMOS Inputs

2.0

IH

Input LOW Voltage

Output HIGH Voltage

Output LOW Voltage

Input Current

0.8

V

IL

2.4

V

I

= –40mA, Note 1.

= 40mA, Note 1.

OH

OL

OH

0.5

±120

4

V

OL

I

IN

µA

pF

mA

C

Input Capacitance

IN

Power Dissipation Capacitance

Maximum Quiescent Supply Current

Maximum PLL Supply Current

25

90

15

Per Output

pd

I

115

20

All VCC Pins

VCCA Pin Only

CC

I

CCPLL

1. The MPC950 outputs can drive series or parallel terminated 50Ω (or 50Ω to V /2) transmission lines on the incident edge

CC

(see Applications Info section).

TIMING SOLUTIONS

BR1333 — Rev 6

3

MOTOROLA

MPC950

PLL INPUT REFERENCE CHARACTERISTICS (T = 0 to 70°C)

A

Symbol

Characteristic

TCLK Input Rise/Falls

Min

Max

3.0

Unit

ns

Condition

t , t

r f

f

Reference Input Frequency

Crystal Oscillator Frequency

Reference Input Duty Cycle

Note 1.

10

Note 1.

25

MHz

%

ref

Note 2.

Xtal

refDC

25

75

1. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider for the TCLK inputs.

2. See Applications Info section for more crystal information.

AC CHARACTERISTICS (T = 0°C to 70°C, V

CC

= 3.3V ±5%)

Min

0.10

/2–1000

A

Symbol

t , t

Characteristic

Output Rise/Fall Time

Output Duty Cycle

Typ

Max

Unit

ns

Condition

0.8 to 2.0V, Note 1.

Note 1.

1.0

r f

t

t /2+1000

CYCLE

ps

pw

CYCLE

t

Output–to–Output Skews Same Frequencies

200

325

375

ps

Note 1.

sk(O)

Different Frequencies

Qa

< 150MHz

> 150MHz

500

750

fmax

f

PLL VCO Lock Range

200

480

MHz

VCO

Maximum Output

Frequency

Qa (÷2)

Qa/Qb (÷4)

Qb (÷8)

180

120

60

Note 1.

max

t

,

Output Disable Time

Output Enable Time

7

6

ns

ps

ms

Note 1.

Note 2.

PLZ HZ

PZL

jitter

lock

Cycle–to–Cycle Jitter (Peak–to–Peak)

Maximum PLL Lock Time

±100

10

1. Termination of 50 to V /2.

CC

2. See Applications Info section for more jitter information.

APPLICATIONS INFORMATION

Programming the MPC950

one must still ensure that the VCO will be stable given the

frequency of the outputs desired. The feedback frequency

should be used to situate the VCO into a frequency range in

which the PLL will be stable. The design of the PLL is such

that for output frequencies between 25 and 180MHz the

MPC950 can generally be configured into a stable region.

The MPC950 clock driver outputs can be configured into

several frequency relationships. The output dividers for the

four output groups allows the user to configure the outputs

into 1:1, 2:1, 4:1 and 4:2:1 frequency ratios. The use of even

dividers ensures that the output duty cycle is always 50%.

Table 1 illustrates the various output configurations, the table

describes the outputs using the VCO frequency as a

reference. As an example for a 4:2:1 relationship the Qa

outputs would be set at VCO/2, the Qb’s and Qc’s at VCO/4

and the Qd’s at VCO/8. These settings will provide output

frequencies with a 4:2:1 relationship.

The relationship between the input reference and the

output frequency is also very flexible. Table 2 shows the

multiplication factors between the inputs and outputs for the

MPC950. Figure 1 through Figure 4 illustrates several

programming possibilities, although not exhaustive it is

representative of the potential applications.

The division settings establish the output relationship, but

MOTOROLA

4

TIMING SOLUTIONS

MPC950

Table 1. Programmable Output Frequency Relationships

INPUTS

OUTPUTS

fsela

fselb

fselc

fseld

Qa

Qb

Qc

Qd

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VCO/2

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

VCO/4

VCO/8

Table 2. Input Reference versus Output Frequency Relationships

FB_Sel = ‘1’

FB_Sel = ‘0’

Config

fsela

fselb

fselc

fseld

Qa

Qb

Qc

Qd

Qa

Qb

Qc

Qd

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4x

2x

x

2x

x

2x

x

2x

x

2x

x

2x

x

2x

x

2x

x

2x

x

2x

x

2x

x

8x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

4x

2x

x

2x

x

2x

x

2x

x

TIMING SOLUTIONS

BR1333 — Rev 6

5

MOTOROLA

MPC950

1

Qa

Qb

Qc

Qd

66.66MHz

33.33MHz

66.66MHz

‘1’

‘0’

fsela

fselb

fselc

fseld

FBsel

Qa

Qb

Qc

Qd

66.66MHz

33.33MHz

‘1’

‘0’

‘1’

fsela

fselb

fselc

fseld

FBsel

2

5

2

5

16.66MHz

Input Ref

33.33MHz

Input Ref

Figure 1. Dual Frequency Configuration

Figure 2. Dual Frequency Configuration

MPC950

1

Qa

Qb

Qc

Qd

66.66MHz

33.33MHz

‘1’

‘0’

fsela

fselb

fselc

fseld

FBsel

Qa

Qb

Qc

Qd

160MHz

80MHz

40MHz

‘0’

‘1’

‘0’

fsela

fselb

fselc

fseld

FBsel

1

2

5

2

5

16.66MHz

Input Ref

20MHz

Input Ref

Figure 3. Dual Frequency Configuration

Jitter Performance of the MPC950

Figure 4. Triple Frequency Configuration

measurement will represent an upper bound of

cycle–to–cycle jitter. Most likely, this is a conservative

estimate of the cycle–to–cycle jitter.

With the clock rates of today’s digital systems continuing

to increase more emphasis is being placed on clock

distribution design and management. Among the issues

being addressed is system clock jitter and how that affects

the overall system timing budget. The MPC950 was

designed to minimize clock jitter by employing a differential

bipolar PLL as well as incorporating numerous power and

ground pins in the design. The following few paragraphs will

outline the jitter performance of the MPC950, illustrate the

measurement limitations and provide guidelines to minimize

the jitter of the device.

There are two sources of jitter in a PLL based clock driver,

the commonly known random jitter of the PLL and the less

intuitive jitter caused by synchronous, different frequency

outputs switching. For the case where all of the outputs are

switching at the same frequency the total jitter is exactly

equal to the PLL jitter. In a device, like the MPC950, where a

number of the outputs can be switching synchronously but at

different frequencies a “multi–modal” jitter distribution can be

seen on the highest frequency outputs. Because the output

being monitored is affected by the activity on the other

outputs it is important to consider what is happening on those

other outputs. From Figure 5, one can see for each rising

edge on the higher frequency signal the activity on the lower

frequency signal is not constant. The activity on the other

outputs tends to alter the internal thresholds of the device

such that the placement of the edge being monitored is

displaced in time. Because the signals are synchronous the

relationship is periodic and the resulting jitter is a compilation

of the PLL jitter superimposed on the displaced edges. When

histograms are plotted the jitter looks like a “multi–modal”

distribution as pictured in Figure 5. Depending on the size of

the PLL jitter and the relative displacement of the edges the

“multi–modal” distribution will appear truly “multi–modal” or

simply like a “fat” Gaussian distribution. Again note that in the

case where all the outputs are switching at the same

frequency there is no edge displacement and the jitter is

reduced to that of the PLL.

The most commonly specified jitter parameter is

cycle–to–cycle jitter. Unfortunately with today’s high

performance measurement equipment there is no way to

measure this parameter for jitter performance in the class

demonstrated by the MPC950. As a result different methods

are used which approximate cycle–to–cycle jitter. The typical

method of measuring the jitter is to accumulate a large

number of cycles, create a histogram of the edge placements

and record peak–to–peak as well as standard deviations of

the jitter. Care must be taken that the measured edge is the

edge immediately following the trigger edge. If this is not the

case the measurement inaccuracy will add significantly to the

measured jitter. The oscilloscope cannot collect adjacent

pulses, rather it collects data from a very large sample of

pulses. It is safe to assume that collecting pulse information

in this mode will produce jitter values somewhat larger than if

consecutive cycles were measured, therefore, this

MOTOROLA

6

TIMING SOLUTIONS

MPC950

most cases is well within the requirements of today’s

microprocessors.

1

2

1

2

40

35

30

25

20

15

10

5

Conf 1

Conf 2

Conf 3

1

2

Peak–to–Peak PLL Jitter

Peak–to–Peak Period Jitter

0

160

240

320

400

480

560

VCO Frequency (MHz)

1

2

3

2

1

2

3

Conf 1 = All Outputs at the Same Frequency

Conf 2 = 4 Outputs at X, 5 Outputs at X/2

Conf 3 = 1 Output at X, 8 Outputs at X/4

Figure 6. RMS PLL Jitter versus VCO Frequency

1

2

3

400

Conf 2

Conf 3

350

300

250

200

150

Peak–to–Peak PLL Jitter

Peak–to–Peak Period Jitter

160

240

320

400

480

560

VCO Frequency (MHz)

Figure 5. PLL Jitter and Edge Displacement

Conf 2 = 4 Outputs at X, 5 Outputs at X/2

Conf 3 = 1 Output at X, 8 Outputs at X/4

Figure 6 graphically represents the PLL jitter of the

MPC950. The data was taken for several different output

configurations. By triggering on the lowest frequency output

the PLL jitter can be measured for configurations in which

outputs are switching at different frequencies. As one can

see in the figure the PLL jitter is much less dependent on

output configuration than on internal VCO frequency.

Figure 7. Peak–to–Peak Period Jitter versus

VCO Frequency

Finally from the data there are some general guidelines

that, if followed, will minimize the output jitter of the device.

First and foremost always configure the device such that the

VCO runs as fast as possible. This is by far the most critical

parameter in minimizing jitter. Second keep the reference

frequency as high as possible. More frequent updates at the

phase detector will help to reduce jitter. Note that if there is a

tradeoff between higher reference frequencies and higher

VCO frequency always chose the higher VCO frequency to

minimize jitter. The third guideline may be the most difficult,

and in some cases impossible, to follow. Try to minimize the

number of different frequencies sourced from a single chip.

The fixed edge displacement associated with the switching

noise in most cases nearly doubles the “effective” jitter of a

high speed output.

Two different configurations were chosen to look at the

period displacement caused by the switching outputs.

Configuration 3 is considered worst case as the “trimodal”

distribution (as pictured in Figure 5) represents the largest

spread between distribution peaks. Configuration 2 is

considered a typical configuration with half the outputs at a

high frequency and the remaining outputs at one half the high

frequency. For these cases the peak–to–peak numbers are

reported in Figure 7 as the sigma numbers are useless

because the distributions are not Gaussian. For situations

where the outputs are synchronous and switching at different

frequencies the measurement technique described here is

insufficient to use for establishing guaranteed limits. Other

techniques are currently being investigated to identify a more

accurate and repeatable measurement so that guaranteed

limits can be provided. The data generated does give a good

indication of the general performance, a performance that in

Power Supply Filtering

The MPC950 is a mixed analog/digital product and as

such it exhibits some sensitivities that would not necessarily

be seen on a fully digital product. Analog circuitry is naturally

TIMING SOLUTIONS

BR1333 — Rev 6

7

MOTOROLA

MPC950

susceptible to random noise, especially if this noise is seen

on the power supply pins. The MPC950 provides separate

power supplies for the output buffers (VCCO) and the

phase–locked loop (VCCA) of the device. The purpose of this

design technique is to try and isolate the high switching noise

digital outputs from the relatively sensitive internal analog

phase–locked loop. In a controlled environment such as an

evaluation board this level of isolation is sufficient. However,

in a digital system environment where it is more difficult to

minimize noise on the power supplies a second level of

isolation may be required. The simplest form of isolation is a

power supply filter on the VCCA pin for the MPC950.

adequate to eliminate power supply noise related problems

in most designs.

Using the On–Board Crystal Oscillator

The MPC950 features an on–board crystal oscillator to

allow for seed clock generation as well as final distribution.

The on–board oscillator is completely self contained so that

the only external component required is the crystal. As the

oscillator is somewhat sensitive to loading on its inputs the

user is advised to mount the crystal as close to the MPC950

as possible to avoid any board level parasitics. To facilitate

co–location surface mount crystals are recommended, but

not required.

Figure 8 illustrates a typical power supply filter scheme.

The MPC950 is most susceptible to noise with spectral

content in the 1KHz to 1MHz range. Therefore the filter

should be designed to target this range. The key parameter

that needs to be met in the final filter design is the DC voltage

The oscillator circuit is a series resonant circuit as

opposed to the more common parallel resonant circuit, this

eliminates the need for large on–board capacitors. Because

the design is a series resonant design for the optimum

frequency accuracy a series resonant crystal should be used

(see specification table below). Unfortunately most off the

shelf crystals are characterized in a parallel resonant mode.

However a parallel resonant crystal is physically no different

than a series resonant crystal, a parallel resonant crystal is

simply a crystal which has been characterized in its parallel

resonant mode. Therefore in the majority of cases a parallel

specified crystal can be used with the MPC950 with just a

minor frequency error due to the actual series resonant

frequency of the parallel resonant specified crystal. Typically

a parallel specified crystal used in a series resonant mode

will exhibit an oscillatory frequency a few hundred ppm lower

than the specified value. For most processor

implementations a few hundred ppm translates into kHz

inaccuracies, a level which does not represent a major issue.

drop that will be seen between the V

pin of the MPC950. From the data sheet the I

supply and the VCCA

current

CC

VCCA

(the current sourced through the VCCA pin) is typically 15mA

(20mA maximum), assuming that a minimum of 3.0V must be

maintained on the VCCA pin very little DC voltage drop can

be tolerated when a 3.3V V

supply is used. The resistor

CC

shown in Figure 8 must have a resistance of 10–15Ω to meet

the voltage drop criteria. The RC filter pictured will provide a

broadband filter with approximately 100:1 attenuation for

noise whose spectral content is above 20KHz. As the noise

frequency crosses the series resonant point of an individual

capacitor it’s overall impedance begins to look inductive and

thus increases with increasing frequency. The parallel

capacitor combination shown ensures that a low impedance

path to ground exists for frequencies well above the

bandwidth of the PLL. It is recommended that the user start

with an 8–10Ω resistor to avoid potential V

and only move to the higher value resistors when a higher

level of attenuation is shown to be needed.

drop problems

CC

Table 3. Crystal Recommendation

Parameter

Value

Fundamental AT Cut

Series Resonance*

±75ppm at 25°C

±150ppm 0 to 70°C

0 to 70°C

Crystal Cut

Resonance

3.3V

Frequency Tolerance

Frequency/Temperature Stability

Operating Range

R =5–15Ω

S

VCCA

MPC950

Shunt Capacitance

5–7pF

22µF

Equivalent Series Resistance (ESR)

Correlation Drive Level

Aging

50 to 80Ω Max

100µW

0.01µF

5ppm/Yr (First 3 Years)

VCC

0.01µF

* See accompanying text for series versus parallel resonant

discussion.

Figure 8. Power Supply Filter

The MPC950 is a clock driver which was designed to

generate outputs with programmable frequency relationships

and not a synthesizer with a fixed input frequency. As a result

the crystal input frequency is a function of the desired output

frequency. To determine the crystal required to produce the

desired output frequency for an application which utilizes

internal feedback the block diagram of Figure 9 should be

used. The P and the M values for the MPC950 are also

Although the MPC950 has several design features to

minimize the susceptibility to power supply noise (isolated

power and grounds and fully differential PLL) there still may

be applications in which overall performance is being

degraded due to system power supply noise. The power

supply filter schemes discussed in this section should be

MOTOROLA

8

TIMING SOLUTIONS

MPC950

included in Figure 9. The M values can be found in the

configuration tables included in this applications section.

technique terminates the signal at the end of the line with a

50Ω resistance to VCC/2. This technique draws a fairly high

level of DC current and thus only a single terminated line can

be driven by each output of the MPC950 clock driver. For the

series terminated case however there is no DC current draw,

thus the outputs can drive multiple series terminated lines.

Figure 10 illustrates an output driving a single series

terminated line vs two series terminated lines in parallel.

When taken to its extreme the fanout of the MPC950 clock

driver is effectively doubled due to its capability to drive

multiple lines.

f

ref

VCO

÷P

÷N

Qn

Phase

Detector

LPF

÷m

f

VCO

m

f

,

f

fQn · N · P

ref

VCO

MPC950

OUTPUT

BUFFER

fQn · N · P

m

f

ref

Z

= 50Ω

O

R = 43Ω

S

m = 8 (FBsel = ‘1’), 16(FBsel = ‘0’)

P = 1

7Ω

IN

OutA

Figure 9. PLL Block Diagram

MPC950

OUTPUT

BUFFER

For the MPC950 clock driver, the following will provide an

example of how to determine the crystal frequency required

for a given design.

Z

O

= 50Ω

R = 43Ω

S

OutB0

OutB1

7Ω

Given:

Z

O

R = 43Ω

S

Qa = 160MHz

Qb = 80MHz

Qc = 40MHz

Qd = 40MHz

FBSel = ‘0’

Figure 10. Single versus Dual Transmission Lines

fQn · N · P

The waveform plots of Figure 11 show the simulation

results of an output driving a single line vs two lines. In both

cases the drive capability of the MPC950 output buffers is

more than sufficient to drive 50Ω transmission lines on the

incident edge. Note from the delay measurements in the

simulations a delta of only 43ps exists between the two

differently loaded outputs. This suggests that the dual line

driving need not be used exclusively to maintain the tight

output–to–output skew of the MPC950. The output waveform

in Figure 11 shows a step in the waveform, this step is

caused by the impedance mismatch seen looking into the

driver. The parallel combination of the 43Ω series resistor

plus the output impedance does not match the parallel

combination of the line impedances. The voltage wave

launched down the two lines will equal:

f

ref

From Table 3

fQd = VCO/8 then N = 8 OR fQa = VCO/2 then N = 2

From Figure 9

m

m = 16 and P = 1

40 · 8 · 1

16

160 · 2 · 1

16

f

20MHz OR

20MHz

ref

Driving Transmission Lines

The MPC950 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user the output

drivers were designed to exhibit the lowest impedance

possible. With an output impedance of approximately 10Ω

the drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

lines the reader is referred to application note AN1091 in the

Timing Solutions brochure (BR1333/D).

VL = VS ( Zo / (Rs + Ro +Zo))

Zo = 50Ω || 50Ω

Rs = 43Ω || 43Ω

Ro = 7Ω

VL = 3.0 (25 / (21.5 + 7 + 25) = 3.0 (25 / 53.5)

= 1.40V

In most high performance clock networks point–to–point

distribution of signals is the method of choice. In a

point–to–point scheme either series terminated or parallel

terminated transmission lines can be used. The parallel

At the load end the voltage will double, due to the near

unity reflection coefficient, to 2.8V. It will then increment

towards the quiescent 3.0V in steps separated by one round

trip delay (in this case 4.0ns).

TIMING SOLUTIONS

BR1333 — Rev 6

9

MOTOROLA

MPC950

3.0

2.5

2.0

1.5

1.0

0.5

0

better match the impedances when driving multiple lines the

situation in Figure 12 should be used. In this case the series

terminating resistors are reduced such that when the parallel

combination is added to the output buffer impedance the line

impedance is perfectly matched.

OutA

= 3.8956

OutB

= 3.9386

t

D

t

D

In

MPC950

OUTPUT

BUFFER

Z

= 50Ω

O

R = 36Ω

S

7Ω

Z

O

R = 36Ω

S

7Ω + 36Ω 36Ω = 50Ω 50Ω

25Ω = 25Ω

2

4

6

8

10

12

14

Figure 12. Optimized Dual Line Termination

TIME (nS)

SPICE level output buffer models are available for

engineers who want to simulate their specific interconnect

schemes. In addition IV characteristics are in the process of

being generated to support the other board level simulators in

general use.

Figure 11. Single versus Dual Waveforms

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To

MOTOROLA

10

TIMING SOLUTIONS

MPC950

OUTLINE DIMENSIONS

FA SUFFIX

LQFP PACKAGE

CASE 873A–02

ISSUE A

BASE

METAL

4X

A

A1

0.20 (0.008) AB T–U

Z

N

32

25

1

F

D

AE

–U–

V1

–T–

P

B

V

J

B1

DETAIL Y

–Z–

DETAIL Y

17

8

SECTION AE–AE

R

8X M

9

4X

0.20 (0.008) AC T–U

Z

9

S1

E

C

S

DETAIL AD

G

W

–AB–

–AC–

Q

K

H

SEATING

PLANE

X

0.10 (0.004) AC

DETAIL AD

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

MILLIMETERS

INCHES

MIN MAX

0.276 BSC

0.138 BSC

0.276 BSC

0.138 BSC

DIM MIN

MAX

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED

AT DATUM PLANE –AB–.

A

A1

B

B1

C

D

E

F

7.000 BSC

3.500 BSC

7.000 BSC

3.500 BSC

1.400 1.600 0.055 0.063

0.300 0.450 0.012 0.018

1.350 1.450 0.053 0.057

0.300 0.400 0.012 0.016

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE –AC–.

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 (0.010) PER SIDE. DIMENSIONS A AND B

DO INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE –AB–.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE D DIMENSION TO EXCEED

0.520 (0.020).

8. MINIMUM SOLDER PLATE THICKNESS SHALL BE

0.0076 (0.0003).

9. EXACT SHAPE OF EACH CORNER MAY VARY

FROM DEPICTION.

G

H

J

K

M

N

P

Q

R

S

S1

V

V1

W

X

0.800 BSC

0.031 BSC

0.050 0.150 0.002 0.006

0.090 0.200 0.004 0.008

0.500 0.700 0.020 0.028

12 REF

0.090 0.160 0.004 0.006

0.400 BSC 0.016 BSC

12 REF

1

5

1

5

0.150 0.250 0.006 0.010

9.000 BSC

4.500 BSC

9.000 BSC

4.500 BSC

0.200 REF

1.000 REF

0.354 BSC

0.177 BSC

0.354 BSC

0.177 BSC

0.008 REF

0.039 REF

TIMING SOLUTIONS

BR1333 — Rev 6

11

MOTOROLA

MPC950

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or

guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the

applicationor use of any product or circuit, and specifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidental

damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in differentapplications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application

by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are

not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where

personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application,

BuyershallindemnifyandholdMotorolaanditsofficers, employees, subsidiaries, affiliates, anddistributorsharmlessagainstallclaims, costs,

damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated

with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the

part. Motorola and

are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;

JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1,

P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569

Technical Information Center: 1–800–521–6274

ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre,

2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

852–26668334

HOME PAGE: http://www.motorola.com/semiconductors/

MOTOROLA

12

TIMING SOLUTIONS

◊

MPC950/D


型号：	MPC950FA
厂家：	NXP
描述：	IC,CPU SYSTEM CLOCK GENERATOR,CMOS,QFP,32PIN,PLASTIC 时钟外围集成电路晶体
文件：	总12页 (文件大小：141K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MPC950FA [NXP]

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