MPC952FA [NXP]
952 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32;
| 型号： | MPC952FA |
| 厂家： | 
NXP |
| 描述： | 952 SERIES, PLL BASED CLOCK DRIVER, 11 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32 PC 驱动 输出元件 逻辑集成电路 |
| 文件： | 总8页 (文件大小：250K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MPC952/D
The MPC952 is a 3.3V compatible, PLL based clock driver device
targeted for high performance clock tree applications. The device
features a fully integrated PLL with no external components required.
With output frequencies of up to 180MHz and eleven low skew outputs
the MPC952 is well suited for high performance designs. The device
employs a fully differential PLL design to optimize jitter and noise
rejection performance. Jitter is an increasingly important parameter as
more microprocessors and ASiC’s are employing on chip PLL clock
distribution.
LOW VOLTAGE
PLL CLOCK DRIVER
• Fully Integrated PLL
• Output Frequency up to 180MHz
• High Impedance Disabled Outputs
• Compatible with PowerPC , Intel and High Performance RISC
Microprocessors
• Output Frequency Configurable
• LQFP Packaging
• ±100ps Cycle–to–Cycle Jitter
FA SUFFIX
LQFP PACKAGE
CASE 873A-02
The MPC952 features three banks of individually configurable outputs.
The banks contain 5 outputs, 4 outputs and 2 outputs. The internal divide
circuitry allows for output frequency ratios of 1:1, 2:1, 3:1 and 3:2:1. The
output frequency relationship is controlled by the fsel frequency control
pins. The fsel pins as well as the other inputs are LVCMOS/LVTTL
compatible inputs.
The MPC952 uses external feedback to the PLL. This features allows
for the use of the device as a “zero delay” buffer. Any of the eleven
outputs can be used as the feedback to the PLL. The VCO_Sel pin allows for the choice of two VCO ranges to optimize PLL
stability and jitter performance. The MR/OE pin allows the user to force the outputs into high impedance for board level test.
For system debug the PLL of the MPC952 can be bypassed. When forced to a logic HIGH, the PLLEN input will route the
signal on the RefClk input around the PLL directly to the internal dividers. Because the signal is routed through the dividers, it
may take several transitions of the RefClk to affect a transition on the outputs. This features allows a designer to single step the
design for debug purposes.
The outputs of the MPC952 are LVCMOS outputs. The outputs are optimally designed to drive terminated transmission lines.
For applications using series terminated transmission lines each MPC952 output can drive two lines. This capability provides an
effective fanout of 22, more than enough clocks for most clock tree designs. For more information on driving transmission lines
consult the applications section of this data sheet.
PowerPC is a trademark of International Business Machines Corporation. Pentium is a trademark of Intel Corporation.
03/01
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Freescale Semiconductor, Inc.
MPC952
Figure 1. MPC952 Logic Diagram
PLL_En
REFCLK
VCO
200–480MHz
PHASE
DETECTOR
Qa0
Qa1
Qa2
Qa3
Qa4
÷4/÷6
÷2
FBin
LPF
(Int Pull Down)
(Int Pull Down)
VCO_Sel
fsela
Qb0
Qb1
Qb2
Qb3
÷4/÷2
(Int Pull Down)
fselb
Qc0
Qc1
÷2/÷4
(Int Pull Down)
(Int Pull Down)
fselc
MR/OE
FUNCTION TABLES
fsela
Qan
fselb Qbn
fselc Qcn
24 23 22 21 20 19 18 17
VCCO
Qb2
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VCCO
Qa2
0
1
÷4
÷6
0
1
÷4
÷2
0
1
÷2
÷4
Control Pin
VCO_Sel
MR/OE
Logic ‘0’
fVCO
Logic ‘1’
fVCO/2
Qb3
Qa1
GNDO
GNDO
Qc0
GNDO
Qa0
Output Enable
Enable PLL
High Z
MPC952
PLL_En
Disable PLL
VCCI
VCCA
PLL_En
Pin Name
VCCA
VCCO
VCCI
Description
PLL Power Supply
Qc1
VCCO
Output Buffer Power Supply
Internal Core Logic Power Supply
Internal Ground
1
2
3
4
5
6
7
8
GNDI
GNDO
Output Buffer Ground
Figure 2. 32–Lead Pinout (Top View)
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MPC952
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
–0.3
–0.3
Max
Unit
V
V
V
Supply Voltage
Input Voltage
Input Current
4.6
CC
V
+ 0.3
V
I
CC
I
IN
±20
mA
°C
T
Stor
Storage Temperature Range
–40
125
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not
implied.
THERMAL CHARACTERISTICS
Proper thermal management is critical for reliable system operation. This is especially true for high fanout and high drive
capability products. Generic thermal information is available for the Motorola Clock Driver products. The means of calculating die
power, the corresponding die temperature and the relationship to longterm reliability is addressed in the Motorola application
note AN1545.
DC CHARACTERISTICS (T = 0° to 70°C, V
CCO
= V
= V = 3.3V ±5%)
CCA
A
CCI
Symbol
Characteristic
Input HIGH Voltage
Min
Typ
Max
3.6
Unit
V
Condition
V
V
V
V
2.0
IH
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input Current
0.8
V
IL
2.4
V
I
I
= –20mA (Note 1.)
= 20mA (Note 1.)
OH
OL
OH
0.5
±120
4.0
V
OL
I
IN
µA
pF
pF
mA
mA
Note 2.
C
C
Input Capacitance
2.7
25
IN
pd
Power Dissipation Capacitance
I
I
Maximum Quiescent Supply Current
PLL Supply Current
160
20
Total ICC Static Current
CC
15
CCA
1. The MPC952 outputs can drive series or parallel terminated 50Ω (or 50Ω to V
Info section).
/2) transmission lines on the incident edge (see Applications
CCO
2. Inputs have pull–up, pull–down resistors which affect input current.
PLL INPUT REFERENCE CHARACTERISTICS (T = 0 to 70°C)
A
Symbol
Characteristic
TCLK Input Rise/Falls
Min
Max
3.0
100
75
Unit
ns
Condition
t , t
r f
f
Reference Input Frequency
Reference Input Duty Cycle
MHz
%
Note 3.
ref
f
25
refDC
3. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.
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MPC952
AC CHARACTERISTICS (T = 0° to 70°C, V
CCO
= V
= V = 3.3V ±5%)
CCA
A
CCI
Symbol
Characteristic
Output Rise/Fall Time (Note 4.)
Output Pulse Width (Note 4.)
Min
Typ
Max
Unit
ns
Condition
0.8 to 2.0V
t , t
r f
0.10
1.0
t
t
/2
t
/2
t
/2
ps
pw
CYCLE
–750
CYCLE
±500
CYCLE
+750
t
os
Output-to-Output Skew
(Note 4.)
Excluding Qa0
All Outputs
350
450
550
ps
Same Frequencies
Same Frequencies
Different Frequencies
All Outputs
f
f
PLL VCO Lock Range
200
480
MHz
MHz
Note 6.
Note 4.
VCO
Maximum Output Frequency
Qc,Qb (÷2)
Qa,Qb,Qc (÷4)
Qa (÷6)
180
120
80
max
t
t
t
t
t
REFCLK to FBIN Delay
Output Disable Time
Output Enable Time
–200
0
200
8
ps
ns
ns
ps
ms
Notes 4., 5.
Note 4.
pd
, t
PLZ PHZ
2
2
, t
10
Note 4.
PZL PLH
Cycle–to–Cycle Jitter
Maximum PLL Lock Time
±100
jit(cc)
lock
10
4. Termination of 50Ω to V
/2.
CCO
5. t isspecifiedfor50MHzinputref,thewindowwillshrink/growproportionallyfromtheminimumlimitwithshorter/longerinputreferenceperiods.
pd
The t does not include jitter.
pd
6. The PLL may be unstable with a divide by 2 feedback ratio.
APPLICATIONS INFORMATION
Driving Transmission Lines
technique terminates the signal at the end of the line with a
50Ω resistance to V /2. This technique draws a fairly high
CCO
The MPC952 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of approximately 7Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091.
level of DC current and thus only a single terminated line can
be driven by each output of the MPC952 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 3 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC952 clock
driver is effectively doubled due to its capability to drive
multiple lines.
MPC952
OUTPUT
BUFFER
The waveform plots of Figure 4 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC952 output buffers is
more than sufficient to drive 50Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC952. The output waveform
in Figure 4 shows a step in the waveform, this step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 43Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
Z
= 50Ω
O
R = 43Ω
S
7Ω
IN
IN
OutA
MPC952
OUTPUT
BUFFER
Z
O
= 50Ω
= 50Ω
R = 43Ω
S
OutB0
OutB1
7Ω
Z
O
R = 43Ω
S
VL = VS (Zo / Rs + Ro +Zo) = 3.0 (25/53.5) = 1.40V
Figure 3. Single versus Dual Transmission Lines
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.8V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
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MPC952
technique is to try and isolate the high switching noise digital
outputs from the relatively sensitive internal analog
phase–locked loop. In a controlled environment such as an
evaluation board this level of isolation is sufficient. However,
in a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of
isolation may be required. The simplest form of isolation is a
power supply filter on the VCCA pin for the MPC952.
3.0
2.5
2.0
1.5
1.0
0.5
0
OutA
= 3.8956
OutB
= 3.9386
t
D
t
D
In
3.3V
R =5–15Ω
S
VCCA
MPC952
22µF
0.01µF
2
4
6
8
10
12
14
TIME (nS)
VCC
Figure 4. Single versus Dual Waveforms
0.01µF
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 5 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
Figure 6. Power Supply Filter
Figure 6 illustrates a typical power supply filter scheme.
The MPC952 is most susceptible to noise with spectral
content in the 1KHz to 1MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the V
pin of the MPC952. From the data sheet the I
VCCA
supply and the VCCA
current
CC
MPC952
OUTPUT
BUFFER
(the current sourced through the VCCA pin) is typically 15mA
(20mA maximum), assuming that a minimum of 3.3V – 5%
must be maintained on the VCCA pin very little DC voltage
Z
= 50Ω
= 50Ω
O
R = 36Ω
S
drop can be tolerated when a 3.3V V
supply is used. The
CC
7Ω
resistor shown in Figure 6 must have a resistance of 5–15Ω
to meet the voltage drop criteria. The RC filter pictured will
provide a broadband filter with approximately 100:1
attenuation for noise whose spectral content is above 20KHz.
As the noise frequency crosses the series resonant point of
an individual capacitor it’s overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL.
Z
O
R = 36Ω
S
7Ω + 36Ω 36Ω = 50Ω 50Ω
25Ω = 25Ω
Figure 5. Optimized Dual Line Termination
Power Supply Filtering
Although the MPC952 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related problems
in most designs.
The MPC952 is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC952 provides separate
power supplies for the output buffers (V ) and the internal
PLL (VCCA) of the device. The purpose of this design
CCO
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MPC952
OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 873A-02
ISSUE A
4X
A
A1
0.20 (0.008) AB T–U
Z
32
25
1
–U–
V
–T–
B
AE
AE
P
B1
DETAIL Y
–Z–
V1
17
8
DETAIL Y
9
4X
0.20 (0.008) AC T–U
Z
9
NOTES:
S1
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
DETAIL AD
G
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
–AB–
–AC–
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
SEATING
PLANE
0.10 (0.004) AC
BASE
METAL
N
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
F
D
8X M
MILLIMETERS
DIM MIN MAX
7.000 BSC
INCHES
MIN MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
R
J
A
A1
B
3.500 BSC
7.000 BSC
3.500 BSC
SECTION AE–AE
E
C
B1
C
1.400
1.600 0.055
0.063
0.018
0.057
0.016
D
E
F
0.300
1.350
0.300
0.450 0.012
1.450 0.053
0.400 0.012
W
G
H
J
K
M
N
P
0.800 BSC
0.031 BSC
Q
H
K
X
0.050
0.090
0.500
0.150 0.002
0.200 0.004
0.700 0.020
0.006
0.008
0.028
12 REF
12 REF
0.006
0.016 BSC
DETAIL AD
0.090
0.160 0.004
0.400 BSC
Q
R
1
5
1
5
0.150
0.250 0.006
0.010
S
9.000 BSC
0.354 BSC
S1
V
V1
W
X
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
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MPC952
NOTES
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MPC952
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
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MPC952/D
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