MPC958FA [MOTOROLA]
PLL Based Clock Driver, MPC900 Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, LQFP-32;
| 型号： | MPC958FA |
| 厂家： | 
MOTOROLA |
| 描述： | PLL Based Clock Driver, MPC900 Series, 10 True Output(s), 0 Inverted Output(s), PQFP32, 7 X 7 MM, LQFP-32 PC |
| 文件： | 总8页 (文件大小：103K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Order this document
by MPC958/D
SEMICONDUCTOR TECHNICAL DATA
The MPC958 is a 3.3V compatible, PLL based clock driver device
targeted for high performance clock tree designs. With output frequencies
of up to 200MHz and output skews of 200ps the MPC958 is ideal for the
most demanding clock tree designs. The devices employ a fully
differential PLL design to minimize cycle–to–cycle and phase jitter.
LOW VOLTAGE
PLL CLOCK DRIVER
• Fully Integrated PLL
• Output Frequency up to 200MHz
• Outputs Disable in High Impedance
• LQFP Packaging
• 100ps Cycle–to–Cycle Jitter
The MPC958 has a differential LVPECL reference input along with an
external feedback input. These features make the MPC958 ideal for use
as a zero delay, low skew fanout buffer. The device performance has
been tuned and optimized for zero delay performance. The MR/OE input
pin will tristate the output buffers when driven “high”.
FA SUFFIX
32–LEAD LQFP PACKAGE
CASE 873A–02
The MPC958 is fully 3.3V compatible and requires no external loop
filter components. All control inputs accept LVCMOS or LVTTL
compatible levels while the outputs provide LVCMOS levels with the
ability to drive terminated 50Ω transmission lines. For series terminated
50Ω lines, each of the MPC958 outputs can drive two traces giving the
device an effective fanout of 1:22. The device is packaged in a 7x7mm
32–lead LQFP package to provide the optimum combination of board
density and performance.
QFB
Q0:8
Q9
(Int pull up)
PECL_CLK
PECL_CLK
0
0
(Int pull down)
9
Phase
Detector
0
VCO
200–400MHz
1
1
LPF
÷2
(Int pull up)
1
÷2
FB_CLK
(Int pull up)
(Int pull up)
(Int pull down)
(Int pull up)
VCO_SEL
BYPASS
MR/OE
PLL_EN
Figure 1. Logic Diagram
06/00
Motorola, Inc. 2000
REV 1
MPC958
FUNCTION TABLES
BYPASS
Function
24 23 22 21 20 19 18 17
GNDO
Q1
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
Q6
1
0
PLL Enabled
PLL Bypass
VCCO
Q7
MR/OE
Function
VCCO
Q0
1
0
Outputs Disabled
Outputs Enabled
GNDO
Q8
MPC958
GNDO
QFB
VCO_SEL
Function
1
0
÷2
÷1
VCCO
VCCO
Q9
PLL_EN
Function
VCO_SEL
GNDO
1
0
Select VCO
Select PECL_CLK
1
2
3
4
5
6
7
8
Figure 2. 32–Lead Pinout (Top View)
ABSOLUTE MAXIMUM RATINGS*
Symbol
Parameter
Min
–0.3
–0.3
Max
Unit
V
V
V
Supply Voltage
Input Voltage
Input Current
4.6
CC
V
+ 0.3
V
I
CC
±20
125
I
IN
mA
°C
T
Stor
Storage Temperature Range
–40
* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or
conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied.
THERMAL CHARACTERISTICS
Proper thermal management is critical for reliable system operation. This is especially true for high fanout and high drive
capability products. Generic thermal information is available for the Motorola Clock Driver products. The means of calculating die
power, the corresponding die temperature and the relationship to longterm reliability is addressed in the Motorola application
note AN1545.
MOTOROLA
2
TIMING SOLUTIONS
MPC958
DC CHARACTERISTICS (T = 0° to 70°C, V
CC
= 3.3V ±5%)
A
Symbol
Characteristic
Min
Typ
Max
3.6
Unit
V
Condition
V
V
V
V
V
V
Input HIGH Voltage LVCMOS Inputs
Input LOW Voltage LVCMOS Inputs
2.0
IH
0.8
V
IL
Peak–to–Peak Input Voltage PECL_CLK
300
1.0
2.4
1000
3.0
mV
V
PP
CMR
OH
OL
Common Mode Range
Output HIGH Voltage
Output LOW Voltage
Input Current
PECL_CLK
Note 1.
V
I
I
= –20mA, Note 2.
= 20mA, Note 2.
OH
0.5
±120
4
V
OL
I
IN
µA
pF
pF
mA
mA
C
C
Input Capacitance
IN
Power Dissipation Capacitance
Maximum Quiescent Supply Current
Maximum PLL Supply Current
25
15
Per Output
pd
I
I
75
20
All VCC Pins
VCCA Pin Only
CC
CCPLL
1. V
CMR
isthecenterofthedifferentialinputsignal. NormaloperationisobtainedwhentheinputcrosspointiswithintheV rangeandtheinput
CMR
swing lies within the V
PP
specification.
2. The MPC958 outputs can drive series or parallel terminated 50Ω (or 50Ω to V /2) transmission lines on the incident edge (see Applications
CC
Info section).
PLL INPUT REFERENCE CHARACTERISTICS (T = 0 to 70°C)
A
Symbol
Characteristic
Reference Input Frequency
Reference Input Duty Cycle
Min
Note 3.
25
Max
Note 3.
75
Unit
MHz
%
Condition
f
f
ref
refDC
3. Maximum and minimum input reference is limited by the VCO lock range and the feedback divider.
AC CHARACTERISTICS (T = 0°C to 70°C, V
CC
= 3.3V ±5%)
A
Symbol
Characteristic
Output Rise/Fall Time
Min
Typ
Max
Unit
Condition
t , t
r f
0.10
1.0
ns
0.8 to 2.0V
Note 4.
t
Output Duty Cycle
PLL Mode tcycle/2 –
400
tcycle/2 +
400
ps
Note 4.
pw
t
f
f
Output–to–Output Skews (Relative to QFB)
PLL VCO Lock Range
200
400
ps
Note 4.
sk(O)
VCO
max
200
MHz
MHz
Maximum Output Frequency
(Note 4.)
PLL Mode
PLL Mode
50
100
100
200
200
VCO_SEL = ‘1’
VCO_SEL = ‘0’
Bypass Mode
t
t
t
t
t
t
(lock)
Input to Ext_FB Delay (with PLL Locked @ 100MHz)
Input to Q Delay
–70
3.0
130
7.0
7
ps
ns
ns
ns
ps
ms
Note 4.
pd
(bypass)
pd
PLL Bypassed
,
Output Disable Time
PLZ HZ
Output Enable Time
6
PZL
Cycle–to–Cycle Jitter (Peak–to–Peak)
Maximum PLL Lock Time
100
10
Note 4.
jitter
lock
4. Termination of 50 to V /2.
CC
3
MOTOROLA
MPC958
Power Supply Filtering
be applications in which overall performance is being
degraded due to system power supply noise. The power
supply filter schemes discussed in this section should be
adequate to eliminate power supply noise related problems
in most designs.
The MPC958 is a mixed analog/digital product and as
such it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is naturally
susceptible to random noise, especially if this noise is seen
on the power supply pins. The MPC958 provides a separate
power supply for the phase–locked loop (VCCA) of the
device. The purpose of this design technique is to try and
isolate the high switching noise digital outputs from the
relatively sensitive internal analog phase–locked loop. In a
controlled environment such as an evaluation board this level
of isolation is sufficient. However, in a digital system
environment where it is more difficult to minimize noise on the
power supplies a second level of isolation may be required.
The simplest form of isolation is a power supply filter on the
VCCA pin for the MPC958.
Driving Transmission Lines
The MPC958 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of approximately 20Ω
the drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to application note AN1091 in the
Timing Solutions brochure (BR1333/D).
In most high performance clock networks point–to–point
distribution of signals is the method of choice. In a
point–to–point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC/2. This technique draws a fairly high
level of DC current and thus only a single terminated line can
be driven by each output of the MPC958 clock driver. For the
series terminated case however there is no DC current draw,
thus the outputs can drive multiple series terminated lines.
Figure 4 illustrates an output driving a single series
terminated line vs two series terminated lines in parallel.
When taken to its extreme the fanout of the MPC958 clock
driver is effectively doubled due to its capability to drive
multiple lines.
Figure 3 illustrates a typical power supply filter scheme.
The MPC958 is most susceptible to noise with spectral
content in the 1KHz to 1MHz range. Therefore the filter
should be designed to target this range. The key parameter
that needs to be met in the final filter design is the DC voltage
drop that will be seen between the V
pin of the MPC958. From the data sheet the I
supply and the VCCA
current
CC
VCCA
(the current sourced through the VCCA pin) is typically 15mA
(20mA maximum), assuming that a minimum of 3.0V must be
maintained on the VCCA pin very little DC voltage drop can
be tolerated when a 3.3V V
supply is used. The resistor
CC
shown in Figure 3 must have a resistance of 10–15Ω to meet
the voltage drop criteria. The RC filter pictured will provide a
broadband filter with approximately 100:1 attenuation for
noise whose spectral content is above 20KHz. As the noise
frequency crosses the series resonant point of an individual
capacitor it’s overall impedance begins to look inductive and
thus increases with increasing frequency. The parallel
capacitor combination shown ensures that a low impedance
path to ground exists for frequencies well above the
bandwidth of the PLL. It is recommended that the user start
MPC958
OUTPUT
BUFFER
Z
O
= 50Ω
R = 36Ω
S
14Ω
IN
IN
OutA
with an 8–10Ω resistor to avoid potential V
and only move to the higher value resistors when a higher
level of attenuation is shown to be needed.
drop problems
CC
MPC958
OUTPUT
BUFFER
Z
= 50Ω
= 50Ω
O
R = 36Ω
S
OutB0
OutB1
3.3V
14Ω
Z
O
R = 36Ω
S
R =5–15Ω
S
V
CCA
22µF
0.01µF
MPC958
Figure 4. Single versus Dual Transmission Lines
The waveform plots of Figure 5 show the simulation
results of an output driving a single line vs two lines. In both
cases the drive capability of the MPC958 output buffers is
more than sufficient to drive 50Ω transmission lines on the
incident edge. Note from the delay measurements in the
simulations a delta of only 43ps exists between the two
differently loaded outputs. This suggests that the dual line
driving need not be used exclusively to maintain the tight
output–to–output skew of the MPC958. The output waveform
in Figure 5 shows a step in the waveform, this step is caused
VCC
0.01µF
Figure 3. Power Supply Filter
Although the MPC958 has several design features to
minimize the susceptibility to power supply noise (isolated
power and grounds and fully differential PLL) there still may
MOTOROLA
4
TIMING SOLUTIONS
MPC958
by the impedance mismatch seen looking into the driver. The
parallel combination of the 43Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To
better match the impedances when driving multiple lines the
situation in Figure 6 should be used. In this case the series
terminating resistors are reduced such that when the parallel
combination is added to the output buffer impedance the line
impedance is perfectly matched.
VL = VS ( Zo / (Rs + Ro +Zo))
Zo = 50Ω || 50Ω
Rs = 36Ω || 36Ω
Ro = 14Ω
MPC958
OUTPUT
BUFFER
VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)
= 1.31V
Z
= 50Ω
= 50Ω
O
R = 22Ω
S
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.62V. It will then increment
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
14Ω
Z
O
R = 22Ω
S
3.0
OutA
= 3.8956
14Ω + 22Ω 22Ω = 50Ω 50Ω
25Ω = 25Ω
OutB
= 3.9386
t
D
2.5
2.0
1.5
1.0
0.5
0
t
D
Figure 6. Optimized Dual Line Termination
In
SPICE level output buffer models are available for
engineers who want to simulate their specific interconnect
schemes. In addition IV characteristics are in the process of
being generated to support the other board level simulators in
general use.
2
4
6
8
10
12
14
TIME (nS)
Figure 5. Single versus Dual Waveforms
5
MOTOROLA
MPC958
OUTLINE DIMENSIONS
FA SUFFIX
LQFP PACKAGE
CASE 873A–02
ISSUE A
4X
A
A1
0.20 (0.008) AB T–U Z
32
25
1
–U–
V
–T–
B
AE
AE
P
B1
DETAIL Y
–Z–
V1
17
8
DETAIL Y
9
4X
0.20 (0.008) AC T–U Z
9
NOTES:
S1
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
S
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD
WHERE THE LEAD EXITS THE PLASTIC BODY AT
THE BOTTOM OF THE PARTING LINE.
4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED
AT DATUM PLANE –AB–.
DETAIL AD
G
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE –AC–.
–AB–
–AC–
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.250 (0.010) PER SIDE. DIMENSIONS A AND B
DO INCLUDE MOLD MISMATCH AND ARE
DETERMINED AT DATUM PLANE –AB–.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. DAMBAR PROTRUSION SHALL
NOT CAUSE THE D DIMENSION TO EXCEED
0.520 (0.020).
SEATING
PLANE
0.10 (0.004) AC
BASE
METAL
N
8. MINIMUM SOLDER PLATE THICKNESS SHALL BE
0.0076 (0.0003).
9. EXACT SHAPE OF EACH CORNER MAY VARY
FROM DEPICTION.
F
D
8X M
MILLIMETERS
DIM MIN MAX
7.000 BSC
INCHES
MIN MAX
0.276 BSC
0.138 BSC
0.276 BSC
0.138 BSC
R
J
A
A1
B
3.500 BSC
7.000 BSC
3.500 BSC
SECTION AE–AE
E
C
B1
C
1.400
1.600 0.055
0.063
0.018
0.057
0.016
D
E
F
0.300
1.350
0.300
0.450 0.012
1.450 0.053
0.400 0.012
W
G
H
J
K
M
N
P
0.800 BSC
0.031 BSC
Q
H
K
X
0.050
0.090
0.500
0.150 0.002
0.200 0.004
0.700 0.020
0.006
0.008
0.028
12 REF
12 REF
0.006
0.016 BSC
DETAIL AD
0.090
0.160 0.004
0.400 BSC
Q
R
1
5
1
5
0.150
0.250 0.006
0.010
S
9.000 BSC
0.354 BSC
S1
V
V1
W
X
4.500 BSC
9.000 BSC
4.500 BSC
0.200 REF
1.000 REF
0.177 BSC
0.354 BSC
0.177 BSC
0.008 REF
0.039 REF
MOTOROLA
6
TIMING SOLUTIONS
MPC958
NOTES
7
MOTOROLA
MPC958
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specificallydisclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
datasheetsand/orspecificationscananddovaryindifferentapplicationsandactualperformancemayvaryovertime. Alloperatingparameters,including“Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applicationsintended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
ordeathmayoccur. ShouldBuyerpurchaseoruseMotorolaproductsforanysuchunintendedorunauthorizedapplication,BuyershallindemnifyandholdMotorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Opportunity/Affirmative Action Employer.
are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal
Mfax is a trademark of Motorola, Inc.
How to reach us:
USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;
JAPAN: Motorola Japan Ltd.; SPD, Strategic Planning Office, 141,
P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 4–32–1 Nishi–Gotanda, Shinagawa–ku, Tokyo, Japan. 81–3–5487–8488
Customer Focus Center: 1–800–521–6274
Mfax : RMFAX0@email.sps.mot.com – TOUCHTONE 1–602–244–6609
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre,
Motorola Fax Back System
– US & Canada ONLY 1–800–774–1848 2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
– http://sps.motorola.com/mfax/
852–26668334
HOME PAGE: http://motorola.com/sps/
MPC958/D
◊
相关型号：
MPC958FAR2
958 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, PLASTIC, LQFP-32
NXP
MPC958FAR2
MPC900 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32
MOTOROLA
MPC9600FAR2
PLL Based Clock Driver, 21 True Output(s), 0 Inverted Output(s), CMOS, PQFP48, PLASTIC, LQFP-48
MOTOROLA
MPC9600FAR2
9600 SERIES, PLL BASED CLOCK DRIVER, 21 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48, PLASTIC, LQFP-48
NXP
MPC9608AC
PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LEAD FREE, LQFP-32
MOTOROLA
MPC9608AC
9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LEAD FREE, PLASTIC, LQFP-32
NXP
MPC9608ACR2
PLL Based Clock Driver, 9608 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32, 7 X 7 MM, LEAD FREE, PLASTIC, LQFP-32
IDT
MPC9608ACR2
9608 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LEAD FREE, PLASTIC, LQFP-32
NXP
©2020 ICPDF网 联系我们和版权申明