MPC9600FAR2_技术文档

Freescale Semiconductor, Inc.

ꢀꢁꢂ ꢁ ꢃꢁ ꢄꢅ

Order Number: MPC9600/D

Rev. 2, 11/2001

SEMICONDUCTOR TECHNICAL DATA

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ꢏꢐ ꢈ ꢋ ꢑꢒ ꢓ ꢏꢓ ꢈ

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ꢛ

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The MPC9600 is a low voltage 2.5 V or 3.3 V compatible, 1:21 PLL

based clock driver and fanout buffer. With output frequencies up to 200

MHz and output skews of 150 ps, the device meets the needs of the most

demanding clock tree applications.

2

Features:

• Multiplication of input frequency by 2, 3, 4 and 6

3.3 V OR 2.5 V

LOW VOLTAGE CMOS

PLL CLOCK DRIVER

• Distribution of output frequency to 21 outputs organized in three output

banks: QA0-QA6, QB0-QB6, QC0-QC6, each fully selectable

• Fully integrated PLL

• Selectable output frequency range is 50 to 100 MHz and 100 to 200 MHz

• Selectable input frequency range is 16.67 to 33 MHz and 25 to 50 MHz

• LVCMOS outputs

• Outputs disable to high impedance (except QFB)

• LVCMOS or LVPECL reference clock options

• 48 lead QFP packaging

•

50 ps cycle-to-cycle jitter

• 150 ps maximum output-to-output skew

• 200 ps maximum static phase offset window

FA SUFFIX

48–LEAD LQFP PACKAGE

CASE 932–03

The MPC9600 is a fully LVCMOS 2.5 V or 3.3 V compatible PLL clock

driver. The MPC9600 has the capability to generate clock signals of 50 to

200 MHz from clock sources of 16.67 to 50 MHz. The internal PLL is

optimized for this frequency range and does not require external loop filter

components. QFB provides an output for the external feedback path to

the feedback input FB_IN. The QFB divider ratio is configurable and de-

termines the PLL frequency multiplication factor when QFB is directly

connected to FB_IN. The MPC9600 is optimized for minimizing the prop-

agation delay between the clock input and FB_IN.

Three output banks of 7 outputs each bank can be individually configured to divide the VCO frequency by 2 or by 4. Combining

the feedback and output divider ratios, the MPC9600 is capable to multiply the input frequency by 2, 3, 4 and 6.

The reference clock is selectable either LVPECL or LVCMOS. The LVPECL reference clock feature allows the designer to use

LVPECL fanout buffers for the inner branches of the clock distribution tree. All control inputs accept LVCMOS compatible levels.

The outputs provide low impedance LVCMOS outputs capable of driving parallel terminated 50 Ω transmission to V_TT=V_CC/2.

For series terminated lines the MPC9600 can drive two lines per output giving the device an effective total fanout of 1:42. With

guaranteed maximum output-to-output skew of 150 ps, the MPC9600 PLL clock driver meets the synchronization requirements

of the most demanding systems.

The V_CCAanalog power pin doubles as a PLL bypass select line for test purpose. When the V_CCAis driven to GND the refer-

ence clock will bypass the PLL.

The device is packaged in a 48-lead LQFP package to provide optimum combination of board density and performance.

Rev 2

174

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MPC9600

ꢎ

ꢁ

ꢈ

ꢎ ꢁꢁ

7

(pulldown)

(pulldn)

0

1

0

1

ꢁ ꢁ ꢂ ꢃ

ꢑ ꢈꢒ

ꢑ ꢈꢜ

ꢉ ꢕꢖ ꢗ ꢈ

/2

0

1

ꢀ

ꢂ

Ref

FB

ꢀꢁ ꢂ ꢃ

D

Q

/4

/8

ꢑ ꢈꢛ

ꢑ ꢈꢚ

Vcc/2

(pullup)

200 - 400 MHz

/12

ꢋ ꢅꢆ ꢊꢇꢅꢂ

ꢆ ꢉꢊꢌ ꢍ

(pulldown)

(pullup)

2

ꢑ ꢈꢙ

ꢑ ꢈꢘ

ꢆ ꢇꢅꢂꢈ

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0

1

D

Q

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7

(pullup)

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ꢆ ꢇꢅꢂ ꢁ

ꢉ

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0

1

D

Q

ꢑ

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0

1

D

Q

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ꢆ

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(pullup)

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ꢄꢅ

(pulldown)

8

ꢏ

ꢍ

ꢐ

Figure 1. MPC9600 Logic Diagram

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

175

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Freescale Semiconductor, Inc.

MPC9600

PIN CONFIGURATION

PCLK, PCLK

CCLK

FB_IN

QAn

I/O

Type

PECL

Description

Input

Output

Input

Differential reference clock frequency input

LVCMOS

Power supply

Ground

Reference clock input

PLL feedback clock input

Bank A outputs

QBn

Bank B outputs

QCn

Bank C outputs

2

QFB

Differential feedback output

REF_SEL

FSELA

FSELB

FSELC

FSEL_FB

OE

Reference clock input select

Selection of bank A output frequency

Selection of bank B output frequency

Selection of bank C output frequency

Selection of feedback frequency

Output enable

VCCA

VCC

Analog power supply and PLL bypass. An external VCC filter is recommended for VCCA

Core power supply

GND

Ground

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ꢙꢔ

ꢙꢡ

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ꢛ ꢚ

ꢛ ꢛ

ꢛ ꢜ

ꢛ ꢒ

ꢜ ꢣ

ꢜ ꢢ

ꢜ ꢡ

ꢜ ꢔ

ꢜ ꢘ

ꢜ ꢙ

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ꢑ ꢁꢒ

ꢑ ꢁꢜ

ꢑ ꢁꢛ

ꢎ ꢁꢁ

ꢑ ꢁꢚ

ꢑ ꢁꢙ

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ꢑ ꢁꢘ

ꢑ ꢁꢔ

ꢄ ꢅ

ꢎ ꢁꢁ

ꢑ ꢈꢔ

ꢑ ꢈꢘ

ꢑ ꢈꢙ

ꢏ ꢍꢐ

ꢑ ꢈꢚ

ꢑ ꢈꢛ

ꢎ ꢁꢁ

MPC9600

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ꢑ ꢈꢒ

ꢆ ꢉꢊ ꢌꢍ

ꢏ ꢍꢐ

ꢎ

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Figure 2. 48 Lead Package Pinout (Top View)

176

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

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Freescale Semiconductor, Inc.

MPC9600

FUNCTION TABLE (CONTROLS)

Control Pin

REF_SEL

VCCA

0

1

CCLK

PCLK

1

PLL Bypass

PLL Power

OE

Outputs Enabled

Outputs Disabled (except QFB)

Output Bank A at VCO/4

Output Bank B at VCO/4

Output Bank C at VCO/4

Feedback Output at VCO/12

FSELA

Output Bank A at VCO/2

Output Bank B at VCO/2

Output Bank C at VCO/2

Feedback Output at VCO/8

FSELB

FSELC

FSEL_FB

2

1. V

= GND, PLL off and bypassed for static test and diagnosis

CCA

Table 1: ABSOLUTE MAXIMUM RATINGS*

Symbol

Parameter

Min

Max

Unit

V

Supply Voltage

–0.3

4.6

CC

IN

DC Input Voltage

V

+ 0.3

V

CC

DC Output Voltage

DC Input Current

+ 0.3

20

V

OUT

I

mA

°C

IN

OUT

DC Output Current

Storage Temperature Range

50

T

–40

125

Stor

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or condi-

tions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is not im-

plied.

Table 2: GENERAL SPECIFICATIONS

Symbol

Characteristics

Output Termination Voltage

Min

Typ

B 2

Max

Unit

V

Condition

V

TT

V

CC

MM

HBM

CDM

LU

ESD Protection (Machine Model)

ESD Protection (Human Body Model)

ESD Protection (Charged Device Model)

Latch–Up Immunity

400

4000

1500

200

V

mA

pF

C

Power Dissipation Capacitance

Input Capacitance

10

Per output

Inputs

PD

C

4.0

IN

Table 3: DC CHARACTERISTICS (V_CC= 3.3 V 5%, T_A= –40° to +85°C)

Symbol

Characteristics

Input High Voltage

Min

Typ

Max

+ 0.3

CC

Unit

V

Condition

V

2.0

V

LVCMOS

IH

Input Low Voltage

0.8

V

LVCMOS

LVPECL

IL

Peak-to-peak Input Voltage (DC)

Common Mode Range (DC)

Output High Voltage

PCLK, PCLK

250

1.0

2.4

mV

V

PP

CMR

OH

OL

a

V

CC

-0.6

b

V

I

=-24 mA

OH

Output Low Voltage

0.55

0.30

V

I

OL

I

OL

= 24mA

= 12mA

Z

I

Output Impedance

14 – 17

2.0

W

OUT

Input Leakage Current

150

5.0

1.0

µA

mA

V

= V or GND

CC

IN

I

Maximum PLL Supply Current

Maximum Quiescent Supply Current

CCA

CCQ

I

All V Pins

CC

a. V

(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V

range

CMR

and the input swing lies within the V (DC) specification.

PP

b. The MPC9600 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmis-

sion line to a termination voltage of V . Alternatively, the device drives up to two 50Ω series terminated transmission lines.

TT

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

177

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MPC9600

Table 4: DC CHARACTERISTICS (V_CC= 2.5 V 5%, T_A= –40° to +85°C)

Symbol

Characteristics

Input High Voltage

Min

Typ

Max

V + 0.3

CC

Unit

V

Condition

LVCMOS

V

1.7

IH

Input Low Voltage

0.7

V

LVCMOS

LVPECL

IL

Peak-to-peak input voltage (DC)

Common Mode Range (DC)

Output High Voltage

PCLK, PCLK

250

1.0

1.8

mV

V

PP

a

V

CC

-0.6

CMR

OH

OL

b

V

I =-15 mA

OH

2

Output Low Voltage

0.6

V

I = 15 mA

OL

Z

I

Output Impedance

17 – 20

3.0

W

OUT

Input Leakage Current

150

5.0

1.0

µA

mA

V

= V or GND

CC

IN

I

Maximum PLL Supply Current

Maximum Quiescent Supply Current

CCA

CCQ

I

All V Pins

CC

a. V

(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V

range

CMR

and the input swing lies within the V (DC) specification.

PP

b. The MPC9600 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated trans-

mission line to a termination voltage of V . Alternatively, the device drives up to two 50 Ω series terminated transmission lines per output.

TT

Table 5: AC CHARACTERISTICS (V_CC= 3.3 V 5% or V_CC= 2.5 V 5%, T_A= –40° to +85°C)^a

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

f

ref

Input Frequency

B8 feedback (FSEL_FB=0)

B12 feedback (FSEL_FB=1)

25

16.67

50

33

MHz

PLL locked

Static test mode (VCCA = GND)

0

500

400

MHz

VCCA = GND

f

VCO Frequency

200

VCO

Maximum Output Frequency

MAX

B2 outputs (FSELx=0)

B4 outputs (FSELx=1)

100

50

200

100

MHz

PLL locked

f

Reference Input Duty Cycle

Peak-to-peak Input Voltage

Common Mode Range

25

75

%

refDC

V

PCLK, PCLK

500

1000

mV

LVPECL

PP

V

b

CMR

PCLK, PCLK (VCC = 3.3 V 5%)

PCLK, PCLK (VCC = 2.5 V 5%)

1.2

V

CC

V

CC

-0.8

-0.6

V

LVPECL

t , t

CCLK Input Rise/Fall Time

Propagation Delay (static phase offset)

1.0

ns

see Figure 12

r

f

t

∅

(

)

CCLK to FB_IN

PECL_CLK to FB_IN

–60

+30

+40

+130

+140

+230

ps

PLL locked

t

Output-to-output Skew

sk(o)

all outputs, single frequency

all outputs, multiple frequency

70

150

ps

Measured at

coincident

rising edge

within QAx output bank

within QBx outputs

within QCx outputs

30

40

30

75

125

75

ps

DC

t , t

Output Duty Cycle

Output Rise/Fall Time

Output Disable Time

Output Enable Time

45

50

55

1.0

10

%

ns

0.1

see Figure 12

r

f

t

PLZ, HZ

PZL, ZH

BW

PLL Closed Loop Bandwidth

B8 feedback (FSEL_FB=0)

B12 feedback (FSEL_FB=1)

–3 dB point of

PLL transfer

characteristic

1.0 – 10

0.6 – 4.0

MHz

178

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

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Freescale Semiconductor, Inc.

MPC9600

Table 5: AC CHARACTERISTICS (V_CC= 3.3 V 5% or V_CC= 2.5 V 5%, T_A= –40° to +85°C)^a

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

c

t

Cycle-to-cycle Jitter

See application

section for

other

JIT(CC)

All outputs in B2 configuration

All outputs in B4 configuration

40

130

180

ps

configurations

c

t

Period Jitter

See application

section for

other

JIT(PER)

All outputs in B2 configuration

All outputs in B4 configuration

25

20

70

100

ps

configurations

2

d

t

I/O Phase Jitter (1 s)

V

CC

V

CC

= 3.3V

= 2.5V

17

ps

RMS value at

∅

JIT(

)

c

15

f =400MHz

VCO

Maximum PLL Lock Time

5.0

ms

LOCK

a. AC characteristics are applicable over the entire ambient temperature and supply voltage range and are production tested. AC characteris-

tics apply for parallel output termination of 50 Ω to V

.

TT

b. V

(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V

range

CMR

and the input swing lies within the V (AC) specification. Violation of V

or V impacts static phase offset t

∅

PP (

PP

CMR

).

c. Cycle–to–cycle and period jitter depends on output divider configuration.

d. See applications section for max I/O phase jitter versus frequency.

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

179

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MPC9600

APPLICATIONS INFORMATION

Programming the MPC9600

tions, the table describes the outputs using the input clock fre-

quency CLK as a reference.

The MPC9600 clock driver outputs can be configured into

several divider modes. Additionally the external feedback of

the device allows for flexibility in establishing various input to

output frequency relationships. The selectable feedback divid-

er of the three output groups allows the user to configure the

device for 1:2, 1:3, 1:4 and 1:6 input:output frequency ratios.

The use of even dividers ensure that the output duty cycle is

The feedback divider division settings establish the output

relationship, in addition, it must be ensured that the VCO will

be stable given the frequency of the outputs desired. The feed-

back frequency should be used to situate the VCO into a fre-

quency range in which the PLL will be stable. The design of the

PLL supports output frequencies from 50 MHz to 200 MHz

while the VCO frequency range is specified from 200 MHz to

2

always 50%. Table 6 illustrates the various output configura- 400 MHz and should not be exceeded for stable operation.

Table 6: Output Frequency Relationship^afor QFB connected to FB_IN

Input

Frequency

Range CLK

[MHz]

Configuration Inputs

Output Frequency Ratio and Range

FSEL_FB

FSELA

FSELB

FSELC

Ratio, QAx [MHz]

Ratio, QBx [MHz]

Ratio, QCx [MHz]

4SCLK (100–200)

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

4SCLK (100–200)

4SCLK (100–200) 2SCLK (50.0–100)

4SCLK (100–200) 2SCLK (50.0–100) 4SCLK (100–200)

4SCLK (100–200) 2SCLK (50.0–100) 2SCLK (50.0–100)

25.0–50.0

2SCLK (50.0–100)

4SCLK (100–200)

2SCLK (50.0–100) 4SCLK (100–200) 2SCLK (50.0–100)

2SCLK (50.0–100) 2SCLK (50.0–100) 4SCLK (100–200)

2SCLK (50.0–100) 2SCLK (50.0–100) 2SCLK (50.0–100)

6SCLK (100–200)

6SCLK (100–200) 3SCLK (50.0–100)

6SCLK (100–200) 3SCLK (50.0–100) 6SCLK (100–200)

6SCLK (100–200) 3SCLK (50.0–100) 3SCLK (50.0–100)

16.67–33.33

3SCLK (50.0–100) 6SCLK (100–200)

6SCLK (100–200)

3SCLK (50.0–100) 6SCLK (100–200) 3SCLK (50.0–100)

3SCLK (50.0–100) 3SCLK (50.0–100) 6SCLK (100–200)

3SCLK (50.0–100) 3SCLK (50.0–100) 3SCLK (50.0–100)

a. Output frequency relationship with respect to input reference frequency CLK. The VCO frequency range is always 200–400.

Typical and Maximum Period Jitter Specification

QA0 to QA6

QB0 to QB6

QC0 to QC6

Device Configuration

Typ

Max

Typ

Max

Typ

Max

a

All output banks in B2 or B4 divider configuration

B2 (FSELA=0 and FESLB=0 and FSELC=0)

B4 (FSELA=1 and FESLB=1 and FSELC=1)

25

20

50

70

50

70

100

25

20

50

70

b

Mixed B2/B4 divider configurations

for output banks in B2 divider configurations

for output banks in B4 divider configurations

80

25

130

70

100

60

150

100

80

25

130

70

a. In this configuration, all MPC9600 outputs generate the same clock frequency. See Figure 1 for an example configuration.

b. Multiple frequency generation. Jitter data are specified for each output divider sepeerately. See Figure 2 for an example.

Typical and Maximum Cycle–to–cycle Jitter Specification

QA0 to QA6

QB0 to QB6

QC0 to QC6

Device Configuration

Typ

Max

Typ

Max

Typ

Max

a

All output banks in B2 or B4 divider configuration

B2 (FSELA=0 and FESLB=0 and FSELC=0)

B4 (FSELA=1 and FESLB=1 and FSELC=1)

40

90

110

80

120

130

180

40

90

110

b

Mixed B2/B4 divider configurations

for output banks in B2 divider configurations

for output banks in B4 divider configurations

150

30

250

110

200

120

280

180

150

30

250

110

a. In this configuration, all MPC9600 outputs generate the same clock frequency.

b. Multiple frequency generation. Jitter data are specified for each output divider sepeerately.

180

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

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MPC9600

Figure 3. Configuration for 125 MHz clocks

Figure 4. Configuration for 133.3/66.67 MHz clocks

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ꢥ ꢦꢝ ꢥ ꢧ ꢚ ꢚꢨ ꢚ ꢚ ꢤꢩ ꢪ

ꢁ ꢁꢂꢃ

ꢑ ꢈꢒ ꢓꢔ

ꢑ ꢉꢒ ꢓꢔ

ꢑ ꢁꢒ ꢓꢔ

ꢜꢛꢘ ꢤꢩ ꢪ

ꢁꢁꢂ ꢃ

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ꢑ ꢉ ꢒꢓ ꢔ

ꢑ ꢁꢒ ꢓꢔ

ꢜ ꢚ ꢚ ꢨꢚ ꢤꢩ ꢪ

ꢔ ꢔ ꢨꢔ ꢡ ꢤꢩ ꢪ

ꢡ

ꢆꢉ ꢊꢌ ꢍ

ꢆꢉ ꢊ ꢌꢍ

ꢆꢇ ꢅꢂ ꢊꢆꢉ

ꢆꢇ ꢅ ꢂꢊ ꢆꢉ

ꢜ

ꢒ

ꢡ

ꢒ

ꢆꢇ ꢅꢂ ꢈ

ꢆꢇ ꢅꢂ ꢉ

ꢆꢇ ꢅꢂ ꢁ

ꢒ

ꢜ

ꢆꢇ ꢅ ꢂꢈ

ꢆꢇ ꢅ ꢂꢉ

ꢆꢇ ꢅ ꢂꢁ

ꢑ ꢆꢉ

ꢑ

ꢆ

ꢉ

2

ꢤ ꢀꢁ ꢣꢔ ꢒꢒ

ꢛꢒ ꢨꢢ ꢚꢚ ꢤ ꢩꢪ ꢫꢆ ꢝꢝꢞ ꢟꢕꢠ ꢗꢬ

ꢤ

ꢀ

ꢁ

ꢣ

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ꢒ

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ꢨ

ꢚ

ꢤ

ꢩ

ꢪ

ꢫ

ꢆ

ꢝ

ꢞ

ꢟ

ꢕ

ꢠ

ꢗ

ꢬ

Frequency range

Input

Min

Max

Frequency range

Input

Min

Max

16.67 MHz

100 MHz

33.33 MHz

200 MHz

25 MHz

100 MHz

50 MHz

200 MHz

QA outputs

QB outputs

QC outputs

QA outputs

QB outputs

QC outputs

ꢋ

ꢧ

ꢣ

ꢓ

ꢜ

ꢒ

Ω

ꢥ

ꢭ

ꢦ

ꢎ

ꢧ

ꢛ

ꢨ

ꢘ

ꢎ

ꢭ

ꢦ

ꢎ

ꢧ

ꢚ

ꢨ

ꢚ

ꢎ

Power Supply Filtering

ꢆ

ꢁ

The MPC9600 is a mixed analog/digital product. Its analog

circuitry is naturally susceptible to random noise, especially if

this noise is seen on the power supply pins. Random noise on

the V_CCA(PLL) power supply impacts the device characteris-

tics, for instance I/O jitter. The MPC9600 provides separate

power supplies for the output buffers (V_CC) and the phase-

locked loop (V_CCA) of the device.The purpose of this design

technique is to isolate the high switching noise digital outputs

from the relatively sensitive internal analog phase-locked loop.

In a digital system environment where it is more difficult to

minimize noise on the power supplies a second level of isola-

tion may be required. The simple but effective form of isolation

is a power supply filter on the V_CCApin for the MPC9600. Fig-

ure 5 illustrates a typical power supply filter scheme. The

MPC9600 frequency and phase stability is most susceptible to

noise with spectral content in the 100kHz to 20MHz range.

Therefore the filter should be designed to target this range.

The key parameter that needs to be met in the final filter design

is the DC voltage drop across the series filter resistor R_F. From

the data sheet the I_CCAcurrent (the current sourced through

the V_CCApin) is typically 3 mA (5 mA maximum), assuming

that a minimum of 2.325 V (V_CC=3.3 V or V_CC=2.5 V) must be

maintained on the V_CCApin. The resistor R_Fshown in Figure 5

“V_CCAPower Supply Filter” must have a resistance of 9-10 W

(V_CC=2.5 V) to meet the voltage drop criteria.

ꢁ

ꢧ

ꢛ

µ

ꢆ

ꢥ

ꢭ

ꢦ

ꢎ

ꢧ

ꢛ

ꢨ

ꢘ

ꢎ

ꢭ

ꢦ

ꢎ

ꢧ

ꢚ

ꢨ

ꢚ

ꢎ

ꢆ

ꢁ

ꢋ

ꢆ

ꢎ

ꢁ

ꢈ

ꢎ

ꢁ

ꢆ

ꢜ

ꢒ

ꢖ

ꢆ

ꢀꢁꢂꢃꢄꢅꢅ

ꢎ

ꢁ

ꢚ

ꢨ

ꢜ

ꢒ

ꢖ

ꢆ

Figure 5. V_CCAPower Supply Filter

As the noise frequency crosses the series resonant point of

an individual capacitor its overall impedance begins to look

inductive and thus increases with increasing frequency. The

parallel capacitor combination shown ensures that a low im-

pedance path to ground exists for frequencies well above the

bandwidth of the PLL. Although the MPC9600 has several de-

The minimum values for R_Fand the filter capacitor C_Fare sign features to minimize the susceptibility to power supply

defined by the required filter characteristics: the RC filter noise (isolated power and grounds and fully differential PLL)

should provide an attenuation greater than 40 dB for noise there still may be applications in which overall performance is

whose spectral content is above 100 kHz. In the example RC being degraded due to system power supply noise. The power

filter shown in Figure 5 “V_CCAPower Supply Filter”, the filter supply filter schemes discussed in this section should be ade-

cut-off frequency is around 3-5 kHz and the noise attenuation quate to eliminate power supply noise related problems in

at 100 kHz is better than 42 dB.

most designs.

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

181

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Freescale Semiconductor, Inc.

MPC9600

Using the MPC9600 in zero–delay applications

Table 8: Confidence Facter CF

Nested clock trees are typical applications for the

MPC9600. For these applications the MPC9600 offers a differ-

ential LVPECL clock input pair as a PLL reference. This allows

for the use of differential LVPECL primary clock distribution

devices such as the Motorola MC100ES6111 or

MC100ES6226, taking advantage of its superior low-skew per-

formance. Clock trees using LVPECL for clock distribution and

the MPC9600 as LVCMOS PLL fanout buffer with zero inser-

tion delay will show significantly lower clock skew than clock

distributions developed from CMOS fanout buffers.

CF

1s

Probability of clock edge within the distribution

0.68268948

0.95449988

0.99730007

0.99993663

0.99999943

0.99999999

2s

3s

4s

5s

6s

2

The feedback trace delay is determined by the board layout

and can be used to fine-tune the effective delay through each

device. In the following example calculation a I/O jitter confi-

dence factor of 99.7% ( 3s) is assumed, resulting in a worst

case timing uncertainty from input to any output of -261 ps to

341 ps relative to CCLK (V_CC=3.3V and f_VCO= 200 MHz):

The external feedback option of the MPC9600 PLL allows

for its use as a zero delay buffer. The PLL aligns the feedback

clock output edge with the clock input reference edge and

virtually eliminates the propagation delay through the device.

The remaining insertion delay (skew error) of the MPC9600

in zero-delay applications is measured between the reference

clock input and any output. This effective delay consists of the

t_SK(PP)

=

[–60ps...140ps] + [–150ps...150ps] +

[(17ps @ –3)...(17ps @ 3)] + t_{PD, LINE(FB)}

static phase offset (SPO or t₍_∅), I/O jitter (t_JIT(_∅, phase or

long-term jitter), feedback path delay and the output-to-output

)

t_SK(PP)

=

[–261ps...341ps] + t_{PD, LINE(FB)}

Above equation uses the maximum I/O jitter number shown

in the AC characteristic table for V_CC=3.3V (17 ps RMS). I/O

jitter is frequency dependant with a maximum at the lowest

VCO frequency (200 MHz for the MPC9600). Applications us-

ing a higher VCO frequency exhibit less I/O jitter than the AC

characteristic limit. The I/O jitter characteristics in Figure 7 can

be used to derive a smaller I/O jitter number at the specific

VCO frequency, resulting in tighter timing limits in zero-delay

skew (t_SK(O)relative to the feedback output.

Calculation of part-to-part skew

The MPC9600 zero delay buffer supports applications

where critical clock signal timing can be maintained across

several devices. If the reference clock inputs (CCLK or PCLK)

of two or more MPC9600 are connected together, the maxi-

mum overall timing uncertainty from the common CCLK input

to any output is:

mode and for part-to-part skew t_SK(PP)

.

t_SK(PP)= t _∅+ t_SK(O)+ t_{PD, LINE(FB)}+ t_JIT(ꢀ CF

∅

)

(

)

This maximum timing uncertainty consist of 4 components:

static phase offset, output skew, feedback board trace delay

and I/O (phase) jitter:

ꢱ

ꢁ

ꢂ

ꢃ

ꢁ

ꢭ

ꢷ

ꢭ

ꢖ

ꢮ

ꢀ

ꢐ

ꢯ

ꢂ

ꢌ

ꢍ

ꢅ

ꢫ

ꢆ

ꢉ

ꢬ

ꢳꢮ

∅

ꢫ

ꢬ

ꢑ

ꢆ

ꢉ

ꢐ ꢝ ꢸ ꢹ ꢠ ꢝ ꢜ

ꢮ

∅

ꢰ ꢌ ꢱ ꢫ

ꢬ

Figure 7. Max. I/O Jitter versus VCO frequency for

V_CC=2.5V and V_CC=3.3V

ꢈ

ꢖ

ꢺ

ꢑ

ꢲ t

ꢇ ꢃ ꢫ ꢄ ꢬ

Driving Transmission Lines

The MPC9600 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user the output drivers

were designed to exhibit the lowest impedance possible. With

an output impedance of less than 20 Ω the drivers can drive

either parallel or series terminated transmission lines. For

more information on transmission lines the reader is referred to

Motorola application note AN1091. In most high performance

clock networks point-to-point distribution of signals is the meth-

od of choice. In a point-to-point scheme either series termi-

nated or parallel terminated transmission lines can be used.

The parallel technique terminates the signal at the end of the

line with a 50Ω resistance to V_CC÷2.

ꢲ

ꢮ

∅

ꢫ

ꢬ

ꢑ

ꢆ

ꢉ

ꢐ

ꢝ

ꢸ

ꢹ

ꢠ

ꢝ

ꢛ

ꢮ

∅

ꢰ ꢌ ꢱ ꢫ

ꢬ

ꢈꢖ ꢺ ꢑ

ꢐ ꢝ ꢸ ꢹ ꢠ ꢝ ꢛ

ꢲ t

ꢇ ꢃ ꢫ ꢄ ꢬ

ꢤ

ꢕ

ꢴ

ꢨ

ꢵ

ꢗ

ꢝ

ꢶ

ꢮ

ꢇ ꢃ ꢫ ꢀ ꢀ ꢬ

Figure 6. MPC9600 max. device-to-device skew

Due to the statistical nature of I/O jitter a RMS value (1 s) is

specified. I/O jitter numbers for other confidence factors (CF)

can be derived from Table 8.

This technique draws a fairly high level of DC current and

thus only a single terminated line can be driven by each output

182

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

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MPC9600

of the MPC9600 clock driver. For the series terminated case

V_L= 3.0 ( 25 ÷ (18+17+25)

= 1.31 V

At the load end the voltage will double due to the near unity

reflection coefficient, to 2.6 V. It will then increment towards the

quiescent 3.0 V in steps separated by one round trip delay (in

this case 4.0 ns).

however there is no DC current draw, thus the outputs can

drive multiple series terminated lines. Figure 8 “Single versus

Dual Transmission Lines” illustrates an output driving a single

series terminated line versus two series terminated lines in

parallel. When taken to its extreme the fanout of the MPC9600

clock driver is effectively doubled due to its capability to drive

multiple lines.

ꢚ ꢨꢒ

ꢄ ꢽ ꢮꢈ

ꢮ ꢧ ꢚ ꢨ ꢢꢣ ꢘꢔ

ꢤꢀꢁ ꢣꢔ ꢒ ꢒ

ꢄ ꢻꢱ ꢀꢻ ꢱ

ꢉꢻ ꢆ ꢆꢅꢋ

ꢄ ꢽ ꢮꢉ

ꢐ

ꢛ ꢨꢘ

ꢛ ꢨꢒ

ꢜ ꢨꢘ

ꢜ ꢨꢒ

ꢒ ꢨꢘ

ꢒ

ꢮ ꢧ ꢚ ꢨ ꢣꢚ ꢢꢔ

ꢐ

2

ꢼ

ꢧ ꢘꢒ Ω

ꢄ

ꢋ ꢧ ꢚꢔ Ω

ꢇ

ꢜ

ꢙΩ

ꢌ ꢖ

ꢌ ꢍ

ꢄ ꢽ ꢮꢈ

ꢤꢀ ꢁꢣ ꢔ ꢒ ꢒ

ꢄꢻ ꢱꢀꢻ ꢱ

ꢉꢻ ꢆꢆ ꢅꢋ

ꢼ

ꢧ ꢘꢒ Ω

ꢄ

ꢋ ꢧ ꢚꢔ Ω

ꢇ

ꢄ ꢽ ꢮꢉ ꢒ

ꢄ ꢽ ꢮꢉ ꢜ

ꢜ

ꢙ

Ω

ꢌ

ꢍ

ꢋ ꢧ ꢚꢔ Ω

ꢇ

ꢛ

ꢙ

ꢔ

ꢢ

ꢜ

ꢒ

ꢜ

ꢛ

ꢜ

ꢙ

ꢱ

ꢌ

ꢤ

ꢅ

ꢫ

ꢖ

ꢇ

ꢬ

Figure 9. Single versus Dual Waveforms

Figure 8. Single versus Dual Transmission Lines

The waveform plots in Figure 9 “Single versus Dual Line

Termination Waveforms” show the simulation results of an out-

put driving a single line versus two lines. In both cases the

drive capability of the MPC9600 output buffer is more than suf-

ficient to drive 50 Ω transmission lines on the incident edge.

Note from the delay measurements in the simulations a delta

of only 43 ps exists between the two differently loaded outputs.

This suggests that the dual line driving need not be used exclu-

sively to maintain the tight output-to-output skew of the

MPC9600. The output waveform in Figure 9 “Single versus

Dual Line Termination Waveforms” shows a step in the wave-

form, this step is caused by the impedance mismatch seen

looking into the driver. The parallel combination of the 36Ω se-

ries resistor plus the output impedance does not match the

parallel combination of the line impedances. The voltage wave

launched down the two lines will equal:

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines the situation

in Figure 10 “Optimized Dual Line Termination” should be

used. In this case the series terminating resistors are reduced

such that when the parallel combination is added to the output

buffer impedance the line impedance is perfectly matched.

ꢤꢀ ꢁꢣ ꢔ ꢒꢒ

ꢄ ꢻꢱꢀ ꢻꢱ

ꢼ

ꢧ ꢘ ꢒ Ω

ꢄ

ꢋ ꢧ ꢛ ꢛ Ω

ꢇ

ꢉ

ꢻ

ꢆ

ꢅ

ꢋ

ꢜ

ꢙ

Ω

ꢋ ꢧ ꢛ ꢛ Ω

ꢇ

V_L= V_S( Z₀÷ (R_S+R₀+Z₀))

Z₀= 50 Ω || 50 Ω

R_S= 36 Ω || 36 Ω

R₀= 14 Ω

14 Ω + 22 Ω ꢁ 22 Ω = 50 Ω ꢁ 50 Ω

25 Ω = 25 Ω

Figure 10. Optimized Dual Line Termination

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

183

For More Information On This Product,

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Freescale Semiconductor, Inc.

MPC9600

The Following Figures Illustrate the Measurement Reference for the MPC9600 Clock Driver Circuit

ꢤꢀ ꢁꢣ ꢔ ꢒꢒ ꢐꢻꢱ

ꢀ ꢽꢿꢵꢝ

ꢏ ꢝꢖꢝ ꢦꢕꢮ ꢭ ꢦ

ꢼ

ꢧ

ꢘ

ꢒ

Ω

ꢼ ꢧ ꢘ ꢒ Ω

ꢄ

ꢼ ꢧ ꢘꢒ W

ꢋ ꢧ ꢘ ꢒ Ω

ꢱ

ꢋ ꢧ ꢘ ꢒ Ω

ꢱ

ꢎ

ꢱ ꢱ

ꢎ

ꢱ ꢱ

2

Figure 11. CCLK MPC9600 AC test reference

ꢤꢀ ꢁꢣ ꢔ ꢒꢒ ꢐꢻ ꢱ

ꢼ

ꢧ

ꢘ

ꢒ

Ω

ꢄ

ꢐꢹ ꢥꢥ ꢝꢦꢝ ꢖꢮ ꢹꢕꢿ

ꢀ ꢽꢿꢵꢝ ꢏ ꢝꢖꢝ ꢦꢕ ꢮꢭꢦ

ꢼ ꢧ ꢘꢒ W

ꢼ

ꢧ ꢘ ꢒ Ω

ꢄ

ꢋ ꢧ ꢘ ꢒ Ω

ꢱ

ꢋ ꢧ ꢘ ꢒ Ω

ꢱ

ꢎ

ꢱ ꢱ

ꢎ

ꢱ ꢱ

Figure 12. PCLK MPC9600 AC test reference

ꢎ

ꢀꢁ ꢂ ꢃ

ꢁ

ꢂ

ꢃ

Bꢛ

ꢁ

ꢎ

ꢁ ꢤ ꢋ

ꢎ

ꢀ ꢀ

ꢏ ꢍꢐ

ꢎ

ꢁ ꢁ

ꢁ

Bꢛ

ꢆꢉ ꢊ ꢌꢍ

ꢁ ꢁ

ꢆ ꢉꢊꢌ ꢍ

ꢏ ꢍꢐ

ꢏ

ꢍ

ꢐ

ꢮ

∅

ꢫ

ꢬ

ꢮ

∅

ꢫ

ꢬ

Figure 13. Propagation delay t₍_∅, static phase

)

Figure 14. Propagation delay t₍_∅₎test reference

offset) test reference

ꢎ

ꢁ ꢁ

ꢎ

ꢁ ꢁ

Bꢛ

ꢁ ꢁ

Bꢛ

ꢁ

ꢏ

ꢍ

ꢐ

ꢏ

ꢍ

ꢐ

ꢮ

ꢀ

ꢎ

ꢁ

Bꢛ

ꢁ

ꢱ

ꢒ

ꢏ

ꢍ

ꢐ

ꢀ

ꢁ

ꢂ

ꢃ

ꢅ

ꢆ

ꢴ

ꢈ

ꢇ

ꢉ

ꢄ

ꢇ

ꢮ

ꢇ

ꢃ

ꢫ

ꢄ

ꢬ

ꢱ ꣀꢝ ꢮꢹ ꢷꢝ ꢥꢦ ꢭ ꢷ ꢮꣀ ꢝ ꢀꢂ ꢂ ꢠꢭꢖ ꢮꢦ ꢭꢿꢿꢝ ꢞ ꢝꢞ ꣂꢝ ꢮ ꢭ ꢮ ꣀꢝ ꢖꢭ ꢖ ꢠꢭꢖ ꢮꢦ ꢭꢿꢿꢝ ꢞ

ꢝ ꢞꣂ ꢝ ꢯ ꢞ ꢹꢸꢹꢞ ꢝꢞ ꢟ ꢺ ꢮꣀ ꢝ ꢮꢹ ꢷꢝ ꢟꢝ ꢮꢶ ꢝꢝꢖ ꢀ ꢂꢂ ꢠꢭꢖ ꢮꢦ ꢭꢿꢿꢝ ꢞ ꢝꢞ ꣂꢝꢵꢯ

ꢝ ꢴꣁ ꢦꢝ ꢵꢵ ꢝꢞ ꢕ ꢵ ꢕ ꣁ ꢝꢦ ꢠꢝꢖ ꢮꢕ ꣂꢝ

ꢱꣀ ꢝ ꣁ ꢹꢖꢓ ꢮ ꢭ ꢓꣁ ꢹꢖ ꢵꢗꢝ ꢶ ꢹꢵ ꢞ ꢝꢥ ꢹꢖ ꢝ ꢞ ꢕ ꢵ ꢮ ꣀꢝ ꢶꢭ ꢦꢵꢮ ꢠꢕ ꢵꢝ ꢞ ꢹꢥꢥ ꢝ ꢦꢝꢖ ꢠ ꢝ ꢹꢖ

ꣁ ꢦꢭ ꣁꢕ ꣂꢕ ꢮ ꢹꢭ ꢖ ꢞ ꢝꢿꢕ ꢺ ꢟ ꢝꢮ ꢶꢝ ꢝ ꢖ ꢕ ꢖꢺ ꢵꢹꢷꢹꢿ ꢕꢦ ꢞ ꢝꢿꢕ ꢺ ꣁ ꢕꢮ ꣀ ꢶꢹꢮ ꣀ ꢹꢖ ꢕ

ꢵꢹꢖ ꣂꢿꢝ ꢞ ꢝꢸꢹꢠꢝ

Figure 15. Output Duty Cycle (DC)

Figure 16. Output–to–output Skew t_SK(O)

184

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

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Freescale Semiconductor, Inc.

MPC9600

ꢆ

ꢂ ꣄ꢆ ꢏ ꢆ

꣄

ꢆ ꢂ ꣄ꢆ ꢏ ꢈ ꣅꢑ ꣄

ꢊ ꢋ ꢆ ꢌ ꢄ ꢍ ꢎ ꢇ

ꢊ ꢋ ꢆ ꢌ ꢁ ꢁ ꢍ

ꢎ

ꢎ ꢐ ꢈ

ꢱ

ꢍ ꢲ ꢜ

ꢱ

ꢍ

ꢒ

ꢱ ꣀꢝ ꢸꢕ ꢦ ꢹꢕꢮ ꢹꢭ ꢖ ꢹꢖ ꢠꢺꢠ ꢿꢝ ꢮ ꢹꢷ ꢝ ꢭꢥ ꢕ ꢵꢹꣂꢖ ꢕꢿ ꢟꢝ ꢮꢶ ꢝꢝ ꢖ ꢕꢞ ꣃꢕꢠꢝ ꢖꢮ ꢠꢺꢠꢿꢝ ꢵꢯ ꢭ ꢸꢝꢦ ꢕ

ꢦ ꢕꢖ ꢞ ꢭꢷ ꢵꢕ ꢷꣁ ꢿꢝ ꢭ ꢥ ꢕ ꢞꣃꢕ ꢠꢝꢖꢮ ꢠꢺꢠꢿꢝ ꣁꢕ ꢹꢦꢵ

ꢱꣀ ꢝ ꢞ ꢝꢸꢹꢕ ꢮ ꢹꢭ ꢖ ꢹꢖ ꢠꢺꢠꢿꢝ ꢮ ꢹꢷꢝ ꢭ ꢥ ꢕ ꢵꢹꣂ ꢖꢕ ꢿ ꢶꢹꢮ ꣀ ꢦꢝ ꢵꣁ ꢝꢠꢮ ꢮ ꢭ ꢮ ꣀ ꢝ ꢹꢞ ꢝꢕ ꢿ ꣁ ꢝꢦ ꢹꢭ ꢞ ꢭ ꢸꢝ ꢦ

ꢕ ꢦꢕ ꢖꢞ ꢭ ꢷ ꢵꢕ ꢷꣁ ꢿꢝ ꢭ ꢥ ꢠꢺꢠꢿꢝ ꢵ

Figure 17. Cycle–to–cycle Jitter

Figure 18. Period Jitter

2

ꢁ ꢁ ꢂ ꢃ

ꢫ ꢀꢁ ꢂꢃꢬ

ꢎ

ꢁ ꢁ

ꢧ ꢚ ꢨꢚ ꢎ

ꢎ

ꢁ ꢁ

ꢧꢛ ꢨ ꢘ ꢎ

ꢜ ꢨꢢ ꢎ

ꢛ

ꢨ

ꢙ

ꢆ

ꢉ

ꢊ

ꢌ

ꢍ

ꢒ

ꢨ

ꢘ

ꢒ

ꢨ

ꢔ

ꢎ

ꢆ

ꢊ ꢋ ꢆ ꢌ

ꢂ ꣄ꢆ ꢏ ꢆ ꢒ ꢓꢔꢕ꣄

ꢇ ꢈ

∅

ꢍ

ꢮ

ꢆ

ꢮ

ꢋ

ꢱ ꣀꢝ ꢞ ꢝꢸ ꢹꢕꢮ ꢹꢭ ꢖ ꢹꢖ ꢮ ꢥꢭ ꢦ ꢕ ꢠꢭꢖ ꢮꢦ ꢭꢿꢿꢝ ꢞ ꢝꢞ ꣂꢝ ꢶ ꢹꢮꣀ ꢦꢝ ꢵꣁꢝꢠꢮ ꢮ ꢭ ꢕ ꢮ ꢷ ꢝꢕꢖ ꢹꢖ ꢕ

ꢒ

ꢦ

ꢕ

ꢖ

ꢞ

ꢭ

ꢷ

ꢵ

ꢕ

ꢷ

ꣁ

ꢿ

ꢝ

ꢭ

ꢥ

ꢠ

ꢺ

ꢠ

ꢿ

ꢝ

ꢵ

Figure 19. I/O Jitter

Figure 20. Output Transition Time Test Reference

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

185

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型号：	MPC9600FAR2
厂家：	NXP
描述：	9600 SERIES, PLL BASED CLOCK DRIVER, 21 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP48, PLASTIC, LQFP-48 驱动输出元件
文件：	总12页 (文件大小：368K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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