MPC9608FA [NXP]
IC,1:10 OUTPUT,LV-CMOS,QFP,32PIN,PLASTIC;
| 型号： | MPC9608FA |
| 厂家： | 
NXP |
| 描述： | IC,1:10 OUTPUT,LV-CMOS,QFP,32PIN,PLASTIC 驱动 输出元件 逻辑集成电路 |
| 文件： | 总12页 (文件大小：421K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor, Inc.
MOTOROLA
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by MPC9608
SEMICONDUCTOR TECHNICAL DATA
MPC9608
1:10 LVCMOS Zero Delay
Clock Buffer
The MPC9608 is a 3.3 V compatible, 1:10 PLL based zero-delay buffer. With a
very wide frequency range and low output skews the MPC9608 is targeted for
high performance and mid-range clock tree designs.
LOW VOLTAGE 3.3 V
LVCMOS 1:10 ZERO-DELAY
CLOCK BUFFER
Features
• 1:10 outputs LVCMOS zero-delay buffer
• Single 3.3 V supply
• Supports a clock I/O frequency range of 12.5 to 200 MHz
• Selectable divide-by-two for one output bank
• Synchronous output enable control (CLK_STOP)
• Output tristate control (output high impedance)
• PLL bypass mode for low frequency system test purpose
• Supports networking, telecommunications and computer applications
• Supports a variety of microprocessors and controllers
• Compatible to PowerQuicc I and II
FA SUFFIX
32-LEAD LQFP PACKAGE
CASE 873A
• Ambient Temperature Range -40°C to +85°C
• 32-lead Pb-free package available
AC SUFFIX
32 LEAD LQFP PACKAGE-Pb-free
CASE 873A
Functional Description
The MPC9608 uses an internal PLL and an external feedback path to lock its
low-skew clock output phase to the reference clock phase, providing virtually zero
propagation delay. This enables nested clock designs with near-zero insertion
delay. Designs using the MPC9608 as PLL fanout buffer will show significantly lower clock skew than clock distributions developed
from traditional fanout buffers. The device offers one reference clock input and two banks of 5 outputs for clock fanout. The input
frequency and phase is reproduced by the PLL and provided at the outputs. A selectable frequency divider sets the bank B outputs
to generate either an identical copy of the bank A clocks or one half of the bank A clock frequency. Both output banks remain syn-
chronized to the input reference for both bank B configurations.
Outputs are only disabled or enabled when the outputs are already in logic low state (CLK_STOP). For system test and diagnosis,
the MPC9608 outputs can also be set to high-impedance state by connecting OE to logic high level. Additionally, the device provides
a PLL bypass mode for low frequency test purpose. In PLL bypass mode, the minimum frequency and static phase offset specification
do not apply.
CLK_STOP and OE do not affect the PLL feedback output (QFB) and down stream clocks can be disabled without the internal PLL
losing lock.
The MPC9608 is fully 3.3 V compatible and requires no external components for the internal PLL. All inputs accept LVCMOS sig-
nals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission lines on the inci-
dent edge. For series terminated transmission lines, each of the MPC9608 outputs can drive one or two traces giving the devices an
effective fanout of 1:20. The device is packaged in a 7x7 mm2 32-lead LQFP package.
REV 2
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MPC9608
Bank A
CCLK
VCO
QA0
Ref
FB
2
CCLK
FB_IN
PLL
QA1
QA2
QA3
QA4
00: 100-200 MHz
01: 50-100 MHz
10: 25- 50 MHz
11:12.5- 25 MHz
STOP
25k
25k
Bank B
F_RANGE[0:1]
PLL_EN
QB0
25k
25k
QB1
QB2
QB3
QB4
÷2
CLK_STOP
25k
25k
25k
BSEL
OE
PLL feedback
QFB
Figure 1. MPC9608 Logic Diagram
24 23 22 21 20 19 18 17
16
25
26
27
28
29
30
31
32
VCC
QB4
QB3
QB2
GND
QB1
VCC
QA4
QA3
QA2
GND
QA1
QA0
VCC
15
14
13
MPC9608
12
11
10
9
QB0
VCC
1
2
3
4
5
6
7
8
Figure 2. MPC9608 32-Lead Package Pinout (Top View)
2
TIMING SOLUTIONS
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MPC9608
TABLE 1. PIN CONFIGURATION
Pin
I/O
Input
Type
Function
CCLK
FB_IN
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
PLL reference clock signal
Input
PLL feedback signal input, connect to a QFB output
PLL frequency range select
F_RANGE[0:1]
BSEL
Input
Input
Frequency divider select for bank B outputs
PLL enable/disable
PLL_EN
OE
Input
Input
Output enable/disable (high-impedance tristate)
Synchronous clock enable/stop
Clock outputs
CLK_STOP
QA0-4, QB0-4
QFB
Input
Output
Output
Supply
Supply
PLL feedback signal output. Connect to FB_IN
Negative power supply
GND
VCCA
VCC
PLL positive power supply (analog power supply). The MPC9608 requires an external RC filter for
the analog power supply pin VCCA. Refer to the Applications Information section for details.
VCC
Supply
VCC
Positive power supply for I/O and core
TABLE 2. FUNCTION TABLE
Control
F_RANGE[0:1]
BSEL
Default
0
1
00
0
PLL frequency range. Refer to Table 3 “Clock frequency configuration for QFB connected to FB_IN”
fQB0-4 = fQA0-4
fQB0-4 = fQA0-4 ÷ 2
CLK_STOP
OE
0
0
Outputs enabled
Outputs synchronously stopped in logic low state
Outputs enabled (active)
Outputs disabled (high-impedance state), independent on
CLK_STOP. Applying OE = 1 and PLL_EN = 1 resets the device. The
PLL feedback output QFB is not affected by OE.
PLL_EN
0
Normal operation mode with PLL enabled.
Test mode with PLL disabled. CCLK is substituted for the internal
VCO output. MPC9608 is fully static and no minimum frequency limit
applies. All PLL related AC characteristics are not applicable.
Applying OE = 1 and PLL_EN = 1 resets the device.
TABLE 3. Clock Frequency Configuration for QFB connected to FB_IN
F_RANGE[0]
F_RANGE[1]
BSEL
fREF (CCLK)
range [MHz]
QA0-QA4
QB0-B4
fQB0-4 [MHz]
QFB
Ratio
f
QA0-4 [MHz]
Ratio
fREF
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100.0 – 200.0
50.0 – 100.0
25.0 – 50.0
12.5 – 25.0
fREF
100.0 – 200.0
100.0 – 200.0
50.0 – 25.0
50.0 – 100.0
25.0 – 50.0
25.0 – 50.0
12.5 – 25.0
12.5 – 25.0
6.25 – 12.5
fREF
fREF
fREF
fREF
fREF
fREF
fREF
fREF
f
f
f
f
REF ÷ 2
fREF
REF ÷ 2
fREF
REF ÷ 2
fREF
fREF
fREF
fREF
50.0 – 100.0
25.0 – 50.0
12.5 – 25
REF ÷ 2
TIMING SOLUTIONS
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MPC9608
TABLE 4. GENERAL SPECIFICATIONS
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
VTT
Output termination voltage
V
CC ÷ 2
V
MM
HBM
LU
ESD protection (Machine model)
ESD protection (Human body model)
Latch-up immunity
200
2000
200
V
V
mA
pF
CPD
Power dissipation capacitance
10
Per output
Inputs
CIN
Input capacitance
4.0
pF
TABLE 5. ABSOLUTE MAXIMUM RATINGSa
Symbol
Characteristics
Min
Max
Unit
Condition
VCC
Supply Voltage
-0.3
3.6
VCC + 0.3
VCC + 0.3
±20
V
VIN
VOUT
IIN
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
Storage temperature
-0.3
-0.3
V
V
mA
mA
°C
IOUT
TS
±50
-65
125
a. Absolute maximum continuos ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
TABLE 6. DC CHARACTERISTICS (VCC = 3.3 V ± 5%, TA = -40° to 85°C)
Symbol
VIH
Characteristics
Input High Voltage
Min
2.0
Typ
Max
VCC + 0.3
Unit
V
Condition
LVCMOS
VIL
Input Low Voltage
0.8
V
V
LVCMOS
IOH = -24 mAa
VOH
Output High Voltage
2.4
VOL
Output Low Voltage
0.55
0.30
V
V
IOL = 24 mA
IOL = 12 mA
ZOUT
IIN
ICCA
ICCQ
Output Impedance
14 – 17
Ω
Input Currentb
±200
8.0
µA
VIN = VCC or GND
Maximum PLL Supply Current
4.0
1.0
mA VCCA Pin
Maximum Quiescent Supply Current
4.0
mA All VCC Pins
a. The MPC9608 is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission
line to a termination voltage of VTT. Alternatively, the device drives up to two 50 Ω series terminated transmission lines.
b. Inputs have pull-down resistors affecting the input current.
4
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TABLE 7. AC CHARACTERISTICS (VCC = 3.3 V ± 5%, TA = -40° to 85°C)a
Symbol
fref
Characteristics
Min
Typ
Max
Unit
Condition
Input reference frequency in PLL modeb
F_RANGE = 00
F_RANGE = 01
F_RANGE = 10
F_RANGE = 11
100
50
200
100
50
MHz
MHz
MHz
MHz
MHz
25
12.5
0
25
Input reference frequency in PLL bypass modec
200
fmax
Output Frequencyd
F_RANGE = 00
100
50
200
100
50
MHz BSEL = 0
MHz BSEL = 0
MHz BSEL = 0
MHz BSEL = 0
F_RANGE = 01
F_RANGE = 10
F_RANGE = 11
25
12.5
25
tPW, MIN
tr, tf
t(
Reference Input Pulse Widthe
CCLK Input Rise/Fall Time
2.0
ns
1.0
ns
0.8 V to 2.0 V
Propagation Delay (SPO) CCLK to FB_IN
)
f
ref = 100 MHz and above
-175
+175
+1.75% of tPER
ps
ps
PLL Locked
f
ref = 12.5 MHz to 100 MHz -1.75% of tPER
tSK(o)
Output-to-Output Skew
ps
Within a bank
Bank-to-bank
All outputs, inluding QFB
80
100
150
DC
Output Duty Cycle
Output Rise/Fall Time
Output Disable Time
Output Enable Time
Cycle-to-cycle jitter
Period Jitter
45
50
55
1.0
10
%
ns
ns
ns
ps
ps
ps
tr, tf
0.1
0.55 V to 2.4 V
tPLZ, HZ
tPZL, LZ
tJIT(CC)
tJIT(PER)
10
150
150
125
BSEL = 0
BSEL = 0
BSEL = 0
tJIT(
I/O Phase Jitter
PLL closed loop bandwidthf
RMS (1 σ)
)
BW
F_RANGE = 00
F_RANGE = 01
F_RANGE = 10
F_RANGE = 11
7 – 15
2 – 7
MHz
MHz
MHz
MHz
1 – 3
0.5 – 1.3
tLOCK
Maximum PLL Lock Time
10
ms
a. AC characteristics apply for parallel output termination of 50 Ω to VTT
.
b. PLL mode requires PLL_EN = 0 to enable the PLL and zero-delay operation.
c. In bypass mode, the MPC9608 divides the input reference clock.
d. Applies for bank A and for bank B if BSEL = 0. If BSEL = 1, the minimum and maximum output frequency of bank B is divided by two.
e. Calculation of reference duty cycle limits: DCREF, MIN = tPW, MIN * fREF *100% and DCREF, MAX = 100% – DCREF, MIN. For example, at
fREF = 100 MHz the input duty cycle range is 20% < DC < 80%.
f.
-3 dB point of PLL transfer characteristics.
TIMING SOLUTIONS
5
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MPC9608
APPLICATIONS INFORMATION
Power Supply Filtering
(isolated power and grounds and fully differential PLL), there
still may be applications in which overall performance is being
degraded due to system power supply noise. The power supply
filter schemes discussed in this section should be adequate to
eliminate power supply noise related problems in most designs.
The MPC9608 is a mixed analog/digital product. Its analog
circuitry is naturally susceptible to random noise, especially if
this noise is seen on the power supply pins. Random noise on
the VCCA (PLL) power supply impacts the device characteris-
tics, for instance I/O jitter. The MPC9608 provides separate
Using the MPC9608 in Zero-delay Applications
power supplies for the output buffers (VCC
) and the
Nested clock trees are typical applications for the
MPC9608. Designs using the MPC9608, as LVCMOS PLL
fanout buffer with zero insertion delay, will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC9608 clock driver allows for its use as a zero delay buffer.
By using the QFB output as a feedback to the PLL the
propagation delay through the device is virtually eliminated.
The PLL aligns the feedback clock output edge with the clock
input reference edge resulting in a near zero delay through the
device. The maximum insertion delay of the device in
zero-delay applications is measured between the reference
clock input and any output. This effective delay consists of the
static phase offset, I/O jitter (phase or long-term jitter), feedback
path delay and the output-to-output skew error relative to the
feedback output.
phase-locked loop (VCCA) of the device. The purpose of this de-
sign technique is to isolate the high switching noise digital out-
puts from the relatively sensitive internal analog phase-locked
loop. In a digital system environment where it is more difficult to
minimize noise on the power supplies a second level of isolation
may be required. The simple but effective form of isolation is a
power supply filter on the VCCA pin for the MPC9608. Figure 3
illustrates a typical power supply filter scheme. The MPC9608
frequency and phase stability is most susceptible to noise with
spectral content in the 100 kHz to 20 MHz range. Therefore the
filter should be designed to target this range. The key parame-
ter that needs to be met in the final filter design is the DC volt-
age drop across the series filter resistor RF. From the data
sheet the ICCA current (the current sourced through the VCCA
pin) is typically 4 mA (8 mA maximum), assuming that a mini-
mum of 3.125 V must be maintained on the VCCA pin. The re-
sistor RF shown in Figure 3 “VCCA Power Supply Filter” must
have a resistance of 9 – 10 Ω (VCC = 3.3 V) to meet the voltage
drop criteria.
Calculation of Part-to-Part Skew
The MPC9608 zero delay buffer supports applications
where critical clock signal timing can be maintained across sev-
eral devices. If the reference clock inputs of two or more
MPC9608 are connected together, the maximum overall timing
uncertainty from the common CCLK input to any output is:
RF = 9-10 Ω for VCC = 3.3 V
CF = 1 µF for VCC = 3.3 V
t
SK(PP) = t( ) + tSK(O) + tPD, LINE(FB) + tJIT( . CF
)
RF
This maximum timing uncertainty consists of 4 compo-
nents: static phase offset, output skew, feedback board trace
delay, and I/O (phase) jitter:
VCCA
VCC
10 nF
CF
MPC9608
VCC
CCLKCommon
tPD,LINE(FB)
-t(
)
33...100 nF
QFBDevice 1
tJIT(
Figure 3. VCCA Power Supply Filter
)
Any QDevice 1
The minimum values for RF and the filter capacitor CF are
+tSK(O)
defined by the required filter characteristics: the RC filter should
provide an attenuation greater than 40 dB for noise whose
spectral content is above 100 kHz. In the example RC filter
shown in Figure 3 “VCCA Power Supply Filter”, the filter cut-off
frequency is around 3-5 kHz and the noise attenuation at
100 kHz is better than 42 dB.
+t(
)
QFBDevice2
tJIT(
)
As the noise frequency crosses the series resonant point
of an individual capacitor, its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low imped-
ance path to ground exists for frequencies well above the band-
width of the PLL. Although the MPC9608 has several design
features to minimize the susceptibility to power supply noise
Any QDevice 2
Max. skew
+tSK(O)
tSK(PP)
Figure 4. MPC9608 maximum device-to-device skew
6
TIMING SOLUTIONS
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Due to the statistical nature of I/O jitter, an RMS value (1 σ)
is specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 8.
MPC9608
OUTPUT
BUFFER
RS = 36 Ω
ZO = 50 Ω
14 Ω
TABLE 8. Confidence Facter CF
IN
IN
OutA
CF
Probability of clock edge within the distribution
± 1σ
± 2σ
± 3σ
± 4σ
± 5σ
± 6σ
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
MPC9608
OUTPUT
BUFFER
ZO = 50 Ω
ZO = 50 Ω
RS = 36 Ω
RS = 36 Ω
OutB0
OutB1
14 Ω
The feedback trace delay is determined by the board layout
and can be used to fine-tune the effective delay through each
device. In the following example calculation a I/O jitter confi-
dence factor of 99.7% (± 3σ) is assumed, resulting in a worst
case timing uncertainty from input to any output of -295 ps to
Figure 5. Single versus Dual Transmission Lines
295 ps1 relative to CCLK:
The waveform plots in Figure 6 “Single versus Dual Line
Termination Waveforms” show the simulation results of an out-
put driving a single line versus two lines. In both cases the drive
capability of the MPC9608 output buffer is more than sufficient
to drive 50 Ω transmission lines on the incident edge. From the
delay measurements in the simulations a delta of only 43 ps ex-
ists between the two differently loaded outputs. This suggests
that the dual line driving need not be used exclusively to main-
tain the tight output-to-output skew of the MPC9608. The output
waveform in Figure 6 “Single versus Dual Line Termination
Waveforms” shows a step in the waveform. This step is caused
by the impedance mismatch seen looking into the driver. The
parallel combination of the 36 Ω series resistor plus the output
impedance does not match the parallel combination of the line
impedances. The voltage wave launched down the two lines will
equal:
tSK(PP)
=
[-100 ps...100 ps] + [-150 ps...150 ps] +
[(15 ps . -3)...(15 ps . 3)] + tPD, LINE(FB)
[-295 ps...295 ps] + tPD, LINE(FB)
tSK(PP)
=
Driving Transmission Lines
The MPC9608 clock driver was designed to drive high
speed signals in a terminated transmission line environment. To
provide the optimum flexibility to the user the output drivers
were designed to exhibit the lowest impedance possible. With
an output impedance of less than 20 Ω the drivers can drive ei-
ther parallel or series terminated transmission lines. For more
information on transmission lines the reader is referred to Mo-
torola application note AN1091. In most high performance clock
networks point-to-point distribution of signals is the method of
choice. In a point-to-point scheme either series terminated or
parallel terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a 50 Ω
resistance to VCC ÷ 2.
VL = VS ( Z0 ÷ (RS + R0 + Z0))
Z0 = 50 Ω || 50 Ω
RS = 36 Ω || 36 Ω
R0 = 14 Ω
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each output
of the MPC9608 clock driver. For the series terminated case
however there is no DC current draw, thus the outputs can drive
multiple series terminated lines. Figure 5 “Single versus Dual
Transmission Lines” illustrates an output driving a single series
terminated line versus two series terminated lines in parallel.
When taken to its extreme, the fanout of the MPC9608 clock
driver is effectively doubled due to its capability to drive multiple
lines.
VL = 3.0 ( 25 ÷ (18 + 17 + 25))
= 1.31 V
At the load end the voltage will double to 2.6 V due to the
near unity reflection coefficient. It will then increment towards
the quiescent 3.0 V in steps separated by one round trip delay
(in this case 4.0 ns).
1. Skew data are designed targets and pending device specifcations.
TIMING SOLUTIONS
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MPC9608
3.0
MPC9608
OutA
OUTPUT
BUFFER
RS = 22 Ω ZO = 50 Ω
RS = 22 Ω ZO = 50 Ω
tD = 3.8956
OutB
2.5
2.0
1.5
1.0
0.5
0
tD = 3.9386
14 Ω
In
14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω
25 Ω = 25 Ω
Figure 7. Optimized Dual Line Termination
2
4
6
8
10
12
14
TIME (nS)
Figure 6. Single versus Dual Waveforms
Since this step is well above the threshold region, it will not
cause any false clock triggering; however, designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the situation
in Figure 7 “Optimized Dual Line Termination” should be used.
In this case the series terminating resistors are reduced such
that when the parallel combination is added to the output buffer
impedance the line impedance is perfectly matched.
MPC9608 DUT
Pulse
Generator
Z = 50 Ω
ZO = 50 Ω
ZO = 50 Ω
RT = 50 Ω
VTT
RT = 50 Ω
VTT
Figure 8. CCLK MPC9608 AC test reference for VCC = 3.3 V
8
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VCC
VCC
CC ÷ 2
V
CC ÷ 2
CCLK
FB_IN
V
GND
GND
VCC
VCC
V
CC ÷ 2
V
CC ÷ 2
GND
GND
tSK(O)
t(
)
The pin-to-pin skew is defined as the worst case difference in propa-
gation delay between any similar delay path within a single device.
Figure 10. Propagation delay (tPD, static phase offset)
Figure 9. Output-to-output Skew tSK(O)
test reference
VCC
CCLK
V
CC ÷ 2
GND
FB_IN
tP
T0
DC = tP/T0 x 100%
TJIT( ) = |T0 - T1 mean|
The deviation in t0 for a controlled edge with respect to a t0 mean in a
random sample of cycles.
The time from the PLL controlled edge to the non controlled edge, di-
vided by the time between PLL controlled edges, expressed as a per-
centage.
Figure 12. I/O Jitter
Figure 11. Output Duty Cycle (DC)
TJIT(PER) = |TN - 1/f0|
TJIT(CC) = |TN -TN + 1
|
TN
TN + 1
T0
The deviation in cycle time of a signal with respect to the ideal period
over a random sample of cycles.
The variation in cycle time of a signal between adjacent cycles, over a
random sample of adjacent cycle pairs.
Figure 14. Period Jitter
Figure 13. Cycle-to-cycle Jitter
VCC
VCC = 3.3 V
2.4
V
CC ÷ 2
CCLK
GND
VCC
0.55
V
CC ÷ 2
CLK_STOP
tF
tR
GND
ts
tH
Figure 15. Output Transition Time Test Reference
Figure 16. Setup and Hold Time (ts, tH) Test Reference
TIMING SOLUTIONS
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OUTLINE DIMENSIONS
4X
0.20
H
A-B D
6
D1
3
A, B, D
e/2
D1/2
32
PIN 1 INDEX
25
1
F
F
A
B
E1/2
E1
6
E
4
DETAIL G
E/2
DETAIL G
8
17
NOTES:
9
7
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
D
4
D/2
4X
D
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
0.20
C
A-B D
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08-mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07-mm.
H
28X e
32X
0.1 C
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25-mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT
SECTION OF THE LEAD BETWEEN 0.1-mm AND
0.25-mm FROM THE LEAD TIP.
SEATING
PLANE
C
DETAIL AD
BASE
METAL
PLATING
b1
c
c1
MILLIMETERS
DIM
A
A1
A2
b
b1
c
c1
D
MIN
1.40
0.05
1.35
0.30
0.30
0.09
0.09
MAX
1.60
0.15
1.45
0.45
0.40
0.20
0.16
b
5
8
8X (θ1˚)
M
0.20
C
A-B
D
R R2
SECTION F-F
R R1
0.25
9.00 BSC
D1
e
E
E1
L
L1
q
q1
R1
R2
S
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
A2
A
GAUGE PLANE
0.50
1.00 REF
0˚ 7˚
12 REF
0.70
(S)
A1
L
θ˚
0.08
0.08
0.20
---
(L1)
0.20 REF
DETAIL AD
FA SUFFIX
LQFP PACKAGE
AC SUFFIX
LQFP PACKAGE-Pb-free
CASE 873A-02
ISSUE A
10
TIMING SOLUTIONS
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MPC9608
NOTES
11
TIMING SOLUTIONS
For More Information On This Product,
Go to: www.freescale.com
Freescale Semiconductor, Inc.
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied
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© Motorola, Inc. 2004
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HOME PAGE: http://motorola.com/semiconductors
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MPC9608
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