MPC961CACR2 [NXP]

961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32;


型号：	MPC961CACR2
厂家：	NXP
描述：	961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32 驱动输出元件逻辑集成电路
文件：	总12页 (文件大小：294K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MPC961C/D

The MPC961 is a 2.5V or 3.3V compatible, 1:18 PLL based zero delay

buffer. With output frequencies of up to 200MHz, output skews of 150ps

the device meets the needs of the most demanding clock tree

applications.

LOW VOLTAGE

• Fully Integrated PLL

ZERO DELAY BUFFER

• Up to 200MHz I/O Frequency

• LVCMOS Outputs

• Outputs Disable in High Impedance

• LVCMOS Reference Clock Options

• LQFP Packaging

• ±50ps Cycle–Cycle Jitter

• 150ps Output Skews

The MPC961 is offered with two different input configurations. The

MPC961C offers an LVCMOS reference clock while the MPC961P offers

an LVPECL reference clock.

FA SUFFIX

32–LEAD LQFP PACKAGE

CASE 873A–02

When pulled high the OE pin will force all of the outputs (except QFB)

into a high impedance state. Because the OE pin does not affect the QFB

output, down stream clocks can be disabled without the internal PLL

losing lock.

The MPC961 is fully 2.5V or 3.3V compatible and requires no external

loop filter components. All control inputs accept LVCMOS compatible

levels and the outputs provide low impedance LVCMOS outputs capable

of driving terminated 50 transmission lines. For series terminated lines

the MPC961 can drive two lines per output giving the device an effective

fanout of 1:36. The device is packaged in a 32 lead LQFP.

PLL

CCLK

FB_IN

Ref

100 – 200 MHz

50k

50 – 100 MHz

Q14

Q15

Q16

F_RANGE

50k

QFB

The MPC961C requires an external RC filter for the analog power supply pin V . Please see applications section for details.

CCA

Figure 1. MPC961C Logic Diagram

03/01

Motorola, Inc. 2001

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MPC961C

24 23 22 21 20 19 18 17

VCC

Q12

Q13

Q14

GND

Q15

Q16

QFB

GND

MPC961C

VCC

Figure 2. 32–Lead Pinout (Top View)

Table 1: PIN CONFIGURATIONS

I/O

Input

Type

Function

CCLK

FB_IN

LVCMOS

PLL reference clock signal

Input

LVCMOS

Ground

PLL feedback signal input, connect to a QFB output

PLL frequency range select

F_RANGE

Input

Output enable/disable

Q0 - Q16

QFB

Output

Supply

Clock outputs

PLL feedback signal output, connect to a FB_IN

Negative power supply

GND

VCCA

VCC

PLL positive power supply (analog power supply). The MPC961C requires

an external RC filter for the analog power supply pin V

plications section for details.

. Please see ap-

CCA

VCC

Supply

VCC

Positive power supply for I/O and core

Not connected

Table 2: FUNCTION TABLE

Control

Default

F_RANGE

PLL high frequency range. MPC961C input reference

and output clock frequency range is 100 – 200 MHz

PLL low frequency range. MPC961C input reference

and output clock frequency range is 50 – 100 MHz

Outputs enabled

Outputs disabled (high–impedance state)

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Table 3: ABSOLUTE MAXIMUM RATINGS*

Symbol

Parameter

Min

–0.3

Max

Unit

Supply Voltage

3.6

DC Input Voltage

DC Output Voltage

DC Input Current

DC Output Current

+ 0.3

OUT

±20

°C

±50

OUT

Storage Temperature Range

–40

125

* Absolute maximum continuous ratings are those values beyond which damage to the device may occur. Exposure to these conditions or

conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is

not implied.

Table 4: DC CHARACTERISTICS (V

= 3.3V ± 5%, T = –40° to 85°C)

Symbol

Characteristic

Input HIGH Voltage

Min

2.0

Typ

Max

V + 0.3

Unit

Condition

LVCMOS

Input LOW Voltage

–0.3

2.4

0.8

= –20mA

Output HIGH Voltage

OUT

= 20mA

Output LOW Voltage

0.55

Output Impedance

Input Current

±120

µA

Input Capacitance

4.0

8.0

2.0

Power Dissipation Capacitance

Maximum PLL Supply Current

Maximum Quiescent Supply Current

Output Termination Voltage

Per Output

V Pin

5.0

CCA

All VCC Pins

a. The MPC961C is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated

transmission line to a termination voltage of V . Alternatively, the device drives up two 50Ω series terminated transmission lines.

= 3.3V ± 5%, T = –40° to 85°C)

Table 5: AC CHARACTERISTICS (V

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

Input Frequency

F_RANGE = 0

F_RANGE = 1

100

200

100

MHz

ref

Maximum Output Frequency

F_RANGE = 0

F_RANGE = 1

100

200

100

MHz

max

Reference Input Duty Cycle

TCLK Input Rise/Fall Time

3.0

120

refDC

t , t

r f

0.8 to 2.0V

PLL locked

(

Propagation Delay

(static phase offset)

CCLK to FB_IN

–80

)

Output–to–Output Skew

150

sk(O)

Output Duty Cycle

F_RANGE = 0

F_RANGE = 1

t , t

r f

Output Rise/Fall Time

Output Disable Time

Output Enable Time

Cycle–to–Cycle Jitter

Period Jitter

0.1

1.0

0.55 to 2.4V

PLZ HZ

PZL LZ

RMS (1

)

JIT(CC)

)

7.0

JIT(PER)

I/O Phase Jitter

JIT(

lock

)

Maximum PLL Lock Time

a. AC characteristics apply for parallel output termination of 50 to V

b. See applications section for part–to–part skew calculation

c. See applications section for calculation for other confidence factors than 1

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Table 6: DC CHARACTERISTICS (V

= 2.5V ± 5%, T = –40° to 85°C)

Symbol

Characteristic

Input HIGH Voltage

Min

1.7

Typ

Max

V + 0.3

Unit

Condition

LVCMOS

Input LOW Voltage

–0.3

1.8

0.7

= –15mA

Output HIGH Voltage

OUT

= 15mA

Output LOW Voltage

0.6

Output Impedance

Input Current

±120

µA

Input Capacitance

4.0

8.0

2.0

Power Dissipation Capacitance

Maximum PLL Supply Current

Maximum Quiescent Supply Current

Output Termination Voltage

Per Output

V Pin

5.0

CCA

All VCC Pins

a. The MPC961C is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated

transmission line to a termination voltage of V . Alternatively, the device drives up two 50Ω series terminated transmission lines.

= 2.5V ± 5%, T = –40° to 85°C)

Table 7: AC CHARACTERISTICS (V

Symbol

Characteristic

Min

Typ

Max

Unit

Condition

Input Frequency

F_RANGE = 0

F_RANGE = 1

100

200

100

MHz

ref

Maximum Output Frequency

F_RANGE = 0

F_RANGE = 1

100

200

100

MHz

max

refDC

Reference Input Duty Cycle

TCLK Input Rise/Fall Time

3.0

120

t , t

r f

0.7 to 1.7V

PLL locked

(

Propagation Delay

(static phase offset)

CCLK to FB_IN

–80

)

Output–to–Output Skew

150

sk(O)

Output Duty Cycle

F_RANGE = 0

F_RANGE = 1

t , t

r f

Output Rise/Fall Time

Output Disable Time

Output Enable Time

Cycle–to–Cycle Jitter

Period Jitter

0.1

1.0

0.6 to 1.8V

PLZ HZ

PZL LZ

RMS (1

)

JIT(CC)

)

7.0

JIT(PER)

I/O Phase Jitter

JIT(

lock

)

Maximum PLL Lock Time

a. AC characteristics apply for parallel output termination of 50 to V

b. See applications section for part–to–part skew calculation

c. See applications section for calculation for other confidence factors than 1

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MPC961C

Power Supply Filtering

adequate to eliminate power supply noise related problems

in most designs.

The MPC961C is a mixed analog/digital product and as

such it exhibits some sensitivities that would not necessarily

be seen on a fully digital product. Analog circuitry is naturally

susceptible to random noise, especially if this noise is seen

on the power supply pins. The MPC961C provides separate

power supplies for the output buffers (V ) and the

phase–locked loop (V

CCA

design technique is to isolate the high switching noise digital

outputs from the relatively sensitive internal analog

phase–locked loop. In a controlled environment such as an

evaluation board this level of isolation is sufficient. However,

in a digital system environment where it is more difficult to

minimize noise on the power supplies a second level of

isolation may be required. The simplest form of isolation is a

Driving Transmission Lines

The MPC961C clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user the output

drivers were designed to exhibit the lowest impedance

possible. With an output impedance of less than 15Ω the

drivers can drive either parallel or series terminated

transmission lines. For more information on transmission

lines the reader is referred to application note AN1091.

) of the device. The purpose of this

In most high performance clock networks point–to–point

distribution of signals is the method of choice. In a

point–to–point scheme either series terminated or parallel

terminated transmission lines can be used. The parallel

technique terminates the signal at the end of the line with a

50Ω resistance to VCC/2. This technique draws a fairly high

level of DC current and thus only a single terminated line can

be driven by each output of the MPC961C clock driver. For

the series terminated case however there is no DC current

draw, thus the outputs can drive multiple series terminated

lines. Figure 4. illustrates an output driving a single series

terminated line vs two series terminated lines in parallel.

When taken to its extreme the fanout of the MPC961C clock

driver is effectively doubled due to its capability to drive

multiple lines.

power supply filter on the V

pin for the MPC961C.

CCA

Figure 3. illustrates a typical power supply filter scheme.

The MPC961C is most susceptible to noise with spectral

content in the 10kHz to 10MHz range. Therefore the filter

should be designed to target this range. The key parameter

that needs to be met in the final filter design is the DC voltage

drop that will be seen between the V

pin of the MPC961C. From the data sheet the I

(the current sourced through the V

(5mA maximum), assuming that a minimum of 2.375V (V

supply and the V

CCA

current

CCA

pin) is typically 2mA

CCA

3.3V or V

= 2.5V) must be maintained on the V

pin.

The resistor R shown in Figure 3. must have a resistance of

CCA

270Ω (V

= 3.3V) or 5 to 15Ω (V = 2.5V) to meet the

voltage drop criteria. The RC filter pictured will provide a

broadband filter with approximately 100:1 attenuation for

noise whose spectral content is above 20kHz. As the noise

frequency crosses the series resonant point of an individual

capacitor it’s overall impedance begins to look inductive and

thus increases with increasing frequency. The parallel

capacitor combination shown ensures that a low impedance

path to ground exists for frequencies well above the

bandwidth of the PLL.

MPC961

OUTPUT

BUFFER

= 50Ω

R = 36Ω

14Ω

OutA

MPC961

OUTPUT

BUFFER

= 50Ω

R = 36Ω

OutB0

OutB1

R = 270Ω for V = 3.3V

14Ω

R = 5–15Ω for V = 2.5V

R = 36Ω

VCCA

VCC

22 µF

10 nF

MPC961C

Figure 4. Single versus Dual Transmission Lines

VCC

The waveform plots of Figure 5. show the simulation

results of an output driving a single line vs two lines. In both

cases the drive capability of the MPC961C output buffer is

more than sufficient to drive 50Ω transmission lines on the

incident edge. Note from the delay measurements in the

simulations a delta of only 43ps exists between the two

differently loaded outputs. This suggests that the dual line

driving need not be used exclusively to maintain the tight

output–to–output skew of the MPC961C. The output

waveform in Figure 5. shows a step in the waveform, this

step is caused by the impedance mismatch seen looking into

the driver. The parallel combination of the 36Ω series resistor

plus the output impedance does not match the parallel

33...100 nF

Figure 3. Power Supply Filter

Although the MPC961C has several design features to

minimize the susceptibility to power supply noise (isolated

power and grounds and fully differential PLL) there still may

be applications in which overall performance is being

degraded due to system power supply noise. The power

supply filter schemes discussed in this section should be

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MPC961C

combination of the line impedances. The voltage wave

launched down the two lines will equal:

SPICE level and IBIS output buffer models are available

for engineers who want to simulate their specific interconnect

schemes.

VL = VS ( Zo / (Rs + Ro +Zo))

Zo = 50Ω || 50Ω

Rs = 36Ω || 36Ω

Using the MPC961C in zero-delay applications

Ro = 14Ω

Nested clock trees are typical applications for the

MPC961C. Designs using the MPC961C as LVCMOS PLL

fanout buffer with zero insertion delay will show significantly

lower clock skew than clock distributions developed from

CMOS fanout buffers. The external feedback option of the

MPC961C clock driver allows for its use as a zero delay

buffer. By using the QFB output as a feedback to the PLL the

propagation delay through the device is virtually eliminated.

The PLL aligns the feedback clock output edge with the clock

input reference edge resulting a near zero delay through the

device. The maximum insertion delay of the device in

zero-delay applications is measured between the reference

clock input and any output. This effective delay consists of

the static phase offset, I/O jitter (phase or long-term jitter),

feedback path delay and the output-to-output skew error

relative to the feedback output.

VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)

= 1.31V

At the load end the voltage will double, due to the near

unity reflection coefficient, to 2.62V. It will then increment

towards the quiescent 3.0V in steps separated by one round

trip delay (in this case 4.0ns).

3.0

OutA

= 3.8956

OutB

= 3.9386

2.5

2.0

1.5

1.0

0.5

Calculation of part-to-part skew

The MPC961C zero delay buffer supports applications

where critical clock signal timing can be maintained across

several devices. If the reference clock inputs of two or more

MPC961C are connected together, the maximum overall

timing uncertainty from the common CCLK input to any

output is:

= t

+ t

This maximum timing uncertainty consist of 4

SK(PP)

( )

SK(O)

PD, LINE(FB)

JIT( )

TIME (nS)

components: static phase offset, output skew, feedback

board trace delay and I/O (phase) jitter:

Figure 5. Single versus Dual Waveforms

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To

better match the impedances when driving multiple lines the

situation in Figure 6. should be used. In this case the series

terminating resistors are reduced such that when the parallel

combination is added to the output buffer impedance the line

impedance is perfectly matched.

CCLK

Common

PD,LINE(FB)

–t

(

)

QFB

Device 1

JIT(

)

Any Q

Device 1

SK(O)

(

)

MPC961

OUTPUT

BUFFER

= 50Ω

QFB

R = 22Ω

Device2

JIT(

)

14Ω

Any Q

Device 2

SK(O)

R = 22Ω

Max. skew

SK(PP)

Figure 7. MPC961C max. device-to-device skew

14Ω + 22Ω 22Ω = 50Ω 50Ω

25Ω = 25Ω

Due to the statistical nature of I/O jitter a rms value (1 ) is

specified. I/O jitter numbers for other confidence factors (CF)

can be derived from Table 8.

Figure 6. Optimized Dual Line Termination

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convection and thermal conductivity of package and board.

This section describes the impact of these parameters on the

junction temperature and gives a guideline to estimate the

MPC961C die junction temperature and the associated

device reliability. For a complete analysis of power

consumption as a function of operating conditions and

associated long term device reliability please refer to the

application note AN1545. According the AN1545, the

long-term device reliability is a function of the die junction

temperature:

Table 8: Confidence Facter CF

Probability of clock edge within the distribution

± 1

± 2

± 3

± 4

± 5

± 6

0.68268948

0.95449988

0.99730007

0.99993663

0.99999943

0.99999999

The feedback trace delay is determined by the board

layout and can be used to fine-tune the effective delay

through each device. In the following example calculation a

I/O jitter confidence factor of 99.7% (± 3 ) is assumed,

resulting in a worst case timing uncertainty from input to any

output of -275 ps to 315 ps relative to CCLK:

Table 9: Die junction temperature and MTBF

Junction temperature (°C)

MTBF (Years)

100

110

120

130

20.4

9.1

4.2

2.0

[–80ps...120ps] + [–150ps...150ps] +

[(15ps –3)...(15ps 3)] + t

SK(PP)

PD, LINE(FB)

[–275ps...315ps] + t

PD, LINE(FB)

Increased power consumption will increase the die

junction temperature and impact the device reliability

(MTBF). According to the system-defined tolerable MTBF,

the die junction temperature of the MPC961C needs to be

controlled and the thermal impedance of the board/package

should be optimized. The power dissipated in the MPC961C

is represented in equation 1.

SK(PP)

Due to the frequency dependence of the I/O jitter,

Figure 8. “Max. I/O Jitter versus frequency” can be used for

a more precise timing performance analysis.

Where I

is the static current consumption of the

is the power dissipation capacitance per

CCQ

MPC961C, C

output, (Μ)ΣC represents the external capacitive output

load, N is the number of active outputs (N is always 27 in

case of the MPC961C). The MPC961C supports driving

transmission lines to maintain high signal integrity and tight

timing parameters. Any transmission line will hide the lumped

capacitive load at the end of the board trace, therefore, ΣC is

zero for controlled transmission line systems and can be

eliminated from equation 1. Using parallel termination output

termination results in equation 2 for power dissipation.

In equation 2, P stands for the number of outputs with a

Figure 8. Max. I/O Jitter versus frequency

parallelorthevenintermination, V , I , V

and I

are a

OL OL OH

function of the output termination technique and DC is the

Power Consumption of the MPC961C and Thermal

Management

clock signal duty cyle. If transmission lines are used ΣC is

The MPC961C AC specification is guaranteed for the

entire operating frequency range up to 200 MHz. The

MPC961C power consumption and the associated long-term

reliability may decrease the maximum frequency limit,

depending on operating conditions such as clock frequency,

supply voltage, output loading, ambient temperature, vertical

zero in equation 2 and can be eliminated. In general, the use

of controlled transmission line techniques eliminates the

impact of the lumped capacitive loads at the end lines and

greatly reduces the power dissipation of the device. Equation

3 describes the die junction temperature T as a function of

the power consumption.

P_TOT

I_CCQV_CCf_CLOCK

C_PD

C_L

V_CC

Equation 1

Equation 2

P_TOT

V_CC

I_CCQV_CCf_CLOCK

C_PD

C_L

DC_QI_OHV_CCV_OH

DC_QI_OLV_OL

Equation 3

Equation 4

T_J

T_AP_TOTR_thja

T_J,MAXT_A

R_thja

f_CLOCK,MAX

I_CCQV_CC

C_PD

V²_CC

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Where R

is the thermal impedance of the package

should be selected according to the MTBF system

J,MAX

thja

(junction to ambient) and T is the ambient temperature.

requirements and Table 9. R

The R

boards will result in a lower thermal impedance than

indicated below.

can be derived from Table10.

thja

represent data based on 1S2P boards, using 2S2P

According to Table 9, the junction temperature can be used to

estimate the long-term device reliability. Further, combining

equation 1 and equation 2 results in a maximum operating

frequency for the MPC961C in a series terminated

transmission line system.

thja

If the calculated maximum frequency is below 200 MHz, it

becomes the upper clock speed limit for the given application

conditions. The following two derating charts describe the

safe frequency operation range for the MPC961C. The charts

were calculated for a maximum tolerable die junction

temperature of 110°C, corresponding to an estimated MTBF

of 9.1 years, a supply voltage of 3.3V and series terminated

transmission line or capacitive loading. Depending on a given

set of these operating conditions and the available device

convection a decision on the maximum operating frequency

can be made. There are no operating frequency limitations if

a 2.5V power supply or the system specifications allow for a

MTBF of 4 years (corresponding to a max. junction

temperature of 120°C.

Table 10: Thermal package impedance of the 32ld

LQFP

Convection, LFPM

Still air

(1P2S board), K/W

thja

100 lfpm

200 lfpm

300 lfpm

400 lfpm

500 lfpm

200

(AC)

MAX

180

160

140

120

100

180

160

140

120

100

T = 85°C

T = 75°C

T = 85°C

Safe operation

500

400

300

200

100

500

400

300

200

100

, CONVECTION

FPM

Figure 9. Maximum MPC961C frequency, V

= 3.3V, MTBF

Figure 10. Maximum MPC961C frequency,

V = 3.3V, MTBF 9.1 years, 4 pF load per line

9.1 years, driving series terminated transmission lines

MPC961C DUT

Pulse

Generator

Z = 50

= 50Ω

Z = 50Ω

R = 50Ω

Figure 11. TCLK MPC961C AC test reference for V = 3.3V and V = 2.5V

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GND

CCLK

FB_IN

GND

SK(O)

(

)

The pin–to–pin skew is defined as the worst case difference in prop-

agation delay between any similar delay path within a single device

Figure 12. Output–to–output Skew t

SK(O)

Figure 13. Propagation delay (t , static phase

offset) test reference

GND

CCLK

FB_IN

DC = t /T x 100%

P 0

JIT

= |T –T mean|

0 1

)

The time from the PLL controlled edge to the non controlled edge,

divided by the time between PLL controlled edges, expressed as a

percentage

The deviation in t for a controlled edge with respect to a t mean in a

random sample of cycles

Figure 14. Output Duty Cycle (DC)

Figure 15. I/O Jitter

= |T –T

N+1

= |T –1/f |

JIT(CC)

JIT(PER) N 0

N+1

The variation in cycle time of a signal between adjacent cycles, over a

random sample of adjacent cycle pairs

The deviation in cycle time of a signal with respect to the ideal period over

a random sample of cycles

Figure 16. Cycle–to–cycle Jitter

Figure 17. Period Jitter

V =3.3V

V =2.5V

2.4

0.55

1.8V

0.6V

Figure 18. Output Transition Time Test

Reference

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OUTLINE DIMENSIONS

FA SUFFIX

LQFP PACKAGE

CASE 873A–02

ISSUE A

0.20 (0.008) AB T–U

–U–

–T–

DETAIL Y

–Z–

DETAIL Y

0.20 (0.008) AC T–U

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DATUM PLANE –AB– IS LOCATED AT BOTTOM OF

LEAD AND IS COINCIDENT WITH THE LEAD

WHERE THE LEAD EXITS THE PLASTIC BODY AT

THE BOTTOM OF THE PARTING LINE.

4. DATUMS –T–, –U–, AND –Z– TO BE DETERMINED

AT DATUM PLANE –AB–.

DETAIL AD

5. DIMENSIONS S AND V TO BE DETERMINED AT

SEATING PLANE –AC–.

–AB–

6. DIMENSIONS A AND B DO NOT INCLUDE MOLD

PROTRUSION. ALLOWABLE PROTRUSION IS

0.250 (0.010) PER SIDE. DIMENSIONS A AND B

DO INCLUDE MOLD MISMATCH AND ARE

DETERMINED AT DATUM PLANE –AB–.

7. DIMENSION D DOES NOT INCLUDE DAMBAR

PROTRUSION. DAMBAR PROTRUSION SHALL

NOT CAUSE THE D DIMENSION TO EXCEED

0.520 (0.020).

SEATING

PLANE

–AC–

0.10 (0.004) AC

BASE

METAL

8. MINIMUM SOLDER PLATE THICKNESS SHALL BE

0.0076 (0.0003).

9. EXACT SHAPE OF EACH CORNER MAY VARY

FROM DEPICTION.

8X M

MILLIMETERS

DIM MIN MAX

7.000 BSC

INCHES

MIN MAX

0.276 BSC

0.138 BSC

0.276 BSC

0.138 BSC

3.500 BSC

7.000 BSC

3.500 BSC

SECTION AE–AE

1.400

1.600 0.055

0.063

0.018

0.057

0.016

0.300

1.350

0.300

0.450 0.012

1.450 0.053

0.400 0.012

0.800 BSC

0.031 BSC

0.050

0.090

0.500

0.150 0.002

0.200 0.004

0.700 0.020

0.006

0.008

0.028

12 REF

0.006

0.016 BSC

DETAIL AD

0.090

0.160 0.004

0.400 BSC

0.150

0.250 0.006

0.010

9.000 BSC

0.354 BSC

4.500 BSC

9.000 BSC

4.500 BSC

0.200 REF

1.000 REF

0.177 BSC

0.354 BSC

0.177 BSC

0.008 REF

0.039 REF

For More Information On This Product,

MOTOROLA

TIMING SOLUTIONS

DL207 — Rev 0

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MPC961C

NOTES

For More Information On This Product,

TIMING SOLUTIONS

DL207 — Rev 0

MOTOROLA

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MPC961C

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or

guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the

applicationor use of any product or circuit, and specifically disclaims any and all liability, includingwithoutlimitationconsequentialorincidental

damages. “Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in differentapplications

and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application

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BuyershallindemnifyandholdMotorolaanditsofficers, employees, subsidiaries, affiliates, anddistributorsharmlessagainstallclaims, costs,

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How to reach us:

USA/EUROPE/Locations Not Listed: Motorola Literature Distribution;

JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1,

P.O. Box 5405, Denver, Colorado 80217. 1–303–675–2140 or 1–800–441–2447 Minami–Azabu. Minato–ku, Tokyo 106–8573 Japan. 81–3–3440–3569

Technical Information Center: 1–800–521–6274

ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre,

2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

852–26668334

HOME PAGE: http://www.motorola.com/semiconductors/

For More Information On This Product,

MOTOROLA

TIMING SOLUTIONS

◊

MPC961C/D

Go to: www.freescale.com

DL207 — Rev 0

MPC961CACR2 [NXP]

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