MPC961PAC [NXP]

961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32;


型号：	MPC961PAC
厂家：	NXP
描述：	961 SERIES, PLL BASED CLOCK DRIVER, 17 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32 驱动输出元件逻辑集成电路
文件：	总9页 (文件大小：162K)
中文：	中文翻译
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Freescale Semiconductor, Inc.

TECHNICAL DATA

Order number: MPC961P

Rev 3, 08/2004

Low Voltage Zero Delay Buffer

The MPC961 is a 2.5 V or 3.3 V compatible, 1:18 PLL based zero delay

buffer. With output frequencies of up to 200 MHz, output skews of 150 ps the

device meets the needs of the most demanding clock tree applications.

MPC961P

LOW VOLTAGE

ZERO DELAY BUFFER

Features

•

Fully Integrated PLL

Up to 200 MHz I/O Frequency

LVCMOS Outputs

Outputs Disable in High Impedance

LVPECL Reference Clock Options

LQFP Packaging

FA SUFFIX

32-LEAD LQFP PACKAGE

CASE 873A-03

32-lead Pb-free Package Available

±50 ps Cycle-Cycle Jitter

150 ps Output Skews

Functional Description

The MPC961 is offered with two different input configurations. The

MPC961P offers an LVCMOS reference clock while the MPC961P offers an

LVPECL reference clock.

When pulled high the OE pin will force all of the outputs (except QFB) into a high impedance state. Because the OE pin does not

affect the QFB output, down stream clocks can be disabled without the internal PLL losing lock.

The MPC961 is fully 2.5 V or 3.3 V compatible and requires no external loop filter components. All control inputs accept LVCMOS

compatible levels and the outputs provide low impedance LVCMOS outputs capable of driving terminated 50 Ω transmission lines.

For series terminated lines the MPC961 can drive two lines per output giving the device an effective fanout of 1:36. The device is

packaged in a 32 lead LQFP package to provide the optimum combination of board density and performance.

V_CC

50 k

PCLK

PLL

Ref

100 – 200 MHz

50 k

50 – 100 MHz

FB_IN

F_RANGE

Q14

Q15

Q16

50 k

QFB

The MPC961P requires an external RC filter for the analog power supply pin V_CCA. Refer to APPLICATIONS INFORMATION for details.

Figure 1. MPC961P Logic Diagram

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FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

MPC961P

24 23 22 21 20 19 18 17

V_CC

Q12

Q13

Q14

GND

Q15

GND

MPC961P

Q16

QFB

V_CC

Figure 2. 32-Lead Pinout (Top View)

Table 1. Pin Configurations

Number

PCLK, PCLK

FB_IN

Name

Type

LVCMOS

Description

Input

PLL reference clock signal

Input

LVCMOS

Ground

PLL feedback signal input, connect to a QFB output

PLL frequency range select

F_RANGE

Input

Output enable/disable

Q0 – Q16

QFB

Output

Clock outputs

PLL feedback signal output, connect to a FB_IN

Negative power supply

GND

Supply

V_CCA

V_CC

PLL positive power supply (analog power supply). The MPC961P requires an

external RC filter for the analog power supply pin V_CCA. Please see applications

section for details.

V_CC

Supply

V_CC

Positive power supply for I/O and core

Table 2. Function Table

Control

Default

F_RANGE

PLL high frequency range. MPC961P input reference and

output clock frequency range is 100 – 200 MHz

PLL low frequency range. MPC961P input reference and

output clock frequency range is 50 – 100 MHz

Outputs enabled

Outputs disabled (high-impedance state)

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

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MPC961P

Table 3. Absolute Maximum Ratings¹

Symbol

Characteristics

Min

Max

Unit

Condition

V_CC

Supply Voltage

–0.3

3.6

V_IN

V_OUT

I_IN

DC Input Voltage

DC Output Voltage

DC Input Current

DC Output Current

Storage Temperature

–0.3

V_CC+ 0.3

±20

°C

I_OUT

T_S

±50

–40

125

1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions

or conditions beyond those indicated may adversely affect device reliability. Functional operation under absolute-maximum-rated conditions is not

implied.

Table 4. DC Characteristics (V_CC= 3.3 V ± 5%, T_A= –40° to 85°C)

Symbol

Characteristics

Input HIGH Voltage

Min

2.0

Typ

Max

V_CC+ 0.3

Unit

Condition

LVCMOS

V_IH

V_IL

V_PP

Input LOW Voltage

–0.3

500

1.2

0.8

1000

Peak-to-peak input voltage¹PECL_CLK, PECL_CLK

mV LVPECL

Common Mode Range²

PECL_CLK, PECL_CLK

V_CMR

V_OH

V_CC– 0.8

LVPECL

I_OH= –20 mA²

I_OL= 20 mA²

Output HIGH Voltage

2.4

V_OL

Output LOW Voltage

0.55

Z_OUT

I_IN

Output Impedance

Ω

Input Current

±120

µA

C_IN

Input Capacitance

4.0

8.0

2.0

C_PD

I_CCA

I_CC

Power Dissipation Capacitance

Maximum PLL Supply Current

pF Per Output

mA V_CCAPin

mA All V_CCPins

5.0

Maximum Quiescent Supply Current

Output Termination Voltage

V_TT

V_CC÷ 2

1. Exceeding the specified V_CMR/V_PPwindow results in a t_PDchanges of approximately 250 ps.

2. The MPC961P is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission

line to a termination voltage of V_TT. Alternatively, the device drives up two 50 Ω series terminated transmission lines.

Table 5. AC Characteristics (V_CC= 3.3 V ± 5%, T_A= –40° to 85°C)¹

Symbol

f_REF

Characteristics

Input Frequency

Min

100

Typ

Max

200

100

200

100

Unit

MHz

Condition

F_RANGE = 0

F_RANGE = 1

f_MAX

Maximum Output Frequency F_RANGE = 0

F_RANGE = 1

Reference Input Duty Cycle

MHz

f_REFDC

t_(∅)

Propagation Delay²

(static phase offset)

PECL_CLK to FB_IN

–80

120

ps PLL locked

Output-to-Output Skew³

Output Duty Cycle

t_sk(O)

DC_O

150

F_RANGE = 0

F_RANGE = 1

t_r, t_f

Output Rise/Fall Time

Output Disable Time

Output Enable Time

0.1

1.0

ns 0.6 to 1.8V

t_{PLZ HZ}

t_{PZL LZ}

t_JIT(CC)

Cycle-to-Cycle Jitter

RMS (1σ)⁴

RMS (1σ)

t_JIT(PER)Period Jitter

7.0

t_JIT(∅)I/O Phase Jitter

RMS (1σ) F_RANGE = 0

ns T = Clock Signal Period

0.0015 · T

0.0010 · T

F_RANGE = 1

t_lock

1. AC characteristics apply for parallel output termination of 50 Ω to V_TT

2. _PDapplies for V_CMR= V_CC–1.3 V and V_PP= 800 mV.

3. Refer to APPLICATIONS INFORMATION for part-to-part skew calculation.

4. Refer to APPLICATIONS INFORMATION for calculation for other confidence factors than 1σ.

Maximum PLL Lock Time

494

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

MPC961P

Table 6. DC Characteristics (V_CC= 2.5 V ± 5%, T_A= –40° to 85°C)

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

V_IH

Input HIGH Voltage

Input LOW Voltage

1.7

V_CC+ 0.3

LVCMOS

V_IL

V_PP

–0.3

500

1.2

0.7

1000

Peak-to-peak input voltage¹PECL_CLK, PECL_CLK

mV LVPECL

Common Mode Range^a

Output HIGH Voltage

PECL_CLK, PECL_CLK

V_CMR

V_OH

V_CC– 0.7

LVPECL

I_OH= –15 mA²

I_OL= 15 mA^b

1.8

V_OL

Output LOW Voltage

0.6

Z_OUT

I_IN

Output Impedance

Ω

Input Current

±120

µA

C_IN

Input Capacitance

4.0

8.0

2.0

C_PD

I_CCA

I_CC

Power Dissipation Capacitance

Maximum PLL Supply Current

pF Per Output

mA V_CCAPin

mA All V_CCPins

5.0

Maximum Quiescent Supply Current

Output Termination Voltage

V_TT

V_CC÷ 2

1. Exceeding the specified V_CMR/V_PPwindow results in a t_PDchanges < 250 ps.

2. The MPC961P is capable of driving 50 Ω transmission lines on the incident edge. Each output drives one 50 Ω parallel terminated transmission

line to a termination voltage of V_TT. Alternatively, the device drives up two 50 Ω series terminated transmission lines.

Table 7. AC Characteristics (V_CC= 2.5 V ± 5%, T_A= –40° to 85°C)¹

Symbol

Characteristics

Min

Typ

Max

Unit

Condition

f_REF

Input Frequency

F_RANGE = 0

F_RANGE = 1

100

200

100

MHz

f_MAX

Maximum Output Frequency

F_RANGE = 0

F_RANGE = 1

100

200

100

MHz

f_REFDC

t_(∅)

Reference Input Duty Cycle

Propagation Delay²

(static phase offset)

CCLK to FB_IN

–50

175

PLL locked

Output-to-Output Skew³

Output Duty Cycle

t_sk(O)

DC_O

150

F_RANGE = 0

F_RANGE = 1

t_r, t_f

Output Rise/Fall Time

Output Disable Time

Output Enable Time

0.1

1.0

0.6 to 1.8 V

t_{PLZ HZ}

t_{PZL LZ}

t_JIT(CC)

Cycle-to-Cycle Jitter

RMS (1σ)⁴

RMS (1σ)

t_JIT(PER)Period Jitter

7.0

t_JIT(∅)

I/O Phase Jitter

RMS (1σ) F_RANGE = 0

T = Clock Signal

Period

0.0015 · T

0.0010 · T

F_RANGE = 1

t_lock

Maximum PLL Lock Time

1. AC characteristics apply for parallel output termination of 50 Ω to V_TT

2. _PDapplies for V_CMR= V_CC–1.3 V and V_PP= 800 mV.

3. Refer to APPLICATIONS INFORMATION for part-to-part skew calculation.

4. Refer to APPLICATIONS INFORMATION for calculation for other confidence factors than 1σ.

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

495

MPC961P

APPLICATIONS INFORMATION

schemes discussed in this section should be adequate to

Power Supply Filtering

eliminate power supply noise related problems in most designs.

The MPC961P is a mixed analog/digital product and as such

it exhibits some sensitivities that would not necessarily be seen

on a fully digital product. Analog circuitry is naturally susceptible

to random noise, especially if this noise is seen on the power

supply pins. The MPC961P provides separate power supplies

Driving Transmission Lines

The MPC961P clock driver was designed to drive high speed

signals in a terminated transmission line environment. To

provide the optimum flexibility to the user the output drivers

were designed to exhibit the lowest impedance possible. With

an output impedance of less than 15 Ω the drivers can drive

either parallel or series terminated transmission lines. For more

information on transmission lines the reader is referred to

application note AN1091.

In most high performance clock networks point-to-point

distribution of signals is the method of choice. In a point-to-point

scheme either series terminated or parallel terminated

transmission lines can be used. The parallel technique

terminates the signal at the end of the line with a 50 Ω

resistance to V_CC/2. This technique draws a fairly high level of

DC current and thus only a single terminated line can be driven

by each output of the MPC961P clock driver. For the series

terminated case however there is no DC current draw, thus the

outputs can drive multiple series terminated lines. Figure 4

illustrates an output driving a single series terminated line vs

two series terminated lines in parallel. When taken to its

extreme the fanout of the MPC961P clock driver is effectively

doubled due to its capability to drive multiple lines.

for the output buffers (V_CC) and the phase-locked loop (V_CCA

)

of the device. The purpose of this design technique is to isolate

the high switching noise digital outputs from the relatively

sensitive internal analog phase-locked loop. In a controlled

environment such as an evaluation board this level of isolation

is sufficient. However, in a digital system environment where it

is more difficult to minimize noise on the power supplies, a

second level of isolation may be required. The simplest form of

isolation is a power supply filter on the V_CCApin for the

MPC961P.

Figure 3 illustrates a typical power supply filter scheme. The

MPC961P is most susceptible to noise with spectral content in

the 10 kHz to 5 MHz range. Therefore the filter should be

designed to target this range. The key parameter that needs to

be met in the final filter design is the DC voltage drop that will

be seen between the V_CCsupply and the V_CCApin of the

MPC961P. From the data sheet the I_CCAcurrent (the current

sourced through the V_CCApin) is typically 2 mA

(5 mA maximum), assuming that a minimum of 2.375 V (V_CC

3.3 V or V_CC= 2.5 V) must be maintained on the V_CCApin. The

resistor R_Fshown in Figure 3 must have a resistance of 270 Ω

(V_CC= 3.3 V) or 5 to 15 Ω (V_CC= 2.5 V) to meet the voltage

drop criteria. The RC filter pictured will provide a broadband

filter with approximately 100:1 attenuation for noise whose

spectral content is above 20 kHz. As the noise frequency

crosses the series resonant point of an individual capacitor it's

overall impedance begins to look inductive and thus increases

with increasing frequency. The parallel capacitor combination

shown ensures that a low impedance path to ground exists for

frequencies well above the bandwidth of the PLL.

MPC961

OUTPUT

BUFFER

_O= 50 Ω

R_S= 36 Ω

14 Ω

OutA

MPC961

OUTPUT

BUFFER

_O= 50 Ω

R_S= 36 Ω

R_F= 270 Ω for V_CC= 3.3 V

R_F= 5–15 Ω for V_CC= 2.5 V

OutB0

OutB1

14 Ω

R_F

V_CCA

V_CC

C_F

10 nF

MPC961P

V_CC

Figure 4. Single versus Dual Transmission Lines

33...100 nF

The waveform plots of Figure 5 show the simulation results

of an output driving a single line vs two lines. In both cases the

drive capability of the MPC961P output buffer is more than

sufficient to drive 50 Ω transmission lines on the incident edge.

Note from the delay measurements in the simulations a delta of

only 43 ps exists between the two differently loaded outputs.

This suggests that the dual line driving need not be used

exclusively to maintain the tight output-to-output skew of the

MPC961P. The output waveform in Figure 5 shows a step in the

waveform, this step is caused by the impedance mismatch seen

Figure 3. Power Supply Filter

Although the MPC961P has several design features to

minimize the susceptibility to power supply noise (isolated

power and grounds and fully differential PLL) there still may be

applications in which overall performance is being degraded

due to system power supply noise. The power supply filter

496

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

MPC961P

looking into the driver. The parallel combination of the 36 Ω

series resistor plus the output impedance does not match the

parallel combination of the line impedances. The voltage wave

launched down the two lines will equal:

SPICE level and IBIS output buffer models are available for

engineers who want to simulate their specific interconnect

schemes.

Using the MPC961P in Zero-Delay Applications

VL = VS (Z_O/ (R_S+ R_O+Z_O))

Nested clock trees are typical applications for the MPC961P.

Designs using the MPC961P as LVCMOS PLL fanout buffer

with zero insertion delay will show significantly lower clock skew

than clock distributions developed from CMOS fanout buffers.

The external feedback option of the MPC961P clock driver

allows for its use as a zero delay buffer. By using the QFB

output as a feedback to the PLL the propagation delay through

the device is virtually eliminated. The PLL aligns the feedback

clock output edge with the clock input reference edge resulting

a near zero delay through the device. The maximum insertion

delay of the device in zero-delay applications is measured

between the reference clock input and any output. This effective

delay consists of the static phase offset, I/O jitter (phase or

long-term jitter), feedback path delay and the output-to-output

skew error relative to the feedback output.

Z_O= 50 Ω || 50 Ω

R_S= 36 Ω || 36 Ω

R_O= 14 Ω

VL = 3.0 (25 / (18 + 14 + 25) = 3.0 (25 / 57)

= 1.31 V

At the load end the voltage will double, due to the near unity

reflection coefficient, to 2.62 V. It will then increment towards

the quiescent 3.0 V in steps separated by one round trip delay

(in this case 4.0ns).

3.0

OutA

OutB

_D= 3.9386

2.5

2.0

1.5

1.0

0.5

t_D= 3.8956

Calculation of Part-to-Part Skew

The MPC961P zero delay buffer supports applications where

critical clock signal timing can be maintained across several

devices. If the reference clock inputs of two or more MPC961P

are connected together, the maximum overall timing uncertainty

from the common PCLK input to any output is:

t_SK(PP)= t_(∅)+ t_SK(O)+ t_{PD, LINE(FB)}+ t_JIT(∅)· CF

This maximum timing uncertainty consist of 4 components:

static phase offset, output skew, feedback board trace delay

and I/O (phase) jitter:

TIME (ns)

TCLK_Common

t_PD,LINE(FB)

Figure 5. Single versus Dual Waveforms

—t(ý)

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines the situation

in Figure 6 should be used. In this case the series terminating

resistors are reduced such that when the parallel combination

is added to the output buffer impedance the line impedance is

perfectly matched.

QFB_{Device 1}

t_JIT(∅)

Any Q_{Device 1}

+t_SK(O)

+t_(∅)

QFB_Device2

MPC961

OUTPUT

BUFFER

t_JIT(∅)

_O= 50 Ω

R_S= 22 Ω

Any Q_{Device 2}

Max. skew

+t_SK(O)

14 Ω

_O= 50 Ω

t_SK(PP)

Figure 7. MPC961P Max. Device-to-Device Skew

Due statistical nature of I/O jitter a rms value (1σ) is

specified. I/O jitter numbers for other confidence factors (CF)

can be derived from Table 8.Confidence Factor CF.

14 Ω + 22 Ω || 22 Ω = 50 Ω || 50 Ω

25 Ω = 25 Ω

Figure 6. Optimized Dual Line Termination

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

497

MPC961P

describes the impact of these parameters on the junction

temperature and gives a guideline to estimate the MPC961P

die junction temperature and the associated device reliability.

For a complete analysis of power consumption as a function of

operating conditions and associated long term device reliability

refer to the Application Note AN1545. According the AN1545,

the long-term device reliability is a function of the die junction

temperature:

Table 8. Confidence Factor CF

Probability of clock edge within the distribution

± 1σ

± 2σ

± 3σ

± 4σ

± 5σ

± 6σ

0.68268948

0.95449988

0.99730007

0.99993663

0.99999943

0.99999999

Table 9. Die Junction Temperature and MTBF

Junction temperature (°C)

MTBF (Years)

100

110

120

130

20.4

9.1

4.2

2.0

The feedback trace delay is determined by the board layout

and can be used to fine-tune the effective delay through each

device. In the following example calculation a I/O jitter

confidence factor of 99.7% (± 3σ) is assumed, resulting in a

worst case timing uncertainty from input to any output of

–236 ps to 361 ps relative to PCLK (f=125 MHz, V_CC=2.5 V):

t_SK(PP)= [-50 ps...175ps] + [-150 ps...150 ps] +

Increased power consumption will increase the die junction

temperature and impact the device reliability (MTBF).

According to the system-defined tolerable MTBF, the die

junction temperature of the MPC961P needs to be controlled

and the thermal impedance of the board/package should be

optimized. The power dissipated in the MPC961P is

represented in equation 1.

[(12ps @ -3)...(12ps @ 3)] + t_{PD, LINE(FB)}

t_SK(PP)= [-236ps...361ps] + t_{PD, LINE(FB)}

Due to the frequency dependence of the I/O jitter, Figure 8

“Max. I/O Jitter versus frequency” can be used for a more

precise timing performance analysis.

Where I_CCQis the static current consumption of the

MPC961P, C_PDis the power dissipation capacitance per output,

(Μ)ΣC_Lrepresents the external capacitive output load, N is the

number of active outputs (N is always 27 in case of the

MPC961P). The MPC961P supports driving transmission lines

to maintain high signal integrity and tight timing parameters.

Any transmission line will hide the lumped capacitive load at the

end of the board trace, therefore, ΣC_Lis zero for controlled

transmission line systems and can be eliminated from

equation 1. Using parallel termination output termination results

in equation 2 for power dissipation.

F_RANGE = 1

F_RANGE = 0

= 2.5 V

= 3.3 V

= 2.5 V

110 130 150 170 190

Clock frequency [MHz]

In equation 2, P stands for the number of outputs with a

parallel or thevenin termination, V_OL, I_OL, V_OH, and I_OHare a

function of the output termination technique and DC_Qis the

clock signal duty cycle. If transmission lines are used ΣC_Lis

zero in equation 2 and can be eliminated. In general, the use of

controlled transmission line techniques eliminates the impact of

the lumped capacitive loads at the end lines and greatly

reduces the power dissipation of the device. Equation 3

describes the die junction temperature T_Jas a function of the

power consumption.

Figure 8. Max. I/O Jitter versus Frequency

Power Consumption of the MPC961P

and Thermal Management

The MPC961P AC specification is guaranteed for the entire

operating frequency range up to 200 MHz. The MPC961P

power consumption and the associated long-term reliability

may decrease the maximum frequency limit, depending on

operating conditions such as clock frequency, supply voltage,

output loading, ambient temperature, vertical convection and

thermal conductivity of package and board. This section

Equation 1

P_TOT= [ I_CCQ+ V_CC· f_CLOCK· ( N · C_PD+ Σ C_L) ] · V_CC

P_TOT= V_CC· [ I_CCQ+ V_CC· f_CLOCK· ( N · C_PD+ Σ C_L) ] + Σ [ DC_Q· I_OH· (V_CC– V_OH) + (1 – DC_Q) · I_OL· V_OL]

Equation 2

Equation 3

T_J= T_A+ P_TOT· R_thja

T_j,MAX– T_A

– (I_CCQ· V_CC

)

]

Equation 4

f_CLOCK,MAX

[

C_PD· N · V²

R_thja

498

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

MPC961P

Where R_thjais the thermal impedance of the package

(junction to ambient) and T_Ais the ambient temperature.

According to Table 9.Die Junction Temperature and MTBF, the

junction temperature can be used to estimate the long-term

device reliability. Further, combining equation 1 and equation 2

results in a maximum operating frequency for the MPC961P in

a series terminated transmission line system.

T_J,MAXshould be selected according to the MTBF system

requirements and Table 9.Die Junction Temperature and MTBF.

R_thjacan be derived from Table 10.Thermal Package

Impedance of the 32ld LQFP. The R_thjarepresent data based

on 1S2P boards, using 2S2P boards will result in a lower

thermal impedance than indicated below.

If the calculated maximum frequency is below 200 MHz, it

becomes the upper clock speed limit for the given application

conditions. The following two derating charts describe the safe

frequency operation range for the MPC961P. The charts were

calculated for a maximum tolerable die junction temperature of

110°C, corresponding to an estimated MTBF of 9.1 years, a

supply voltage of 3.3 V and series terminated transmission line

or capacitive loading. Depending on a given set of these

operating conditions and the available device convection a

decision on the maximum operating frequency can be made.

There are no operating frequency limitations if a 2.5 V power

supply or the system specifications allow for a MTBF of 4 years

(corresponding to a max. junction temperature of 120°C.

Table 10. Thermal Package Impedance of the 32ld LQFP

R_thja(1P2S board), K/W

Convection, LFPM

Still air

100 lfpm

200 lfpm

300 lfpm

400 lfpm

500 lfpm

200

_MAX(AC)

f_MAX(AC)

180

160

140

120

100

180

160

140

120

100

T_A= 85°C

T_A= 75°C

_A= 85°C

Safe operation

500

400

300

200

100

400

300

200

100

I_FPM, CONVECTION

Figure 9. Maximum MPC961P Frequency, V_CC= 3.3 V,

Figure 10. Maximum MPC961P Frequency,

V_CC= 3.3 V, MTBF 9.1 Years, 4 pF Load per Line

MTBF 9.1 Years, Driving Series Terminated

Transmission Lines

MPC961P DUT

Pulse

Generator

Z = 50 Ω

Z_O= 50 Ω

R_T= 50 Ω

V_TT

Figure 11. TCLK MPC961P AC Test Reference for V_CC= 3.3 V and V_CC= 2.5 V

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

499

MPC961P

PCLK

V_PP

V_CMR

V_CC= 3.3 V V_CC= 2.5 V

2.4

1.8 V

V_CC

_CC÷ 2

0.55

0.6 V

Ext_FB

GND

t_F

t_R

t_(∅)

Figure 12. Propagation Delay (t_∅, static phase

offset) Test Reference

Figure 13. Output Transition Time Test

Reference

V_CC

V_CC÷ 2

_CC÷ 2

GND

V_CC

t_P

_CC÷ 2

T₀

GND

DC = t_P/T₀x 100%

t_SK(O)

The pin-to-pin skew is defined as the worst case difference

in propagation delay between any similar delay path within a

single device

The time from the PLL controlled edge to the non controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

Figure 14. Output Duty Cycle (DC)

Figure 15. Output-to-Output Skew t_SK(O)

T_JIT(CC)= |T_N–T_N+1

T_JIT(PER)= |T_N–1/f₀|

T_N

T_N+1

T₀

The variation in cycle time of a signal between adjacent cycles,

over a random sample of adjacent cycle pairs

The deviation in cycle time of a signal with respect to the ideal

period over a random sample of cycles

Figure 16. Cycle-to-Cycle Jitter

Figure 17. Period Jitter

PCLK

Ext_FB

T_JIT(∅)= |T₀–T₁mean|

The deviation in t₀for a controlled edge with respect to a T₀

mean in a random sample of cycles

Figure 18. I/O Jitter

500

FREESCALE SEMICONDUCTOR ADVANCED CLOCK DRIVERS DEVICE DATA

MPC961PAC [NXP]

相关型号：

SI9130DB

SI9135LG-T1

SI9135LG-T1-E3

SI9135_11

SI9136_11

SI9130CG-T1-E3

SI9130LG-T1-E3

SI9130_11

SI9137

SI9137DB

SI9137LG

SI9122E