MPC962305DT-1H [NXP]

IC,1:5 OUTPUT,TSSOP,8PIN,PLASTIC;


型号：	MPC962305DT-1H
厂家：	NXP
描述：	IC,1:5 OUTPUT,TSSOP,8PIN,PLASTIC 输出元件
文件：	总12页 (文件大小：439K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Freescale Semiconductor, Inc.

MOTOROLA

Order number: MPC962305

Rev 5, 08/2004

SEMICONDUCTOR TECHNICAL DATA

MPC962305

MPC962309

Low-Cost 3.3 V Zero Delay Buffer

The MPC962309 is a zero delay buffer designed to distribute high-speed

clocks. Available in a 16-pin SOIC or TSSOP package, the device accepts one

reference input and drives nine low-skew clocks. The MPC962305 is the 8-pin

version of the MPC962309 which drives five outputs with one reference input.

The -1H versions of these devices have higher drive than the -1 devices and

can operate up to 100/-133 MHz frequencies. These parts have on-chip PLLs

which lock to an input clock presented on the REF pin. The PLL feedback is

on-chip and is obtained from the CLOCKOUT pad.

D SUFFIX

8-LEAD SOIC PACKAGE

CASE 751-06

Features

•

1:5 LVCMOS zero-delay buffer (MPC962305)

1:9 LVCMOS zero-delay buffer (MPC962309)

Zero input-output propagation delay

Multiple low-skew outputs

DT SUFFIX

8-LEAD TSSOP PACKAGE

CASE 948J-01

250 ps max output-output skew

700 ps max device-device skew

Supports a clock I/O frequency range of 10 MHz to 133 MHz,

compatible with CPU and PCI bus frequencies

D SUFFIX

16-LEAD SOIC PACKAGE

CASE 751B-05

•

Low jitter, 200 ps max cycle-cycle, and compatible with Pentium^®based

systems

•

Test Mode to bypass PLL (MPC962309 only. See “Select Input Decoding”)

8-pin SOIC or 8-pin TSSOP package (MPC962305);16-pin SOIC or 16-pin

TSSOP package (MPC962309)

•

Single 3.3 V supply

Ambient temperature range: –40°C to +85°C

Compatible with the CY2305, CY23S05, CY2309, CY23S09

Spread spectrum compatible

DT SUFFIX

16-LEAD TSSOP PACKAGE

CASE 948F-01

Functional Description

The MPC962309 has two banks of four outputs each, which can be con-

trolled by the Select Inputs as shown in Table 3.Select Input Decoding for

MPC962309. Bank B can be tri-stated if all of the outputs are not required. Select inputs also allow the input clock to be directly applied

to the outputs for chip and system testing purposes.

The MPC962305 and MPC962309 PLLs enters a power down state when there are no rising edges on the REF input. During this

state, all of the outputs are in tristate, the PLL is turned off, and there is less than 25.0 µA of current draw for the device. The PLL

shuts down in one additional case as shown in Table 3.Select Input Decoding for MPC962309.

Multiple MPC962305 and MPC962309 devices can accept the same input clock and distribute it throughout the system. In this

situation, the difference between the output skews of two devices will be less than 700 ps.

All outputs have less than 200 ps of cycle-cycle jitter. The input-to-output propagation delay on both devices is guaranteed to be

less than 350 ps and the output-to-output skew is guaranteed to be less than 250 ps.

The MPC962305 and MPC962309 are available in two/three different configurations, as shown on the ordering information page.

The MPC962305-1/MPC962309-1 are the base parts. High drive versions of those devices, MPC962305-1H and MPC962309-1H,

are available to provide faster rise and fall times of the base device.

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MPC962305 MPC962309

Block Diagram

Pin Configuration

SOIC/TSSOP

Top View

CLKOUT

PLL

REF

CLKOUT

MUX

CLKA1

CLKA2

V_DD

GND

CLKB1

CLKB2

CLKA4

CLKA3

V_DD

CLKA1

CLKA2

CLKA3

CLKA4

REF

GND

CLKB4

CLKB3

CLKB1

CLKB2

CLKB3

CLKB4

SOIC/TSSOP

Top View

Select Input

Decoding

REF

CLKOUT

CLK2

CLK1

GND

CLK4

V_DD

CLK3

Table 1. Pin Description for MPC962309

Signal

Description

REF¹

Input reference frequency, 5 V-tolerant input

Buffered clock output, Bank A

3.3 V supply

CLKA1²

CLKA2²

V_DD

GND

Ground

CLKB1²

CLKB2²

S2³

Buffered clock output, Bank B

Select input, bit 2

S1³

Select input, bit 1

CLKB3²

Buffered clock output, Bank B

CLKB4²

GND

Ground

V_DD

3.3 V supply

CLKA3²

CLKA4²

CLKOUT²

Buffered clock output, Bank A

Buffered output, internal feedback on this pin

Table 2. Pin Description for MPC962305

Signal

Description

REF¹

Input reference frequency, 5 V-tolerant input

Buffered clock output

CLK2²

CLK1²

GND

Buffered clock output

Ground

CLK3²

V_DD

Buffered clock output

3.3 V supply

CLK4²

Buffered clock output

CLKOUT²

Buffered clock output, internal feedback on this pin³

1. Weak pull-down.

2. Weak pull-down on all outputs.

3. Weak pull-ups on these inputs.

TIMING SOLUTIONS

MOTOROLA

For More Informat²ion On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MPC962305 MPC962309

Table 3. Select Input Decoding for MPC962309

CLKOUT¹

Driven

CLOCK A1–A4

Three-State

Driven

CLOCK B1–B4

Three-State

Driven

Output Source

PLL

PLL Shutdown

Driven

PLL

Driven

Reference

PLL

Driven

1. This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference

and output.

Table 4. Maximum Ratings

Characteristics

Value

Unit

Supply Voltage to Ground Potential

DC Input Voltage (Except Ref)

−0.5 to +3.9

−0.5 to V_DD+0.5

DC Input Voltage REF

Storage Temperature

Junction Temperature

−0.5 to 5.5

−65 to +150

150

°C

Static Discharge Voltage (per MIL-STD-883, Method 3015)

>2000

Table 5. Operating Conditions for MPC962305-X and MPC962309-X Industrial Temperature Devices

Parameter

Description

Min

Max

Unit

V_DD

Supply Voltage

3.0

3.6

T_A

C_L

Operating Temperature (Ambient Temperature)

Load Capacitance, below 100 MHz

Load Capacitance, from 100 MHz to 133 MHz

Input Capacitance

−40

°C

C_L

C_IN

Table 6. Electrical Characteristics for MPC962305-X and MPC962309-X Industrial Temperature Devices¹

Parameter

Description

Input LOW Voltage²

Test Conditions

Min

Max

Unit

V_IL

0.8

Input HIGH Voltage²

Input LOW Current

V_IH

I_IL

2.0

µA

V_IN= 0 V

V_IN= V_DD

50.0

100.0

0.4

I_IH

Input HIGH Current

Output LOW Voltage³

V_OL

I_OL= 8 mA (−1)

I_OH= 12 mA (−1H)

Output HIGH Voltage³

V_OH

I_OH= −8 mA (−1)

2.4

I_OL= −12 mA (−1H)

_DD(PD mode)

I_DD

Power Down Supply Current

Supply Current

REF = 0 MHz

25.0

35.0

µA

Unloaded outputs at 66.67 MHz,

SEL inputs at V_DD

1. All parameters are specified with loaded outputs.

2. REF input has a threshold voltage of V_PP/2.

3. Parameter is guaranteed by design and characterization. Not 100% tested in production.

MOTOROLA

TIMING SOLUTIONS

For More Informat³ion On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MPC962305 MPC962309

Table 7. Switching Characteristics for MPC962305-1 and MPC962309-1 Industrial Temperature Devices¹

Parameter

Name

Test Conditions

Min

Typ

Max

Unit

t₁

Output Frequency

30-pF load

10-pF load

100

133.33

MHz

Duty Cycle²= t₂÷ t₁

Measured at 1.4 V, F_OUT= 66.67 MHz

40.0

50.0

60.0

Rise Time²

Measured between 0.8 V and 2.0 V

All outputs equally loaded

t₃

t₄

2.50

250

Fall Time²

Output to Output Skew²

t₅

t_6A

Delay, REF Rising Edge to

CLKOUT Rising Edge²

±350

Measured at V_DD/2

t_6B

Delay, REF Rising Edge to

CLKOUT Rising Edge²

Measured at V_DD/2. Measured in PLL Bypass Mode,

MPC962309 device only

8.7

Device to Device Skew²

Measured at V_DD/2 on the CLKOUT pins of devices

t₇

700

Cycle to Cycle Jitter²

PLL Lock Time²

Measured at 66.67 MHz, loaded outputs

t_J

200

1.0

t_LOCK

Stable power supply, valid clock presented on REF pin

1. All parameters are specified with loaded outputs.

2. Parameter is guaranteed by design and characterization. Not 100% tested in production.

Table 8. Switching Characteristics for MPC962305-1H and MPC962309-1H Industrial Temperature Devices¹

Parameter

Name

Test Conditions

Min

Typ

Max

Unit

t₁

Output Frequency

30-pF load

10-pF load

100

133.33

MHz

Duty Cycle²= t2 ÷ t1

Measured at 1.4 V, F_OUT= 66.67 MHz

Measured at 1.4 V, F_OUT< 50 MHz

40.0

45.0

50.0

55.0

60.0

55.0

Rise Time²

Measured between 0.8 V and 2.0 V

All outputs equally loaded

t₃

t₄

1.50

250

Fall Time²

Output to Output Skew²

t₅

t_6A

Delay, REF Rising Edge to

CLKOUT Rising Edge²

±350

Measured at V_DD/2

t_6B

Delay, REF Rising Edge to Measured at V_DD/2. Measured in PLL Bypass Mode,

CLKOUT Rising Edge²

8.7

MPC962309 device only

Device to Device Skew²

Measured at V_DD/2 on the CLKOUT pins of devices

t₇

700

Output Slew Rate²

Cycle to Cycle Jitter²

PLL Lock Time²

Measured between 0.8 V and 2.0 V using Test Circuit #2

Measured at 66.67 MHz, loaded outputs

t₈

t_J

V/ns

200

1.0

t_LOCK

Stable power supply, valid clock presented on REF pin

1. All parameters are specified with loaded outputs.

2. Parameter is guaranteed by design and characterization. Not 100% tested in production.

TIMING SOLUTIONS

MOTOROLA

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Freescale Semiconductor, Inc.

MPC962305 MPC962309

APPLICATIONS INFORMATION

V_CC

1.4 V

CCLK

GND

V_CC÷ 2

GND

V_CC

1.4 V

V_CC÷ 2

FB_IN

GND

t₅

t₆

The pin-to-pin skew is defined as the worst case difference in propagation

delay between any similar delay path within a single device

Figure 1. Output-to-Output Skew t_SK(O)

Figure 2. Static Phase Offset Test Reference

V_CC

1.4 V

DEVICE 1

DEVICE 2

V_CC÷ 2

GND

t₂

V_CC

V_CC÷ 2

t₁

DC = t₂/t₁x 100%

GND

t₇

The time from the PLL controlled edge to the non-controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

Figure 4. Device-to-Device Skew

Figure 3. Output Duty Cycle (DC)

V_CC= 3.3 V

2.0

0.8

t_J= |t_N–t_N+1

t_N

t_N+1

t₄

t₃

The variation in cycle time of a signal between adjacent cycles,

over a random sample of adjacent cycle pairs

Figure 5. Cycle-to-Cycle Jitter

Figure 6. Output Transition Time Test Reference

MOTOROLA

TIMING SOLUTIONS

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Freescale Semiconductor, Inc.

MPC962305 MPC962309

Test Circuit #1

Test Circuit #2

V_DD

1 K Ω

0.1 µF

CLK_OUT

OUTPUTS

GND

OUTPUTS

CLK_OUT

C_LOAD

1 K Ω

10 pF

V_DD

GND

V_DD

GND

0.1 µF

Test Circuit for all parameters except t₈

Test Circuit for t₈, Output slew rate on –1H, –5 device

Table 9. Ordering Information

Ordering Code

Package Type

MPC962305D-1

8-pin 150-mil SOIC

MPC962305D-1R2

MPC962305D-1H

MPC962305D-1HR2

MPC962305DT-1H

MPC962305DT-1HR2

MPC962309D-1

8-pin 150-mil SOIC-Tape and Reel

8-pin 150-mil SOIC

8-pin 150-mil SOIC-Tape and Reel

8-pin 150-mil TSSOP

8-pin 150-mil TSSOP-Tape and Reel

16-pin 150-mil SOIC

MPC962309D-1R2

MPC962309D-1H

MPC962309D-1HR2

MPC962309DT-1H

MPC962309DT-1HR2

16-pin 150-mil SOIC-Tape and Reel

16-pin 150-mil SOIC

16-pin 150-mil SOIC-Tape and Reel

16-pin 4.4-mm TSSOP

16-pin 4.4-mm TSSOP-Tape and Reel

TIMING SOLUTIONS

MOTOROLA

For More Informat⁶ion On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MPC962305 MPC962309

PACKAGE DIMENSIONS

D SUFFIX

8-LEAD SOIC PACKAGE

CASE 751-06

ISSUE T

NOTES:

1. DIMENSIONING AND TOLERANCING PER ASME

Y14.5M, 1994.

2. DIMENSIONS ARE IN MILLIMETER.

3. DIMENSION D AND E DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS

OF THE B DIMENSION AT MAXIMUM MATERIAL

CONDITION.

0.25

X 45˚

MILLIMETERS

DIM

MIN

1.35

0.10

0.35

0.19

4.80

3.80

MAX

1.75

0.25

0.49

0.25

5.00

4.00

SEATING

PLANE

1.27 BSC

0.10

5.80

0.25

0.40

0˚

6.20

0.50

1.25

7˚

0.25

D SUFFIX

STYLE 1:

PIN 1. EMITTER

STYLE 2:

STYLE 4:

PIN 1. ANODE

2. ANODE

16-L^SE^TA^YLD^{E 3}S^:OIC PACKAGE

PIN 1. COLLECTOR, DIE, #1

2. COLLECTOR, #1

3. COLLECTOR, #2

4. COLLECTOR, #2

5. BASE, #2

PIN 1. DRAIN, DIE #1

CASE 751B-05

2. COLLECTOR

3. COLLECTOR

4. EMITTER

5. EMITTER

6. BASE

2. DRAIN, #1

3. DRAIN, #2

3. ANODE

4. ANODE

5. ANODE

6. ANODE

7. ANODE

8. COMMON CATHODE

ISSUE K

4. DRAIN, #2

5. GATE, #2

6. SOURCE, #2

7. GATE, #1

6. EMITTER, #2

7. BASE, #1

8. EMITTER, #1

0.25

7. BASE

8. EMITTER

1.75

1.35

8. SOURCE, #1

6.2

0.25

^8X5.8

PIN'S

NUMBER

0.10

0.49

0.35

16X

STYLE 8:

T A B _{COLLECTOR, DIE #1}

PIN 1.

2. BASE, #1

STYLE 5:

STYLE 6:

STYLE 7:

PIN 1. INPUT

0.25

PIN 1. DRAIN

2. DRAIN

3. DRAIN

PIN 1. SOURCE

2. DRAIN

3. DRAIN

4. SOURCE

5. SOURCE

6. GATE

2. EXTERNAL BYPASS

3. THIRD STAGE SOURCE

4. GROUND

3. BASE, #2

14X

4. DRAIN

5. GATE

4. COLLECTOR, #2

5. COLLECTOR, #2

6. EMITTER, #2

7. EMITTER, #1

NOTES:

8. COLLECTOR, #1

1. DIMENSIONS ARE IN MILLIMETERS.

PIN 1 INDEX

5. DRAIN

6. GATE 3

1.27

6. GATE

7. SOURCE

8. SOURCE

7. GATE

8. SOURCE

7. SECOND STAGE Vd

8. FIRST STAGE Vd

10.0

9.8

2. DIMENSIONING AND TOLERANCING PER

ASME Y14.5M, 1994.

3. DATUMS A AND B TO BE DETERMINED AT THE

_STYLEA_10:

STYLE 9:

STYLE 11:

STYLE 12:

PLANE WHERE THE BOTTOM OF THE LEADS

PIN 1. EMITTER, COMMON

2. COLLECTOR, DIE #1

3. COLLECTOR, DIE #2

4. EMITTER, COMMON

5. EMITTER, COMMON

PIN 1. GROUND

2. BIAS 1

PIN 1. SOURCE 1

2. GATE 1

PIN 1. SOURCE

EXIT THE PLASTIC BODY.

2. SOURCE

4. THIS DIMENSION DOES NOT INCLUDE MOLD

3. OUTPUT

4. GROUND

5. GROUND

3. SOURCE 2

4. GATE 2

3. SOURCE

FLASH, PROTRUSION OR GATE BURRS. MOLD

4. GATE

FLASH, PROTRUSION OR GATE BURRS SHALL

5. DRAIN 2

6. DRAIN 2

7. DRAIN 1

5. DRAIN

NOT EXCEED 0.15MM PER SIDE.THIS

6. BASE

7. BASE, DIE #1

, DIE #2

6. BIAS 2

7. INPUT

8. GROUND

6. DRAIN

DIMENSION IS DETERMINED AT THE PLANE

SEATING

PLANE

7. DRAIN

WHERE THE BOTTOM OF THE LEADS EXIT

^{EMITTER, COMMON}4.0

8. DRAIN 1

8. DRAIN

THE PLASTIC BODY.

5. THIS DIMENSION DOES NOT INCLUDE

INTER-LEAD FLASH OR PROTRUSIONS.

INTER-LEAD FLASH AND PROTRUSIONS

16X

3.8

0.1 T

STYLE 13:

PIN 1. N.C.

STYLE 14:

PIN 1. N-SOURCE

STYLE 15:

STYLE 16:

SHALL NOT EXCEED 0.25MM PER SIDE.THIS

DIMENSION IS DETERMINED AT THE PLANE

PIN 1. ANODE 1

2. ANODE 1

3. ANODE 1

4. ANODE 1

PIN 1. EMITTER, DIE #1

2. BASE, DIE #1

2. SOURCE

3. SOURCE

4. GATE

2. N-GATE

3. P-SOURCE

4. P-GATE

5. P-DRAIN

6. P-DRAIN

7. N-DRAIN

8. N-DRAIN

WHERE THE BOTTOM OF THE LEADS EXIT

3. EMITTER, DIE #2

4. BASE, DIE #2

THE PLASTIC BODY.

6. THIS DIMENSION DOES NOT INCLUDE

5. DRAIN

5. CATHODE, COMMON

6. CATHODE, COMMON

7. CATHODE, COMMON

8. CATHODE, COMMON

0.25

5. COLLECTOR, DIE #2

6. COLLECTOR, DIE #2

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL NOT CAUSE

0.50

6. DRAIN

0.25^7.^X^D⁴^R⁵^A^˚^IN

8. DRAIN

7. COLLECTOR, DIE #1

8. COLLECTOR, DIE #1

THE LEAD WIDTH TO EXCEED 0.62MM.

0.19

STYLE 17:

STYLE 18:

PIN 1. ANODE

PIN 1. VCC

2. V2OUT

3. V1OUT

4. TXE

2. ANODE

3. SOURCE

4. GATE

1.25

0.40

7˚

0˚

5. RXE

6. VEE

7. GND

8. ACC

5. DRAIN

6. DRAIN

7. CATHODE

8. CATHODE

SECTION A-A

MOTOROLA

TIMING SOLUTIONS

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Go to: www.freescale.com

Freescale Semiconductor, Inc.

MPC962305 MPC962309

PACKAGE DIMENSIONS

DT SUFFIX

8-LEAD TSSOP PACKAGE

CASE 948J-01

ISSUE O

K 8x REF

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

0.10 (0.004)

T U

0.15 (0.006) T

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH. PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH

OR PROTRUSION SHALL NOT EXCEED 0.25

(0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.

2X L/2

J J1

-U-

PIN 1

IDENT.

SECTION N-N

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

0.25 (0.010)

0.15 (0.006) T

-V-

MILLIMETERS

INCHES

DIM MIN

MAX

3.10

4.50

1.20

0.15

0.75

MIN

MAX

0.122

0.177

0.047

0.006

0.030

2.90

4.30

---

0.114

0.169

---

0.05

0.50

0.002

0.020

DETAIL E

0.65 BSC

0.026 BSC

0.50

0.09

0.19

0.60

0.20

0.16

0.30

0.25

0.020

0.004

0.007

0.024

0.008

0.006

0.012

0.010

-W-

0.10 (0.004)

SEE DETAIL E

SEATING

PLANE

6.40 BSC

0˚ 8˚

0.252 BSC

0˚ 8˚

-T-

CASE 948J-01

ISSUE O

DATE 08/21/95

TIMING SOLUTIONS

MOTOROLA

For More Informat⁸ion On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MPC962305 MPC962309

PACKAGE DIMENSIONS

DT SUFFIX

16-LEAD TSSOP PACKAGE

CASE 948F-01

ISSUE O

16X REF

0.10 (0.004)

T U

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

0.15 (0.006) T U

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD

FLASH. PROTRUSIONS OR GATE BURRS.

MOLD FLASH OR GATE BURRS SHALL NOT

EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD

FLASH OR PROTRUSION. INTERLEAD FLASH

OR PROTRUSION SHALL NOT EXCEED

0.25 (0.010) PER SIDE.

5. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.

2X L/2

-U-

SECTION N-N

PIN 1

IDENT.

6. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE DETERMINED

AT DATUM PLANE -W-.

0.25 (0.010)

0.15 (0.006) T U

-V-

MILLIMETERS

INCHES

DIM

MIN

4.90

4.30

---

MAX

5.10

4.50

1.20

0.15

0.75

MIN

MAX

0.200

0.177

0.047

0.006

0.030

0.193

0.169

---

0.05

0.50

0.002

0.020

DETAIL E

0.65 BSC

0.026 BSC

0.18

0.09

0.19

0.28

0.20

0.16

0.30

0.25

0.007

0.004

0.007

0.011

0.008

0.006

0.012

0.010

-W-

0.10 (0.004)

6.40 BSC

0.252 BSC

8˚

DETAIL E

0˚

8˚

0˚

SEATING

PLANE

-T-

CASE 948F-01

ISSUE O

DATE 12/20/

MOTOROLA

TIMING SOLUTIONS

For More Informat⁹ion On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MPC962305 MPC962309

NOTES

TIMING SOLUTIONS

MOTOROLA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MPC962305 MPC962309

NOTES

MOTOROLA

TIMING SOLUTIONS

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied

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HOME PAGE: http://motorola.com/semiconductors

MPC962305

For More Information On This Product,

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MPC962305DT-1H [NXP]

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