MPC9774AER2_技术文档

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SEMICONDUCTOR TECHNICAL DATA

Order Number: MPC9774/D

Rev 2, 05/2003

Freescale Semiconductor, Inc.

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The MPC9774 is a 3.3V compatible, 1:14 PLL based clock generator

targeted for high performance low-skew clock distribution in mid-range to

high-performance networking, computing and telecom applications. With

output frequencies up to 125 MHz and output skews less than 175 ps the

device meets the needs of the most demanding clock applications.

2

3.3V 1:14 LVCMOS

Features

PLL CLOCK GENERATOR

• 1:14 PLL based low-voltage clock generator

• 3.3V power supply

• Internal power–on reset

• Generates clock signals up to 125 MHz

• Maximum output skew of 175 ps

• Two LVCMOS PLL reference clock inputs

• External PLL feedback supports zero-delay capability

• Various feedback and output dividers (see application section)

• Supports up to three individual generated output clock frequencies

• Drives up to 28 clock lines

• Ambient temperature range 0°C to +70°C

• Pin and function compatible to the MPC974

FA SUFFIX

52 LEAD LQFP PACKAGE

CASE 848D

Functional Description

The MPC9774 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the

MPC9774 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path. The

reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to match

the VCO frequency range.

The MPC9774 features frequency programmability between the three output banks outputs as well as the output to input

relationships. Output frequency ratios of 1:1, 2:1, 3:1, 3:2 and 3:2:1 can be realized. Additionally, the device supports a separate

configurable feedback output which allows for a wide variety of of input/output frequency multiplication alternatives. The

VCO_SEL pin provides an extended PLL input reference frequency range.

The REF_SEL pin selects the internal crystal oscillator or the LVCMOS compatible inputs as the reference clock signal. Two

alternative LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL

bypass configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output

dividers bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL

characteristics do not apply.

The MPC9774 has an internal power–on reset.

The MPC9774 is fully 3.3V compatible and requires no external loop filter components. All inputs (except XTAL) accept

LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 Ω transmission

lines. For series terminated transmission lines, each of the MPC9774 outputs can drive one or two traces giving the devices an

effective fanout of 1:12. The device is pin and function compatible to the MPC974 and is packaged in a 52-lead LQFP package.

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

245

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Freescale Semiconductor, Inc.

MPC9774

All input resistors have a value of 25kΩ

Bank A

QA0

QA1

QA2

QA3

QA4

V

CC

÷2

÷4

0

1

0

1

CCLK0

CLK

STOP

0

1

÷2, ÷4

Ref

VCO

CCLK1

CCLK_SEL

PLL

÷4, ÷6

÷4, ÷6, ÷8, ÷12

200-500 MHz

Bank B

QB0

QB1

QB2

QB3

QB4

2

V

CC

CLK

STOP

FB_IN

FB

PLL_EN

VCO_SEL

FSEL_A

FSEL_B

FSEL_C

FSEL_FB[1:0]

2

Bank C

QC0

QC1

QC2

QC3

CLK

STOP

V

CC

CLK_STOP

MR/OE

V

CC

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QFB

Figure 1. MPC9774 Logic Diagram

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MPC9774

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Figure 2. MPC9774 52–Lead Package Pinout (Top View)

246

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

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MPC9774

Table 1. PIN CONFIGURATION

CCLK0

I/O

Input

Type

Function

PLL reference clock

LVCMOS

CCLK1

Alternative PLL reference clock

FB_IN

PLL feedback signal input, connect to QFB

LVCMOS clock reference select

CCLK_SEL

VCO_SEL

PLL_EN

MR/OE

VCO operating frequency select

PLL enable/PLL bypass mode select

Output enable/disable (high-impedance tristate) and device reset

Output enable/clock stop (logic low state)

Frequency divider select for bank A outputs

Frequency divider select for bank B outputs

Frequency divider select for bank C outputs

Frequency divider select for the QFB output

Clock outputs (Bank A)

2

CLK_STOP

FSEL_A

FSEL_B

FSEL_C

FSEL_FB[1:0]

QA[4:0]

Output LVCMOS

Supply Ground

QB[4:0]

Clock outputs (Bank B)

QC[3:0]

QFB

Clock outputs (Bank C)

PLL feedback output. Connect to FB_IN.

Negative power supply

GND

VCC_PLL

Supply

V

CC

PLL positive power supply (analog power supply). It is recommended to use an external RC filter

for the analog power supply pin V Please see applications section for details.

CC_PLL.

V

CC

Supply

V

CC

Positive power supply for I/O and core. All V pins must be connected to the positive power

CC

supply for correct operation

Table 2. Function Table (MPC9774 configuration controls)

Control

CCLK_SEL

VCO_SEL

Default

0

1

0

Selects CCLK0 as PLL refererence signal input

Selects CCKL1 as PLL reference signal input

Selects VCO ÷ 2. The VCO frequency is scaled by a

Selects VCO ÷ 4. The VCO frequency is scaled by a

factor of 2 (high input frequency range)

factor of 4 (low input frequency range).

PLL_EN

1

Test mode with the PLL bypassed. The reference clock is Normal operation mode with PLL enabled.

substituted for the internal VCO output. MPC9774 is fully

static and no minimum frequency limit applies. All PLL

related AC characteristics are not applicable.

CLK_STOP

MR/OE

1

QA, QB an QC outputs disabled in logic low state. QFB

is not affected by CLK_STOP. CLK_STOP deassertion

may cause the initial output clock pulse to be distorted.

Outputs enabled (active)

Outputs disabled (high-impedance state) and reset of the Outputs enabled (active)

device. During reset/output disable the PLL feedback

loop is open and the internal VCO is tied to its lowest

frequency. The MPC9774 requires reset after any loss of

PLL lock. Loss of PLL lock may occur when the external

feedback path is interrupted. The length of the reset

pulse should be greater than one reference clock cycle

(CCLKx). The device is reset by the internal power–on

reset (POR) circuitry during power–up.

VCO_SEL, FSEL_A, FSEL_B, FSEL_C and FSEL_FB[1:0] control the operating PLL frequency range and input/output frequency ratios.

See Table 3 and Table 4 for the device frequency configuration.

Table 3. Function Table (Output Dividers Bank A, B, and C)

VCO_SEL

FSEL_A

QA[4:0]

VCO ÷ 4

VCO ÷ 8

VCO ÷ 16

VCO_SEL

FSEL_B

QB[4:0]

VCO ÷ 4

VCO ÷ 8

VCO ÷ 16

VCO_SEL

FSEL_C

QC[3:0]

VCO ÷ 8

VCO ÷ 12

VCO ÷ 16

VCO ÷ 24

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

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MPC9774

Table 4. Function Table (QFB)

VCO_SEL

FSEL_B1

FSEL_B0

QFB

0

1

0

1

0

1

0

1

0

1

0

1

0

1

VCO ÷ 8

VCO ÷ 16

VCO ÷ 12

VCO ÷ 24

VCO ÷ 16

VCO ÷ 32

VCO ÷ 24

VCO ÷ 48

2

Table 5. General Specifications

Symbol

Characteristics

Min

Typ

÷ 2

Max

Unit

V

Condition

V

TT

Output Termination Voltage

V

CC

MM

HBM

LU

ESD protection (Machine Model)

200

2000

200

V

ESD protection (Human Body Model)

Latch-Up Immunity

V

mA

pF

C

Power Dissipation Capacitance

Input Capacitance

12

4.0

Per output

Inputs

PD

C

IN

Table 6. Absolute Maximum Ratings^a

Symbol

Characteristics

Min

-0.3

Max

3.9

Unit

V

Condition5

V

CC

Supply Voltage

V

IN

DC Input Voltage

V

+ 0.3

V

CC

V

OUT

DC Output Voltage

DC Input Current

+ 0.3

20

V

I

IN

mA

°C

I

DC Output Current

Storage Temperature

50

OUT

T

S

-65

125

a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these con-

ditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated condi-

tions is not implied.

Table 7. DC Characteristics (V_CC= 3.3V 5%, T_A= 0°C to +70°C)

Symbol

Characteristics

PLL Supply Voltage

Min

3.02

2.0

Typ

Max

Unit

V

Condition

LVCMOS

V

CC

CC_PLL

V

IH

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

V

+ 0.3

V

LVCMOS

CC

V

IL

0.8

V

a

V

OH

2.4

V

I

= -24 mA

OH

V

OL

0.55

0.30

V

I

OL

I

OL

= 24 mA

= 12 mA

Z

Output Impedance

14 - 17

5.0

Ω

OUT

b

I

IN

Input Current

200

7.5

8.0

µA

mA

V

= V or GND

CC

IN

I

Maximum PLL Supply Current

CC_PLL

I

Maximum Quiescent Supply Current

All V Pins

CC

CCQ

a. The MPC9774 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmis-

sion line to a termination voltage of V . Alternatively, the device drives up to two 50Ω series terminated transmission lines.

TT

b. Inputs have pull-down or pull-up resistors affecting the input current.

248

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

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MPC9774

Table 8. AC Characteristics (V_CC= 3.3V 5%, T_A= 0°C to +70°C)^a

Symbol

Characteristics

Input Reference Frequency

Min

Typ

Max

Unit

Condition

f

÷8 feedback

÷12 feedback

÷16 feedback

÷24 feedback

÷32 feedback

÷48 feedback

25.0

16.6

12.5

8.33

6.25

4.16

62.5

41.6

31.25

20.83

15.625

10.41

MHz

PLL locked

REF

b

Input Reference Frequency in PLL Bypass Mode

250

500

MHz

PLL bypass

PLL locked

c

2

f

VCO Frequency Range

200

VCO

Output Frequency

÷4 output

÷8 output

÷12 output

÷16 output

÷24 output

50.0

25.0

16.6

12.5

8.33

125.0

62.5

41.6

31.25

20.83

MHz

MAX

d

t

Input Reference Pulse Width

CCLKx Input Rise/Fall Time

2.0

ns

PW,MIN

t , t

R

1.0

0.8 to 2.0V

PLL locked

F

e

t

∅

(

Propagation Delay (static phase offset)

)

CCLKx to FB_IN (FB=÷8 and f

=50 MHz)

REF

-250

+100

ps

f

t

Output-to-output Skew

within QA bank

within QB bank

within QC bank

any output

100

125

100

175

ps

SK(O)

DC

t , t

Output Duty Cycle

Output Rise/Fall Time

Output Disable Time

Output Enable Time

47

50

53

1.0

10

90

%

ns

ps

0.1

0.55 to 2.4V

R

F

t

PLZ, HZ

PZL

g

Cycle-to-cycle Jitter

JIT(CC)

JIT(PER)

f

Period Jitter

h

I/O Phase Jitter RMS (1 σ)

FB=÷8

FB=÷12

FB=÷16

FB=÷24

FB=÷32

FB=÷48

15

49

18

22

26

34

ps

∅

JIT(

)

i

BW

PLL Closed Loop Bandwidth

FB=÷8

FB=÷12

FB=÷16

FB=÷24

FB=÷32

FB=÷48

0.50 - 1.80

0.30 - 1.00

0.25 - 0.70

0.17 - 0.40

0.12 - 0.30

0.07 - 0.20

MHz

MHZ

MHz

t

Maximum PLL Lock Time

10

ms

LOCK

a

b

c

d

AC characteristics apply for parallel output termination of 50Ω to V .

TT

In bypass mode, the MPC9774 divides the input reference clock.

The input reference frequency must match the VCO lock range divided by the total feedback divider ratio (FB): f

=f

E.g. at f

÷(M ⋅ VCO_SEL).

REF VCO

Calculation of reference duty cycle limits: DC

= t

⋅ f

⋅ 100% and DC

= 100% - DC

=62.5 MHz

REF

REF,MIN

PW,MIN REF

REF,MAX

REF, MIN.

the input duty cycle range is 12.5% < DC < 87.5%.

Static phase offset depends on the reference frequency: t = +50 ps (1÷(120 ꢀ f )) for any reference frequency.

REF

See application section for part-to-part skew calculation.

Valid for all outputs at the same fequency.

e

f

g

h

∅

(

)

I/O jitter for f =400 MHz. See application section for I/O jitter at other frequencies and for a jitter calculation for confidence factors other

VCO

than 1 s.

i

-3 dB point of PLL transfer characteristics.

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

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MPC9774

APPLICATIONS INFORMATION

MPC9774 Configurations

specified frequency range. This divider is controlled by the

VCO_SEL pin. VCO_SEL effectively extends the usable input

frequency range while it has no effect on the output to refer-

ence frequency ratio. The output frequency for each bank can

be derived from the VCO frequency and the output divider:

Configuring the MPC9774 amounts to properly configuring

the internal dividers to produce the desired output frequencies.

The output frequency can be represented by this formula:

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f

_QA[4:0]= f_VCO÷ (VCO_SEL ⋅ N_A)

f_QB[4:0]= f_VCO÷ (VCO_SEL ⋅ N_B)

_QC[3:0]= f_VCO÷ (VCO_SEL ⋅ N_C)

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f

2

Table 9. MPC9774 Divider

Divider

Function

VCO_SEL

Values

÷ꢔ

M

PLL feedback

FSEL_FB[0:1]

÷2

÷4

÷2

÷4

÷2

÷4

÷2

÷4

8, 12, 16, 24

16, 24, 32, 48

4, 8

where f_REFis the reference frequency of the selected input

clock source (CCLKO or CCLK1), M is the PLL feedback divid-

er and N is a output divider. M is configured by the

FSEL_FB[0:1] and N is individually configured for each output

bank by the FSEL_A, FSEL_B and FSEL_C inputs.

N

Bank A Output

Divider FSEL_A

A

8, 16

N

Bank B Output

Divider FSEL_B

4, 8

B

The reference frequency f_REFand the selection of the feed-

back-divider M is limited by the specified VCO frequency

range. f_REFand M must be configured to match the VCO fre-

quency range of 200 to 500 MHz in order to achieve stable PLL

operation:

8, 16

N

Bank C Output

Divider FSEL_C

8, 12

C

16, 24

Table 9 shows the various PLL feedback and output divid-

ers. The output dividers for the three output banks allow the

user to configure the outputs into 1:1, 2:1, 3:2 and 3:2:1 fre-

f_VCO,MINꢁ (f_REF⋅ VCO_SEL ⋅ M) ꢁ f_VCO,MAX

The PLL post-divider VCO_SEL is either a divide-by-two or quency ratios. Figure 3 and Figure 4 display example configu-

a divide-by-four and can be used to situate the VCO into the rations for the MPC9774:

Figure 3. Example Configuration

Figure 4. Example Configuration

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ꢄꢄꢏ ꢗ ꢂ

ꢄꢄꢏ ꢗ ꢊ

ꢄꢄꢏ ꢗ ꢌ ꢍꢎ ꢏ

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ꢀ ꢑꢁ

ꢊꢉ ꢚ ꢔꢧ ꢨ

ꢛꢉ ꢦ ꢚ ꢔꢧ ꢨ

ꢊ ꢂ ꢂ ꢔꢧ ꢨ

ꢚ ꢂ ꢔꢧ ꢨ

ꢂ

ꢀ ꢁꢰ ꢒꢱ ꢂꢲ

ꢀ ꢄꢰ ꢈꢱ ꢂꢲ

ꢀ ꢑꢁ

ꢃ ꢄꢋ ꢌꢍ ꢎꢏ

ꢑꢁ ꢌꢓ ꢅ

ꢃ ꢄꢋ ꢌ ꢍꢎ ꢏ

ꢑꢁ ꢌ ꢓꢅ

ꢂ

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ꢂ

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ꢑꢍ ꢎꢏ ꢌꢐ

ꢑꢍ ꢎꢏ ꢌꢁ

ꢑꢍ ꢎꢏ ꢌꢄ

ꢑꢍ ꢎꢏ ꢌꢑꢁ ꢰ ꢊꢱꢂ ꢲ

ꢑꢍ ꢎ ꢏꢌ ꢐ

ꢑꢍ ꢎ ꢏꢌ ꢁ

ꢑꢍ ꢎ ꢏꢌ ꢄ

ꢑꢍ ꢎ ꢏꢌ ꢑꢁ ꢰ ꢊꢱ ꢂ ꢲ

ꢛꢉꢦ ꢚ ꢔꢧ ꢨ

ꢈ ꢈ ꢦꢈ ꢔꢧ ꢨ

ꢊ

ꢂ

ꢊ

MPC9774

ꢉ

ꢂ

ꢦ

ꢝ

ꢈ

ꢔ

ꢧ

ꢨ

ꢩ

ꢑ

ꢥ

ꢪ

ꢫ

ꢬ

ꢭ

ꢮ

ꢯ

ꢉ

ꢚ

ꢔ

ꢧ

ꢨ

ꢩ

ꢑ

ꢥ

ꢪ

ꢫ

ꢬ

ꢭ

ꢮ

ꢯ

MPC9774 example configuration (feedback of

QFB = 20.83 MHz, VCO_SEL = ÷2, M = 12, N_A=

2, N_B= 4, N_C= 4, f_VCO= 500 MHz).

MPC9774 example configuration (feedback of

QFB = 25 MHz, VCO_SEL = ÷2, M = 8, N_A= 2,

N_B= 4, N_C= 6, f_VCO= 400 MHz).

Frequency range

Input

Min

Max

Frequency range

Input

Min

Max

8.33 MHz

50 MHz

25 MHz

20.83 MHz

125 MHz

62.5 MHz

20 MHz

50 MHz

100 MHz

48 MHz

120 MHz

200 MHz

QA outputs

QB outputs

QC outputs

QA outputs

QB outputs

QC outputs

250

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MPC9774

Using the MPC9774 in zero-delay applications

Table 10. Confidence factor CF

Nested clock trees are typical applications for the

MPC9774. Designs using the MPC9774 as LVCMOS PLL fan-

out buffer with zero insertion delay will show significantly lower

clock skew than clock distributions developed from CMOS fan-

out buffers. The external feedback of the MPC9774 clock driv-

er allows for its use as a zero delay buffer. The PLL aligns the

feedback clock output edge with the clock input reference

edge resulting a near zero delay through the device (the propa-

gation delay through the device is virtually eliminated). The

maximum insertion delay of the device in zero-delay applica-

tions is measured between the reference clock input and any

output. This effective delay consists of the static phase offset,

I/O jitter (phase or long-term jitter), feedback path delay and

the output-to-output skew error relative to the feedback output.

CF

1s

Probability of clock edge within the distribution

0.68268948

0.95449988

0.99730007

0.99993663

0.99999943

0.99999999

2s

3s

4s

5s

6s

2

The feedback trace delay is determined by the board layout

and can be used to fine-tune the effective delay through each

device.

Due to the frequency dependence of the static phase offset

and I/O jitter, using Figure 6 and Figure 7 to predict a maximum

I/O jitter and the specified t₍_∅parameter relative to the input

)

reference frequency results in a precise timing performance

analysis.

Calculation of part-to-part skew

The MPC9774 zero delay buffer supports applications

where critical clock signal timing can be maintained across

several devices. If the reference clock inputs of two or more

MPC9774 are connected together, the maximum overall timing

uncertainty from the common CCLK input to any output is:

In the following example calculation a I/O jitter confidence

factor of 99.7% ( 3σ) is assumed, resulting in a worst case

timing uncertainty from the common input reference clock to

any output of -470 ps to +320 ps relative to CCLK (PLL feed-

back = B8, reference frequency = 50 MHz, VCO frequency =

t_SK(PP)= t _∅+ t_SK(O)+ t_{PD, LINE(FB)}+ t_JIT(ꢂ CF

∅

)

(

)

400 MHz, I/O jitter = 15 ps rms max., static phase offset t₍_∅

–250 ps to +100 ps):

=

)

This maximum timing uncertainty consist of 4 components:

static phase offset, output skew, feedback board trace delay

and I/O (phase) jitter:

t_SK(PP)

=

[–250 ps...+100 ps] + [–175 ps...175 ps] +

[(15 ps ⋅ –3)...(15 ps ⋅ 3)] + t_{PD, LINE(FB)}

[–470 ps...+320 ps] + t_{PD, LINE(FB)}

ꢔꢬ ꢸꢦ ꢓ ꢖ ꢋ ꢙ ꣃꢬ ꢹꢥ ꢵꢿꢳ ꢳ ꢥꢤ ꢩꢕꢔ ꢍ ꢯ ꢾꢥ ꢤꢹꣂ ꢹ ꢑꢤꢥ ꣁ ꣂꢥ ꢽ ꢭꣀ

ꢙ ꢬꢤ ꢬꢼ ꢥꢳ ꢥ ꢤꢱ ꢙ ꢏꢏ ꢑꢥ ꢥꢪ ꢫ ꢬꢭ ꢮ ꢇꢿꢾꢿꢪ ꢥ ꢤ ꢑꢁ

ꢊ ꢂꢂ

ꢝ ꢂ

ꢄ ꢄ ꢏ ꢗ

ꢄ ꢻꢼ ꢼ ꢻꢽ

ꢳ

ꢙ ꢇ ꢴ ꢏ ꢓ ꢅ ꢎ ꢩ ꢑ ꢁ ꢯ

ꢶꢳ

∅

ꢩ

ꢯ

ꢑꢁ ꢣ ÷ꢈ ꢉ

ꢑꢁ ꢣ ÷ꢊ ꢛ

ꢛ ꢂ

ꢀ

ꢑ

ꢁ

ꢒ

ꢂ

ꢇ ꢥ ꢾ ꢿ ꢭ ꢥ ꢊ

ꢳ

∅

ꢵ ꢓ ꢘ ꢩ

ꢯ

ꢑ

ꢁ

ꢣ

÷

ꢝ

ꢉ ꢂ

ꢂ

ꢐ

ꢽ

ꣀ

ꢀ

t

ꢍ

ꢗ

ꢩ

ꢋ

ꢯ

ꢉ

ꢂ

ꢉ

ꢚ

ꢂ

ꢈ

ꢂ

ꢈ

ꢚ

ꢂ

ꢒ

ꢂ

ꢒ

ꢚ

ꢂ

ꢚ

ꢂ

ꢃ

ꢄ

ꢋ

ꢡ

ꢤ

ꢥ

ꣁ

ꣂ

ꢥ

ꢽ

ꢭ

ꣀ

ꢰ

ꢔ

ꢧ

ꢨ

ꢲ

ꢷ

ꢳ

∅

ꢩ

ꢯ

Figure 6. MPC9774 I/O Jitter

ꢀ

ꢑ

ꢁ

ꢇ

ꢥ

ꢾ

ꢿ

ꢭ

ꢥ

ꢉ

ꢳ

∅

ꢵ ꢓ ꢘ ꢩ

ꢯ

ꢔꢬ ꢸꢦ ꢓ ꢖ ꢋ ꢙ ꣃꢬ ꢹꢥ ꢵꢿꢳ ꢳ ꢥꢤ ꢩꢕꢔ ꢍ ꢯ ꢾꢥ ꢤꢹꣂ ꢹ ꢑꢤꢥ ꣁ ꣂꢥ ꢽ ꢭꣀ

ꢙ ꢬꢤ ꢬꢼ ꢥꢳ ꢥ ꢤꢱ ꢙ ꢏꢏ ꢑꢥ ꢥꢪ ꢫ ꢬꢭ ꢮ ꢇꢿꢾꢿꢪ ꢥ ꢤ ꢑꢁ

ꢐ

ꢽ

ꣀ

ꢀ

ꢇ

ꢥ

ꢾ

ꢿ

ꢭ

ꢥ

ꢉ

t

ꢊ ꢛꢂ

ꢊ ꢒꢂ

ꢊ ꢉꢂ

ꢊ ꢂꢂ

ꢝ ꢂ

ꢍ

ꢗ

ꢩ

ꢋ

ꢯ

ꢑ

ꢁ

ꢣ

÷

ꢊ

ꢉ

ꢔ

ꢬ

ꢸ

ꢦ

ꢹ

ꢮ

ꢥ

ꢺ

ꢳ

ꢍ

ꢗ

ꢩ

ꢙ

ꢯ

ꢑꢁ ꢣ ÷ꢒ ꢝ

ꢑꢁ ꢣ ÷ꢉ ꢒ

Figure 5. MPC9774 max. device-to-device skew

ꢛ

ꢂ

ꢒ

ꢂ

ꢉ

ꢂ

ꢉ

ꢂ

ꢉ

ꢚ

ꢂ

ꢈ ꢂꢂ

ꢈ ꢚꢂ

ꢒ ꢂꢂ

ꢒ ꢚꢂ

ꢚ ꢂ ꢂ

Due to the statistical nature of I/O jitter a rms value (1 σ) is

specified. I/O jitter numbers for other confidence factors (CF)

can be derived from Table 10.

ꢃ ꢄꢋ ꢡ ꢤꢥ ꣁꣂ ꢥ ꢽꢭꣀ ꢰ ꢔꢧꢨꢲ

Figure 7. MPC9774 I/O Jitter

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

251

For More Information On This Product,

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Freescale Semiconductor, Inc.

MPC9774

Driving Transmission Lines

looking into the driver. The parallel combination of the 36Ω se-

ries resistor plus the output impedance does not match the

parallel combination of the line impedances. The voltage wave

launched down the two lines will equal:

The MPC9774 clock driver was designed to drive high

speed signals in a terminated transmission line environment.

To provide the optimum flexibility to the user the output drivers

were designed to exhibit the lowest impedance possible. With

an output impedance of less than 20Ω the drivers can drive

either parallel or series terminated transmission lines. For

more information on transmission lines the reader is referred to

Motorola application note AN1091. In most high performance

clock networks point-to-point distribution of signals is the meth-

od of choice. In a point-to-point scheme either series termi-

nated or parallel terminated transmission lines can be used.

The parallel technique terminates the signal at the end of the

line with a 50Ω resistance to V_CC÷ 2.

V_L= V_S( Z₀÷ (R_S+ R₀+ Z₀))

Z₀= 50Ω || 50Ω

R_S= 36Ω || 36Ω

R₀= 14Ω

V_L= 3.0 ( 25 ÷ (18 + 17 + 25)

= 1.31V

2

At the load end the voltage will double, due to the near unity

reflection coefficient, to 2.6V. It will then increment towards the

quiescent 3.0V in steps separated by one round trip delay (in

this case 4.0ns).

This technique draws a fairly high level of DC current and

thus only a single terminated line can be driven by each output

of the MPC9774 clock driver. For the series terminated case

however there is no DC current draw, thus the outputs can

drive multiple series terminated lines. Figure 8 “Single versus

Dual Transmission Lines” illustrates an output driving a single

series terminated line versus two series terminated lines in

parallel. When taken to its extreme the fanout of the MPC9774

clock driver is effectively doubled due to its capability to drive

multiple lines.

ꢈ ꢦꢂ

ꢋ ꣂ ꢳꢐ

ꢳ ꢣ ꢈ ꢦ ꢝꢞ ꢚꢛ

ꢋ ꣂ ꢳꢁ

ꢳ ꢣ ꢈ ꢦ ꢞꢈ ꢝꢛ

ꢇ

ꢉ ꢦꢚ

ꢉ ꢦꢂ

ꢊ ꢦꢚ

ꢊ ꢦꢂ

ꢂ ꢦꢚ

ꢂ

ꢇ

ꢓ ꢽ

ꢔꢙꢄ ꢞꢜ ꢜ ꢒ

ꢋ ꢢꢘ ꢙꢢ ꢘ

ꢁꢢ ꢑ ꢑꢎꢕ

꣇

ꢣ ꢚꢂΩ

ꢋ

ꢕ ꢣ ꢈꢛ Ω

ꢍ

ꢊ ꢒΩ

ꢓ ꢅ

ꢋ ꣂ ꢳꢐ

ꢉ

ꢒ

ꢛ

ꢝ

ꢊ ꢂ

ꢊ ꢉ

ꢊ ꢒ

ꢘꢓ ꢔꢎ ꢩꢽ ꢍ ꢯ

ꢔꢙ ꢄꢞ ꢜ ꢜ ꢒ

ꢋꢢ ꢘꢙꢢ ꢘ

ꢁꢢ ꢑꢑ ꢎꢕ

Figure 9. Single versus Dual Waveforms

꣇

ꢣ ꢚꢂΩ

Since this step is well above the threshold region it will not

cause any false clock triggering, however designers may be

uncomfortable with unwanted reflections on the line. To better

match the impedances when driving multiple lines the situation

in Figure 10 “Optimized Dual Line Termination” should be

used. In this case the series terminating resistors are reduced

such that when the parallel combination is added to the output

buffer impedance the line impedance is perfectly matched.

ꢋ

ꢕ ꢣ ꢈꢛ Ω

ꢍ

ꢋ ꣂ ꢳꢁ ꢂ

ꢋ ꣂ ꢳꢁ ꢊ

ꢊ ꢒΩ

ꢓ

ꢅ

ꢕ ꢣ ꢈꢛ Ω

ꢍ

Figure 8. Single versus Dual Transmission Lines

ꢔꢙ ꢄꢞ ꢜ ꢜꢒ

ꢋ ꢢꢘꢙ ꢢꢘ

The waveform plots in Figure 9 “Single versus Dual Line

Termination Waveforms” show the simulation results of an out-

put driving a single line versus two lines. In both cases the

drive capability of the MPC9774 output buffer is more than suf-

ficient to drive 50Ω transmission lines on the incident edge.

Note from the delay measurements in the simulations a delta

of only 43ps exists between the two differently loaded outputs.

This suggests that the dual line driving need not be used exclu-

sively to maintain the tight output-to-output skew of the

MPC9774. The output waveform in Figure 9 “Single versus

Dual Line Termination Waveforms” shows a step in the wave-

form, this step is caused by the impedance mismatch seen

꣇

ꢣ ꢚ ꢂΩ

ꢋ

ꢕ ꢣ ꢉ ꢉΩ

ꢍ

ꢁ ꢢꢑꢑꢎ ꢕ

ꢊ

ꢒ

Ω

ꢕ ꢣ ꢉ ꢉΩ

ꢍ

14Ω + 22Ω ꢃ 22Ω = 50Ω ꢃ 50Ω

25Ω = 25Ω

Figure 10. Optimized Dual Line Termination

252

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MPC9774

Power Supply Filtering

filter shown in Figure 11, the filter cut-off frequency is around

3-5 kHz and the noise attenuation at 100 kHz is better than 42

dB.

The MPC9774 is a mixed analog/digital product. Its analog

circuitry is naturally susceptible to random noise, especially if

this noise is seen on the power supply pins. Random noise on

the VCC_PLL power supply impacts the device characteris-

tics, for instance I/O jitter. The MPC9774 provides separate

power supplies for the output buffers (VCC) and the phase-

locked loop (VCC_PLL) of the device.The purpose of this de-

sign technique is to isolate the high switching noise digital out-

puts from the relatively sensitive internal analog phase-locked

loop. In a digital system environment where it is more difficult

to minimize noise on the power supplies a second level of

isolation may be required. The simple but effective form of

isolation is a power supply filter on the VCC_PLL pin for the

MPC9774. Figure 11 illustrates a typical power supply filter

scheme. The MPC9774 frequency and phase stability is most

susceptible to noise with spectral content in the 100 kHz to 20

MHz range. Therefore the filter should be designed to target

this range. The key parameter that needs to be met in the final

filter design is the DC voltage drop across the series filter resis-

tor R_F. From the data sheet the ICC_PLL current (the current

sourced through the VCC_PLL pin) is typically 5 mA (7.5 mA

maximum), assuming that a minimum of 3.02 V (VCC_PLL,

min) must be maintained on the VCC_PLL pin. The resistor R_F

shown in Figure 11 must have a resistance of 5-15Ω to meet

the voltage drop criteria.

ꢕ ꢣ ꢚ ꢠꢊ ꢚ Ω

ꢑ

ꢄ ꢣ ꢉ ꢉ µꢑ

ꢑ

ꢕ

ꢑ

ꢃ ꢄꢄꢌ ꢙ ꢏꢏ

ꢃ ꢄꢄ

ꢄ

ꢑ

ꢊ ꢂ ꢽ ꢑ

ꢀꢁꢂꢃꢄꢄꢅ

2

ꢃ ꢄꢄ

ꢈ ꢈꢦ ꢦ ꢦ ꢊꢂ ꢂ ꢽ ꢑ

Figure 11. V_{CC_PLL}Power Supply Filter

As the noise frequency crosses the series resonant point of

an individual capacitor its overall impedance begins to look

inductive and thus increases with increasing frequency. The

parallel capacitor combination shown ensures that a low im-

pedance path to ground exists for frequencies well above the

bandwidth of the PLL. Although the MPC9774 has several de-

sign features to minimize the susceptibility to power supply

noise (isolated power and grounds and fully differential PLL)

there still may be applications in which overall performance is

The minimum values for RF and the filter capacitor C_Fare being degraded due to system power supply noise. The power

defined by the required filter characteristics: the RC filter supply filter schemes discussed in this section should be ade-

should provide an attenuation greater than 40 dB for noise quate to eliminate power supply noise related problems in

whose spectral content is above 100 kHz. In the example RC most designs.

ꢔꢙ ꢄꢞ ꢜ ꢜꢒ ꢇꢢ ꢘ

ꢙ ꣂ꣈ꢹꢥ

ꢆ ꢥꢽꢥ ꢤꢬꢳ ꢻ ꢤ

꣇ ꢣ ꢚꢂΩ

꣇ ꢣ ꢚ ꢂ Ω

꣇ ꢣ ꢚꢂ W

ꢕ ꢣ ꢚ ꢂ Ω

ꢘ

ꢕ ꢣ ꢚ ꢂΩ

ꢘ

ꢃ

ꢘ ꢘ

ꢃ

ꢘ ꢘ

Figure 12. CCLK MPC9774 AC test reference

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

253

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

MPC9774

ꢃ

ꢄ ꢄ

Bꢉ

ꢄ ꢄ

ꢃ

ꢄ ꢄ

ꢆ ꢅꢇ

ꢄꢄ ꢏꢗ ꢸ

ꢑꢁ ꢌ ꢓꢅ

Bꢉ

ꢄ ꢄ

ꢃ

ꢄ ꢄ

ꢆ ꢅꢇ

Bꢉ

ꢄ ꢄ

ꢃ

ꢄ

ꢆ

ꢅ

ꢇ

Bꢉ

ꢄ

ꢳ

ꢍ

ꢗ

ꢩ

ꢋ

ꢯ

ꢆ

ꢅ

ꢇ

ꢘ ꣃꢥ ꣆ ꢿꢽ ꢠꢳ ꢻꢠ ꣆ ꢿꢽ ꢹ ꢮꢥꢺ ꢿꢹ ꢪꢥ ꢡꢿꢽ ꢥꢪ ꢬꢹ ꢳ ꣃꢥ ꢺꢻ ꢤꢹꢳ ꢭꢬꢹ ꢥ ꢪꢿꢡꢡ ꢥꢤꢥ ꢽꢭꢥ ꢿꢽ

꣆ ꢤꢻ ꣆ ꢬ꣉ ꢬ ꢳꢿꢻ ꢽ ꢪ ꢥ꣈ ꢬꣀ ꢫꢥ ꢳꢺ ꢥꢥꢽ ꢬꢽ ꣀ ꢹꢿꢼ ꢿ꣈ꢬꢤ ꢪꢥ ꣈ꢬꣀ ꣆ꢬ ꢳꣃ ꢺ ꢿꢳꣃ ꢿꢽ ꢬ

ꢹꢿꢽ ꣉ ꣈ꢥ ꢪ ꢥꢾꢿ ꢭꢥ

ꢳ

∅

ꢩ

ꢯ

2

Figure 13. Output–to–output Skew t_SK(O)

Figure 14. Propagation delay (t₍_∅, static phase

)

offset) test reference

ꢃ

ꢄ

ꢏ

ꢗ

ꢸ

Bꢉ

ꢄ

ꢆ

ꢅ

ꢇ

ꢳ

ꢙ

ꢑ

ꢁ

ꢌ

ꢓ

ꢅ

ꢘ

ꢂ

ꢀ

ꢁ

ꢂ

ꢃ

ꢅ

ꢆ

ꢸ

ꢈ

ꢇ

ꢉ

ꢆ

ꢊ ꢋ ꢆ ꢌ

ꢂ ꣊ꢆ ꢎ ꢆ ꢏꢐ ꢑ ꢒ꣊

ꢇ ꢈ

ꢄ

ꢇ

∅

ꢍ

ꢘ ꣃꢥ ꢳꢿ ꢼꢥ ꢡꢤ ꢻ ꢼ ꢳꣃ ꢥ ꢙ ꢏꢏ ꢭꢻꢽ ꢳꢤ ꢻ꣈꣈ꢥ ꢪ ꢥꢪ ꣉ꢥ ꢳ ꢻ ꢳ ꣃꢥ ꢽꢻ ꢽ ꢭꢻꢽ ꢳꢤ ꢻ꣈꣈ꢥ ꢪ

ꢥ ꢪ꣉ ꢥ ꢴ ꢪ ꢿꢾꢿꢪ ꢥ ꢪ ꢫ ꣀ ꢳ ꣃꢥ ꢳ ꢿꢼ ꢥ ꢫꢥ ꢳꢺ ꢥꢥ ꢽ ꢙ ꢏꢏ ꢭꢻꢽ ꢳꢤ ꢻ꣈꣈ꢥ ꢪ ꢥꢪ ꣉ꢥꢹꢴ

ꢥ ꢸ꣆ ꢤꢥ ꢹꢹ ꢥꢪ ꢬ ꢹ ꢬ ꣆ꢥ ꢤꢭꢥꢽ ꢳꢬ ꣉ꢥ

ꢘꣃ ꢥ ꢪ ꢥꢾꢿꢬ ꢳ ꢿꢻ ꢽ ꢿꢽ ꢳ ꢡ ꢻꢤ ꢬ ꢭꢻ ꢽꢳ ꢤꢻ ꣈꣈ꢥ ꢪ ꢥ ꢪ꣉ ꢥ ꢺꢿꢳ ꣃ ꢤꢥ ꢹ꣆ ꢥꢭꢳ ꢳ ꢻ ꢬ ꢳ ꢼꢥ ꢬ ꢽ ꢿꢽ ꢬ

ꢤꢬ ꢽꢪ ꢻ ꢼ ꢹꢬ ꢼ꣆ ꣈ꢥ ꢻ ꢡ ꢭꣀꢭ꣈ꢥ ꢹ

ꢂ

Figure 15. Output Duty Cycle (DC)

Figure 16. I/O Jitter

ꢃ

ꢂ

꣊

ꢆ

ꢎ

ꢆ

꣊

ꢃ

ꢂ

꣊

ꢆ

ꢎ

ꢌ

ꢈ

÷

ꢗ

ꢯ

꣊

ꢊ

ꢋ

ꢆ

ꢌ

ꢁ

ꢍ

ꢓ

ꢔ

ꢈ

ꢊ

ꢋ

ꢆ

ꢌ

ꢄ

ꢕ

ꢖ

ꢍ

ꢓ

ꢇ

ꢘ

ꢅ ꢷ ꢊ

ꢘ

ꢅ

ꢂ

ꢘ ꣃꢥ ꢾꢬ ꢤ ꢿꢬꢳ ꢿꢻ ꢽ ꢿꢽ ꢭꣀꢭ ꣈ꢥ ꢳ ꢿꢼ ꢥ ꢻꢡ ꢬ ꢹꢿ꣉ꢽ ꢬ꣈ ꢫꢥ ꢳꢺ ꢥꢥ ꢽ ꢬꢪ ꣄ꢬꢭꢥ ꢽꢳ ꢭꣀꢭ꣈ꢥ ꢹꢴ ꢻ ꢾꢥꢤ ꢬ

ꢤ ꢬꢽ ꢪ ꢻꢼ ꢹꢬ ꢼ꣆ ꣈ꢥ ꢻ ꢡ ꢬ ꢪ꣄ꢬ ꢭꢥꢽꢳ ꢭꣀꢭ꣈ꢥ ꣆ꢬ ꢿꢤꢹ

ꢘꣃ ꢥ ꢪ ꢥꢾꢿꢬ ꢳ ꢿꢻ ꢽ ꢿꢽ ꢭꣀꢭ꣈ꢥ ꢳ ꢿꢼꢥ ꢻ ꢡ ꢬ ꢹꢿ꣉ ꢽꢬ ꣈ ꢺꢿꢳ ꣃ ꢤꢥ ꢹ꣆ ꢥꢭꢳ ꢳ ꢻ ꢳ ꣃ ꢥ ꢿꢪ ꢥꢬ ꣈ ꣆ ꢥꢤ ꢿꢻ ꢪ ꢻ ꢾꢥ ꢤ

ꢬ ꢤꢬ ꢽꢪ ꢻ ꢼ ꢹꢬ ꢼ꣆ ꣈ꢥ ꢻ ꢡ ꢭꣀꢭ꣈ꢥ ꢹ

Figure 17. Cycle–to–cycle Jitter

Figure 18. Period Jitter

ꢃ

ꢄ ꢄ

ꢣ ꢈꢦ ꢈꢃ

ꢉꢦ ꢒ

ꢂ

ꢦ

ꢚ

ꢳ

ꢑ

ꢳ

ꢕ

Figure 19. Output Transition Time Test Reference

254

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

For More Information On This Product,

Go to: www.freescale.com


型号：	MPC9774AER2
厂家：	NXP
描述：	9774 SERIES, PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, PLASTIC, LQFP-52 驱动输出元件逻辑集成电路
文件：	总10页 (文件大小：344K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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