MPC97H73FAR2 [NXP]
IC,1:12 OUTPUT,CMOS,QFP,52PIN,PLASTIC;
| 型号： | MPC97H73FAR2 |
| 厂家： | 
NXP |
| 描述： | IC,1:12 OUTPUT,CMOS,QFP,52PIN,PLASTIC 驱动 输出元件 逻辑集成电路 |
| 文件： | 总20页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ꢀꢁꢂ ꢁ ꢃꢁ ꢄꢅ
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC97H73/D
Rev 0, 10/2003
ꢆ
ꢇ
ꢆ
ꢈ
ꢉ
ꢊ
ꢉ
ꢋ
ꢄ
ꢈ
ꢌ
ꢀ
ꢁ
ꢍ
ꢎ
ꢄ
ꢄ
ꢌ
ꢏ
ꢐ
ꢑ
ꢒ
ꢀ
ꢎ
ꢌ
ꢙ
ꢚ
ꢛ
ꢚ
ꢆ
ꢓꢔꢕ ꢔꢖꢗꢘꢐ ꢖ
The MPC97H73 is a 3.3V compatible, 1:12 PLL based clock generator
targeted for high performance low-skew clock distribution in mid-range to
high-performance networking, computing and telecom applications. With
output frequencies up to 240 MHz and output skews less than 250 ps the
device meets the needs of the most demanding clock applications.
3.3V 1:12 LVCMOS
PLL CLOCK GENERATOR
Features
• 1:12 PLL based low-voltage clock generator
• 3.3V power supply
• Internal power–on reset
• Generates clock signals up to 240 MHz
• Maximum output skew of 250 ps
• Differential PECL reference clock input
• Two LVCMOS PLL reference clock inputs
• External PLL feedback supports zero-delay capability
• Various feedback and output dividers (see application section)
• Supports up to three individual generated output clock frequencies
FA SUFFIX
52 LEAD LQFP PACKAGE
CASE 848D
• Synchronous output clock stop circuitry for each individual output for
power down support
• Drives up to 24 clock lines
• Ambient temperature range 0°C to +70°C
• Pin and function compatible to the MPC973
Functional Description
The MPC97H73 utilizes PLL technology to frequency lock its outputs onto an input reference clock. Normal operation of the
MPC97H73 requires the connection of the PLL feedback output QFB to feedback input FB_IN to close the PLL feedback path.
The reference clock frequency and the divider for the feedback path determine the VCO frequency. Both must be selected to
match the VCO frequency range. The MPC97H73 features an extensive level of frequency programmability between the 12
outputs as well as the output to input relationships, for instance 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 5:4, 5:6, 6:1, 8:1 and 8:3.
The QSYNC output will indicate when the coincident rising edges of the above relationships will occur. The selectability of the
feedback frequency is independent of the output frequencies. This allows for very flexible programming of the input reference
versus output frequency relationship. The output frequencies can be either odd or even multiples of the input reference. In
addition the output frequency can be less than the input frequency for applications where a frequency needs to be reduced by a
non–binary factor. The MPC97H73 also supports the 180° phase shift of one of its output banks with respect to the other output
banks. The QSYNC outputs reflects the phase relationship between the QA and QC outputs and can be used for the generation
of system baseline timing signals.
The REF_SEL pin selects the LVPECL or the LVCMOS compatible inputs as the reference clock signal. Two alternative
LVCMOS compatible clock inputs are provided for clock redundancy support. The PLL_EN control selects the PLL bypass
configuration for test and diagnosis. In this configuration, the selected input reference clock is routed directly to the output dividers
bypassing the PLL. The PLL bypass is fully static and the minimum clock frequency specification and all other PLL characteristics
do not apply.
The outputs can be individually disabled (stopped in logic low state) by programming the serial CLOCK_STOP interface of the
MPC97H73. The MPC97H73 has an internal power–on reset.
The MPC97H73 is fully 3.3V compatible and requires no external loop filter components. All inputs (except PCLK) accept
LVCMOS signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 W transmission
lines. For series terminated transmission lines, each of the MPC97H73 outputs can drive one or two traces giving the devices an
effective fanout of 1:24. The device is pin and function compatible to the MPC973 and is packaged in a 52-lead LQFP package.
Motorola, Inc. 2003
MPC97H73
ꢈꢡꢡ ꢢꢣ ꢤꢥꢦ ꢧ ꢨꢩꢢ ꢩꢦ ꢪꢧ ꢩ ꢫꢬ ꢭꢨ ꢬ ꢭꢬꢡ ꢥꢨ ꢪꢮ ꢍꢛ ꢯΩ
ꢉ ꢈꢇ
ꢉ ꢈꢆ
ꢉ ꢈꢍ
ꢉ ꢈꢊ
ꢅ ꢬꢣ ꢯ ꢈ
ꢙꢌ ꢃ ꢔ
ꢙꢌ ꢃ ꢔ
ꢌꢃ ꢔ
ꢁ ꢘꢑ ꢙ
1
0
1
÷ꢚ ꢠ ÷ꢜ ꢠ ÷ꢞ ꢠ ÷ꢆ ꢍ
÷ꢚ ꢠ ÷ꢜ ꢠ ÷ꢞ ꢠ ÷ꢆ ꢇ
÷ꢍ ꢠ ÷ꢚ ꢠ ÷ꢜ ꢠ ÷ꢞ
ꢖꢨ ꢮ
0
1
÷2
÷1
ꢋ ꢌꢑ
ꢋ
ꢌꢌ
0
ꢌ ꢌ ꢃ ꢔꢇ
0
PLL
÷ꢚ ꢠ ÷ꢜ ꢠ ÷ꢞ ꢠ ÷ꢆ ꢇ
÷ꢆ ꢍꢠ ÷ꢆ ꢜꢠ ÷ꢍ ꢇ
1
ꢌ
ꢌ
ꢃ
ꢔ
ꢆ
ꢉ ꢅꢇ
ꢍꢇ ꢇꢵꢚ ꢞꢇ ꢕ ꢶꢷ
ꢅ ꢬꢣ ꢯ ꢅ
ꢌ ꢌ ꢃ ꢔꢄ ꢁꢂ ꢃ
ꢋ
ꢌꢌ
ꢉ ꢅꢆ
ꢉ ꢅꢍ
ꢉ ꢅꢊ
ꢁ ꢳꢣꢴ ꢙ ꢥꢡ ꢩꢨ
ꢌꢃ ꢔ
ꢁ ꢘꢑ ꢙ
ꢖ ꢂꢀꢄ ꢁꢂꢃ
ꢀ ꢅꢄꢓ ꢏ
ꢀ
ꢅ
ꢋꢌ ꢑꢄ ꢁꢂꢃ
ꢙꢃ ꢃꢄ ꢂꢏ
ꢅ ꢬꢣ ꢯ ꢌ
ꢉ ꢌ ꢇ
ꢋ
ꢋ
ꢌꢌ
ꢌꢃ ꢔ
ꢁ ꢘꢑ ꢙ
ꢉ ꢌ ꢆ
ꢉ ꢌ ꢍ
2
2
2
3
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢈ
ꢰ
ꢇ
ꢱ
ꢆ
ꢲ
ꢀ ꢁꢂꢃꢄ ꢅꢰ ꢇꢱ ꢆꢲ
ꢀꢁꢂꢃ ꢄ ꢌ ꢰꢇ ꢱꢆ ꢲ
ꢀꢁ ꢂꢃ ꢄꢀ ꢅꢰꢇ ꢱꢍ ꢲ
0
1
ꢌꢃ ꢔ
ꢁ ꢘꢑ ꢙ
ꢉ ꢌ ꢊ
ꢉ ꢀꢅ
ꢌꢌ
ꢙ ꢑꢸꢂ ꢖ ꢵꢑꢏ ꢖ ꢂꢁꢂ ꢘ
ꢌꢃ ꢑ ꢌꢔ ꢁ ꢘꢑ ꢙ
ꢓꢏ ꢋꢄ ꢌ ꢃ ꢔ
ꢌꢃ ꢔ
ꢁ ꢘꢑ ꢙ
ꢉ
ꢁ
ꢒ
ꢏ
ꢌ
12
ꢁꢘ ꢑꢙꢄ ꢐ ꢈꢘꢈ
ꢁꢘ ꢑꢙꢄ ꢌ ꢃ ꢔ
ꢕ
ꢖ
ꢗ
ꢑ
ꢂ
Figure 1. MPC97H73 Logic Diagram
ꢊ
ꢟ
ꢊ
ꢞ
ꢊ
ꢝ
ꢊ
ꢜ
ꢊ
ꢛ
ꢊ
ꢚ
ꢊ
ꢊ
ꢊ
ꢍ
ꢊ
ꢆ
ꢊ
ꢇ
ꢍ
ꢟ
ꢍ
ꢞ
ꢍ
ꢝ
ꢀꢁ ꢂꢃ ꢄꢅ ꢆ
ꢀꢁ ꢂꢃ ꢄꢅ ꢇ
ꢀꢁ ꢂꢃ ꢄꢈ ꢆ
ꢀꢁ ꢂꢃ ꢄꢈ ꢇ
ꢉ ꢈꢊ
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢀ
ꢅ
ꢆ
ꢚꢇ
ꢚꢆ
ꢚꢍ
ꢚꢊ
ꢚꢚ
ꢚꢛ
ꢚꢜ
ꢚꢝ
ꢚꢞ
ꢚꢟ
ꢛꢇ
ꢛꢆ
ꢛꢍ
ꢍ ꢜ
ꢍ ꢛ
ꢍ ꢚ
ꢍ ꢊ
ꢍ ꢍ
ꢍ ꢆ
ꢍ ꢇ
ꢆ ꢟ
ꢆ ꢞ
ꢆ ꢝ
ꢆ ꢜ
ꢆ ꢛ
ꢆ ꢚ
ꢉ ꢁ ꢒꢏ ꢌ
ꢎ ꢏꢐ
ꢉ
ꢌ
ꢇ
ꢋ
ꢌ
ꢌ
ꢋ
ꢌ
ꢌ
ꢉ
ꢌ
ꢆ
ꢉ
ꢈ
ꢍ
ꢀꢁ ꢂ ꢃꢄ ꢌꢇ
ꢀꢁ ꢂ ꢃꢄ ꢌꢆ
ꢉ ꢌꢍ
MPC97H73
ꢎ
ꢏ
ꢐ
ꢉ
ꢈ
ꢆ
ꢋ
ꢌ
ꢌ
ꢋ
ꢌ
ꢌ
ꢉ
ꢈ
ꢇ
ꢉ
ꢌ
ꢊ
ꢎ
ꢏ
ꢐ
ꢎ
ꢏ
ꢐ
ꢋ
ꢌ
ꢑ
ꢄ
ꢁ
ꢂ
ꢃ
ꢓ
ꢏ
ꢋ
ꢄ
ꢌ
ꢃ
ꢔ
ꢆ
ꢍ
ꢊ
ꢚ
ꢛ
ꢜ
ꢝ
ꢞ
ꢟ
ꢆ
ꢇ
ꢆ
ꢆ
ꢆ
ꢍ
ꢆ
ꢊ
Figure 2. MPC97H73 52–Lead Package Pinout (Top View)
MOTOROLA
2
TIMING SOLUTIONS
MPC97H73
Table 1. PIN CONFIGURATION
Pin
I/O
Input
Type
Function
CCLK0
CCLK1
LVCMOS
LVCMOS
PLL reference clock
Input
Alternative PLL reference clock
PCLK, PCLK
FB_IN
Input
Input
Input
Input
Input
Input
LVPECL
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Differential LVPECL reference clock
PLL feedback signal input, connect to an QFB
LVCMOS clock reference select
CCLK_SEL
REF_SEL
VCO_SEL
PLL_EN
LVCMOS/PECL reference clock select
VCO operating frequency select
PLL enable/PLL bypass mode select
MR/OE
Input
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
Ground
Output enable/disable (high-impedance tristate) and device reset
Frequency divider select for bank A outputs
Frequency divider select for bank B outputs
Frequency divider select for bank C outputs
Frequency divider select for the QFB output
Clock phase selection for outputs QC2 and QC3
Clock input for clock stop circuitry
FSEL_A[0:1]
FSEL_B[0:1]
FSEL_C[0:1]
FSEL_FB[0:2]
INV_CLK
STOP_CLK
STOP_DATA
QA[0-3]
Input
Input
Input
Input
Input
Input
Input
Configuration data input for clock stop circuitry
Clock outputs (Bank A)
Output
Output
Output
Output
Output
Supply
Supply
QB[0-3]
Clock outputs (Bank B)
QC[0-3]
Clock outputs (Bank C)
QFB
PLL feedback output. Connect to FB_IN.
Synchronization pulse output
QSYNC
GND
Negative power supply
VCC_PLL
VCC
PLL positive power supply (analog power supply). It is recommended to use an external
RC filter for the analog power supply pin V . Please see applications section for
CC_PLL
details.
VCC
Supply
VCC
Positive power supply for I/O and core. All VCC pins must be connected to the positive
power supply for correct operation
Table 2. FUNCTION TABLE (Configuration Controls)
Control
REF_SEL
CCLK_SEL
VCO_SEL
Default
0
Selects CCLKx as the PLL reference clock
Selects CCLK0
1
1
1
1
Selects the LVPECL inputs as the PLL reference clock
Selects CCLK1
Selects VCO÷2. The VCO frequency is scaled by a
Selects VCO÷1. (high VCO frequency range)
factor of 2 (low VCO frequency range).
PLL_EN
1
Test mode with the PLL bypassed. The reference clock
is substituted for the internal VCO output. MPC97H73 is
fully static and no minimum frequency limit applies. All
PLL related AC characteristics are not applicable.
Normal operation mode with PLL enabled.
INV_CLK
MR/OE
1
1
QC2 and QC3 are in phase with QC0 and QC1
QC2 and QC3 are inverted (180° phase shift) with
respect to QC0 and QC1
Outputs disabled (high-impedance state) and device is
reset. During reset/output disable the PLL feedback loop
is open and the internal VCO is tied to its lowest
frequency. The MPC97H73 requires reset after any loss
of PLL lock. Loss of PLL lock may occur when the
external feedback path is interrupted. The length of the
reset pulse should be greater than one reference clock
cycle (CCLKx). The device is reset by the internal
power–on reset (POR) circuitry during power–up.
Outputs enabled (active)
VCO_SEL, FSEL_A[0:1], FSEL_B[0:1], FSEL_C[0:1], FSEL_FB[0:2] control the operating PLL frequency range and input/output frequency
ratios. See Table 3 to Table 6 and the applications section for supported frequency ranges and output to input frequency ratios.
TIMING SOLUTIONS
3
MOTOROLA
MPC97H73
Table 3. Output Divider Bank A (NA)
Table 5. Output Divider Bank C (NC)
VCO_SEL FSEL_A1
FSEL_A0
QA[0:3]
VCO÷8
VCO÷12
VCO÷16
VCO÷24
VCO÷4
VCO÷6
VCO÷8
VCO÷12
VCO_SEL FSEL_C1
FSEL_C0
QC[0:3]
VCO÷4
VCO÷8
VCO÷12
VCO÷16
VCO÷2
VCO÷4
VCO÷6
VCO÷8
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table 4. Output Divider Bank B (NB)
VCO_SEL FSEL_B1
FSEL_B0
QB[0:3]
VCO÷8
VCO÷12
VCO÷16
VCO÷20
VCO÷4
VCO÷6
VCO÷8
VCO÷10
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Table 6. Output Divider PLL Feedback (M)
VCO_SEL
FSEL_FB2
FSEL_FB1
FSEL_FB0
QFB
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
VCO÷8
VCO÷12
VCO÷16
VCO÷20
VCO÷16
VCO÷24
VCO÷32
VCO÷40
VCO÷4
VCO÷6
VCO÷8
VCO÷10
VCO÷8
VCO÷12
VCO÷16
VCO÷20
MOTOROLA
4
TIMING SOLUTIONS
MPC97H73
Table 7. GENERAL SPECIFICATIONS
Symbol
Characteristics
Output Termination Voltage
Min
Typ
Max
Unit
V
Condition
V
TT
V
B 2
CC
MM
HBM
LU
ESD Protection (Machine Model)
ESD Protection (Human Body Model)
Latch–Up Immunity
200
2000
200
V
V
mA
pF
pF
C
PD
Power Dissipation Capacitance
Input Capacitance
12
Per output
Inputs
C
IN
4.0
Table 8. ABSOLUTE MAXIMUM RATINGSa
Symbol
Characteristics
Min
-0.3
-0.3
-0.3
Max
3.9
Unit
V
Condition
V
CC
Supply Voltage
V
IN
DC Input Voltage
V
V
+0.3
CC
V
V
OUT
DC Output Voltage
DC Input Current
+0.3
CC
V
I
IN
20
50
mA
mA
°C
I
DC Output Current
Storage Temperature
OUT
T
S
-65
125
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
Table 9. DC CHARACTERISTICS (VCC = 3.3V 5%, TA = 0°C to 70°C)
Symbol
Characteristics
PLL Supply Voltage
Min
3.0
2.0
Typ
Max
Unit
V
Condition
LVCMOS
V
V
CC
CC_PLL
V
IH
Input High Voltage
Input Low Voltage
V
+ 0.3
V
LVCMOS
LVCMOS
CC
V
IL
0.8
V
V
Peak–to–peak Input Voltage PCLK, PCLK
250
mV
LVPECL
LVPECL
PP
a
V
CMR
Common Mode Range
Output High Voltage
Output Low Voltage
PCLK, PCLK
1.0
2.4
V
CC
– 0.6
V
V
b
V
OH
I =-24 mA
OH
V
OL
0.55
0.30
V
V
I = 24 mA
OL
I = 12 mA
OL
Z
Output Impedance
8 - 11
8.0
W
OUT
c
I
Input Current
200
13.5
35
µA
mA
mA
V
V
= V or GND
CC
IN
IN
I
Maximum PLL Supply Current
Pin
CC_PLL
CC_PLL
I
Maximum Quiescent Supply Current
All V Pins
CC
CCQ
a.
V
CMR
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
range
CMR
and the input swing lies within the V (DC) specification.
PP
b. The MPC97H73 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated
transmission line to a termination voltage of V . Alternatively, the device drives up to two 50Ω series terminated transmission lines.
TT
c. Inputs have pull–down resistors affecting the input current.
TIMING SOLUTIONS
5
MOTOROLA
MPC97H73
Table 10. AC CHARACTERISTICS (VCC = 3.3V 5%, TA = 0°C to 70°C)a b
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
f
Input reference frequency
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
6.25
5.00
120.0
80.0
60.0
48.0
40.0
30.0
24.0
20.0
15.0
12.0
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
PLL locked
REF
Input reference frequency in PLL bypass mode
250
480
MHz
MHz
PLL bypass
PLL locked
c
f
f
VCO frequency range
200
VCO
Output Frequency
÷2 output
100.0
50.0
33.3
25.0
20.0
16.6
12.5
10.0
8.33
240.0
120.0
80.0
60.0
48.0
40.0
30.0
24.0
20.0
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MAX
÷4 output
÷6 output
÷8 output
÷10 output
÷12 output
÷16 output
÷20 output
÷24 output
f
Serial interface clock frequency
Peak-to-peak input voltage
Common Mode Range
20
MHz
mV
V
STOP_CLK
V
V
PCLK, PCLK
PCLK, PCLK
400
1.2
2.0
1000
LVPECL
LVPECL
PP
d
V
-0.9
CC
CMR
d
t
Input Reference Pulse Width
ns
PW,MIN
e
t , t
CCLKx Input Rise/Fall Time
1.0
ns
0.8 to 2.0V
PLL locked
R
F
f
t
∅
( )
Propagation Delay (static phase offset)
6.25 MHz < f
< 65.0 MHz
< 125 MHz
-3
-4
-166
+3
+4
+166
°
°
ps
REF
65.0 MHz < f
=50 MHz and feedback=÷8
REF
f
REF
g
t
Output-to-output Skew
within QA outputs
within QB outputs
within QC outputs
all outputs
100
100
100
250
ps
ps
ps
ps
SK(O)
h
DC
t , t
Output Duty Cycle
(T÷2) - 200
T÷2
(T÷2) +200
1.0
ps
ns
ns
ns
ps
ps
Output Rise/Fall Time
Output Disable Time
Output Enable Time
0.1
0.55 to 2.4V
R
F
t
t
t
t
t
8.0
PLZ, HZ
PZL, LZ
JIT(CC)
JIT(PER)
8.0
i
Cycle-to-cycle jitter
150
200
j
Period Jitter
150
k
I/O Phase Jitter RMS (1 σ)
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
11
86
13
88
16
19
21
22
27
30
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
(VCO=400 MHz)
∅
JIT(
)
MOTOROLA
6
TIMING SOLUTIONS
MPC97H73
Table 10. AC CHARACTERISTICS (VCC = 3.3V 5%, TA = 0°C to 70°C)a b
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
l
BW
PLL closed loop bandwidth
÷4 feedback
÷6 feedback
÷8 feedback
÷10 feedback
÷12 feedback
÷16 feedback
÷20 feedback
÷24 feedback
÷32 feedback
÷40 feedback
1.20 - 3.50
0.70 - 2.50
0.50 - 1.80
0.45 - 1.20
0.30 - 1.00
0.25 - 0.70
0.20 - 0.55
0.17 - 0.40
0.12 - 0.30
0.11 - 0.28
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
t
Maximum PLL Lock Time
AC characteristics apply for parallel output termination of 50Ω to V
10
ms
LOCK
a
b
c
.
TT
The input reference frequency must match the VCO lock range divided by the feedback divider ratio: f
= f
÷ (M ⋅ VCO_SEL).
REF VCO
V
CMR
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
range
can
CMR
and the input swing lies within the V (AC) specification. Violation of V
or V impacts static phase offset t
.
∅
)
.
PP
CMR
PP
(
d
e
Calculation of reference duty cycle limits: DC
= t
⋅ f
⋅ 100% and DC
= 100% - DC
REF,MIN
PW,MIN REF
REF,MAX
REF, MIN
The MPC97H73 will operate with input rise/fall times up to 3.0 ns, but the A.C. characteristics, specifically t , t
, DC and f
PW,MIN MAX
∅
(
)
only be guaranteed if t , t are within the specified range.
R
F
f
CCLKx or PCLK to FB_IN. Static phase offset depends on the reference frequency. t [s] = t [°] ÷ (f
⋅ 360°).
∅
∅
( )
(
)
REF
g
h
i
j
k
l
Excluding QSYNC output. See application section for part-to-part skew calculation.
Output duty cycle is DC = (0.5 200 ps ⋅ f ) 100%. E.g. the DC range at f =100MHz is 48%<DC<52%. T = output period.
Cycle jitter is valid for all outputs in the same divider configuration. See application section for more details.
Period jitter is valid for all outputs in the same divider configuration. See application section for more details.
I/O jitter is valid for a VCO frequency of 400 MHz. See application section for I/O jitter vs. VCO frequency.
-3 dB point of PLL transfer characteristics.
⋅
OUT
OUT
TIMING SOLUTIONS
7
MOTOROLA
MPC97H73
APPLICATIONS INFORMATION
MPC97H73 Configurations
the specified frequency range. This divider is controlled by
the VCO_SEL pin. VCO_SEL effectively extends the usable
input frequency range while it has no effect on the output to
reference frequency ratio.
Configuring the MPC97H73 amounts to properly
configuring the internal dividers to produce the desired output
frequencies. The output frequency can be represented by
this formula:
The output frequency for each bank can be derived from
the VCO frequency and output divider:
ꢮ
ꢺ ꢮ
⋅ ꢕ ÷ ꢏ
ꢑꢹ ꢘ ꢖꢂ ꢀ
fQA[0:3] = fVCO ÷ (VCO_SEL ⋅ NA)
fQB[0:3] = fVCO ÷ (VCO_SEL ⋅ NB)
fQC[0:3] = fVCO ÷ (VCO_SEL ⋅ NC)
ꢮ
ꢮ
÷ꢋ ꢌꢑ ꢄꢁ ꢂꢃ
ꢑꢹ ꢘ
ꢙ
ꢃ
ꢃ
÷ꢏ
ꢖꢂ ꢀ
÷ꢕ
Table 11. MPC97H73 Divider
Divider
Function
VCO_SEL
Values
where fREF is the reference frequency of the selected input
clock source (CCLKO, CCLK1 or PCLK), M is the PLL
feedback divider and N is a output divider. The PLL feedback
divider is configured by the FSEL_FB[2:0] and the output
dividers are individually configured for each output bank by
the FSEL_A[1:0], FSEL_B[1:0] and FSEL_C[1:0] inputs.
÷1
÷2
4, 6, 8, 10, 12, 16
M
PLL feedback
FSEL_FB[0:3]
8, 12, 16, 20, 24, 32,
40
÷1
÷2
÷1
÷2
÷1
÷2
4, 6, 8, 12
8, 12, 16, 24
4, 6, 8, 10
N
A
N
B
N
C
Bank A Output Di-
vider FSEL_A[0:1]
The reference frequency fREF and the selection of the
feedback-divider M is limited by the specified VCO frequency
range. fREF and M must be configured to match the VCO
frequency range of 200 to 480 MHz in order to achieve stable
PLL operation:
Bank B Output Di-
vider FSEL_B[0:1]
8, 12, 16, 20
2, 4, 6, 8
Bank C Output Di-
vider FSEL_C[0:1]
4, 8, 12, 16
fVCO,MIN ≤ (fREF ⋅ VCO_SEL ⋅ M) ≤ fVCO,MAX
Table 11 shows the various PLL feedback and output
dividers and Figure 3. and Figure 4. display example
configurations for the MPC97H73:
The PLL post-divider VCO_SEL is either a divide-by-one
or a divide-by-two and can be used to situate the VCO into
Figure 3. Example Configuration
Figure 4. Example Configuration
ꢌꢌ ꢃꢔ ꢇ
ꢌ ꢌꢃꢔ ꢆ
ꢌ ꢌꢃꢔ ꢄꢁ ꢂꢃ
ꢌꢌꢃ ꢔ ꢇ
ꢌꢌꢃ ꢔ ꢆ
ꢌꢌꢃ ꢔ ꢄ ꢁꢂ ꢃ
ꢉ ꢈꢰ ꢊꢱ ꢇꢲ
ꢉ ꢅꢰ ꢊꢱ ꢇꢲ
ꢉ ꢌꢰ ꢊꢱ ꢇꢲ
ꢉ ꢀꢅ
ꢉ ꢈ ꢰꢊ ꢱ ꢇ ꢲ
ꢉ ꢅ ꢰꢊ ꢱ ꢇ ꢲ
ꢉ ꢌꢰ ꢊ ꢱꢇ ꢲ
ꢉ ꢀꢅ
ꢊꢊꢻ ꢊ ꢕꢶ ꢷ
ꢆꢇꢇ ꢕꢶ ꢷ
ꢜ ꢍ ꢻꢛ ꢕꢶ ꢷ
ꢜꢍ ꢻ ꢛ ꢕꢶ ꢷ
ꢮ
ꢧ
ꢨ
ꢮ
ꢺ
ꢊ
ꢊ
ꢻ
ꢊ
ꢕ
ꢶ
ꢷ
ꢮ ꢧꢨ ꢮ ꢺ ꢍ ꢛ ꢕꢶ ꢷ
ꢆ
ꢆ
ꢋ ꢌꢑ ꢄꢁ ꢂꢃ
ꢀꢅ ꢄꢓ ꢏ
ꢋ ꢌꢑ ꢄ ꢁꢂ ꢃ
ꢀꢅ ꢄ ꢓꢏ
ꢆ ꢆ
ꢇ ꢇ
ꢇ ꢇ
ꢇ ꢇ
ꢇ ꢇ
ꢇ ꢇ
ꢀꢁ ꢂꢃ ꢄꢈ ꢰꢆ ꢱꢇ ꢲ
ꢀꢁ ꢂꢃ ꢄꢅ ꢰꢆ ꢱꢇ ꢲ
ꢀꢁ ꢂꢃ ꢄꢌ ꢰꢆ ꢱꢇꢲ
ꢀꢁ ꢂꢃ ꢄꢀꢅ ꢰ ꢍꢱꢇ ꢲ
ꢀꢁ ꢂ ꢃꢄ ꢈ ꢰ ꢆꢱ ꢇ ꢲ
ꢀꢁ ꢂ ꢃꢄ ꢅ ꢰ ꢆꢱ ꢇ ꢲ
ꢀꢁ ꢂ ꢃꢄ ꢌꢰ ꢆ ꢱ ꢇꢲ
ꢀꢁ ꢂ ꢃꢄ ꢀꢅ ꢰ ꢍꢱ ꢇ ꢲ
ꢍ
ꢇ
ꢇ
ꢕ
ꢶ
ꢷ
ꢆꢍ ꢛ ꢕꢶ ꢷ
ꢆ
ꢇ
ꢆ
ꢇ ꢆꢆ
MPC97H73
MPC97H73
ꢊꢊ ꢻꢊ ꢕ ꢶꢷ ꢼ ꢀꢨ ꢨꢽꢾ ꢬꢴꢯꢿ
ꢍ
ꢛ
ꢕ
ꢶ
ꢷ
ꢼ
ꢀ
ꢨ
ꢨ
ꢽ
ꢾ
ꢬ
ꢴ
ꢯ
ꢿ
MPC97H73 example configuration (feedback of
QFB = 33.3 MHz, fVCO=400 MHz, VCO_SEL=÷1,
M=12, NA=12, NB=4, NC=2).
MPC97H73 example configuration (feedback of
QFB = 25 MHz, fVCO=250 MHz, VCO_SEL=÷1,
M=10, NA=4, NB=4, NC=2).
Frequencyrange
Input
Min
Max
Frequencyrange
Input
Min
Max
16.6 MHz
16.6 MHz
50 MHz
40 MHz
40 MHz
120 MHz
240 MHz
20 MHz
50 MHz
50 MHz
100 MHz
48 MHz
120 MHz
120 MHz
240 MHz
QA outputs
QB outputs
QC outputs
QA outputs
QB outputs
QC outputs
100 MHz
MOTOROLA
8
TIMING SOLUTIONS
MPC97H73
MPC97H73 Individual Output Disable (Clock Stop)
Circuitry
writing logic ‘0’ to the respective stop enable bit. Likewise, the
user may programmably enable an output clock by writing
logic ‘1’ to the respective enable bit. The clock stop logic
enables or disables clock outputs during the time when the
output would be in normally in logic low state, eliminating the
possibility of short or ‘runt’ clock pulses.
The individual clock stop (output enable) control of the
MPC97H73 allows designers, under software control, to
implement power management into the clock distribution
design. A simple serial interface and a clock stop control logic
provides a mechanism through which the MPC97H73 clock
outputs can be individually stopped in the logic ‘0’ state: The
clock stop mechanism allows serial loading of a 12–bit serial
input register. This register contains one programmable clock
stop bit for 12 of the 14 output clocks. The QC0 and QFB
outputs cannot be stopped (disabled) with the serial port.
The user can write to the serial input register through the
STOP_DATA input by supplying a logic ‘0’ start bit followed
serially by 12 NRZ disable/enable bits. The period of each
STOP_DATA bit equals the period of the free–running
STOP_CLK signal. The STOP_DATA serial transmission
should be timed so the MPC97H73 can sample each
STOP_DATA bit with the rising edge of the free–running
STOP_CLK signal. (see Figure 5. )
The user can program an output clock to stop (disable) by
ꢁꢘ ꢑꢙꢄ ꢌ ꢃ ꢔ
ꢁ ꢘꢈ ꢖꢘ ꢉ ꢈꢇ
ꢉ ꢈꢆ
ꢉ ꢈꢍ
ꢉ ꢈ ꢊ
ꢉ ꢅ ꢇ
ꢉ ꢅ ꢆ
ꢉ
ꢅ
ꢍ
ꢉ
ꢅ
ꢊ
ꢉ ꢌꢆ
ꢉ ꢌꢍ
ꢉ ꢌꢊ ꢉ ꢁ ꢒꢏ ꢌ
ꢁ
ꢘ
ꢑ
ꢙ
ꢄ
ꢐ
ꢈ
ꢘ
ꢈ
Figure 5. Clock Stop Circuit Programming
TIMING SOLUTIONS
9
MOTOROLA
MPC97H73
SYNC Output Description
coincident rising edges of the QA and QC outputs. The
duration and the placement of the pulse is dependent QA and
QC output frequencies: the QSYNC pulse width is equal to
the period of the higher of the QA and QC output frequencies.
Figure 6. shows various waveforms for the QSYNC output.
The QSYNC output is defined for all possible combinations of
the bank A and bank C outputs.
The MPC97H73 has a system synchronization pulse
output QSYNC. In configurations with the output frequency
relationships are not integer multiples of each other QSYNC
provides a signal for system synchronization purposes. The
MPC97H73 monitors the relationship between the A bank
and the B bank of outputs. The QSYNC output is asserted
(logic low) one period in duration and one period prior to the
ꢮꢋꢌ ꢑ
ꢀ
ꢁ
ꢀ
ꢂ
ꢃ
ꢄ
ꢅ
ꢉ ꢈ
ꢉ ꢌ
ꢉ
ꢁ
ꢒ
ꢏ
ꢌ
ꢆ ꢁꢀ ꢂꢃꢄ ꢅ
ꢉ ꢈ
ꢉꢌ
ꢉ ꢁꢒꢏ ꢌ
ꢇ ꢁꢀ ꢂꢃꢄ ꢅ
ꢇ ꢁꢆ ꢂꢃꢄ ꢅ
ꢈ ꢁꢀ ꢂꢃꢄ ꢅ
ꢈ ꢁꢇ ꢂꢃꢄ ꢅ
ꢉ ꢁꢀ ꢂꢃꢄ ꢅ
ꢉ ꢌ ꢼ÷ꢍ ꢿ
ꢉ ꢈꢼ÷ꢜ ꢿ
ꢉ ꢁꢒꢏ ꢌ
ꢉ ꢈꢼ÷ꢚ ꢿ
ꢉ ꢌꢼ÷ꢜ ꢿ
ꢉ ꢁꢒꢏ ꢌ
ꢉ ꢌ ꢼ÷ꢍ ꢿ
ꢉ ꢈꢼ÷ꢞ ꢿ
ꢉ ꢁꢒꢏ ꢌ
ꢉ ꢈꢼ÷ꢜ ꢿ
ꢉ ꢌꢼ÷ꢞ ꢿ
ꢉ ꢁꢒꢏ ꢌ
ꢉ ꢈ ꢼ÷ꢆ ꢍꢿ
ꢉ ꢌ ꢼ÷ꢍ ꢿ
ꢉ ꢁꢒꢏ ꢌ
Figure 6. QSYNC Timing Diagram
MOTOROLA
10
TIMING SOLUTIONS
MPC97H73
Power Supply Filtering
Using the MPC97H73 in zero–delay applications
The MPC97H73 is a mixed analog/digital product. Its
analog circuitry is naturally susceptible to random noise,
especially if this noise is seen on the power supply pins.
Random noise on the VCC_PLL power supply impacts the
device characteristics, for instance I/O jitter. The MPC97H73
Nested clock trees are typical applications for the
MPC97H73. Designs using the MPC97H73 as LVCMOS PLL
fanout buffer with zero insertion delay will show significantly
lower clock skew than clock distributions developed from
CMOS fanout buffers. The external feedback option of the
MPC97H73 clock driver allows for its use as a zero delay
buffer. The PLL aligns the feedback clock output edge with
the clock input reference edge resulting a near zero delay
through the device (the propagation delay through the device
is virtually eliminated). The maximum insertion delay of the
device in zero-delay applications is measured between the
reference clock input and any output. This effective delay
consists of the static phase offset, I/O jitter (phase or
long-term jitter), feedback path delay and the output-to-output
skew error relative to the feedback output.
provides separate power supplies for the output buffers (VCC
)
and the phase-locked loop (VCC_PLL) of the device. The
purpose of this design technique is to isolate the high
switching noise digital outputs from the relatively sensitive
internal analog phase-locked loop. In a digital system
environment where it is more difficult to minimize noise on the
power supplies a second level of isolation may be required.
The simple but effective form of isolation is a power supply
filter on the VCCA_PLL pin for the MPC97H73. Figure 7.
illustrates a typical power supply filter scheme. The
MPC97H73 frequency and phase stability is most
susceptible to noise with spectral content in the 100kHz to
20MHz range. Therefore the filter should be designed to
target this range. The key parameter that needs to be met in
the final filter design is the DC voltage drop across the series
filter resistor RF. From the data sheet the ICC_PLL current (the
current sourced through the VCC_PLL pin) is typically 8 mA
(13.5 mA maximum), assuming that a minimum of 3.0V must
be maintained on the VCC_PLL pin. The resistor RF shown in
Figure 7. “VCC_PLL Power Supply Filter” must have a
resistance of 5-10W to meet the voltage drop criteria.
Calculation of part-to-part skew
The MPC97H73 zero delay buffer supports applications
where critical clock signal timing can be maintained across
several devices. If the reference clock inputs of two or more
MPC97H73 are connected together, the maximum overall
timing uncertainty from the common CCLKx input to any
output is:
tSK(PP) = t ∅ + tSK(O) + tPD, LINE(FB) + tJIT( ꢀ CF
∅
)
(
)
ꢖ ꢺ ꢛꢵ ꢆꢇΩ
ꢀ
ꢌ ꢺ ꢍꢍ µꢀ
ꢀ
ꢖ
This maximum timing uncertainty consist of 4
components: static phase offset, output skew, feedback
board trace delay and I/O (phase) jitter:
ꢀ
ꢋ ꢌꢌꢄ ꢙꢃ ꢃ
ꢋ
ꢌ
ꢌ
ꢌ
ꢆꢇ ꢣꢀ
ꢀ
ꢂ ꢊꢋ ꢌꢍ ꢎꢍ ꢇ
ꢋ
ꢌ
ꢌ
ꢊꢊ ꢻꢻ ꢻ ꢆꢇꢇ ꢣꢀ
ꢌꢌꢃ ꢔ
ꢌ ꢪ ꣅꣅ ꢪ ꢣ
ꢦ
ꢙ ꢐ ꢠ ꢃꢓ ꢏ ꢂ ꢼꢀ ꢅ ꢿ
ꣂ ꢦ
∅
ꢼ
ꢿ
Figure 7. VCC_PLL Power Supply Filter
ꢉ ꢀꢅ
ꢐ ꢨꢭꢢ ꢴꢨ ꢆ
ꢦ
∅
ꣀꢓ ꢘ ꢼ
ꢿ
The minimum values for RF and the filter capacitor CF are
defined by the required filter characteristics: the RC filter
should provide an attenuation greater than 40 dB for noise
whose spectral content is above 100 kHz. In the example RC
filter shown in Figure 7. “VCC_PLL Power Supply Filter”, the
filter cut-off frequency is around 4.5 kHz and the noise
attenuation at 100 kHz is better than 42 dB.
ꢈ
ꢣ
ꢳ
ꢉ
ꢐ ꢨꢭꢢ ꢴꢨ ꢆ
ꣁ t
ꢁ ꢔ ꢼꢑꢿ
ꣁ ꢦ
∅
ꢼ
ꢿ
ꢉ ꢀꢅ
ꢐ ꢨꢭꢢ ꢴꢨꢍ
ꢦ
∅
ꣀ
ꢓ
ꢘ
ꢼ
ꢿ
As the noise frequency crosses the series resonant point
of an individual capacitor its overall impedance begins to look
inductive and thus increases with increasing frequency. The
parallel capacitor combination shown ensures that a low
impedance path to ground exists for frequencies well above
the bandwidth of the PLL. Although the MPC97H73 has
several design features to minimize the susceptibility to
power supply noise (isolated power and grounds and fully
differential PLL) there still may be applications in which
overall performance is being degraded due to system power
supply noise. The power supply filter schemes discussed in
this section should be adequate to eliminate power supply
noise related problems in most designs.
ꢈ ꢣꢳ ꢉ
ꢐ
ꢨ
ꢭ
ꢢ
ꢴ
ꢨ
ꢍ
ꣁ t
ꢁ ꢔ ꢼꢑꢿ
ꢕꢬ ꣃꢻ ꢩꢯꢨ ꣄
ꢦ
ꢁ
ꢔ
ꢼ
ꢙ
ꢙ
ꢿ
Figure 8. MPC97H73 max. device-to-device skew
Due to the statistical nature of I/O jitter a RMS value (1 s) is
specified. I/O jitter numbers for other confidence factors (CF)
can be derived from Table 12.
TIMING SOLUTIONS
11
MOTOROLA
MPC97H73
Table 12. Confidence Facter CF
ꢕꢬ ꣃꢻ ꢓ ꢗ ꢑ ꢙ ꢫꢬ ꢩꢨ ꣀꢢꢦ ꢦ ꢨ ꢧ ꢭꢨ ꢧꢩꢥ ꢩ ꢀꢧ ꢨ ꢥ ꢨꢣ ꢴꢳ
ꢙ ꢬꢧ ꢬ ꣅꢨ ꢦꢨ ꢧ ꢱ ꢙ ꢃꢃ ꢀꢨ ꢨꢽ ꢾ ꢬ ꢴꢯ ꢐꢢ ꢭꢢꢽ ꢨꢧ ꢀꢅ
CF
1s
Probability of clock edge within the distribution
0.68268948
0.95449988
0.99730007
0.99993663
0.99999943
0.99999999
ꢆ ꢍꢇ
ꢆ ꢇꢇ
ꢞ ꢇ
2s
3s
4s
5s
6s
ꢀꢅ ꢺ ÷ꢜ
ꢀꢅ ꢺ ÷ꢍ ꢚ
ꢜ ꢇ
ꢚ ꢇ
ꢀꢅ ꢺ ÷ꢆ ꢍ
ꢍ ꢇ
ꢇ
The feedback trace delay is determined by the board
layout and can be used to fine-tune the effective delay
through each device.
ꢍ
ꢇ
ꢇ
ꢍ ꢛꢇ
ꢊ ꢇꢇ
ꢊ ꢛꢇ
ꢚ ꢇꢇ
ꢚ
ꢛ
ꢇ
ꢚ
ꢞ
ꢇ
ꢋ
ꢌ
ꢑ
ꢮ
ꢧ
ꢨ
ꢥ
ꢨ
ꢣ
ꢴ
ꢳ
ꢰ
ꢕ
ꢶ
ꢷ
ꢲ
Due to the frequency dependence of the static phase
offset and I/O jitter, using Figure 9. to Figure 11. to predict a
Figure 10. MPC9772 I/O Jitter
maximum I/O jitter and the specified t(∅ parameter relative to
the input reference frequency results in a precise timing
performance analysis.
)
ꢕꢬ ꣃꢻ ꢓ ꢗ ꢑ ꢙ ꢫꢬ ꢩꢨ ꣀꢢꢦ ꢦ ꢨ ꢧ ꢭꢨ ꢧꢩꢥ ꢩ ꢀꢧ ꢨ ꢥ ꢨꢣ ꢴꢳ
ꢙ ꢬꢧ ꢬ ꣅꢨ ꢦꢨ ꢧ ꢱ ꢙ ꢃꢃ ꢀꢨ ꢨꢽ ꢾ ꢬ ꢴꢯ ꢐꢢ ꢭꢢꢽ ꢨꢧ ꢀꢅ
ꢆ ꢚꢇ
ꢆ ꢍꢇ
ꢆ ꢇꢇ
ꢞ ꢇ
In the following example calculation an I/O jitter confidence
factor of 99.7% ( 3s) is assumed, resulting in a worst case
timing uncertainty from the common input reference clock to
any output of -455 ps to +455 ps relative to CCLK (PLL
feedback = ÷8, reference frequency = 50 MHz, VCO
frequency = 400 MHz, I/O jitter = 13 ps rms max., static
ꢀꢅ ꢺ ÷ꢆ ꢇ
ꢀꢅ ꢺ ÷ꢚ ꢇ
ꢜ
ꢇ
ꢚ
ꢇ
ꢀ
ꢅ
ꢺ
÷
ꢍ
ꢇ
phase offset t(∅
=
166 ps):
)
ꢍ
ꢇ
ꢇ
ꢍ
ꢇ
ꢇ
ꢍ
ꢛ
ꢇ
ꢊ
ꢇ
ꢇ
ꢊ
ꢛ
ꢇ
ꢚ
ꢇ
ꢇ
ꢚ
ꢛ
ꢇ
ꢚ
ꢞ
ꢇ
tSK(PP)
=
=
[–166ps...166ps] + [–250ps...250ps] +
[(13ps @ –3)...(13ps @ 3)] + tPD, LINE(FB)
ꢋ
ꢌ
ꢑ
ꢮ
ꢧ
ꢨ
ꢥ
ꢨ
ꢣ
ꢴ
ꢳ
ꢰ
ꢕ
ꢶ
ꢷ
ꢲ
Figure 11. MPC9772 I/O Jitter
Driving Transmission Lines
tSK(PP)
[–455ps...455ps] + tPD, LINE(FB)
The MPC97H73 clock driver was designed to drive high
speed signals in a terminated transmission line environment.
To provide the optimum flexibility to the user the output
drivers were designed to exhibit the lowest impedance
possible. With an output impedance of less than 20Ω the
drivers can drive either parallel or series terminated
transmission lines. For more information on transmission
lines the reader is referred to Motorola application note
AN1091. In most high performance clock networks
point-to-point distribution of signals is the method of choice.
In a point-to-point scheme either series terminated or parallel
terminated transmission lines can be used. The parallel
technique terminates the signal at the end of the line with a
50Ω resistance to VCC÷2.
ꢕꢬ ꣃꢻ ꢓꢗ ꢑ ꢙ ꢫꢬꢩꢨ ꣀꢢ ꢦꢦ ꢨꢧ ꢭꢨꢧ ꢩꢥ ꢩ ꢀꢧ ꢨ ꢥꢨ ꢣꢴꢳ
ꢙꢬ ꢧ ꢬꣅ ꢨꢦ ꢨꢧ ꢱ ꢙ ꢃꢃ ꢀꢨ ꢨꢽꢾ ꢬꢴꢯ ꢐꢢ ꢭꢢ ꢽꢨ ꢧ ꢀꢅ
ꢆ
ꢜ
ꢇ
ꢆ ꢚꢇ
ꢆ ꢍꢇ
ꢆ ꢇꢇ
ꢞ ꢇ
ꢀ
ꢅ
ꢺ
÷
ꢊ
ꢍ
ꢀ ꢅꢺ ÷ꢆꢜ
ꢀꢅ ꢺ ÷ꢞ
ꢜ
ꢇ
ꢚ
ꢇ
ꢍ
ꢇ
ꢀ ꢅꢺ ÷ꢚ
ꢍ ꢛꢇ
ꢇ
ꢍ ꢇꢇ
ꢊ
ꢇ
ꢇ
ꢊ
ꢛ
ꢇ
ꢚ
ꢇ
ꢇ
ꢚ
ꢛ
ꢇ
ꢚ
ꢞ
ꢇ
This technique draws a fairly high level of DC current and
thus only a single terminated line can be driven by each
output of the MPC97H73 clock driver. For the series
terminated case however there is no DC current draw, thus
ꢋ
ꢌ
ꢑ
ꢮ
ꢧ
ꢨ
ꢥ
ꢨ
ꢣ
ꢴ
ꢳ
ꢰ
ꢕ
ꢶ
ꢷ
ꢲ
Figure 9. MPC9772 I/O Jitter
MOTOROLA
12
TIMING SOLUTIONS
MPC97H73
the outputs can drive multiple series terminated lines.
Figure 12. “Single versus Dual Transmission Lines”
illustrates an output driving a single series terminated line
versus two series terminated lines in parallel. When taken to
its extreme the fanout of the MPC97H73 clock driver is
effectively doubled due to its capability to drive multiple lines.
towards the quiescent 3.0V in steps separated by one round
trip delay (in this case 4.0ns).
1. Final skew data pending specification.
ꢊ ꢻꢇ
ꢑ ꢥ ꢦꢈ
ꢑ ꢥ ꢦꢅ
ꢦ ꢺ ꢊ ꢻ ꢞꢟ ꢛꢜ
ꢐ
ꢍ ꢻꢛ
ꢍ ꢻꢇ
ꢆ ꢻꢛ
ꢆ ꢻꢇ
ꢇ ꢻꢛ
ꢇ
ꢦ ꢺ ꢊ ꢻꢟ ꢊ ꢞ ꢜ
ꢕꢙꢌ ꢟꢝ ꢶ ꢝ ꢊ
ꢑ ꢹꢘ ꢙꢹ ꢘ
ꢅꢹ ꢀ ꢀꢂꢖ
ꢐ
ꢓ ꢣ
ꢺ ꢛꢇ Ω
ꢑ
ꢖ ꢺ ꢊꢜ Ω
ꢁ
ꢆ ꢚΩ
ꢓ
ꢏ
ꢑ ꢥ ꢦꢈ
ꢕꢙꢌ ꢟꢝ ꢶ ꢝ ꢊ
ꢑ ꢹꢘ ꢙꢹ ꢘ
ꢅꢹ ꢀ ꢀꢂꢖ
ꢺ ꢛꢇ Ω
ꢺ ꢛꢇ Ω
ꢑ
ꢑ
ꢖ ꢺ ꢊꢜ Ω
ꢁ
ꢑ ꢥ ꢦꢅ ꢇ
ꢑ ꢥ ꢦꢅ ꢆ
ꢆ ꢚΩ
ꢓ ꢏ
ꢖ ꢺ ꢊꢜ Ω
ꢁ
ꢍ
ꢚ
ꢜ
ꢞ
ꢆ ꢇ
ꢆ ꢍ
ꢆ
ꢚ
ꢘꢓ ꢕꢂ ꢼꢣ ꢁ ꢿ
Figure 13. Single versus Dual Waveforms
Figure 12. Single versus Dual Transmission Lines
Since this step is well above the threshold region it will not
cause any false clock triggering, however designers may be
uncomfortable with unwanted reflections on the line. To better
match the impedances when driving multiple lines the
situation in Figure 14. “Optimized Dual Line Termination”
should be used. In this case the series terminating resistors
are reduced such that when the parallel combination is added
to the output buffer impedance the line impedance is perfectly
matched.
The waveform plots in Figure 13. “Single versus Dual
Line Termination Waveforms” show the simulation results of
an output driving a single line versus two lines. In both cases
the drive capability of the MPC97H73 output buffer is more
than sufficient to drive 50Ω transmission lines on the incident
edge. Note from the delay measurements in the simulations a
delta of only 43ps exists between the two differently loaded
outputs. This suggests that the dual line driving need not be
used exclusively to maintain the tight output-to-output skew
of the MPC97H73. The output waveform in Figure 13.
“Single versus Dual Line Termination Waveforms” shows a
step in the waveform, this step is caused by the impedance
mismatch seen looking into the driver. The parallel
combination of the 36Ω series resistor plus the output
impedance does not match the parallel combination of the
line impedances. The voltage wave launched down the two
lines will equal:
ꢕꢙ ꢌꢟ ꢝ ꢶꢝ ꢊ
ꢑ ꢹꢘꢙ ꢹꢘ
ꢺ ꢛ ꢇΩ
ꢺ ꢛ ꢇΩ
ꢑ
ꢑ
ꢖ ꢺ ꢍ ꢍΩ
ꢁ
ꢅ ꢹꢀꢀꢂ ꢖ
ꢆꢚΩ
ꢖ ꢺ ꢍ ꢍΩ
ꢁ
VL = VS ( Z0 ÷ (RS+R0 +Z0))
Z0 = 50Ω || 50Ω
RS = 36Ω || 36Ω
R0 = 14Ω
14Ω + 22Ω k 22Ω = 50Ω k 50Ω
25Ω = 25Ω
Figure 14. Optimized Dual Line Termination
VL = 3.0 ( 25 ÷ (18+17+25)
= 1.31V
At the load end the voltage will double, due to the near
unity reflection coefficient, to 2.6V. It will then increment
TIMING SOLUTIONS
13
MOTOROLA
MPC97H73
ꢕꢙ ꢌꢟ ꢝ ꢶꢝ ꢊ ꢐꢹ ꢘ
ꢙ ꢥꢡ ꢩꢨ
ꢎ ꢨꢣꢨ ꢧ ꢬꢦ ꢪꢧ
ꢺ ꢛꢇ W
ꢺ ꢛꢇΩ
ꢺ ꢛ ꢇΩ
ꢑ
ꢑ
ꢖ ꢺ ꢛ ꢇΩ
ꢘ
ꢖ ꢺ ꢛ ꢇΩ
ꢘ
ꢋ
ꢘ ꢘ
ꢋ
ꢘ ꢘ
Figure 15. CCLK MPC97H73 AC test reference
ꢕꢙ ꢌꢟ ꢝ ꢶꢝ ꢊ ꢐꢹ ꢘ
ꢺ ꢛꢇ Ω
ꢑ
ꢐꢢ ꢮ ꢮ ꢨꢧ ꢨꢣ ꢦꢢ ꢬꢡ
ꢙ ꢥꢡ ꢩꢨ ꢎ ꢨꢣꢨ ꢧ ꢬꢦ ꢪꢧ
ꢺ ꢛꢇ W
ꢺ ꢛ ꢇ Ω
ꢑ
ꢖ ꢺ ꢛ ꢇ Ω
ꢘ
ꢖ ꢺ ꢛ ꢇ Ω
ꢘ
ꢋ
ꢘ ꢘ
ꢋ
ꢘ ꢘ
Figure 16. PCLK MPC97H73 AC test reference
MOTOROLA
14
TIMING SOLUTIONS
MPC97H73
ꢋ
ꢋ
ꢌ ꢌ
Bꢍ
ꢌ ꢌ
ꢋ
ꢋ
ꢌ ꢌ
ꢎꢏ ꢐ
ꢌꢌꢃ ꢔ ꣃ
ꢀꢅ ꢄ ꢓꢏ
Bꢍ
ꢌ ꢌ
ꢋ
ꢋ
ꢌ ꢌ
ꢎꢏ ꢐ
Bꢍ
ꢌ ꢌ
ꢋ
ꢋ
ꢌ ꢌ
ꢎꢏ ꢐ
Bꢍ
ꢌ ꢌ
ꢦ
ꢁ ꢔ ꢼꢑꢿ
ꢎ
ꢏ
ꢐ
ꢘ ꢫꢨ ꢤ ꢢꢣ ꢵꢦ ꢪ ꢵꢤ ꢢꢣ ꢩ ꢯꢨ꣄ ꢢ ꢩ ꢽꢨ ꢮꢢ ꢣꢨ ꢽ ꢬꢩ ꢦ ꢫꢨ ꣄ ꢪꢧ ꢩꢦ ꢴꢬꢩ ꢨ ꢽꢢ ꢮ ꢮꢨ ꢧ ꢨꢣꢴ ꢨ
ꢢꢣ ꢤ ꢧ ꢪꢤ ꢬ ꢬ ꢦꢢ ꢪꢣ ꢽ ꢨꢡ ꢬꢳ ꢾꢨ ꢦ꣄ ꢨꢨ ꢣ ꢬꢣ ꢳ ꢩꢢ ꣅ ꢢꢡ ꢬꢧ ꢽꢨ ꢡꢬ ꢳ ꢤꢬ ꢦꢫ ꣄ꢢ ꢦ ꢫꢢ ꢣ ꢬ
ꢩꢢ ꢣ ꢡꢨ ꢽ ꢨꢭꢢ ꢴꢨ
ꢦ
∅
ꢼ
ꢿ
Figure 17. Output–to–output Skew tSK(O)
Figure 18. Propagation delay (t(∅ , static phase
)
offset) test reference
ꢋ
ꢋ
ꢌ
ꢌ
ꢌ
ꢌ
ꢃ
ꢔ
ꣃ
Bꢍ
ꢌꢌ
ꢎ
ꢏ
ꢐ
ꢦ
ꢙ
ꢀ
ꢅ
ꢄ
ꢓ
ꢏ
ꢘ
ꢇ
ꢀ
ꢁ
ꢂ
ꢃ
ꢅ
ꢆ
ꣃ
ꢈ
ꢇ
ꢇ
ꢉ
ꢆ
ꢊꢋ ꢆ ꢌ
ꢂ ꢆ ꢎ ꢆ ꢏꢐ ꢑꢒ
ꢇ ꢈ
ꢄ
ꢇ
∅
ꢍ
ꢘ ꢫꢨ ꢦꢢ ꣅꢨ ꢮꢧ ꢪ ꣅ ꢦꢫ ꢨ ꢙ ꢃꢃ ꢴꢪꢣ ꢦꢧ ꢪ ꢡꢡ ꢨ ꢽ ꢨꢽ ꢨ ꢦ ꢪ ꢦ ꢫꢨ ꢣꢪ ꢣ ꢴꢪꢣ ꢦꢧ ꢪ ꢡ ꢡꢨ ꢽ
ꢨ ꢽ ꢨ ꢠ ꢽ ꢢꢭꢢ ꢽꢨ ꢽ ꢾ ꢳ ꢦ ꢫꢨ ꢦ ꢢꣅ ꢨ ꢾꢨ ꢦ꣄ ꢨꢨ ꢣ ꢙ ꢃꢃ ꢴꢪꢣ ꢦꢧ ꢪ ꢡꢡ ꢨ ꢽ ꢨꢽ ꢨꢩꢠ
ꢨ ꣃꢤ ꢧꢨ ꢩꢩꢨ ꢽ ꢬ ꢩ ꢬ ꢤꢨ ꢧ ꢴꢨꢣꢦ ꢬ ꢨ
ꢘꢫ ꢨ ꢽ ꢨꢭꢢ ꢬꢦ ꢢ ꢪꢣ ꢢꢣ ꢦ ꢮ ꢪ ꢧ ꢬ ꢴꢪ ꢣꢦ ꢧ ꢪꢡ ꢡꢨ ꢽ ꢨ ꢽ ꢨ ꣄ꢢ ꢦꢫ ꢧꢨ ꢩꢤ ꢨ ꢴꢦ ꢦ ꢪ ꢬ ꢦ ꣅꢨ ꢬꢣ ꢢꢣ ꢬ
ꢧꢬ ꢣ ꢽꢪ ꣅ ꢩꢬ ꣅꢤ ꢡꢨ ꢪ ꢮ ꢴꢳꢴꢡꢨ ꢩ
ꢇ
ꢇ
Figure 19. Output Duty Cycle (DC)
Figure 20. I/O Jitter
ꢆ
ꢂ ꢆ ꢎꢆ
ꢆ ꢂ ꢆ ꢎ ꢈꢗ ꢗ
ꢊꢋ ꢆ ꢌꢄ ꢕ ꢖ ꢍ ꢓ ꢇ
ꢊ
ꢋ
ꢆ
ꢌ
ꢁ
ꢁ
ꢍ
ꢓ
ꢓ
ꢔ
ꢈ
ꢘ
ꢘ
ꢏ ꣁ ꢆ
ꢘ
ꢏ
ꢇ
ꢘ ꢫꢨ ꢭꢬ ꢧ ꢢꢬ ꢦꢢ ꢪꢣ ꢢꢣ ꢴꢳꢴ ꢡꢨ ꢦ ꢢꣅ ꢨ ꢪꢮ ꢬ ꢩꢢ ꢣꢬ ꢡ ꢾꢨ ꢦ꣄ ꢨꢨꢣ ꢬꢽ ꢬ ꢴꢨꢣꢦ ꢴꢳꢴꢡ ꢨꢩꢠ ꢪ ꢭꢨꢧ ꢬ
ꢧ ꢬꢣ ꢽ ꢪꣅ ꢩꢬ ꣅꢤ ꢡ ꢨ ꢪ ꢮ ꢬ ꢽ ꢬ ꢴꢨꢣꢦ ꢴꢳꢴꢡ ꢨ ꢤꢬ ꢢꢧ ꢩ
ꢘꢫ ꢨ ꢽ ꢨꢭꢢ ꢬꢦ ꢢ ꢪꢣ ꢢꢣ ꢴꢳꢴꢡꢨ ꢦ ꢢꣅ ꢨ ꢪ ꢮ ꢬ ꢩꢢ ꢣ ꢬꢡ ꣄ꢢ ꢦꢫ ꢧꢨ ꢩꢤ ꢨꢴ ꢦ ꢦ ꢪ ꢦ ꢫꢨ ꢢꢽ ꢨ ꢬꢡ ꢤ ꢨ ꢧꢢ ꢪꢽ ꢪ ꢭꢨ ꢧ
ꢬ ꢧꢬ ꢣ ꢽꢪ ꣅ ꢩꢬ ꣅꢤ ꢡꢨ ꢪ ꢮ ꢴꢳꢴꢡꢨ ꢩ
Figure 21. Cycle–to–cycle Jitter
Figure 22. Period Jitter
ꢋ ꢺ ꢊꢻ ꢊꢋ
ꢌꢌ
ꢍꢻ ꢚ
ꢇ
ꢻ
ꢛ
ꢛ
ꢦ
ꢦ
ꢖ
ꢀ
Figure 23. Output Transition Time Test Reference
TIMING SOLUTIONS
15
MOTOROLA
MPC97H73
OUTLINE DIMENSIONS
FA SUFFIX
52 LEAD LQFP PACKAGE
CASE 848D-03
ISSUE D
4X
4X 13 TIPS
ꢇꢻ ꢍꢇ ꢼ ꢇ ꢻꢇ ꢇꢞꢿ ꢶ ꢃꢵ ꢕ ꢏ
ꢇ ꢻ ꢍꢇ ꢼꢇ ꢻ ꢇꢇ ꢞ ꢿ ꢘ ꢃ ꢵꢕ ꢏ
52
40
–X–
X=L, M, N
1
39
ꢌ
ꢃ
3X VIEW Y
–L–
AB
AB
G
–M–
B1
B
V
VIEW Y
V1
ꢏ
ꢑ
ꢘ
ꢂ
ꢁ
ꢱ
13
27
ꢆꢻ ꢐ ꢓ ꢕꢂꢏ ꢁ ꢓ ꢑꢏ ꢓ ꢏ ꢎ ꢈ ꢏꢐ ꢘ ꢑꢃ ꢂꢖ ꢈ ꢏ ꢌ ꢓꢏ ꢎ ꢙ ꢂꢖ ꢈ ꢏ ꢁꢓ
ꢒ ꢆꢚꢻ ꢛꢕꢠ ꢆꢟꢞ ꢍꢻ
14
26
ꢍꢻ ꢌ ꢑ ꢏ ꢘꢖ ꢑ ꢃꢃ ꢓꢏ ꢎ ꢐ ꢓ ꢕꢂꢏ ꢁ ꢓꢑ ꢏ ꢱ ꢕꢓ ꢃꢃꢓ ꢕꢂ ꢘꢂ ꢖ ꢻ
ꢊꢻ ꢐ ꢈꢘ ꢹ ꢕ ꢙ ꢃꢈꢏ ꢂ ꢵ ꢶ ꢵ ꢓ ꢁ ꢃꢑ ꢌ ꢈꢘ ꢂꢐ ꢈ ꢘ ꢅ ꢑꢘ ꢘ ꢑ ꢕ ꢑ ꢀ
ꢃꢂ ꢈꢐ ꢈ ꢏ ꢐ ꢓ ꢁ ꢌ ꢑ ꢓꢏ ꢌ ꢓ ꢐ ꢂ ꢏꢘ ꢸꢓ ꢘꢶ ꢘ ꢶ ꢂ ꢃꢂ ꢈꢐ
ꢸꢶ ꢂ ꢖ ꢂ ꢘ ꢶ ꢂ ꢃꢂ ꢈꢐ ꢂ ꢓ ꢘꢁ ꢘ ꢶ ꢂ ꢙ ꢃꢈꢁ ꢘ ꢓꢌ ꢅ ꢑꢐ ꢒ ꢈ ꢘ
ꢘ ꢶ ꢂ ꢅ ꢑꢘ ꢘ ꢑ ꢕ ꢑ ꢀ ꢘ ꢶ ꢂ ꢙꢈ ꢖꢘ ꢓ ꢏ ꢎ ꢃꢓ ꢏ ꢂꢻ
ꢚꢻ ꢐ ꢈꢘ ꢹ ꢕꢁ ꢵ ꢃꢵ ꢠ ꢵ ꢕꢵ ꢈ ꢏ ꢐ ꢵ ꢏ ꢵ ꢘ ꢑ ꢅ ꢂ ꢐ ꢂ ꢘꢂ ꢖ ꢕꢓꢏ ꢂꢐ
ꢈ ꢘ ꢐ ꢈꢘ ꢹ ꢕ ꢙ ꢃꢈꢏ ꢂ ꢵ ꢶ ꢵ ꢻ
–N–
A1
S1
ꢛꢻ ꢐ ꢓ ꢕꢂꢏ ꢁ ꢓ ꢑꢏ ꢁ ꢁ ꢈ ꢏ ꢐ ꢋ ꢘ ꢑ ꢅ ꢂ ꢐ ꢂꢘ ꢂ ꢖ ꢕꢓꢏ ꢂ ꢐ ꢈ ꢘ
ꢁ ꢂꢈꢘ ꢓꢏ ꢎ ꢙ ꢃꢈꢏ ꢂ ꢵ ꢘ ꢵ ꢻ
A
S
ꢜꢻ ꢐ ꢓ ꢕꢂꢏ ꢁ ꢓꢑ ꢏ ꢁ ꢈ ꢈ ꢏ ꢐ ꢅ ꢐ ꢑ ꢏ ꢑ ꢘ ꢓ ꢏ ꢌꢃ ꢹ ꢐ ꢂ ꢕꢑ ꢃꢐ
ꢙ ꢖꢑ ꢘ ꢖ ꢹ ꢁꢓ ꢑ ꢏ ꢻ ꢈ ꢃꢃꢑ ꢸꢈ ꢅꢃꢂ ꢙ ꢖꢑ ꢘ ꢖ ꢹ ꢁꢓ ꢑ ꢏ ꢓ ꢁ
ꢇꢻ ꢍꢛ ꢼ ꢇꢻꢇ ꢆꢇꢿ ꢙ ꢂꢖ ꢁ ꢓꢐ ꢂ ꢻ ꢐ ꢓ ꢕꢂꢏ ꢁ ꢓ ꢑꢏ ꢁ ꢈ ꢈ ꢏ ꢐ ꢅ
ꢐ ꢑ ꢓ ꢏ ꢌꢃ ꢹ ꢐ ꢂ ꢕꢑ ꢃꢐ ꢕꢓ ꢁꢕ ꢈꢘ ꢌ ꢶ ꢈ ꢏꢐ ꢈ ꢖꢂ
ꢐ ꢂ ꢘꢂ ꢖ ꢕꢓꢏ ꢂ ꢐ ꢈ ꢘ ꢐ ꢈꢘ ꢹ ꢕ ꢙ ꢃꢈꢏ ꢂ ꢶ ꢻ
ꢝꢻ ꢐ ꢓ ꢕꢂꢏ ꢁ ꢓ ꢑꢏ ꢐ ꢐ ꢑ ꢂꢁ ꢏ ꢑ ꢘ ꢓ ꢏ ꢌꢃ ꢹ ꢐ ꢂ ꢐ ꢈ ꢕꢅꢈ ꢖ
ꢙ ꢖꢑ ꢘ ꢖ ꢹ ꢁꢓ ꢑ ꢏ ꢻ ꢐ ꢈ ꢕꢅꢈ ꢖ ꢙ ꢖꢑ ꢘ ꢖ ꢹ ꢁꢓ ꢑ ꢏ ꢁ ꢶꢈ ꢃꢃ
ꢏ ꢑ ꢘ ꢌ ꢈꢹ ꢁ ꢂ ꢘ ꢶ ꢂ ꢃꢂ ꢈꢐ ꢸꢓ ꢐ ꢘꢶ ꢘ ꢑ ꢂ ꢌ ꢂ ꢂꢐ ꢇꢻ ꢚ ꢜ
ꢼ ꢇꢻꢇ ꢆꢞꢿ ꢻ ꢕꢓ ꢏ ꢓꢕ ꢹ ꢕ ꢁ ꢙꢈ ꢌ ꢂ ꢅ ꢂꢘ ꢸꢂꢂ ꢏ
ꢙ ꢖꢑ ꢘ ꢖ ꢹ ꢁꢓ ꢑ ꢏ ꢈ ꢏ ꢐ ꢈ ꢐꣀ ꢈꢌ ꢂ ꢏ ꢘ ꢃꢂ ꢈꢐ ꢑ ꢖ
ꢙ ꢖ ꢑꢘ ꢖ ꢹ ꢁꢓ ꢑ ꢏ ꢇꢻ ꢇꢝ ꢼ ꢇꢻꢇ ꢇꢊꢿ ꢻ
4X q2
4X q3
C
ꢇ
ꢻ
ꢆ
ꢇ
ꢼ
ꢇ
ꢻ
ꢇ
ꢇ
ꢚ
ꢿ
ꢘ
–H–
–T–
ꢂꢐ ꢖꢖ ꢐ ꢂꢔ ꢗꢔ ꢘ ꢕ
ꢏ ꢐ ꢂ ꢂꢐ ꢒ ꢂꢑ ꢓ
ꢆꢇꢻ ꢇꢇ ꢅ ꢁꢌ
ꢐ ꢒ ꢋꢎ ꢔ ꢕ
ꢂꢐ ꢒ ꢂꢑ ꢓ
ꢕꢔ ꢑꢗꢐ ꢒ ꢛ
ꢊꢖ ꢑꢒ ꢔ
ꢑ
ꢑ ꢀ
ꢙ
ꢇꢻ ꢊꢟꢚ ꢅ ꢁꢌ
ꢇꢻ ꢆꢟꢝ ꢅ ꢁꢌ
ꢇꢻ ꢊꢟꢚ ꢅ ꢁꢌ
ꢇꢻ ꢆꢟꢝ ꢅ ꢁꢌ
VIEW AA
ꢛꢻ ꢇꢇ ꢅ ꢁꢌ
ꢆꢇꢻ ꢇꢇ ꢅ ꢁꢌ
ꢛꢻ ꢇꢇ ꢅ ꢁꢌ
ꢙ ꢀ
ꢋ
ꢁ
ꢇ
ꢻ
ꢇ
ꢛ
ꢼ
ꢇ
ꢻ
ꢇ
ꢇ
ꢍ
ꢿ
ꢵ ꢵ ꢵ
ꢇꢻ ꢇꢛ
ꢆꢻ ꢊꢇ
ꢇꢻ ꢍꢇ
ꢇꢻ ꢚꢛ
ꢇꢻ ꢍꢍ
ꢆꢻ ꢝꢇ
ꢵ ꢵ ꢵ
ꢇꢻ ꢇꢇꢍ
ꢇꢻ ꢇꢛꢆ
ꢇꢻ ꢇꢇꢞ
ꢇꢻ ꢇꢆꢞ
ꢇꢻ ꢇꢜꢝ
ꢋ ꢀ
ꢋ ꢆ
ꢏ
ꢇꢻ ꢍꢇ
ꢆꢻ ꢛꢇ
ꢇꢻ ꢚꢇ
ꢇꢻ ꢝꢛ
ꢇꢻ ꢊꢛ
ꢇꢻ ꢇꢇꢞ
ꢇꢻ ꢇꢛꢟ
ꢇꢻ ꢇꢆꢜ
ꢇꢻ ꢇꢊꢇ
W
2X R R1
q1
ꢔ
ꢚ
ꢇꢻ ꢇꢇꢟ ꢇꢻ ꢇꢆꢚ
ꢇꢻ ꢇꢍꢜ ꢅ ꢁꢌ
ꢇꢻ ꢍꢛ ꢼ ꢇ ꢻꢇ ꢆ ꢇꢿ
ꢛ
ꢇ
ꢻ
ꢜ
ꢛ
ꢅ
ꢁ
ꢌ
C2
q
ꢜ
ꢇꢻ ꢇꢝ
ꢇꢻ ꢛꢇ ꢖ ꢂꢀ
ꢇꢻ ꢇꢞ
ꢆꢍꢻ ꢇꢇ ꢅ ꢁꢌ
ꢇ
ꢻ
ꢍ
ꢇ
ꢇꢻ ꢇꢇꢊ
ꢇꢻ ꢇꢍꢇ ꢖ ꢂ ꢀ
ꢇꢻ ꢇꢇꢊ ꢇꢻ ꢇꢇꢞ
ꢇꢻ ꢚꢝꢍ ꢅ ꢁꢌ
ꢇ
ꢻ
ꢇ
ꢇ
ꢞ
ꢝ
ꢛ
ꢑ
ꢛ
ꢔ
ꢢ
ꢊ
ꢖ
ꢑ
ꢒ
ꢔ
ꢘ ꢀ
ꢕ
ꢇ
ꢻ
ꢍ
ꢇ
ꢕ ꢀ
ꢞ
ꢜꢻ ꢇꢇ ꢅ ꢁꢌ
ꢇꢻ ꢇꢟꢇ ꢻꢆ ꢜ
ꢆꢍꢻ ꢇꢇ ꢅ ꢁꢌ
ꢜꢻ ꢇꢇ ꢅ ꢁꢌ
ꢇꢻ ꢍꢇ ꢖ ꢂꢀ
ꢆꢻ ꢇꢇ ꢖ ꢂꢀ
ꢇꢻ ꢍꢊꢜ ꢅ ꢁꢌ
ꢇꢻ ꢇꢇꢜ
ꢇꢻ ꢚꢝꢍ ꢅ ꢁꢌ
ꢇꢻ ꢍꢊꢜ ꢅ ꢁꢌ
ꢇꢻ ꢇꢇꢞ ꢖ ꢂ ꢀ
ꢇꢻ ꢇꢊꢟ ꢖ ꢂ ꢀ
K
ꢇ
ꢻ
ꢇ
ꢇ
ꢚ
C1
BASE METAL
ꢟ
F
E
PLATING
ꢟ ꢀ
ꢠ
ꢡ
VIEW AA
Z
θ
ꢇ
ꢇ
ꢆꢍ
ꢆꢍ
ꢝ
ꢵ ꢵ ꢵ
ꢇ
ꢇ
ꢆꢍ
ꢆꢍ
ꢝ
ꢵ ꢵ ꢵ
_
_
_
_
J
U
θꢀ
θꢆ
θꢇ
_
_
ꢖ ꢂ ꢀ
ꢖ ꢂꢀ
ꢖ ꢂꢀ
ꢖ ꢂꢀ
_
_
_
_
D
ꢕ
ꢁ
ꢁ
ꢇ ꢻ ꢆꢊ ꢼꢇ ꢻ ꢇꢇ ꢛ ꢿ
ꢘ ꢃ ꢵꢕ
ꢏ
SECTION AB–AB
ROTATED 90_ CLOCKWISE
MOTOROLA
16
TIMING SOLUTIONS
MPC97H73
NOTES
TIMING SOLUTIONS
17
MOTOROLA
MPC97H73
NOTES
MOTOROLA
18
TIMING SOLUTIONS
MPC97H73
NOTES
TIMING SOLUTIONS
19
MOTOROLA
MPC97H73
Information in this document is provided solely to enable system and software implementers to use Motorola products. There are no express or implied copyright
licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding
the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola
data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals”
must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the rights of
others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury
or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees
arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part.
MOTOROLA and the Stylized M Logo are registered in the US Patent and Trademark Office. All other product or service names are the property of their respective
owners.
E Motorola Inc. 2003
HOW TO REACH US:
USA/EUROPE/LOCATIONS NOT LISTED:
ASIA/PACIFIC: Motorola Semiconductors H.K. Ltd.; Silicon Harbour Centre,
2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.
852–26668334
TECHNICAL INFORMATION CENTER:
1–800–521–6274 or 480–768–2130
HOME PAGE: http://motorola.com/semiconductors
JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center,
3–20–1, Minami–Azabu, Minato–ku, Tokyo 106–8573 Japan
81–3–3440–3569
◊
MPC97H73/D
相关型号：
MPC97H74AER2
PLL Based Clock Driver, 97H Series, 14 True Output(s), 0 Inverted Output(s), CMOS, PQFP52, LEAD FREE, LQFP-52
IDT
MPC97R73FA
PLL Based Clock Driver, 12 True Output(s), 0 Inverted Output(s), CMOS, PQFP52, LQFP-52
MOTOROLA
MPC97R74FA
PLL BASED CLOCK DRIVER, 14 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP52, LQFP-52
MOTOROLA
©2020 ICPDF网 联系我们和版权申明