MPC9817SD [NXP]
66MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO20, SSOP-20;
| 型号： | MPC9817SD |
| 厂家： | 
NXP |
| 描述： | 66MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO20, SSOP-20 时钟 光电二极管 外围集成电路 晶体 |
| 文件： | 总8页 (文件大小：97K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MPC9817
Rev 1, 11/2004
Freescale Semiconductor
Technical Data
Clock Generator for PowerQUICC
and PowerPC Microprocessors and
Microcontrollers
MPC9817
The MPC9817 is a PLL-based clock generator specifically designed for
Freescale Semiconductor Microprocessor and Microcontroller applications
including the PowerPC and PowerQUICC. This device generates the
microprocessor input clock and other microprocessor system and bus clocks at
any one of four output frequencies. These frequencies include the popular
33- and 66-MHz PCI bus frequencies. The device offers five low-skew clock
outputs plus three reference outputs. The clock input reference is 25 MHz and
may be derived from an external source or by the addition of a 25-MHz crystal to
the on-chip crystal oscillator. The extended temperature range of the MPC9817
supports telecommunication and networking requirements.
MICROPROCESSOR
CLOCK GENERATOR
SD SUFFIX
20 SSOP PACKAGE
CASE 1461-01
Features
•
•
•
•
•
•
•
•
•
•
5 LVCMOS outputs for processor and other system circuitry
3 Buffered 25-MHz reference clock outputs
Crystal oscillator or external reference input
25-MHz input reference frequency
Selectable output frequencies include: 25, 33, 50, or 66 MHz
Low cycle-to-cycle and period jitter
EN SUFFIX
Package: 20-lead SSOP
20 SSOP PACKAGE
Pb-FREE PACKAGE
CASE 1461-01
3.3-V supply
Supports computing, networking, and telecommunications applications
Ambient temperature range: –40°C to +85°C
Functional Description
The MPC9817 uses a PLL with a 25-MHz input reference frequency to generate a single bank of five configurable LVCMOS
output clocks. The output frequency of this bank is configurable to either 25, 33, 50, or 66 MHz by two FSEL pins. The 25-MHz
reference may be either an external frequency source or a 25-MHz crystal. The 25-MHz crystal is directly connected to the
XTAL_IN and XTAL_OUT pins with no additional components required. An external reference may be applied to the XTAL_IN
pin with the XTAL_OUT pin left floating. The input reference, whether provided by a crystal or an external input, is also directly
buffered to a second bank of three LVCMOS outputs. These outputs may be used as the clock source for processor I/O
applications such as an Ethernet PHY. When FSEL0 and FSEL1 are both configured low, the QA outputs are directly fed from
the input reference providing a total of eight low-skew 25-MHz outputs. For all other combinations of FSEL0 and FSEL1 the
single-ended LVCMOS outputs provide five low-skew outputs for use in driving a microprocessor or microcontroller clock input
as well as other system components.
The MPC9817 is packaged in a 20-lead SSOP package.
© Freescale Semiconductor, Inc., 2004. All rights reserved.
QA0
QA1
XTAL_IN
Ref
OSC
XTAL_OUT
PLL
33,50,66 MHz
400 MHz
QA2
QA3
FSEL0
FSEL1
QA4
Data
Generator
25 MHz
QREF0
QREF1
QREF2
MR/OE
Figure 1. MPC9817 Logic Diagram
Table 1. Pin Configurations
Pin
QA0, QA1, QA2, QA3, QA4
QREF0, QREF1, QREF2
XTAL_IN
I/O
Output
Output
Input
Output
Input
Input
—
Type
Function
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS
—
Clock Outputs
Reference Output (25 MHz)
Crystal Oscillator Input Pin
Crystal Oscillator Output Pin
XTAL_OUT
FSEL0, FSEL1
MR/OE
Configures Bank A Clock Output Frequency (pull-up)
Enables All Outputs (pull-down)
3.3-V Supply
VDD
GND
—
—
Ground
Table 2. Function Table
Control
Default
11
00
01
10
11
66 MHz
FSEL0,FSEL1
25 MHz fed directly
from reference input,
PLL disabled
33 MHz
50 MHz
MPC9817
Advanced Clock Drivers Devices
Freescale Semiconductor
2
XTAL_IN
XTAL_OUT
FSEL0
VDD
1
20
19
18
17
16
15
14
13
12
11
VDD
2
QA4
QA3
GND
QA2
QA1
VDD
3
4
FSEL1
QREF2
GND
5
6
7
QREF1
QREF0
VDD
8
QA0
MR/OE
GND
9
10
Figure 2. MPC9817 20-Lead SSOP Package Pinout (Top View)
MPC9817 OPERATION
Crystal Oscillator
the reference frequency may be higher than the specified
25 MHz. Externally supplied capacitors on both the XTAL_IN
and XTAL_OUT pins may be used to trim the frequency as
desired.
The crystal should be located as close to the MPC9817
XTAL_IN and XTAL_OUT pins as possible to avoid any board
level parasitic.
The MPC9817 features a fully integrated Pierce oscillator
to minimize system implementation costs. Other than the
addition of a 25-MHz crystal, no external components are
required.The crystal selection should be: 25 MHz, parallel
resonant type with a load specification of CL = 10 pF. Crystals
with a load specification of CL = 20 pF may be used, however,
Table 3. Crystal Specifications
Parameter
Crystal Cut
Value
Fundamental AT Cut
Parallel Resonance
5–7 pF
Resonance
Shunt Capacitance (CL)
Load Capacitance (CO)
10 pF
Equivalent Series Resistance (ESR) 20–60 Ω
Power Supply Bypassing
External Clock Source
The MPC9817 should have all VDD pins bypassed with
0.01 capacitors and a minimum of one 1.0 capacitor for the
overall package. All capacitors should be located as close to
the SSOP pins as possible.
An external reference source of 25 MHz may be applied to
the XTAL_IN pin. In this mode of operation, the XTAL_OUT
pin should be left floating.
MPC9817
Advanced Clock Drivers Devices
Freescale Semiconductor
3
Table 4. Absolute Maximum Ratings(1)
Symbol
VDD
IIN
Characteristics
Min
–0.3
—
Max
3.8
Unit
V
Condition
Supply Voltage
DC Input Current
DC Output Current
Storage Temperature
±20
±75
125
mA
mA
°C
IOUT
TS
—
–65
1. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these
conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated
conditions is not implied.
Table 5. General Specifications
Symbol
VTT
Characteristics
Output Termination Voltage
Min
—
Typ
VDD ÷ 2
—
Max
—
Unit
V
Condition
MM
HBM
LU
ESD Protection (machine model)
ESD Protection (human body model)
Latch-Up Immunity
200
2000
200
—
—
V
—
—
V
—
—
mA
pF
°C/W
°C
CIN
Input Capacitance
4
—
Inputs
θJA
Thermal Resistance (junction-to-ambient)
Ambient Temperature
—
80.8
—
TC
–40
85
Table 6. DC Characteristics (VDD = 3.3 V ± 5%, TA = –40° to +85°C)
Symbol
VIH
Characteristics
Input High Voltage (XTAL_IN)
Min
2.4
2.0
—
Typ
—
Max
VDD + 0.3
VDD + 0.3
0.8
Unit
V
Condition
Input threshold = VDD/2
VIH
Input High Voltage
—
V
VIL
Input Low Voltage
—
V
LVCMOS
IIN
Input Current(1)
—
—
150
µA
V
VIN = VDDL or GND
IOH = –12 mA
IOL = 12 mA
VOH
VOL
ZOUT
IDD
Output High Voltage
Output Low Voltage
Output Impedance
2.4
—
—
—
—
0.4
V
—
14
8.0
—
Ω
Maximum Quiescent Supply Current
—
15.0
mA
VDD pins
1. Inputs have pull-down resistors affecting the input current.
MPC9817
Advanced Clock Drivers Devices
Freescale Semiconductor
4
Table 7. AC Characteristics(1) (2) (VDD = 3.3 V ± 5%, TA = –40° to +85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
Input and Output Timing Specification
fref
Input Reference Frequency
25 MHz Input
XTAL Input
25
25
MHz
MHz
fVCO
fMCX
VCO Frequency Range
Output Frequency (QAx)
—
400
—
MHz
FSEL0, FSEL1 = 00
FSEL0, FSEL1 = 01
FSEL0, FSEL1 = 10
FSEL0, FSEL1 = 11
25
33
50
66
25
—
—
—
—
—
MHz
MHz
MHz
MHz
MHz
PLL locked
Output Frequency (QREFx)
Reference Input Pulse Width
Output Duty Cycle
frefPW
DC
10
—
—
ns
%
@ 25 MHz
47.5
50
52.5
fout
Output Frequency Accuracy
Crystal(3)
External Reference
—
—
100
0
ppm
ppm
With recommended crystal
see Table 3
PLL Specifications
BW
PLL Closed Loop Bandwidth(4)
500
kHz
ms
tLOCK
Maximum PLL Lock Time
10
Skew and Jitter Specifications
tsk(O) Output-to-Output Skew (within a bank)
tsk(O)
100
200
150
ps
Output-to-Output Skew (between bank A and bank Ref)
FSEL0, FSEL1 = 00
tJIT(CC) Cycle-to-Cycle Jitter
ps
ps
ns
@ 25 MHz Input Reference
Q
A output
@ 25 MHz Input Reference
A output
tJIT(PER) Period Jitter
100
1
Q
tr, tf
Output Rise/Fall Time
20% to 80%
1. AC characteristics are design targets and pending characterization.
2. AC characteristics apply for parallel output termination of 50 Ω to VTT
.
3. Based upon recommended crystal specifications as outlined in operation section.
4. –3 dB point of PLL transfer characteristics.
Z = 50 Ω
Z = 50 Ω
Pulse
Generator
Z = 50 Ω
RT = 50 Ω
RT = 50 Ω
DUT MPC9817
VTT
VTT
Figure 3. MPC9817 AC Test Reference (LVCMOS Outputs)
MPC9817
Advanced Clock Drivers Devices
Freescale Semiconductor
5
Table 8. MPC9817 Pin List
Pin
1
Description
XTAL_IN
Pin
11
12
13
14
Description
GND
2
XTAL_OUT
FSEL0
VDD
MR/OE
QA0
3
4
VDD
5
6
FSEL1
QREF2
GND
15
16
17
18
19
20
QA1
QA2
GND
QA3
QA4
VDD
7
8
QREF1
QREF0
VDD
9
10
MPC9817
Advanced Clock Drivers Devices
Freescale Semiconductor
6
PACKAGE DIMENSIONS
.236
.157
.150
4
D
.061
.055
5
PIN 1 ID
18X
1
20
.025
B
4
B
4
B
A
.0125
.344
.337
C
5
L
10
11
SEATING
PLANE
3
H
C
2X
.118
2X 10 TIPS
.003
H
A-B
D
20X
.004
C
7
.010
C
A-B
D
A
A
NOTES:
1. DIMENSIONS ARE IN INCHES.
2. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
3. DATUM PLANE H LOCATED AT MOLD PARTING
LINE AND COINCIDENT WITH LEAD, WHERE
LEAD EXITS PLASTIC BODY AT BOTTOM OF
PARTING LINE.
4. DATUM A, B AND D TO BE DETRMINED WHERE
CENTERLINE BETWEEN LEADS EXITS PLASTIC
BODY AT DATUM PLANE H.
0˚
MIN
(.010)
BASE METAL
5. THIS DIMENSION DOES NOT INCLUDE MOLD
FLASH OR PROTRUSIONS, BUT DO INCLUDE
MOLD MISMATCH AND ARE MEASURED AT THE
MOLD PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED .006
INCHES FOR ENDS AND .008 INCHES FOR
SIDES.
6. THIS DIMENSION IS LENGTH OF TERMINAL FOR
SOLDERING A SUBSTRATE.
7. FORMED LEADS SHALL BE PLANAR WITH
RESPECT TO ONE ANOTHER WITHIN .004
INCHES AT SEATING PLANE.
R.003 MIN
.010
.010
.007
(.008)
.0098
.0040
8
GAUGE PLANE
.012
.008
PLATING
.035
.016
M
.007
C A-B D
8˚
0˚
6
SECTION A-A
SECTION B-B
8. THIS DIMENSION IS DEFINED AS THE DISTANCE
FROM THE SEATING PLANE TO THE LOWEST
POINT OF THE PACKAGE BODY.
CASE 1461-02
ISSUE O
20 SSOP PACKAGE
MPC9817
Advanced Clock Drivers Devices
Freescale Semiconductor
7
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MPC9817
Rev. 1
11/2004
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