MPC9857DW [NXP]

IC,1:10 OUTPUT, DIFFERENTIAL,CMOS,TSSOP,48PIN,PLASTIC;


型号：	MPC9857DW
厂家：	NXP
描述：	IC,1:10 OUTPUT, DIFFERENTIAL,CMOS,TSSOP,48PIN,PLASTIC 驱动光电二极管输出元件逻辑集成电路
文件：	总8页 (文件大小：246K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Freescale Semiconductor, Inc.

SEMICONDUCTOR TECHNICAL DATA

Order this document

by MPC9857/D

The MPC9857 is a high performance, low skew, low jitter, phase-lock

loop (PLL) clock driver. The PLL is used to precisely align the frequency

and phase with the feedback (FBOUT) output to the clock (CLK) input

signal. The MPC9857 operates at 2.5V or 3.3V (PLL) and 2.5V (output

buffer). The MPC9857 which is a zero delay buffer, distributes an SSTL_2

differential clock input pair to 10 SSTL_2 differential output pairs. The

PHASE LOCK LOOP

ZERO DELAY BUFFER

FOR DOUBLE DATA RATE

SDRAM

operating frequency is 50 MHz to 150 MHz.

Enable/Disable pin is provided for low power disable.

A CMOS style

Features:

• SSTL_2 interface clock inputs and outputs

• CMOS control signal input

• 48 pin TSSOP package

• Output frequencies from 50 to 150 MHz

• 10 Differential ouputs (Y0 - Y9)

• 2.5V VCC and 2.5V or 3.3V PLL VCC

• ±100 ps cycle-to-cycle jitter

• ±100 ps peak-to-peak jitter

DW SUFFIX

48 LEAD TSSOP PACKAGE

CASE 1201

• 100 ps maximum output-to-output skew

The MPC9857 has one bank of ten inverting and noninverting outputs

that provide ten low-skew, low-jitter copies of the CLK. The output signal’s

duty cycles are adjusted to 50% which is independent of the duty cycle at

CLK. All the outputs have a enable or disable mechanism via a single

output enable input. When the G input is low the outputs are disabled to

high impedance state (3-state) while if the G input is high, the outputs

switch in phase and frequency with CLK.

Since the loop filter for the PLL in integrated on-chip, the MPC9857

does not require external RC networks resulting in the minimizing of

component count, board space, and cost. The MPC9857 is

characterized for operation from 0°C to 85°C.

Due to the PLL circuitry, the MPC9857 requires a stabilization time to achieve phase lock of the feedback signal to the

reference signal. This stabilization time is required following power up and application of a fixed-frequency, fixed-phase signal at

CLK, as well as following any changes to the PLL reference or feedback signals. For test purposes, the PLL can be bypassed by

strapping AVCC to ground.

This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.

07/00

For More Information On This Product,

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Freescale Semiconductor, Inc.

MPC9857

CLK

PLL

FBIN

AVCC = 3.3V

Note: All outputs are connected to VCC = 2.5V

FBOUT

Figure 1. MPC9857 Logic Diagram

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MPC9857

FUNCTION TABLE

INPUTS

OUTPUTS

PLL

CLK

FBOUT

OFF

GND

VCC

GND

VCC

CLK

VCC

FBIN

CLK

VCC

FBIN

VCC

AVCC

AGND

FBOUT

GND

VCC

GND

Figure 2. 48 Lead Package Pinout (Top View)

For More Information On This Product,

TIMING SOLUTIONS

BR1333 — Rev 6

MOTOROLA

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MPC9857

PIN CONFIGURATION

I/O

Type

Ground

Power

Description

AGND

AVCC

Ground

Power

Analog ground. AGND provides the ground reference for the analog circuitry.

Analog power supply. AVCC provides the power reference for the analog circuitry. In

addition, AVCC can be used to bypass the PLL for test purposes. When AVCC is

strapped to ground, PLL is bypassed and CLK is buffered directly to the device

outputs. During disable (G=0), the PLL is powered down.

CLK, CLK

Input

CMOS

Clock input, CLK provides the clock signal to be distributed by the MPC9857 clock

driver. CLK is used to provide the reference signal to the integrated PLL that

generates the clock ouput signals. CLK must have a fixed frequency and fixed phase

for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK

signal is applied, a stabilization time is required for the PLL to phase lock the feedback

signal to its reference signal.

FBIN, FBIN

FBOUT, FBOUT

Input

Output

Input

SSTL_2

CMOS

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be

hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and

FBIN so that there is nominally zero phase error between CLK and FBIN.

Feedback output. FBOUT is dedicated for external feedback. It switches at the same

frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback

loop of the PLL.

Output bank enable. G is the output enable for outputs Y# and Y#. When G is low,

outputs Y# are disabled to a high-impedance state. When G is high, all outputs Y# are

enabled and switch at the same frequency as CLK.

GND

VCC

Ground

Power

Output

Ground

Power

Ground

Power supply

Y0:10 / Y0:10

SSTL_2

Differential Clock output pairs. These outputs are low-skew copies of CLK/CLK.

ABSOLUTE MAXIMUM RATINGS*

Symbol

VCC

VIN

Characteristics

Supply Voltage

Min

-0.5

Max

4.6

Unit

Condition

Input Voltage

Input Current

VCC+0.5

±50

IIN

°C

Storage temperature

-65

150

NOTE: Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these

conditionsorconditionsbeyondthoseindicatedmayadverselyaffectdevicereliability.Functionaloperationunderabsolute-maximum-rated

conditions is not implied.

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MPC9857

DC CHARACTERISTICS (T = 0 to 85°C)

Symbol

VCC

AVCC

VIH

Characteristics

Min

Typ

2.5

3.3

Max

2.7

Unit

Condition

Supply voltage & I/O Supply voltage

PLL voltage

2.3

3.0

Vref + 0.35

-0.3

3.6

Input high voltage

VCC + 0.3

Vref - 0.35

VCC

VIL

Input low voltage

Note 1

VOH

VOL

Output High Voltage

Output Low Voltage

2.0

0.5

1. The MPC9857 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge

AC CHARACTERISTICS (VCC = 2.5V ± 5%, AVCC = 3.3V, TA = 0 to 85°C)

Symbol

fclk

Characteristics

Clock frequency

Ouput clock skew

Differential clock skew

Output slew rate

Peak-to-peak jitter

Cycle-to-cycle jitter

Duty cycle

Min

Typ

Max

150

100

Unit

MHz

Condition

Note 2

tsk

tdifsk

tsl

1.5

V/ns

Jitter

-100

>-100

100

<100

fdc

Input capacitance

2.5

2. The PLL must be able to handle spread spectrum induced skew (the specification for this frequency modulation can be found in the Intel PC100

registered DIMM specification REV 1.0)

For More Information On This Product,

TIMING SOLUTIONS

BR1333 — Rev 6

MOTOROLA

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Freescale Semiconductor, Inc.

MPC9857

DC CHARACTERISTICS (T = 0 to 85°C)

Symbol

VCC

AVCC

VIH

Characteristics

Supply voltage & I/O Supply voltage

PLL voltage

Min

Typ

2.5

Max

2.7

Unit

Condition

2.3

Vref + 0.35

-0.3

2.7

Input high voltage

VCC + 0.3

Vref - 0.35

VCC

VIL

Input low voltage

Note 3

VOH

VOL

Output High Voltage

Output Low Voltage

2.0

0.5

3. The MPC9857 outputs can drive series or parallel terminated 50Ω (or 50Ω to VCC/2) transmission lines on the incident edge

AC CHARACTERISTICS (VCC = 2.5V ± 5%, AVCC = 2.5V, TA = 0 to 85°C)

Symbol

fclk

Characteristics

Clock frequency

Ouput clock skew

Differential clock skew

Output slew rate

Peak-to-peak jitter

Cycle-to-cycle jitter

Duty cycle

Min

Typ

Max

150

100

Unit

MHz

Condition

Note 4

tsk

tdifsk

tsl

1.5

V/ns

Jitter

-100

>-100

100

<100

fdc

Input capacitance

2.5

4. The PLL must be able to handle spread spectrum induced skew (the specification for this frequency modulation can be found in the Intel PC100

registered DIMM specification REV 1.0)

For More Information On This Product,

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MPC9857

OUTLINE DIMENSIONS

DW SUFFIX

48 LEAD TSSOP PACKAGE

CASE 1201

ISSUE A

48X K REF

NOTES:

0.12 (0.005)

T U

1. DIMENSIONING AND TOLERANCING PER

ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS A AND B DO NOT INCLUDE

MOLD FLASH, PROTRUSIONS OR GATE

BURRS. MOLD FLASH OR GATE BURRS

SHALL NOT EXCEED 0.15 (0.006) PER SIDE.

4. DIMENSION K DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE DAMBAR

PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN

EXCESS OF THE K DIMENSION AT MAXIMUM

MATERIAL CONDITION.

SECTION N–N

–U–

5. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

6. DIMENSIONS A AND B ARE TO BE

DETERMINED AT DATUM PLANE –W–.

MILLIMETERS

DIM MIN MAX

INCHES

–V–

PIN 1

MIN

MAX

0.496

0.244

0.043

0.006

0.030

IDENT.

12.40

6.00

–––

12.60 0.488

6.20 0.236

1.10

–––

0.05

0.50

0.15 0.002

0.75 0.020

0.25 (0.010)

DETAIL E

0.50 BSC

0.0197 BSC

0.37

0.09

0.17

7.95

––– 0.015

0.20 0.004

0.16 0.004

0.27 0.007

0.23 0.007

8.25 0.313

–––

0.008

0.006

0.011

0.009

0.325

–W–

0.076 (0.003)

DETAIL E

–T–

SEATING

PLANE

For More Information On This Product,

TIMING SOLUTIONS

BR1333 — Rev 6

MOTOROLA

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MPC9857

Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or

guaranteeregardingthesuitabilityofitsproductsforanyparticularpurpose,nordoesMotorolaassumeanyliabilityarisingoutoftheapplication

or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages.

“Typical” parameters which may be provided in Motorola data sheets and/or specifications can and do vary in different applications and actual

performancemayvaryovertime. Alloperatingparameters, including“Typicals”mustbevalidatedforeachcustomerapplicationbycustomer’s

technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed,

intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support

orsustainlife,orforanyotherapplicationinwhichthefailureoftheMotorolaproductcouldcreateasituationwherepersonalinjuryordeathmay

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unauthorizeduse, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are

registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.

How to reach us:

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JAPAN: Motorola Japan Ltd.; SPS, Technical Information Center, 3–20–1,

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Technical Information Center: 1–800–521–6274

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2, Dai King Street, Tai Po Industrial Estate, Tai Po, N.T., Hong Kong.

852–26668334

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◊

MPC9857/D

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MPC9857DW [NXP]

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