MPC99J93FA [NXP]
PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32;
| 型号： | MPC99J93FA |
| 厂家： | 
NXP |
| 描述： | PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32 驱动 输出元件 逻辑集成电路 |
| 文件： | 总8页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MOTOROLA
Order Number: MPC99J93/D
Rev 1, 08/2003
SEMICONDUCTOR TECHNICAL DATA
MPC99J93
Product Preview
Intelligent Dynamic Clock
Switch (IDCS) PLL Clock
Driver
The MPC99J93 is a PLL clock driver designed specifically for redun-
dant clock tree designs. The device receives two differential LVPECL
clock signals from which it generates 5 new differential LVPECL clock
outputs. Two of the output pairs regenerate the input signals frequency
and phase while the other three pairs generate 2x, phase aligned clock
outputs.
FA SUFFIX
32--LEAD LQFP PACKAGE
CASE 873A
Features:
• Fully Integrated PLL
• Intelligent Dynamic Clock Switch
• LVPECL Clock Outputs
• LVCMOS Control I/O
• 3.3V Operation
• 32--Lead LQFP Packaging
Functional Description
The MPC99J93 Intelligent Dynamic Clock Switch (IDCS) circuit continuously monitors both input CLK signals. Upon detection
of a failure (CLK stuck HIGH or LOW for at least 1 period), the INP_BAD for that CLK will be latched (H). If that CLK is the primary
clock, the IDCS will switch to the good secondary clock and phase/frequency alignment will occur with minimal output phase
disturbance. The typical phase bump caused by a failed clock is eliminated. (See Application Information section).
PLL_En
Clk_Selected
Inp1bad
Inp0bad
Man_Override
Dynamic Switch
Logic
Qb0
Qb0
Alarm_Reset
OR
Qb1
Qb1
Sel_Clk
CLK0
CLK0
CLK1
CLK1
Qb2
Qb2
÷2
÷4
PLL
Qa0
Qa0
Ext_FB
Ext_FB
200 -- 360 MHz
Qa1
Qa1
MR
Figure 1. Block Diagram
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
E Motorola Inc. 2003
MOTOROLA TIMING SOLUTIONS
1
MPC99J93
24 23 22 21 20 19 18 17
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
Qa1
Qa1
VCC
Inp0bad
Inp1bad
Clk_Selected
GND
Qa0
Qa0
MPC99J93
VCC
VCC_PLL
Man_Override
PLL_En
Ext_FB
Ext_FB
GND
1
2
3
4
5
6
7
8
Figure 2. 32--Lead Pinout (Top View)
Table 1. Pin Descriptions
Pin Name
I/O
Pin Definition
CLK0, CLK0
CLK1, CLK1
LVPECL Input
LVPECL Input
Differential PLL clock reference (CLK0 pulldown, CLK0 pullup)
Differential PLL clock reference (CLK1 pulldown, CLK1 pullup)
Ext_FB, Ext_FB
Qa0:1, Qa0:1
Qb0:2, Qb0:2
Inp0bad
LVPECL Input
LVPECL Output
LVPECL Output
Differential PLL feedback clock (Ext_FB pulldown, Ext_FB pullup)
Differential 1x output pairs. Connect one QAx pair to Ext_FB.
Differential 2x output pairs
LVCMOS Output Indicates detection of a bad input reference clock 0 with respect to the feedback signal. The output
is active HIGH and will remain HIGH until the alarm reset is asserted
Inp1bad
LVCMOS Output Indicates detection of a bad input reference clock 1 with respect to the feedback signal. The output
is active HIGH and will remain HIGH until the alarm reset is asserted
Clk_Selected
Alarm_Reset
LVCMOS Output ‘0’ if clock 0 is selected, ‘1’ if clock 1 is selected
LVCMOS Input
‘0’ will reset the input bad flags and align Clk_Selected with Sel_Clk. The input is “one--shotted”
(50kΩ pullup)
Sel_Clk
Manual_Override
PLL_En
MR
LVCMOS Input
LVCMOS Input
LVCMOS Input
LVCMOS Input
Power Supply
Power Supply
Power Supply
Power Supply
‘0’ selects CLK0, ‘1’ selects CLK1 (50kΩ pulldown)
‘1’ disables internal clock switch circuitry (50kΩ pulldown)
‘0’ bypasses selected input reference around the phase--locked loop (50kΩ pullup)
‘0’ resets the internal dividers forcing Q outputs LOW. Asynchronous to the clock (50kΩ pullup)
VCCA
PLL power supply
Digital power supply
PLL ground
VCC
GNDA
GND
Digital ground
2
MPC99J93
Table 2. ABSOLUTE MAXIMUM RATINGSa
Symbol
Characteristics
Min
-0.3
-0.3
-0.3
Max
Unit
V
Condition
V
Supply Voltage
3.9
CC
V
DC Input Voltage
V
V
+0.3
V
IN
CC
CC
V
DC Output Voltage
DC Input Current
+0.3
V
OUT
I
±20
mA
mA
°C
IN
I
DC Output Current
Storage temperature
±50
OUT
T
S
-65
125
a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions
or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not
implied.
Table 3. GENERAL SPECIFICATIONS
Symbol
Characteristics
Output termination voltage
Min
Typ
Max
Unit
V
Condition
V
V
- 2
CC
TT
MM
HBM
CDM
LU
ESD Protection (Machine model)
ESD Protection (Human body model)
ESD Protection (Charged device model
Latch-up immunity
175
1500
1000
100
V
V
V
mA
pF
C
IN
Input Capacitance
4.0
Inputs
θ
JA
Thermal resistance junction to ambient
JESD 51-3, single layer test board
83.1
73.3
68.9
63.8
57.4
86.0
75.4
70.9
65.3
59.6
°C/W
°C/W
°C/W
°C/W
°C/W
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
JESD 51-6, 2S2P multilayer test board
Thermal resistance junction to case
59.0
54.4
52.5
50.4
47.8
60.6
55.7
53.8
51.5
48.8
°C/W
°C/W
°C/W
°C/W
°C/W
Natural convection
100 ft/min
200 ft/min
400 ft/min
800 ft/min
θ
JC
23.0
26.3
°C/W
MIL-SPEC 883E
Method 1012.1
a
T
J
Operating junction temperature
(continuous operation)
MTBF = 9.1 years
110
°C
a. Operating junction temperature impacts device life time. Maximum continuous operating junction temperature should be selected according
to the application life time requirements (See application note AN1545 for more information). The device AC and DC parameters are speci-
fied up to 110°C junction temperature allowing the MPC99J93 to be used in applications requiring industrial temperature range. It is recom-
mended that users of the MPC99J93 employ thermal modeling analysis to assist in applying the junction temperature specifications to their
particular application.
MOTOROLA TIMING SOLUTIONS
3
MPC99J93
Table 4. DC CHARACTERISTICS (VCC = 3.3V ± 5%, TA = --40° to +85°C)
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
LVCMOS control inputs (MR, PLL_En, Sel_Clk, Man_Override, Alarm_Reset)
V
V
Input High Voltage
Input Low Voltage
2.0
V
+ 0.3
CC
V
V
IH
IL
0.8
a
I
Input Current
±100
µA
V
=V or GND
IN
IN
CC
LVCMOS control outputs (Clk_selected, Inp0bad, Inp1bad)
V
V
Output High Voltage
Output Low Voltage
2.0
0.1
V
V
I
I
=-24 mA
OH
OL
OH
0.55
1.3
= 24 mA
OL
b
LVPECL clock inputs (CLK0, CLK1, Ext_FB)
c
V
V
DC Differential Input Voltage
V
V
Differential operation
Differential operation
PP
d
Differential Cross Point Voltage
V
-1.8
V
-0.3
CC
CMR
CC
a
I
Input Current
±100
µA
V =V or GND
IN CC
IN
LVPECL clock outputs (QA[1:0], QB[2:0])
V
V
Output High Voltage
Output Low Voltage
V
-1.20
-1.90
V
V
-0.95
-1.75
V
V
-0.70
V
V
Termination 50Ω to V
Termination 50Ω to V
OH
OL
CC
CC
CC
CC
CC
CC
TT
TT
V
-1.45
Supply Current
I
I
Maximum Power Supply Current
Maximum PLL Supply Current
180
15
mA
mA
GND pins
GND
V
pin
CC_PLL
CC_PLL
a. Inputs have internal pull-up/pull-down resistors affecting the input current.
b. Clock inputs driven by differential LVPECL compatible signals.
c.
d. V
V
is the minimum differential input voltage swing required to maintain AC characteristics.
CMR
PP
(DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the V
(DC)
CMR
range and the input swing lies within the V (DC) specification.
PP
4
MPC99J93
Table 5. AC Characteristics (VCC = 3.3V ± 5%, TA = --40°C to +85°C)a
Symbol
Characteristics
Input Reference Frequency
Min
50
Typ
Max
90
Unit
MHz
MHz
Condition
f
f
f
÷4 feedback
÷4 feedback
PLL locked
ref
b
VCO Frequency Range
Output Frequency
200
360
VCO
MAX
QA[1:0]
QB[2:0]
50
100
90
180
MHz
MHz
PLL locked
f
t
Reference Input Duty Cycle
Propagation Delay
25
75
%
refDC
c
SPO, static phase offset
-0.15
0.9
+0.17
1.8
ns
ns
PLL_EN=1
PLL_EN=0
∅
(
)
CLK0, CLK1 to any Q
d
V
V
Differential input voltage
(peak-to-peak)
0.25
1.3
V
V
PP
e
Differential input crosspoint voltage
V
-1.7
V
-0.3
CC
CMR
sk(O)
CC
t
Output-to-output Skew
within QA[2:0] or QB[1:0]
50
80
ps
ps
within device
f
f
g
g
∆
Rate of change of period
QA[1:0]
20
10
200
100
50
25
400
200
ps
ps
ps
ps
per/cycle
QB[2:0]
QA[1:0]
QB[2:0]
DC
Output Duty Cycle
45
50
25
55
%
ps
ms
ns
t
t
Cycle-to-Cycle Jitter
Maximum PLL Lock Time
Output Rise/Fall Time
RMS (1 σ)
JIT(CC)
LOCK
10
t , t
r
0.05
0.70
20% to 80%
f
a. AC characteristics apply for parallel output termination of 50Ω to V
.
CC - 2V
b. The input reference frequency must match the VCO lock range divided by the feedback divider ratio (FB): f = f
÷ FB.
ref
VCO
c. CLK0, CLK1 to Ext_FB.
d. V is the minimum differential input voltage swing required to maintain AC characteristics including SPO and device-to-device skew. Ap-
PP
plicable to CLK0, CLK1 and Ext_FB.
e. V
(AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the V
(AC)
CMR
CMR
range and the input swing lies within the V
(AC) specification. Violation of V
(AC) or V (AC) impacts the SPO, device and part-to-
PP
CMR PP
part skew. Applicable to CLK0, CLK1 and Ext_FB.
f. Specification holds for a clock switch between two input signals (CLK0, CLK1) no greater than 400 ps out of phase. Delta period change
per cycle is averaged over the clock switch excursion.
g. Specification holds for a clock switch between two input signals (CLK0, CLK1) at any phase difference (±180_). Delta period change per
cycle is averaged over the clock switch excursion.
MOTOROLA TIMING SOLUTIONS
5
MPC99J93
APPLICATIONS INFORMATION
The MPC99J93 is a dual clock PLL with on--chip Intelligent latched (L) indicating CLK0 is the PLL reference signal. While
Dynamic Clock Switch (IDCS) circuitry.
neither INP_BAD is latched (H), the Clk_Selected can be freely
changed with Sel_Clk. Whenever a CLK switch occurs,
(manually or by IDCS), following the next negative edge of the
newly selected PLL reference signal, the next positive edge pair
of Ext_FB and the newly selected PLL reference signal will slew
to alignment.
To calculate the overall uncertainty between the input CLKs
and the outputs from multiple MPC99J93’s, the following
procedure should be used. Assuming that the input CLKs to all
MPC9993’s are exactly in phase, the total uncertainty will be the
sum of the static phase offset, max I/O jitter, and output to output
skew.
During a dynamic switch, the output phase between two
devices may be increased for a short period of time. If the two
input CLKs are 400ps out of phase, a dynamic switch of an
MPC99J93 will result in an instantaneous phase change of
400ps to the PLL reference signal without a corresponding
change in the output phase (due to the limited response of the
PLL). As a result, the I/O phase of a device, undergoing this
switch, will initially be 400ps and diminish as the PLL slews to
its new phase alignment. This transient timing issue should be
considered when analyzing the overall skew budget of a
system.
Definitions
primary clock: The input CLK selected by Sel_Clk.
secondary clock: The input CLK NOT selected by Sel_Clk.
PLL reference signal: The CLK selected as the PLL refer-
ence signal by Sel_Clk or IDCS. (IDCS can override Sel_Clk).
Status Functions
Clk_Selected: Clk_Selected (L) indicates CLK0 is selected as
the PLL reference signal. Clk_Selected (H) indicates CLK1 is
selected as the PLL reference signal.
INP_BAD: Latched (H) when it’s CLK is stuck (H) or (L) for at
least one Ext_FB period (Pos to Pos or Neg to Neg). Cleared
(L) on assertion of Alarm_Reset.
Control Functions
Sel_Clk: Sel_Clk (L) selects CLK0 as the primary clock.
Sel_Clk (H) selects CLK1 as the primary clock.
Alarm_Reset: Asserted by a negative edge. Generates a
one--shot reset pulse that clears INPUT_BAD latches and
Clk_Selected latch.
PLL_En: While (L), the PLL reference signal is substituted for
the VCO output.
MR: While (L), internal dividers are held in reset which holds all
Q outputs LOW.
Hot insertion and withdrawal
In PECL applications, a powered up driver will experience a
low impedance path through an MPC99J93 input to its powered
down VCC pins. In this case, a 100 ohm series resistance
should be used in front of the input pins to limit the driver current.
The resistor will have minimal impact on the rise and fall times
of the input signals.
Man Override (H)
(IDCS is disabled, PLL functions normally). PLL reference
signal (as indicated by Clk_Selected) will always be the CLK
selected by Sel_Clk. The status function INP_BAD is active in
Man Override (H) and (L).
Acquiring Frequency Lock
Man Override (L)
1. While the MPC99J93 is receiving a valid CLK signal, assert
Man_Override HIGH.
(IDCS is enabled, PLL functions enhanced). The first CLK to
fail will latch it’s INP_BAD (H) status flag and select the other
input as the Clk_Selected for the PLL reference clock. Once
2. The PLL will phase and frequency lock within the specified
latched, the Clk_Selected and INP_BAD remain latched until lock time.
assertion of Alarm_Reset which clears all latches (INP_BADs 3. Apply a HIGH to LOW transition to Alarm_Reset to reset
are cleared and Clk_Selected = Sel_Clk). NOTE: If both CLKs Input Bad flags.
are bad when Alarm_Reset is asserted, both INP_BADs will be 4. De--assert Man_Override LOW to enable Intelligent Dynam-
latched (H) after one Ext_FB period and Clk_Selected will be ic Clock Switch mode.
6
MPC99J93
OUTLINE DIMENSIONS
FA SUFFIX
PLASTIC LQFP PACKAGE
CASE 873A--03
ISSUE B
4X
0.20
H
A--B D
6
D1
3
A, B, D
e/2
D1/2
32
PIN 1 INDEX
25
1
F
F
A
B
E1/2
E1
6
E
4
DETAIL G
E/2
DETAIL G
17
8
NOTES:
9
7
1. DIMENSIONS ARE IN MILLIMETERS.
D
4
2. INTERPRET DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994.
D/2
3. DATUMS A, B, AND D TO BE DETERMINED AT
DATUM PLANE H.
4X
D
4. DIMENSIONS D AND E TO BE DETERMINED AT
SEATING PLANE C.
0.20
C
A--B
D
5. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED
THE MAXIMUM b DIMENSION BY MORE THAN
0.08--mm. DAMBAR CANNOT BE LOCATED ON THE
LOWER RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSION AND ADJACENT LEAD OR
PROTRUSION: 0.07--mm.
H
28X e
32X
0.1 C
SEATING
PLANE
6. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS
0.25--mm PER SIDE. D1 AND E1 ARE MAXIMUM
PLASTIC BODY SIZE DIMENSIONS INCLUDING
MOLD MISMATCH.
C
DETAIL AD
BASE
PLATING
METAL
7. EXACT SHAPE OF EACH CORNER IS OPTIONAL.
8. THESE DIMENSIONS APPLY TO THE FLAT SECTION
OF THE LEAD BETWEEN 0.1--mm AND 0.25--mm
FROM THE LEAD TIP.
b1
c
c1
MILLIMETERS
DIM MIN
MAX
1.60
0.15
1.45
0.45
0.40
0.20
0.16
A
A1
A2
b
1.40
0.05
1.35
0.30
0.30
0.09
0.09
b
5
8
_
8X (θ1 )
M
0.20
C A--B
D
R R2
b1
c
SECTION F--F
R R1
c1
D
9.00 BSC
D1
e
7.00 BSC
0.80 BSC
9.00 BSC
7.00 BSC
A2
A
0.25
E
GAUGE PLANE
E1
L
0.50
0.70
L1
1.00 REF
(S)
θ
0
7
_
_
A1
_
θ
L
θ1
R1
R2
S
12 REF
_
0.08
0 . 0 8
0.20
-- -- --
(L1)
0.20 REF
DETAIL AD
MOTOROLA TIMING SOLUTIONS
7
MPC99J93
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“Typicals”, must be validated for each customer application by customer’s technical experts. Motorola does not convey any license under its patent rights nor the
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owners. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
E Motorola Inc. 2003
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HOME PAGE: http://motorola.com/semiconductors
◊
MPC99J93/D
相关型号：
MPC99J93FAR2
PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, PLASTIC, LQFP-32
NXP
MPC99J93FAR2
PLL Based Clock Driver, 5 True Output(s), 0 Inverted Output(s), PQFP32, PLASTIC, LQFP-32
MOTOROLA
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