MR1A8AVYS35 [NXP]
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| 型号： | MR1A8AVYS35 |
| 厂家： | 
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Document Number: MR0A16A
Rev. 2, 11/2007
Freescale Semiconductor
Data Sheet
64K x 16-Bit 3.3-V
Asynchronous
MR0A16A
44-TSOP
Case 924A-02
Magnetoresistive RAM
Introduction
Features
•
•
Single 3.3-V power supply
The MR0A16A is a 1,048,576-bit magnetoresistive
random access memory (MRAM) device
Commercial temperature range (0°C to
70°C), Industrial temperature range (-40°C
to 85°C) and Extended temperature range
(-40°C to 105°C)
organized as 65,536 words of 16 bits. The
MR0A16A is equipped with chip enable (E), write
enable (W), and output enable (G) pins, allowing
for significant system design flexibility without bus
contention. Because the MR0A16A has separate
byte-enable controls (LB and UB), individual bytes
can be written and read.
•
•
•
•
Symmetrical high-speed read and write with
fast access time (35 ns)
Flexible data bus control — 8 bit or 16 bit
access
MRAM is a nonvolatile memory technology that
protects data in the event of power loss and does
not require periodic refreshing. The MR0A16A is
the ideal memory solution for applications that
must permanently store and retrieve critical data
quickly.
Equal address and chip-enable access
times
Automatic data protection with low-voltage
inhibit circuitry to prevent writes on power
loss
•
All inputs and outputs are
The MR0A16A is available in a 400-mil, 44-lead
plastic small-outline TSOP type-II package with an
industry-standard center power and ground SRAM
pinout.
transistor-transistor logic (TTL) compatible
•
•
Fully static operation
Full nonvolatile operation with 20 years
minimum data retention
The MR0A16A is available in Commercial (0°C to
70°C), Industrial (-40°C to 85°C) and Extended
(-40°C to 105°C) ambient temperature ranges.
This document contains information on a new product under development. Freescale
reserves the right to change or discontinue this product without notice.
© Freescale Semiconductor, Inc., 2007. All rights reserved.
Device Pin Assignment
OUTPUT
ENABLE
BUFFER
G
UPPER BYTE OUTPUT ENABLE
LOWER BYTE OUTPUT ENABLE
8
A[15:0]
16
ADDRESS
BUFFERS
UPPER
BYTE
OUTPUT
BUFFER
8
ROW
DECODER
COLUMN
DECODER
8
8
SENSE
CHIP
ENABLE
BUFFER
E
AMPS
16
8
LOWER
BYTE
8
64K x 16
OUTPUT
BUFFER
BIT
MEMORY
ARRAY
UPPER
BYTE
WRITE
ENABLE
BUFFER
8
W
DQU[15:8]
DQL[7:0]
8
8
WRITE
DRIVER
16
FINAL
WRITE
DRIVERS
LOWER
BYTE
WRITE
DRIVER
8
UB
LB
UB
LB
UPPER BYTE WRITE ENABLE
LOWER BYTE WRITE ENABLE
BYTE
ENABLE
BUFFER
Figure 1. Block Diagram
Device Pin Assignment
A0
A1
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A15
A14
A13
G
2
Table 1. Pin Functions
Signal Name Function
Address input
A2
3
A3
4
A4
5
UB
LB
E
6
A
DQL0
DQL1
DQL2
DQL3
7
DQU15
DQU14
DQU13
DQU12
E
Chip enable
8
9
W
Write enable
10
11
12
13
14
15
16
17
18
19
20
21
22
G
Output enable
Upper byte select
Lower byte select
V
V
SS
DD
V
VDD
UB
LB
DQL
DQU
SS
DQL4
DQL5
DQL6
DQL7
W
DQU11
DQU10
DQU9
DQU8
NC
Data I/O, lower byte
Data I/O, upper byte
Power supply
A5
VDD
V
V
DD
SS
A6
V
SS
Ground
A7
A12
A11
A10
A8
NC
Do not connect this pin
A9
Figure 2. MR0A16A in 44-Pin TSOP Type II Package
MR0A16A Advanced Information Data Sheet, Rev. 2
2
Freescale Semiconductor
Electrical Specifications
Table 2. Operating Modes
V
1
1
1
1
1
2
2
DD
E
G
W
LB
UB
Mode
DQL[7:0]
DQU[15:8]
Current
H
X
H
X
L
X
H
X
H
H
H
L
X
X
H
L
X
X
H
H
L
Not selected
I
, I
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
Hi-Z
SB1 SB2
L
L
L
L
L
L
L
L
Output disabled
Output disabled
Lower byte read
Upper byte read
Word read
I
I
I
I
I
DDR
DDR
DDR
DDR
DDR
D
Out
L
H
L
Hi-Z
D
D
Out
Out
L
L
D
Out
X
X
X
L
H
L
Lower byte write
Upper byte write
Word write
I
I
I
D
Hi-Z
DDW
DDW
DDW
In
L
H
L
Hi-Z
D
D
In
In
L
L
D
In
NOTES:
1
H = high, L = low, X = don’t care
Hi-Z = high impedance
2
Electrical Specifications
Absolute Maximum Ratings
This device contains circuitry to protect the inputs against damage caused by high static voltages or
electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage
greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic fields. Precautions should be taken to
avoid application of any magnetic field more intense than the maximum field intensity specified in the
maximum ratings.
MR0A16A Advanced Information Data Sheet, Rev. 2
Freescale Semiconductor
3
Electrical Specifications
1
Table 3. Absolute Maximum Ratings
Parameter
Symbol
Value
Unit
V
2
Supply voltage
V
–0.5 to 4.0
DD
2
Voltage on any pin
Output current per pin
V
–0.5 to V + 0.5
V
In
DD
I
20
mA
W
Out
3
Package power dissipation
P
0.600
D
Temperature under bias
MR0A16AYS35 (Commercial)
MR0A16ACYS35 (Industrial)
MR0A16AVYS35 (Extended)
–10 to 85
–45 to 95
–45 to 110
T
°C
Bias
Storage temperature
T
–55 to 150
260
°C
°C
stg
Lead temperature during solder (3 minute max)
T
Lead
Maximum magnetic field during write
MR0A16AYS35 (Commercial)
MR0A16ACYS35 (Industrial)
MR0A16AVYS35 (Extended)
15
25
25
H
Oe
Oe
max_write
Maximum magnetic field during read or standby
H
100
max_read
NOTES:
1
Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation
should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields
could affect device reliability.
2
3
All voltages are referenced to V
.
SS
Power dissipation capability depends on package characteristics and use environment.
Table 4. Operating Conditions
Parameter
Symbol
Min
Typ
3.3
2.7
Max
Unit
V
1
Power supply voltage
Write inhibit voltage
V
3.0
3.6
DD
1
V
2.5
3.0
V
WI
V
0.3
+
DD
Input high voltage
V
2.2
—
—
V
V
2
IH
3
Input low voltage
V
–0.5
0.8
IL
Operating temperature
MR0A16AYS35 (Commercial)
MR0A16ACYS35 (Industrial)
MR0A16AVYS35 (Extended)
0
-40
-40
70
85
105
T
°C
A
NOTES:
1
After power up or if V
falls below V , a waiting period of 2 ms must be observed, and E and W
WI
DD
must remain high for 2 ms. Memory is designed to prevent writing for all input pin conditions if V
DD
falls below minimum V
.
WI
2
3
V
V
(max) = V + 0.3 Vdc; V (max) = V + 2.0 Vac (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
(min) = –0.5 Vdc; V (min) = –2.0 Vac (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
IH
IL
DD IH DD
IL
MR0A16A Advanced Information Data Sheet, Rev. 2
4
Freescale Semiconductor
Electrical Specifications
Direct Current (dc)
Table 5. dc Characteristics
Parameter
Symbol
Min
Typ
—
Max
1
Unit
μA
Input leakage current
Output leakage current
Output low voltage
I
—
—
lkg(I)
I
—
1
μA
lkg(O)
(I = +4 mA)
V
—
—
—
0. 4
V
V
OL
OL
(I = +100 μA)
V
+ 0.2
OL
SS
Output high voltage
(I = –4 mA)
V
2. 4
—
OH
OH
(I = –100 mA)
V
– 0.2
OH
DD
Table 6. Power Supply Characteristics
Parameter Symbol Typ
Max
Unit
1
ac active supply current — read modes
I
55
80
mA
DDR
(I
= 0 mA, V = max)
Out
DD
1
ac active supply current — write modes
(V = max)
DD
105
105
105
155
165
165
MR0A16AYS35 (Commercial)
MR0A16ACYS35 (Industrial)
MR0A16AVYS35 (Extended)
I
DDW
mA
ac standby current
(V = max, E = V )
(no other restrictions on other inputs)
I
18
9
28
12
mA
mA
DD
IH
SB1
SB2
CMOS standby current
(E ≥ V – 0.2 V and V ≤ V + 0.2 V or ≥ V – 0.2 V)
I
DD
In
SS
DD
(V = max, f = 0 MHz)
DD
NOTES:
1
All active current measurements are measured with one address transition per cycle.
1
Table 7. Capacitance
Parameter
Symbol
Typ
—
Max
Unit
Address input capacitance
Control input capacitance
Input/output capacitance
C
C
6
6
8
pF
pF
pF
In
In
—
C
—
I/O
NOTES:
1
f = 1.0 MHz, dV = 3.0 V, T = 25°C, periodically sampled rather than 100% tested.
A
MR0A16A Advanced Information Data Sheet, Rev. 2
Freescale Semiconductor
5
Electrical Specifications
Table 8. ac Measurement Conditions
Parameter
Value
1.5 V
Logic input timing measurement reference level
Logic output timing measurement reference level
Logic input pulse levels
1.5 V
0 or 3.0 V
2 ns
Input rise/fall time
Output load for low and high impedance parameters
Output load for all other timing parameters
See Figure 3A
See Figure 3B
+3.3 V
ZD = 50 Ω
725 Ω
OUTPUT
OUTPUT
600 Ω
RL = 50 Ω
5 pF
V = 1.5 V
L
A
B
Figure 3. Output Load for ac Test
MR0A16A Advanced Information Data Sheet, Rev. 2
6
Freescale Semiconductor
Electrical Specifications
This page is intentionally blank.
MR0A16A Advanced Information Data Sheet, Rev. 2
Freescale Semiconductor
7
Timing Specifications
Timing Specifications
Read Mode
1, 2
Table 9. Read Cycle Timing
Symbol
Parameter
Min
Max
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Read cycle time
t
35
—
—
—
—
3
AVAV
Address access time
t
t
35
35
15
15
—
AVQV
ELQV
GLQV
3
Enable access time
Output enable access time
Byte enable access time
t
t
BLQV
AXQX
Output hold from address change
t
4, 5
Enable low to output active
t
3
—
ELQX
GLQX
4, 5
Output enable low to output active
t
0
—
4, 5
Byte enable low to output active
t
0
—
BLQX
EHQZ
GHQZ
4, 5
Enable high to output Hi-Z
t
0
15
10
10
4, 5
Output enable high to output Hi-Z
t
0
4, 5
Byte high to output Hi-Z
t
0
BHQZ
NOTES:
1
W is high for read cycle.
2
Due to product sensitivities to noise, power supplies must be properly grounded and
decoupled, and bus contention conditions must be minimized or eliminated during read and
write cycles.
Addresses valid before or at the same time E goes low.
This parameter is sampled and not 100% tested.
3
4
5
Transition is measured 200 mV from steady-state voltage.
MR0A16A Advanced Information Data Sheet, Rev. 2
8
Freescale Semiconductor
Timing Specifications
tAVAV
A (ADDRESS)
Q (DATA OUT)
tAXQX
PREVIOUS DATA VALID
DATA VALID
tAVQV
NOTES:
Device is continuously selected (E ≤ V , G ≤ V ).
IL
IL
Figure 4. Read Cycle 1
tAVAV
A (ADDRESS)
tAVQV
tELQV
E (CHIP ENABLE)
tEHQZ
tELQX
G (OUTPUT ENABLE)
tGHQZ
tGLQV
tGLQX
LB, UB (BYTE ENABLE)
Q (DATA OUT)
tBHQZ
tBLQV
tBLQX
DATA VALID
Figure 5. Read Cycle 2
MR0A16A Advanced Information Data Sheet, Rev. 2
Freescale Semiconductor
9
Timing Specifications
Write Mode
1, 2, 3, 4, 5
Table 10. Write Cycle Timing 1 (W Controlled)
Parameter Symbol Min
Max
—
Unit
ns
6
Write cycle time
t
35
0
AVAV
Address set-up time
t
—
ns
AVWL
AVWH
AVWH
Address valid to end of write (G high)
Address valid to end of write (G low)
t
t
18
20
—
ns
—
ns
t
t
WLWH
Write pulse width (G high)
Write pulse width (G low)
15
15
—
—
ns
ns
WLEH
t
WLWH
t
WLEH
DVWH
WHDX
Data valid to end of write
Data hold time
t
t
10
0
—
—
12
—
—
ns
ns
ns
ns
ns
7, 8, 9
Write low to data Hi-Z
t
0
WLQZ
WHQX
7, 8, 9
Write high to output active
t
3
Write recovery time
NOTES:
t
12
WHAX
1
A write occurs during the overlap of E low and W low.
2
Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and
bus contention conditions must be minimized or eliminated during read and write cycles.
If G goes low at the same time or after W goes low, the output will remain in a high-impedance state.
After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum
of 2 ns.
The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent
cycle is the same as the minimum cycle time allowed for the device.
3
4
5
6
7
8
9
All write cycle timings are referenced from the last valid address to the first transition address.
This parameter is sampled and not 100% tested.
Transition is measured 200 mV from steady-state voltage.
At any given voltage or temperature, t
max < t
min.
WLQZ
WHQX
MR0A16A Advanced Information Data Sheet, Rev. 2
10
Freescale Semiconductor
Timing Specifications
tAVAV
A (ADDRESS)
tAVWH
tWHAX
E (CHIP ENABLE)
tWLEH
tWLWH
W (WRITE ENABLE)
tAVWL
LB, UB (BYTE ENABLE)
tDVWH
tWHDX
D (DATA IN)
DATA VALID
Hi-Z
tWLQZ
Hi-Z
Q (DATA OUT)
tWHQX
Figure 6. Write Cycle 1 (W Controlled)
MR0A16A Advanced Information Data Sheet, Rev. 2
Freescale Semiconductor
11
Timing Specifications
1, 2, 3, 4, 5
Table 11. Write Cycle Timing 2 (E Controlled)
Parameter Symbol
Min
35
0
Max
—
Unit
ns
6
Write cycle time
t
t
AVAV
AVEL
AVEH
AVEH
ELEH
Address set-up time
—
ns
Address valid to end of write (G high)
Address valid to end of write (G low)
t
t
t
18
20
—
ns
—
ns
Enable to end of write (G high)
15
15
—
—
ns
ns
t
ELWH
t
7, 8
ELEH
ELWH
Enable to end of write (G low)
t
t
t
Data valid to end of write
Data hold time
10
0
—
—
—
ns
ns
ns
DVEH
EHDX
Write recovery time
NOTES:
t
12
EHAX
1
A write occurs during the overlap of E low and W low.
2
Due to product sensitivities to noise, power supplies must be properly grounded and decoupled
and bus contention conditions must be minimized or eliminated during read and write cycles.
3
4
5
If G goes low at the same time or after W goes low, the output will remain in a high-impedance
state.
After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a
minimum of 2 ns.
The minimum time between E being asserted low in one cycle to E being asserted low in a
subsequent cycle is the same as the minimum cycle time allowed for the device.
6
7
8
All write cycle timings are referenced from the last valid address to the first transition address.
If E goes low at the same time or after W goes low, the output will remain in a high-impedance state.
If E goes high at the same time or before W goes high, the output will remain in a high-impedance
state.
MR0A16A Advanced Information Data Sheet, Rev. 2
12
Freescale Semiconductor
Timing Specifications
tAVAV
A (ADDRESS)
tAVEH
tEHAX
tELEH
E (CHIP ENABLE)
tAVEL
tELWH
W (WRITE ENABLE)
LB, UB (BYTE ENABLE)
tDVEH
tEHDX
D (DATA IN)
DATA VALID
Hi-Z
Q (DATA OUT)
Figure 7. Write Cycle 2 (E Controlled)
MR0A16A Advanced Information Data Sheet, Rev. 2
Freescale Semiconductor
13
Timing Specifications
1, 2, 3, 4, 5, 6
Table 12. Write Cycle Timing 3 (LB/UB Controlled)
Parameter Symbol Min
Max
—
Unit
ns
7
Write cycle time
t
t
35
0
AVAV
AVBL
Address set-up time
—
ns
Address valid to end of write (G high)
Address valid to end of write (G low)
t
t
t
18
20
—
ns
AVBH
AVBH
—
ns
BLEH
BLWH
Byte pulse width (G high)
Byte pulse width (G low)
15
15
—
—
ns
ns
t
t
BLEH
BLWH
t
t
t
Data valid to end of write
Data hold time
10
0
—
—
—
ns
ns
ns
DVBH
BHDX
Write recovery time
NOTES:
t
12
BHAX
1
A write occurs during the overlap of E low and W low.
Due to product sensitivities to noise, power supplies must be properly grounded and decoupled and
bus contention conditions must be minimized or eliminated during read and write cycles.
If G goes low at the same time or after W goes low, the output will remain in a high-impedance state.
After W, E, or UB/LB has been brought high, the signal must remain in steady-state high for a minimum
of 2 ns.
2
3
4
5
6
7
If both byte control signals are asserted, the two signals must have no more than 2 ns skew between
them.
The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent
cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
MR0A16A Advanced Information Data Sheet, Rev. 2
14
Freescale Semiconductor
Timing Specifications
tAVAV
A (ADDRESS)
tAVBH
tBHAX
E (CHIP ENABLE)
tAVBL
tBLEH
tBLWH
LB, UB (BYTE ENABLE)
W (WRITE ENABLE)
tBHDX
tDVBH
DATA VALID
D (DATA IN)
Hi-Z
Hi-Z
Q (DATA OUT)
Figure 8. Write Cycle 3 (LB/UB Controlled)
MR0A16A Advanced Information Data Sheet, Rev. 2
Freescale Semiconductor
15
Ordering Information
Ordering Information
This product is available in Commercial, Industrial, and Extended temperature versions.
Freescale's semiconductor products can be classified into the following tiers: “Commercial”, “Industrial”
and “Extended.” A product should only be used in applications appropriate to its tier as shown below. For
questions, please contact a Freescale sales representative.
•
Commercial — Typically 5 year applications - personal computers, PDA's, portable telecom
products, consumer electronics, etc.
•
Industrial, Extended — Typically 10 year applications - installed telecom equipment,
workstations, servers, etc. These products can also be used in Commercial applications.
Part Numbering System
(Order by Full Part Number)
16 YS 35
MR
0
A
A
V
Timing Set (35 = 35 ns)
Package Type (YS = TSOP II)
Freescale MRAM Memory Prefix
Operating Temperature Range
(Missing = 0°C to 70°C,
Density Code (0 = 1 Mb, 1 = 2 Mb,
2 = 4 Mb, 4 = 16 Mb)
C = -40°C to 85°C, V = -40°C to 105°C)
Memory Type (A = async, S = sync)
Revision (A = rev 1)
I/O Configuration (08 = 8 bits, 16 = 16 bits)
Package Information
Table 13. Package Information
Pin
Device
Package
Type
RoHS
Compliant
Designator
Case No.
Document No.
Count
TSOP
Type II
MR0A16A
44
YS
924A-02
98ASS23673W
True
MR0A16A Advanced Information Data Sheet, Rev. 2
16
Freescale Semiconductor
Revision History
Revision History
Revision History
Revision
Date
18 Jun 2007 Initial Advance Information Release
Page 1: Removed Advance Information label next to Data Sheet.
Description of Change
0
1
2
21 Sep 2007
Table 6: Applied values to TBD’s in IDD specifications.
12 Nov 2007 Table 2: Changed IDDA to IDDR or IDDW.
Mechanical Drawing
The following pages detail the package available to MR0A16A.
MR0A16A Advanced Information Data Sheet, Rev. 2
Freescale Semiconductor
17
Mechanical Drawing
MR0A16A Advanced Information Data Sheet, Rev. 2
18
Freescale Semiconductor
Mechanical Drawing
MR0A16A Advanced Information Data Sheet, Rev. 2
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19
Mechanical Drawing
MR0A16A Advanced Information Data Sheet, Rev. 2
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Freescale Semiconductor
Mechanical Drawing
MR0A16A Advanced Information Data Sheet, Rev. 2
Freescale Semiconductor
21
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© Freescale Semiconductor, Inc. 2007.
MR0A16A
Rev. 2, 11/2007
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