MSC7112VM800 [NXP]
32-BIT, 200MHz, OTHER DSP, PBGA400, 17 X 17 MM, LEAD FREE, BGA-400;型号: | MSC7112VM800 |
厂家: | NXP |
描述: | 32-BIT, 200MHz, OTHER DSP, PBGA400, 17 X 17 MM, LEAD FREE, BGA-400 时钟 外围集成电路 |
文件: | 总56页 (文件大小:911K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet
Document Number: MSC7112
Rev. 11, 4/2008
MSC7112
Low-Cost 16-bit DSP with
DDR Controller
MAP-BGA–400
17 mm × 17 mm
•
StarCore® SC1400 DSP extended core with one SC1400 DSP
core, 192 Kbyte of internal SRAM M1 memory, 16 way 16 Kbyte
instruction cache (ICache), four-entry write buffer, programmable
interrupt controller (PIC), and low-power Wait and Stop
processing modes.
•
•
Multi-channel DMA controller with 32 time-multiplexed
unidirectional channels, priority-based time-multiplexing
between channels using 32 internal priority levels, fixed- or
round-robin-priority operation, major-minor loop structure, and
DONE or DRACK protocol from requesting units.
Two independent TDM modules with independent receive and
transmit, programmable sharing of frame sync and clock,
programmable word size (8 or 16-bit), hardware-base
A-law/μ-law conversion, up to 50 Mbps data rate per TDM, up to
128 channels, with glueless interface to E1/T1 frames and MVIP,
SCAS, and H.110 buses.
•
•
8 Kbyte boot ROM.
AHB-Lite crossbar switch that allows parallel data transfers
between four master ports and six slave ports, where each port
connects to an AHB-Lite bus; fixed or round robin priority
programmable at each slave port; programmable bus parking at
each slave port; low power mode.
•
•
Internal PLL generates up to 266 MHz clock for the SC1400 core
and up to 133 MHz for the crossbar switch, DMA channels, and
other peripherals.
Clock synthesis module provides predivision of PLL input clock;
independent clocking of the internal timers and DDR module;
programmable operation in the SC1400 low power Stop mode;
independent shutdown of different regions of the device.
Enhanced 16-bit wide host interface (HDI16) provides a glueless
connection to industry-standard microcomputers,
microprocessors, and DSPs and can also operate with an 8-bit host
data bus, making if fully compatible with the DSP56300 HI08
from the external host side.
DDR memory controller that supports byte enables for up to a
32-bit data bus; glueless interface to 150 MHz 14-bit page mode
DDR-RAM; 14-bit external address bus supporting up to 1 Gbyte;
and 16-bit or 32-bit external data bus.
•
•
•
UART with full-duplex operation up to 5.0 Mbps.
Up to 41 general-purpose input/output (GPIO) ports.
I2C interface that allows booting from EEPROM devices up to 1
Mbyte.
Two quad timer modules, each with sixteen configurable 16-bit
timers.
fieldBIST™ unit detects and provides visibility into unlikely field
failures for systems with high availability to ensure structural
integrity, that the device operates at the rated speed, is free from
reliability defects, and reports diagnostics for partial or complete
device inoperability.
Standard JTAG interface allows easy integration to system
firmware and internal on-chip emulation (OCE10) module.
Optional booting external host via 8-bit or 16-bit access through
the HDI16, I2C, or SPI using in the boot ROM to access serial SPI
Flash/EEPROM devices; different clocking options during boot
with the PLL on or off using a variety of input frequency ranges.
•
•
•
•
•
•
•
•
Programmable memory interface with independent read buffers,
programmable predictive read feature for each buffer, and a write
buffer.
System control unit performs software watchdog timer function;
includes programmable bus time-out monitors on AHB-Lite slave
buses; includes bus error detection and programmable time-out
monitors on AHB-Lite master buses; and has address
out-of-range detection on each crossbar switch buses.
Event port collects and counts important signal events including
DMA and interrupt requests and trigger events such as interrupts,
breakpoints, DMA transfers, or wake-up events; units operate
independently, in sequence, or triggered externally; can be used
standalone or with the OCE10.
•
© Freescale Semiconductor, Inc., 2004, 2008. All rights reserved.
Table of Contents
1
2
Pin Assignments. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 6. DDR DRAM Output Timing Diagram . . . . . . . . . . . . . 26
Figure 7. DDR DRAM AC Test Load . . . . . . . . . . . . . . . . . . . . . 26
Figure 8. TDM Receive Signals. . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 9. TDM Transmit Signals . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 10. Read Timing Diagram, Single Data Strobe . . . . . . . . 29
Figure 11. Read Timing Diagram, Double Data Strobe. . . . . . . . 30
Figure 12. Write Timing Diagram, Single Data Strobe. . . . . . . . . 30
Figure 13. Write Timing Diagram, Double Data Strobe . . . . . . . . 31
Figure 14. Host DMA Read Timing Diagram, HPCR[OAD] = 0. . 31
Figure 15. Host DMA Write Timing Diagram, HPCR[OAD] = 0 . . 32
Figure 16. I2C Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 17. UART Input Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 18. UART Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 19. EE Pin Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 20. EVNT Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 21. GPI/GPO Pin Timing . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 22. Test Clock Input Timing Diagram . . . . . . . . . . . . . . . . 36
Figure 23. Boundary Scan (JTAG) Timing Diagram . . . . . . . . . . 37
Figure 24. Test Access Port Timing Diagram . . . . . . . . . . . . . . . 37
Figure 25. TRST Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 26. Voltage Sequencing Case 1. . . . . . . . . . . . . . . . . . . . 40
Figure 27. Voltage Sequencing Case 2. . . . . . . . . . . . . . . . . . . . 41
Figure 28. Voltage Sequencing Case 3. . . . . . . . . . . . . . . . . . . . 42
Figure 29. Voltage Sequencing Case 4. . . . . . . . . . . . . . . . . . . . 43
Figure 30. Voltage Sequencing Case 5. . . . . . . . . . . . . . . . . . . . 44
Figure 31. PLL Power Supply Filter Circuits . . . . . . . . . . . . . . . . 45
Figure 32. SSTL Termination Techniques . . . . . . . . . . . . . . . . . . 50
Figure 33. SSTL Power Value . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
1.1 MAP-BGA Ball Layout Diagrams . . . . . . . . . . . . . . . . . .4
1.2 Signal List By Ball Location. . . . . . . . . . . . . . . . . . . . . . .6
Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.1 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
2.2 Recommended Operating Conditions. . . . . . . . . . . . . .18
2.3 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .18
2.4 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . .19
2.5 AC Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Hardware Design Considerations. . . . . . . . . . . . . . . . . . . . . .38
3.1 Thermal Design Considerations . . . . . . . . . . . . . . . . . .38
3.2 Power Supply Design Considerations. . . . . . . . . . . . . .39
3.3 Estimated Power Usage Calculations. . . . . . . . . . . . . .46
3.4 Reset and Boot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
3.5 DDR Memory System Guidelines . . . . . . . . . . . . . . . . .50
Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Package Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Product Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
3
4
5
6
7
List of Figures
Figure 1. MSC7112 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. MSC7112 Molded Array Process-Ball Grid Array
(MAP-BGA), Top View . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. MSC7112 Molded Array Process-Ball Grid Array
(MAP-BGA), Bottom View . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Timing Diagram for a Reset Configuration Write . . . . 24
Figure 5. DDR DRAM Input Timing Diagram . . . . . . . . . . . . . . 24
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
2
DMA
(32 Channel)
AMDMA
JTAG Port
JTAG
ASM2
128
64
Boot ROM
(8 KB)
to IPBus
DSP
Extended
Core
SC1400
Core
ASEMI
External Bus
32
External
Trace
Buffer
(8 KB)
Memory
Interface
from
64
IPBus
Interrupts
Interrupt Control
Fetch
Unit
Host
HDI16
Port
Interface
(HDI16)
Instruction
Cache
ASTH
AMIC
TDM
32
(16 KB)
64
128
64
2 TDMs
AMEC
PLL/Clock
Extended
Core
Interface
ASAPB
PLL/Clock
2
I C
32
2
APB
I C
RS-232
GPIO
UART
M1
SRAM
ASM1
GPIO
(192 KB)
128
64
64
ASIB
System Ctrl
64
P XA XB
Events
32
32
Watchdog
Event Port
BTMs
to EMI
to/from OCE10
Timers
to DMA
Note: The arrows show the
direction of the transfer.
IPBus
Figure 1. MSC7112 Block Diagram
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
3
Assignments
1
Pin Assignments
This section includes diagrams of the MSC7112 package ball grid array layouts and pinout allocation tables.
1.1
MAP-BGA Ball Layout Diagrams
Top and bottom views of the MAP-BGA package are shown in Figure 2 and Figure 3 with their ball location index numbers.
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
B
C
D
E
F
GND
GND
DQM1 DQS2
CK
CK
HD15
HD12
HD10
HD7
HD6
HD4
HD1
HD0
GND
NC
NC
NC
NC
NC
VDDM
NC
D30
D28
D26
D15
D13
D12
VDDM
CS0
D25
D27
D31
D29
GND
D11
D9
DQM2 DQS3 DQS0
CKE
WE
HD14
CAS
HD11
HD13
VDDM
VDDM
VDDM
HD8
HD9
HD5
HD3
HD2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
HA2
NC
NC
NC
NC
NC
NC
HA1
D24
CS1
DQM3 DQM0 DQS1
RAS
VDDM
VDDC
NC
VDDM
VDDM
VDDM
VDDC
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDC
A10
VDDM
VDDC
VDDC
VDDM
VDDM
VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
VDDC
GND
VDDM
VDDC
VDDM
VDDM
VDDM
VDDC
VDDC
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDC
VDDC
VDDIO VDDIO VDDIO VDDIO VDDIO
VDDC
GND
VDDM
VDDM
VDDIO
VDDC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDM
VDDC
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDM
VDDM
VDDC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDC
VDDC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDIO
GND
GND
GND
GND
GND
VDDIO VDDIO
G
H
J
GND
D14
D10
D0
GND
GND
VDDM
GND
GND
GND
GND
GND
GND
GND
GND
VDDM
VDDM
VDDC
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDM
VDDC
VDDIO VDDIO
VDDIO
GND
HA3
HA0
HACK HREQ
VDDIO VDDIO
K
L
GND
GND
VDDM
D8
GND
GND
GND
VDDM
VDDM
VDDM
VDDC
VDDC
HDDS
HDS
VDDIO VDDIO VDDIO
D1
D3
HCS2 HCS1
HRW
VDDC
M
N
P
R
T
D2
D5
GND
GND
GND
GND
GND
SDA
UTXD URXD
VREF
VDDIO
VDDC
VSSPLL
VDDPLL
TEST0
D4
D6
D17
D19
D20
D21
NC
CLKIN
SCL
VDDIO VDDIO
D7
D16
D18
D22
D23
A13
A12
A9
PORESET TPSEL
VDDIO VDDIO
GND
VDDM
TDO
NC
EE0
VDDIO VDDIO VDDIO VDDIO
VDDC
TMS HRESET
VDDC
VDDC
VDDC
VDDC
VDDC
U
V
W
Y
GND
NC
TCK
NC
TRST
TDI
VDDM
A11
A8
A5
A6
A4
A2
A3
BA0
NC
NC
EVNT0 EVNT4 T0TCK T1RFS T1TD GPIA28 GPID6 GPIA22 GPIA24
VDDM
GND
A7
EVNT1 EVNT2 T0RFS T0TFS T1RD T1TFS GDPD4 GPIA27 GPIA19 GPIA23 GPIA26 H8BIT
EVNT3 T0RCK T0RD TOTD T1RCK T1TCK GPIA29 GPID5 GPIA20 GPIA21 GND GPIA25
VDDM
GND
A1
A0
BA1
NMI
Figure 2. MSC7112 Molded Array Process-Ball Grid Array (MAP-BGA), Top View
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
4
Freescale Semiconductor
Pin Assignments
Bottom View
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
NC
NC
NC
NC
NC
GND
HD0
HD1
HD4
HD6
HD7
HD10
HD12
HD15
CK
CK
DQS2 DQM1
GND
GND
VDDM
NC
NC
NC
NC
NC
NC
HA1
NC
NC
NC
NC
NC
NC
HA2
NC
NC
NC
NC
NC
NC
NC
HA3
HA0
NC
NC
NC
NC
NC
NC
NC
NC
HD2
NC
HD5
HD3
HD8
HD9
HD11
HD13
VDDM
VDDM
VDDM
HD14
CAS
VDDM
VDD
WE
RAS
VDDM
VDD
CKE
DQS0 DQS3 DQM2
CS0
D25
D27
D31
D29
GND
D11
D9
NC
D30
D28
D26
D15
D13
D12
VDDM
DQS1 DQM0 DQM3
CS1
GND
VDDM
VDD
D24
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO
VDDM
VDDM
VDDM
VDDM
VDD
VDDM
VDD
VDDIO VDDIO VDDIO VDDIO VDDIO
VDD
VDD
GND
VDD
VDDIO
VDDM
VDD
VDDM
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDIO
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDM
VDDM
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDM
VDD
VDDIO VDDIO
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
VDD
VDDM
VDDM
VDDM
VDD
G
H
J
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDM
VDD
GND
GND
GND
GND
GND
GND
GND
GND
VDDM
VDDM
VDD
GND
GND
VDDM
GND
D14
D10
D0
VDDIO VDDIO
VDDIO
HREQ HACK
GND
VDDIO VDDIO
K
L
HDS
HDDS
GND
GND
GND
VDDM
VDDM
VDDM
VDD
D8
GND
GND
VDDM
VDDIO VDDIO VDDIO
VDD
HRW
HCS1 HCS2
D3
D1
VDD
VDDM
VDDM
VDDM
VDDM
VDDM
VDDM
M
N
P
R
T
URXD UTXD
SDA
CLKIN
PORESET
TDO
GND
GND
GND
GND
GND
D5
D2
VSSPLL
VDDPLL
TEST0
VDD
VDDIO
VREF
SCL
TPSEL
EE0
D6
D17
D19
D20
D21
NC
D4
VDDIO VDDIO
D16
D18
D22
D23
A13
A12
A9
D7
VDDIO VDDIO
GND
VDDM
VDD
VDDIO VDDIO VDDIO VDDIO
HRESET TMS
NC
VDD
VDD
VDD
VDD
VDD
VDD
VDD
U
V
W
Y
TRST
TDI
TCK
NC
NC
GND
VDDM
GPIA24 GPIA22 GPID6 GPIA28 T1TD T1RFS T0TCK EVNT4 EVNT0
NC
BA0
NC
A2
A3
A5
A6
A4
A10
A11
A8
VDDM
H8BIT GPIA26 GPIA23 GPIA19 GPIA27 GDPD4 T1TFS T1RD T0TFS T0RFS EVNT2 EVNT1
GPIA25 GND GPIA21 GPIA20 GPID5 GPIA29 T1TCK T1RCK TOTD T0RD T0RCK EVNT3
A7
GND
VDDM
NMI
BA1
A0
A1
GND
Figure 3. MSC7112 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
5
Assignments
1.2
Signal List By Ball Location
Table 1 lists the signals sorted by ball number and configuration.
Table 1. MSC7112 Signals by Ball Designator
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
A1
GND
A2
GND
DQM1
DQS2
CK
A3
A4
A5
A6
CK
A7
GPIC7
GPIC4
GPIC2
GPOC7
GPOC4
GPOC2
HD15
HD12
HD10
HD7
A8
A9
A10
A11
A12
A13
A14
A15
A16 (1L44X)
A16 (1M88B)
A17
A18
A19
A20
B1
reserved
reserved
reserved
reserved
reserved
HD6
HD4
HD1
HD0
GND
NC
BM3
GPID8
GPOD7
reserved
NC
NC
NC
NC
V
DDM
B2
NC
CS0
B3
B4
DQM2
DQS3
DQS0
CKE
B5
B6
B7
B8
WE
B9
GPIC6
GPIC3
GPIC0
GPOC6
GPOC3
GPOC0
HD14
HD11
HD8
B10
B11
B12
B13
B14
B15 (1L44X)
reserved
reserved
HD5
HD2
NC
NC
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
6
Freescale Semiconductor
Pin Assignments
Table 1. MSC7112 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
B15 (1M88B)
B16
B17
B18
B19
B20
C1
BM2
GPID7
GPOD7
reserved
NC
NC
NC
NC
NC
D24
D30
D25
CS1
C2
C3
C4
C5
DQM3
DQM0
DQS1
RAS
C6
C7
C8
C9
CAS
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D1
GPIC5
GPIC1
GPOC5
GPOC1
HD13
HD9
HD3
reserved
NC
NC
NC
NC
NC
NC
NC
NC
V
DDM
D2
D28
D27
D3
D4
GND
D5
V
V
V
V
V
V
DDM
DDM
DDM
DDM
DDM
DDM
DDIO
DDIO
D6
D7
D8
D9
D10
D11
D12
V
V
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
7
Assignments
Table 1. MSC7112 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Hardware Controlled
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
Primary
Alternate
D13
D14
D15
D16
D17
D18
D19
D20
E1
V
V
V
V
DDIO
DDIO
DDIO
DDIO
V
DDC
NC
NC
NC
GND
D26
D31
E2
E3
E4
V
V
DDM
DDM
E5
E6
V
V
V
V
DDC
DDC
DDC
DDC
DDM
DDIO
DDIO
DDIO
DDIO
DDIO
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
F1
V
V
V
V
V
V
V
V
DDC
DDC
NC
NC
NC
V
DDM
F2
D15
F3
D29
F4
V
DDC
DDC
DDC
F5
V
V
F6
F7
GND
GND
GND
F8
F9
F10
V
DDM
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
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Freescale Semiconductor
Pin Assignments
Table 1. MSC7112 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
F11
F12
F13
F14
F15
F16
F17
F18
F19
F20
G1
V
DDM
GND
GND
GND
V
DDIO
V
DDC
DDC
V
NC
NC
NC
GND
D13
GND
G2
G3
G4
V
V
DDM
DDM
G5
G6
GND
GND
GND
GND
GND
GND
GND
GND
GND
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
H1
V
DDIO
DDIO
V
V
DDC
NC
NC
NC
D14
D12
D11
H2
H3
H4
V
DDM
DDM
H5
V
H6
GND
GND
GND
H7
H8
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
9
Assignments
Table 1. MSC7112 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
H9
H10
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
J1
GND
GND
GND
GND
GND
GND
V
DDIO
DDIO
V
V
DDC
NC
reserved
HA2
HA1
reserved
D10
J2
V
DDM
J3
D9
J4
V
DDM
DDM
DDM
J5
V
V
J6
J7
GND
GND
GND
GND
GND
GND
GND
GND
GND
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18 (1L44X)
J18 (1M88B)
J19
J20
K1
V
DDIO
V
DDC
reserved
reserved
HA3
GPIC11
GPOC11
HA3
HACK/HACK or HRRQ/HRRQ
HREQ/HREQ or HTRQ/HTRQ
HDSP
reserved
D0
GND
D8
K2
K3
K4
V
DDC
DDM
K5
V
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
10
Pin Assignments
Table 1. MSC7112 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
K6
K7
GND
GND
GND
GND
GND
GND
GND
GND
GND
K8
K9
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
L1
V
DDIO
DDIO
V
V
DDC
reserved
HA0
reserved
reserved
HDDS
HDS/HDS or HWR/HWR
D1
GND
D3
L2
L3
L4
V
DDC
DDM
L5
V
L6
GND
GND
GND
GND
GND
GND
GND
GND
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18 (1L44X)
L18 (1M88B)
L19
L20
M1
V
DDIO
DDIO
DDIO
V
V
V
DDC
reserved
HCS2/HCS2
HCS2/HCS2
GPIB11
GPOB11
reserved
reserved
HCS1/HCS1
HRW or HRD/HRD
D2
M2
V
DDM
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
11
Assignments
Table 1. MSC7112 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
M3
M4
D5
V
DDM
DDM
M5
V
M6
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
N1
V
V
DDC
DDC
GPIA14
IRQ15
IRQ3
IRQ2
GPOA14
GPOA12
GPOA13
SDA
UTXD
URXD
GPIA12
GPIA13
D4
D6
N2
N3
V
REF
DDM
DDM
DDM
N4
V
V
V
N5
N6
N7
GND
GND
GND
GND
GND
GND
GND
GND
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
V
DDIO
V
DDC
DDC
V
CLKIN
GPIA15
IRQ14
GPOA15
SCL
V
SSPLL
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
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Freescale Semiconductor
Pin Assignments
Table 1. MSC7112 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
P1
P2
D7
D17
D16
P3
P4
V
DDM
DDM
DDM
P5
V
V
P6
P7
GND
GND
GND
GND
GND
GND
GND
GND
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
R1
V
DDIO
DDIO
V
V
DDC
PORESET
TPSEL
V
DDPLL
GND
D19
D18
R2
R3
R4
V
V
V
DDM
DDM
DDM
R5
R6
R7
GND
R8
V
DDM
R9
GND
R10
R11
R12
R13
R14
R15
R16
R17
R18
V
DDM
GND
GND
V
DDIO
GND
V
DDIO
DDIO
V
V
DDC
TDO
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
13
Assignments
Table 1. MSC7112 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
R19
R20
T1
reserved
EE0/DBREQ
TEST0
V
DDM
T2
D20
D22
T3
T4
V
DDM
DDM
T5
V
T6
V
DDC
DDM
DDM
T7
V
V
T8
T9
V
DDC
DDM
DDM
DDIO
DDIO
DDIO
DDIO
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
U1
V
V
V
V
V
V
V
V
DDC
DDC
NC
TMS
HRESET
GND
U2
D21
U3
D23
U4
V
DDM
U5
V
V
V
V
V
V
V
V
V
V
V
V
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
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Freescale Semiconductor
Pin Assignments
Table 1. MSC7112 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Hardware Controlled
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
Primary
Alternate
U17
U18
U19
U20
V1
V
DDC
NC
TCK
TRST
V
DDM
V2
NC
A13
A11
A10
A5
V3
V4
V5
V6
V7
A2
V8
BA0
NC
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
reserved
EVNT0
EVNT4
T0TCK
T1RFS
T1TD
SWTE
GPIA16
IRQ12
IRQ6
GPOA16
GPOA8
GPOA4
GPOA0
GPOA28
GPOD6
GPOA22
GPOA24
GPIA8
GPIA4
GPIA0
GPIA28
IRQ1
IRQ11
IRQ17
reserved
reserved
reserved
reserved
GPID6
GPIA22
GPIA24
IRQ22
IRQ24
reserved
reserved
NC
TDI
GND
V
DDM
A12
A8
A7
A6
A3
NC
GPIA17
IRQ13
GPOA17
GPOC14
GPOA10
GPOA7
GPOA3
GPOA1
EVNT1
CLKO
BM0
GPIC14
EVNT2
T0RFS
T0TFS
T1RD
GPIA10
GPIA7
GPIA3
GPIA1
IRQ5
IRQ7
IRQ8
IRQ10
T1TFS
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
15
Assignments
Table 1. MSC7112 Signals by Ball Designator (continued)
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
W15
W16
W17
W18
W19
W20
Y1
GPID4
GPOD4
GPOA27
GPOA19
GPOA23
GPOA26
reserved
reserved
reserved
reserved
reserved
GPIA27
IRQ18
IRQ19
IRQ23
IRQ26
GPIA19
GPIA23
GPIA26
reserved
reserved
reserved
H8BIT
V
DDM
Y2
GND
A9
Y3
Y4
A1
Y5
A0
Y6
A4
Y7
BA1
Y8
reserved
GPIA11
NMI
reserved
Y9
BM1
GPIC15
GPOC15
GPOA11
GPOA9
GPOA6
GPOA5
GPOA2
GPOA29
GPOD5
GPOA20
GPOA21
EVNT3
T0RCK
T0RD
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
IRQ4
GPIA9
GPIA6
T0TD
GPIA5
GPIA2
GPIA29
IRQ0
IRQ9
T1RCK
T1TCK
IRQ16
reserved
reserved
reserved
reserved
GPID5
GPIA20
GPIA21
IRQ20
IRQ21
reserved
reserved
GND
GPIA25
IRQ25
GPOA25
reserved
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
16
Specifications
2
Specifications
This chapter covers power considerations, DC/AC electrical characteristics, and AC timing specifications. For additional
information, see the MSC711x Reference Manual.
Note: The MSC7112 electrical specifications are preliminary and many are from design simulations. These specifications
may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be
published after thorough characterization and device qualifications have been completed.
2.1
Maximum Ratings
CAUTION
This device contains circuitry protecting against damage
due to high static voltage or electrical fields; however,
normal precautions should be taken to avoid exceeding
maximum voltage ratings. Reliability is enhanced if unused
inputs are tied to an appropriate logic voltage level (for
example, either GND or V ).
DD
In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification
does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values
in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction.
Therefore, a “maximum” value for a specification never occurs in the same device with a “minimum” value for another
specification; adding a maximum to a minimum represents a condition that can never exist.
Table 2 describes the maximum electrical ratings for the MSC7112.
Table 2. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Core supply voltage
Memory supply voltage
PLL supply voltage
I/O supply voltage
Input voltage
V
V
1.5
V
V
DDC
DDM
4.0
1.5
V
V
DDPLL
V
–0.2 to 4.0
(GND – 0.2) to 4.0
4.0
V
DDIO
V
V
IN
Reference voltage
V
V
REF
Maximum operating temperature
T
105
°C
°C
°C
J
Minimum operating temperature
T
–40
A
Storage temperature range
T
–55 to +150
STG
Notes: 1. Functional operating conditions are given in Table 3.
2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond
the listed limits may affect device reliability or cause permanent damage.
3. Section 3.1, Thermal Design Considerations includes a formula for computing the chip junction temperature (T ).
J
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
17
ifications
2.2
Recommended Operating Conditions
Table 3 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed.
Table 3. Recommended Operating Conditions
Rating
Symbol
Value
Unit
Core supply voltage
Memory supply voltage
PLL supply voltage
V
V
1.14 to 1.26
2.38 to 2.63
1.14 to 1.26
3.14 to 3.47
1.19 to 1.31
V
V
V
V
V
DDC
DDM
V
DDPLL
I/O supply voltage
V
DDIO
Reference voltage
V
REF
Operating temperature range
T
maximum: 105
minimum: –40
°C
°C
J
T
A
2.3
Thermal Characteristics
Table 4 describes thermal characteristics of the MSC7112 for the MAP-BGA package.
Table 4. Thermal Characteristics for MAP-BGA Package
MAP-BGA 17 × 17 mm5
Characteristic
Symbol
Unit
Natural
200 ft/min
Convection
(1 m/s) airflow
1, 2
Junction-to-ambient
R
R
R
R
39
23
12
7
31
20
°C/W
°C/W
°C/W
°C/W
°C/W
θJA
θJA
θJB
θJC
1, 3
Junction-to-ambient, four-layer board
4
Junction-to-board
5
Junction-to-case
6
Junction-to-package-top
Ψ
2
JT
Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on
the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
Section 3.1, Thermal Design Considerations explains these characteristics in detail.
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
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Freescale Semiconductor
Specifications
2.4
DC Electrical Characteristics
This section describes the DC electrical characteristics for the MSC7112.
Note: The leakage current is measured for nominal voltage values must vary in the same direction (for example, both VDDIO
and VDDC vary by +2 percent or both vary by –2 percent).
Table 5. DC Electrical Characteristics
Characteristic
Symbol
Min
Typical
Max
Unit
Core and PLL voltage
V
1.14
1.2
1.26
V
DDC
V
DDPLL
1
DRAM interface I/O voltage
I/O voltage
V
2.375
3.135
2.5
3.3
2.625
3.465
V
V
DDM
V
DDIO
2
DRAM interface I/O reference voltage
V
0.49 × V
1.25
0.51 × V
DDM
V
REF
DDM
3
DRAM interface I/O termination voltage
Input high CLKIN voltage
VTT
V
– 0.04
V
V + 0.04
REF
V
REF
REF
REF
V
2.4
3.0
3.465
V + 0.3
DDM
V
IHCLK
DRAM interface input high I/O voltage
DRAM interface input low I/O voltage
V
V
+ 0.28
V
V
IHM
DDM
V
–0.3
GND
V
– 0.18
REF
V
ILM
Input leakage current, V = V
I
–1.0
—
0.09
—
1
µA
µA
µA
IN
DDIO
IN
V
input leakage current
I
5
1
REF
VREF
Tri-state (high impedance off state) leakage current,
= V
I
–1.0
0.09
OZ
V
IN
DDIO
Signal low input current, V = 0.4 V
I
–1.0
–1.0
2.0
0.09
0.09
3.0
0
1
1
µA
µA
V
IL
L
Signal high input current, V = 2.0 V
I
IH
H
Output high voltage, I = –2 mA, except open drain pins
V
—
OH
OH
Output low voltage, I = 5 mA
V
—
0.4
V
OL
OL
5
Typical core power
P
C
•
•
at 200 MHz
at 266 MHz (mask set 1M88B only)
—
—
222
293
—
—
mW
mW
Notes: 1. The value of V
at the MSC7112 device must remain within 50 mV of V
at the DRAM device at all times.
DDM
DDM
2.
V
must be equal to 50% of V
and track V
variations as measured at the receiver. Peak-to-peak noise must not
REF
DDM
DDM
exceed ±2% of the DC value.
is not applied directly to the MSC7112 device. It is the level measured at the far end signal termination. It should be equal
3.
V
TT
to V
. This rail should track variations in the DC level of V
.
REF
REF
4. Output leakage for the memory interface is measured with all outputs disabled, 0 V ≤ V
≤ V
.
DDM
OUT
5. The core power values were measured.using a standard EFR pattern at typical conditions (25°C, 200 MHz or 266 MHz, 1.2 V
core).
Table 6 lists the DDR DRAM capacitance.
Table 6. DDR DRAM Capacitance
Parameter/Condition
Symbol
Max
Unit
Input/output capacitance: DQ, DQS
Delta input/output capacitance: DQ, DQS
Note: These values were measured under the following conditions:
• V = 2.5 V ± 0.125 V
C
30
30
pF
pF
IO
C
DIO
DDM
• f = 1 MHz
• T = 25°C
A
• V
• V
= V
/2
OUT
OUT
DDM
(peak to peak) = 0.2 V
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
19
ifications
2.5
AC Timings
This section presents timing diagrams and specifications for individual signals and parallel I/O outputs and inputs. All AC
timings are based on a 30 pF load, except where noted otherwise, and a 50 Ω transmission line. For any additional pF, use the
following equations to compute the delay:
•
•
Standard interface: 2.45 + (0.054 × Cload) ns
DDR interface: 1.6 + (0.002 × Cload) ns
2.5.1
Clock and Timing Signals
The following tables describe clock signal characteristics. Table 7 shows the maximum frequency values for internal (core,
reference, and peripherals) and external (CLKO) clocks. You must ensure that maximum frequency values are not exceeded (see
for the allowable ranges when using the PLL).
Table 7. Maximum Frequencies
Maximum in MHz
Characteristic
Mask Set 1L44X
Mask Set 1M88B
Core clock frequency (CLOCK)
200
50
266
67
External output clock frequency (CLKO)
Memory clock frequency (CK, CK)
TDM clock frequency (TxRCK, TxTCK)
100
50
133
67
Table 8. Clock Frequencies in MHz
Max
Characteristic
Symbol
Min
Mask Set 1L44X
Mask Set 1M88B
CLKIN frequency
F
F
10
—
—
—
—
—
100
200
100
50
100
266
133
50
CLKIN
CLOCK frequency
CORE
CK, CK frequency
F
CK
TDMxRCK, TDMxTCK frequency
CLKO frequency
F
TDMCK
F
F
50
67
CKO
AHB/IPBus/APB clock frequency
100
133
BCK
Note:
The rise and fall time of external clocks should be 5 ns maximum
Table 9. System Clock Parameters
Min
Characteristic
Max
Unit
CLKIN frequency
CLKIN slope
10
—
—
—
100
5
MHz
ns
CLKIN frequency jitter (peak-to-peak)
CLKO frequency jitter (peak-to-peak)
1000
150
ps
ps
2.5.2
Configuring Clock Frequencies
This section describes important requirements for configuring clock frequencies in the MSC7112 device when using the PLL
block. To configure the device clocking, you must program four fields in the Clock Control Register (CLKCTL):
•
•
•
•
PLLDVF field. Specifies the PLL division factor. The output of the divider block is the input to the multiplier block.
PLLMLTF field. Specifies the PLL multiplication factor. The output from the multiplier block is the VCO.
RNG field. Selects the available PLL frequency range.
CKSEL field. Selects the source for the core clock.
There are restrictions on the frequency range permitted at the beginning of the multiplication portion of the PLL that affect the
allowable values for the PLLDVF and PLLMLTF fields. The following sections define these restrictions and provide guidelines
to configure the device clocking when using the PLL. Refer to the Clock and Power Management chapter in the MSC711x
Reference Manual for details on the clock programming model.
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
20
Freescale Semiconductor
Specifications
2.5.2.1
PLL Multiplier Restrictions
There are two restrictions for correct usage of the PLL block:
•
•
The input frequency to the PLL multiplier block (that is, the output of the divider) must be in the range 10.5–19.5 MHz.
The output frequency of the PLL multiplier must be in the range 300-600 MHz.
When programming the PLL for a desired output frequency using the PLLDVF, PLLMLTF, and RNG fields, you must meet
these constraints.
2.5.2.2
Division Factors and Corresponding CLKIN Frequency Range
The value of the PLLDVF field determines the allowable CLKIN frequency range, as shown in Table 10.
Table 10. CLKIN Frequency Ranges by Divide Factor Value
PLLDVF
Field Value
Divide
Factor
CLKIN Frequency Range
Comments
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
1
2
3
4
5
6
7
8
9
10.5 to 19.5 MHz
21 to 39 MHz
Pre-Division by 1
Pre-Division by 2
Pre-Division by 3
Pre-Division by 4
Pre-Division by 5
Pre-Division by 6
Pre-Division by 7
Pre-Division by 8
Pre-Division by 9
31.5 to 58.5 MHz
42 to 78 MHz
52.5 to 97.5 MHz
63 to 100 MHz
73.5 to 100 MHz
84 to 100 MHz
94.5 to 100 MHz
Note:
The maximum CLKIN frequency is 100 MHz. Therefore, the PLLDVF value must be in the range from 1–9.
2.5.2.3
Multiplication Factor Range
The multiplier block output frequency ranges depend on the input clock frequency as shown in Table 11.
Table 11. PLLMLTF Ranges
Multiplier Block (Loop) Output Range
Minimum PLLMLTF Value Maximum PLLMLTF Value
300 ≤ [Pre-Divided Clock × (PLLMLTF + 1)] ≤ 600 MHz
300/Pre-Divided Clock
600/Pre-Divided Clock
Note:
This table results from the allowed range for F
frequency of the Pre-Divided Clock.
. The minimum and maximum multiplication factors are dependent on the
Loop
2.5.2.4
Allowed Core Clock Frequency Range
The frequency delivered to the core, extended core, and peripheral depends on the value of the CLKCTRL[RNG] bit as shown
in Table 12.
Table 12. Fvco Frequency Ranges
CLKCTRL[RNG] Value
Allowed Range of Fvco
1
0
300 ≤ F
150 ≤ F
≤ 600 MHz
≤ 300 MHz
vco
vco
Note:
This table results from the allowed range for F , which is F
modified by CLKCTRL[RNG].
Loop
vco
This bit along with the CKSEL determines the frequency range of the core clock.
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
21
ifications
Table 13. Resulting Ranges Permitted for the Core Clock
Resulting
Division
Factor
Allowed Range
of Core Clock
CLKCTRL[CKSEL]
CLKCTRL[RNG]
Comments
11
11
01
01
1
0
1
0
1
2
2
4
Reserved
Reserved
150 ≤ Core_Clk ≤ 200 MHz
150 ≤ Core_Clk ≤ 200 MHz
75 ≤ Core_Clk ≤ 150 MHz
Limited by range of PLL
Limited by range of PLL
Limited by range of PLL
Note:
This table results from the allowed range for F
, which depends on clock selected via CLKCTRL[CKSEL].
OUT
2.5.2.5
Core Clock Frequency Range When Using DDR Memory
The core clock can also be limited by the frequency range of the DDR devices in the system. Table 14 summarizes this
restriction.
Table 14. Core Clock Ranges When Using DDR
Allowed Frequency
Range for DDR CK
Corresponding Range
for the Core Clock
DDR Type
Comments
DDR 200 (PC-1600)
DDR 266 (PC-2100)
DDR 333 (PC-2600)
83–100 MHz
83–133 MHz
83–150 MHz
166 ≤ core clock ≤ 200 MHz
166 ≤ core clock ≤ 266 MHz
166 ≤ core clock ≤ 300 MHz
Core limited to 2 × maximum DDR frequency
Core limited to 2 × maximum DDR frequency
Core limited to 2 × maximum DDR frequency
2.5.3
Reset Timing
The MSC7112 device has several inputs to the reset logic. All MSC7112 reset sources are fed into the reset controller, which
takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause
a reset. Table 15 describes the reset sources.
Table 15. Reset Sources
Name
Direction
Description
Power-on reset
(PORESET)
Input
Initiates the power-on reset flow that resets the MSC7112 and configures various attributes of the
MSC7112. On PORESET, the entire MSC7112 device is reset. SPLL and DLL states are reset,
HRESET is driven, the SC1400 extended core is reset, and system configuration is sampled. The
system is configured only when PORESET is asserted.
External Hard
reset (HRESET)
Input/ Output
Initiates the hard reset flow that configures various attributes of the MSC7112. While HRESET is
asserted, HRESET is an open-drain output. Upon hard reset, HRESET is driven and the SC1400
extended core is reset.
Software
watchdog reset
Internal
Internal
Internal
When the MSC7112 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
Bus monitor
reset
When the MSC7112 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
JTAG EXTEST,
CLAMP, or
When a Test Access Port (TAP) executes an EXTEST, CLAMP, or HIGHZ command, the TAP logic
asserts an internal reset signal that generates an internal soft reset sequence.
HIGHZ command
Table 16 summarizes the reset actions that occur as a result of the different reset sources.
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
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Freescale Semiconductor
Specifications
Table 16. Reset Actions for Each Reset Source
Power-On Reset
(PORESET)
Hard Reset
(HRESET)
Soft Reset
(SRESET)
Reset Action/Reset Source
External or
Internal (Software
Watchdog or Bus
Monitor)
JTAG Command:
EXTEST, CLAMP,
or HIGHZ
External only
Configuration pins sampled (refer to Section 2.5.3.1 for
details).
Yes
No
No
PLL and clock synthesis states Reset
HRESET Driven
Yes
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
Software watchdog and bus time-out monitor registers
Yes
Yes
Clock synthesis modules (STOPCTRL, HLTREQ, and
HLTACK) reset
Extended core reset
Yes
Yes
Yes
Yes
Yes
Yes
Peripheral modules reset
2.5.3.1
Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN cycles after
external power to the MSC7112 reaches at least 2/3 VDD
.
2.5.3.2
Reset Configuration
The MSC7112 has two mechanisms for writing the reset configuration:
•
•
From a host through the host interface (HDI16)
From memory through the I2C interface
Five signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the boot and
operating conditions:
•
•
•
•
BM[0–1]
SWTE
H8BIT
HDSP
2.5.3.3
Reset Timing Tables
Table 17 and Figure 4 describe the reset timing for a reset configuration write.
Table 17. Timing for a Reset Configuration Write
No.
Characteristics
Expression
Unit
1
2
Required external PORESET duration minimum
Delay from PORESET deassertion to HRESET deassertion
Timings are not tested, but are guaranteed by design.
16/F
clocks
clocks
CLKIN
521/F
CLKIN
Note:
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
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23
ifications
1
PORESET
Input
Configuration Pins
are sampled
PORESET
Internal
HRESET
Output(I/O)
2
Figure 4. Timing Diagram for a Reset Configuration Write
2.5.4
DDR DRAM Controller Timing
This section provides the AC electrical characteristics for the DDR DRAM interface.
2.5.4.1
DDR DRAM Input AC Timing Specifications
Table 18 provides the input AC timing specifications for the DDR DRAM interface.
Table 18. DDR DRAM Input AC Timing
Max
No.
Parameter
Symbol
Min
Unit
Mask Set
1L44X
Mask Set
1M88B
—
—
AC input low voltage
V
—
V
– 0.31
V – 0.31
REF
V
V
IL
REF
AC input high voltage
V
V
+ 0.31
V
+ 0.3
V
+ 0.3
IH
REF
DDM
DDM
201
Maximum Dn input setup skew relative to DQSn
input
—
—
1026
900
ps
202
Maximum Dn input hold skew relative to DQSn
input
—
—
386
900
ps
Notes: 1. Maximum possible skew between a data strobe (DQSn) and any corresponding bit of data (D[8n + {0...7}] if 0 ≤ n ≤ 7).
2. See Table 19 for t value.
CK
3. Dn should be driven at the same time as DQSn. This is necessary because the DQSn centering on the DQn data tenure is
done internally.
DQSn
202
202
D1
D0
Dn
201
201
Note: DQS centering is done internally.
Figure 5. DDR DRAM Input Timing Diagram
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
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Freescale Semiconductor
Specifications
2.5.4.2
DDR DRAM Output AC Timing Specifications
Table 19 and Table 20 list the output AC timing specifications and measurement conditions for the DDR DRAM interface.
Table 19. DDR DRAM Output AC Timing
Min
No.
200
204
Parameter
Symbol
Max
Unit
Mask Set
1L44X
Mask Set
1M88B
1
CK cycle time, (CK/CK crossing)
t
CK
•
•
100 MHz (DDR200)
133 MHz (DDR266)
10
1.0
7.52
—
—
ns
ns
Not applicable
An/RAS/CAS/WE/CKE output setup with respect to
CK
t
0.5 × t – 2250
0.5 × t – 1000
—
ps
DDKHAS
CK
CK
205
206
207
208
209
An/RAS/CAS/WE/CKE output hold with respect to CK
CSn output setup with respect to CK
t
t
0.5 × t – 1250
0.5 × t – 1000
—
—
ps
ps
ps
ps
ps
DDKHAX
CK
CK
0.5 × t – 2250
0.5 × t – 1000
DDKHCS
DDKHCX
DDKHMH
CK
CK
CSn output hold with respect to CK
t
0.5 × t – 1250
0.5 × t – 1000
—
CK
CK
2
CK to DQSn
t
–600
–600
600
—
3
Dn/DQMn output setup with respect to DQSn
t
0.25 × t
–
0.25 × t – 750
DDKHDS,
MCK
CK
t
1050
DDKLDS
3
210
Dn/DQMn output hold with respect to DQSn
t
0.25 × t – 1050
0.25 × t – 750
—
ps
DDKHDX,
CK
CK
t
DDKLDX
DDKHMP
DDKHME
4
211
212
DQSn preamble start
t
t
–0.25 × t
–0.25 × t
—
ps
ps
CK
CK
5
DQSn epilogue end
–600
–600
600
Notes: 1. All CK/CK referenced measurements are made from the crossing of the two signals ±0.1 V.
2. can be modified through the TCFG2[WRDD] DQSS override bits. The DRAM requires that the first write data strobe
t
DDKHMH
arrives 75–125% of a DRAM cycle after the write command is issued. Any skew between DQSn and CK must be considered
when trying to achieve this 75%–125% goal. The TCFG2[WRDD] bits can be used to shift DQSn by 1/4 DRAM cycle
increments. The skew in this case refers to an internal skew existing at the signal connections. By default, the CK/CK crossing
occurs in the middle of the control signal (An/RAS/CAS/WE/CKE) tenure. Setting TCFG2[ACSM] bit shifts the control signal
assertion 1/2 DRAM cycle earlier than the default timing. This means that the signal is asserted no earlier than 410 ps before
the CK/CK crossing and no later than 677 ps after the crossing time; the device uses 1087 ps of the skew budget (the interval
from –410 to +677 ps). Timing is verified by referencing the falling edge of CK. See Chapter 10 of the MSC711x Reference
Manual for details.
3. Determined by maximum possible skew between a data strobe (DQS) and any corresponding bit of data. The data strobe
should be centered inside of the data eye.
4. Please note that this spec is in reference to the DQSn first rising edge. It could also be referenced from CK(r), but due to
programmable delay of the write strobes (TCFG2[WRDD]), there pre-amble may be extended for a full DRAM cycle. For this
reason, we reference from DQSn.
5. All outputs are referenced to the rising edge of CK. Note that this is essentially the CK/DQSn skew in spec 208. In addition
there is no real “maximum” time for the epilogue end. JEDEC does not require this is as a device limitation, but simply for the
chip to guarantee fast enough write to read turn-around times. This is already guaranteed by the memory controller operation.
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
25
ifications
Figure 6 shows the DDR DRAM output timing diagram.
CK
CK
200
204
205
206
An
RAS
207
CAS
WE
CKE
DQMn
Write A0
NOOP
211
208
DQSn
Dn
212
209
209
D0
D1
210
210
Figure 6. DDR DRAM Output Timing Diagram
Figure 7 provides the AC test load for the DDR DRAM bus.
Output
VOUT
Z0 = 50 Ω
RL = 50 Ω
Figure 7. DDR DRAM AC Test Load
Table 20. DDR DRAM Measurement Conditions
Symbol
DDR DRAM
Unit
1
V
V
V
± 0.31 V
REF
V
V
TH
2
0.5 × V
OUT
DDM
Notes: 1. Data input threshold measurement point.
2. Data output measurement point.
2.5.5
TDM Timing
Table 21. TDM Timing
Expression
No.
Characteristic
Min
Max
Units
300
301
302
303
304
305
306
TDMxRCK/TDMxTCK
TC
20.0
8.0
8.0
3.0
3.5
2.0
4.0
—
—
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
TDMxRCK/TDMxTCK High Pulse Width
TDMxRCK/TDMxTCK Low Pulse Width
TDM all input Setup time
0.4 × TC
0.4 × TC
TDMxRD Hold time
TDMxTFS/TDMxRFS input Hold time
TDMxTCK High to TDMxTD output active
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
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26
Specifications
Units
Table 21. TDM Timing
Expression
No.
Characteristic
Min
Max
307
308
309
310
311
TDMxTCK High to TDMxTD output valid
TDMxTD hold time
—
2.0
—
14.0
—
ns
ns
ns
ns
ns
TDMxTCK High to TDMxTD output high impedance
TDMXTFS/TDMxRFS output valid
10.0
13.5
—
—
TDMxTFS/TDMxRFS output hold time
2.5
Notes: 1. Output values are based on 30 pF capacitive load.
2. Inputs are referenced to the sampling that the TDM is programmed to use. Outputs are referenced to the programming edge
they are programmed to use. Use of the rising edge or falling edge as a reference is programmable. Refer to the MSC711x
Reference Manual for details. TDMxTCK and TDMxRCK are shown using the rising edge.
300
302
301
304
TDMxRCK
TDMxRD
303
305
303
TDMxRFS
310
311
TDMxRFS (output)
Figure 8. TDM Receive Signals
300
302
301
TDMxTCK
309
308
307
306
TDMxTD
TDMxRCK
310
311
TDMxTFS (output)
TDMxTFS (input)
305
303
Figure 9. TDM Transmit Signals
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
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27
ifications
2.5.6
HDI16 Signals
Table 22. Host Interface (HDI16) Timing1, 2
Mask Set 1L44X
Mask Set 1M88B
Expression Value
Unit
No.
Characteristics3
Expression
Value
40 Host Interface Clock period
T
Note 1
T
Note 1
ns
HCLK
CORE
4
44a Read data strobe minimum assertion width
HACK read minimum assertion width
3.0 × T
1.5 × T
2.5 × T
Note 11 2.0 × T
+ 9.0 Note 11 ns
HCLK
HCLK
HCLK
CORE
4
4
44b Read data strobe minimum deassertion width
HACK read minimum deassertion width
Note 11
Note 11
1.5 × T
CORE
Note 11 ns
44c Read data strobe minimum deassertion width after “Last Data
2.5 × T
Note 11 ns
Note 11 ns
Note 11 ns
CORE
CORE
CORE
5,6
Register” reads , or between two consecutive CVR, ICR, or ISR
7
reads
5,6
HACK minimum deassertion width after “Last Data Register” reads
8
45 Write data strobe minimum assertion width
1.5 × T
Note 11
1.5 × T
HCLK
HACK write minimum assertion width
8
46 Write data strobe minimum deassertion width
HACK write minimum deassertion width after ICR, CVR and Data
5
Register writes
2.5 × T
Note 11
3.0
2.5 × T
HCLK
47 Host data input minimum setup time before write data strobe
8
deassertion
—
—
2.5
2.5
ns
ns
Host data input minimum setup time before HACK write deassertion
48 Host data input minimum hold time after write data strobe
8
deassertion
—
—
4.0
1.0
—
—
Host data input minimum hold time after HACK write deassertion
49 Read data strobe minimum assertion to output data active from high
4
impedance
HACK read minimum assertion to output data active from high
impedance
1.0
ns
4
50 Read data strobe maximum assertion to output data valid
HACK read maximum assertion to output data valid
(2.0 × T
) + 8.0 Note 11 (2.0 × T
) + 8.0 Note 11 ns
HCLK
CORE
51 Read data strobe maximum deassertion to output data high
4
impedance
—
8.0
—
9.0
ns
HACK read maximum deassertion to output data high impedance
4
52 Output data minimum hold time after read data strobe deassertion
Output data minimum hold time after HACK read deassertion
—
—
—
1.0
—
—
—
1.0
0.5
0.0
ns
ns
ns
4
53 HCS[1–2] minimum assertion to read data strobe assertion
0.0
8
54 HCS[1–2] minimum assertion to write data strobe assertion
0.0
55 HCS[1–2] maximum assertion to output data valid
(2.0 × T
(3.0 × T
) + 8.0 Note 11 (2.0 × T
) + 6.0 Note 11 ns
HCLK
CORE
9
56 HCS[1–2] minimum hold time after data strobe deassertion
—
0.0
—
0.5
5.0
5.0
ns
ns
ns
9
57 HA[0–3], HRW minimum setup time before data strobe assertion
—
—
5.0
5.0
—
—
9
58 HA[0–3], HRW minimum hold time after data strobe deassertion
61 Maximum delay from read data strobe deassertion to host request
) + 8.0 Note 11 (3.0 × T
) + 6.0 Note 11 ns
HCLK
CORE
4, 5, 10
deassertion for “Last Data Register” read
62 Maximum delay from write data strobe deassertion to host request
5,8,10
deassertion for “Last Data Register” write
(3.0 × T
(2.0 × T
(5.0 × T
) + 8.0 Note 11 (3.0 × T
) + 1.0 Note 11 (2.0 × T
) + 8.0 Note 11 (5.0 × T
) + 6.0 Note 11 ns
) + 1.0 Note 11 ns
) + 6.0 Note 11 ns
HCLK
HCLK
HCLK
CORE
CORE
CORE
63 Minimum delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) deassertion to HREQ assertion.
64 Maximum delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) assertion to HREQ deassertion
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
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28
Table 22. Host Interface (HDI16) Timing1, 2 (continued)
Mask Set 1L44X
Characteristics3
Mask Set 1M88B
Expression Value
Unit
No.
Expression
Value
Notes: 1.
T
= 2/ (Core Clock). At 200 MHz, T
= 10 ns. T
= core clock period. At 266 MHz, T
= 3.75 ns.
HCLK
HCLK
CORE
CORE
2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
3. = 3.3 V ± 0.15 V; T = –40°C to +105 °C, C = 30 pF for maximum delay timings and C = 0 pF for minimum delay timings.
V
DD
J
L
L
4. The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data strobe mode.
5. For 64-bit transfers, The “last data register” is the register at address 0x7, which is the last location to be read or written in data
transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian mode (HBE = 1).
6. This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers
without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ/HREQ signal.
7. This timing is applicable only if two consecutive reads from one of these registers are executed.
8. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
9. The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and host data strobe
(HDS/HDS) in the single data strobe mode.
10. The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and HTRQ/HTRQ in the double host
request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is deasserted only if HORX fifo is full
(treat as level Host Request).
11. Compute the value using the expression.
12. For mask set 1M88B, the read and write data strobe minimum deassertion width for non-”last data register” accesses in single
and dual data strobe modes is based on timings 57 and 58.
Figure 10 and Figure 11 show HDI16 read signal timing. Figure 12 and Figure 13 show HDI16 write signal
timing.
HA[0–3]
57
58
56
53
HCS[1–2]
57
58
HRW
HDS
44a
51
55
50
44c
52
49
HD[0–15]
61
HREQ (single host request)
HRRQ (double host request)
Figure 10. Read Timing Diagram, Single Data Strobe
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
29
HA[0–3]
57
58
56
53
HCS[1–2]
HRD
44a
51
55
44a
50
52
49
HD[0–15]
61
HREQ (single host request)
HRRQ (double host request)
Figure 11. Read Timing Diagram, Double Data Strobe
HA[0–3]
57
58
56
54
HCS[1–2]
HRW
57
58
45
HDS
46
47
48
HD[0–15]
62
HREQ (single host request)
HTRQ (double host request)
Figure 12. Write Timing Diagram, Single Data Strobe
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
30
HA[0–3]
57
58
56
54
HCS[1–2]
HWR
45
46
48
47
HD[0–15]
62
HREQ (single host request)
HTRQ (double host request)
Figure 13. Write Timing Diagram, Double Data Strobe
HREQ
(Output)
63
64
44a
44b
RX[0–3]
Read
HACK
50
51
49
52
Data
Valid
HD[0–15]
(Output)
Figure 14. Host DMA Read Timing Diagram, HPCR[OAD] = 0
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
31
HREQ
(Output)
63
64
46
45
TX[0–3]
Write
HACK
47
48
Data
Valid
HD[0–15]
(Input)
Figure 15. Host DMA Write Timing Diagram, HPCR[OAD] = 0
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
32
2
2.5.7
I C Timing
Table 23. I2C Timing
Fast
No.
Characteristic
Unit
Min
Max
450
451
452
453
454
455
456
457
458
459
460
Note:
SCL clock frequency
0
400
—
kHz
μs
μs
μs
μs
μs
ns
ns
ns
μs
μs
Hold time START condition
SCL low period
(Clock period/2) – 0.3
(Clock period/2) – 0.3
(Clock period/2) – 0.1
—
SCL high period
—
Repeated START set-up time (not shown in figure)
Data hold time
2 × 1/F
—
BCK
0
—
Data set-up time
250
—
SDA and SCL rise time
SDA and SCL fall time
Set-up time for STOP
—
700
300
—
—
(Clock period/2) – 0.7
(Clock period/2) – 0.3
Bus free time between STOP and START
—
SDA set-up time is referenced to the rising edge of SCL. SDA hold time is referenced to the falling edge of SCL. Load capacitance
on SDA and SCL is 400 pF.
453
458
3
457
Start Condition
Stop Condition
Start Condition
1
4
5
6
SCL
SDA
2
7
8
9
A
C
K
452
451
Data Byte
457
460
458
459
Start Condition
SCL
SDA
Data Byte
Figure 16. I2C Timing Diagram
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
33
2.5.8
UART Timing
Table 24. UART Timing
Expression
Mask Set
1L44X
Mask Set
1M88B
Unit
No.
Characteristics
Min
Max
Min
Max
—
—
Internal bus clock (APBCLK)
F
/2
—
10.0
160.0
—
100
—
—
5
—
7.52
120.3
—
133
—
—
5
MHz
ns
CORE
Internal bus clock period (1/APBCLK)
URXD and UTXD inputs high/low duration
URXD and UTXD inputs rise/fall time
UTXD output rise/fall time
T
APBCLK
400
401
402
16 × T
ns
APBCLK
ns
—
5
—
5
ns
401
401
UTXD, URXD
inputs
400
400
Figure 17. UART Input Timing
402
402
UTXD output
Figure 18. UART Output Timing
Table 25. EE0 Timing
2.5.9
EE Timing
Number
Characteristics
Type
Min
65
66
EE0 input to the core
EE0 output from the core
Asynchronous
4 core clock periods
1 core clock period
Synchronous to core clock
Notes: 1. The core clock is the SC1400 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.
2. Configure the direction of the EE pin in the EE_CTRL register (see the SC1400 Core Reference Manual for details.
3. Refer to Table 15 for details on EE pin functionality.
Figure 19 shows the signal behavior of the EE pin.
65
EE0 in
66
EE0 out
Figure 19. EE Pin Timing
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2.5.10 Event Timing
Table 26. EVNT Signal Timing
Type
Number
Characteristics
Min
67
68
EVNT as input
EVNT as output
Asynchronous
1.5 × APBCLK periods
1 APBCLK period
Synchronous to core clock
Notes: 1. Refer to Table 24 for a definition of the APBCLK period.
2. Direction of the EVNT signal is configured through the GPIO and Event port registers.
3. Refer to the MSC711x Reference Manual for details on EVNT pin functionality.
Figure 20 shows the signal behavior of the EVNT pin.
67
EVNT in
68
EVNT out
Figure 20. EVNT Pin Timing
2.5.11 GPIO Timing
Table 27. GPIO Signal Timing1,2,3
Number
Characteristics
Type
Min
4.5
5
601
602
603
604
GPI
Asynchronous
Synchronous to core clock
Asynchronous
1.5 × APBCLK periods
1 APBCLK period
GPO
Port A edge-sensitive interrupt
Port A level-sensitive interrupt
1.5 × APBCLK periods
6
Asynchronous
3 × APBCLK periods
Notes: 1. Refer to Table 24 for a definition of the APBCLK period.
2. Direction of the GPIO signal is configured through the GPIO port registers.
3. Refer to MSC711x Reference Manual for details on GPIO pin functionality.
4. GPI data is synchronized to the APBCLK internally and the minimum listed is the capability of the hardware to capture data
into a register when the GPA_DR is read. The specification is not tested due to the asynchronous nature of the input and
dependence on the state of the DSP core. It is guaranteed by design.
5. The input and output signals cannot toggle faster than 50 MHz.
6. Level-sensitive interrupts should be held low until the system determines (via the service routine) that the interrupt is
acknowledged.
Figure 21 shows the signal behavior of the GPI/GPO pin.
601
GPI
602
GPO
Figure 21. GPI/GPO Pin Timing
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2.5.12 JTAG Signals
Table 28. JTAG Timing
All frequencies
No.
Characteristics
Unit
Min
Max
700
701
702
703
704
705
706
707
708
709
710
711
712
Note:
TCK frequency of operation (1/(T × 3); maximum 22 MHz)
0.0
25.0
11.0
0.0
40.0
—
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
TCK cycle time
TCK clock pulse width measured at V
TCK rise and fall times
1.6 V
—
M =
3.0
—
Boundary scan input data set-up time
Boundary scan input data hold time
TCK low to output data valid
TCK low to output high impedance
TMS, TDI data set-up time
5.0
14.0
0.0
—
20.0
20.0
—
0.0
5.0
TMS, TDI data hold time
25.0
0.0
—
TCK low to TDO data valid
24.0
10.0
—
TCK low to TDO high impedance
TRST assert time
0.0
100.0
All timings apply to OCE module data transfers as the OCE module uses the JTAG port as an interface.
701
702
V
M
V
M
V
TCK
(Input)
IH
V
IL
703
703
Figure 22. Test Clock Input Timing Diagram
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V
TCK
(Input)
IH
V
IL
704
705
Data
Inputs
Input Data Valid
706
707
Data
Outputs
Output Data Valid
Data
Outputs
Figure 23. Boundary Scan (JTAG) Timing Diagram
V
IH
TCK
(Input)
V
IL
709
708
Input Data Valid
TDI
TMS
(Input)
710
TDO
(Output)
Output Data Valid
711
TDO
(Output)
Figure 24. Test Access Port Timing Diagram
TRST
(Input)
712
Figure 25. TRST Timing Diagram
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ware Design Considerations
3
Hardware Design Considerations
This section described various areas to consider when incorporating the MSC7112 device into a system design.
3.1
Thermal Design Considerations
An estimation of the chip-junction temperature, TJ, in °C can be obtained from the following:
TJ = TA + (R JA × PD)
Eqn. 1
θ
where
TA = ambient temperature near the package (°C)
R
JA = junction-to-ambient thermal resistance (°C/W)
θ
PD = PINT + PI/O = power dissipation in the package (W)
PINT = IDD × VDD = internal power dissipation (W)
PI/O = power dissipated from device on output pins (W)
The power dissipation values for the MSC7112 are listed in Table 4. The ambient temperature for the device is the air
temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC
standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the
value determined on a single layer board and the value obtained on a board with two planes. The value that more closely
approximates a specific application depends on the power dissipated by other components on the printed circuit board (PCB).
The value obtained using a single layer board is appropriate for tightly packed PCB configurations. The value obtained using a
board with internal planes is more appropriate for boards with low power dissipation (less than 0.02 W/cm2 with natural
convection) and well separated components. Based on an estimation of junction temperature using this technique, determine
whether a more detailed thermal analysis is required. Standard thermal management techniques can be used to maintain the
device thermal junction temperature below its maximum. If TJ appears to be too high, either lower the ambient temperature or
the power dissipation of the chip.
You can verify the junction temperature by measuring the case temperature using a small diameter thermocouple (40 gauge is
recommended) or an infrared temperature sensor on a spot on the device case. Use the following equation to determine TJ:
TJ = TT + (ΨJT × PD)
Eqn. 2
where
TT = thermocouple (or infrared) temperature on top of the package (°C)
JT = thermal characterization parameter (°C/W)
PD = power dissipation in the package (W)
Ψ
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Hardware Design Considerations
3.2
Power Supply Design Considerations
This section outlines the MSC7112 power considerations: power supply, power sequencing, power planes, decoupling, power
supply filtering, and power consumption. It also presents a recommended power supply design and options for low-power
consumption. For information on AC/DC electrical specifications and thermal characteristics, refer to Section 2.
3.2.1
Power Supply
The MSC7112 requires four input voltages, as shown in Table 29.
Table 29. MSC7112 Voltages
Symbol
Voltage
Value
Core
V
V
1.2 V
2.5 V
1.25 V
3.3 V
DDC
DDM
Memory
Reference
I/O
V
REF
V
DDIO
You should supply the MSC7112 core voltage via a variable switching supply or regulator to allow for compatibility with
possible core voltage changes on future silicon revisions. The core voltage is supplied with 1.2 V (+5% and –10%) across VDDC
and GND and the I/O section is supplied with 3.3 V (± 10%) across VDDIO and GND. The memory and reference voltages supply
the DDR memory controller block. The memory voltage is supplied with 2.5 V across VDDM and GND. The reference voltage
is supplied across VREF and GND and must be between 0.49 × VDDM and 0.51 × VDDM. Refer to the JEDEC standard JESD8
(Stub Series Terminated Logic for 2.5 Volts (STTL_2)) for memory voltage supply requirements.
3.2.2
Power Sequencing
One consequence of multiple power supplies is that the voltage rails ramp up at different rates when power is initially applied.
The rates depend on the power supply, the type of load on each power supply, and the way different voltages are derived. It is
extremely important to observe the power up and power down sequences at the board level to avoid latch-up, forward biasing
of ESD devices, and excessive currents, which all lead to severe device damage.
Note: There are five possible power-up/power-down sequence cases. The first four cases listed in the following sections are
recommended for new designs. The fifth case is not recommended for new designs and must be carefully evaluated
for current spike risks based on actual information for the specific application.
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
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ware Design Considerations
3.2.2.1
Case 1
The power-up sequence is as follows:
1. Turn on the VDDIO (3.3 V) supply first.
2. Turn on the VDDC (1.2 V) supply second.
3. Turn on the VDDM (2.5 V) supply third.
4. Turn on the VREF (1.25 V) supply fourth (last).
The power-down sequence is as follows:
1. Turn off the VREF (1.25 V) supply first.
2. Turn off the VDDM (2.5 V) supply second.
3. Turn off the VDDC (1.2 V) supply third.
4. Turn of the VDDIO (3.3 V) supply fourth (last).
Use the following guidelines:
•
•
Make sure that the time interval between the ramp-down of VDDIO and VDDC is less than 10 ms.
Make sure that the time interval between the ramp-up or ramp-down for VDDC and VDDM is less than 10 ms for
power-up and power-down.
•
Refer to Figure 26 for relative timing for power sequencing case 1.
Ramp-down
Ramp-up
VDDIO = 3.3 V
VDDM = 2.5 V
VREF = 1.25 V
VDDC = 1.2 V
<10 ms
<10 ms
<10 ms
<10 ms
Time
Figure 26. Voltage Sequencing Case 1
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Hardware Design Considerations
3.2.2.2
Case 2
The power-up sequence is as follows:
1. Turn on the VDDIO (3.3 V) supply first.
2. Turn on the VDDC (1.2 V) and VDDM (2.5 V) supplies simultaneously (second).
3. Turn on the VREF (1.25 V) supply last (third).
Note: Make sure that the time interval between the ramp-up of VDDIO and VDDC/VDDM is less than 10 ms.
The power-down sequence is as follows:
1. Turn off the VREF (1.25 V) supply first.
2. Turn off the VDDM (2.5 V) supply second.
3. Turn off the VDDC (1.2 V) supply third.
4. Turn of the VDDIO (3.3 V) supply fourth (last).
Use the following guidelines:
•
•
Make sure that the time interval between the ramp-down for VDDIO and VDDC is less than 10 ms.
Make sure that the time interval between the ramp-up or ramp-down for VDDC and VDDM is less than 10 ms for
power-up and power-down.
•
Refer to Figure 27 for relative timing for Case 2.
Ramp-down
Ramp-up
VDDIO = 3.3 V
VDDM = 2.5 V
VREF = 1.25 V
VDDC = 1.2 V
<10 ms
<10 ms
<10 ms
Time
Figure 27. Voltage Sequencing Case 2
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
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ware Design Considerations
3.2.2.3
Case 3
The power-up sequence is as follows:
1. Turn on the VDDIO (3.3 V) supply first.
2. Turn on the VDDC (1.2 V) supply second.
3. Turn on the VDDM (2.5 V) and VREF (1.25 V) supplies simultaneously (third).
Note: Make sure that the time interval between the ramp-up of VDDIO and VDDC is less than 10 ms.
The power-down sequence is as follows:
1. Turn off the VDDM (2.5 V) and VREF (1.25 V) supplies simultaneously (first).
2. Turn off the VDDC (1.2 V) supply second.
3. Turn of the VDDIO (3.3 V) supply third (last).
Use the following guidelines:
•
•
Make sure that the time interval between the ramp-down for VDDIO and VDDC is less than 10 ms.
Make sure that the time interval between the ramp-up or ramp-down time for VDDC and VDDM is less than 10 ms for
power-up and power-down.
•
Refer to Figure 28 for relative timing for Case 3.
Ramp-down
Ramp-up
VDDIO = 3.3 V
VDDM = 2.5 V
VREF = 1.25 V
VDDC = 1.2 V
<10 ms
<10 ms
<10 ms
<10 ms
Time
Figure 28. Voltage Sequencing Case 3
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Hardware Design Considerations
3.2.2.4
Case 4
The power-up sequence is as follows:
1. Turn on the VDDIO (3.3 V) supply first.
2. Turn on the VDDC (1.2 V), VDDM (2.5 V), and VREF (1.25 V) supplies simultaneously (second).
Note: Make sure that the time interval between the ramp-up of VDDIO and VDDC is less than 10 ms.
The power-down sequence is as follows:
1. Turn off the VDDC (1.2 V), VREF (1.25 V), and VDDM (2.5 V) supplies simultaneously (first).
2. Turn of the VDDIO (3.3 V) supply last.
Use the following guidelines:
•
Make sure that the time interval between the ramp-up or ramp-down time for VDDC and VDDM is less than 10 ms for
power-up and power-down.
•
Refer to Figure 29 for relative timing for Case 4.
Ramp-down
Ramp-up
VDDIO = 3.3 V
VDDM = 2.5 V
VREF = 1.25 V
VDDC = 1.2 V
<10 ms
<10 ms
Time
Figure 29. Voltage Sequencing Case 4
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ware Design Considerations
3.2.2.5
Case 5 (not recommended for new designs)
The power-up sequence is as follows:
1. Turn on the VDDIO (3.3 V) supply first.
2. Turn on the VDDM (2.5 V) supply second.
3. Turn on the VDDC (1.2 V) supply third.
4. Turn on the VREF (1.25 V) supply fourth (last).
Note: Make sure that the time interval between the ramp-up of VDDIO and VDDM is less than 10 ms.
The power-down sequence is as follows:
1. Turn off the VREF (1.25 V) supply first.
2. Turn off the VDDC (1.2 V) supply second.
3. Turn off the VDDM (2.5 V) supply third.
4. Turn of the VDDIO (3.3 V) supply fourth (last).
Use the following guidelines:
•
•
Make sure that the time interval between the ramp-down of VDDIO and VDDM is less than 10 ms.
Make sure that the time interval between the ramp-up or ramp-down for VDDC and VDDM is less than 2 ms for
power-up and power-down.
•
Refer to Figure 30 for relative timing for power sequencing case 5.
Ramp-down
Ramp-up
VDDIO = 3.3 V
VDDM = 2.5 V
VREF = 1.25 V
VDDC = 1.2 V
<2 ms
<2 ms
<10 ms
<10 ms
Time
Figure 30. Voltage Sequencing Case 5
Note: Cases 1, 2, 3, and 4 are recommended for system design. Designs that use Case 5 may have large current spikes on
the VDDM supply at startup and is not recommended for most designs. If a design uses case 5, it must accommodate
the potential current spikes. Verify risks related to current spikes using actual information for the specific application.
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Hardware Design Considerations
3.2.3
Power Planes
Each power supply pin (VDDC, VDDM, and VDDIO) should have a low-impedance path to the board power supply. Each GND pin
should be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on the device.
The MSC7112 VDDC power supply pins should be bypassed to ground using decoupling capacitors. The capacitor leads and
associated printed circuit traces connecting to device power pins and GND should be kept to less than half an inch per capacitor
lead. A minimum four-layer board that employs two inner layers as power and GND planes is recommended. See Section 3.5
for DDR Controller power guidelines.
3.2.4
Decoupling
Both the I/O voltage and core voltage should be decoupled for switching noise. For I/O decoupling, use standard capacitor
values of 0.01 μF for every two to three voltage pins. For core voltage decoupling, use two levels of decoupling. The first level
should consist of a 0.01 µF high frequency capacitor with low effective series resistance (ESR) and effective series inductance
(ESL) for every two to three voltage pins. The second decoupling level should consist of two bulk/tantalum decoupling
capacitors, one 10 μF and one 47 μF, (with low ESR and ESL) mounted as closely as possible to the MSC7112 voltage pins.
Additionally, the maximum drop between the power supply and the DSP device should be 15 mV at 1 A.
3.2.5
PLL Power Supply Filtering
The MSC7112 VDDPLL power signal provides power to the clock generation PLL. To ensure stability of the internal clock, the
power supplied to this pin should be filtered with capacitors that have low and high frequency filtering characteristics. VDDPLL
can be connected to VDDC through a 2 Ω resistor. VSSPLL can be tied directly to the GND plane. A circuit similar to the one
shown in Figure 31 is recommended. The PLL loop filter should be placed as closely as possible to the VDDPLL pin (which are
located on the outside edge of the silicon package) to minimize noise coupled from nearby circuits.The 0.01 µF capacitor should
be closest to VDDPLL, followed by the 0.1 µF capacitor, the 10 µF capacitor, and finally the 2-Ω resistor to VDDC. These traces
should be kept short.
2 Ω
VDDC
VDDPLL
0.1 µF 0.01 µF
10 µF
Figure 31. PLL Power Supply Filter Circuits
3.2.6
Power Consumption
You can reduce power consumption in your design by controlling the power consumption of the following regions of the device:
•
•
•
•
Extended core. Use the SC1400 Stop and Wait modes by issuing a stop or wait instruction.
Clock synthesis module. Disable the PLL, timer, watchdog, or DDR clocks or disable the CLKO pin.
AHB subsystem. Freeze or shut down the AHB subsystem using the GPSCTL[XBR_HRQ] bit.
Peripheral subsystem. Halt the individual on-device peripherals such as the DDR memory controller, HDI16, TDM,
UART, I2C, and timer modules.
For details, see the “Clocks and Power Management” chapter of the MSC711x Reference Manual.
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ware Design Considerations
3.2.7
Power Supply Design
One of the most common ways to derive power is to use either a simple fixed or adjustable linear regulator. For the system I/O
voltage supply, a simple fixed 3.3 V supply can be used. However, a separate adjustable linear regulator supply for the core
voltage VDDC should be implemented. For the memory power supply, regulators are available that take care of all DDR power
requirements.
Table 30. Recommended Power Supply Ratings
Supply
Symbol
Nominal Voltage
Current Rating
Core
V
V
1.2 V
2.5 V
1.25 V
3.3 V
1.5 A per device
0.5 A per device
10 µA per device
1.0 A per device
DDC
DDM
Memory
Reference
I/O
V
REF
V
DDIO
3.3
Estimated Power Usage Calculations
The following equations permit estimated power usage to be calculated for individual design conditions. Overall power is
derived by totaling the power used by each of the major subsystems:
PTOTAL = PCORE + PPERIPHERALS + PDDRIO + PIO + PLEAKAGE
This equation combines dynamic and static power. Dynamic power is determined using the generic equation:
C × V2 × F × 10–3 mW
Eqn. 3
Eqn. 4
where,
C = load capacitance in pF
V = peak-to-peak voltage swing in V
F = frequency in MHz
3.3.1
Core Power
Estimation of core power is straightforward. It uses the generic dynamic power equation and assumes that the core load
capacitance is 750 pF, core voltage swing is 1.2 V, and the core frequency is 200 MHz or 266 MHz. This yields:
PCORE = 750 pF × (1.2 V)2 × 200 MHz × 10–3 = 216 mW
Eqn. 5
Eqn. 6
P
CORE = 750 pF × (1.2 V)2 × 266 MHz × 10–3 = 287 mW
This equation allows for adjustments to voltage and frequency if necessary.
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Hardware Design Considerations
3.3.2
Peripheral Power
Peripherals include the DDR memory controller, DMA controller, HDI16, TDM, UART, timers, GPIOs, and the I2C module.
Basic power consumption by each module is assumed to be the same and is computed by using the following equation which
assumes an effective load of 20 pF, core voltage swing of 1.2 V, and a switching frequency of 100 MH or 133 MHz. This yields:
PPERIPHERAL = 20 pF × (1.2 V)2 × 100 MHz × 10–3 = 2.88 mW per peripheral
PERIPHERAL = 20 pF × (1.2 V)2 × 133 MHz × 10–3 = 3.83 mW per peripheral
Eqn. 7
Eqn. 8
P
Multiply this value by the number of peripherals used in the application to compute the total peripheral power consumption.
3.3.3
External Memory Power
Estimation of power consumption by the DDR memory system is complex. It varies based on overall system signal line usage,
termination and load levels, and switching rates. Because the DDR memory includes terminations external to the MSC7112
device, the 2.5 V power source provides the power for the termination, which is a static value of 16 mA per signal driven high.
The dynamic power is computed, however, using a differential voltage swing of ±0.200 V, yielding a peak-to-peak swing of 0.4
V. The equations for computing the DDR power are:
PDDRIO = PSTATIC + PDYNAMIC
Eqn. 9
PSTATIC = (unused pins × % driven high) × 16 mA × 2.5 V
Eqn. 10
PDYNAMIC = (pin activity value) × 20 pF × (0.4 V)2 × 200 MHz × 10–3 mW
Eqn. 11
PDYNAMIC = (pin activity value) × 20 pF × (0.4 V)2 × 266 MHz × 10–3 mW
Eqn. 12
Eqn. 13
pin activity value = (active data lines × % activity × % data switching) + (active address lines × % activity)
As an example, assume the following:
unused pins = 16 (DDR uses 16-pin mode)
% driven high = 50%
active data lines = 16
% activity = 60%
% data switching = 50%
active address lines = 3
In this example, the DDR memory power consumption is:
P
DDRIO = ((16 × 0.5) × 16 × 2.5) + (((16 × 0.6 × 0.5) + (3 × 0.6)) × 20 × (0.4)2 × 200 × 10–3) = 324.2 mW
Eqn. 14
Eqn. 15
PDDRIO = ((16 × 0.5) × 16 × 2.5) + (((16 × 0.6 × 0.5) + (3 × 0.6)) × 20 × (0.4)2 × 266 × 10–3) = 326.3 mW
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ware Design Considerations
3.3.4
External I/O Power
The estimation of the I/O power is similar to the computation of the peripheral power estimates. The power consumption per
signal line is computed assuming a maximum load of 20 pF, a voltage swing of 3.3 V, and a switching frequency of 25 MHz or
33 MHz, which yields:
PIO = 20 pF × (3.3 V)2 × 25 MHz × 10–3 = 5.44 mW per I/O line
IO = 20 pF × (3.3 V)2 × 33 MHz × 10–3 = 7.19 mW per I/O line
Multiply this number by the number of I/O signal lines used in the application design to compute the total I/O power.
Eqn. 16
Eqn. 17
P
Note: The signal loading depends on the board routing. For systems using a single DDR device, the load could be as low as
7 pF.
3.3.5
Leakage Power
The leakage power is for all power supplies combined at a specific temperature. The value is temperature dependent. The
observed leakage value at room temperature is 64 mW.
3.3.6
Example Total Power Consumption
Using the examples in this section and assuming four peripherals and 10 I/O lines active, a total power consumption value is
estimated as the following:
P
TOTAL (200 MHz core) = 216 + (4 × 2.88) + 324,2 + (10 × 5.44) + 64 = 670.12 mW
Eqn. 18
Eqn. 19
PTOTAL (266 MHz core) = 287 + (4 × 3.83) + 326.3 + (10 × 7.19) + 64 = 764.52 mW
3.4
Reset and Boot
This section describes the recommendations for configuring the MSC7112 at reset and boot.
3.4.1
Reset Circuit
HRESET is a bidirectional signal and, if driven as an input, should be driven with an open collector or open-drain device. For
an open-drain output such as HRESET, take care when driving many buffers that implement input bus-hold circuitry. The
bus-hold currents can cause enough voltage drop across the pull-up resistor to change the logic level to low. Either a smaller
value of pull-up or less current loading from the bus-hold drivers overcomes this issue. To avoid exceeding the MSC7112 output
current, the pull-up value should not be too small (a 1 KΩ pull-up resistor is used in the MSC711xADS reference design).
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Hardware Design Considerations
3.4.2
Reset Configuration Pins
Table 31 shows the MSC7112 reset configuration signals. These signals are sampled at the deassertion (rising edge) of
PORESET. For details, refer to the Reset chapter of the MSC711x Reference Manual.
Table 31. Reset Configuration Signals
Signal
Description
Settings
BM[1–0]
Determines boot mode.
0
Boot from HDI16 port.
Boot from I2C.
01
1x
0
Reserved.
SWTE
HDSP
H8BIT
Determines watchdog functionality.
Configures HDI16 strobe polarity.
Configures HDI16 operation mode.
Watchdog timer disabled.
Watchdog timer enabled.
Host Data strobes active low.
Host Data strobes active high.
1
0
1
0
HDI16 port configured for 16-bit operation.
HDI16 port configured for 8-bit operation.
1
3.4.3
Boot
After a power-on reset, the PLL is bypassed and the device is directly clocked from the CLKIN pin. Using this input
clock, the system initializes using the boot loader program that resides in the internal ROM. After initialization, the
DSP core can enable the PLL and start the device operating at a higher speed. The MSC7112 can boot from an
2
external host through the HDI16 or download a user program through the I C port. The boot operating mode is set
by configuring the BM[1–0] signals sampled at the rising edge of PORESET, as shown in Table 32.
Table 32. Boot Mode Settings
BM1
BM0
Boot Source
0
0
1
1
0
1
0
1
External host via HDI16 with the PLL disabled.
2
I C.
External host via the HDI16 with the PLL enabled.
Reserved.
3.4.3.1
HDI16 Boot
If the MSC7112 device boots from an external host through the HDI16, the port is configured as follows:
•
•
•
•
Operate in Non-DMA mode.
Operate in polled mode on the device side.
Operate in polled mode on the external host side.
External host must write four 16-bit values at a time with the first word as the most significant and the fourth word as
the least significant.
When booting from a power-on reset, the HDI16 is additionally configurable as follows:
•
•
8- or 16-bit mode as specified by the H8BIT pin.
Data strobe as specified by the HDSP and HDDS pins.
These pins are sampled only on the deassertion of power-on reset. During a boot from a hard reset, the configuration of these
pins is unaffected.
Note: When the HDI16 is used for booting or other purposes, bit 0 is the least significant bit and not the most significant bit
as for other DSP products.
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
49
ware Design Considerations
3.4.3.2
I2C Boot
When the MSC7112 device is configured to boot from the I2C port, the boot program configures the GPIO pins shared with the
I2C pins as I2C pins. The I2C interface is configured as follows:
•
•
I2C in master mode.
EPROM in slave mode.
For details on the boot procedure, see the “Boot Program” chapter of the MSC711x Reference Manual.
3.5
DDR Memory System Guidelines
MSC7112 devices contain a memory controller that provides a glueless interface to external double data rate (DDR) SDRAM
memory modules with Class 2 Series Stub Termination Logic 2.5 V (SSTL_2). There are two termination techniques, as shown
in Figure 32. Technique B is the most popular termination technique.
VTT
Generator
VTT
Controller
RS
DDR
Bank
DDR
Bank
RT
SSTL_2
SSTL_2
Address
Command
Chip Selects
Technique A
RS
RT
Data
Strobes
Mask
SSTL_2
VREF
VTT
Generator
Controller
RS
DDR
Bank
DDR
Bank
RT
SSTL_2
SSTL_2
Address
Command
Technique B
Chip Selects
RS
RT
Data
Strobes
Mask
SSTL_2
Figure 32. SSTL Termination Techniques
Figure 33 illustrates the power wattage for the resistors. Typical values for the resistors are as follows:
•
•
RS = 22 Ω
RT = 24 Ω
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
50
Freescale Semiconductor
Hardware Design Considerations
VTT
Driver
VDDQ
RT
Receiver
RS
VREF
VSS
Figure 33. SSTL Power Value
3.5.1
V
and V Design Constraints
REF TT
VTT and VREF are isolated power supplies at the same voltage, with VTT as a high current power source. This section outlines
the voltage supply design needs and goals:
•
•
Minimize the noise on both rails.
VTT must track variation in the VREF DC offsets. Although they are isolated supplies, one possible solution is to use a
single IC to generate both signals.
•
•
Both references should have minimal drift over temperature and source supply.
It is important to minimize the noise from coupling onto VREF as follows:
— Isolate VREF and shield it with a ground trace.
— Use 15–20 mm track.
— Use 20–30 mm clearance between other traces for isolating.
— Use the outer layer route when possible.
— Use distributed decoupling to localize transient currents and return path and decouple with an inductance less than
3 nH.
•
•
Max source/sink transient currents of up to 1.8 A for a 32-bit data bus.
Use a wide island trace on the outer layer:
— Place the island at the end of the bus.
— Decouple both ends of the bus.
— Use distributed decoupling across the island.
— Place SSTL termination resistors inside the VTT island and ensure a good, solid connection.
Place the VTT regulator as closely as possible to the termination island.
— Reduce inductance and return path.
•
— Tie current sense pin at the midpoint of the island.
3.5.2
Decoupling
The DDR decoupling considerations are as follows:
•
•
•
•
DDR memory requires significantly more burst current than previous SDRAMs.
In the worst case, up to 64 drivers may be switching states.
Pay special attention and decouple discrete ICs per manufacturer guidelines.
Leverage VTT island topology to minimize the number of capacitors required to supply the burst current needs of the
termination rail.
•
See the Micron DesignLine publication entitled Decoupling Capacitor Calculation for a DDR Memory Channel
(http://download.micron.com/pdf/pubs/designline/3Q00dl1-4.pdf).
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
51
ware Design Considerations
3.5.3
General Routing
The general routing considerations for the DDR are as follows:
•
All DDR signals must be routed next to a solid reference:
— For data, next to solid ground planes.
— For address/command, power planes if necessary.
•
•
All DDR signals must be impedance controlled. This is system dependent, but typical values are 50–60 ohm.
Minimize other cross-talk opportunities. As possible, maintain at least a four times the trace width spacing between all
DDR signals to non-DDR signals.
•
•
Keep the number of vias to a minimum to eliminate additional stubs and capacitance.
Signal group routing priorities are as follows:
— DDR clocks.
— Route MVTT/MVREF.
— Data group.
— Command/address.
•
Minimize data bit jitter by trace matching.
3.5.4
Routing Clock Distribution
The DDR clock distribution considerations are as follows:
•
DDR controller supports six clock pairs:
— 2 DIMM modules.
— Up to 36 discrete chips.
•
For route traces as for any other differential signals:
— Maintain proper difference pair spacing.
— Match pair traces within 25 mm.
Match all clock traces to within 100 mm.
Keep all clocks equally loaded in the system.
Route clocks on inner critical layers.
•
•
•
3.5.5
Data Routing
The DDR data routing considerations are as follows:
•
•
•
•
•
Route each data group (8-bits data + DQS + DM) on the same layer. Avoid switching layers within a byte group.
Take care to match trace lengths, which is extremely important.
To make trace matching easier, let adjacent groups be routed on alternate critical layers.
Pin swap bits within a byte group to facilitate routing (discrete case).
Tight trace matching is recommended within the DDR data group. Keep each 8-bit datum and its DM signal within ±
25 mm of its respective strobe.
•
Minimize lengths across the entire DDR channel:
— Between all groups maintain a delta of no more than 500 mm.
— Allows greater flexibility in the design for readjustments as needed.
DDR data group separation:
•
— If stack-up allows, keep DDR data groups away from the address and control nets.
— Route address and control on separate critical layers.
— If resistor networks (RNs) are used, attempt to keep data and command lines in separate packages.
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
52
Freescale Semiconductor
Ordering Information
3.6
Connectivity Guidelines
This section summarizes the connections and special conditions, such as pull-up or pull-down resistors, for the MSC7112
device. Following are guidelines for signal groups and configuration settings:
•
Clock and reset signals.
— SWTE is used to configure the MSC7112 device and is sampled on the deassertion of PORESET, so it should be
tied to VDDC or GND either directly or through pull-up or pull-down resistors until PORESET is deasserted. After
PORESET, this signal can be left floating.
— BM[0–1] configure the MSC7112 device and are sampled until PORESET is deasserted, so they should be tied to
VDDIO or GND either directly or through pull-up or pull-down resistors.
— HRESET should be pulled up.
Interrupt signals. When used, IRQ pins must be pulled up.
HDI16 signals.
•
•
— When they are configured for open-drain, the HREQ/HREQ or HTRQ/HTRQ signals require a pull-up resistor.
However, these pins are also sampled at power-on reset to determine the HDI16 boot mode and may need to be
pulled down. When these pins must be pulled down on reset and pulled up otherwise, a buffer can be used with
the HRESET signal as the enable.
— When the device boots through the HDI16, the HDDS, HDSP and H8BIT pins should be pulled up or down,
depending on the required boot mode settings.
•
•
I2C signals. The SCL and SDA signals, when programmed for I2C, requires an external pull-up resistor.
General-purpose I/O (GPIO) signals. An unused GPIO pin can be disconnected. After boot, program it as an output
pin.
•
Other signals.
— The TEST0 pin must be connected to ground.
— The TPSEL pin should be pulled up to enable debug access via the EOnCE port and pulled down for boundary
scan.
— Pins labelled NO CONNECT (NC) must not be connected.
— When a 16-pin double data rate (DDR) interface is used, the 16 unused data pins should be no connects (floating)
if the used lines are terminated.
— Do not connect DBREQ to DONE (as you would for the MSC8101 device). Connect DONE to one of the EVNT
pins, and DBREQ to HRRQ.
4
Ordering Information
Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.
Core
Frequency
(MHz)
Supply
Voltage
Pin
Count
Part
Package Type
Solder Spheres
Order Number
MSC7112
(mask
1L44X
1.2 V core
2.5 V mem.
3.3 V I/O
Molded Array Process-Ball Grid
Array (MAP-BGA)
400
400
200
Lead-free
Lead-bearing
Lead-free
MSC7112VM800
MSC7112VF800
MSC7112VM1000
MSC7112VF1000
MSC7112
(mask
1M88B)
1.2 V core
2.5 V mem
3.3 V I/O
Molded Array Process-Ball Grid
Array (MAP-BGA)
266
Lead-bearing
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
53
age Information
5
Package Information
Notes:
1. All dimensions in millimeters.
2. Dimensioning and tolerancing
per ASME Y14.5M–1994.
3. Maximum solder ball diameter
measured parallel to Datum A.
4. Datum A, the seating plane, is
determined by the spherical
crowns of the solder balls.
5. Parallelism measurement shall
exclude any effect of mark on
top surface of package.
CASE 1568-01
Figure 34. MSC7112 Mechanical Information, 400-pin MAP-BGA Package
6
Product Documentation
•
MSC711x Reference Manual (MSC711xRM). Includes functional descriptions of the extended cores and all the
internal subsystems including configuration and programming information.
•
•
Application Notes. Cover various programming topics related to the StarCore DSP core and the MSC7112 device.
SC140/SC1400 DSP Core Reference Manual. Covers the SC140 and SC1400 core architecture, control registers, clock
registers, program control, and instruction set.
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
54
Freescale Semiconductor
Revision History
7
Revision History
Table 33 provides a revision history for this data sheet.
Table 33. Document Revision History
Description
Revision
Date
0
1
2
Apr 2004
May 2004
Aug. 2004
•
•
Initial public release.
Added ordering information and new package options.
•
•
•
Updated clock parameter values.
Updated DDR timing specifications.
Updated I2C timing specifications.
3
4
Sep. 2004
Jan. 2005
•
•
•
Updated Figures 1-2 and 1-2 to correct HDSP and DBREQ.
Corrected EE0 port reference.
Updated ball location for HDSP.
•
•
Added signal HA3.
Updated absolute maximum ratings, DDR DRAM capacitance specifications, clock parameters, reset
timing, and TDM timing.
•
•
•
•
•
Added note for timing reference for I2C interface.
Expanded GPIO timing information.
Corrected pin T20 and K20 signal designation.
Corrected signal names to GPAO15 and IRQ2.
Expanded design guidelines in Chapter 4.
5
Mar. 2005
•
•
•
•
•
Updated features list.
Updated power specifications.
Changed CLKIN frequency range.
Added clock configuration information.
Updated JTAG timings.
6
7
8
Apr. 2005
Oct. 2005
Dec. 2005
•
•
•
Added recommended power supply ratings and updated equations to estimate power consumption.
Updated core and total power consumption examples.
Added information about signals GPIOA16, GPIOA17, GPIOA27, GPIOA28, and GPIOA29 to signal
description and pinout location lists.
9
Nov. 2006
Aug. 2007
•
•
•
Updated Reference Manual reference to MSC711x Reference Manual.
Updated arrows in Host DMA Writing Timing figure.
Updated boot overview.
10
•
•
•
Updated to new data sheet format. Reorganized and renumbered sections, figures, and tables.
Added a note to clarify the definition of TCK timing 700 in new Table 31.
The power-up and power-down sequences have been expanded to five possible design scenarios/cases.
These cases replace the previously recommended power-up/power-down sequence recommendations. The
section has been clarified by adding subsection headings.
11
Apr 2008
•
Change the PLL filter resistor from 20 Ω to 2 Ω in Section 3.2.5.
MSC7112 Low-Cost 16-bit DSP with DDR Controller Data Sheet, Rev. 11
Freescale Semiconductor
55
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Document Number: MSC7112
Rev. 11
4/2008
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