MSC7116VF800 [NXP]
IC,DSP,16-BIT,CMOS,BGA,400PIN,PLASTIC;
| 型号： | MSC7116VF800 |
| 厂家： | 
NXP |
| 描述： | IC,DSP,16-BIT,CMOS,BGA,400PIN,PLASTIC |
| 文件： | 总100页 (文件大小：1804K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MSC7116
Rev. 8, 12/2005
Freescale Semiconductor
Technical Data
MSC7116
Low-Cost DSP with DDR Controller and 10/100 Mbps Ethernet MAC
128
The MSC7116 device targets
high-bandwidth highly
computational DSP
M2 SRAM
(192 KB)
DMA
ASM2
128
AMDMA
64
JTAG Port
64
128
(32 ch)
JTAG
64
Boot ROM
(8 KB)
to IPBus
applications and is optimized
for Enterprise class packet
telephony applications,
providing a competitive price
per channel for voice over
packet systems.
ASEMI
64
External Bus
32
External
Memory
Interface
DSP
Extended
Core
from
IPBus
SC1400
Core
Trace
Buffer
(8 KB)
Host
HDI16
Port
Interface
(HDI16)
ASTH
64
32
TDM
Fetch
Unit
2 TDMs
ASAPB
32
RS-232
GPIO
Instruction
Cache
UART
GPIO
AMIC
APB
(16 KB)
What’s New?
Rev. 8 includes the following
changes:
128
64
AMEC
Extended
Core
Watchdog
Interface
•
All chapters were updated to
reflect the addition of mask set
1M88B. This change includes
signal descriptions, timing
specifications, pin-outs, and
power computations. Review
all chapters for changes.
Interrupts
PLL/Clock
Interrupt
Control
ASAPB
32
M1
SRAM
(192 KB)
PLL/Clock
ASM1
ASSB
32
128
64
System Control
to/from OCE
64 64
64
AMENT
32
P XAXB
Events
Event Port
to EMI
to DMA
Timers
I2C
to Crossbar
Ethernet
MAC
I2C
Note: The arrows show the
direction of the transfer.
IPBus
MII/RMII
Figure 1. MSC7116 Block Diagram
The MSC7116 device is a highly integrated DSP processor that contains the StarCore™ SC1400 core, 384 KB of SRAM
memory, 16 KB 16-way instruction cache, 8 KB boot ROM, two 128-channel time-division multiplexing (TDM) interfaces
with hardware support for µ/A-law decoding/encoding, a UART, a 32-channel DMA controller, a 16-bit host interface
(HDI16) to support an external host processor, a 10/100Base-T MII/RMII, a programmable interrupt controller (PIC), an I2C
interface, two 16-bit quad cascadable timers, GPIO signals, and an on-chip emulator (OCE) and an event port for enhanced
debug and system integration capability. The SC1400 core has four ALUs and performs at 1000 DSP million multiply-
accumulates per second (MMACS) with an internal 266 MHz clock at 1.2 V.
© Freescale Semiconductor, Inc., 2004, 2005. All rights reserved.
Table of Contents
Features...............................................................................................................................................................iii
Product Documentation ....................................................................................................................................viii
Chapter 1
Signals/Connections
1.1
1.2
1.3
1.4
1.5
1.6
1.7
Power ................................................................................................................................................................1-4
Ground ..............................................................................................................................................................1-4
Clock and Reset ................................................................................................................................................1-4
Memory Controller ...........................................................................................................................................1-5
Multiplexed I/O Signal Ports A–D ...................................................................................................................1-6
OCE Event and JTAG Test Access Port..........................................................................................................1-19
Reserved Signals.............................................................................................................................................1-19
Chapter 2
Specifications
2.1
2.2
2.3
2.4
2.5
Maximum Ratings.............................................................................................................................................2-1
Recommended Operating Conditions...............................................................................................................2-2
Thermal Characteristics....................................................................................................................................2-3
DC Electrical Characteristics............................................................................................................................2-4
AC Timings.......................................................................................................................................................2-5
Chapter 3
Chapter 4
Packaging
3.1
3.2
MAP-BGA Package..........................................................................................................................................3-1
MAP-BGA Package Mechanical Drawing.....................................................................................................3-29
Design Considerations
4.1
4.2
4.4
4.5
4.6
Thermal Design Considerations........................................................................................................................4-1
Power Supply Design Considerations...............................................................................................................4-2
Reset and Boot..................................................................................................................................................4-6
DDR Memory System Guidelines....................................................................................................................4-8
Connectivity Guidelines .................................................................................................................................4-11
Data Sheet Conventions
OVERBAR
Indicates a signal that is active when pulled low (For example, the RESET pin is active when
low.)
“asserted”
Means that a high true (active high) signal is high or that a low true (active low) signal is low
Means that a high true (active high) signal is low or that a low true (active low) signal is high
“deasserted”
Examples:
Signal/Symbol
Logic State
Signal State
Asserted
Voltage
PIN
V /V
True
IL OL
PIN
PIN
PIN
V
V
/V
False
True
False
Deasserted
Asserted
IH OH
/V
IH OH
V /V
Deasserted
IL OL
Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
MSC7116 Technical Data, Rev. 8
ii
Freescale Semiconductor
Features
Table 1 lists the features of the MSC7116 device.
Table 1. MSC7116 Features
Feature
Description
•
Up to 1000 MMACS using an internal 266 MHz clock at 1.2 V. A multiply-accumulate operation includes a
multiply-add instruction with the associated data move and pointer update.
4 data ALUs.
16 data registers, 40 bits each.
27 address registers, 32 bits each.
Hardware support for fractional and integer data types.
Very rich 16-bit wide orthogonal instruction set.
Up to six instructions executed in a single clock cycle.
Variable-length execution set (VLES) that can be optimized for code density and performance.
IEEE® Std. 1149.1™ JTAG port.
•
•
•
•
•
•
•
•
•
StarCore
SC1400 Core
On-chip emulator (OCE10) module with real-time debugging capabilities.
The high-performance extended core delivers up to 1000 MMACS using 4 ALUs running up to 266 MHz,
including:
•
•
•
•
•
•
SC1400 core processor.
192 KB multi-port SRAM (M1) accessed by the SC1400 core with no wait states.
16 KB, 16-way instruction cache (ICache).
Programmable instruction fetch unit.
Write buffer (4-entry).
Extended Core
Internal Memory
Extended core interface module.
The large internal memory space totals 408 KB:
•
•
•
192 KB of M1 memory.
16 KB ICache.
192 KB internal shared memory (M2), accessible from the SC1400 instruction fetch unit, extended core
interface, and DMA controller via the crossbar switch.
8 KB boot ROM accessible from the SC1400 core.
•
•
•
•
•
•
DDR memory controller.
Glueless interface to 133 MHz DDR-RAM.
14-bit external address bus, supporting up to 1 GB of external memory.
16- or 32-bit external data bus.
External Memory
Interface
Memory controller supports:
−Byte enables for 32-bit external data bus.
−Data pipeline to reduce data set-up time for synchronous devices.
Programmable modules include:
•
•
•
•
•
•
•
Crossbar switch.
DMA controller.
DDR controller.
IPBus
Clock synthesis module.
2
I C module.
System control unit.
Timers.
AHB-Lite crossbar switch, allowing parallel data transfers between four master ports and six slave ports,
where each port connects to an AHB-Lite bus.
Crossbar Switch
DMA Controller
Multi-channel DMA controller:
•
•
•
•
32 time-multiplexed channels.
Priority-based time-multiplexing between channels using 32 internal priority levels
Priorities can be fixed or round-robin.
A flexible channel configuration:
− All channels support all features.
− All channels connect to the slave ports on the crossbar.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
iii
Table 1. MSC7116 Features (Continued)
Feature
Description
External interfaces and control modules managed on the advanced peripheral bus (APB), including:
•
•
•
•
•
•
•
•
16-bit host interface (HDI16)
10/100Base-T MII/RMII Ethernet interface.
Two time-division multiplexing (TDM) modules, each supporting up to 128 channels.
RS-232 interface/universal asynchronous receiver/transmitter (UART).
External Interfaces
2
I C interface.
Two 16-bit quad cascadable timers
General-purpose input/output (GPIO) signals.
Interrupt controller to handle external interrupt functions (input and output).
Enhanced 16-bit wide interface provides a glueless connection to industry-standard microcontrollers,
Host Interface (HDI16) microprocessors, and DSPs. The HDI16 can also operate in 8-bit data bus mode and is fully compatible with
the DSP56300 HDI08 bus from the external host side.
Ethernet interface:
•
•
•
•
Designed to comply with IEEE Std. 802.3™, 802.3u™, 802.3x™, and 802.3ac™.
Internal receive and transmit FIFOs and a FIFO controller.
Direct access to internal memories via its own DMA controller.
Support for 10/100 Mbps media independent interfaces (MIIs) and 10/100 Mbps reduced media
independent interface (RMII).
Ethernet Interface
•
•
•
•
•
•
Full and half duplex operation.
Programmable maximum frame length.
Virtual local area network (VLAN) tag and priority support.
Retransmission of transmit FIFO following collision.
CRC generation and verification for inbound and outbound packets.
Address recognition including promiscuous, broadcast, individual address. hash/exact match, and multicast
hash match.
Two independent TDM modules, each with the following features:
•
Totally independent receive and transmit, each having one data line, one clock line, and one frame sync
line.
•
Frame sync line and clock line can be shared between receive and transmit within a single TDM or across
all TDMs.
•
•
•
•
•
•
•
•
•
•
Glueless interface to E1/T1 frames and MVIP, SCAS, and H.110 buses.
Hardware A-law/µ-law conversion
Up to 50 Mbps per TDM (50 MHz bit clock).
Maximum rate is 1/4 the core frequency.
Up to 128 channels.
Each channel can be programmed to be active or inactive.
8- or 16-bit word widths.
The TDM sync signals (TDMxTFS/TDMxRFS) can be configured as either input or output.
The TDM clock signals (TDMxTCK/TDMxRCK) can be configured as either input or output.
Frame sync and data signals can be programmed to be sampled either on the rising edge or on the falling
edge of the clock.
TDM Modules
•
•
•
Frame sync can be programmed as active low or active high.
Selectable delay (0–3 bits) between the Frame Sync signal and the beginning of the frame.
MSB or LSB first support.
MSC7116 Technical Data, Rev. 8
iv
Freescale Semiconductor
Table 1. MSC7116 Features (Continued)
Feature
Description
•
•
•
•
•
•
•
•
•
Two signals for transmit data and receive data.
No clock, asynchronous mode.
Full-duplex operation.
Standard mark/space non-return-to-zero (NRZ) format.
13-bit baud rate selection.
Programmable 8-bit or 9-bit data format.
Separately enabled transmitter and receiver.
Programmable transmitter output polarity.
Two receiver wake-up methods:
−Idle line wake-up.
−Address mark wake-up.
•
•
Separate receiver and transmitter interrupt requests.
Eight flags, the first five can generate interrupt request:
−Transmitter empty.
UART
−Transmission complete.
−Receiver full.
−Idle receiver input.
−Receiver overrun.
−Noise error.
−Framing error.
−Parity error.
Receiver framing error detection.
Hardware parity checking.
1/16 bit-time noise detection.
Maximum bit rate 5.0 Mbps.
Single-wire and loop operations.
•
•
•
•
•
•
•
•
•
•
2-wire serial interface through GPIO.
Filtered inputs for noise suppression.
Compatibility with I C bus standard up to 100 kbps for standard mode and up to 400 kbps for Fast mode.
Bidirectional Data Transfer Protocol.
Multiple-master operation that also allows any number of devices implementing the I C-master software
2
I2C Port
2
module to access the memory simultaneously at boot or any time.
2
•
Compatible with the I C-serial EEPROM access protocol, allowing memory access of up to one MB.
Two 16-bit quad cascadable timers, each with the following features:
•
•
•
•
•
•
•
Cyclic or one-shot.
Input clock polarity control.
Interrupt request when counting reaches a programmed threshold.
Pulse or level interrupts.
Dynamically updated programmed threshold.
Read counter any time.
Timers
Maximum rate is 1/4 the core frequency.
Bidirectional signal lines that either serve the peripherals or act as programmable I/O ports. Each port can be
programmed separately to serve up to two dedicated peripherals.
General-Purpose I/O
(GPIO) Port
Consolidates maskable interrupt and non-maskable interrupt sources.
Programmable
Interrupt Controller
(PIC)
•
•
Collects important signal devices.
Programmable combinations to provide triggering to internal device units including interrupts, breakpoints,
or wake-up from low-power stop mode.
Event Port
•
•
Lines can be configured to operate independently, be sequenced, or be enabled from an external source.
Can be used independently or with the OCE10 debug module.
•
•
•
•
•
•
Reset controller.
Clock controller module.
Hardware bus monitors for the MSC7116 buses.
Software watchdog timer function.
fieldBIST™ hardware health diagnostics that can be invoked at power-up or off-line via software.
Event port.
System Control
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
v
Table 1. MSC7116 Features (Continued)
Feature
Description
Generates up to 266 MHz clock for the SC1400 core and up to 133 MHz for the crossbar switch, DMA
channels, M2 memory, and other peripherals.
Internal PLL
•
•
•
Programmable low-power Stop and Wait modes.
Generation of all device clocks.
Halt and restart capability for on-chip peripherals.
Clock Synthesis
Module
•
•
•
Separate power supply for internal logic and I/O.
Low-power standby modes.
Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-
dependent).
Reduced Power
Dissipation
Detects and provides visibility into unlikely field failures for systems with high availability. The Freescale
unique fieldBIST ensures that the device:
•
•
•
Has structural integrity.
Operates at the rated speed.
Is free from reliability defects.
fieldBIST Hardware
Diagnostics
Diagnostics can report partial or complete device inoperability. fieldBIST resolution can pinpoint the following
uniquely:
•
•
•
6 memory blocks, including ROM
3 logic levels (top, extended core, and peripherals)
1 PLL
Simple JTAG interface allows easy integration to system firmware.
400 ball MAP-BGA:
•
•
•
17 × 17 mm.
0.8 mm pitch.
Pb-free or Pb-bearing packaging technology.
Packaging
Real-time operating systems (RTOS) that fully supports MSC7116 device architecture (multi-core, memory
hierarchy, ICache, timers, DMA, interrupts, peripherals):
•
•
•
•
•
•
•
High-performance and deterministic, delivering predictive response time.
Optimized to provide low interrupt latency with high data throughput.
Preemptive and priority-based multitasking.
Fully interrupt/event driven.
Small memory footprint.
Comprehensive set of APIs.
Fully supports MSC7116 DMA, interrupts, and timer schemes.
Distributed system support, enables transparent inter-task communications:
•
•
Messaging mechanism between tasks using mailboxes and semaphores.
Networking support; data transfer between tasks running inside and outside the device using networking
protocols.
•
Includes integrated device drivers for such peripherals as TDM, UART, and external buses.
Additional features:
•
•
Incorporates task debugging utilities integrated with compilers and vendors.
Board support package (BSP) for MSC7100 ADS.
Software Support
®
®
Metrowerks CodeWarrior Integrated Development Environment (IDE):
•
C/C++ compiler with in-line assembly. Enables the developer to generate highly optimized DSP code. It
translates code written in C/C++ into parallel fetch sets and maintains high code density.
SC1400 Core Simulator. Allows the user to run test code to emulate operation on the SC1400 core
processor.
•
•
•
•
•
Librarian. Enables the user to create libraries for modularity.
C libraries. A collection of C/C++ functions for the developer’s use.
Linker. Highly efficient linker to produce executables from object code.
Debugger. Seamlessly integrated real-time, non-intrusive multi-mode debugger that enables debugging of
highly optimized DSP algorithms. The developer can choose to debug in source code, assembly code, or
mixed mode.
•
Profiler. An analysis tool using a patented Binary Code Instrumentation (BCI) technique that enables the
developer to identify program design inefficiencies.
Boot options:
•
•
HDI16.
I C.
2
MSC7116 Technical Data, Rev. 8
vi
Freescale Semiconductor
Table 1. MSC7116 Features (Continued)
Feature
Description
•
•
•
•
Host debug through single JTAG connector supports both processors.
Two kinds of ADS configurations: one with the MSC7116 as the host CPU and one without a host CPU.
Big Flash memory for stand-alone applications.
Support for the following communications ports:
−10/100Base-T.
−T1/E1 TDM interface.
−H.110.
−Voice codec.
MetroWerks
Application
Development System
(ADS) Board
−RS-232.
−High-density (MICTOR) logic analyzer connectors to monitor MSC7116 signals
−6U CompactPCI form factor.
•
•
•
•
•
•
•
•
•
•
MSC7116 device.
Single 32-bit DDR memory.
2
256 KB I C EEPROM to boot the MSC7116 device.
OCE10 emulator/JTAG connector for debugging.
On-board 5 V power supply.
External power supply and cables.
Kit documentation.
Power indicators for 2.5 V, 3.3 V, and 5 V.
Hard-reset push-button to reset the MSC7116 device.
Support for the following communications ports:
−HDI16 host port interface header.
MetroWerks
Evaluation Module
(EVM) Kits
−10/100Base-T (RJ-45).
−T1/E1 TDM interface header.
−16-bit audio codec (3.5 mm jacks).
−RS-232 (UART port).
−Output header for timers, interrupts, and GPIOs.
Software support:
•
−MSC711xEVM includes full-featured CodeWarrior Development Studio for MSC711x.
−MSC711xEVMT includes evaluation copy of CodeWarrior Development Studio for MSC711x.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
vii
Product Documentation
The documents listed in Table 2 are required for a complete description of the MSC7116 device and are necessary
to design properly with the part. Documentation is available from a local Freescale distributor, a Freescale
semiconductor sales office, or a Freescale Semiconductor Literature Distribution Center. For documentation
updates, visit the Freescale DSP website. See the contact information on the back cover of this document.
Table 2. MSC7116 Documentation
Name
Description
Order Number
MSC7116
Technical Data
MSC7116 features list and physical, electrical, timing, and package
specifications
MSC7116
MSC711x
Detailed functional description of memory and peripheral configuration,
MSC711xRM
Reference Manual operation, and register programming
SC1000 Family
Processor Core
Reference Manual
Detailed description of the SC1000 family processor cores, including the
SC1400, and instruction set
10180
See the StarCore LLC website at
www.starcore-dsp.com
OCE10 On-Chip
Emulator
Reference Manual
Detailed description of the SC1000 family on-chip emulator.
10055
See the StarCore LLC website at
www.starcore-dsp.com
Application Notes Documents describing specific applications or optimized device operation
including code examples
See the MSC7116 product website
MSC7116 Technical Data, Rev. 8
viii
Freescale Semiconductor
Signals/Connections
1
The MSC7116 external signals are organized into functional groups. Table 1-1 lists the functional groups and the
number of signal connections in each group, and it references the table that gives a detailed listing of multiplexed
signals within each group.
Most MSC7116 external peripherals are configured through ports A–D. The port configuration registers allow
signal lines to be configured as software-controlled or hardware-controlled. If a signal is configured as software-
controlled, it can be further defined as an input or an output. For port A, some signals configured as inputs may be
configured as general-purpose signals or as maskable interrupt lines. If a signal is configured as hardware-
controlled, it has a special function supporting one of the peripheral interfaces (for example, the HDI16). Some
signals can also have an alternate hardware function (such as the CLKO signal). Figure 1-1 shows MSC7116
external signals organized by hardware-controlled function. Figure 1-2 shows the configuration combinations for
signals enabled through ports A–D.
Table 1-1. MSC7116 Functional Signal Groupings
Number of
Functional Group
Signal
Detailed Description
Connections
Power
125
96
3
Table 1-2 on page 1-4.
Ground
Table 1-3 on page 1-4.
Table 1-4 on page 1-4.
Table 1-5 on page 1-5
Clock and Reset
Memory Controller
64
Signals Configured through ports A–D:
• TDM[0–1]
• Ethernet
12
18
27
2
2
5
Table 1-6 on page 1-7
Table 1-7 on page 1-9
Table 1-8 on page 1-13
Table 1-9 on page 1-16
Table 1-10 on page 1-16
Table 1-11 on page 1-17
Table 1-12 on page 1-18
Table 1-13 on page 1-19
• Host Interface (HDI16)
2
• I C Interface
• UART Interface
• Event port
• Boot mode (BM[3–2]) for mask set 1M88B only
• Non-maskable interrupt (NMI)
2
1
Note:
Signals are grouped by the principal function, but individual signal
lines have alternate functions. For example, there are a total
possible 42 GPIOs for mask set 1L44X or 46 GPIOs for mask set
1M88B, but none of them have this as the principal function. See
Section 1.5 for details.
Debugging (JTAG Test Access Port and OCE module)
7
1
Table 1-14 on page 1-19
Table 1-15 on page 1-19
Reserved
No connect (NC)
37
Do not connect any line, component,
trace, or via to these pins.
Note: Although the package for this device uses ball connections, the connections are sometimes conventionally
referred to as pins.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
1-1
Signals/Connections
Hardware-Controlled
MSC7116
Primary
RMII
Alternate
MII
V
V
→ 42
→ 49
→ 32
1
1
1
1
1
↔ TXD0
↔ TXD1
↔ TXD2
↔ TXD3
↔ RXD0
TXD0
DDC
TXD1
DDM
DDIO
V
reserved
reserved
RXD0
reserved
reserved
Power
V
→
→
1
1
DDPLL
V
REF
1
1
1
↔ RXD1
↔ RXD2
↔ RXD3
RXD1
GND → 95
reserved
reserved
reserved
reserved
Gnds
V
→
1
SSPLL
Ethernet
Interface
1
1
1
1
1
1
1
1
1
1
↔ TXCLK
↔ TX_EN
↔ TX_ER
↔ RXCLK
↔ RX_DV
↔ RX_ER
← COL
← CRS
↔ MDC
↔ MDIO
REFCLK
TX_EN
reserved
reserved
CRS_DV
RX_ER
reserved
reserved
MDC
CLKIN →
PORESET →
HRESET →
1
1
1
Clock/
Reset
reserved
reserved
Reset
A[13–0] ← 14
BA[1–0] ←
D[31–0] ↔ 32
2
H8BIT
MDIO
DQM[3–0] ←
DQS[3–0] ↔
CK ←
4
4
1
1
1
1
1
1
2
4
8
8
2
1
↔ HA[3–0]
↔ HD[15–8]
↔ HD[7–0]
↔ HCS[1–2]
↔ HDDS
Memory
Controller
(SSTL2)
CK ←
CKE ←
RAS ←
CAS ←
Host
Single Strobe
↔ HRW
↔ HDS/HDS
Dual Strobe
HRD/HRD
HRW/HRW
Dual HREQ
Interface
(HDI16)
WE ←
1
1
CS[0–1] ←
Hardware-
Controlled
Single HREQ
1
1
↔ HREQ/HREQ HTRQ/HTRQ
HDSP
T0RCK ↔
T0RFS ↔
T0RD ↔
T0TCK ↔
T0TFS ↔
T0TD ↔
1
1
1
1
1
1
↔ HACK/HACK
HRRQ/HRRQ
1
1
↔ SCL
↔ SDA
I2C
TDM0
1
1
↔ URXD
↔ UTXD
UART
T1RCK ↔
T1RFS ↔
T1RD ↔
T1TCK ↔
T1TFS ↔
T1TD ↔
1
1
1
1
1
1
1
1
1
1
1
1
↔ EVENT0
↔ EVENT1
↔ EVENT2
↔ EVENT3
↔ EVENT4
↔ EE0/DBREQ
CLK0
TDM1
BM0
BM1
SWTE
Event
Port
TEST0 →
1
Reserved
NMI
1
← NMI
1
1
1
1
1
1
← TCK
← TDI
→ TDO
← TMS
← TRST
← TPSEL
TAP and
OCE
Module
Note:
For software-controlled functionality, see Figure 1-2. This figure does not include the 37 NC pins.
Figure 1-1. MSC7116 External Signals (Hardware-Controlled Functions)
MSC7116 Technical Data, Rev. 8
1-2
Freescale Semiconductor
Software Controlled (GPxCTL[x] = 0)
Hardware Controlled (GPxCTL[x] = 1)
Primary Function
Reset
Configuration
(sampled at
deassertion of
PORESET only)
Alternate Function
CHPCFG[PAS] = 1
CHPCFG[PDS] = 1
Port
Signal
GPI (Default)
GPxDDR[x] = 0
GPA_INTEN[x] = 0
Interrupt
GPxDDR[x] = 0
GPA_INTEN[x] = 1
CHPCFG[PAS] and CHPCFG[PDS] = 0
GPO
GPxDDR[x] = 1
Ethernet (MII or RMII)
PA29
PA28
PA27
PA26
PA25
PA24
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
PA15
PA14
PA13
PA12
PA11
PA10
PA9
GPIA29
GPIA28
GPIA27
GPIA26
GPIA25
GPIA24
GPIA23
GPIA22
GPIA21
GPIA20
GPIA19
reserved
GPIA17
GPIA16
GPIA15
GPIA14
GPIA13
GPIA12
GPIA11
GPIA10
GPIA9
IRQ18
IRQ17
IRQ16
IRQ26
IRQ25
IRQ24
IRQ23
IRQ22
IRQ21
IRQ20
IRQ19
NMI
IRQ13
IRQ12
IRQ14
IRQ15
IRQ2
IRQ3
IRQ4
IRQ5
reserved
IRQ6
IRQ7
reserved
IRQ0
IRQ1
IRQ8
GPOA29
GPOA28
GPOA27
GPOA26
GPOA25
GPOA24
GPOA23
GPOA22
GPOA21
GPOA20
GPOA19
reserved
GPOA17
GPOA16
GPOA15
GPOA14
GPOA13
GPOA12
GPOA11
GPOA10
GPOA9
RXD3 or reserved
TX_ER or reserved
TXD3 or reserved
RX_ER
RX_DV or CRS_DV
TX_EN
reserved
reserved
reserved
TXCLK or REFCLK
RXD0
RXD1
TXD0
TXD1
Event
Clock
CLKO
EVNT1
2
EVNT4
I C
SCL
SDA
SWTE
UART
URXD
UTXD
TDM0
T0RCK
T0RFS
T0RD
T0TCK
T0TFS
T0TD
PA8
PA7
PA6
PA5
PA4
PA3
GPIA8
GPIA7
GPIA6
GPIA5
GPIA4
GPIA3
GPOA8
GPOA7
GPOA6
GPOA5
GPOA4
GPOA3
TDM1
T1RCK
T1RFS
T1RD
PA2
PA1
PA0
GPIA2
GPIA1
GPIA0
IRQ9
IRQ10
IRQ11
GPOA2
GPOA1
GPOA0
T1TCK
T1TFS
T1TD
HDI16
PB14
PB13
PB12
PB11
PB10
PB9
PB8
PB7
PB6
PB5
reserved
reserved
reserved
reserved
reserved
reserved
HDDS
HDS or HWR
HRW or HRD
HCS2
1
1
GPIB11
GPOB11
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
GPIC15
GPIC14
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
reserved
GPOC15
GPOC14
reserved
HCS1
HACK or HRRQ
HREQ or HTRQ
HD7
HDSP
HD6
HD5
HD4
HD3
HD2
HD1
HD0
PB4
PB3
PB2
PB1
PB0
PC15
PC14
PC13
EVNT3
EVNT2
EVNT0
BM1
BM0
EE0/
PC12
PC11
PC10
PC9
PC8
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PD8
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
reserved
GPIC11
reserved
GPOC11
DBREQ
1
1
HA3
HA2
HA1
reserved
reserved
reserved
GPIC7
GPIC6
GPIC5
GPIC4
GPIC3
GPIC2
GPIC1
GPIC0
reserved
reserved
reserved
GPOC7
GPOC6
GPOC5
GPOC4
GPOC3
GPOC2
GPOC1
GPOC0
HA0
HD15
HD14
HD13
HD12
HD11
HD10
HD9
HD8
1
1
2
GPID8
GPID7
GPOD8
GPOD7
BM3
1
1
2
BM2
GPID6
GPID5
GPID4
reserved
reserved
reserved
reserved
GPOD6
GPOD5
GPOD4
reserved
reserved
reserved
reserved
RXD2 or reserved
RXCLK or reserved
TXD2 or reserved
MDIO
MDC
CRS or reserved
COL or reserved
reserved
reserved
reserved
H8BIT
Notes: 1. Mask set 1M88B. For mask set 1L44X, these signals are reserved.
2. Mask set 1M88B only. For mask set 1L44X, these signals are not implemented.
Figure 1-2. Port A–D Signal Configuration Diagram
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
1-3
Signals/Connections
1.1 Power
Table 1-2. Power Inputs
Signal Name
Description
V
Internal Logic Power
DDC
A dedicated well-regulated power source for the device core. Provide an extremely low impedance path to the V
power rail.
DDC
V
V
V
SSTL IO Driver Power
DDM
A dedicated power source for the DDR DRAM interface buffers. Provide adequate external decoupling capacitors.
Input/Output Power
DDIO
DDPLL
The power source for the I/O buffers. Provide adequate external decoupling capacitors.
System PLL Power
A dedicated well-regulated power for the system Phase Lock Loop (PLL). Provide an extremely low impedance path to
the V
power rail.
DDPLL
V
SSTL Reference Power
REF
A reference power level for the SSTL2 memory interface.
1.2 Ground
Table 1-3. Ground Connections
Signal Name
Description
GND
System Ground
An isolated common ground for the internal processing logic, I/O buffers, and the DDR DRAM interface buffers. Provide
adequate external decoupling capacitors.
V
System PLL Ground
SSPLL
An isolated ground for the system PLL. Provide an extremely low-impedance path to this ground.
1.3 Clock and Reset
Table 1-4. Clock and Reset Pin Definitions
Signal Name
Type
Description
CLKIN
Input
Input
Input/
Input Clock
Provides the primary clock source for the device.
PORESET
HRESET
Power-On Reset
When asserted, this line causes the MSC7116 device to enter the power-on reset state.
Hard Reset
Output
When asserted, this open-drain line causes the MSC7116 to enter the hard reset state.
Note:
Connect an external pull-up to this pin.
MSC7116 Technical Data, Rev. 8
1-4
Freescale Semiconductor
Memory Controller
1.4 Memory Controller
Refer to the memory controller chapter in the MC711x Reference Manual for details on configuring these signals.
To support DDR DRAM external memory, the memory controller uses SSTL2+ signal levels.
Table 1-5. Memory Controller Signals
Signal Name
Type
Description
A[13–0]
Output
Address Bus
The memory interface address bus used to connect to external memory devices.
BA[1–0]
D[31–0]
Output
Bank Address
Selects the DDR SDRAM bank.
Input/
Data Bus
Output
The MSC7116 device drives the bus during write cycles and the external memory drives the bus
during read cycles.
DQM[3–0]
DQS[3–0]
CK
Output
Input/Output
Output
Output
Output
Output
Output
Output
Output
DDR SDRAM DQM
Selects the specific byte lanes for DDR SDRAM devices.
DDR SDRAM DQS
Strobe for byte-lane data capture.
System Clock Out
The system bus clock.
CK
System Clock Out Inverted
The inverted system bus clock.
CKE
Clock Enable
When asserted, this signal enables the system bus clock for the DDR SDRAM.
RAS
Row Address Strobe
Connects to DDR SDRAM RAS input.
CAS
Column Address Strobe
Connects to DDR SDRAM CAS input.
WE
Write Enable
Connects to DDR SDRAM WE input.
CS[0–1]
Chip Select 0–1
Enables specific memory devices or peripherals connected to the bus.
Note: The address and data bit ordering for the MSC7116 device differs from the MSC810x ordering. For the
MSC7116 device, bit 0 is the least significant bit.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
1-5
Signals/Connections
1.5 Multiplexed I/O Signal Ports A–D
Most MSC7116 I/O signals are multiplexed through ports A–D as shown in Figure 1-2. The function of the signals
in this category depends on when the signals are used and how they are configured:
• Some configuration signals lines are sampled when the PORESET signal is deasserted. Pulling these signals up or
down at reset configures specific aspects of device operation after reset.
• After reset, individual signals are defined by the settings of the Port Configuration Registers, with the following
constraints:
—
Although the four port control registers are 32 bits wide, not all possible signal lines are implemented. The
four ports support the following number of signal lines:
Port A supports 29 GPI signals.
°
°
°
°
Port B does not support GPI signals for mask set 1L44x but supports 1 GPI signal for mask set 1M88B.
Port C supports 10 GPI signals for mask set 1L44X and 11 GPI signals for mask set 1M88B.
Port D supports 3 GPI signals for mask set 1L44X and 5 GPI signals for mask set 1M88B.
—
The default configuration after reset for all port signals is software-controlled, general-purpose input
(GPI), but this functionality is not implemented for all signals lines. Signal lines that cannot be defined as
GPI are reserved. The four ports support the following number GPI signals:
Port A supports 29 GPO signals.
°
°
°
°
Port B does not support GPO signals for mask set 1L44X but supports 1 GPO signal for mask set 1M88B.
Port C supports 10 GPO signals for mask set 1L44X and 11 GPO signals for mask set 1M88B.
Port D supports 3 GPO signals for mask set 1L44X and 5 GPO signals for mask set 1M88B.
—
—
Port A supports 27 maskable interrupts (IRQ[0–26]) and 1 non-maskable interrupt (NMI) inputs. The NMI input
line can only be used for this purpose and cannot be configured as any other signal. If the lines are
configured as interrupt inputs through the Port A Interrupt Enable Register, they are not available for the
other functions.
Leaving the port configuration for a signal line as software-controlled and changing the data direction to
output changes the signal to a general-purpose output (GPO). Selecting this configuration for a port A
signal disables the associated interrupt function if enabled by the Port A Interrupt Enable Register. The
four ports support the following number of GPO signals:
Port A supports 24 GPO signals.
Port B does not support GPO signals.
Port C supports 10 GPO signals.
Port D supports 3 GPO signals.
°
°
°
°
—
—
Changing the port configuration for a signal to hardware-controlled changes the signal functionality to the
hardware-controlled function. For port A signals, this configuration also disables any associated interrupt
function. The hardware-controlled function defines the individual signal for one of the supported
2
interfaces, including TDM0, TDM1, Ethernet, the host interface (HDI16), I C interface, UART (RS-232)
interface, or the event port. For proper operation, all the required signals in a specified interface must be
enabled through the port registers and configured correctly through the individual interface configuration
registers.
Ports A and D also have an alternate function for some signals. The ports must be configured as hardware-
controlled and the PAS and PDS bits in the CHPCFG register must be set to select the alternate
functionality. The alternate signals support a clock output signal. Selecting the alternate function disables
the specific signals used by the primary hardware-controlled function.
Note: Refer to the MC711x Reference Manual for details on configuring these signals.
MSC7116 Technical Data, Rev. 8
1-6
Freescale Semiconductor
Multiplexed I/O Signal Ports A–D
The following subsections describe the individual interfaces supported by the hardware-controlled options and
indicate the other signals that are multiplexed with the supported signals.
1.5.1 TDM[0–1] Interface
Table 1-6. TDM[0–1] Interface Signals
Pin
Type
Input
Description
GPIA11
General-Purpose Input A11 (default)
When configured through port A bit 11, performs as a general-purpose input.
IRQ4
Input
Interrupt Request 4
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA11
Output
General-Purpose Output A11
When configured through port A bit 11, performs as a general-purpose output.
T0RCK
GPIA10
Input/Output
Input
TDM0 Receive Clock
The receive clock for TDM0. See the MC711x Reference Manual for operation details.
General-Purpose Input A10 (default)
When configured through port A bit 10, performs as a general-purpose input.
IRQ5
Input
Interrupt Request 5
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA10
Output
General-Purpose Output A10
When configured through port A bit 10, performs as a general-purpose output.
T0RFS
GPIA9
Input/Output
Input
TDM0 Receive Frame Sync
The receive frame sync for TDM0. See the MC711x Reference Manual for operation details.
General-Purpose Input A9 (default)
When configured through port A bit 9, performs as a general-purpose input.
GPOA9
Output
General-Purpose Output A9
When configured through port A bit 9, performs as a general-purpose output.
T0RD
Input/Output
Input
TDM0 Receive Data
The receive data for TDM0. See the MC711x Reference Manual for operation details.
GPIA8
General-Purpose Input A8 (default)
When configured through port A bit 8, performs as a general-purpose input.
IRQ6
Input
Interrupt Request 6
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA8
Output
General-Purpose Output A8
When configured through port A bit 8, performs as a general-purpose output.
T0TCK
GPIA7
Input/Output
Input
TDM0 Transmit Clock
The transmit clock for TDM0. See the MC711x Reference Manual for operation details.
General-Purpose Input A7 (default)
When configured through port A bit 7, performs as a general-purpose input.
IRQ7
Input
Interrupt Request 7
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA7
T0TFS
Output
General-Purpose Output A7
When configured through port A bit 7, performs as a general-purpose output.
Input/Output
TDM0 Transmit Frame Sync
The transmit frame sync for TDM0. See the MC711x Reference Manual for operation details.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
1-7
Signals/Connections
Table 1-6. TDM[0–1] Interface Signals (Continued)
Pin
Type
Description
GPIA6
Input
General-Purpose Input A9 (default)
When configured through port A bit 6, performs as a general-purpose input.
GPOA6
Output
General-Purpose Output A6
When configured through port A bit 6, performs as a general-purpose output.
T0TD
Input/Output
Input
TDM0 Transmit Data
The transmit data for TDM0. See the MC711x Reference Manual for operation details.
GPIA5
General-Purpose Input A5 (default)
When configured through port A bit 5, performs as a general-purpose input.
IRQ0
Input
Interrupt Request 0
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA5
Output
General-Purpose Output A5
When configured through port A bit 5, performs as a general-purpose output.
T1RCK
GPIA4
Input/Output
Input
TDM1 Receive Clock
The receive clock for TDM1. See the MC711x Reference Manual for operation details.
General-Purpose Input A4 (default)
When configured through port A bit 4, performs as a general-purpose input.
IRQ1
Input
Interrupt Request 1
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA4
Output
General-Purpose Output A4
When configured through port A bit 4, performs as a general-purpose output.
T1RFS
GPIA3
Input/Output
Input
TDM1 Receive Frame Sync
The receive frame sync for TDM1. See the MC711x Reference Manual for operation details.
General-Purpose Input A3 (default)
When configured through port A bit 3, performs as a general-purpose input.
IRQ8
Input
Interrupt Request 8
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA3
Output
General-Purpose Output A3
When configured through port A bit 3, performs as a general-purpose output.
T1RD
Input/Output
Input
TDM1 Receive Data
The receive data for TDM1. See the MC711x Reference Manual for operation details.
GPIA2
General-Purpose Input A2 (default)
When configured through port A bit 2, performs as a general-purpose input.
IRQ9
Input
Interrupt Request 9
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA2
T1TCK
Output
General-Purpose Output A2
When configured through port A bit 2, performs as a general-purpose output.
Input/Output
TDM1 Transmit Clock
The transmit clock for TDM1. See the MC711x Reference Manual for operation details.
MSC7116 Technical Data, Rev. 8
1-8
Freescale Semiconductor
Multiplexed I/O Signal Ports A–D
Table 1-6. TDM[0–1] Interface Signals (Continued)
Pin
Type
Input
Description
GPIA1
General-Purpose Input A1 (default)
When configured through port A bit 1, performs as a general-purpose input.
IRQ10
Input
Interrupt Request 10
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA1
Output
General-Purpose Output A1
When configured through port A bit 1, performs as a general-purpose output.
T1TFS
GPIA0
Input/Output
Input
TDM1 Transmit Frame Sync
The transmit frame sync for TDM1. See the MC711x Reference Manual for operation details.
General-Purpose Input A9 (default)
When configured through port A bit 6, performs as a general-purpose input.
IRQ11
GPOA0
T1TD
Input
Interrupt Request 11
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
Output
General-Purpose Output A0
When configured through port A bit 0, performs as a general-purpose output.
Input/Output
TDM1 Transmit Data
The transmit data for TDM1. See the MC711x Reference Manual for operation details.
1.5.2 Ethernet Interface
Table 1-7. Ethernet Interface Signals
Pin
Data Flow
Description
GPIA20
Input
General-Purpose Input A20 (default)
When configured through port A bit 20, performs as a general-purpose input.
IRQ20
Input
Interrupt Request 20
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA20
Output
General-Purpose Output A20
When configured through port A bit 20, performs as a general-purpose output.
TXD0
Output
Input
Transmit Data 0
MII and RMII transmit data bit 0. See the MC711x Reference Manual for operation details.
GPIA19
General-Purpose Input A19 (default)
When configured through port A bit 19, performs as a general-purpose input.
IRQ19
GPOA19
TXD1
Input
Interrupt Request 19
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
Output
Output
General-Purpose Output A19
When configured through port A bit 19, performs as a general-purpose output.
Transmit Data 1
MII and RMII transmit data bit 1. See the MC711x Reference Manual for operation details.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
1-9
Signals/Connections
Table 1-7. Ethernet Interface Signals
Pin
Data Flow
Description
GPID4
Input
General-Purpose Input D4 (default)
When configured through port D bit 4, performs as a general-purpose input.
GPOD4
TXD2
Output
Output
General-Purpose Output D4
When configured through port D bit 4, performs as a general-purpose output.
Transmit Data 2
MII transmit data bit 2. For RMII mode, this signal is reserved. See the MC711x Reference Manual
for operation details.
Reserved
GPIA27
Input/Output
Input
Reserved D4 (alternate hardware function)
When configured through port D bit 4, a reserved signal.
General-Purpose Input A27 (default)
When configured through port A bit 27, performs as a general-purpose input.
IRQ19
GPOA27
TXD3
Input
Interrupt Request 16
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
Output
Output
General-Purpose Output A27
When configured through port A bit 27, performs as a general-purpose output.
Transmit Data 3
MII transmit data bit 3. For RMII mode, this signal is reserved. See the MC711x Reference Manual
for operation details.
Reserved
GPIA22
Input/Output
Input
Reserved A27 (alternate hardware function
When configured through port A bit 27, a reserved signal.
General-Purpose Input A22 (default)
When configured through port A bit 22, performs as a general-purpose input.
IRQ22
Input
Interrupt Request 22
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA22
Output
General-Purpose Output A22
When configured through port A bit 22, performs as a general-purpose output.
RXD0
Input
Input
Receive Data 0
MII and RMII receive data bit 0. See the MC711x Reference Manual for operation details.
GPIA21
General-Purpose Input A21 (default)
When configured through port A bit 21, performs as a general-purpose input.
IRQ21
Input
Interrupt Request 21
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA21
RXD1
Output
Input
General-Purpose Output A21
When configured through port A bit 21, performs as a general-purpose output.
Receive Data 1
MII and RMII receive data bit 1. See the MC711x Reference Manual for operation details.
MSC7116 Technical Data, Rev. 8
1-10
Freescale Semiconductor
Multiplexed I/O Signal Ports A–D
Table 1-7. Ethernet Interface Signals
Pin
Data Flow
Description
GPID6
Input
General-Purpose Input D6 (default)
When configured through port D bit 6, performs as a general-purpose input.
GPOD6
RXD2
Output
Input
General-Purpose Output D6
When configured through port D bit 6, performs as a general-purpose output.
Receive Data 2
MII receive data bit 2. For RMII mode, this signal is reserved. See the MC711x Reference Manual
for operation details.
Reserved
GPIA29
Input/Output
Input
Reserved D6 (alternate hardware function)
When configured through port D bits, this signal is reserved.
General-Purpose Input A29 (default)
When configured through port A bit 29, performs as a general-purpose input.
IRQ18
Input
Interrupt Request 18
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA29
RXD3
Output
Input
General-Purpose Output A29
When configured through port A bit 29, performs as a general-purpose output.
Receive Data 3
MII receive data bit 3. For RMII mode, this signal is reserved. See the MC711x Reference Manual
for operation details.
Reserved
GPIA23
Input/Output
Input
Reserved A29 (alternate hardware function)
When configured through port A bit 29, a reserved signal.
General-Purpose Input A23 (default)
When configured through port A bit 23, performs as a general-purpose input.
IRQ23
Input
Interrupt Request 23
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA23
TXCLK
Output
Input
General-Purpose Output A23
When configured through port A bit 23, performs as a general-purpose output.
Transmit Clock
MII transmit clock. See the MC711x Reference Manual for operation details.
REFCLK
GPIA24
Input
Input
Reference Clock
RMII reference clock. See the MC711x Reference Manual for operation details.
General-Purpose Input A24 (default)
When configured through port A bit 24, performs as a general-purpose input.
IRQ24
Input
Interrupt Request 24
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA24
TX_EN
Output
Output
General-Purpose Output A24
When configured through port A bit 24, performs as a general-purpose output.
Transmit Data Valid
MII and RMII transmit data valid. See the MC711x Reference Manual for operation details.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
1-11
Signals/Connections
Table 1-7. Ethernet Interface Signals
Pin
Data Flow
Description
GPIA28
Input
General-Purpose Input A28 (default)
When configured through port A bit 28, performs as a general-purpose input.
IRQ17
Input
Interrupt Request 17
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA28
TX_ER
Output
Output
General-Purpose Output A28
When configured through port A bit 28, performs as a general-purpose output.
Transmit Error
MII transmit error. For RMII mode, this signal is reserved. See the MC711x Reference Manual for
operation details.
Reserved
GPID5
Input/Output
Input
Reserved A28 (alternate hardware function)
When configured through port A bit 28, a reserved signal.
General-Purpose Input D5 (default)
When configured through port D bit 5, performs as a general-purpose input.
GPOD5
RXCLK
Output
Input
General-Purpose Output D5
When configured through port D bit 5, performs as a general-purpose output.
Receive Clock
MII receive clock. For RMII mode, this signal is reserved. See the MC711x Reference Manual for
operation details.
Reserved
GPIA25
Input/Output
Input
Reserved D5 (alternate hardware function)
When configured through port D bit 5, a reserved signal.
General-Purpose Input A25 (default)
When configured through port A bit 25, performs as a general-purpose input.
IRQ25
Input
Interrupt Request 25
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA25
RX_DV
Output
Input
General-Purpose Output A25
When configured through port A bit 25, performs as a general-purpose output.
Receive Data Valid
MII receive data valid. See the MC711x Reference Manual for operation details.
CRS_DV
GPIA26
Input
Input
Carrier Sense/Receive Data Valid
RMII carrier sense/receive data valid. See the MC711x Reference Manual for operation details.
General-Purpose Input A26 (default)
When configured through port A bit 26, performs as a general-purpose input.
IRQ26
Input
Interrupt Request 26
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA26
Output
General-Purpose Output A26
When configured through port A bit 26, performs as a general-purpose output.
RX_ER
Input
Input
Receive Error
MII and RMII receive error. See the MC711x Reference Manual for operation details.
Reserved
Reserved D0 (default)
When configured through port D bit 0, a reserved signal.
COL
Input
Collision
MII collision. In RMII mode, this signal is reserved. See the MC711x Reference Manual for
operation details.
MSC7116 Technical Data, Rev. 8
1-12
Freescale Semiconductor
Multiplexed I/O Signal Ports A–D
Table 1-7. Ethernet Interface Signals
Pin
Data Flow
Description
Reserved
Input
Reserved D1 (default)
When configured through port D bit 1, a reserved signal.
CRS
Input
Carrier Sense
MII carrier sense. In RMII mode, this signal is reserved. See the MC711x Reference Manual for
operation details.
Reserved
MDC
Input
Reserved D2 (default)
When configured through port D bit 2, a reserved signal.
Output
Management Clock
MII and RMII management clock. See the MC711x Reference Manual for operation details.
Host 8/16 Bit Mode
H8BIT
Input
This pin is sampled at the deassertion of PORESET. If the line is pulled up at reset, the HDI16
operates in 8-bit mode when enabled. If the line is pulled down at reset, the HDI16 operates in 16-
bit mode.
Reserved
MDIO
Input
Reserved D3 (default)
When configured through port D bit 3, a reserved signal.
Input/Output
Management Data
MII and RMII management data. See the MC711x Reference Manual for operation details.
1.5.3 Host Interface Port
Table 1-8. Host Interface Signals
Pin
Data Flow
Description
Reserved or
GPIC11
Input
Reserved C11 or General-Purpose Input C11 (default)
When configured through port C bit 11, a reserved signal (mask set 1L44X) or a general-purpose
input (mask set 1M88B).
Reserved or
GPOC11
Output
Reserved C11 or General-Purpose Output C11
When configured through port C bit 11, a reserved signal (mask set 1L44X) or a general-purpose
output (mask set 1M88B).
HA3
Input
Input
Host Address 3
Host address line 3. Tie this signal to ground.
Reserved
Reserved C10–C8 (default)
When configured through port C bits 10–8, reserved signals.
HA[2–0]
Input
Input
Host Address 2–0
Host address bus. See the MC711x Reference Manual for operation details.
GPIC[7–0]
General-Purpose Inputs C7–C0 (default)
When configured through port C bits 7–0, perform as a general-purpose inputs.
GPOC[7–0]
HD[15–8]
Output
General-Purpose Outputs C7–C0
When configured through port C bits 7–0, perform as a general-purpose outputs.
Input/Output
Host Data Bus (Upper Half)
The host data bus is used to access the internal host registers. See the MC711x Reference Manual
for operation details.
Reserved
HD[7–0]
Input
Reserved B7–B0 (default)
When configured through port B bits 7–0, reserved signals.
Input/Output
Host Data Bus (Lower Half)
The host data bus is used to access the internal host registers. See the MC711x Reference Manual
for operation details.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
1-13
Signals/Connections
Table 1-8. Host Interface Signals (Continued)
Pin
Data Flow
Description
Reserved
Input
Reserved B10 (default)
When configured through port B bit 10, reserved signal.
HCS1/HCS1
Input
Host Chip Select 1
When the HDI16 interface is enabled, this is one of the two chip-select pins. The polarity of this pin
is programmable. The HDI16 chip select is a logical OR of HCS1 and HCS2 with appropriate
polarity.
Reserved or
GPIB11
Input
Reserved B11 or General-Purpose Input B11 (default)
When configured through port B bit 11, a reserved signal (mask set 1L44X) or a general-purpose
input (mask set 1M88B).
Reserved or
GPOB11
Output
Input
Reserved B11 or General-Purpose Output B11
When configured through port B bit 11, a reserved signal (mask set 1L44X) or a general-purpose
output (mask set 1M88B).
HCS2/HCS2
Host Chip Select 2
When the HDI16 interface is enabled, this is one of the two chip-select pins. The polarity of this pin
is programmable. The HDI16 chip select is a logical OR of HCS1 and HCS2 with appropriate
polarity.
Reserved
HRW
Input
Input
Reserved B12 (default)
When configured through port B bit 12, reserved signal.
Host Read Write
When HDI16 is configured to work in single strobe mode, this is the Read/Write input (HRW).
Host Read Data Strobe
HRD/HRD
Reserved
Input
Input
When HDI16 is programmed to interface a double data strobe host bus, this pin is the Read Data
Strobe input (HRD). The polarity of the data strobe is programmable.
Reserved B13 (default)
When configured through port B bit 13, reserved signal.
HDS/HDS
Input
Input
Host Data Strobe
When the HDI16 is programmed to interface a single data strobe host bus, this pin is the Data
Strobe input (HDS). The polarity of the data strobe is programmable.
HWR/HWR
Host Write Data Strobe
When the HDI16 is programmed to interface a double data strobe host bus, this pin is the Write
Data Strobe input (HWR). The polarity of the data strobe is programmable.
Reserved
HDDS
Input
Input
Reserved B14 (default)
When configured through port B bit 14, reserved signal.
Host Dual Data Strobe
When the HDI16 is enabled, this pin indicates whether to use Single or Dual Data Strobe mode.
MSC7116 Technical Data, Rev. 8
1-14
Freescale Semiconductor
Multiplexed I/O Signal Ports A–D
Table 1-8. Host Interface Signals (Continued)
Pin
Data Flow
Description
Reserved
Input
Reserved B8 (default)
When configured through port B bit 8, reserved signal.
HREQ/HREQ
HTRQ/HTRQ
HDSP
Output
Output
Input
Host Request
When the HDI16 is programmed to interface a single host request host bus, this pin is the Host
Request output (HREQ). The polarity of the host request is programmable. The host request may
be programmed as a driven or open-drain output.
When configured for open drain, an external pull-up must be used on this pin.
Host Transmit Request
When the HDI16 is programmed to interface a double host request host bus, this pin is the Transmit
Host Request output (HTRQ). The polarity of the host request is programmable. The host request
may be programmed as a driven or open-drain output.
When configured for open drain, an external pull-up must be used on this pin.
Host Data Strobe Polarity
This pin is sampled at the deassertion of PORESET. This pin defines the polarity of host port read-
write strobes.
Reserved
Input
Input
Reserved B9 (default)
When configured through port B bit 9, reserved signal.
HACK/HACK
Host Acknowledge
When the HDI16 is programmed to interface a single host request host bus, this pin is the Host
Acknowledge input (HACK). The polarity of the host acknowledge is programmable.
HRRQ/HRRQ
Output
Host Receive Request
When the HDI16 is programmed to interface a double host request host bus, this pin is the Receive
Host Request output (HRRQ). The polarity of the host request is programmable. The host request
may be programmed as a driven or open-drain output.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
1-15
Signals/Connections
1.5.4 I2C Port
Table 1-9. I2C Signals
Description
Pin
Data Flow
GPIA15
Input
General-Purpose Input A15 (default)
When configured through port A bit 15, performs as a general-purpose input.
IRQ14
GPOA15
SCL
Input
Interrupt Request 14
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
Output
Input/Output
General-Purpose Output A15
When configured through port A bit 15, performs as a general-purpose output.
2
I C Clock
2
2
The I C clock signal. For I C, use an external pull-up on this pin. See the MC711x Reference
Manual for operation details.
GPIA14
IRQ15
GPOA14
SDA
Input
General-Purpose Input A14 (default)
When configured through port A bit 14, performs as a general-purpose input.
Input
Interrupt Request 15
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
Output
Input/Output
General-Purpose Output A14
When configured through port A bit 14, performs as a general-purpose output.
2
I C Data
2
2
I C data signal. When used for I C, use an external pull-up on this pin. See the MC711x Reference
Manual for operation details.
1.5.5 UART Port
Table 1-10. UART Signals
Pin
Data Flow
Description
GPIA13
Input
General-Purpose Input A13 (default)
When configured through port A bit 13, performs as a general-purpose input.
IRQ2
Input
Interrupt Request 2
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA13
Output
General-Purpose Output A13
When configured through port A bit 13, performs as a general-purpose output.
URXD
Input
Input
UART Receive Data
UART receive data line.
GPIA12
General-Purpose Input A12 (default)
When configured through port A bit 12, performs as a general-purpose input.
IRQ3
Input
Interrupt Request 3
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA12
UTXD
Output
Output
General-Purpose Output A12
When configured through port A bit 12, performs as a general-purpose output.
UART Transmit Data
UART transmit data line.
MSC7116 Technical Data, Rev. 8
1-16
Freescale Semiconductor
Multiplexed I/O Signal Ports A–D
1.5.6 Event Port
Table 1-11. Event Port Signals
Description
Pin
Data Flow
Reserved
Input
Reserved PC13 (default)
When configured through port C bit 13, reserved signal.
EVNT0
GPIA17
Input/
Output
Event 0
Provides input and output events to the system control unit event multiplexers.
Input
General-Purpose Input A17 (default)
When configured through port A bit 17, performs as a general-purpose input.
IRQ13
Input
Interrupt Request 13
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA17
EVNT1
Output
General-Purpose Output A17
When configured through port A bit 17, performs as a general-purpose output.
Input/
Event 1
Output
Provides input and output events to the system control unit event multiplexers.
CLKO
Output
Input
CLKO
Output clock signal when the function is enabled.
GPIC14
General-Purpose Input C14 (default)
When configured through port C bit 14, performs as a general-purpose input.
GPOC14
EVNT2
BM0
Output
General-Purpose Output C14
When configured through port C bit 14, performs as a general-purpose output.
Input/
Output
Event 2
Provides input and output events to the system control unit event multiplexers.
Input
Boot Mode 0
This pin is sampled at the deassertion of PORESET. With BM1, the value of this signal
defines the boot mode of the MSC7116. See the MC711x Reference Manual for operation details.
GPIC15
GPOC15
EVNT3
BM1
Input
General-Purpose Input C15 (default)
When configured through port C bit 15, performs as a general-purpose input.
Output
General-Purpose Output C15
When configured through port C bit 15, performs as a general-purpose output.
Input/
Output
Event 3
Provides input and output events to the system control unit event multiplexers.
Input
Boot Mode 1
This pin is sampled at the deassertion of PORESET. With BM0, the value of this signal
defines the boot mode of the MSC7116. See the MC711x Reference Manual for operation details.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
1-17
Signals/Connections
Table 1-11. Event Port Signals
Description
Pin
Data Flow
GPIA16
Input
General-Purpose Input A16 (default)
When configured through port A bit 16, performs as a general-purpose input.
IRQ12
Input
Interrupt Request 12
One of the 27 maskable interrupts that can be configured for the MSC7116 device.
GPOA16
EVNT4
Output
General-Purpose Output A16
When configured through port A bit 16, performs as a general-purpose output.
Input/
Event 4
Output
Provides input and output events for the system control unit event multiplexers. Can be used to
indicate that the SC1400 core is in Debug mode.
SWTE
Input
Input
Software Watchdog Timer Disable
This pin is sampled at the deassertion of PORESET. If the signal is sampled high, the watchdog
timer is enabled. If it is sampled low, the watchdog timer is disabled.
Reserved
Reserved PC12 (default)
When configured through port C bit 12, reserved signal.
EE0/DBREQ
Input/
OCE Event Bit 0/Debug Request
Output
Debug port EE0 functionality is detected by EDCA0 when EE0DEF=00, which generates an OCE
event or enables EDCA0 when EE0DEF=10 in the SC1400 EE_CTRL register. When the port is
programmed for Debug mode (EE0DEF=11 in the SC1400 EE_CTRL register, asserting this signal
causes the core to enter Debug mode.
1.5.7 Boot Mode 3–2 (implemented in mask set 1M88B only)
Table 1-12. BM[3–2] Signals
Pin
Data Flow
Description
Reserved or
GPID8
Input
Reserved D8 or General-Purpose Input D8 (default)
When configured through port D bit 8, a reserved signal (mask set 1L44X) or a general-purpose
input (mask set 1M88B).
Reserved or
GPOD8
Output
Input
Reserved D8 or General-Purpose Output D8
When configured through port D bit 8, a reserved signal (mask set 1L44X) or a general-purpose
output (mask set 1M88B).
BM3
Boot Mode 3
For the 1M88B mask set only, this pin is sampled at the deassertion of PORESET. Along with
BM[0–2] the value of this signal defines the boot mode for the device. For designs developed using
the 1L44X mask set, this signal can be left unconnected.
Reserved or
GPID7
Input
Reserved D7 or General-Purpose Input D7 (default)
When configured through port D bit 7, a reserved signal (mask set 1L44X) or a general-purpose
input (mask set 1M88B).
Reserved or
GPOD7
Output
Input
Reserved B11 or General-Purpose Output B11
When configured through port D bit 7, a reserved signal (mask set 1L44X) or a general-purpose
output (mask set 1M88B).
BM2
Boot Mode 2
For the 1M88B mask set only, this pin is sampled at the deassertion of PORESET. Along with
BM[0–1] and BM3, the value of this signal defines the boot mode for the device. For designs
developed using the 1L44X mask set, this signal can be left unconnected.
MSC7116 Technical Data, Rev. 8
1-18
Freescale Semiconductor
OCE Event and JTAG Test Access Port
1.5.8 NMI
Table 1-13. NMI Signal
Signal Description
Signal Name
Type
Reserved
Input
Reserved A18 (default)
When configured through port A bit 18, reserved signal.
NMI
Input
Non-Maskable Interrupt
External device may assert this line to generate a non-maskable interrupt to the MSC7116 device.
1.6 OCE Event and JTAG Test Access Port
The MSC7116 supports the standard set of test access port (TAP) signals defined by IEEE® Std 1149.1™ Test
Access Port and Boundary-Scan Architecture specification and described in Table 1-14. The TPSEL pin should be
tied to GND to access the TAP.
Table 1-14. OCE Event and JTAG TAP Signals
Pin
Data Flow
Description
TCK
TDI
Input
Test Clock (JTAG)
Clock input for the MSC7116 JTAG controller to synchronize the test logic.
Input
Test Data In (JTAG)
A test data input (with an internal pull-up resistor) that is sampled on the rising edge of TCK.
TDO
Output
Test Data Out (JTAG)
A data output that can be three-stated and actively driven in the shift-IR and shift-DR controller
states. TDO changes on the falling edge of TCK.
TMS
Input
Test Mode Select (JTAG)
A test mode select input (with an internal pull-up resistor) that is sampled on the rising edge of TCK
to sequence the TAP controllers state machine.
TRST
Input
Input
Test Reset (JTAG)
The reset input to the MSC7116 JTAG controller (with an internal pull-up resistor).
TPSEL
Tap Select
When deasserted, the Boundary Scan TAP controller is selected, allowing for boundary scan. When
asserted, the Debug TAP controller is selected, allowing access to the OCE port.
1.7 Reserved Signals
Table 1-15. Reserved Signals
Signal Description
Signal Name
Type
TEST0
Input
Test
For manufacturing testing. You must connect this pin to GND.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
1-19
Signals/Connections
MSC7116 Technical Data, Rev. 8
1-20
Freescale Semiconductor
Specifications
2
This document contains detailed information on power considerations, DC/AC electrical characteristics, and AC
timing specifications. For additional information, see the MSC711x Reference Manual.
Note: The MSC7116 electrical specifications are preliminary and many are from design simulations. These
specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized
specifications will be published after thorough characterization and device qualifications have been
completed.
2.1 Maximum Ratings
CAUTION
This device contains circuitry protecting against damage
due to high static voltage or electrical fields; however,
normal precautions should be taken to avoid exceeding
maximum voltage ratings. Reliability is enhanced if unused
inputs are tied to an appropriate logic voltage level (for
example, either GND or V ).
DD
In calculating timing requirements, adding a maximum value of one specification to a minimum value of another
specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation
of process parameter values in one direction. The minimum specification is calculated using the worst case for the
same parameters in the opposite direction. Therefore, a “maximum” value for a specification never occurs in the
same device with a “minimum” value for another specification; adding a maximum to a minimum represents a
condition that can never exist.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
2-1
Specifications
Table 2-1 describes the maximum electrical ratings for the MSC7116.
Table 2-1. Absolute Maximum Ratings
Rating
Symbol
Value
Unit
Core supply voltage
Memory supply voltage
PLL supply voltage
I/O supply voltage
Input voltage
V
V
1.5
V
V
DDC
DDM
4.0
1.5
V
V
DDPLL
V
–0.2 to 4.0
(GND – 0.2) to 4.0
4.0
V
DDIO
V
V
IN
Reference voltage
V
V
REF
Maximum operating temperature
T
105
°C
°C
°C
J
Minimum operating temperature
T
–40
A
Storage temperature range
T
–55 to +150
STG
Notes: 1. Functional operating conditions are given in Table 2-2.
2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond
the listed limits may affect device reliability or cause permanent damage.
3. Section 4.1, Thermal Design Considerations includes a formula for computing the chip junction temperature (T ).
J
2.2 Recommended Operating Conditions
Table 2-2 lists recommended operating conditions. Proper device operation outside of these conditions is not
guaranteed.
Table 2-2. Recommended Operating Conditions
Rating
Symbol
Value
Unit
Core supply voltage
Memory supply voltage
PLL supply voltage
V
V
1.14 to 1.26
2.38 to 2.63
1.14 to 1.26
3.14 to 3.47
1.19 to 1.31
V
V
V
V
V
DDC
DDM
V
DDPLL
I/O supply voltage
V
DDIO
Reference voltage
V
REF
Operating temperature range
T
maximum: 105
minimum: –40
°C
°C
J
T
A
MSC7116 Technical Data, Rev. 8
2-2
Freescale Semiconductor
Thermal Characteristics
2.3 Thermal Characteristics
Table 2-3 describes thermal characteristics of the MSC7116 for the MAP-BGA package.
Table 2-3. Thermal Characteristics for MAP-BGA Package
MAP-BGA 17 × 17 mm5
Characteristic
Symbol
Unit
Natural
200 ft/min
Convection
(1 m/s) airflow
1, 2
Junction-to-ambient
R
R
R
R
39
23
12
7
31
20
°C/W
°C/W
°C/W
°C/W
°C/W
θJA
θJA
θJB
θJC
1, 3
Junction-to-ambient, four-layer board
4
Junction-to-board
5
Junction-to-case
6
Junction-to-package-top
Ψ
2
JT
Notes: 1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal.
4. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on
the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2.
Section 4.1, Thermal Design Considerations explains these characteristics in detail.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
2-3
Specifications
2.4 DC Electrical Characteristics
This section describes the DC electrical characteristics for the MSC7116.
Note: The leakage current is measured for nominal voltage values must vary in the same direction (for example,
both VDDIO and VDDC vary by +2 percent or both vary by –2 percent).
Table 2-4. DC Electrical Characteristics
Characteristic
Symbol
Min
Typical
Max
Unit
Core and PLL voltage
V
1.14
1.2
1.26
V
DDC
V
DDPLL
1
DRAM interface I/O voltage
I/O voltage
V
2.375
3.135
2.5
3.3
2.625
3.465
V
V
DDM
V
DDIO
2
DRAM interface I/O reference voltage
V
0.49 × V
1.25
0.51 × V
DDM
V
REF
DDM
3
DRAM interface I/O termination voltage
Input high CLKIN voltage
VTT
V
– 0.04
V
V + 0.04
REF
V
REF
REF
REF
V
2.4
3.0
3.465
V + 0.3
DDM
V
IHCLK
DRAM interface input high I/O voltage
DRAM interface input low I/O voltage
V
V
+ 0.28
V
V
IHM
DDM
V
–0.3
GND
V
– 0.18
REF
V
ILM
Input leakage current, V = V
I
–1.0
—
0.09
—
1
µA
µA
µA
IN
DDIO
IN
V
input leakage current
I
5
1
REF
VREF
Tri-state (high impedance off state) leakage current,
= V
I
–1.0
0.09
OZ
V
IN
DDIO
Signal low input current, V = 0.4 V
I
–1.0
–1.0
2.0
0.09
0.09
3.0
0
1
1
µA
µA
V
IL
L
Signal high input current, V = 2.0 V
I
IH
H
Output high voltage, I = –2 mA, except open drain pins
V
—
OH
OH
Output low voltage, I = 5 mA
V
—
0.4
V
OL
OL
5
Typical core power
P
C
•
•
at 200 MHz
at 266 MHz (mask set 1M88B only)
—
—
222
293
—
—
mW
mW
Notes: 1. The value of V
at the MSC7116 device must remain within 50 mV of V
at the DRAM device at all times.
DDM
DDM
2.
V
must be equal to 50% of V
and track V
variations as measured at the receiver. Peak-to-peak noise must not
REF
DDM
DDM
exceed 2% of the DC value.
is not applied directly to the MSC7116 device. It is the level measured at the far end signal termination. It should be equal
3.
V
TT
to V
. This rail should track variations in the DC level of V
.
REF
REF
4. Output leakage for the memory interface is measured with all outputs disabled, 0 V ≤V
≤V
.
OUT
DDM
5. The core power values were measured.using a standard EFR pattern at typical conditions (25°C, 200 MHz or 266 MHz, 1.2 V
core).
Table 2-5 lists the DDR DRAM capacitance.
Table 2-5. DDR DRAM Capacitance
Parameter/Condition
Symbol
Max
Unit
Input/output capacitance: DQ, DQS
Delta input/output capacitance: DQ, DQS
Note: These values were measured under the following conditions:
• V = 2.5 V 0.125 V
C
30
30
pF
pF
IO
C
DIO
DDM
• f = 1 MHz
• T = 25° C
A
• V
• V
= V
/2
OUT
OUT
DDM
(peak to peak) = 0.2 V
MSC7116 Technical Data, Rev. 8
2-4
Freescale Semiconductor
AC Timings
2.5 AC Timings
This section presents timing diagrams and specifications for individual signals and parallel I/O outputs and inputs.
All AC timings are based on a 30 pF load, except where noted otherwise, and a 50 Ω transmission line. For any
additional pF, use the following equations to compute the delay:
•
•
Standard interface: 2.45 + (0.054 × C ) ns
load
DDR interface: 1.6 + (0.002 × C ) ns
load
2.5.1 Clock and Timing Signals
The following tables describe clock signal characteristics. Table 2-6 shows the maximum frequency values for
internal (core, reference, and peripherals) and external (CLKO) clocks. You must ensure that maximum frequency
values are not exceeded (see for the allowable ranges when using the PLL).
Table 2-6. Maximum Frequencies
Maximum in MHz
Characteristic
Mask Set 1L44X
Mask Set 1M88B
Core clock frequency (CLOCK)
200
50
266
67
External output clock frequency (CLKO)
Memory clock frequency (CK, CK)
TDM clock frequency (TxRCK, TxTCK)
100
50
133
67
Table 2-7. Clock Frequencies in MHz
Max
Characteristic
Symbol
Min
Mask Set 1L44X
Mask Set 1M88B
CLKIN frequency
F
F
10
—
—
—
—
—
100
200
100
50
100
266
133
50
CLKIN
CLOCK frequency
CORE
CK, CK frequency
F
CK
TDMxRCK, TDMxTCK frequency
CLKO frequency
F
TDMCK
F
F
50
67
CKO
AHB/IPBus/APB clock frequency
100
133
BCK
Note:
The rise and fall time of external clocks should be 5 ns maximum
Table 2-8. System Clock Parameters
Characteristic
Min
Max
Unit
CLKIN frequency
10
—
—
—
100
5
MHz
ns
CLKIN slope
CLKIN frequency jitter (peak-to-peak)
CLKO frequency jitter (peak-to-peak)
1000
150
ps
ps
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
2-5
Specifications
2.5.2 Configuring Clock Frequencies
This section describes important requirements for configuring clock frequencies in the MSC7116 device when
using the PLL block. To configure the device clocking, you must program four fields in the Clock Control Register
(CLKCTL):
•
PLLDVF field. Specifies the PLL division factor. The output of the divider block is the input to the
multiplier block.
•
•
•
PLLMLTF field. Specifies the PLL multiplication factor. The output from the multiplier block is the VCO.
RNG field. Selects the available PLL frequency range.
CKSEL field. Selects the source for the core clock.
There are restrictions on the frequency range permitted at the beginning of the multiplication portion of the PLL
that affect the allowable values for the PLLDVF and PLLMLTF fields. The following sections define these
restrictions and provide guidelines to configure the device clocking when using the PLL. Refer to the Clock and
Power Management chapter in the MSC711x Reference Manual for details on the clock programming model.
2.5.2.1
PLL Multiplier Restrictions
There are two restrictions for correct usage of the PLL block:
•
The input frequency to the PLL multiplier block (that is, the output of the divider) must be in the range
10.5–19.5 MHz.
•
The output frequency of the PLL multiplier must be in the range 300-600 MHz.
When programming the PLL for a desired output frequency using the PLLDVF, PLLMLTF, and RNG fields, you
must meet these constraints.
2.5.2.2
Division Factors and Corresponding CLKIN Frequency Range
The value of the PLLDVF field determines the allowable CLKIN frequency range, as shown in Table 2-9.
Table 2-9. CLKIN Frequency Ranges by Divide Factor Value
PLLDVF
Field Value
Divide
Factor
CLKIN Frequency Range
Comments
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
1
2
3
4
5
6
7
8
9
10.5 to 19.5 MHz
21 to 39 MHz
Pre-Division by 1
Pre-Division by 2
Pre-Division by 3
Pre-Division by 4
Pre-Division by 5
Pre-Division by 6
Pre-Division by 7
Pre-Division by 8
Pre-Division by 9
31.5 to 58.5 MHz
42 to 78 MHz
52.5 to 97.5 MHz
63 to 100 MHz
73.5 to 100 MHz
84 to 100 MHz
94.5 to 100 MHz
Note:
The maximum CLKIN frequency is 100 MHz. Therefore, the PLLDVF value must be in the range from 1–9.
MSC7116 Technical Data, Rev. 8
2-6
Freescale Semiconductor
AC Timings
2.5.2.3
Multiplication Factor Range
The multiplier block output frequency ranges depend on the input clock frequency as shown in Table 2-10.
Table 2-10. PLLMLTF Ranges
Multiplier Block (Loop) Output Range
Minimum PLLMLTF Value Maximum PLLMLTF Value
300 ≤[Pre-Divided Clock × (PLLMLTF + 1)] ≤600 MHz
300/Pre-Divided Clock
600/Pre-Divided Clock
Note:
This table results from the allowed range for F
frequency of the Pre-Divided Clock.
. The minimum and maximum multiplication factors are dependent on the
Loop
2.5.2.4
Allowed Core Clock Frequency Range
The frequency delivered to the core, extended core, and peripheral depends on the value of the CLKCTRL[RNG]
bit as shown in Table 2-11.
Table 2-11. Fvco Frequency Ranges
CLKCTRL[RNG] Value
Allowed Range of Fvco
1
0
300 ≤F
150 ≤F
≤600 MHz
≤300 MHz
vco
vco
Note:
This table results from the allowed range for F , which is F
modified by CLKCTRL[RNG].
Loop
vco
This bit along with the CKSEL determines the frequency range of the core clock.
Table 2-12. Resulting Ranges Permitted for the Core Clock
Resulting
Division
Factor
Allowed Range
of Core Clock
CLKCTRL[CKSEL]
CLKCTRL[RNG]
Comments
11
11
01
01
1
0
1
0
1
2
2
4
Reserved
Reserved
150 ≤Core_Clk ≤200 MHz
150 ≤Core_Clk ≤200 MHz
75 ≤Core_Clk ≤150 MHz
Limited by range of PLL
Limited by range of PLL
Limited by range of PLL
Note:
This table results from the allowed range for F
, which depends on clock selected via CLKCTRL[CKSEL].
OUT
2.5.2.5
Core Clock Frequency Range When Using DDR Memory
The core clock can also be limited by the frequency range of the DDR devices in the system. Table 2-13
summarizes this restriction.
Table 2-13. Core Clock Ranges When Using DDR
Allowed Frequency
Range for DDR CK
Corresponding Range
for the Core Clock
DDR Type
Comments
DDR 200 (PC-1600)
DDR 266 (PC-2100)
DDR 333 (PC-2600)
83–100 MHz
83–133 MHz
83–150 MHz
166 ≤core clock ≤200 MHz
166 ≤core clock ≤266 MHz
166 ≤core clock ≤300 MHz
Core limited to 2 × maximum DDR frequency
Core limited to 2 × maximum DDR frequency
Core limited to 2 × maximum DDR frequency
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
2-7
Specifications
2.5.3 Reset Timing
The MSC7116 device has several inputs to the reset logic. All MSC7116 reset sources are fed into the reset
controller, which takes different actions depending on the source of the reset. The reset status register indicates the
most recent sources to cause a reset. Table 2-14 describes the reset sources.
Table 2-14. Reset Sources
Name
Direction
Description
Power-on reset
(PORESET)
Input
Initiates the power-on reset flow that resets the MSC7116 and configures various attributes of the
MSC7116. On PORESET, the entire MSC7116 device is reset. SPLL and DLL states are reset,
HRESET is driven, the SC1400 extended core is reset, and system configuration is sampled. The
system is configured only when PORESET is asserted.
External Hard
reset (HRESET)
Input/ Output
Initiates the hard reset flow that configures various attributes of the MSC7116. While HRESET is
asserted, HRESET is an open-drain output. Upon hard reset, HRESET is driven and the SC1400
extended core is reset.
Software
watchdog reset
Internal
Internal
Internal
When the MSC7116 watchdog count reaches zero, a software watchdog reset is signalled. The
enabled software watchdog event then generates an internal hard reset sequence.
Bus monitor
reset
When the MSC7116 bus monitor count reaches zero, a bus monitor hard reset is asserted. The
enabled bus monitor event then generates an internal hard reset sequence.
JTAG EXTEST,
CLAMP, or
When a Test Access Port (TAP) executes an EXTEST, CLAMP, or HIGHZ command, the TAP logic
asserts an internal reset signal that generates an internal soft reset sequence.
HIGHZ command
Table 2-15 summarizes the reset actions that occur as a result of the different reset sources.
Table 2-15. Reset Actions for Each Reset Source
Power-On Reset
(PORESET)
Hard Reset
(HRESET)
Soft Reset
(SRESET)
Reset Action/Reset Source
External or
Internal (Software
Watchdog or Bus
Monitor)
JTAG Command:
EXTEST, CLAMP,
or HIGHZ
External only
Configuration pins sampled (refer to Section 2.5.3.1 for
details).
Yes
No
No
PLL and clock synthesis states Reset
HRESET Driven
Yes
Yes
Yes
Yes
No
No
No
Yes
Yes
Yes
Software watchdog and bus time-out monitor registers
Yes
Yes
Clock synthesis modules (STOPCTRL, HLTREQ, and
HLTACK) reset
Extended core reset
Yes
Yes
Yes
Yes
Yes
Yes
Peripheral modules reset
MSC7116 Technical Data, Rev. 8
2-8
Freescale Semiconductor
AC Timings
2.5.3.1 Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET must be asserted externally for at least 16 CLKIN
cycles after external power to the MSC7116 reaches at least 2/3 VDD
.
2.5.3.2 Reset Configuration
The MSC7116 has two mechanisms for writing the reset configuration:
•
•
From a host through the host interface (HDI16)
2
From memory through the I C interface
Five signal levels (see Chapter 1 for signal description details) are sampled on PORESET deassertion to define the
boot and operating conditions:
•
•
•
•
BM[0–1]
SWTE
H8BIT
HDSP
2.5.3.3 Reset Timing Tables
Table 2-16 and Figure 2-1 describe the reset timing for a reset configuration write.
Table 2-16. Timing for a Reset Configuration Write
No.
Characteristics
Expression
Unit
1
2
Required external PORESET duration minimum
Delay from PORESET deassertion to HRESET deassertion
Timings are not tested, but are guaranteed by design.
16/F
clocks
clocks
CLKIN
521/F
CLKIN
Note:
1
PORESET
Input
Configuration Pins
are sampled
PORESET
Internal
HRESET
Output(I/O)
2
Figure 2-1. Timing Diagram for a Reset Configuration Write
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
2-9
Specifications
2.5.4 DDR DRAM Controller Timing
This section provides the AC electrical characteristics for the DDR DRAM interface.
2.5.4.1 DDR DRAM Input AC Timing Specifications
Table 2-17 provides the input AC timing specifications for the DDR DRAM interface.
Table 2-17. DDR DRAM Input AC Timing
Max
No.
Parameter
Symbol
Min
Unit
Mask Set
1L44X
Mask Set
1M88B
—
—
AC input low voltage
V
—
V
– 0.31
V – 0.31
REF
V
V
IL
REF
AC input high voltage
V
V
+ 0.31
V
+ 0.3
V
+ 0.3
IH
REF
DDM
DDM
201
Maximum Dn input setup skew relative to DQSn
input
—
—
1026
900
ps
202
Maximum Dn input hold skew relative to DQSn
input
—
—
386
900
ps
Notes: 1. Maximum possible skew between a data strobe (DQSn) and any corresponding bit of data (D[8n + {0...7}] if 0 ≤n ≤7).
2. See Table 2-18 for t value.
CK
3. Dn should be driven at the same time as DQSn. This is necessary because the DQSn centering on the DQn data tenure is
done internally.
DQSn
202
202
D1
D0
Dn
201
201
Note: DQS centering is done internally.
Figure 2-2. DDR DRAM Input Timing Diagram
MSC7116 Technical Data, Rev. 8
2-10
Freescale Semiconductor
AC Timings
2.5.4.2 DDR DRAM Output AC Timing Specifications
Table 2-18 and Table 2-19 list the output AC timing specifications and measurement conditions for the DDR
DRAM interface.
Table 2-18. DDR DRAM Output AC Timing
Min
No.
200
204
Parameter
Symbol
Max
Unit
Mask Set
1L44X
Mask Set
1M88B
1
CK cycle time, (CK/CK crossing)
t
CK
•
•
100 MHz (DDR200)
133 MHz (DDR266)
10
1.0
7.52
—
—
ns
ns
Not applicable
An/RAS/CAS/WE/CKE output setup with respect to
CK
t
0.5 × t – 2250
0.5 × t – 1000
—
ps
DDKHAS
CK
CK
205
206
207
208
209
An/RAS/CAS/WE/CKE output hold with respect to CK
CSn output setup with respect to CK
t
t
0.5 × t – 1250
0.5 × t – 1000
—
—
ps
ps
ps
ps
ps
DDKHAX
CK
CK
0.5 × t – 2250
0.5 × t – 1000
DDKHCS
DDKHCX
DDKHMH
CK
CK
CSn output hold with respect to CK
t
0.5 × t – 1250
0.5 × t – 1000
—
CK
CK
2
CK to DQSn
t
–600
–600
600
—
3
Dn/DQMn output setup with respect to DQSn
t
0.25 × t
–
0.25 × t – 750
DDKHDS,
MCK
CK
t
1050
DDKLDS
3
210
Dn/DQMn output hold with respect to DQSn
t
0.25 × t – 1050 0.25 × t – 750
—
ps
DDKHDX,
CK
CK
t
DDKLDX
DDKHMP
DDKHME
4
211
212
DQSn preamble start
t
t
–0.25 × t
–0.25 × t
—
ps
ps
CK
CK
5
DQSn epilogue end
–600
–600
600
Notes: 1. All CK/CK referenced measurements are made from the crossing of the two signals 0.1 V.
2. can be modified through the TCFG2[WRDD] DQSS override bits. The DRAM requires that the first write data strobe
t
DDKHMH
arrives 75–125% of a DRAM cycle after the write command is issued. Any skew between DQSn and CK must be considered
when trying to achieve this 75%–125% goal. The TCFG2[WRDD] bits can be used to shift DQSn by 1/4 DRAM cycle
increments. The skew in this case refers to an internal skew existing at the signal connections. By default, the CK/CK crossing
occurs in the middle of the control signal (An/RAS/CAS/WE/CKE) tenure. Setting TCFG2[ACSM] bit shifts the control signal
assertion 1/2 DRAM cycle earlier than the default timing. This means that the signal is asserted no earlier than 410 ps before
the CK/CK crossing and no later than 677 ps after the crossing time; the device uses 1087 ps of the skew budget (the interval
from –410 to +677 ps). Timing is verified by referencing the falling edge of CK. See Chapter 10 of the MSC711x Reference
Manual for details.
3. Determined by maximum possible skew between a data strobe (DQS) and any corresponding bit of data. The data strobe
should be centered inside of the data eye.
4. Please note that this spec is in reference to the DQSn first rising edge. It could also be referenced from CK(r), but due to
programmable delay of the write strobes (TCFG2[WRDD]), there pre-amble may be extended for a full DRAM cycle. For this
reason, we reference from DQSn.
5. All outputs are referenced to the rising edge of CK. Note that this is essentially the CK/DQSn skew in spec 208. In addition
there is no real “maximum” time for the epilogue end. JEDEC does not require this is as a device limitation, but simply for the
chip to guarantee fast enough write to read turn-around times. This is already guaranteed by the memory controller operation.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
2-11
Specifications
Figure 2-3 shows the DDR DRAM output timing diagram.
CK
CK
200
204
205
206
An
RAS
207
CAS
WE
CKE
DQMn
Write A0
NOOP
211
208
DQSn
Dn
212
209
209
D0
D1
210
210
Figure 2-3. DDR DRAM Output Timing Diagram
Figure 2-4 provides the AC test load for the DDR DRAM bus.
Output
VOUT
Z0 = 50 Ω
RL = 50 Ω
Figure 2-4. DDR DRAM AC Test Load
Table 2-19. DDR DRAM Measurement Conditions
Symbol
DDR DRAM
Unit
1
V
V
V
0.31 V
V
V
TH
REF
2
0.5 × V
OUT
DDM
Notes: 1. Data input threshold measurement point.
2. Data output measurement point.
MSC7116 Technical Data, Rev. 8
2-12
Freescale Semiconductor
AC Timings
2.5.5 TDM Timing
Table 2-20. TDM Timing
Expression
No.
Characteristic
Min
Max
Units
300
301
302
303
304
305
306
307
308
309
310
311
TDMxRCK/TDMxTCK
TC
20.0
8.0
8.0
3.0
3.5
2.0
4.0
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TDMxRCK/TDMxTCK High Pulse Width
TDMxRCK/TDMxTCK Low Pulse Width
TDM all input Setup time
0.4 × TC
0.4 × TC
—
—
TDMxRD Hold time
—
TDMxRFS input Hold time
—
TDMxTCK High to TDMxTD output active
TDMxTCK High to TDMxTD output valid
TDMxTD hold time
—
14.0
—
2.0
—
TDMxTCK High to TDMxTD output high impedance
TDMXTFS output valid
10.0
13.5
—
—
TDMxTFS output hold time
2.5
Notes: 1. Output values are based on 30 pF capacitive load.
2. Inputs are referenced to the sampling that the TDM is programmed to use. Outputs are referenced to the programming edge
they are programmed to use. Use of the rising edge or falling edge as a reference is programmable. Refer to the MSC711x
Reference Manual for details. TDMxTCK and TDMxRCK are shown using the rising edge.
300
302
301
304
TDMxRCK
TDMxRD
303
305
303
TDMxRFS
310
311
TDMxRFS (output)
Figure 2-5. TDM Receive Signals
300
302
301
TDMxTCK
309
308
307
306
TDMxTD
TDMxRCK
310
311
TDMxTFS (output)
TDMxTFS (input)
305
303
Figure 2-6. TDM Transmit Signals
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
2-13
Specifications
2.5.6 Ethernet Timing
2.5.6.1 Receive Signal Timing
Table 2-21. Receive Signal Timing
Characteristics
No.
Min
Max
Unit
800
Receive clock period:
• MII: RXCLK (max frequency = 25 MHz)
• RMII: REFCLK (max frequency = 50 MHz)
40
20
—
—
ns
ns
801
802
Receive clock pulse width high—as a percent of clock period
• MII: RXCLK
• RMII: REFCLK
35
14
7
65
—
—
%
ns
ns
Receive clock pulse width low—as a percent of clock period:
• MII: RXCLK
• RMII: REFCLK
35
14
7
65
—
—
%
ns
ns
803
804
RXDn, RX_DV, CRS_DV, RX_ER to receive clock rising edge setup time
Receive clock rising edge to RXDn, RX_DV, CRS_DV, RX_ER hold time
4
2
—
—
ns
ns
800
802
801
Receive
clock
803
804
RXDn
RX_DV
CRS_DV
RX_ER
Valid
Figure 2-7. Ethernet Receive Signal Timing
MSC7116 Technical Data, Rev. 8
2-14
Freescale Semiconductor
AC Timings
2.5.6.2 Transmit Signal Timing
Table 2-22. Transmit Signal Timing
Characteristics
No.
Min
Max
Unit
800
Transmit clock period:
• MII: TXCLK
40
20
—
—
ns
ns
• RMII: REFCLK
801
802
Transmit clock pulse width high—as a percent of clock period
• MII: RXCLK
• RMII: REFCLK
35
14
7
65
—
—
%
ns
ns
Transmit clock pulse width low—as a percent of clock period:
• MII: RXCLK
• RMII: REFCLK
35
14
7
65
—
—
%
ns
ns
805
806
Transmit clock to TXDn, TX_EN, TX_ER invalid
Transmit clock to TXDn, TX_EN, TX_ER valid
4
—
ns
ns
—
14
800
802
801
Transmit
clock
806
805
TXDn
TX_EN
TX_ER
Valid
Figure 2-8. Ethernet Receive Signal Timing
2.5.6.3 Asynchronous Input Signal Timing
Table 2-23. Asynchronous Input Signal Timing
Characteristics
No.
Min
Max
Unit
807
• MII: CRS and COL minimum pulse width (1.5 × TXCLK period)
• RMII: CRS_DV minimum pulse width (1.5 x REFCLK period)
60
30
—
—
ns
ns
CRS
COL
CRS_DV
807
Figure 2-9. Asynchronous Input Signal Timing
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
2-15
Specifications
2.5.6.4 Management Interface Timing
Table 2-24. Ethernet Controller Management Interface Timing
Characteristics
No.
Min
Max
Unit
808
809
810
811
812
813
814
MDC period
400
160
160
0
—
—
—
—
15
—
—
ns
ns
ns
ns
ns
ns
ns
MDC pulse width high
MDC pulse width low
MDS falling edge to MDIO output invalid (minimum propagation delay)
MDS falling edge to MDIO output valid (maximum propagation delay)
MDIO input to MDC rising edge setup time
—
10
MDC rising edge to MDIO input hold time
10
808
809
810
MDC (output)
MDIO (output)
811
812
813
814
MDIO (input)
Figure 2-10. Serial Management Channel Timing
MSC7116 Technical Data, Rev. 8
2-16
Freescale Semiconductor
AC Timings
2.5.7 HDI16 Signals
Table 2-25. Host Interface (HDI16) Timing1, 2
Mask Set 1L44X
Experssion Value
Mask Set 1M88B
Unit
No.
Characteristics3
Expression
Value
40 Host Interface Clock period
T
Note 1
T
Note 1
ns
HCLK
CORE
CORE
4
44a Read data strobe minimum assertion width
HACK read minimum assertion width
3.0 × T
1.5 × T
2.5 × T
Note 11 2.0 × T
+ 9.0 Note 11 ns
HCLK
HCLK
HCLK
4
4
44b Read data strobe minimum deassertion width
HACK read minimum deassertion width
Note 11
Note 11
1.5 × T
CORE
Note 11 ns
44c Read data strobe minimum deassertion width after “Last Data
2.5 × T
Note 11 ns
Note 11 ns
Note 11 ns
CORE
CORE
CORE
5,6
Register” reads , or between two consecutive CVR, ICR, or ISR
7
reads
5,6
HACK minimum deassertion width after “Last Data Register” reads
8
45 Write data strobe minimum assertion width
1.5 × T
Note 11
1.5 × T
HCLK
HCLK
HACK write minimum assertion width
8
46 Write data strobe minimum deassertion width
HACK write minimum deassertion width after ICR, CVR and Data
5
Register writes
2.5 × T
Note 11
3.0
2.5 × T
47 Host data input minimum setup time before write data strobe
8
deassertion
—
—
2.5
2.5
ns
ns
Host data input minimum setup time before HACK write deassertion
48 Host data input minimum hold time after write data strobe
8
deassertion
—
—
4.0
1.0
—
—
Host data input minimum hold time after HACK write deassertion
49 Read data strobe minimum assertion to output data active from high
4
impedance
HACK read minimum assertion to output data active from high
impedance
1.0
ns
4
50 Read data strobe maximum assertion to output data valid
HACK read maximum assertion to output data valid
(2.0 × T
) + 8.0 Note 11 (2.0 × T
) + 8.0 Note 11 ns
CORE
HCLK
51 Read data strobe maximum deassertion to output data high
4
impedance
—
8.0
—
9.0
ns
HACK read maximum deassertion to output data high impedance
4
52 Output data minimum hold time after read data strobe deassertion
Output data minimum hold time after HACK read deassertion
—
—
—
1.0
—
—
—
1.0
0.5
0.0
ns
ns
ns
4
53 HCS[1–2] minimum assertion to read data strobe assertion
0.0
8
54 HCS[1–2] minimum assertion to write data strobe assertion
0.0
55 HCS[1–2] maximum assertion to output data valid
(2.0 × T
(3.0 × T
) + 8.0 Note 11 (2.0 × T
) + 6.0 Note 11 ns
CORE
HCLK
9
56 HCS[1–2] minimum hold time after data strobe deassertion
—
0.0
—
0.5
5.0
5.0
ns
ns
ns
9
57 HA[0–3], HRW minimum setup time before data strobe assertion
—
—
5.0
—
—
9
58 HA[0–3], HRW minimum hold time after data strobe deassertion
5.0
61 Maximum delay from read data strobe deassertion to host request
) + 8.0 Note 11 (3.0 × T
) + 6.0 Note 11 ns
HCLK
CORE
4, 5, 10
deassertion for “Last Data Register” read
62 Maximum delay from write data strobe deassertion to host request
5,8,10
deassertion for “Last Data Register” write
(3.0 × T
(2.0 × T
(5.0 × T
) + 8.0 Note 11 (3.0 × T
) + 1.0 Note 11 (2.0 × T
) + 8.0 Note 11 (5.0 × T
) + 6.0 Note 11 ns
) + 1.0 Note 11 ns
) + 6.0 Note 11 ns
HCLK
HCLK
HCLK
CORE
CORE
CORE
63 Minimum delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) deassertion to HREQ assertion.
64 Maximum delay from DMA HACK (OAD=0) or Read/Write data
strobe(OAD=1) assertion to HREQ deassertion
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
2-17
Specifications
No.
Table 2-25. Host Interface (HDI16) Timing1, 2 (Continued)
Mask Set 1L44X
Characteristics3
Mask Set 1M88B
Expression Value
Unit
Experssion
Value
Notes: 1.
2. In the timing diagrams below, the controls pins are drawn as active low. The pin polarity is programmable.
3. = 3.3 V 0.15 V; T = –40°C to +105 °C, C = 30 pF for maximum delay timings and C = 0 pF for minimum delay timings.
T
= 2/ (Core Clock). At 200 MHz, T
= 10 ns. T
= core clock period. At 266 MHz, T
= 3.75 ns.
HCLK
HCLK
CORE
CORE
V
DD
J
L
L
4. The read data strobe is HRD/HRD in the dual data strobe mode and HDS/HDS in the single data strobe mode.
5. For 64-bit transfers, The “last data register” is the register at address 0x7, which is the last location to be read or written in data
transfers. This is RX0/TX0 in the little endian mode (HBE = 0), or RX3/TX3 in the big endian mode (HBE = 1).
6. This timing is applicable only if a read from the “last data register” is followed by a read from the RXL, RXM, or RXH registers
without first polling RXDF or HREQ bits, or waiting for the assertion of the HREQ/HREQ signal.
7. This timing is applicable only if two consecutive reads from one of these registers are executed.
8. The write data strobe is HWR in the dual data strobe mode and HDS in the single data strobe mode.
9. The data strobe is host read (HRD/HRD) or host write (HWR/HWR) in the dual data strobe mode and host data strobe
(HDS/HDS) in the single data strobe mode.
10. The host request is HREQ/HREQ in the single host request mode and HRRQ/HRRQ and HTRQ/HTRQ in the double host
request mode. HRRQ/HRRQ is deasserted only when HOTX fifo is empty, HTRQ/HTRQ is deasserted only if HORX fifo is full
(treat as level Host Request).
11. Compute the value using the expression.
12. For mask set 1M88B, the read and write data strobe minimum deassertion width for non-”last data register” accesses in single
and dual data strobe modes is based on timings 57 and 58.
Figure 2-11 and Figure 2-12 show HDI16 read signal timing. Figure 2-13 and Figure 2-14 show HDI16 write
signal timing.
HA[0–3]
57
58
56
53
HCS[1–2]
57
58
HRW
HDS
44a
51
55
50
44c
52
49
HD[0–15]
61
HREQ (single host request)
HRRQ (double host request)
Figure 2-11. Read Timing Diagram, Single Data Strobe
MSC7116 Technical Data, Rev. 8
2-18
Freescale Semiconductor
AC Timings
HA[0–3]
57
58
56
53
HCS[1–2]
HRD
44a
51
55
44a
50
52
49
HD[0–15]
61
HREQ (single host request)
HRRQ (double host request)
Figure 2-12. Read Timing Diagram, Double Data Strobe
HA[0–3]
57
58
56
54
HCS[1–2]
HRW
57
58
45
HDS
46
47
48
HD[0–15]
62
HREQ (single host request)
HTRQ (double host request)
Figure 2-13. Write Timing Diagram, Single Data Strobe
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
2-19
Specifications
HA[0–3]
57
58
56
54
HCS[1–2]
HWR
45
46
48
47
HD[0–15]
62
HREQ (single host request)
HTRQ (double host request)
Figure 2-14. Write Timing Diagram, Double Data Strobe
HREQ
(Output)
63
64
44a
44b
RX[0–3]
Read
HACK
50
51
49
52
Data
Valid
HD[0–15]
(Output)
Figure 2-15. Host DMA Read Timing Diagram, HPCR[OAD] = 0
MSC7116 Technical Data, Rev. 8
2-20
Freescale Semiconductor
AC Timings
HREQ
(Output)
63
64
46
45
TX[0–3]
Write
HACK
47
48
Data
Valid
HD[0–15]
(Output)
Figure 2-16. Host DMA Write Timing Diagram, HPCR[OAD] = 0
2.5.8 I2C Timing
Table 2-26. I2C Timing
Fast
No.
Characteristic
Unit
Min
Max
450
451
452
453
454
455
456
457
458
459
460
Note:
SCL clock frequency
0
400
—
kHz
µs
µs
µs
µs
µs
ns
ns
ns
µs
µs
Hold time START condition
SCL low period
(Clock period/2) – 0.3
(Clock period/2) – 0.3
(Clock period/2) – 0.1
—
SCL high period
—
Repeated START set-up time (not shown in figure)
Data hold time
2 × 1/F
—
BCK
0
—
Data set-up time
250
—
SDA and SCL rise time
SDA and SCL fall time
—
700
300
—
—
Set-up time for STOP
(Clock period/2) – 0.7
(Clock period/2) – 0.3
Bus free time between STOP and START
—
SDA set-up time is referenced to the rising edge of SCL. SDA hold time is referenced to the falling edge of SCL. Load capacitance
on SDA and SCL is 400 pF.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
2-21
Specifications
453
6
458
3
457
Start Condition
Stop Condition
Start Condition
1
4
5
SCL
2
7
8
9
A
C
K
452
451
SDA
Data Byte
457
460
458
459
Start Condition
SCL
SDA
Data Byte
Figure 2-17. I2C Timing Diagram
2.5.9 UART Timing
Table 2-27. UART Timing
Mask Set
1L44X
Mask Set
1M88B
Unit
No.
Characteristics
Expression
Min
Max
Min
Max
—
—
Internal bus clock (APBCLK)
F
/2
—
10.0
160.0
—
100
—
—
5
—
7.52
120.3
—
133
—
—
5
MHz
ns
CORE
Internal bus clock period (1/APBCLK)
URXD and UTXD inputs high/low duration
URXD and UTXD inputs rise/fall time
UTXD output rise/fall time
T
APBCLK
400
401
402
16 × T
ns
APBCLK
ns
—
5
—
5
ns
401
401
UTXD, URXD
inputs
400
400
Figure 2-18. UART Input Timing
402
402
UTXD output
Figure 2-19. UART Output Timing
MSC7116 Technical Data, Rev. 8
2-22
Freescale Semiconductor
AC Timings
2.5.10 EE Timing
Table 2-28. EE0 Timing
Number
Characteristics
Type
Min
65
66
EE0 input to the core
Asynchronous
4 core clock periods
1 core clock period
EE0 output from the core
Synchronous to core clock
Notes: 1. The core clock is the SC1400 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset.
2. Configure the direction of the EE pin in the EE_CTRL register (see the SC1400 Core Reference Manual for details.
3. Refer to Table 1-12 for details on EE pin functionality.
Figure 2-21 shows the signal behavior of the EE pin.
65
EE0 in
66
EE0 out
Figure 2-20. EE Pin Timing
2.5.11 Event Timing
Table 2-29. EVNT Signal Timing
Number
Characteristics
Type
Min
67
68
EVNT as input
EVNT as output
Asynchronous
1.5 × APBCLK periods
1 APBCLK period
Synchronous to core clock
Notes: 1. Refer to Table 2-27 for a definition of the APBCLK period.
2. Direction of the EVNT signal is configured through the GPIO and Event port registers.
3. Refer to Table 1-10 on page 1-12 for details on EVNT pin functionality.
Figure 2-21 shows the signal behavior of the EVNT pin.
67
EVNT in
68
EVNT out
Figure 2-21. EVNT Pin Timing
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
2-23
Specifications
2.5.12 GPIO Timing
Table 2-30. GPIO Signal Timing1,2,3
Number
Characteristics
Type
Min
4.5
5
601
602
603
604
GPI
Asynchronous
1.5 × APBCLK periods
1 APBCLK period
GPO
Synchronous to core clock
Port A edge-sensitive interrupt
Port A level-sensitive interrupt
Asynchronous
Asynchronous
1.5 × APBCLK periods
6
3 × APBCLK periods
Notes: 1. Refer to Table 2-27 for a definition of the APBCLK period.
2. Direction of the GPIO signal is configured through the GPIO port registers.
3. Refer to Table 1-12 on page 1-14 for details on GPIO pin functionality.
4. GPI data is synchronized to the APBCLK internally and the minimum listed is the capability of the hardware to capture data
into a register when the GPA_DR is read. The specification is not tested due to the asynchronous nature of the input and
dependence on the state of the DSP core. It is guaranteed by design.
5. The input and output signals cannot toggle faster than 50 MHz.
6. Level-sensitive interrupts should be held low until the system determines (via the service routine) that the interrupt is
acknowledged.
Figure 2-22 shows the signal behavior of the GPI/GPO pin.
601
GPI
602
GPO
Figure 2-22. GPI/GPO Pin Timing
MSC7116 Technical Data, Rev. 8
2-24
Freescale Semiconductor
AC Timings
2.5.13 JTAG Signals
Table 2-31. JTAG Timing
All frequencies
No.
Characteristics
Unit
Min
Max
700
701
702
703
704
705
706
707
708
709
710
711
712
Note:
TCK frequency of operation (1/(T × 3); maximum 22 MHz)
0.0
25.0
11.0
0.0
40.0
—
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
C
TCK cycle time
TCK clock pulse width measured at V
TCK rise and fall times
1.6 V
—
M =
3.0
—
Boundary scan input data set-up time
Boundary scan input data hold time
TCK low to output data valid
TCK low to output high impedance
TMS, TDI data set-up time
5.0
14.0
0.0
—
20.0
20.0
—
0.0
5.0
TMS, TDI data hold time
25.0
0.0
—
TCK low to TDO data valid
24.0
10.0
—
TCK low to TDO high impedance
TRST assert time
0.0
100.0
All timings apply to OCE module data transfers as the OCE module uses the JTAG port as an interface.
701
702
V
M
V
M
V
TCK
(Input)
IH
V
IL
703
703
Figure 2-23. Test Clock Input Timing Diagram
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
2-25
Specifications
V
TCK
(Input)
IH
V
IL
704
705
Data
Inputs
Input Data Valid
706
707
Data
Outputs
Output Data Valid
Data
Outputs
Figure 2-24. Boundary Scan (JTAG) Timing Diagram
V
IH
TCK
(Input)
V
IL
709
708
Input Data Valid
TDI
TMS
(Input)
710
TDO
(Output)
Output Data Valid
711
TDO
(Output)
Figure 2-25. Test Access Port Timing Diagram
TRST
(Input)
712
Figure 2-26. TRST Timing Diagram
MSC7116 Technical Data, Rev. 8
2-26
Freescale Semiconductor
Packaging
3
This section on the MSC7116 package includes diagrams of the package ball layout and tables showing how the
signals discussed in Chapter 1 are allocated. The MSC7116 is available in a 400-pin molded array process-ball
grid array (MAP-BGA) package with either lead-free or lead-bearing solder spheres.
Note: See Lead-Free BGA Solder Joint Assembly Evaluation (EB635) for manufacturing and assembly guidelines.
3.1 MAP-BGA Package
Figure 3-1 and Figure 3-2 show top and bottom views of the MAP-BGA package, including ball location. Signal
names shown in the figures represent the only signal assigned to the location or, for multiplexed signals, the
primary hardware-controlled option. Signals used only during power-on reset (SWTE, HDSP, and BM[0–1]) are not
shown in these figures.
Table 3-1 lists the MSC7116 signals alphabetically by signal name. Connections with multiple names are listed
individually by each name. Signals with programmable polarity are shown both as asserted low (default) and high
(that is, NAME/NAME). Table 3-2 lists the signals numerically by pin number. Each pin number is listed once with the
various signals that are multiplexed to it categorized by the configuration or state that defines the signal. Four host
interface signals have alternate functions (single or double host request and single or double data strobe) that are
configured by the host interface registers.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
3-1
Packaging
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
B
C
D
E
F
GND
GND
NC
DQM1 DQS2
CK
CK
HD15
HD12
HD10
HD14
CAS
HD7
HD6
HD4
HD1
HD0
GND
NC
NC
NC
NC
NC
V
CS0
D25
D27
D31
D29
GND
D11
D9
DQM2 DQS3 DQS0
CKE
WE
HD11
HD13
HD8
HD9
HD5
HD3
HD2
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
HA2
NC
NC
NC
NC
NC
NC
HA1
DDM
D24
D30
D28
D26
D15
D13
D12
CS1
DQM3 DQM0 DQS1
RAS
V
V
V
V
V
V
V
V
V
V
V
V
V
V
GND
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
GND
DDM
DDC
DDC
DDC
DDC
DDM
DDIO
DDIO
DDIO
DDC
V
V
V
V
V
V
DDM
V
V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DDM
DDC
DDC
DDC
DDM
DDC
V
G
H
J
GND
D14
D10
D0
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDIO
DDIO
DDIO
DDIO
DDIO
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDM
V
V
V
GND
HA3
HA0
HACK HREQ
DDM
DDM
DDM
V
V
K
L
GND
GND
D8
GND
GND
GND
HDDS
HDS
DDC
DDIO
DDIO
V
V
V
D1
D3
HCS2 HCS1
HRW
DDC
DDIO
V
V
V
V
V
M
N
P
R
T
D2
D5
GND
GND
SDA
CLKIN
PORESET
TDO
UTXD URXD
DDM
DDM
DDC
V
V
V
V
V
D4
D6
GND
GND
GND
SCL
TPSEL
EE0
REF
DDM
DDM
DDIO
DDIO
DDIO
DDIO
DDC
SSPLL
V
V
V
V
V
V
D7
D17
D19
D20
D21
NC
D16
D18
D22
D23
A13
A12
A9
DDM
DDM
DDIO
DDPLL
V
V
V
V
V
V
GND
TEST0
DDM
DDM
DDM
DDM
DDIO
DDIO
V
V
V
V
V
V
V
V
V
V
V
V
V
MDIO
COL
TMS HRESET
DDM
DDM
DDC
DDM
DDM
DDC
DDM
DDM
DDIO
DDIO
DDIO
DDC
V
V
V
V
V
V
V
V
V
V
V
V
DDC
U
V
W
Y
GND
TCK
TRST
TDI
DDM
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
V
A11
A8
A10
A7
A5
A6
A4
A2
A3
BA0
NC
NC
EVNT0 EVNT4 T0TCK T1RFS T1TD TX_ER RXD2 RXD0 TX_EN CRS
DDM
V
GND
EVNT1 EVNT2 T0RFS T0TFS T1RD T1TFS TXD2 RXD3 TXD1 TXCLK RX_ER MDC
DDM
V
GND
A1
A0
BA1
NMI
EVNT3 T0RCK T0RD TOTD T1RCK T1TCK TXD3 RXCLK TXD0 RXD1
GND RX_DV
DDM
Figure 3-1. MSC7116 Molded Array Process-Ball Grid Array (MAP-BGA), Top View
MSC7116 Technical Data, Rev. 8
3-2
Freescale Semiconductor
MAP-BGA Package
Bottom View
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
A
B
C
D
E
F
NC
NC
NC
NC
NC
GND
HD0
HD1
HD4
HD6
HD7
HD10
HD12
HD15
CK
CK
DQS2 DQM1
GND
GND
V
NC
NC
NC
NC
NC
NC
HA1
NC
NC
NC
NC
NC
NC
HA2
NC
NC
NC
NC
NC
NC
NC
HA3
HA0
NC
NC
NC
NC
NC
NC
NC
NC
HD2
NC
HD5
HD3
HD8
HD9
HD11
HD13
HD14
CAS
WE
CKE
DQS0 DQS3 DQM2
CS0
D25
D27
D31
D29
GND
D11
D9
NC
DDM
RAS
DQS1 DQM0 DQM3
CS1
D30
D28
D26
D15
D13
D12
D24
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
GND
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDM
DDM
DDM
DDM
DDM
DDM
DDM
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
GND
DD
DDIO
DDIO
DDIO
DDM
DD
DD
DD
DD
DDM
DDM
V
V
V
V
V
V
V
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
DD
DDM
DDM
DD
DD
DD
DDM
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
G
H
J
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
D14
D10
D0
DDIO
DDIO
DDIO
DDIO
DDIO
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
V
DDM
V
V
V
HREQ HACK
GND
DDM
DDM
DDM
V
V
K
L
HDS
HDDS
GND
GND
GND
D8
GND
GND
DDIO
DD
V
V
V
HRW
HCS1 HCS2
D3
D1
DDIO
DDIO
DD
V
V
V
M
N
P
R
T
URXD UTXD
SDA
CLKIN
PORESET
TDO
GND
GND
D5
D2
DD
DDM
DDM
V
V
V
V
V
V
SCL
TPSEL
EE0
GND
GND
GND
D6
D4
SSPLL
DD
DDIO
DDIO
DDIO
DDIO
DDM
DDM
REF
V
V
V
V
V
V
V
V
D16
D18
D22
D23
A13
A12
A9
D17
D19
D20
D21
NC
D7
DDPLL
DDIO
DDM
DDM
V
V
V
V
V
TEST0
GND
DDIO
DDIO
DDM
DDM
DDM
DDM
V
V
V
V
V
V
V
V
V
V
V
V
HRESET TMS
MDIO
COL
DD
DDIO
DDIO
DDIO
DDM
DDM
DD
DDM
DDM
DD
DDM
DDM
V
V
V
V
V
V
V
V
V
V
V
V
V
U
V
W
Y
TRST
TDI
TCK
GND
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DD
DDM
V
CRS TX_EN RXD0 RXD2 TX_ER T1TD T1RFS T0TCK EVNT4 EVNT0
NC
BA0
NC
A2
A3
A5
A6
A4
A10
A7
A11
A8
DDM
V
MDC RX_ER TXCLK TXD1 RXD3 TXD2 T1TFS T1RD T0TFS T0RFS EVNT2 EVNT1
GND
DDM
V
RX_DV GND
RXD1 TXD0 RXCLK TXD3 T1TCK T1RCK TOTD T0RD T0RCK EVNT3
NMI
BA1
A0
A1
GND
DDM
Figure 3-2. MSC7116 Molded Array Process-Ball Grid Array (MAP-BGA), Bottom View
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
3-3
Packaging
Table 3-1. MSC7116 Signals By Name
Signal Name
Ball Designator
A0
Y5
Y4
A1
A2
V7
A3
W7
Y6
A4
A5
V6
A6
W6
W5
W4
Y3
A7
A8
A9
A10
V5
A11
V4
A12
W3
V3
A13
BA0
V8
BA1
Y7
BM0
W10
Y9
BM1
BM2 (mask set 1M88B only)
B15
A16
C9
A5
BM3 (mask set 1M88B only)
CAS
CK
CK
A6
CKE
CLKIN
CLKO
COL
CRS
CRS_DV
CS0
CS1
D0
B7
N18
W9
U18
V19
Y20
B3
C4
K1
D1
L1
D2
M1
L3
D3
D4
N1
M3
N2
P1
D5
D6
D7
MSC7116 Technical Data, Rev. 8
3-4
Freescale Semiconductor
MAP-BGA Package
Table 3-1. MSC7116 Signals By Name (Continued)
Signal Name
Ball Designator
D8
D9
K3
J3
D10
J1
D11
H3
H2
G2
H1
F2
D12
D13
D14
D15
D16
P3
P2
R3
R2
T2
D17
D18
D19
D20
D21
U2
T3
D22
D23
U3
C1
C3
E2
D3
D2
F3
D24
D25
D26
D27
D28
D29
D30
C2
E3
R19
C6
A3
B4
C5
B6
C7
A4
B5
R19
V10
W9
W10
Y9
V11
D31
DBREQ
DQM0
DQM1
DQM2
DQM3
DQS0
DQS1
DQS2
DQS3
EE0
EVNT0
EVNT1
EVNT2
EVNT3
EVNT4
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
3-5
Packaging
Table 3-1. MSC7116 Signals By Name (Continued)
Signal Name
Ball Designator
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
A1
A2
A15
D4
E1
F7
F8
F9
F12
F13
F14
G1
G3
G6
G7
G8
G9
G10
G11
G12
G13
G14
H6
H7
H8
H9
H10
H11
H12
H13
H14
J7
J8
J9
J10
J11
J12
J13
J14
MSC7116 Technical Data, Rev. 8
3-6
Freescale Semiconductor
MAP-BGA Package
Table 3-1. MSC7116 Signals By Name (Continued)
Signal Name
Ball Designator
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
J15
K2
K6
K7
K8
K9
K10
K11
K12
K13
K14
L2
L6
L7
L8
L9
L10
L11
L12
L13
M6
M7
M8
M9
M10
M11
M12
M13
M14
M15
N7
N8
N9
N10
N11
N12
N13
N14
P7
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
3-7
Packaging
Table 3-1. MSC7116 Signals By Name (Continued)
Signal Name
Ball Designator
GND
GND
P8
P9
GND
P10
P11
P12
P13
P14
R1
GND
GND
GND
GND
GND
GND
R7
GND
R9
GND
R11
R12
R14
U1
GND
GND
GND
GND
W1
GND
Y2
GND
Y19
V14
W14
Y14
W13
V13
Y13
Y12
W12
V12
Y11
W11
Y10
M19
M20
M18
N19
V11
W9
GPIA0
GPIA1
GPIA2
GPIA3
GPIA4
GPIA5
GPIA6
GPIA7
GPIA8
GPIA9
GPIA10
GPIA11
GPIA12
GPIA13
GPIA14
GPIA15
GPIA16
GPIA17
GPIA19
GPIA20
GPIA21
GPIA22
W17
Y17
Y18
V17
MSC7116 Technical Data, Rev. 8
3-8
Freescale Semiconductor
MAP-BGA Package
Table 3-1. MSC7116 Signals By Name (Continued)
Signal Name
Ball Designator
GPIA23
W18
V18
Y20
W19
W16
V15
Y15
L18
B11
C11
A9
GPIA24
GPIA25
GPIA26
GPIA27
GPIA28
GPIA29
GPIB11 (mask set 1M88B only)
GPIC0
GPIC1
GPIC2
GPIC3
B10
A8
GPIC4
GPIC5
C10
B9
GPIC6
GPIC7
A7
GPIC11 (mask set 1M88B only)
J18
W10
Y9
GPIC14
GPIC15
GPID4
W15
Y16
V16
B15
A16
V14
W14
Y14
W13
V13
Y13
Y12
W12
V12
Y11
W11
Y10
M19
M20
M18
GPID5
GPID6
GPID7 (mask set 1M88B only)
GPID8 (mask set 1M88B only)
GPOA0
GPOA1
GPOA2
GPOA3
GPOA4
GPOA5
GPOA6
GPOA7
GPOA8
GPOA9
GPOA10
GPOA11
GPOA12
GPOA13
GPOA14
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
3-9
Packaging
Table 3-1. MSC7116 Signals By Name (Continued)
Signal Name
Ball Designator
GPOA15
N19
W17
Y17
Y18
V17
W18
V18
Y20
W19
W16
V15
Y15
L18
B11
C11
A9
GPOA19
GPOA20
GPOA21
GPOA22
GPOA23
GPOA24
GPOA25
GPOA26
GPOA27
GPOA28
GPOA29
GPOB11 (mask set 1M88B only)
GPOC0
GPOC1
GPOC2
GPOC3
B10
A8
GPOC4
GPOC5
C10
B9
GPOC6
GPOC7
A7
GPOC11 (mask set 1M88B only)
J18
W10
Y9
GPOC14
GPOC15
GPOD4
W15
Y16
V16
B15
A16
W20
K18
H20
H19
J18
J19
L19
L18
A14
A13
GPOD5
GPOD6
GPOD7 (mask set 1M88B only)
GPOD8 (mask set 1M88B only)
H8BIT
HA0
HA1
HA2
HA3
HACK/HACK
HCS1/HCS1
HCS2/HCS2
HD0
HD1
MSC7116 Technical Data, Rev. 8
3-10
Freescale Semiconductor
MAP-BGA Package
Table 3-1. MSC7116 Signals By Name (Continued)
Signal Name
Ball Designator
HD10
HD11
A9
B10
A8
HD12
HD13
C10
B9
HD14
HD15
A7
HD2
B13
C12
A12
B12
A11
A10
B11
C11
K19
K20
J20
L20
J20
T20
J19
L20
J20
K20
Y13
V13
W14
V14
V11
W9
HD3
HD4
HD5
HD6
HD7
HD8
HD9
HDDS
HDS/HDS
HDSP
HRD/HRD
HREQ/HREQ
HRESET
HRRQ/HRRQ
HRW
HTRQ/HTRQ
HWR/HWR
IRQ0
IRQ1
IRQ10
IRQ11
IRQ12
IRQ13
IRQ14
IRQ15
IRQ16
IRQ17
IRQ18
IRQ19
IRQ2
N19
M18
Y15
V15
W16
W17
M20
Y17
Y18
IRQ20
IRQ21
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
3-11
Packaging
Table 3-1. MSC7116 Signals By Name (Continued)
Signal Name
Ball Designator
IRQ22
IRQ23
IRQ24
IRQ25
IRQ26
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
MDC
MDIO
NC
V17
W18
V18
Y20
W19
M19
Y10
W11
V12
W12
W13
Y14
W20
T18
A16
A17
A18
A19
A20
B2
NC
NC
NC
NC
NC
NC
B14
B15
B16
B17
B18
B19
B20
C13
C14
C15
C16
C17
C18
C19
C20
D18
D19
D20
E18
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
MSC7116 Technical Data, Rev. 8
3-12
Freescale Semiconductor
MAP-BGA Package
Table 3-1. MSC7116 Signals By Name (Continued)
Signal Name
Ball Designator
NC
NC
E19
E20
F18
F19
F20
G18
G19
G20
H18
V2
NC
NC
NC
NC
NC
NC
NC
NC
NC
V9
NC
W8
NMI
Y8
PORESET
RAS
P18
C8
REFCLK
RX_DV
RX_ER
RXCLK
RXD0
RXD1
RXD2
RXD3
SCL
W18
Y20
W19
Y16
V17
Y18
V16
W16
N19
M18
V11
Y10
Y11
W11
V12
Y12
W12
Y13
W13
V13
Y14
V14
W14
U19
SDA
SWTE
T0RCK
T0RD
T0RFS
T0TCK
T0TD
T0TFS
T1RCK
T1RD
T1RFS
T1TCK
T1TD
T1TFS
TCK
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
3-13
Packaging
Table 3-1. MSC7116 Signals By Name (Continued)
Signal Name
Ball Designator
TDI
V20
R18
R20
T19
P19
U20
V18
V15
W18
Y17
W17
W15
Y15
M20
M19
D17
E6
TDO
TEST0
TMS
TPSEL
TRST
TX_EN
TX_ER
TXCLK
TXD0
TXD1
TXD2
TXD3
URXD
UTXD
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
E7
E8
E9
E16
E17
F4
F5
F6
F16
F17
G17
H17
J17
K4
K17
L4
L17
M16
M17
N16
N17
P17
MSC7116 Technical Data, Rev. 8
3-14
Freescale Semiconductor
MAP-BGA Package
Table 3-1. MSC7116 Signals By Name (Continued)
Signal Name
Ball Designator
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
R17
T6
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
T9
T16
T17
U5
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
D11
D12
D13
D14
D15
D16
E11
E12
E13
E14
E15
F15
G15
G16
H15
H16
J16
K15
K16
L14
L15
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
3-15
Packaging
Table 3-1. MSC7116 Signals By Name (Continued)
Signal Name
Ball Designator
V
V
V
V
V
V
V
V
V
V
V
L16
N15
P15
P16
R13
R15
R16
T12
T13
T14
T15
B1
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
DDIO
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
D1
D5
D6
D7
D8
D9
D10
E4
E5
E10
F1
F10
F11
G4
G5
H4
H5
J2
J4
J5
J6
K5
L5
M2
M4
M5
N4
MSC7116 Technical Data, Rev. 8
3-16
Freescale Semiconductor
MAP-BGA Package
Table 3-1. MSC7116 Signals By Name (Continued)
Signal Name
Ball Designator
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
N5
N6
P4
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
DDM
P5
P6
R4
R5
R6
R8
R10
T1
T4
T5
T7
T8
T10
T11
U4
V1
W2
Y1
V
P20
N3
N20
B8
DDPLL
V
REF
V
SSPLL
WE
Notes: 1. This table lists every signal name. Because many signals are multiplexed, an
individual ball designator number may be listed several times.
2. Signals listed as NC must not be connected or used as signal junction locations in
board designs.
3. Many peripheral signals must be enabled before they can be used. Some signals
are reserved after reset if they are not enabled. “Reserved” signals are not included
in this list. Refer to Table 3-2 to determine which signals must be enabled after
reset.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
3-17
Packaging
Number
Table 3-2. MSC7116 Signals by Ball Designator
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
A1
GND
A2
GND
DQM1
DQS2
CK
A3
A4
A5
A6
CK
A7
GPIC7
GPIC4
GPIC2
GPOC7
GPOC4
GPOC2
HD15
HD12
HD10
HD7
A8
A9
A10
reserved
A11
reserved
reserved
reserved
reserved
HD6
A12
HD4
A13
HD1
A14
HD0
A15
GND
NC
A16 (1L44X)
A16 (1M88B)
BM3
GPID8
GPOD7
reserved
A17
NC
NC
NC
NC
A18
A19
A20
B1
V
DDM
B2
NC
CS0
B3
B4
DQM2
DQS3
DQS0
CKE
B5
B6
B7
B8
WE
B9
GPIC6
GPIC3
GPIC0
GPOC6
GPOC3
GPOC0
HD14
HD11
HD8
B10
B11
B12
reserved
reserved
HD5
B13
HD2
B14
NC
NC
B15 (1L44X)
B15 (1M88B)
B16
BM2
GPID7
GPOD7
reserved
NC
MSC7116 Technical Data, Rev. 8
3-18
Freescale Semiconductor
MAP-BGA Package
Table 3-2. MSC7116 Signals by Ball Designator (Continued)
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
B17
B18
B19
B20
C1
NC
NC
NC
NC
D24
D30
D25
CS1
C2
C3
C4
C5
DQM3
DQM0
DQS1
RAS
C6
C7
C8
C9
CAS
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
D1
GPIC5
GPIC1
GPOC5
GPOC1
HD13
HD9
HD3
reserved
NC
NC
NC
NC
NC
NC
NC
NC
V
DDM
D2
D28
D27
D3
D4
GND
D5
V
V
V
V
V
V
DDM
DDM
DDM
DDM
DDM
DDM
DDIO
DDIO
DDIO
DDIO
D6
D7
D8
D9
D10
D11
D12
D13
D14
V
V
V
V
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
3-19
Packaging
Number
Table 3-2. MSC7116 Signals by Ball Designator (Continued)
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
D15
D16
D17
D18
D19
D20
E1
V
V
DDIO
DDIO
V
DDC
NC
NC
NC
GND
D26
D31
E2
E3
E4
V
V
DDM
DDM
E5
E6
V
V
V
V
DDC
DDC
DDC
DDC
DDM
DDIO
DDIO
DDIO
DDIO
DDIO
E7
E8
E9
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
F1
V
V
V
V
V
V
V
V
DDC
DDC
NC
NC
NC
V
DDM
F2
D15
F3
D29
F4
V
DDC
DDC
DDC
F5
V
V
F6
F7
GND
GND
GND
F8
F9
F10
F11
F12
V
V
DDM
DDM
GND
MSC7116 Technical Data, Rev. 8
3-20
Freescale Semiconductor
MAP-BGA Package
Table 3-2. MSC7116 Signals by Ball Designator (Continued)
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
F13
F14
F15
F16
F17
F18
F19
F20
G1
GND
GND
V
DDIO
V
V
DDC
DDC
NC
NC
NC
GND
D13
GND
G2
G3
G4
V
V
DDM
DDM
G5
G6
GND
GND
GND
GND
GND
GND
GND
GND
GND
G7
G8
G9
G10
G11
G12
G13
G14
G15
G16
G17
G18
G19
G20
H1
V
DDIO
DDIO
V
V
DDC
NC
NC
NC
D14
D12
D11
H2
H3
H4
V
DDM
DDM
H5
V
H6
GND
GND
GND
GND
GND
H7
H8
H9
H10
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
3-21
Packaging
Number
Table 3-2. MSC7116 Signals by Ball Designator (Continued)
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
H11
H12
H13
H14
H15
H16
H17
H18
H19
H20
J1
GND
GND
GND
GND
V
V
DDIO
DDIO
V
DDC
NC
reserved
HA2
HA1
reserved
D10
J2
V
DDM
J3
D9
J4
V
DDM
DDM
DDM
J5
V
V
J6
J7
GND
GND
GND
GND
GND
GND
GND
GND
GND
J8
J9
J10
J11
J12
J13
J14
J15
J16
J17
J18 (1L44X)
J18 (1M88B)
J19
J20
K1
V
DDIO
V
DDC
reserved
reserved
HA3
HA3
GPIC11
GPOC11
HACK/HACK or HRRQ/HRRQ
HREQ/HREQ or HTRQ/HTRQ
HDSP
reserved
D0
GND
D8
K2
K3
K4
V
DDC
DDM
K5
V
K6
GND
GND
K7
MSC7116 Technical Data, Rev. 8
3-22
Freescale Semiconductor
MAP-BGA Package
Table 3-2. MSC7116 Signals by Ball Designator (Continued)
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
K8
K9
GND
GND
GND
GND
GND
GND
GND
K10
K11
K12
K13
K14
K15
K16
K17
K18
K19
K20
L1
V
V
DDIO
DDIO
V
DDC
reserved
HA0
reserved
reserved
HDDS
HDS/HDS or HWR/HWR
D1
GND
D3
L2
L3
L4
V
DDC
DDM
L5
V
L6
GND
GND
GND
GND
GND
GND
GND
GND
L7
L8
L9
L10
L11
L12
L13
L14
L15
L16
L17
L18 (1L44X)
L18 (1M88B)
L19
L20
M1
V
DDIO
DDIO
DDIO
V
V
V
DDC
reserved
HCS2/HCS2
HCS2/HCS2
GPIB11
GPOB11
reserved
reserved
HCS1/HCS1
HRW or HRD/HRD
D2
M2
V
DDM
M3
D5
M4
V
DDM
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
3-23
Packaging
Number
Table 3-2. MSC7116 Signals by Ball Designator (Continued)
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
M5
M6
V
DDM
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
M7
M8
M9
M10
M11
M12
M13
M14
M15
M16
M17
M18
M19
M20
N1
V
V
DDC
DDC
GPIA14
IRQ15
IRQ3
IRQ2
GPOA14
GPOA12
GPOA13
SDA
UTXD
URXD
GPIA12
GPIA13
D4
D6
N2
N3
V
REF
DDM
DDM
DDM
N4
V
V
V
N5
N6
N7
GND
GND
GND
GND
GND
GND
GND
GND
N8
N9
N10
N11
N12
N13
N14
N15
N16
N17
N18
N19
N20
P1
V
DDIO
V
DDC
V
DDC
CLKIN
GPIA15
IRQ14
GPOA15
SCL
V
SSPLL
D7
P2
D17
MSC7116 Technical Data, Rev. 8
3-24
Freescale Semiconductor
MAP-BGA Package
Table 3-2. MSC7116 Signals by Ball Designator (Continued)
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
P3
P4
D16
V
V
V
DDM
P5
DDM
DDM
P6
P7
GND
GND
GND
GND
GND
GND
GND
GND
P8
P9
P10
P11
P12
P13
P14
P15
P16
P17
P18
P19
P20
R1
V
DDIO
DDIO
V
V
DDC
PORESET
TPSEL
V
DDPLL
GND
D19
D18
R2
R3
R4
V
V
V
DDM
DDM
DDM
R5
R6
R7
GND
R8
V
DDM
R9
GND
R10
R11
R12
R13
R14
R15
R16
R17
R18
R19
R20
V
DDM
GND
GND
V
DDIO
GND
V
DDIO
DDIO
V
V
DDC
TDO
reserved
EE0/DBREQ
TEST0
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
3-25
Packaging
Number
Table 3-2. MSC7116 Signals by Ball Designator (Continued)
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
T1
T2
V
DDM
D20
D22
T3
T4
V
DDM
DDM
T5
V
T6
V
DDC
DDM
DDM
T7
V
V
T8
T9
V
DDC
DDM
DDM
DDIO
DDIO
DDIO
DDIO
T10
T11
T12
T13
T14
T15
T16
T17
T18
T19
T20
U1
V
V
V
V
V
V
V
DDC
DDC
V
reserved
MDIO
TMS
HRESET
GND
U2
D21
U3
D23
U4
V
DDM
U5
V
V
V
V
V
V
V
V
V
V
V
V
V
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
DDC
U6
U7
U8
U9
U10
U11
U12
U13
U14
U15
U16
U17
U18
reserved
COL
MSC7116 Technical Data, Rev. 8
3-26
Freescale Semiconductor
MAP-BGA Package
Table 3-2. MSC7116 Signals by Ball Designator (Continued)
Signal Names
Software Controlled
Hardware Controlled
Number
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
Primary
Alternate
U19
U20
V1
TCK
TRST
V
DDM
V2
NC
A13
A11
A10
A5
V3
V4
V5
V6
V7
A2
V8
BA0
NC
V9
V10
V11
V12
V13
V14
V15
V16
V17
V18
V19
V20
W1
W2
W3
W4
W5
W6
W7
W8
W9
W10
W11
W12
W13
W14
W15
W16
reserved
EVNT0
EVNT4
T0TCK
T1RFS
T1TD
SWTE
GPIA16
GPID6
IRQ12
IRQ6
GPOA16
GPOA8
GPOA4
GPOA0
GPOA28
GPOD6
GPOA22
GPOA24
GPIA8
GPIA4
GPIA0
GPIA28
IRQ1
IRQ11
IRQ17
TX_ER
RXD2
reserved
reserved
RXD0
GPIA22
GPIA24
IRQ22
IRQ24
TX_EN
CRS
reserved
TDI
GND
V
DDM
A12
A8
A7
A6
A3
NC
GPIA17
IRQ13
GPOA17
GPOC14
GPOA10
GPOA7
GPOA3
GPOA1
GPOD4
GPOA27
EVNT1
CLKO
EVNT2
BM0
GPIC14
GPIA10
GPIA7
GPIA3
GPIA1
IRQ5
IRQ7
IRQ8
IRQ10
T0RFS
T0TFS
T1RD
T1TFS
GPID4
TXD2
RXD3
reserved
reserved
GPIA27
IRQ18
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
3-27
Packaging
Number
Table 3-2. MSC7116 Signals by Ball Designator (Continued)
Signal Names
Software Controlled
Hardware Controlled
Primary Alternate
End of Reset
GPI Enabled
(Default)
Interrupt
Enabled
GPO Enabled
W17
W18
W19
W20
Y1
GPIA19
IRQ19
IRQ23
GPOA19
GPOA23
GPOA26
TXD1
GPIA23
GPIA26
TXCLK or REFCLK
RX_ER
IRQ26
H8BIT
reserved
MDC
V
DDM
Y2
GND
A9
Y3
Y4
A1
Y5
A0
Y6
A4
Y7
BA1
Y8
reserved
GPIA11
NMI
reserved
Y9
BM1
GPIC15
GPOC15
GPOA11
GPOA9
GPOA6
GPOA5
GPOA2
GPOA29
GPOD5
GPOA20
GPOA21
EVNT3
T0RCK
T0RD
Y10
Y11
Y12
Y13
Y14
Y15
Y16
Y17
Y18
Y19
Y20
IRQ4
GPIA9
GPIA6
T0TD
GPIA5
GPIA2
GPIA29
IRQ0
IRQ9
T1RCK
T1TCK
IRQ16
TXD3
reserved
reserved
GPID5
RXCLK
GPIA20
GPIA21
IRQ20
IRQ21
TXD0
RXD1
GND
GPIA25
IRQ25
GPOA25
RX_DV or CRS_DV
MSC7116 Technical Data, Rev. 8
3-28
Freescale Semiconductor
MAP-BGA Package Mechanical Drawing
3.2 MAP-BGA Package Mechanical Drawing
Notes:
1. All dimensions in millimeters.
2. Dimensioning and tolerancing
per ASME Y14.5M–1994.
3. Maximum solder ball diameter
measured parallel to Datum A.
4. Datum A, the seating plane, is
determined by the spherical
crowns of the solder balls.
5. Parallelism measurement shall
exclude any effect of mark on
top surface of package.
CASE 1568-01
Figure 3-3. MSC7116 Mechanical Information, 400-pin MAP-BGA Package
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
3-29
Packaging
MSC7116 Technical Data, Rev. 8
3-30
Freescale Semiconductor
Design Considerations
4
This section described various areas to consider when incorporating the MSC7116 device into a system design.
4.1 Thermal Design Considerations
An estimation of the chip-junction temperature, T , in °C can be obtained from the following:
J
TJ = TA + (R JA × PD)
Equation 1
θ
where
T = ambient temperature near the package (°C)
A
R
= junction-to-ambient thermal resistance (°C/W)
JA
θ
P = P
+ P = power dissipation in the package (W)
I/O
D
INT
P
P
= I × V = internal power dissipation (W)
DD DD
INT
I/O
= power dissipated from device on output pins (W)
The power dissipation values for the MSC7116 are listed in Table 2-3. The ambient temperature for the device is
the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal
resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are
two values in common usage: the value determined on a single layer board and the value obtained on a board with
two planes. The value that more closely approximates a specific application depends on the power dissipated by
other components on the printed circuit board (PCB). The value obtained using a single layer board is appropriate
for tightly packed PCB configurations. The value obtained using a board with internal planes is more appropriate
2
for boards with low power dissipation (less than 0.02 W/cm with natural convection) and well separated
components. Based on an estimation of junction temperature using this technique, determine whether a more
detailed thermal analysis is required. Standard thermal management techniques can be used to maintain the device
thermal junction temperature below its maximum. If T appears to be too high, either lower the ambient
J
temperature or the power dissipation of the chip.
You can verify the junction temperature by measuring the case temperature using a small diameter thermocouple
(40 gauge is recommended) or an infrared temperature sensor on a spot on the device case. Use the following
equation to determine T :
J
TJ = TT + (Ψ × PD)
Equation 2
JT
where
T = thermocouple (or infrared) temperature on top of the package (°C)
T
Ψ = thermal characterization parameter (° C/W)
JT
P = power dissipation in the package (W)
D
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
4-1
Design Considerations
4.2 Power Supply Design Considerations
This section outlines the MSC7116 power considerations: power supply, power sequencing, power planes,
decoupling, power supply filtering, and power consumption. It also presents a recommended power supply design
and options for low-power consumption. For information on AC/DC electrical specifications and thermal
characteristics, refer to Chapter 2.
• Power Supply. The MSC7116 requires four input voltages, as shown in Table 4-1.
Table 4-1. MSC7116 Voltages
Voltage
Symbol
Value
Core
V
1.2 V
2.5 V
1.25 V
3.3 V
DDC
DDM
Memory
Reference
I/O
V
V
REF
V
DDIO
You should supply the MSC7116 core voltage via a variable switching supply or regulator to allow for
compatibility with possible core voltage changes on future silicon revisions. The core voltage is supplied with
1.2 V (+5% and –10%) across V
and GND and the I/O section is supplied with 3.3 V ( 10%) across V
DDC
DDIO
and GND. The memory and reference voltages supply the DDR memory controller block. The memory voltage is
supplied with 2.5 V across V and GND. The reference voltage is supplied across V and GND and must be
DDM
REF
between 0.49 × V
and 0.51 × V
. Refer to the JEDEC standard JESD8 (Stub Series Terminated Logic for
2.5 Volts (STTL_2)) for memory voltage supply requirements.
DDM
DDM
• Power sequencing. One consequence of multiple power supplies is that the voltage rails ramp up at different
rates when power is initially applied. The rates depend on the power supply, the type of load on each power
supply, and the way different voltages are derived. It is extremely important to observe the power up and power
down sequences at the board level to avoid latch-up, forward biasing of ESD devices, and excessive currents,
which all lead to severe device damage. The correct power-up sequence is as follows:
—
—
—
Turn on the highest supply first (3.3 V).
Turn on the 2.5 V supply.
Turn on the lowest supply last (1.2 V).
The correct power-down sequence is as follows:
—
—
—
Turn off the lowest supply first (1.2 V).
Turn off the 2.5 V supply.
Turn off the highest supply last (3.3 V).
At any instant during power-up and power-down, the 2.5 V supply must maintain a differential of +0.7 V or more
below the 3.3 V supply. Also, at any instant, the 1.2 V supply must maintain a differential of +0.7 V or more
below the 2.5 V supply, as shown in Figure 4-1. The power-down sequence is not as critical as the power-up
sequence.
MSC7116 Technical Data, Rev. 8
4-2
Freescale Semiconductor
Power Supply Design Considerations
VDDIO = 3.3 V
Ramp-up
Ramp-down
VDDM = 2.5 V
0.7 V or More
0.7 V or More
VDDC = 1.2 V
Differential should always be
0.7 V or more.
Time
Figure 4-1. Voltage Sequencing
• Power planes. Each power supply pin (VDDC, VDDM, and VDDIO) should have a low-impedance path to the board
power supply. Each GND pin should be provided with a low-impedance path to ground. The power supply pins
drive distinct groups of logic on the device. The MSC7116 VDDC power supply pins should be bypassed to ground
using decoupling capacitors. The capacitor leads and associated printed circuit traces connecting to device power
pins and GND should be kept to less than half an inch per capacitor lead. A minimum four-layer board that
employs two inner layers as power and GND planes is recommended. See Section 4.5 for DDR Controller power
guidelines.
• Decoupling. Both the I/O voltage and core voltage should be decoupled for switching noise. For I/O decoupling,
use standard capacitor values of 0.01 µF for every two to three voltage pins. For core voltage decoupling, use
two levels of decoupling. The first level should consist of a 0.01 µF high frequency capacitor with low effective
series resistance (ESR) and effective series inductance (ESL) for every two to three voltage pins. The second
decoupling level should consist of two bulk/tantalum decoupling capacitors, one 10 µF and one 47 µF, (with low
ESR and ESL) mounted as closely as possible to the MSC7116 voltage pins. Additionally, the maximum drop
between the power supply and the DSP device should be 15 mV at 1 A.
• PLL power supply filtering. The MSC7116 VDDPLL power signal provides power to the clock generation PLL. To
ensure stability of the internal clock, the power supplied to this pin should be filtered with capacitors that have
low and high frequency filtering characteristics. VDDPLL can be connected to V
through a 20 Ωresistor.
DDC
V
can be tied directly to the GND plane. A circuit similar to the one shown in Figure 4-2 is recommended.
SSPLL
The PLL loop filter should be placed as closely as possible to the VDDPLL pin (which are located on the outside
edge of the silicon package) to minimize noise coupled from nearby circuits.The 0.01 µF capacitor should be
closest to VDDPLL, followed by the 0.1 µF capacitor, the 10 µF capacitor, and finally the 20-Ωresistor to VDDC
These traces should be kept short. VCCSYN and VCCSYN1 should be bypassed to ground by 0.1 µF and 47 µF
capacitors located as closely as possible to the device package.
.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
4-3
Design Considerations
20 Ω
VDDC
V
DDPLL
0.1 µF 0.01 µF
10 µF
10 Ω
V
V
CCSYN
VDDC
CCSYN1
47 µF
0.1 µF
Figure 4-2. PLL Power Supply Filter Circuits
• Power consumption. You can reduce power consumption in your design by controlling the power consumption
of the following regions of the device:
—
—
—
—
Extended core. Use the SC1400 Stop and Wait modes by issuing a stop or wait instruction.
Clock synthesis module. Disable the PLL, timer, watchdog, or DDR clocks or disable the CLKO pin.
AHB subsystem. Freeze or shut down the AHB subsystem using the GPSCTL[XBR_HRQ] bit.
Peripheral subsystem. Halt the individual on-device peripherals such as the DDR memory controller,
2
Ethernet MAC, HDI16, TDM, UART, I C, and timer modules.
For details, see the “Clocks and Power Management” chapter of the MSC711x Reference Manual.
• Power supply design. One of the most common ways to derive power is to use either a simple fixed or adjustable
linear regulator. For the system I/O voltage supply, a simple fixed 3.3 V supply can be used. However, a separate
adjustable linear regulator supply for the core voltage VDDC should be implemented. For the memory power
supply, regulators are available that take care of all DDR power requirements. Table 4-2 lists the recommended
current rating for each supply per device supported.
Table 4-2. Recommended Power Supply Ratings
Supply
Symbol
Nominal Voltage
Current Rating
Core
V
V
1.2 V
2.5 V
1.25 V
3.3 V
1.5 A per device
0.5 A per device
10 µA per device
1.0 A per device
DDC
DDM
Memory
Reference
I/O
V
REF
V
DDIO
4.3 Estimated Power Usage Calculations
The following equations permit estimated power usage to be calculated for individual design conditions. Overall
power is derived by totaling the power used by each of the major subsystems:
PTOTAL = PCORE + PPERIPHERALS + PDDRIO + PIO + PLEAKAGE
This equation combines dynamic and static power. Dynamic power is determined using the generic equation:
C × V2 × F × 10–3 mW
Equation 4
Equation 3
where,
C = load capacitance in pF
V = peak-to-peak voltage swing in V
F = frequency in MHz
MSC7116 Technical Data, Rev. 8
4-4
Freescale Semiconductor
Estimated Power Usage Calculations
4.3.1 Core Power
Estimation of core power is straightforward. It uses the generic dynamic power equation and assumes that the core
load capacitance is 750 pF, core voltage swing is 1.2 V, and the core frequency is 200 MHz or 266 MHz. This
yields:
PCORE = 750 pF × (1.2 V)2 × 200 MHz × 10–3 = 216 mW
PCORE = 750 pF × (1.2 V)2 × 266 MHz × 10–3 = 287 mW
Equation 5
Equation 6
This equation allows for adjustments to voltage and frequency if necessary.
4.3.2 Peripheral Power
Peripherals include the DDR memory controller, DMA controller, HDI16, TDM, UART, timers, GPIOs, and the
2
I C module. Basic power consumption by each module is assumed to be the same and is computed by using the
following equation which assumes an effective load of 20 pF, core voltage swing of 1.2 V, and a switching
frequency of 100 MH or 133 MHz. This yields:
PPERIPHERAL = 20 pF × (1.2 V)2 × 100 MHz × 10–3 = 2.88 mW per peripheral
PPERIPHERAL = 20 pF × (1.2 V)2 × 133 MHz × 10–3 = 3.83 mW per peripheral
Equation 7
Equation 8
Multiply this value by the number of peripherals used in the application to compute the total peripheral power
consumption.
4.3.3 External Memory Power
Estimation of power consumption by the DDR memory system is complex. It varies based on overall system signal
line usage, termination and load levels, and switching rates. Because the DDR memory includes terminations
external to the MSC7116 device, the 2.5 V power source provides the power for the termination, which is a static
value of 16 mA per signal driven high. The dynamic power is computed, however, using a differential voltage
swing of 0.200 V, yielding a peak-to-peak swing of 0.4 V. The equations for computing the DDR power are:
PDDRIO = PSTATIC + PDYNAMIC
Equation 9
Equation 10
Equation 11
Equation 12
PSTATIC = (unused pins × % driven high) × 16 mA × 2.5 V
P
P
DYNAMIC = (pin activity value) × 20 pF × (0.4 V)2 × 200 MHz × 10–3 mW
DYNAMIC = (pin activity value) × 20 pF × (0.4 V)2 × 266 MHz × 10–3 mW
pin activity value = (active data lines × % activity × % data switching) + (active address lines × % activity) Equation 13
As an example, assume the following:
unused pins = 16 (DDR uses 16-pin mode)
% driven high = 50%
active data lines = 16
% activity = 60%
% data switching = 50%
active address lines = 3
In this example, the DDR memory power consumption is:
PDDRIO = ((16 × 0.5) × 16 × 2.5) + (((16 × 0.6 × 0.5) + (3 × 0.6)) × 20 × (0.4)2 × 200 × 10–3) = 324.2 mW Equation 14
PDDRIO = ((16 × 0.5) × 16 × 2.5) + (((16 × 0.6 × 0.5) + (3 × 0.6)) × 20 × (0.4)2 × 266 × 10–3) = 326.3 mW Equation 15
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
4-5
Design Considerations
4.3.4 External I/O Power
The estimation of the I/O power is similar to the computation of the peripheral power estimates. The power
consumption per signal line is computed assuming a maximum load of 20 pF, a voltage swing of 3.3 V, and a
switching frequency of 25 MHz or 33 MHz, which yields:
PIO = 20 pF × (3.3 V)2 × 25 MHz × 10–3 = 5.44 mW per I/O line
PIO = 20 pF × (3.3 V)2 × 33 MHz × 10–3 = 7.19 mW per I/O line
Equation 16
Equation 17
Multiply this number by the number of I/O signal lines used in the application design to compute the total I/O
power.
Note: The signal loading depends on the board routing. For systems using a single DDR device, the load could be
as low as 7 pF.
4.3.5 Leakage Power
The leakage power is for all power supplies combined at a specific temperature. The value is temperature
dependent. The observed leakage value at room temperature is 64 mW.
4.3.6 Example Total Power Consumption
Using the examples in this section and assuming four peripherals and 10 I/O lines active, a total power
consumption value is estimated as the following:
PTOTAL (200 MHz core) = 216 + (4 × 2.88) + 324,2 + (10 × 5.44) + 64 = 670.12 mW
PTOTAL (266 MHz core) = 287 + (4 × 3.83) + 326.3 + (10 × 7.19) + 64 = 764.52 mW
Equation 18
Equation 19
4.4 Reset and Boot
This section describes the recommendations for configuring the MSC7116 at reset and boot.
4.4.1 Reset Circuit
HRESET is a bidirectional signal and, if driven as an input, should be driven with an open collector or open-drain
device. For an open-drain output such as HRESET, take care when driving many buffers that implement input bus-
hold circuitry. The bus-hold currents can cause enough voltage drop across the pull-up resistor to change the logic
level to low. Either a smaller value of pull-up or less current loading from the bus-hold drivers overcomes this issue.
To avoid exceeding the MSC7116 output current, the pull-up value should not be too small (a 1 KΩpull-up resistor
is used in the MSC711xADS reference design).
4.4.2 Reset Configuration Pins
Table 4-3 shows the MSC7116 reset configuration signals. These signals are sampled at the deassertion (rising
edge) of PORESET. For details, refer to the Reset chapter of the MSC711x Reference Manual.
Table 4-3. Reset Configuration Signals
Signal
Description
Settings
BM[1–0]
Determines boot mode.
0
Boot from HDI16 port.
01
1x
Boot from I2C.
Reserved.
MSC7116 Technical Data, Rev. 8
4-6
Freescale Semiconductor
Reset and Boot
Table 4-3. Reset Configuration Signals (Continued)
Signal
Description
Settings
SWTE
Determines watchdog functionality.
0
1
0
1
0
1
Watchdog timer disabled.
Watchdog timer enabled.
Host Data strobes active low.
Host Data strobes active high.
HDSP
H8BIT
Configures HDI16 strobe polarity.
Configures HDI16 operation mode.
HDI16 port configured for 16-bit operation.
HDI16 port configured for 8-bit operation.
4.4.3 Boot
After a power-on reset, the PLL is bypassed and the device is directly clocked from the CLKIN pin. Thus, the device
operates slowly during the boot process. After the boot program is loaded, it can enable the PLL and start the
device operating at a higher speed. The MSC7116 can boot from an external host through the HDI16 or download
2
a user program through the I C port. The boot operating mode is set by configuring the BM[0–1] signals sampled at
the rising edge of PORESET, as shown in Table 4-4.
Table 4-4. Boot Mode Settings
BM0
BM1
Boot Source
0
0
1
0
1
x
External host via HDI16.
2
I C.
Reserved.
4.4.3.1 HDI16 Boot
If the MSC7116 device boots from an external host through the HDI16, the port is configured as follows:
• Operate in Non-DMA mode.
• Operate in polled mode on the device side.
• Operate in polled mode on the external host side.
• External host must write four 16-bit values at a time with the first word as the most significant and the fourth
word as the least significant.
When booting from a power-on reset, the HDI16 is additionally configurable as follows:
• 8- or 16-bit mode as specified by the H8BIT pin.
• Data strobe as specified by the HDSP and HDDS pins.
These pins are sampled only on the deassertion of power-on reset. During a boot from a hard reset, the
configuration of these pins is unaffected.
Note: When the HDI16 is used for booting or other purposes, bit 0 is the least significant bit and not the most
significant bit as for other DSP products.
2
4.4.3.2 I C Boot
2
When the MSC7116 device is configured to boot from the I C port, the boot program configures the GPIO pins
2
2
2
shared with the I C pins as I C pins. The I C interface is configured as follows:
2
• I C in master mode.
• EPROM in slave mode.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
4-7
Design Considerations
For details on the boot procedure, see the “Boot Program” chapter of the MSC711x Reference Manual.
4.5 DDR Memory System Guidelines
MSC7116 devices contain a memory controller that provides a glueless interface to external double data rate
(DDR) SDRAM memory modules with Class 2 Series Stub Termination Logic 2.5 V (SSTL_2). There are two
termination techniques, as shown in Figure 4-3. Technique B is the most popular termination technique.
VTT
Generator
VTT
Controller
RS
RS
DDR
Bank
DDR
Bank
RT
SSTL_2
SSTL_2
Address
Command
Chip Selects
Technique A
RT
Data
Strobes
Mask
SSTL_2
VREF
VTT
Generator
Controller
RS
DDR
Bank
DDR
Bank
RT
SSTL_2
SSTL_2
Address
Command
Technique B
Chip Selects
RS
RT
Data
Strobes
Mask
SSTL_2
Figure 4-3. SSTL Termination Techniques
MSC7116 Technical Data, Rev. 8
4-8
Freescale Semiconductor
DDR Memory System Guidelines
Figure 4-4 illustrates the power wattage for the resistors. Typical values for the resistors are as follows:
• RS = 22 Ω
• RT = 24 Ω
VTT
Driver
VDDQ
RT
Receiver
RS
VREF
VSS
Figure 4-4. SSTL Power Value
4.5.1 VREF and VTT Design Constraints
V
and V
are isolated power supplies at the same voltage, with V as a high current power source. This
TT
REF TT
section outlines the voltage supply design needs and goals:
• Minimize the noise on both rails.
• V must track variation in the V
DC offsets. Although they are isolated supplies, one possible solution is to
REF
TT
use a single IC to generate both signals.
• Both references should have minimal drift over temperature and source supply.
• It is important to minimize the noise from coupling onto V as follows:
REF
—
—
—
—
—
Isolate V
and shield it with a ground trace.
REF
Use 15–20 mm track.
Use 20–30 mm clearance between other traces for isolating.
Use the outer layer route when possible.
Use distributed decoupling to localize transient currents and return path and decouple with an inductance
less than 3 nH.
• Max source/sink transient currents of up to 1.8 A for a 32-bit data bus.
• Use a wide island trace on the outer layer:
—
—
—
—
Place the island at the end of the bus.
Decouple both ends of the bus.
Use distributed decoupling across the island.
Place SSTL termination resistors inside the V island and ensure a good, solid connection.
TT
• Place the V regulator as closely as possible to the termination island.
TT
—
—
Reduce inductance and return path.
Tie current sense pin at the midpoint of the island.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
4-9
Design Considerations
4.5.2 Decoupling
The DDR decoupling considerations are as follows:
• DDR memory requires significantly more burst current than previous SDRAMs.
• In the worst case, up to 64 drivers may be switching states.
• Pay special attention and decouple discrete ICs per manufacturer guidelines.
• Leverage V island topology to minimize the number of capacitors required to supply the burst current needs of
TT
the termination rail.
• See the Micron DesignLine publication entitled Decoupling Capacitor Calculation for a DDR Memory Channel
(http://download.micron.com/pdf/pubs/designline/3Q00dl1-4.pdf).
4.5.3 General Routing
The general routing considerations for the DDR are as follows:
• All DDR signals must be routed next to a solid reference:
—
—
For data, next to solid ground planes.
For address/command, power planes if necessary.
• All DDR signals must be impedance controlled. This is system dependent, but typical values are 50–60 ohm.
• Minimize other cross-talk opportunities. As possible, maintain at least a four times the trace width spacing
between all DDR signals to non-DDR signals.
• Keep the number of vias to a minimum to eliminate additional stubs and capacitance.
• Signal group routing priorities are as follows:
—
—
—
—
DDR clocks.
Route MVTT/MVREF.
Data group.
Command/address.
• Minimize data bit jitter by trace matching.
4.5.4 Routing Clock Distribution
The DDR clock distribution considerations are as follows:
• DDR controller supports six clock pairs:
—
—
2 DIMM modules.
Up to 36 discrete chips.
• For route traces as for any other differential signals:
—
—
Maintain proper difference pair spacing.
Match pair traces within 25 mm.
• Match all clock traces to within 100 mm.
• Keep all clocks equally loaded in the system.
• Route clocks on inner critical layers.
MSC7116 Technical Data, Rev. 8
4-10
Freescale Semiconductor
Connectivity Guidelines
4.5.5 Data Routing
The DDR data routing considerations are as follows:
• Route each data group (8-bits data + DQS + DM) on the same layer. Avoid switching layers within a byte group.
• Take care to match trace lengths, which is extremely important.
• To make trace matching easier, let adjacent groups be routed on alternate critical layers.
• Pin swap bits within a byte group to facilitate routing (discrete case).
• Tight trace matching is recommended within the DDR data group. Keep each 8-bit datum and its DM signal
within 25 mm of its respective strobe.
• Minimize lengths across the entire DDR channel:
—
—
Between all groups maintain a delta of no more than 500 mm.
Allows greater flexibility in the design for readjustments as needed.
• DDR data group separation:
—
—
—
If stack-up allows, keep DDR data groups away from the address and control nets.
Route address and control on separate critical layers.
If resistor networks (RNs) are used, attempt to keep data and command lines in separate packages.
4.6 Connectivity Guidelines
This section summarizes the connections and special conditions, such as pull-up or pull-down resistors, for the
MSC7116 device. Following are guidelines for signal groups and configuration settings:
• Clock and reset signals.
—
SWTE is used to configure the MSC7116 device and is sampled on the deassertion of PORESET, so it
should be tied to VDDC or GND either directly or through pull-up or pull-down resistors until PORESET is
deasserted. After PORESET, this signal can be left floating.
—
—
BM[0–1] configure the MSC7116 device and are sampled until PORESET is deasserted, so they should be
tied to VDDIO or GND either directly or through pull-up or pull-down resistors.
HRESET should be pulled up.
• Interrupt signals. When used, IRQ pins must be pulled up.
• HDI16 signals.
—
—
When they are configured for open-drain, the HREQ/HREQ or HTRQ/HTRQ signals require a pull-up resistor.
However, these pins are also sampled at power-on reset to determine the HDI16 boot mode and may need
to be pulled down. When these pins must be pulled down on reset and pulled up otherwise, a buffer can be
used with the HRESET signal as the enable.
When the device boots through the HDI16, the HDDS, HDSP and H8BIT pins should be pulled up or down,
depending on the required boot mode settings.
• Ethernet MAC/TDM2 signals. The MDIO signal requires an external pull-up resistor.
2
2
• I C signals. The SCL and SDA signals, when programmed for I C, requires an external pull-up resistor.
• General-purpose I/O (GPIO) signals. An unused GPIO pin can be disconnected. After boot, program it as an
output pin.
MSC7116 Technical Data, Rev. 8
Freescale Semiconductor
4-11
Design Considerations
• Other signals.
—
—
The TEST0 pin must be connected to ground.
The TPSEL pin should be pulled up to enable debug access via the EOnCE port and pulled down for
boundary scan.
—
—
Pins labelled NO CONNECT (NC) must not be connected.
When a 16-pin double data rate (DDR) interface is used, the 16 unused data pins should be no connects
(floating) if the used lines are terminated.
—
Do not connect DBREQ to DONE (as you would for the MSC8101 device). Connect DONE to one of the
EVNT pins, and DBREQ to HRRQ.
MSC7116 Technical Data, Rev. 8
4-12
Freescale Semiconductor
Ordering Information
Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.
Core
Frequency
(MHz)
Supply
Voltage
Pin
Count
Part
Package Type
Solder Spheres
Order Number
MSC7116
(mask
1L44X
1.2 V core
2.5 V mem.
3.3 V I/O
Molded Array Process-Ball Grid
Array (MAP-BGA)
400
400
200
Lead-free
Lead-bearing
Lead-free
MSC7116VM800
MSC7116VF800
MSC7116VM1000
MSC7116VF1000
MSC7116
(mask
1M88B)
1.2 V core
2.5 V mem
3.3 V I/O
Molded Array Process-Ball Grid
Array (MAP-BGA)
266
Lead-bearing
Information in this document is provided solely to enable system and software implementers to
use Freescale Semiconductor products. There are no express or implied copyright licenses
granted hereunder to design or fabricate any integrated circuits or integrated circuits based on
the information in this document.
How to Reach Us:
Home Page:
www.freescale.com
E-mail:
support@freescale.com
Freescale Semiconductor reserves the right to make changes without further notice to any
products herein. Freescale Semiconductor makes no warranty, representation or guarantee
regarding the suitability of its products for any particular purpose, nor does Freescale
Semiconductor assume any liability arising out of the application or use of any product or
circuit, and specifically disclaims any and all liability, including without limitation consequential
or incidental damages. “Typical” parameters which may be provided in Freescale
Semiconductor data sheets and/or specifications can and do vary in different applications and
actual performance may vary over time. All operating parameters, including “Typicals” must be
validated for each customer application by customer’s technical experts. Freescale
Semiconductor does not convey any license under its patent rights nor the rights of others.
Freescale Semiconductor products are not designed, intended, or authorized for use as
components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the
Freescale Semiconductor product could create a situation where personal injury or death may
occur. Should Buyer purchase or use Freescale Semiconductor products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Freescale
Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless
against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of,
directly or indirectly, any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent
regarding the design or manufacture of the part.
USA/Europe or Locations not listed:
Freescale Semiconductor
Technical Information Center, CH370
1300 N. Alma School Road
Chandler, Arizona 85224
+1-800-521-6274 or +1-480-768-2130
support@freescale.com
Europe, Middle East, and Africa:
Freescale Halbleiter Deutschland GMBH
Technical Information Center
Schatzbogen 7
81829 München, Germany
+44 1296 380 456 (English)
+46 8 52200080 (English)
+49 89 92103 559 (German)
+33 1 69 35 48 48 (French)
support@freescale.com
Japan:
Freescale Semiconductor Japan Ltd.
Headquarters
ARCO Tower 15F
1-8-1, Shimo-Meguro, Meguro-ku,
Tokyo 153-0064, Japan
0120 191014 or +81 3 5437 9125
support.japan@freescale.com
Freescale™, the Freescale logo, CodeWarrior, and fieldBIST are trademarks of Freescale
Semiconductor, Inc. StarCore is a trademark of StarCore LLC. The StarCore SC1400 core is
based on StarCore technology under license from StarCore LLC. All other product or service
names are the property of their respective owners.
Asia/Pacific:
Freescale Semiconductor Hong Kong Ltd.
Technical Information Center
2 Dai King Street
Tai Po Industrial Estate
Tai Po, N.T. Hong Kong
+800 2666 8080
© Freescale Semiconductor, Inc. 2004, 2005.
support.asia@freescale.com
For Literature Requests Only:
Freescale Semiconductor Literature Distribution Center
P.O. Box 5405
Denver, Colorado 80217
1-800-441-2447 or 303-675-2140
Fax: 303-675-2150
LDCForFreescaleSemiconductor@hibbertgroup.com
Document Order No.: MSC7116
Rev. 8
12/2005
相关型号：
MSC7128-01GS-BK
Dot Matrix LCD Driver, 16 X 36 Dots, CMOS, PQFP64, 14 X 20 MM, 1 MM PITCH, PLASTIC, QFP-64
OKI
©2020 ICPDF网 联系我们和版权申明